diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.cproject b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.cproject new file mode 100644 index 0000000000..536166225f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.cproject @@ -0,0 +1,315 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.project b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.project new file mode 100644 index 0000000000..9982af7b53 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.project @@ -0,0 +1,32 @@ + + + ble_baremetal_ek_ra4w1 + + + + + + com.renesas.cdt.ra.contentgen.raBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + com.renesas.cdt.ra.contentgen.raNature + + diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/CoverageSetting.xml b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/CoverageSetting.xml similarity index 100% rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/CoverageSetting.xml rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/CoverageSetting.xml diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/DebugVirtualConsoleSetting.xml b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/DebugVirtualConsoleSetting.xml similarity index 100% rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/DebugVirtualConsoleSetting.xml rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/DebugVirtualConsoleSetting.xml diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central new file mode 100644 index 0000000000..cfdcfba7d3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central @@ -0,0 +1 @@ +{"Scan":{"Name":"Scan","CheckEnableFast":false,"CheckSetAdvertisePeriod":false,"FastWindow":30,"FastInterval":60,"FastPeriod":30000,"ReduceWindow":11.25,"ReduceInterval":1280,"ReducePeriod":0,"PassiveScanning":true,"ActiveScanning":false,"AllowAll":true,"AllowOnlyWhitelist":false,"FilterDisabled":false,"FilterEnabled":true,"CheckFilterReset":false},"ScanFilterData":[{"Name":"Flags","AdType":1,"Check":false,"LimitediscoverableMode":false,"GeneralDiscoverableMode":true,"NonDiscoverableMode":false,"NotSupported":true,"Controller":false,"Host":false},{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":false,"ShortName":false,"LocalName":""},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"Connection":{"Name":"Connection","Interval":50,"Latency":0,"SupervisionTiomeOut":5120,"connectionTiomeOut":5}} \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral new file mode 100644 index 0000000000..97f1179109 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral @@ -0,0 +1 @@ +{"AdvertisingData":[{"Name":"Flags","AdType":1,"Check":true,"LimitediscoverableMode":false,"GeneralDiscoverableMode":true,"NonDiscoverableMode":false,"NotSupported":false,"Controller":true,"Host":true},{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":true,"ShortName":true,"LocalName":"RBLE"},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"Scan":[{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":true,"ShortName":false,"LocalName":"TEST_RBLE"},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"AdvertisingEventsData":{"Name":"AdvertisingEventsData","CheckEnableFast":false,"CheckSetAdvertisePeriod":false,"FastInterval":30,"FastPeriod":30000,"ReduceInterval":60,"ReducePeriod":0,"CheckChannel37":true,"CheckChannel38":true,"CheckChannel39":true,"PublicAddress":false,"RandomAddress":true,"CheckImage":true}} \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile new file mode 100644 index 0000000000..c65f8aa8eb --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile @@ -0,0 +1 @@ +{"profileName":"Profile","qeIsCentralDevice":false,"services":[{"name":"GAP Service","uuid":["0x00","0x18"],"abbreviation":"gap","description":"The generic_access service contains generic information about the device.","aux_properties":["None"],"error_codes":[],"characteristics":[{"name":"Device Name","abbreviation":"dev name","uuid":["0x00","0x2A"],"description":"The Device Name characteristic shall contain the name of the device.","properties":["Read","Write"],"aux_properties":[],"value":"","db_size":128,"fields":[{"name":"Name","description":"Name","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Appearance","abbreviation":"appearance","uuid":["0x01","0x2A"],"description":"The Appearance characteristic defines the representation of the external appearance of the device.","properties":["Read"],"aux_properties":[],"value":"","db_size":2,"fields":[{"name":"Category","description":"Category","format":"uint16_t","length":"1","enumerations":[{"value":"Unknown","key":0,"description":"Unknown"},{"value":"Generic Phone","key":64,"description":"Generic Phone"},{"value":"Generic Computer","key":128,"description":"Generic Computer"},{"value":"Generic Watch","key":192,"description":"Generic Watch"},{"value":"Watch Sports Watch","key":193,"description":"Watch: Sports Watch"},{"value":"Generic Clock","key":256,"description":"Generic Clock"},{"value":"Generic Display","key":320,"description":"Generic Display"},{"value":"Generic Remote Control","key":384,"description":"Generic Remote Control"},{"value":"Generic Eye-glasses","key":448,"description":"Generic Eye-glasses"},{"value":"Generic Tag","key":512,"description":"Generic Tag"},{"value":"Generic Keyring","key":576,"description":"Generic Keyring"},{"value":"Generic Media Player","key":640,"description":"Generic Media Player"},{"value":"Generic Barcode Scanner","key":704,"description":"Generic Barcode Scanner"},{"value":"Generic Thermometer","key":768,"description":"Generic Thermometer"},{"value":"Thermometer Ear","key":769,"description":"Thermometer Ear"},{"value":"Generic Heart rate Sensor","key":832,"description":"Generic Heart rate Sensor"},{"value":"Heart Rate Sensor Heart Rate Belt","key":833,"description":"Heart Rate Sensor Heart Rate Belt"},{"value":"Generic Blood Pressure","key":896,"description":"Generic Blood Pressure"},{"value":"Blood Pressure Arm","key":897,"description":"Blood Pressure: Arm"},{"value":"Blood Pressure Wrist","key":898,"description":"Blood Pressure: Wrist"},{"value":"Human Interface Device","key":960,"description":"Human Interface Device (HID)"},{"value":"Keyboard","key":961,"description":"Keyboard"},{"value":"Mouse","key":962,"description":"Mouse"},{"value":"Joystick","key":963,"description":"Joystick"},{"value":"Gamepad","key":964,"description":"Gamepad"},{"value":"Digitizer Tablet","key":965,"description":"Digitizer Tablet"},{"value":"Card Reader","key":966,"description":"Card Reader"},{"value":"Digital Pen","key":967,"description":"Digital Pen"},{"value":"Barcode Scanner","key":968,"description":"Barcode Scanner"},{"value":"Generic Glucose Meter","key":1024,"description":"Generic Glucose Meter"},{"value":"Generic Running Walking Sensor","key":1088,"description":"Generic: Running Walking Sensor"},{"value":"Running Walking Sensor In Shoe","key":1089,"description":"Running Walking Sensor: In-Shoe"},{"value":"Running Walking Sensor On Shoe","key":1090,"description":"Running Walking Sensor: On-Shoe"},{"value":"Running Walking Sensor On Hip","key":1091,"description":"Running Walking Sensor: On-Hip"},{"value":"Generic: Cycling","key":1152,"description":"Generic Cycling"},{"value":"Cycling Cycling Computer","key":1153,"description":"Cycling Cycling Computer"},{"value":"Cycling Speed Sensor","key":1154,"description":"Cycling Speed Sensor"},{"value":"Cycling Cadence Sensor","key":1155,"description":"Cycling Cadence Sensor"},{"value":"Cycling Power Sensor","key":1156,"description":"Cycling: Power Sensor"},{"value":"Cycling Speed and Cadence Sensor","key":1157,"description":"Cycling Speed and Cadence Sensor"},{"value":"Generic Pulse Oximeter","key":3136,"description":"Generic Pulse Oximeter"},{"value":"Fingertip","key":3137,"description":"Fingertip"},{"value":"Wrist Worn","key":3138,"description":"Wrist Worn"},{"value":"Generic: Weight Scale","key":3200,"description":"Generic Weight Scale"},{"value":"Generic Outdoor Sports Activity","key":5184,"description":"Generic Outdoor Sports Activity"},{"value":"Location Display Device","key":5185,"description":"Location Display Device"},{"value":"Location and Navigation Display Device","key":5186,"description":"Location and Navigation Display Device"},{"value":"Location Pod","key":5187,"description":"Location Pod"},{"value":"Location and Navigation Pod","key":5188,"description":"Location and Navigation Pod"}],"fields":[]}],"descriptors":[]},{"name":"Peripheral Preferred Connection Parameters","abbreviation":"per pref conn param","uuid":["0x04","0x2A"],"description":"The Peripheral Preferred Connection Parameters (PPCP) characteristic contains the preferred connection parameters of the Peripheral","properties":["Read"],"aux_properties":[],"value":"","db_size":8,"fields":[{"name":"Minimum Connection Interval","description":"Minimum Connection Interval","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Maximum Connection Interval","description":"Maximum Connection Interval","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Slave Latency","description":"Slave Latency","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Connection Supervision Timeout Multiplier","description":"Connection Supervision Timeout Multiplier","format":"uint16_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Central Address Resolution","abbreviation":"cent addr rslv","uuid":["0xA6","0x2A"],"description":"The Peripheral should check if the peer device supports address resolution by reading the Central Address Resolution characteristic.","properties":["Read"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"Central Address Resolution Support","description":"Central Address Resolution Support","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Resolvable Private Address Only","abbreviation":"rslv priv addr only","uuid":["0xC9","0x2A"],"description":"The device should check if the peer will only use Resolvable Private Addresses (RPAs) after bonding by reading the Resolvable Private Address Only characteristic.","properties":["Read"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"Resolvable Private Address Only","description":"Resolvable Private Address Only","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]}],"qeServiceDataIsSigAdopted":true,"qeServiceDefinitionJsonFileName":"generic_access.service.json","qeServiceDataIsOutputServerRole":true,"qeServiceDataIsOutputClentRole":true},{"name":"GATT Service","uuid":["0x01","0x18"],"abbreviation":"gat","description":"The Generic Attribute Service contains generic information of the GATT attributes.","aux_properties":["None"],"error_codes":[],"characteristics":[{"name":"Service Changed","abbreviation":"serv chged","uuid":["0x05","0x2A"],"description":"The Service Changed characteristic is a control-point attribute that shall be used to indicate to connected devices that services have changed.","properties":["Indicate"],"aux_properties":[],"value":"","db_size":4,"fields":[{"name":"start_hdl","description":"Start of Affected Attribute Handle Range","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"end_hdl","description":"End of Affected Attribute Handle Range","format":"uint16_t","length":"1","bits":[],"fields":[]}],"descriptors":[{"name":"Client Characteristic Configuration","abbreviation":"cli cnfg","uuid":["0x02","0x29"],"description":"Client Characteristic Configuration Descriptor","aux_properties":["Peer Specific"],"properties":["Read","Write"],"value":"","db_size":2,"fields":[{"name":"cli cnfg","description":"Client Characteristic Configuration","format":"uint16_t","length":"1","bits":[],"fields":[]}]}]}],"qeServiceDataIsSigAdopted":true,"qeServiceDefinitionJsonFileName":"generic_attribute.service.json","qeServiceDataIsOutputServerRole":true,"qeServiceDataIsOutputClentRole":false},{"name":"LED Switch Service","uuid":["0xE0","0xFC","0x8E","0x8E","0x96","0xB4","0x01","0xAB","0x67","0x42","0x05","0x5F","0x26","0x19","0x83","0x58"],"abbreviation":"ls","description":"This service exposes a control point to allow a peer device to control LEDs and switched on the device.","aux_properties":["None"],"error_codes":[],"characteristics":[{"name":"Switch State","abbreviation":"switch state","uuid":["0xE0","0xFC","0x8E","0x8E","0x96","0xB4","0x01","0xAB","0x67","0x42","0x05","0x5F","0x57","0x7F","0x83","0x58"],"description":"","properties":["Notify"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"State","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[{"name":"Client Characteristic Configuration","abbreviation":"cli cnfg","uuid":["0x02","0x29"],"description":"Client Characteristic Configuration Descriptor","aux_properties":["Peer Specific"],"properties":["Read","Write"],"value":"","db_size":2,"fields":[{"name":"cli cnfg","description":"Client Characteristic Configuration","format":"uint16_t","length":"1","bits":[],"fields":[]}]}]},{"name":"LED Blink Rate","abbreviation":"blink rate","uuid":["0xE0","0xFC","0x8E","0x8E","0x96","0xB4","0x01","0xAB","0x67","0x42","0x05","0x5F","0x2F","0xC3","0x83","0x58"],"description":"","properties":["Read","Write"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"Rate","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]}],"qeServiceDataIsSigAdopted":true,"qeServiceDefinitionJsonFileName":"led_switch.service.json","qeServiceDataIsOutputServerRole":true,"qeServiceDataIsOutputClentRole":false}]} \ No newline at end of file diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs similarity index 68% rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs index 86de7bc296..450a47cf61 100644 --- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs @@ -1,4 +1,4 @@ eclipse.preferences.version=1 is.toolchain.version=true store.version=2 -toolchain.version=8.3.1.20190703 +toolchain.version=9.2.1.20191025 diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs new file mode 100644 index 0000000000..466ccd04c2 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs @@ -0,0 +1,26 @@ +Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|12129667,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|4111916304,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|490858859,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|498646134,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|4163895945,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1395162982,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|4214990036,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2506583203,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3679261956,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3831616655,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2083176475,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|373608954,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2924246150,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|2262931981,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1383382254,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2182658037,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2220305532,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|984407218,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3047267965,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3528041316,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|979987894,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h +Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries= +Renesas\#\#BSP\#\#Board\#\#ra4w1_ek\#\#\#\#1.1.1/all=2052694186,ra/board/ra4w1_ek/board_leds.c|848047679,ra/board/ra4w1_ek/board_leds.h|3691049713,ra/board/ra4w1_ek/board_init.h|3724812700,ra/board/ra4w1_ek/board.h|3585244943,ra/board/ra4w1_ek/board_init.c +Renesas\#\#BSP\#\#Board\#\#ra4w1_ek\#\#\#\#1.1.1/libraries= +Renesas\#\#BSP\#\#ra4w1\#\#device\#\#\#\#1.1.1/all=3326152699,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +Renesas\#\#BSP\#\#ra4w1\#\#device\#\#\#\#1.1.1/libraries= +Renesas\#\#BSP\#\#ra4w1\#\#device\#\#R7FA4W1AD2CNG\#\#1.1.1/libraries= +Renesas\#\#BSP\#\#ra4w1\#\#fsp\#\#\#\#1.1.1/all=513511271,ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h|3768927438,ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h|2917656687,ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +Renesas\#\#BSP\#\#ra4w1\#\#fsp\#\#\#\#1.1.1/libraries= +Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.1.1/all=2826325088,ra/fsp/src/bsp/mcu/all/bsp_io.h|1465263727,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1248105138,ra/fsp/inc/api/bsp_api.h|3744453931,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1705712330,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|724348230,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2503058501,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3081550272,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1610165669,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1219976787,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3312859967,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3331707473,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1455154544,ra/fsp/inc/fsp_version.h|15519568,ra/fsp/src/bsp/mcu/all/bsp_irq.h|4239686018,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1067477278,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1417282846,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1747067909,ra/fsp/inc/fsp_common_api.h|2298882886,ra/fsp/inc/instances/r_ioport.h|1686790147,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|4110700937,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1954369379,ra/fsp/inc/fsp_features.h|3706642864,ra/fsp/src/bsp/mcu/all/bsp_common.h|3326152699,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2856633492,ra/fsp/inc/api/r_ioport_api.h|839014393,ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd|2687014826,ra/fsp/src/bsp/mcu/all/bsp_common.c|3332349192,ra/fsp/src/bsp/mcu/all/bsp_io.c|3017820483,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1455555581,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c +Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.1.1/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_agt\#\#\#\#1.1.1/all=1213652139,ra/fsp/inc/api/r_timer_api.h|752065559,ra/fsp/inc/instances/r_agt.h|1787020898,ra/fsp/src/r_agt/r_agt.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_agt\#\#\#\#1.1.1/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ble_all\#\#\#\#1.1.1/all=1286995238,ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a|2507386388,ra/fsp/inc/api/r_ble_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ble_all\#\#\#\#1.1.1/libraries=libr_ble.a +Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_lp\#\#\#\#1.1.1/all=4021293974,ra/fsp/inc/api/r_flash_api.h|370552005,ra/fsp/src/r_flash_lp/r_flash_lp.c|1716362007,ra/fsp/inc/instances/r_flash_lp.h|3984233619,ra/fsp/inc/api/r_cgc_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_lp\#\#\#\#1.1.1/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#1.1.1/all=1213652139,ra/fsp/inc/api/r_timer_api.h|1724221452,ra/fsp/src/r_gpt/r_gpt.c|126802177,ra/fsp/inc/instances/r_gpt.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#1.1.1/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#1.1.1/all=75401505,ra/fsp/src/r_icu/r_icu.c|654709621,ra/fsp/inc/api/r_external_irq_api.h|6538417,ra/fsp/inc/instances/r_icu.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#1.1.1/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.1.1/all=1161308720,ra/fsp/src/r_ioport/r_ioport.c|2856633492,ra/fsp/inc/api/r_ioport_api.h|2298882886,ra/fsp/inc/instances/r_ioport.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.1.1/libraries= +Renesas\#\#Middleware\#\#all\#\#rm_ble_abs\#\#\#\#1.1.1/all=656510312,ra/fsp/inc/api/rm_ble_abs_api.h|776300984,ra/fsp/src/rm_ble_abs/rm_ble_abs.c|1853646049,ra/fsp/inc/instances/rm_ble_abs.h +Renesas\#\#Middleware\#\#all\#\#rm_ble_abs\#\#\#\#1.1.1/libraries= +eclipse.preferences.version=1 diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.settingseditor.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.settingseditor.prefs new file mode 100644 index 0000000000..317de65114 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.settingseditor.prefs @@ -0,0 +1,2 @@ +com.renesas.cdt.ra.settingseditor.active_page=PinConfiguration +eclipse.preferences.version=1 diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.threads.configurator.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.threads.configurator.prefs new file mode 100644 index 0000000000..fbcb06897b --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/com.renesas.cdt.ra.threads.configurator.prefs @@ -0,0 +1,3 @@ +collapse/module.driver.ble_abs_on_ble.1062255950=false +collapse/module.network_on_ble_a.1874446514=false +eclipse.preferences.version=1 diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/e2studio_project.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/e2studio_project.prefs similarity index 56% rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/e2studio_project.prefs rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/e2studio_project.prefs index 22fbdcba51..136ed46f8b 100644 --- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/e2studio_project.prefs +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/e2studio_project.prefs @@ -1,3 +1,3 @@ # -#Mon Mar 30 11:36:40 IST 2020 -activeConfiguration=com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.1012749351 +#Wed Jun 03 15:58:50 JST 2020 +activeConfiguration=com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.940582034 diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/language.settings.xml b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/language.settings.xml similarity index 90% rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/language.settings.xml rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/language.settings.xml index 346f148cf7..132ae99269 100644 --- a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/language.settings.xml +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/language.settings.xml @@ -1,22 +1,22 @@ - + - + - + - + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/org.eclipse.cdt.core.prefs b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000000..253f23cad3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,172 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.core.formatter.align_composite_type_declarators=false +org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18 +org.eclipse.cdt.core.formatter.alignment_for_assignment=16 +org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=82 +org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16 +org.eclipse.cdt.core.formatter.alignment_for_compact_if=0 +org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=82 +org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18 +org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0 +org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16 +org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48 +org.eclipse.cdt.core.formatter.alignment_for_expression_list=0 +org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=82 +org.eclipse.cdt.core.formatter.alignment_for_member_access=0 +org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16 +org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16 +org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16 +org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line +org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line +org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line +org.eclipse.cdt.core.formatter.comment.line_up_line_comment_in_blocks_on_first_column=false +org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1 +org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true +org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=true +org.eclipse.cdt.core.formatter.compact_else_if=true +org.eclipse.cdt.core.formatter.continuation_indentation=2 +org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2 +org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false +org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false +org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0 +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false +org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=false +org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false +org.eclipse.cdt.core.formatter.indent_empty_lines=false +org.eclipse.cdt.core.formatter.indent_preprocessor_directives=false +org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true +org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=true +org.eclipse.cdt.core.formatter.indentation.size=4 +org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_after_template_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_at_end_of_file_if_missing=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_catch_in_try_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_before_closing_brace_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_colon_in_constructor_initializer_list=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_else_in_if_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_before_identifier_in_function_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_while_in_do_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block=insert +org.eclipse.cdt.core.formatter.insert_space_after_assignment_operator=insert +org.eclipse.cdt.core.formatter.insert_space_after_binary_operator=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_brace_in_block=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_paren_in_cast=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_base_clause=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_labeled_statement=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_expression_list=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_throws=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_cast=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_catch=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_parenthesized_expression=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_switch=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_while=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_postfix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_prefix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_question_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_after_semicolon_in_for=insert +org.eclipse.cdt.core.formatter.insert_space_after_unary_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_assignment_operator=insert +org.eclipse.cdt.core.formatter.insert_space_before_binary_operator=insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_cast=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_catch=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_for=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_if=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression=do not insert 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+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_expression_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_throws=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_invocation_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_cast=insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_method_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_list=insert +org.eclipse.cdt.core.formatter.insert_space_before_identifier_in_declarator_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_namespace_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_switch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_type_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_catch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_exception_specification=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_for=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_if=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_switch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_while=insert +org.eclipse.cdt.core.formatter.insert_space_before_postfix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_prefix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert 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+org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false +org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false +org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false +org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false +org.eclipse.cdt.core.formatter.lineSplit=120 +org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1 +org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true +org.eclipse.cdt.core.formatter.tabulation.char=space +org.eclipse.cdt.core.formatter.tabulation.size=4 +org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/R7FA4W1AD2CNG.pincfg b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/R7FA4W1AD2CNG.pincfg new file mode 100644 index 0000000000..652a1e38ee --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/R7FA4W1AD2CNG.pincfg @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/RA4W1-EK.pincfg b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/RA4W1-EK.pincfg new file mode 100644 index 0000000000..417e7b87c8 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/RA4W1-EK.pincfg @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/reset_ek_ra6m3 Debug.jlink b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ble_baremetal_ek_ra4w1 Debug.jlink similarity index 100% rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/reset_ek_ra6m3 Debug.jlink rename to application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ble_baremetal_ek_ra4w1 Debug.jlink diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ble_baremetal_ek_ra4w1 Debug.launch b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ble_baremetal_ek_ra4w1 Debug.launch new file mode 100644 index 0000000000..5c4fc8ecbd --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ble_baremetal_ek_ra4w1 Debug.launch @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/configuration.xml b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/configuration.xml new file mode 100644 index 0000000000..6a88fd72ce --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/configuration.xml @@ -0,0 +1,365 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + EK-RA4W1 Board Support Files + Renesas.RA_board_ra4w1_ek.1.1.1.pack + + + Board Support Package Common Files + Renesas.RA.1.1.1.pack + + + I/O Port + Renesas.RA.1.1.1.pack + + + Arm CMSIS Version 5 - Core (M) + Arm.CMSIS5.5.6.0.pack + + + Board support package for R7FA4W1AD2CNG + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Board support package for RA4W1 + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Board support package for RA4W1 - FSP Data + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Asynchronous General Purpose Timer + Renesas.RA.1.1.1.pack + + + Flash Memory Low Power + Renesas.RA.1.1.1.pack + + + General PWM Timer + Renesas.RA.1.1.1.pack + + + External Interrupt + Renesas.RA.1.1.1.pack + + + Bluetooth Low Energy Abstraction + Renesas.RA.1.1.1.pack + + + Renesas Bluetooth Low Energy Library + Renesas.RA.1.1.1.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/app_main.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/app_main.c new file mode 100644 index 0000000000..b39f9d12b6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/app_main.c @@ -0,0 +1,684 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/****************************************************************************** +* File Name : app_main.c +* Device(s) : RA4W1 +* Tool-Chain : e2Studio +* Description : This is a application file for peripheral role. +*******************************************************************************/ + +/****************************************************************************** + Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#include "rm_ble_abs_api.h" +#include "gatt_db.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "profile_cmn/r_ble_servc_if.h" +#include "hal_data.h" + +/* This code is needed for using FreeRTOS */ +#if (BSP_CFG_RTOS == 2) +#include "FreeRTOS.h" +#include "task.h" +#include "event_groups.h" +#define BLE_EVENT_PATTERN (0x0A0A) +EventGroupHandle_t g_ble_event_group_handle; +#endif +#include "r_ble_lss.h" + +/****************************************************************************** + User file includes +*******************************************************************************/ +/* Start user code for file includes. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +#define BLE_LOG_TAG "app_main" +#define BLE_GATTS_QUEUE_ELEMENTS_SIZE (14) +#define BLE_GATTS_QUEUE_BUFFER_LEN (245) +#define BLE_GATTS_QUEUE_NUM (1) + +/****************************************************************************** + User macro definitions +*******************************************************************************/ +/* Start user code for macro definitions. Do not edit comment generated here */ +#define BLE_CFG_BOARD_TYPE 1 + +#define BLE_BOARD_SW1_PIN BSP_IO_PORT_04_PIN_02 +#undef BLE_BOARD_SW2_PIN +#define BLE_BOARD_SW1_IRQ ELC_EVENT_ICU_IRQ4 +#undef BLE_BOARD_SW2_IRQ +#define BLE_BOARD_LED1_PIN BSP_IO_PORT_01_PIN_06 +#define BLE_BOARD_LED2_PIN BSP_IO_PORT_04_PIN_04 +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated function prototype declarations +*******************************************************************************/ +/* Internal functions */ +void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data); +void gatts_cb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data); +void gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data); +void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data); +ble_status_t ble_init(void); +void app_main(void); + +/****************************************************************************** + User function prototype declarations +*******************************************************************************/ +/* Start user code for function prototype declarations. Do not edit comment generated here */ +typedef enum +{ + BLE_BOARD_LED1, /**< LED1 */ + BLE_BOARD_LED2, /**< LED2 */ + + BLE_BOARD_LED_MAX +} e_ble_led_t; + +/*******************************************************************************************************************//** + * @brief Switch number. +***********************************************************************************************************************/ +typedef enum +{ + BLE_BOARD_SW1, /**< Switch1 */ + BLE_BOARD_SW2, /**< Switch2 */ + + BLE_BOARD_SW_MAX +} e_ble_sw_t; + + +typedef void (*ble_sw_cb_t)(void); +static void timer_update(); +static void sw_cb(void); +static void R_BLE_BOARD_Init(void); +static void R_BLE_BOARD_ToggleLEDState(e_ble_led_t led); +static void R_BLE_BOARD_SetLEDState(e_ble_led_t led, bool onoff); +static void R_BLE_BOARD_RegisterSwitchCb(e_ble_sw_t sw, ble_sw_cb_t cb); +static ble_sw_cb_t gs_sw_cb[BLE_BOARD_SW_MAX]; +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated global variables +*******************************************************************************/ +/* Advertising Data */ +static uint8_t gs_advertising_data[] = +{ + /* Flags */ + 0x02, /**< Data Size */ + 0x01, /**< Data Type */ + ( 0x1a ), /**< Data Value */ + + /* Shortened Local Name */ + 0x05, /**< Data Size */ + 0x08, /**< Data Type */ + 0x52, 0x42, 0x4c, 0x45, /**< Data Value */ +}; + +/* Scan Response Data */ +static uint8_t gs_scan_response_data[] = +{ + /* Complete Local Name */ + 0x0A, /**< Data Size */ + 0x09, /**< Data Type */ + 0x54, 0x45, 0x53, 0x54, 0x5f, 0x52, 0x42, 0x4c, 0x45, /**< Data Value */ +}; + +ble_abs_legacy_advertising_parameter_t g_ble_advertising_parameter = +{ + .p_peer_address = NULL, ///< Peer address. + .slow_advertising_interval = 0x00000060, ///< Slow advertising interval. 60.0(ms) + .slow_advertising_period = 0x0000, ///< Slow advertising period. + .p_advertising_data = gs_advertising_data, ///< Advertising data. If p_advertising_data is specified as NULL, advertising data is not set. + .advertising_data_length = ARRAY_SIZE(gs_advertising_data), ///< Advertising data length (in bytes). + .p_scan_response_data = gs_scan_response_data, ///< Scan response data. If p_scan_response_data is specified as NULL, scan response data is not set. + .scan_response_data_length = ARRAY_SIZE(gs_scan_response_data), ///< Scan response data length (in bytes). + .advertising_filter_policy = BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY, ///< Advertising Filter Policy. + .advertising_channel_map = ( BLE_GAP_ADV_CH_37 | BLE_GAP_ADV_CH_38 | BLE_GAP_ADV_CH_39 ), ///< Channel Map. + .own_bluetooth_address_type = BLE_GAP_ADDR_RAND, ///< Own Bluetooth address type. + .own_bluetooth_address = { 0 }, +}; + +/* GATT server callback parameters */ +ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[] = +{ + { + .gatt_server_callback_function = gatts_cb, + .gatt_server_callback_priority = 1, + }, + { + .gatt_server_callback_function = NULL, + } +}; + +/* GATT client callback parameters */ +ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[] = +{ + { + .gatt_client_callback_function = gattc_cb, + .gatt_client_callback_priority = 1, + }, + { + .gatt_client_callback_function = NULL, + } +}; + +/* GATT server Prepare Write Queue parameters */ +static st_ble_gatt_queue_elm_t gs_queue_elms[BLE_GATTS_QUEUE_ELEMENTS_SIZE]; +static uint8_t gs_buffer[BLE_GATTS_QUEUE_BUFFER_LEN]; +static st_ble_gatt_pre_queue_t gs_queue[BLE_GATTS_QUEUE_NUM] = { + { + .p_buf_start = gs_buffer, + .buffer_len = BLE_GATTS_QUEUE_BUFFER_LEN, + .p_queue = gs_queue_elms, + .queue_size = BLE_GATTS_QUEUE_ELEMENTS_SIZE, + } +}; + +/* Connection handle */ +uint16_t g_conn_hdl; + +/****************************************************************************** + User global variables +*******************************************************************************/ +/* Start user code for global variables. Do not edit comment generated here */ +static bool g_interval_update_flag = true; +static uint8_t g_current_blinky_interval = 0x88; +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated function definitions +*******************************************************************************/ +/****************************************************************************** + * Function Name: gap_cb + * Description : Callback function for GAP API. + * Arguments : uint16_t type - + * Event type of GAP API. + * : ble_status_t result - + * Event result of GAP API. + * : st_ble_vs_evt_data_t *p_data - + * Event parameters of GAP API. + * Return Value : none + ******************************************************************************/ +void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GAP callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + switch(type) + { + case BLE_GAP_EVENT_STACK_ON: + { + /* Get BD address for Advertising */ + R_BLE_VS_GetBdAddr(BLE_VS_ADDR_AREA_REG, BLE_GAP_ADDR_RAND); + } break; + + case BLE_GAP_EVENT_CONN_IND: + { + if (BLE_SUCCESS == result) + { + /* Store connection handle */ + st_ble_gap_conn_evt_t *p_gap_conn_evt_param = (st_ble_gap_conn_evt_t *)p_data->p_param; + g_conn_hdl = p_gap_conn_evt_param->conn_hdl; + } + else + { + /* Restart advertising when connection failed */ + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } + } break; + + case BLE_GAP_EVENT_DISCONN_IND: + { + /* Restart advertising when disconnected */ + g_conn_hdl = BLE_GAP_INVALID_CONN_HDL; + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } break; + + case BLE_GAP_EVENT_CONN_PARAM_UPD_REQ: + { + /* Send connection update response with value received on connection update request */ + st_ble_gap_conn_upd_req_evt_t *p_conn_upd_req_evt_param = (st_ble_gap_conn_upd_req_evt_t *)p_data->p_param; + + st_ble_gap_conn_param_t conn_updt_param = { + .conn_intv_min = p_conn_upd_req_evt_param->conn_intv_min, + .conn_intv_max = p_conn_upd_req_evt_param->conn_intv_max, + .conn_latency = p_conn_upd_req_evt_param->conn_latency, + .sup_to = p_conn_upd_req_evt_param->sup_to, + }; + + R_BLE_GAP_UpdConn(p_conn_upd_req_evt_param->conn_hdl, + BLE_GAP_CONN_UPD_MODE_RSP, + BLE_GAP_CONN_UPD_ACCEPT, + &conn_updt_param); + } break; + +/* Hint: Add cases of GAP event macros defined as BLE_GAP_XXX */ +/* Start user code for GAP callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: gatts_cb + * Description : Callback function for GATT Server API. + * Arguments : uint16_t type - + * Event type of GATT Server API. + * : ble_status_t result - + * Event result of GATT Server API. + * : st_ble_gatts_evt_data_t *p_data - + * Event parameters of GATT Server API. + * Return Value : none + ******************************************************************************/ +void gatts_cb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GATT Server callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVS_GattsCb(type, result, p_data); + switch(type) + { +/* Hint: Add cases of GATT Server event macros defined as BLE_GATTS_XXX */ +/* Start user code for GATT Server callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: gattc_cb + * Description : Callback function for GATT Client API. + * Arguments : uint16_t type - + * Event type of GATT Client API. + * : ble_status_t result - + * Event result of GATT Client API. + * : st_ble_gattc_evt_data_t *p_data - + * Event parameters of GATT Client API. + * Return Value : none + ******************************************************************************/ +void gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GATT Client callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVC_GattcCb(type, result, p_data); + switch(type) + { + +/* Hint: Add cases of GATT Client event macros defined as BLE_GATTC_XXX */ +/* Start user code for GATT Client callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: vs_cb + * Description : Callback function for Vendor Specific API. + * Arguments : uint16_t type - + * Event type of Vendor Specific API. + * : ble_status_t result - + * Event result of Vendor Specific API. + * : st_ble_vs_evt_data_t *p_data - + * Event parameters of Vendor Specific API. + * Return Value : none + ******************************************************************************/ +void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for vender specific callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVS_VsCb(type, result, p_data); + switch(type) + { + case BLE_VS_EVENT_GET_ADDR_COMP: + { + /* Start advertising when BD address is ready */ + st_ble_vs_get_bd_addr_comp_evt_t * get_address = (st_ble_vs_get_bd_addr_comp_evt_t *)p_data->p_param; + memcpy(g_ble_advertising_parameter.own_bluetooth_address, get_address->addr.addr, BLE_BD_ADDR_LEN); + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } break; + +/* Hint: Add cases of vender specific event macros defined as BLE_VS_XXX */ +/* Start user code for vender specific callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: lss_cb + * Description : Callback function for LED Switch Service server feature. + * Arguments : uint16_t type - + * Event type of LED Switch Service server feature. + * : ble_status_t result - + * Event result of LED Switch Service server feature. + * : st_ble_servs_evt_data_t *p_data - + * Event parameters of LED Switch Service server feature. + * Return Value : none + ******************************************************************************/ +static void lss_cb(uint16_t type, ble_status_t result, st_ble_servs_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for LED Switch Service Server callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + switch(type) + { +/* Hint: Add cases of LED Switch Service server events defined in e_ble_lss_event_t */ +/* Start user code for LED Switch Service Server callback function event process. Do not edit comment generated here */ + case BLE_LSS_EVENT_BLINK_RATE_WRITE_REQ: + { + g_current_blinky_interval = *(uint8_t *)p_data->p_param; + + if (g_current_blinky_interval == 0x00) + { + R_BLE_BOARD_SetLEDState(BLE_BOARD_LED1, true); // LED OFF + } + else if (g_current_blinky_interval == 0xFF) + { + R_BLE_BOARD_SetLEDState(BLE_BOARD_LED1, false); // LED ON + } + g_interval_update_flag = true; + } break; + + default: + break; +/* End user code. Do not edit comment generated here */ + } +} +/****************************************************************************** + * Function Name: ble_init + * Description : Initialize BLE and profiles. + * Arguments : none + * Return Value : BLE_SUCCESS - SUCCESS + * BLE_ERR_INVALID_OPERATION - + * Failed to initialize BLE or profiles. + ******************************************************************************/ +ble_status_t ble_init(void) +{ + ble_status_t status; + fsp_err_t err; + + /* Initialize BLE */ + err = RM_BLE_ABS_Open(&g_ble_abs0_ctrl, &g_ble_abs0_cfg); + if (FSP_SUCCESS != err) + { + return err; + } + + /* Initialize GATT Database */ + status = R_BLE_GATTS_SetDbInst(&g_gatt_db_table); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /* Initialize GATT server */ + status = R_BLE_SERVS_Init(); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /*Initialize GATT client */ + status = R_BLE_SERVC_Init(); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /* Set Prepare Write Queue */ + R_BLE_GATTS_SetPrepareQueue(gs_queue, BLE_GATTS_QUEUE_NUM); + + /* Initialize LED Switch Service server API */ + status = R_BLE_LSS_Init(lss_cb); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + return status; +} + +/****************************************************************************** + * Function Name: app_main + * Description : Application main function with main loop + * Arguments : none + * Return Value : none + ******************************************************************************/ +void app_main(void) +{ +#if (BSP_CFG_RTOS == 2) + /* Create Event Group */ + g_ble_event_group_handle = xEventGroupCreate(); + assert(g_ble_event_group_handle); +#endif + + /* Initialize BLE and profiles */ + ble_init(); + +/* Hint: Input process that should be done before main loop such as calling initial function or variable definitions */ +/* Start user code for process before main loop. Do not edit comment generated here */ + R_BLE_BOARD_Init(); + R_BLE_BOARD_RegisterSwitchCb(BLE_BOARD_SW1, sw_cb); +/* End user code. Do not edit comment generated here */ + + /* main loop */ + while (1) + { + /* Process BLE Event */ + R_BLE_Execute(); + +/* When this BLE application works on the FreeRTOS */ +#if (BSP_CFG_RTOS == 2) + if(0 != R_BLE_IsTaskFree()) + { + /* If the BLE Task has no operation to be processed, it transits block state until the event from RF transciever occurs. */ + xEventGroupWaitBits(g_ble_event_group_handle, + (EventBits_t)BLE_EVENT_PATTERN, + pdTRUE, + pdFALSE, + portMAX_DELAY); + } +#endif + +/* Hint: Input process that should be done during main loop such as calling processing functions */ +/* Start user code for process during main loop. Do not edit comment generated here */ + timer_update(); +/* End user code. Do not edit comment generated here */ + } + +/* Hint: Input process that should be done after main loop such as calling closing functions */ +/* Start user code for process after main loop. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + /* Terminate BLE */ + RM_BLE_ABS_Close(&g_ble_abs0_ctrl); +} + +/****************************************************************************** + User function definitions +*******************************************************************************/ +/* Start user code for function definitions. Do not edit comment generated here */ +/****************************************************************************** + * Function Name: timer_cb + * Description : Callback function for timer for LED blink. + * Arguments : uint32_t timer_hdl - + * Timer handle identifying a expired timer. + * Return Value : none + ******************************************************************************/ +static void timer_update() +{ + static uint32_t remain_time; + + if(true == g_interval_update_flag){ + remain_time = 1 + (uint32_t) g_current_blinky_interval * 50000 / 0xFF; + g_interval_update_flag = false; + }else if ((0 == remain_time)&&(0 != g_current_blinky_interval)&&(0xFF != g_current_blinky_interval)) + { + R_BLE_BOARD_ToggleLEDState (BLE_BOARD_LED1); + remain_time = 1 + (uint32_t) g_current_blinky_interval * 50000 / 0xFF; + } + + remain_time--; + +} + +static void sw_cb(void) +{ + uint8_t state = 1; + +#if (BLE_CFG_BOARD_TYPE == 1) +#endif + R_BLE_LSS_NotifySwitchState(g_conn_hdl, &state); +} + +static void R_BLE_BOARD_SetLEDState(e_ble_led_t led, bool onoff) +{ + FSP_PARAMETER_NOT_USED (onoff); + + if (led == BLE_BOARD_LED1) + { +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); +#if (BLE_CFG_BOARD_TYPE == 1) + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (onoff) ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); +#else + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (onoff) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); +#endif + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } + else if (led == BLE_BOARD_LED2) + { +#ifdef BLE_BOARD_LED2_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); +#if (BLE_CFG_BOARD_TYPE == 1) + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (onoff) ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); +#else + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (onoff) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); +#endif + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } +} + +static void R_BLE_BOARD_ToggleLEDState(e_ble_led_t led) +{ + bsp_io_level_t level; + + if (led == BLE_BOARD_LED1) + { +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + g_ioport.p_api->pinRead(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, &level); + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (level == BSP_IO_LEVEL_HIGH) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } + else if (led == BLE_BOARD_LED2) + { +#ifdef BLE_BOARD_LED2_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + g_ioport.p_api->pinRead(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, &level); + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (level == BSP_IO_LEVEL_HIGH) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } +} + +static void R_BLE_BOARD_RegisterSwitchCb(e_ble_sw_t sw, ble_sw_cb_t cb) +{ + FSP_PARAMETER_NOT_USED (cb); + + if (sw == BLE_BOARD_SW1) + { +#ifdef BLE_BOARD_SW1_IRQ + gs_sw_cb[0] = cb; + g_ble_sw_irq.p_api->open(g_ble_sw_irq.p_ctrl, g_ble_sw_irq.p_cfg); + g_ble_sw_irq.p_api->enable(g_ble_sw_irq.p_ctrl); +#endif + } + else if (sw == BLE_BOARD_SW2) + { +#ifdef BLE_BOARD_SW2_IRQ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_NMI_PIN, cb); + R_ICU->NMIER_b.NMIEN = 1; +#endif + } +} + +static void irq_pin_set(void) +{ + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + +#if (BLE_CFG_BOARD_TYPE == 0) /* for customer board */ + +#elif (BLE_CFG_BOARD_TYPE == 1) /* Promotion board */ + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW1_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + +#elif (BLE_CFG_BOARD_TYPE == 2) /* Reserve */ + +#elif (BLE_CFG_BOARD_TYPE == 3) /* RF Evaluation board */ + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW1_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW2_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + +#endif /* BLE_CFG_BOARD_TYPE == x */ + + g_ioport.p_api->close(g_ioport.p_ctrl); +} + +static void R_BLE_BOARD_Init(void) +{ + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, + IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_HIGH); +#endif +#if BLE_BOARD_LED2_PIN + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, + IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_LOW); +#endif + + g_ioport.p_api->close(g_ioport.p_ctrl); + + irq_pin_set(); + + /* Set wake up trigger */ +#if (BLE_CFG_BOARD_TYPE == 1) /* Promotion board */ +#elif (BLE_CFG_BOARD_TYPE == 2) /* RSSK */ +#elif (BLE_CFG_BOARD_TYPE == 3) /* Evaluation boars */ + R_BLE_BOARD_RegisterSwitchCb(BLE_BOARD_SW2, ble_sw_cb); +#endif +} + +void Callback_ble_sw_irq(external_irq_callback_args_t *p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + gs_sw_cb[0](); +} +/* End user code. Do not edit comment generated here */ \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c new file mode 100644 index 0000000000..29f53a1342 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c @@ -0,0 +1,519 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include "r_ble_disc.h" + +static uint8_t gs_state; +static uint8_t gs_target_inc_serv_pos; + +/* Entries */ +static const st_ble_disc_entry_t *gs_prim_entries; +static uint8_t gs_num_of_prim_entries; +static uint8_t gs_prim_entry_pos; + +/* Primary Service */ +static st_ble_gatt_hdl_range_t gs_serv_range; +static uint8_t gs_num_of_servs; + +/* Included Srvice */ +static st_disc_inc_serv_param_t gs_inc_servs[BLE_DISC_INC_SERV_MAX_NUM]; +static uint8_t gs_inc_serv_pos; +static uint8_t gs_num_of_inc_servs; + +/* Characteristic */ +static st_disc_char_param_t gs_chars[BLE_DISC_CHAR_MAX_NUM]; +static uint8_t gs_num_of_chars; +static uint8_t gs_char_pos; + +/* Descriptor */ +static st_disc_desc_param_t gs_descs[BLE_DISC_DESC_MAX_NUM]; +static uint8_t gs_num_of_descs; + +static bool gs_in_progress; +static ble_disc_comp_cb_t gs_comp_cb; + +static void r_ble_start_serv_disc(uint16_t conn_hdl); +static void r_ble_start_inc_serv_disc(uint16_t conn_hdl); +static void r_ble_start_char_disc(uint16_t conn_hdl); +static void r_ble_start_desc_disc(uint16_t conn_hdl); + +static bool r_ble_disc_next_prim_serv(uint16_t conn_hdl) +{ + gs_prim_entry_pos++; + + if (gs_prim_entry_pos < gs_num_of_prim_entries) + { + gs_inc_serv_pos = 0; + gs_state = 0; + r_ble_start_serv_disc(conn_hdl); + } + else + { + if (NULL != gs_comp_cb) + { + gs_comp_cb(conn_hdl); + } + + gs_in_progress = false; + } + + return true; +} + +static bool r_ble_disc_next_inc_serv(uint16_t conn_hdl) +{ + if (gs_inc_serv_pos < gs_num_of_inc_servs) + { + gs_state = 1; + + for (uint8_t i = gs_inc_serv_pos; i < gs_num_of_inc_servs; i++) + { + for (uint8_t j = 0; j < gs_prim_entries[gs_prim_entry_pos].num_of_inc_servs; j++) + { + st_ble_disc_entry_t *p_inc_serv = &gs_prim_entries[gs_prim_entry_pos].inc_servs[j]; + + if (p_inc_serv->uuid_type == gs_inc_servs[i].uuid_type) + { + if ( + ((BLE_GATT_16_BIT_UUID_FORMAT == p_inc_serv->uuid_type) && + (((p_inc_serv->p_uuid[1] << 8) | (p_inc_serv->p_uuid[0])) == gs_inc_servs[i].value.inc_serv_16.service.uuid_16)) || + ((BLE_GATT_128_BIT_UUID_FORMAT == p_inc_serv->uuid_type) && + (0 == memcmp(p_inc_serv->p_uuid, gs_inc_servs[i].value.inc_serv_128.service.uuid_128, BLE_GATT_128_BIT_UUID_SIZE)))) + { + gs_serv_range.start_hdl = gs_inc_servs[i].value.inc_serv_16.service.range.start_hdl; + gs_serv_range.end_hdl = gs_inc_servs[i].value.inc_serv_16.service.range.end_hdl; + gs_inc_serv_pos = (uint8_t)(i + 1); + gs_target_inc_serv_pos = j; + r_ble_start_char_disc(conn_hdl); + return true; + } + } + } + } + } + + return false; +} + +static bool r_ble_disc_next_char(uint16_t conn_hdl) +{ + gs_char_pos++; + + if (gs_char_pos < gs_num_of_chars) + { + r_ble_start_desc_disc(conn_hdl); + return true; + } + + return false; +} + +static void r_ble_all_disc_process(uint16_t event, uint16_t conn_hdl) +{ + switch (event) + { + case BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP: + { + if (0 == gs_num_of_servs) + { + r_ble_disc_next_prim_serv(conn_hdl); + } + else + { + r_ble_start_inc_serv_disc(conn_hdl); + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_DISC_COMP: + { + r_ble_start_char_disc(conn_hdl); + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP: + { + r_ble_start_desc_disc(conn_hdl); + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP: + { + bool next; + + next = r_ble_disc_next_char(conn_hdl); + + if (false == next) + { + next = r_ble_disc_next_inc_serv(conn_hdl); + + if (false == next) + { + r_ble_disc_next_prim_serv(conn_hdl); + } + } + } break; + + default: + { + } break; + } +} + +static void r_ble_start_serv_disc(uint16_t conn_hdl) +{ + gs_num_of_servs = 0; + + memset(&gs_serv_range, 0x00, sizeof(gs_serv_range)); + + R_BLE_GATTC_DiscPrimServ(conn_hdl, + gs_prim_entries[gs_prim_entry_pos].p_uuid, + gs_prim_entries[gs_prim_entry_pos].uuid_type); +} + +static void r_ble_start_inc_serv_disc(uint16_t conn_hdl) +{ + gs_num_of_inc_servs = 0; + gs_inc_serv_pos = 0; + + for (uint8_t i = 0; i < BLE_DISC_INC_SERV_MAX_NUM; i++) + { + memset(&gs_inc_servs[i], 0x00, sizeof(gs_inc_servs[i])); + } + + R_BLE_GATTC_DiscIncServ(conn_hdl, &gs_serv_range); +} + +static void r_ble_start_char_disc(uint16_t conn_hdl) +{ + gs_num_of_chars = 0; + gs_char_pos = 0; + + for (uint8_t i = 0; i < BLE_DISC_CHAR_MAX_NUM; i++) + { + memset(&gs_chars[i], 0x00, sizeof(gs_chars[i])); + } + + R_BLE_GATTC_DiscAllChar(conn_hdl, &gs_serv_range); +} + +static void r_ble_start_desc_disc(uint16_t conn_hdl) +{ + gs_num_of_descs = 0; + + for (uint8_t i = 0; i < BLE_DISC_DESC_MAX_NUM; i++) + { + memset(&gs_descs[i], 0x00, sizeof(gs_descs[i])); + } + + st_ble_gatt_hdl_range_t range; + + if (BLE_GATT_16_BIT_UUID_FORMAT == gs_chars[gs_char_pos].uuid_type) + { + range.start_hdl = gs_chars[gs_char_pos].value.char_16.decl_hdl; + } + else + { + range.start_hdl = gs_chars[gs_char_pos].value.char_128.decl_hdl; + } + + if (gs_char_pos < (gs_num_of_chars - 1)) + { + if (BLE_GATT_16_BIT_UUID_FORMAT == gs_chars[gs_char_pos+1].uuid_type) + { + range.end_hdl = gs_chars[gs_char_pos+1].value.char_16.decl_hdl; + } + else + { + range.end_hdl = gs_chars[gs_char_pos+1].value.char_128.decl_hdl; + } + } + else + { + range.end_hdl = gs_serv_range.end_hdl; + } + + R_BLE_GATTC_DiscAllCharDesc(conn_hdl, &range); +} + +static void r_ble_disc_gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data) // @suppress("Function length") +{ + /* unused arg */ + (void)result; + + switch (type) + { + case BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND: + { + st_ble_gattc_serv_16_evt_t *p_serv_uuid_16_evt_params = + (st_ble_gattc_serv_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_serv_16_evt_t)); i++) + { + if (gs_num_of_servs == gs_prim_entries[gs_prim_entry_pos].idx) + { + st_disc_serv_param_t serv_param = { + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .value.serv_16.range = p_serv_uuid_16_evt_params[i].range, + .value.serv_16.uuid_16 = p_serv_uuid_16_evt_params[i].uuid_16, + }; + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_FOUND, + &serv_param); + + memcpy(&gs_serv_range, &p_serv_uuid_16_evt_params[i].range, sizeof(gs_serv_range)); + } + + gs_num_of_servs++; + } + } break; + + case BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND: + { + st_ble_gattc_serv_128_evt_t *p_serv_uuid_128_evt_params = + (st_ble_gattc_serv_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_serv_128_evt_t)); i++) + { + if (gs_num_of_servs == gs_prim_entries[gs_prim_entry_pos].idx) + { + st_disc_serv_param_t serv_param = { + .uuid_type = BLE_GATT_128_BIT_UUID_FORMAT, + .value.serv_128.range = p_serv_uuid_128_evt_params[i].range, + }; + memcpy(serv_param.value.serv_128.uuid_128, p_serv_uuid_128_evt_params[i].uuid_128, BLE_GATT_128_BIT_UUID_SIZE); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_FOUND, + &serv_param); + memcpy(&gs_serv_range, &p_serv_uuid_128_evt_params[i].range, sizeof(gs_serv_range)); + } + + gs_num_of_servs++; + } + } break; + + case BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP: + { + if (0 == gs_num_of_servs) + { + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_NOT_FOUND, + NULL); + } + + r_ble_all_disc_process(BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_INC_SERV_16_DISC_IND: + { + st_ble_gattc_inc_serv_16_evt_t *p_inc_serv_16_evt_param = + (st_ble_gattc_inc_serv_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_inc_serv_16_evt_t)); i++) + { + gs_inc_servs[gs_num_of_inc_servs].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_16, + &p_inc_serv_16_evt_param[0], + sizeof(gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_16)); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_INC_SERV_FOUND, + &gs_inc_servs[gs_num_of_inc_servs]); + + gs_num_of_inc_servs++; + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_128_DISC_IND: + { + st_ble_gattc_inc_serv_128_evt_t *p_inc_serv_128_evt_param = + (st_ble_gattc_inc_serv_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_inc_serv_128_evt_t)); i++) + { + gs_inc_servs[gs_num_of_inc_servs].uuid_type = BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_128, + p_inc_serv_128_evt_param, + sizeof(gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_128)); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_INC_SERV_FOUND, + &gs_inc_servs[gs_num_of_inc_servs]); + + gs_num_of_inc_servs++; + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_DISC_COMP: + { + r_ble_all_disc_process(BLE_GATTC_EVENT_INC_SERV_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_CHAR_16_DISC_IND: + { + st_ble_gattc_char_16_evt_t *p_char_16_evt_params = + (st_ble_gattc_char_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_16_evt_t)); i++) + { + gs_chars[gs_num_of_chars].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_chars[gs_num_of_chars].value.char_16, + &p_char_16_evt_params[i], + sizeof(gs_chars[gs_num_of_chars].value.char_16)); + + gs_num_of_chars++; + } + } break; + + case BLE_GATTC_EVENT_CHAR_128_DISC_IND: + { + st_ble_gattc_char_128_evt_t *p_char_128_evt_params = + (st_ble_gattc_char_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_128_evt_t)); i++) + { + gs_chars[gs_num_of_chars].uuid_type = BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_chars[gs_num_of_chars].value.char_128, + &p_char_128_evt_params[i], + sizeof(gs_chars[gs_num_of_chars].value.char_128)); + + gs_num_of_chars++; + } + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP: + { + r_ble_all_disc_process(BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND: + { + st_ble_gattc_char_desc_16_evt_t *p_char_desc_16_evt_params = + (st_ble_gattc_char_desc_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_desc_16_evt_t)); i++) + { + gs_descs[gs_num_of_descs].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_descs[gs_num_of_descs].value.desc_16, + &p_char_desc_16_evt_params[i], + sizeof(gs_descs[gs_num_of_descs].value.desc_16)); + + gs_num_of_descs++; + } + } break; + + case BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND: + { + st_ble_gattc_char_desc_128_evt_t *p_char_desc_128_evt_params = + (st_ble_gattc_char_desc_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_desc_128_evt_t)); i++) + { + gs_descs[gs_num_of_descs].uuid_type = + BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_descs[gs_num_of_descs].value.desc_128, + &p_char_desc_128_evt_params[i], + sizeof(gs_descs[gs_num_of_descs].value.desc_128)); + + gs_num_of_descs++; + } + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP: + { + gs_chars[gs_char_pos].descs = gs_descs; + gs_chars[gs_char_pos].num_of_descs = gs_num_of_descs; + + if (0 == gs_state) + { + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_CHAR_FOUND, + &gs_chars[gs_char_pos]); + } + else if (1 == gs_state) + { + gs_prim_entries[gs_prim_entry_pos].inc_servs[gs_target_inc_serv_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].inc_servs[gs_target_inc_serv_pos].idx, + BLE_DISC_CHAR_FOUND, + &gs_chars[gs_char_pos]); + } + else + { + /* Do nothing. */ + } + + r_ble_all_disc_process(BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + default: + { + /* Do nothing. */ + } + } +} + +ble_status_t R_BLE_DISC_Init(void) // @suppress("API function naming") +{ + return R_BLE_GATTC_RegisterCb(r_ble_disc_gattc_cb, 1); +} + +ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, const st_ble_disc_entry_t *p_entries, uint8_t num_of_entires, ble_disc_comp_cb_t cb) // @suppress("API function naming") +{ + if (gs_in_progress) + { + return BLE_ERR_ALREADY_IN_PROGRESS; + } + + gs_prim_entries = p_entries; + gs_num_of_prim_entries = num_of_entires; + + gs_in_progress = true; + gs_comp_cb = cb; + gs_prim_entry_pos = 0; + + r_ble_start_serv_disc(conn_hdl); + + return BLE_SUCCESS; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h new file mode 100644 index 0000000000..c7f6045a69 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h @@ -0,0 +1,215 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup discovery GATT Discovery Library + * @{ + * @ingroup profile_cmn + * @brief GATT Discovery Library + * @details This library provides APIs to discovery remote GATT database. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#include "r_ble_rx23w_if.h" +#else +/*RA4W*/ +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef R_BLE_DISC_H +#define R_BLE_DISC_H + +/** @defgroup discovery_macro Macros + * @{ + * @brief Macro definition + */ +/*******************************************************************************************************************//** + * @brief Maximum number of services to discover. +***********************************************************************************************************************/ +#define BLE_DISC_PRIM_SERV_MAX_NUM (10) + +/*******************************************************************************************************************//** + * @brief Maximum number of included services to discover. +***********************************************************************************************************************/ +#define BLE_DISC_INC_SERV_MAX_NUM (2) + +/*******************************************************************************************************************//** + * @brief Maximum number of characteristics to discover in a service. +***********************************************************************************************************************/ +#define BLE_DISC_CHAR_MAX_NUM (40) + +/*******************************************************************************************************************//** + * @brief Maximum number of descriptors to discover in a characteristic +***********************************************************************************************************************/ +#define BLE_DISC_DESC_MAX_NUM (10) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief GATT Discovery event. +***********************************************************************************************************************/ +typedef enum +{ + BLE_DISC_PRIM_SERV_FOUND, /**< Service discovered event */ + BLE_DISC_INC_SERV_FOUND, /**< Included service discovered event */ + BLE_DISC_PRIM_SERV_NOT_FOUND, /**< Service not discovered event */ + BLE_DISC_CHAR_FOUND, /**< Characteristic discovered event */ +} e_ble_disc_evt_t; +/*@}*/ + +/** @defgroup discovery_callback Callbacks + * @{ + * @brief Callback definition + */ +/*******************************************************************************************************************//** + * @brief Callback invoked when discovery is completed. + * @param conn_hdl connection handle +***********************************************************************************************************************/ +typedef void (* ble_disc_comp_cb_t)(uint16_t conn_hdl); + +/*******************************************************************************************************************//** + * @brief Callback invoked when service discovered. + * @param conn_hdl connection handle +***********************************************************************************************************************/ +typedef void (* ble_disc_serv_cb_t)(uint16_t conn_hdl, uint8_t idx, uint16_t type, void *p_param); +/*@}*/ + +/** @defgroup discovery_struct Structures + * @{ + * @brief Structure definition + */ +/*******************************************************************************************************************//** + * @brief Structure of service uuid to discover. +***********************************************************************************************************************/ +typedef struct st_ble_disc_entry_t +{ + uint8_t idx; /**< Service Index */ + uint8_t *p_uuid; /**< Service UUID */ + uint8_t uuid_type; /**< Service UUID type */ + ble_disc_serv_cb_t serv_cb; /**< Service discovery callback */ + uint8_t num_of_inc_servs; /**< Number of included services */ + struct st_ble_disc_entry_t *inc_servs; /**< Included service entries */ +} st_ble_disc_entry_t; + +/*******************************************************************************************************************//** + * @brief Discovered service information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered service UUID type */ + union + { + st_ble_gattc_serv_16_evt_t serv_16; + st_ble_gattc_serv_128_evt_t serv_128; + } value; +} st_disc_serv_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered included service information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered service UUID type */ + union + { + st_ble_gattc_inc_serv_16_evt_t inc_serv_16; + st_ble_gattc_inc_serv_128_evt_t inc_serv_128; + } value; +} st_disc_inc_serv_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered descriptor information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered descriptor UUID type */ + union + { + st_ble_gattc_char_desc_16_evt_t desc_16; + st_ble_gattc_char_desc_128_evt_t desc_128; + } value; +} st_disc_desc_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered characteristic information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered characteristic UUID type */ + union + { + st_ble_gattc_char_16_evt_t char_16; + st_ble_gattc_char_128_evt_t char_128; + } value; + + uint8_t num_of_descs; + st_disc_desc_param_t *descs; +} st_disc_char_param_t; +/*@}*/ + +/** @defgroup discovery_func Functions + * @{ + * @brief Function definition + */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @fn ble_status_t R_BLE_DISC_Init(void) + * @brief Initialize the GATT services discovery function. + * @return See @ref ble_status_t +***********************************************************************************************************************/ +ble_status_t R_BLE_DISC_Init(void); + +/*******************************************************************************************************************//** + * @fn ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, + * const st_ble_disc_entry_t *p_entries, + * uint8_t num_of_entires, + * ble_disc_comp_cb_t cb + * ) + * @brief Start GATT service discovery. + * @param[in] conn_hdl connection handle + * @param[in] p_entries The information of services to be detected. + * @param[in] num_of_entires The number of services to be detected. + * @param[in] cb The callback function which is called when the service has been detected. + * @return See @ref ble_status_t +***********************************************************************************************************************/ +ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, const st_ble_disc_entry_t *p_entries, uint8_t num_of_entires, ble_disc_comp_cb_t cb); +/*@}*/ + +#endif /* R_BLE_DISC_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.c new file mode 100644 index 0000000000..978147b065 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.c @@ -0,0 +1,918 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/** + * GATT DATABASE QUICK REFERENCE TABLE: + * Abbreviations used for PROPERTIES: + * BC = Broadcast + * RD = Read + * WW = Write Without Response + * WR = Write + * NT = Notification + * IN = Indication + * RW = Reliable Write + * + * HANDLE | ATT_TYPE | PROPERTIES | ATT_VALUE | DEFINITION + * ============================================================================================ + * GAP Service + * ============================================================================================ + * 0x0001 | 0x28,0x00 | RD | 0x00,0x18 | GAP Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0002 | 0x28,0x03 | RD | 0x0A,0x03,0x00,0x00,0x2A | Device Name characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0003 | 0x00,0x2A | RD,WR | 0x00,0x00,0x00,0x00,0x00,0x00... | Device Name characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0004 | 0x28,0x03 | RD | 0x02,0x05,0x00,0x01,0x2A | Appearance characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0005 | 0x01,0x2A | RD | 0x00,0x00 | Appearance characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0006 | 0x28,0x03 | RD | 0x02,0x07,0x00,0x04,0x2A | Peripheral Preferred Connection Parameters characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0007 | 0x04,0x2A | RD | 0x00,0x00,0x00,0x00,0x00,0x00... | Peripheral Preferred Connection Parameters characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0008 | 0x28,0x03 | RD | 0x02,0x09,0x00,0xA6,0x2A | Central Address Resolution characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0009 | 0xA6,0x2A | RD | 0x00 | Central Address Resolution characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000A | 0x28,0x03 | RD | 0x02,0x0B,0x00,0xC9,0x2A | Resolvable Private Address Only characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000B | 0xC9,0x2A | RD | 0x00 | Resolvable Private Address Only characteristic value + * ============================================================================================ + * GATT Service + * ============================================================================================ + * 0x000C | 0x28,0x00 | RD | 0x01,0x18 | GATT Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000D | 0x28,0x03 | RD | 0x20,0x0E,0x00,0x05,0x2A | Service Changed characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000E | 0x05,0x2A | IN | 0x00,0x00,0x00,0x00 | Service Changed characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000F | 0x02,0x29 | RD,WR | 0x00,0x00 | Client Characteristic Configuration descriptor + * ============================================================================================ + * LED Switch Service + * ============================================================================================ + * 0x0010 | 0x28,0x00 | RD | 0xE0,0xFC,0x8E,0x8E,0x96,0xB4... | LED Switch Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0011 | 0x28,0x03 | RD | 0x10,0x12,0x00,0xE0,0xFC,0x8E... | Switch State characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0012 | 0xE0,0xFC,0x8E... | NT | 0x00 | Switch State characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0013 | 0x02,0x29 | RD,WR | 0x00,0x00 | Client Characteristic Configuration descriptor + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0014 | 0x28,0x03 | RD | 0x0A,0x15,0x00,0xE0,0xFC,0x8E... | LED Blink Rate characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0015 | 0xE0,0xFC,0x8E... | RD,WR | 0x00 | LED Blink Rate characteristic value + * ============================================================================================ + + */ + +/******************************************************************************* +* Includes , "Project Includes" +*******************************************************************************/ +#include +#include "gatt_db.h" + +/***************************************************************************** +* Global definition +******************************************************************************/ +static const uint8_t gs_gatt_const_uuid_arr[] = +{ + /* Primary Service Declaration : 0 */ + 0x00, 0x28, + + /* Secondary Service Declaration : 2 */ + 0x01, 0x28, + + /* Included Service Declaration : 4 */ + 0x02, 0x28, + + /* Characteristic Declaration : 6 */ + 0x03, 0x28, + + /* GAP Service : 8 */ + 0x00, 0x18, + + /* Device Name : 10 */ + 0x00, 0x2A, + + /* Appearance : 12 */ + 0x01, 0x2A, + + /* Peripheral Preferred Connection Parameters : 14 */ + 0x04, 0x2A, + + /* Central Address Resolution : 16 */ + 0xA6, 0x2A, + + /* Resolvable Private Address Only : 18 */ + 0xC9, 0x2A, + + /* GATT Service : 20 */ + 0x01, 0x18, + + /* Service Changed : 22 */ + 0x05, 0x2A, + + /* Client Characteristic Configuration : 24 */ + 0x02, 0x29, + + /* LED Switch Service : 26 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x26, 0x19, 0x83, 0x58, + + /* Switch State : 42 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x57, 0x7F, 0x83, 0x58, + + /* LED Blink Rate : 58 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x2F, 0xC3, 0x83, 0x58, + +}; + +static uint8_t gs_gatt_value_arr[] = +{ + /* Device Name */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Appearance */ + 0x00, 0x00, + + /* Peripheral Preferred Connection Parameters */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Central Address Resolution */ + 0x00, + + /* Resolvable Private Address Only */ + 0x00, + + /* LED Blink Rate */ + 0x00, + +}; + +static const uint8_t gs_gatt_const_value_arr[] = +{ + /* Device Name */ + 0x0A, // Properties + 0x03, 0x00, // Attr Handle + 0x00, 0x2A, // UUID + + /* Appearance */ + 0x02, // Properties + 0x05, 0x00, // Attr Handle + 0x01, 0x2A, // UUID + + /* Peripheral Preferred Connection Parameters */ + 0x02, // Properties + 0x07, 0x00, // Attr Handle + 0x04, 0x2A, // UUID + + /* Central Address Resolution */ + 0x02, // Properties + 0x09, 0x00, // Attr Handle + 0xA6, 0x2A, // UUID + + /* Resolvable Private Address Only */ + 0x02, // Properties + 0x0B, 0x00, // Attr Handle + 0xC9, 0x2A, // UUID + + /* Service Changed */ + 0x20, // Properties + 0x0E, 0x00, // Attr Handle + 0x05, 0x2A, // UUID + + /* Switch State */ + 0x10, // Properties + 0x12, 0x00, // Attr Handle + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x57, 0x7F, 0x83, 0x58, // UUID + + /* LED Blink Rate */ + 0x0A, // Properties + 0x15, 0x00, // Attr Handle + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x2F, 0xC3, 0x83, 0x58, // UUID + +}; + +static uint8_t gs_gatt_db_peer_specific_val_arr[4*8]; + +static const uint8_t gs_gatt_db_const_peer_specific_val_arr[] = +{ + /* Service Changed : Client Characteristic Configuration */ + 0x00, 0x00, + + /* Switch State : Client Characteristic Configuration */ + 0x00, 0x00, + +}; + +static const st_ble_gatts_db_uuid_cfg_t gs_gatt_type_table[] = +{ + /* 0 : Primary Service Declaration */ + { + /* UUID Offset */ + 0, + /* First Occurrence for Type */ + 0x0001, + /* Last Occurrence for Type */ + 0x0010, + }, + + /* 1 : GAP Service */ + { + /* UUID Offset */ + 8, + /* First Occurrence for Type */ + 0x0001, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 2 : Characteristic Declaration */ + { + /* UUID Offset */ + 6, + /* First Occurrence for Type */ + 0x0002, + /* Last Occurrence for Type */ + 0x0014, + }, + + /* 3 : Device Name */ + { + /* UUID Offset */ + 10, + /* First Occurrence for Type */ + 0x0003, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 4 : Appearance */ + { + /* UUID Offset */ + 12, + /* First Occurrence for Type */ + 0x0005, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 5 : Peripheral Preferred Connection Parameters */ + { + /* UUID Offset */ + 14, + /* First Occurrence for Type */ + 0x0007, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 6 : Central Address Resolution */ + { + /* UUID Offset */ + 16, + /* First Occurrence for Type */ + 0x0009, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 7 : Resolvable Private Address Only */ + { + /* UUID Offset */ + 18, + /* First Occurrence for Type */ + 0x000B, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 8 : GATT Service */ + { + /* UUID Offset */ + 20, + /* First Occurrence for Type */ + 0x000C, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 9 : Service Changed */ + { + /* UUID Offset */ + 22, + /* First Occurrence for Type */ + 0x000E, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 10 : Client Characteristic Configuration */ + { + /* UUID Offset */ + 24, + /* First Occurrence for Type */ + 0x000F, + /* Last Occurrence for Type */ + 0x0013, + }, + + /* 11 : LED Switch Service */ + { + /* UUID Offset */ + 26, + /* First Occurrence for Type */ + 0x0010, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 12 : Switch State */ + { + /* UUID Offset */ + 42, + /* First Occurrence for Type */ + 0x0012, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 13 : LED Blink Rate */ + { + /* UUID Offset */ + 58, + /* First Occurrence for Type */ + 0x0015, + /* Last Occurrence for Type */ + 0x0000, + }, + +}; + +static const st_ble_gatts_db_attr_cfg_t gs_gatt_db_attr_table[] = +{ + /* Handle : 0x0000 */ + /* Blank */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_NO_AUXILIARY_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0001, + /* UUID Offset */ + 0, + /* Value */ + NULL, + }, + + /* Handle : 0x0001 */ + /* GAP Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x000C, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 8), + }, + + /* Handle : 0x0002 */ + /* Device Name : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0004, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 0), + }, + + /* Handle : 0x0003 */ + /* Device Name */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 128, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 10, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 0), + }, + + /* Handle : 0x0004 */ + /* Appearance : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0006, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 5), + }, + + /* Handle : 0x0005 */ + /* Appearance */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 12, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 128), + }, + + /* Handle : 0x0006 */ + /* Peripheral Preferred Connection Parameters : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0008, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 10), + }, + + /* Handle : 0x0007 */ + /* Peripheral Preferred Connection Parameters */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 8, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 14, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 130), + }, + + /* Handle : 0x0008 */ + /* Central Address Resolution : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x000A, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 15), + }, + + /* Handle : 0x0009 */ + /* Central Address Resolution */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 16, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 138), + }, + + /* Handle : 0x000A */ + /* Resolvable Private Address Only : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x000D, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 20), + }, + + /* Handle : 0x000B */ + /* Resolvable Private Address Only */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 18, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 139), + }, + + /* Handle : 0x000C */ + /* GATT Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0010, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 20), + }, + + /* Handle : 0x000D */ + /* Service Changed : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0011, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 25), + }, + + /* Handle : 0x000E */ + /* Service Changed */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 4, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 22, + /* Value */ + (NULL), + }, + + /* Handle : 0x000F */ + /* Service Changed : Client Characteristic Configuration */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0013, + /* UUID Offset */ + 24, + /* Value */ + (uint8_t *)(gs_gatt_db_peer_specific_val_arr + 0), + }, + + /* Handle : 0x0010 */ + /* LED Switch Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 16, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 26), + }, + + /* Handle : 0x0011 */ + /* Switch State : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 19, + /* Next Attribute Type Index */ + 0x0014, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 30), + }, + + /* Handle : 0x0012 */ + /* Switch State */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 42, + /* Value */ + (NULL), + }, + + /* Handle : 0x0013 */ + /* Switch State : Client Characteristic Configuration */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 24, + /* Value */ + (uint8_t *)(gs_gatt_db_peer_specific_val_arr + 2), + }, + + /* Handle : 0x0014 */ + /* LED Blink Rate : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 19, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 49), + }, + + /* Handle : 0x0015 */ + /* LED Blink Rate */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 58, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 140), + }, + +}; + +static const st_ble_gatts_db_char_cfg_t gs_gatt_characteristic[] = +{ + /* 0 : Device Name */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0002, + /* Service Index */ + 0, + }, + + /* 1 : Appearance */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0004, + /* Service Index */ + 0, + }, + + /* 2 : Peripheral Preferred Connection Parameters */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0006, + /* Service Index */ + 0, + }, + + /* 3 : Central Address Resolution */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0008, + /* Service Index */ + 0, + }, + + /* 4 : Resolvable Private Address Only */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x000A, + /* Service Index */ + 0, + }, + + /* 5 : Service Changed */ + { + /* Number of Attributes */ + { + 3, + }, + /* Start Handle */ + 0x000D, + /* Service Index */ + 1, + }, + + /* 6 : Switch State */ + { + /* Number of Attributes */ + { + 3, + }, + /* Start Handle */ + 0x0011, + /* Service Index */ + 2, + }, + + /* 7 : LED Blink Rate */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0014, + /* Service Index */ + 2, + }, + +}; + +static const st_ble_gatts_db_serv_cfg_t gs_gatt_service[] = +{ + /* GAP Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x0001, + /* Service End Handle */ + 0x000B, + /* Characteristic Start Index */ + 0, + /* Characteristic End Index */ + 4, + }, + + /* GATT Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x000C, + /* Service End Handle */ + 0x000F, + /* Characteristic Start Index */ + 5, + /* Characteristic End Index */ + 5, + }, + + /* LED Switch Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x0010, + /* Service End Handle */ + 0x0015, + /* Characteristic Start Index */ + 6, + /* Characteristic End Index */ + 7, + }, + +}; + +st_ble_gatts_db_cfg_t g_gatt_db_table = +{ + gs_gatt_const_uuid_arr, + gs_gatt_value_arr, + gs_gatt_const_value_arr, + gs_gatt_db_peer_specific_val_arr, + gs_gatt_db_const_peer_specific_val_arr, + gs_gatt_type_table, + gs_gatt_db_attr_table, + gs_gatt_characteristic, + gs_gatt_service, + ARRAY_SIZE(gs_gatt_service), + ARRAY_SIZE(gs_gatt_characteristic), + ARRAY_SIZE(gs_gatt_type_table), + ARRAY_SIZE(gs_gatt_db_const_peer_specific_val_arr), +}; \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.h new file mode 100644 index 0000000000..8fa92f9a9a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/gatt_db.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef GATT_DB_H +#define GATT_DB_H + +#include "profile_cmn/r_ble_serv_common.h" + +extern st_ble_gatts_db_cfg_t g_gatt_db_table; + +typedef enum +{ + BLE_INVALID_ATTR_HDL = 0x0000, + BLE_GAPS_DECL_HDL = 0x0001, + BLE_GAPS_DEV_NAME_DECL_HDL = 0x0002, + BLE_GAPS_DEV_NAME_VAL_HDL = 0x0003, + BLE_GAPS_APPEARANCE_DECL_HDL = 0x0004, + BLE_GAPS_APPEARANCE_VAL_HDL = 0x0005, + BLE_GAPS_PER_PREF_CONN_PARAM_DECL_HDL = 0x0006, + BLE_GAPS_PER_PREF_CONN_PARAM_VAL_HDL = 0x0007, + BLE_GAPS_CENT_ADDR_RSLV_DECL_HDL = 0x0008, + BLE_GAPS_CENT_ADDR_RSLV_VAL_HDL = 0x0009, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_DECL_HDL = 0x000A, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_VAL_HDL = 0x000B, + BLE_GATS_DECL_HDL = 0x000C, + BLE_GATS_SERV_CHGED_DECL_HDL = 0x000D, + BLE_GATS_SERV_CHGED_VAL_HDL = 0x000E, + BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL = 0x000F, + BLE_LSS_DECL_HDL = 0x0010, + BLE_LSS_SWITCH_STATE_DECL_HDL = 0x0011, + BLE_LSS_SWITCH_STATE_VAL_HDL = 0x0012, + BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL = 0x0013, + BLE_LSS_BLINK_RATE_DECL_HDL = 0x0014, + BLE_LSS_BLINK_RATE_VAL_HDL = 0x0015, +} e_ble_attr_hdl_t; + +#define BLE_GAPS_DEV_NAME_LEN (128) +#define BLE_GAPS_APPEARANCE_LEN (2) +#define BLE_GAPS_PER_PREF_CONN_PARAM_LEN (8) +#define BLE_GAPS_CENT_ADDR_RSLV_LEN (1) +#define BLE_GAPS_RSLV_PRIV_ADDR_ONLY_LEN (1) +#define BLE_GATS_SERV_CHGED_LEN (4) +#define BLE_GATS_SERV_CHGED_CLI_CNFG_LEN (2) +#define BLE_LSS_SWITCH_STATE_LEN (1) +#define BLE_LSS_SWITCH_STATE_CLI_CNFG_LEN (2) +#define BLE_LSS_BLINK_RATE_LEN (1) + +#endif /* GATT_DB_H */ \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h new file mode 100644 index 0000000000..44259dc968 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef R_BLE_PROFILE_CMN_H +#define R_BLE_PROFILE_CMN_H + +#ifdef ENABLE_PROFILE_UT_TEST +#define UT_MOCK(name) __mock_ ## name +#else +#define UT_MOCK(name) name +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array)\ + (sizeof(array) / sizeof(array[0])) +#endif + +/** + * Packing Macros. + * + * Syntax: BT_PACK___BYTE + * + * Usage: Based on the endian-ness defined for each protocol/profile layer, + * appropriate packing macros to be used by each layer. + * + * Example: HCI is defined as little endian protocol, + * so if HCI defines HCI_PACK_2_BYTE for packing a parameter of size 2 byte, + * that shall be mapped to BT_PACK_LE_2_BYTE + * + * By default both the packing and unpaking macros uses pointer to + * a single or multi-octet variable which to be packed to or unpacked from + * a buffer (unsinged character array). + * + * For the packing macro, another variation is available, + * where the single or multi-octet variable itself is used (not its pointer). + * + * Syntax: BT_PACK___BYTE_VAL + */ +/* Little Endian Packing Macros */ +#ifndef BT_PACK_LE_1_BYTE +#define BT_PACK_LE_1_BYTE(dst, src) \ + { \ + uint8_t val; \ + val = (uint8_t)(*(src)); \ + BT_PACK_LE_1_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_1_BYTE_VAL +#define BT_PACK_LE_1_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (src); +#endif + +#ifndef BT_PACK_LE_2_BYTE +#define BT_PACK_LE_2_BYTE(dst, src) \ + { \ + uint16_t val; \ + val = (uint16_t)(*(src)); \ + BT_PACK_LE_2_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_2_BYTE_VAL +#define BT_PACK_LE_2_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src); \ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8); +#endif + +#ifndef BT_PACK_LE_3_BYTE +#define BT_PACK_LE_3_BYTE(dst, src) \ + { \ + uint32_t val; \ + val = (uint32_t)(*(src)); \ + BT_PACK_LE_3_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_3_BYTE_VAL +#define BT_PACK_LE_3_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src);\ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8);\ + *((uint8_t *)(dst) + 2) = (uint8_t)((src) >> 16); +#endif + +#ifndef BT_PACK_LE_4_BYTE +#define BT_PACK_LE_4_BYTE(dst, src) \ + { \ + uint32_t val; \ + val = (uint32_t)(*(src)); \ + BT_PACK_LE_4_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_4_BYTE_VAL +#define BT_PACK_LE_4_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src);\ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8);\ + *((uint8_t *)(dst) + 2) = (uint8_t)((src) >> 16);\ + *((uint8_t *)(dst) + 3) = (uint8_t)((src) >> 24); + +/* Update based on 64 Bit, 128 Bit Data Types */ +#endif + +#ifndef BT_PACK_LE_8_BYTE +#define BT_PACK_LE_8_BYTE(dst,val)\ + memcpy ((dst), (val), 8) +#endif + +#ifndef BT_PACK_LE_16_BYTE +#define BT_PACK_LE_16_BYTE(dst,val)\ + memcpy ((dst), (val), 16) +#endif + +#ifndef BT_PACK_LE_N_BYTE +#define BT_PACK_LE_N_BYTE(dst,val,n)\ + memcpy ((dst), (val), (n)) +#endif + +/** + * Unpacking Macros. + * + * Syntax: BT_UNPACK___BYTE + * + * Usage: Based on the endian-ness defined for each protocol/profile layer, + * appropriate unpacking macros to be used by each layer. + * + * Example: HCI is defined as little endian protocol, + * so if HCI defines HCI_UNPACK_4_BYTE for unpacking a parameter of size 4 byte, + * that shall be mapped to BT_UNPACK_LE_4_BYTE + */ +/* Little Endian Unpacking Macros */ +#ifndef BT_UNPACK_LE_1_BYTE +#define BT_UNPACK_LE_1_BYTE(dst,src)\ + *((uint8_t *)(dst)) = (uint8_t)(*((uint8_t *)(src))); +#endif + +#ifndef BT_UNPACK_LE_2_BYTE +#define BT_UNPACK_LE_2_BYTE(dst,src)\ + *((uint16_t *)(dst)) = (uint16_t)( \ + (((uint16_t)(*((src) + 0))) << 0) | \ + (((uint16_t)(*((src) + 1))) << 8) \ + ); +#endif + +#ifndef BT_UNPACK_LE_3_BYTE +#define BT_UNPACK_LE_3_BYTE(dst,src)\ + *((uint32_t *)(dst)) = (uint32_t)( \ + (((uint32_t)(*((src) + 0))) << 0) | \ + (((uint32_t)(*((src) + 1))) << 8) | \ + (((uint32_t)(*((src) + 2))) << 16) \ + ); +#endif + +#ifndef BT_UNPACK_LE_4_BYTE +#define BT_UNPACK_LE_4_BYTE(dst,src)\ + *((uint32_t *)(dst)) = (uint32_t)( \ + (((uint32_t)(*((src) + 0))) << 0) | \ + (((uint32_t)(*((src) + 1))) << 8) | \ + (((uint32_t)(*((src) + 2))) << 16) | \ + (((uint32_t)(*((src) + 3))) << 24) \ + ); +#endif + +/* Update based on 64 Bit, 128 Bit Data Types */ +#ifndef BT_UNPACK_LE_8_BYTE +#define BT_UNPACK_LE_8_BYTE(dst,src)\ + memcpy ((dst), (src), 8) +#endif + +#ifndef BT_UNPACK_LE_16_BYTE +#define BT_UNPACK_LE_16_BYTE(dst,src)\ + memcpy ((dst), (src), 16) +#endif + +#ifndef BT_UNPACK_LE_N_BYTE +#define BT_UNPACK_LE_N_BYTE(dst,src,n)\ + memcpy ((dst), (src), (n)) +#endif + +#ifndef MAX +#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +#endif + +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn Profile Common Library + * @{ + * @ingroup app_lib + * @brief Profile Common Library + * @details This library provides APIs to encode/decode default type and data types. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +/** @defgroup profile_cmn_struct Structures + * @{ + * @brief Structure definition + */ +/*******************************************************************************************************************//** + * @brief IEEE 11073 FLOAT type. +***********************************************************************************************************************/ +typedef struct { + int8_t exponent; /**< 8-bit exponent to base 10 */ + int32_t mantissa; /**< 24-bit mantissa */ +} st_ble_ieee11073_float_t; + +/*******************************************************************************************************************//** + * @brief IEEE 11073 short FLOAT type. +***********************************************************************************************************************/ +typedef struct { + int8_t exponent; /**< 4-bit exponent to base 10 */ + int16_t mantissa; /**< 12-bit mantissa */ +} st_ble_ieee11073_sfloat_t; + +/*******************************************************************************************************************//** + * @brief Date Time characteristic parameters. +***********************************************************************************************************************/ +typedef struct { + uint16_t year; /**< Year */ + uint8_t month; /**< Month */ + uint8_t day; /**< Day */ + uint8_t hours; /**< Hours */ + uint8_t minutes; /**< Minutes */ + uint8_t seconds; /**< Seconds */ +} st_ble_date_time_t; +/*@}*/ + +#endif /* R_BLE_PROFILE_CMN_H */ +/*@}*/ \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c new file mode 100644 index 0000000000..0fc6e5ba25 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c @@ -0,0 +1,267 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include + +#include "r_ble_serv_common.h" + +ble_status_t decode_8bit(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint8_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = p_gatt_value->p_value[0]; + + return BLE_SUCCESS; +} + +ble_status_t encode_8bit(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint8_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = *p_app_value; + + return BLE_SUCCESS; +} + +ble_status_t decode_16bit(uint16_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint16_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint16_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8)); + + return BLE_SUCCESS; +} + +ble_status_t encode_16bit(const uint16_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint16_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = (uint8_t)((*p_app_value) & 0xFF); + p_gatt_value->p_value[1] = (uint8_t)(((*p_app_value) >> 8) & 0xFF); + + return BLE_SUCCESS; +} + +ble_status_t decode_24bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != 3) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint32_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8) | + (p_gatt_value->p_value[2] << 16)); + + return BLE_SUCCESS; +} + +ble_status_t decode_32bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint32_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint32_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8) | + (p_gatt_value->p_value[2] << 16) | (p_gatt_value->p_value[3] << 24)); + + return BLE_SUCCESS; +} + +ble_status_t encode_24bit(const uint32_t * p_app_value, st_ble_gatt_value_t * p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < 3) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = *p_app_value & 0xFF; + p_gatt_value->p_value[1] = (*p_app_value >> 8) & 0xFF; + p_gatt_value->p_value[2] = (*p_app_value >> 16) & 0xFF; + p_gatt_value->value_len = 3; + + return BLE_SUCCESS; +} + +ble_status_t encode_32bit(const uint32_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint32_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = (uint8_t)(*p_app_value & 0xFF); + p_gatt_value->p_value[1] = (uint8_t)((*p_app_value >> 8) & 0xFF); + p_gatt_value->p_value[2] = (uint8_t)((*p_app_value >> 16) & 0xFF); + p_gatt_value->p_value[3] = (uint8_t)((*p_app_value >> 24) & 0xFF); + + return BLE_SUCCESS; +} + +ble_status_t decode_allcopy(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + memcpy(p_app_value, p_gatt_value->p_value, p_gatt_value->value_len); + + return BLE_SUCCESS; +} + +ble_status_t encode_allcopy(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + memcpy(p_gatt_value->p_value, p_app_value, p_gatt_value->value_len); + + return BLE_SUCCESS; + +} + +ble_status_t decode_st_ble_seq_data_t(st_ble_seq_data_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + p_app_value->data = p_gatt_value->p_value; + p_app_value->len = p_gatt_value->value_len; + return BLE_SUCCESS; +} + +ble_status_t encode_st_ble_seq_data_t(const st_ble_seq_data_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (p_app_value->len > p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memcpy(p_gatt_value->p_value, p_app_value->data, p_app_value->len); + + /* for characteristic size */ + p_gatt_value->value_len = p_app_value->len; + + return BLE_SUCCESS; +} + +uint8_t pack_st_ble_ieee11073_sfloat_t(uint8_t *p_dst, const st_ble_ieee11073_sfloat_t *p_src) +{ + uint8_t pos = 0; + uint16_t sfloat = (uint16_t)((p_src->mantissa & 0x0FFF) | (p_src->exponent << 12)); + + p_dst[pos++] = (uint8_t)(sfloat & 0xFF); + p_dst[pos++] = (uint8_t)((sfloat >> 8) & 0xFF); + + return pos; +} + +uint8_t unpack_st_ble_ieee11073_sfloat_t(st_ble_ieee11073_sfloat_t *p_dst, const uint8_t *p_src) +{ + p_dst->mantissa = (int16_t)(p_src[0] | ((p_src[1] & 0x0F) << 8)); + p_dst->exponent = (int8_t)(p_src[1] >> 4); + + if (p_dst->exponent & 0x08) + { + p_dst->exponent = (int8_t)(p_dst->exponent | 0xF0); + } + + return 2; +} + +uint8_t pack_st_ble_date_time_t(uint8_t *p_dst, const st_ble_date_time_t *p_src) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_dst[pos], &p_src->year); + pos += 2; + p_dst[pos++] = p_src->month; + p_dst[pos++] = p_src->day; + p_dst[pos++] = p_src->hours; + p_dst[pos++] = p_src->minutes; + p_dst[pos++] = p_src->seconds; + + return (uint8_t)pos; +} + +uint8_t unpack_st_ble_date_time_t(st_ble_date_time_t *p_dst, const uint8_t *p_src) +{ + uint32_t pos = 0; + + BT_UNPACK_LE_2_BYTE(&p_dst->year, &p_src[pos]); + pos += 2; + p_dst->month = p_src[pos++]; + p_dst->day = p_src[pos++]; + p_dst->hours = p_src[pos++]; + p_dst->minutes = p_src[pos++]; + p_dst->seconds = p_src[pos++]; + + return (uint8_t)pos; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h new file mode 100644 index 0000000000..ffff3fe868 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h @@ -0,0 +1,329 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn Profile Common Library + * @{ + * @ingroup app_lib + * @brief Profile Common Library + * @details This library provides APIs to encode/decode default type and data types. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +#ifndef R_BLE_SERV_COMMON_H +#define R_BLE_SERV_COMMON_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#include "r_ble_rx23w_if.h" +#else +/*RA4W*/ +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#endif + +#include "r_ble_profile_cmn.h" + +/** @defgroup profile_cmn_macro Macros + * @{ + * @brief Macro definition + */ +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** + * @def BLE_PRF_MAX_NUM_OF_SERVS + * @brief Maximum Number of Services. + */ +#define BLE_PRF_MAX_NUM_OF_SERVS (10) + +/** + * @def BLE_SERV_CLI_CNFG_LEN + * @brief Length of Client Characteristic Configuration descriptor. + */ +#define BLE_SERV_CLI_CNFG_LEN (2) + +/** + * @def BLE_SERV_SER_CNFG_LEN + * @brief Length of Server Characteristic Configuration descriptor. + */ +#define BLE_SERV_SER_CNFG_LEN (2) + +/** + * @def BLE_SERV_CLI_CNFG_UUID + * @brief UUID of Client Characteristic Configuration descriptor. + */ +#define BLE_SERV_CLI_CNFG_UUID (0x2902) + +/** + * @def BLE_SERV_SER_CNFG_UUID + * @brief UUID of Server Characteristic Configuration descriptor. + */ +#define BLE_SERV_SER_CNFG_UUID (0x2903) + +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#define BLE_PRF_MTU_SIZE (BLE_CFG_GATT_MTU_SIZE) +#define BLE_PRF_CONN_MAX (BLE_CFG_RF_CONN_MAX) +#else +/*RA4W*/ +#define BLE_PRF_MTU_SIZE (BLE_ABS_CFG_GATT_MTU_SIZE) +#define BLE_PRF_CONN_MAX (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) +#endif +/*@}*/ + +/** @defgroup profile_cmn_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_seq_data_t + * @brief st_ble_seq_data_t is value field for variable length. + **********************************************************************************************************************/ +typedef struct { + /** + * @brief Data value. + */ + uint8_t *data; + /** + * @brief Data length. + */ + uint16_t len; +} st_ble_seq_data_t; +/*@}*/ + +/** @defgroup profile_cmn_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Decode data value for 8bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_8bit(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 8bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_8bit(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 16bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_16bit(uint16_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 16bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_16bit(const uint16_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 32bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_32bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 32bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_32bit(const uint32_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 24bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_24bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 24bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_24bit(const uint32_t * p_app_value, st_ble_gatt_value_t * p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 8bit array. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_allcopy(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 8bit array. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_allcopy(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for value type st_ble_seq_data_t. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_st_ble_seq_data_t(st_ble_seq_data_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for value type st_ble_seq_data_t. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_st_ble_seq_data_t(const st_ble_seq_data_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Pack value type of st_ble_ieee11073_sfloat_t to GATT DB. + * @param[out] p_dst GATT database value of characteristic or descriptor. + * @param[in] p_src Application value field which is st_ble_ieee11073_sfloat_t type. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t pack_st_ble_ieee11073_sfloat_t(uint8_t *p_dst, const st_ble_ieee11073_sfloat_t *p_src); + +/******************************************************************************************************************//** + * @brief Unpack value type of st_ble_ieee11073_sfloat_t from GATT DB. + * @param[out] p_dst Application value field which is st_ble_ieee11073_sfloat_t type. + * @param[in] p_src GATT database value of characteristic or descriptor. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t unpack_st_ble_ieee11073_sfloat_t(st_ble_ieee11073_sfloat_t *p_dst, const uint8_t *p_src); + +/******************************************************************************************************************//** + * @brief Pack value type of st_ble_date_time_t to GATT DB. + * @param[out] p_dst GATT database value of characteristic or descriptor. + * @param[in] p_src Application value field which is st_ble_date_time_t type. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t pack_st_ble_date_time_t(uint8_t *p_dst, const st_ble_date_time_t *p_src); + +/******************************************************************************************************************//** + * @brief Unpack value type of st_ble_date_time_t from GATT DB. + * @param[out] p_dst Application value field which is st_ble_date_time_t type. + * @param[in] p_src GATT database value of characteristic or descriptor. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t unpack_st_ble_date_time_t(st_ble_date_time_t *p_dst, const uint8_t *p_src); +/*@}*/ + +/** @defgroup profile_cmn_macro Macros + * @{ + * @brief Macro definition + */ +/** + * @def decode_uint8_t + * @brief Function macro for decoding uint8_t + */ +#define decode_uint8_t decode_8bit + +/** + * @def encode_uint8_t + * @brief Function macro for encoding uint8_t + */ +#define encode_uint8_t encode_8bit + +/** + * @def decode_int8_t + * @brief Function macro for decoding int8_t + */ +#define decode_int8_t decode_8bit + +/** + * @def encode_int8_t + * @brief Function macro for encoding int8_t + */ +#define encode_int8_t encode_8bit + +/** + * @def decode_uint16_t + * @brief Function macro for decoding uint16_t + */ +#define decode_uint16_t decode_16bit + +/** + * @def encode_uint16_t + * @brief Function macro for encoding uint16_t + */ +#define encode_uint16_t encode_16bit + +/** + * @def decode_int16_t + * @brief Function macro for decoding int16_t + */ +#define decode_int16_t decode_16bit + +/** + * @def encode_int16_t + * @brief Function macro for encoding int16_t + */ +#define encode_int16_t encode_16bit + +/** + * @def decode_uint32_t + * @brief Function macro for decoding uint32_t + */ +#define decode_uint32_t decode_32bit + +/** + * @def encode_uint32_t + * @brief Function macro for encoding uint32_t + */ +#define encode_uint32_t encode_32bit + +/** + * @def decode_int32_t + * @brief Function macro for decoding int32_t + */ +#define decode_int32_t decode_32bit + +/** + * @def encode_int32_t + * @brief Function macro for encoding int32_t + */ +#define encode_int32_t encode_32bit +/*@}*/ + +#endif /* R_BLE_SERV_COMMON_H */ +/*@}*/ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c new file mode 100644 index 0000000000..1937ffaf2a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c @@ -0,0 +1,1102 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include +#include "r_ble_servc_if.h" +#include "discovery/r_ble_disc.h" + +typedef struct { + st_ble_dev_addr_t bd_addr; + uint16_t conn_hdl; + uint8_t conn_idx; + + /* Used for Long Read */ + uint16_t read_attr_hdl; + uint8_t *p_read_buf; + uint16_t read_buf_pos; + + /* Used for Long Write */ + uint16_t write_attr_hdl; +} st_ble_conn_info_t; + +static st_ble_conn_info_t gs_conn_info[BLE_SERVC_MAX_NUM_OF_SAVED]; +static const st_ble_servc_info_t *gs_clients[BLE_SERVC_MAX_NUM_OF_CLIENTS]; +static uint8_t gs_num_of_clients; + +static uint8_t find_conn_idx_from_bd_addr(const st_ble_dev_addr_t *p_addr) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if ((gs_conn_info[i].bd_addr.type == p_addr->type) && + (0 == memcmp(gs_conn_info[i].bd_addr.addr, p_addr->addr, BLE_BD_ADDR_LEN))) + { + return i; + } + } + + return 0xFF; +} + +static uint8_t find_conn_idx_from_conn_hdl(uint16_t conn_hdl) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if (gs_conn_info[i].conn_hdl == conn_hdl) + { + return i; + } + } + + return 0xFF; +} + +static void set_conn_idx(uint16_t conn_hdl, const st_ble_dev_addr_t *p_addr) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + /* If we already have the peer attr hdls, use it. */ + if ((gs_conn_info[i].bd_addr.type == p_addr->type) && + (0 == memcmp(gs_conn_info[i].bd_addr.addr, p_addr->addr, BLE_BD_ADDR_LEN))) + { + gs_conn_info[i].conn_hdl = conn_hdl; + return; + } + } + + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if (BLE_GAP_INVALID_CONN_HDL == gs_conn_info[i].conn_hdl) + { + memcpy(&gs_conn_info[i].bd_addr, p_addr, sizeof(gs_conn_info[i].bd_addr)); + gs_conn_info[i].conn_hdl = conn_hdl; + break; + } + } +} + +static void clear_conn_idx(uint16_t conn_hdl) +{ + uint8_t conn_idx; + + conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + if (0xFF != conn_idx) + { + gs_conn_info[conn_idx].conn_hdl = BLE_GAP_INVALID_CONN_HDL; + } +} + +static void find_attr(uint8_t conn_idx, + uint16_t attr_hdl, + const st_ble_servc_info_t **pp_client, + const st_ble_servc_char_info_t **pp_char) +{ + for (uint8_t s = 0; s < gs_num_of_clients; s++) + { + for (uint8_t c = 0; c < gs_clients[s]->num_of_chars; c++) + { + if ((gs_clients[s]->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl <= attr_hdl) && + (gs_clients[s]->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl >= attr_hdl)) + { + *pp_client = gs_clients[s]; + *pp_char = gs_clients[s]->pp_chars[c]; + } + } + } +} + +static void read_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t *p_value, ble_status_t result) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + /* Characteristic */ + if (attr_hdl == p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (BLE_SUCCESS == result) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + ret = p_attr->decode(p_app_value, p_value); + + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, conn_hdl, ret, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + else + { + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + } + /* Descriptor */ + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (attr_hdl == p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (BLE_SUCCESS == result) + { + ble_status_t ret; + uint8_t *p_app_value; + + p_app_value = malloc(p_attr->pp_descs[d]->app_size); + memset(p_app_value, 0x00, p_attr->pp_descs[d]->app_size); + + ret = p_attr->pp_descs[d]->decode(p_app_value, p_value); + + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(&p_attr->pp_descs[d], conn_hdl, ret, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_attr->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + else + { + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(&p_attr->pp_descs[d], conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + break; + } + } + } + } +} + +static void write_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, ble_status_t result) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + /* Characteristics */ + if (attr_hdl == p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (NULL != p_attr->write_rsp_cb) + { + p_attr->write_rsp_cb(p_attr, conn_hdl, result); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), result, &evt_data); + } + } + /* Descriptors */ + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (attr_hdl == p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (NULL != p_attr->pp_descs[d]->write_rsp_cb) + { + p_attr->pp_descs[d]->write_rsp_cb(&p_attr->pp_descs[d], conn_hdl, result); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), result, &evt_data); + } + break; + } + } + } + } +} + +void R_BLE_SERVC_GattcCb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t * p_data) +{ + switch (type) + { + case BLE_GATTC_EVENT_CONN_IND: + { + st_ble_gattc_conn_evt_t *p_conn_evt_param = + (st_ble_gattc_conn_evt_t *)p_data->p_param; + + set_conn_idx(p_data->conn_hdl, p_conn_evt_param->p_addr); + } break; + + case BLE_GATTC_EVENT_DISCONN_IND: + { + clear_conn_idx(p_data->conn_hdl); + } break; + + case BLE_GATTC_EVENT_CHAR_READ_RSP: + { + st_ble_gattc_rd_char_evt_t *p_rd_char_evt_param = + (st_ble_gattc_rd_char_evt_t *)p_data->p_param; + + read_evt_handler(p_data->conn_hdl, + p_rd_char_evt_param->read_data.attr_hdl, + &p_rd_char_evt_param->read_data.value, + result); + } break; + + case BLE_GATTC_EVENT_CHAR_PART_READ_RSP: + { + st_ble_gattc_rd_char_evt_t *p_rd_char_evt_param = + (st_ble_gattc_rd_char_evt_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_rd_char_evt_param->read_data.attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + if (p_rd_char_evt_param->read_data.attr_hdl == + p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (BLE_SUCCESS == result) + { + if (NULL == gs_conn_info[conn_idx].p_read_buf) + { + gs_conn_info[conn_idx].p_read_buf = malloc(p_attr->db_size); + memset(gs_conn_info[conn_idx].p_read_buf, 0x00, p_attr->db_size); + + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = p_rd_char_evt_param->read_data.attr_hdl; + } + + memcpy(&gs_conn_info[conn_idx].p_read_buf[gs_conn_info[conn_idx].read_buf_pos], + p_rd_char_evt_param->read_data.value.p_value, + p_rd_char_evt_param->read_data.value.value_len); + gs_conn_info[conn_idx].read_buf_pos += p_rd_char_evt_param->read_data.value.value_len; + } + else + { + if (NULL != gs_conn_info[conn_idx].p_read_buf) + { + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } + + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, p_data->conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + } + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (p_rd_char_evt_param->read_data.attr_hdl == + p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (BLE_SUCCESS == result) + { + if (NULL == gs_conn_info[conn_idx].p_read_buf) + { + gs_conn_info[conn_idx].p_read_buf = malloc(p_attr->pp_descs[d]->db_size); + memset(gs_conn_info[conn_idx].p_read_buf, 0x00, p_attr->pp_descs[d]->db_size); + + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = p_rd_char_evt_param->read_data.attr_hdl; + } + + memcpy(&gs_conn_info[conn_idx].p_read_buf[gs_conn_info[conn_idx].read_buf_pos], + p_rd_char_evt_param->read_data.value.p_value, + p_rd_char_evt_param->read_data.value.value_len); + gs_conn_info[conn_idx].read_buf_pos += p_rd_char_evt_param->read_data.value.value_len; + } + else + { + if (NULL != gs_conn_info[conn_idx].p_read_buf) + { + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } + + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(p_attr, p_data->conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->pp_descs[d]->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + break; + } + } + } + } + } break; + + case BLE_GATTC_EVENT_LONG_CHAR_READ_COMP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + st_ble_gatt_value_t value = { + .p_value = gs_conn_info[conn_idx].p_read_buf, + .value_len = gs_conn_info[conn_idx].read_buf_pos, + }; + + read_evt_handler(p_data->conn_hdl, + gs_conn_info[conn_idx].read_attr_hdl, + &value, + result); + + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } break; + + case BLE_GATTC_EVENT_CHAR_WRITE_RSP: + { + st_ble_gattc_wr_char_evt_t *p_wr_char_evt_param = + (st_ble_gattc_wr_char_evt_t *)p_data->p_param; + write_evt_handler(p_data->conn_hdl, p_wr_char_evt_param->value_hdl, result); + } break; + + case BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + st_ble_gattc_char_part_wr_evt_t *p_char_part_wr_param = + (st_ble_gattc_char_part_wr_evt_t *)p_data->p_param; + + gs_conn_info[conn_idx].write_attr_hdl = p_char_part_wr_param->write_data.attr_hdl; + } break; + + case BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + write_evt_handler(p_data->conn_hdl, gs_conn_info[conn_idx].write_attr_hdl, result); + } break; + + case BLE_GATTC_EVENT_HDL_VAL_NTF: + { + st_ble_gatt_hdl_value_pair_t *p_hdl_value_pair_param = + (st_ble_gatt_hdl_value_pair_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_hdl_value_pair_param->attr_hdl, &p_client, &p_attr); + + if ((NULL != p_attr) && (NULL != p_attr->decode)) + { + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + p_attr->decode(p_app_value, &p_hdl_value_pair_param->value); + + if (NULL != p_attr->hdl_val_ntf_cb) + { + p_attr->hdl_val_ntf_cb(p_attr, p_data->conn_hdl, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_HDL_VAL_NTF), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTC_EVENT_HDL_VAL_IND: + { + st_ble_gatt_hdl_value_pair_t *p_hdl_value_pair_param = + (st_ble_gatt_hdl_value_pair_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_hdl_value_pair_param->attr_hdl, &p_client, &p_attr); + + if ((NULL != p_attr) && (NULL != p_attr->decode)) + { + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + p_attr->decode(p_app_value, &p_hdl_value_pair_param->value); + + if (NULL != p_attr->hdl_val_ind_cb) + { + p_attr->hdl_val_ind_cb(p_attr, p_data->conn_hdl, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_HDL_VAL_IND), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTC_EVENT_ERROR_RSP: + { + st_ble_gattc_err_rsp_evt_t *p_err_rsp_evt_param = + (st_ble_gattc_err_rsp_evt_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_err_rsp_evt_param->attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + switch (p_err_rsp_evt_param->op_code) + { + case 0x0A: /* Read Request */ + { + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, p_data->conn_hdl, p_err_rsp_evt_param->rsp_code, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 2, + .p_param = &p_err_rsp_evt_param->attr_hdl, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), p_err_rsp_evt_param->rsp_code, &evt_data); + } + } break; + + case 0x12: /* Write Request) */ + { + if (NULL != p_attr->write_rsp_cb) + { + p_attr->write_rsp_cb(p_attr, p_data->conn_hdl, p_err_rsp_evt_param->rsp_code); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 2, + .p_param = &p_err_rsp_evt_param->attr_hdl, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), p_err_rsp_evt_param->rsp_code, &evt_data); + } + } break; + } + } + } break; + + case BLE_GATTC_EVENT_INVALID: + { + } break; + + case BLE_GATTC_EVENT_EX_MTU_RSP: + case BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP: + case BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP: + case BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP: + case BLE_GATTC_EVENT_RELIABLE_WRITES_COMP: + default: + { + break; + } + } +} + +ble_status_t R_BLE_SERVC_Init(void) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + gs_conn_info[i].conn_hdl = BLE_GAP_INVALID_CONN_HDL; + } + gs_num_of_clients = 0; + return BLE_SUCCESS; +} + +ble_status_t R_BLE_SERVC_RegisterClient(const st_ble_servc_info_t *p_info) +{ + ble_status_t ret; + if( BLE_SERVC_MAX_NUM_OF_CLIENTS > gs_num_of_clients ) + { + gs_clients[gs_num_of_clients++] = p_info; + ret = BLE_SUCCESS; + } + else + { + ret = BLE_ERR_CONTEXT_FULL; + } + + return ret; +} + +ble_status_t R_BLE_SERVC_ReadChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl) +{ + ble_status_t ret; + + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 3)) + { + ret = R_BLE_GATTC_ReadChar(conn_hdl, (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl+1)); + } + else + { + ret = R_BLE_GATTC_ReadLongChar(conn_hdl, (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl+1), 0); + } + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl + 1), + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_data.value.value_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteCmdChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl + 1), + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + ret = R_BLE_GATTC_WriteCharWithoutRsp(conn_hdl, &write_data); + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_ReadDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl) +{ + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 1)) + { + return R_BLE_GATTC_ReadChar(conn_hdl, p_attr->p_attr_hdls[conn_idx]); + } + else + { + return R_BLE_GATTC_ReadLongChar(conn_hdl, p_attr->p_attr_hdls[conn_idx], 0); + } +} + +ble_status_t R_BLE_SERVC_ReadDesc_with_Type(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, int32_t type) +{ + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (0 == type) + { + return R_BLE_GATTC_ReadChar(conn_hdl, p_attr->p_attr_hdls[conn_idx]); + } + else + { + return R_BLE_GATTC_ReadLongChar(conn_hdl, p_attr->p_attr_hdls[conn_idx], 0); + } +} + + + +ble_status_t R_BLE_SERVC_WriteDesc( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteDesc2( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_data.value.value_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + + + +ble_status_t R_BLE_SERVC_WriteDesc_with_Size( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const st_ble_seq_data_t *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + uint16_t write_len; + write_len = (p_app_value->len < p_attr->db_size) ? p_app_value->len : p_attr->db_size; + + p_byte_value = malloc(write_len); + memset(p_byte_value, 0x00, write_len); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = write_len, + }; + + //ret = p_attr->encode(p_app_value, &gatt_value); + ret = p_attr->encode(p_app_value->data, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + + + + +void R_BLE_SERVC_ServDiscCb(const st_ble_servc_info_t *p_info, uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + /* unused arg */ + (void)serv_idx; + + if (0xFF == conn_idx) + { + return; + } + + switch (type) + { + case BLE_DISC_PRIM_SERV_FOUND: + { + st_disc_serv_param_t *p_serv_param = (st_disc_serv_param_t *)p_param; + memcpy(&p_info->p_attr_hdls[conn_idx], &p_serv_param->value.serv_16.range, sizeof(p_info->p_attr_hdls[conn_idx])); + } break; + + case BLE_DISC_CHAR_FOUND: + { + st_disc_char_param_t *p_char_param = (st_disc_char_param_t *)p_param; + + for (uint8_t c = 0; c < p_info->num_of_chars; c++) + { + if ((BLE_GATT_16_BIT_UUID_FORMAT == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_type == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_16 == p_char_param->value.char_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl)) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl = p_char_param->value.char_16.decl_hdl; + + if (p_char_param->num_of_descs > 0) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = + p_char_param->descs[p_char_param->num_of_descs-1].value.desc_16.desc_hdl; + } + else + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = p_char_param->value.char_16.value_hdl; + } + + for (uint8_t d = 0; d < p_char_param->num_of_descs; d++) + { + for (uint8_t dd = 0; dd < p_info->pp_chars[c]->num_of_descs; dd++) + { + if ((p_info->pp_chars[c]->pp_descs[dd]->uuid_16 == p_char_param->descs[d].value.desc_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx])) + { + p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx] = p_char_param->descs[d].value.desc_16.desc_hdl; + break; + } + } + } + break; + } + else if ((BLE_GATT_128_BIT_UUID_FORMAT == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_type == p_char_param->uuid_type) && + (0 == memcmp(p_info->pp_chars[c]->uuid_128, p_char_param->value.char_128.uuid_128, 0x10)) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl)) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl = p_char_param->value.char_128.decl_hdl; + + if (p_char_param->num_of_descs > 0) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = + p_char_param->descs[p_char_param->num_of_descs-1].value.desc_16.desc_hdl; + } + else + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = p_char_param->value.char_128.value_hdl; + } + + for (uint8_t d = 0; d < p_char_param->num_of_descs; d++) + { + for (uint8_t dd = 0; dd < p_info->pp_chars[c]->num_of_descs; dd++) + { + if ((p_info->pp_chars[c]->pp_descs[dd]->uuid_16 == p_char_param->descs[d].value.desc_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx])) + { + p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx] = p_char_param->descs[d].value.desc_16.desc_hdl; + break; + } + } + } + break; + + } + } + } break; + + default: + { + /* Do nothing. */ + } break; + } +} + +uint8_t R_BLE_SERVC_GetConnIdx(const st_ble_dev_addr_t *p_addr) +{ + return find_conn_idx_from_bd_addr(p_addr); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h new file mode 100644 index 0000000000..8757faf490 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h @@ -0,0 +1,354 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn_cli Profile Common Client Library + * @{ + * @ingroup profile_cmn + * @brief Profile Common Client Library Library + * @details This library provides APIs to implement GATT profile client. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +#include "r_ble_serv_common.h" + +#ifndef R_BLE_SERVC_IF_H +#define R_BLE_SERVC_IF_H + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** @defgroup profile_cmn_cli_macro Macros + * @{ + * @brief Macro definition + */ + +/** + * @def BLE_SERVC_MAX_NUM_OF_SAVED + * @brief Max number of connection to be saved. + */ +#define BLE_SERVC_MAX_NUM_OF_SAVED (BLE_PRF_CONN_MAX) + +/** + * @def BLE_SERVC_MAX_NUM_OF_CLIENTS + * @brief Max number of client service to be saved. + */ +#define BLE_SERVC_MAX_NUM_OF_CLIENTS (10) + +/* attr_idx:6bit, inst_idx:4bit, type_idx:1bit, evt_idx:5bit */ +/** + * @def BLE_SERVC_MULTI_ATTR_EVENT + * @brief Event type used in callback. This macro is used if same service is used. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] inst_idx Service index. 4bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVC_MULTI_ATTR_EVENT(attr_idx, inst_idx, evt_idx) ((uint16_t)((attr_idx << 10) | (inst_idx << 6) | (evt_idx << 0))) + +/** + * @def BLE_SERVC_ATTR_EVENT + * @brief Event type used in callback. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVC_ATTR_EVENT(attr_idx, evt_idx) BLE_SERVC_MULTI_ATTR_EVENT(attr_idx, 0, evt_idx) + +/** + * @enum e_ble_servc_event_t + * @brief Client callback events. + */ +typedef enum { + /** + * @brief Receive a write response. + */ + BLE_SERVC_WRITE_RSP, + /** + * @brief Receive a read response. + */ + BLE_SERVC_READ_RSP, + /** + * @brief Receive a notification. + */ + BLE_SERVC_HDL_VAL_NTF, + /** + * @brief Receive a indication. + */ + BLE_SERVC_HDL_VAL_IND, +} e_ble_servc_event_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servc_evt_data_t + * @brief st_ble_servc_evt_data_t includes connection handle and value for connection parameter. + **********************************************************************************************************************/ +typedef struct { + uint16_t conn_hdl; /**< Connection handle. */ + uint16_t param_len; /**< Event parameter length. */ + const void *p_param; /**< Event parameter.\n Value is set after decode function is called. */ +} st_ble_servc_evt_data_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_callback Callbacks + * @{ + * @brief Callback definition + */ +/*************************************************************************************************************//** + * @brief Callback invoked when write response received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write response. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_write_rsp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result); + +/*************************************************************************************************************//** + * @brief Callback invoked when read response received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of read response. + * @param[in] p_app_value Characteristic value or descriptor value of read response. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_read_rsp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when notification received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value of notification. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_hdl_val_ntf_t)(const void *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when indication received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value of indication. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_hdl_val_ind_t)(const void *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when events defined in service occurred. + * @param[in] type Event type of callback. Refer e_ble_XXX_event_t of each service. + * @param[in] result Result of event. + * @param[in] p_data Event data. +***********************************************************************************************************************/ +typedef void (*ble_servc_app_cb_t)(uint16_t type, ble_status_t result, st_ble_servc_evt_data_t *p_data); +/*@}*/ + +/** @defgroup profile_cmn_cli_func Functions + * @{ + * @brief Function definition + */ +/*************************************************************************************************************//** + * @brief Decode function. Convert data from GATT database value to application data value. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servc_attr_decode_t)(void *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/*************************************************************************************************************//** + * @brief Encode function. Convert data from application data value to GATT database value. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servc_attr_encode_t)(const void *p_app_value, st_ble_gatt_value_t *p_gatt_value); +/*@}*/ + +/** @defgroup profile_cmn_cli_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servc_desc_info_t + * @brief st_ble_servc_desc_info_t includes information about descriptor. + **********************************************************************************************************************/ +typedef struct { + uint16_t uuid_16; /**< 16bit UUID of descriptor. */ + const uint8_t *uuid_128; /**< 128bit UUID of descriptor. */ + uint8_t uuid_type; /**< Select from 16bit UUID or 128bit UUID.\n 128bit UUID should be used for custom service.\n 16bit UUID = BLE_GATT_16_BIT_UUID_FORMAT\n 128bit UUID = BLE_GATT_128_BIT_UUID_FORMAT */ + uint8_t desc_idx; /**< Index of descriptor. */ + uint8_t inst_idx; /**< Index used if same descriptor is set in one characteristic. */ + uint16_t *p_attr_hdls; /**< Attribute handle for each connection. */ + uint16_t app_size; /**< Descriptor value size used in application. */ + uint16_t db_size; /**< Descriptor value size used in GATT database. */ + ble_servc_attr_write_rsp_t write_rsp_cb; /**< Write response callback function. Set function if needed. */ + ble_servc_attr_read_rsp_t read_rsp_cb; /**< Read response callback function. Set function if needed. */ + ble_servc_attr_decode_t decode; /**< Decode function. */ + ble_servc_attr_encode_t encode; /**< Encode function. */ +} st_ble_servc_desc_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servc_char_info_t + * @brief st_ble_servc_char_info_t includes information about characteristic. + **********************************************************************************************************************/ +typedef struct { + uint16_t uuid_16; /**< 16bit UUID of characteristic*/ + const uint8_t *uuid_128; /**< 128bit UUID of characteristic*/ + uint8_t uuid_type; /**< Select from 16bit UUID or 128bit UUID.\n 128bit UUID should be used for custom service.\n 16bit UUID = BLE_GATT_16_BIT_UUID_FORMAT\n 128bit UUID = BLE_GATT_128_BIT_UUID_FORMAT */ + st_ble_gatt_hdl_range_t *p_attr_hdls; /**< Attribute handle range of characteristic. */ + uint8_t char_idx; /**< Index of characteristic. */ + uint8_t inst_idx; /**< Index used if same characteristic is set in one service. */ + uint16_t app_size; /**< Size of characteristic value in Application. */ + uint16_t db_size; /**< Size of characteristic value in GATT database. */ + const st_ble_servc_desc_info_t **pp_descs; /**< Set all descriptor information structure included in this characteristic. */ + uint8_t num_of_descs; /**< Number of descriptors included in this characteristic. */ + ble_servc_attr_write_rsp_t write_rsp_cb; /**< Write response callback function. Set function if needed. */ + ble_servc_attr_read_rsp_t read_rsp_cb; /**< Read response callback function. Set function if needed. */ + ble_servc_attr_hdl_val_ntf_t hdl_val_ntf_cb; /**< Notification callback function. Set function if needed. */ + ble_servc_attr_hdl_val_ind_t hdl_val_ind_cb; /**< Indication callback function. Set function if needed. */ + ble_servc_attr_decode_t decode; /**< Decode function. */ + ble_servc_attr_encode_t encode; /**< Encode function. */ +} st_ble_servc_char_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servc_info_t + * @brief st_ble_servc_info_t includes information about service. + **********************************************************************************************************************/ +typedef struct { + const st_ble_servc_char_info_t **pp_chars; /**< Set all characteristic information structure included in this service. */ + uint16_t num_of_chars; /**< Number of characteristics included in this service. */ + st_ble_gatt_hdl_range_t *p_attr_hdls; /**< Attribute handle range of service. */ + ble_servc_app_cb_t cb; /**< Service event callback function. */ +} st_ble_servc_info_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Initialize profile common client library. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_Init(void); + +/******************************************************************************************************************//** + * @brief Register client service to profile common client library. + * @param[in] p_info Client service to be registered. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_RegisterClient(const st_ble_servc_info_t *p_info); + +/******************************************************************************************************************//** + * @brief Callback function used for service discovery. + * @param[in] p_info Client server information structure to be discovered. + * @param[in] conn_hdl Connection handle. + * @param[in] serv_idx Index used if same service is included in one profile. + * @param[in] type Event type of discovery. + * @param[in] p_param Parameter of discovered information. + **********************************************************************************************************************/ +void R_BLE_SERVC_ServDiscCb(const st_ble_servc_info_t *p_info, uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param); + +/******************************************************************************************************************//** + * @brief Get connection handle from BD address. + * @param[in] p_addr BD address of connected device. + * @return connection handle. + **********************************************************************************************************************/ +uint8_t R_BLE_SERVC_GetConnIdx(const st_ble_dev_addr_t *p_addr); + +/******************************************************************************************************************//** + * @brief Send read request of characteristic value for read operation. + * @param[in] p_attr Characteristic sending read request. + * @param[in] conn_hdl Connection handle. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @brief Send write request of characteristic value for write operation. + * @param[in] p_attr Characteristic sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write command of characteristic value for write without request operation. + * @param[in] p_attr Characteristic sending write command. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write command. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteCmdChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send read request of descriptor value for read operation. + * @param[in] p_attr Descriptor sending read request. + * @param[in] conn_hdl Connection handle. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @brief Send read request of descriptor value for read operation or read long operation. + * @param[in] p_attr Descriptor sending read request. + * @param[in] conn_hdl Connection handle. + * @param[in] type Defines read operation or read long operation.\n 0 = read operation\n Other value = read long operation + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadDesc_with_Type(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, int32_t type); + +/******************************************************************************************************************//** + * @brief Send write request of descriptor value for write operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write request of variable descriptor value for write operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Data value and size to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc_with_Size(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const st_ble_seq_data_t *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write request of descriptor value for write without request operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc2(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Callback function used for GATT client events. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function to enable all client callback event included in profile. + **********************************************************************************************************************/ +void R_BLE_SERVC_GattcCb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t * p_data); +/*@}*/ + +#endif /* R_BLE_SERVC_IF_H */ +/* @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c new file mode 100644 index 0000000000..6ced9b9dcc --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c @@ -0,0 +1,738 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include +#include "r_ble_servs_if.h" + +static const st_ble_servs_info_t *gs_servs[BLE_PRF_MAX_NUM_OF_SERVS]; +static uint8_t gs_num_of_servs; + +static void find_attr(uint16_t attr_hdl, + const st_ble_servs_info_t **pp_serv, + const st_ble_servs_char_info_t **pp_char) +{ + for (uint8_t s = 0; s < gs_num_of_servs; s++) + { + for (uint8_t c = 0; c < gs_servs[s]->num_of_chars; c++) + { + if ((gs_servs[s]->pp_chars[c]->start_hdl <= attr_hdl) && + (gs_servs[s]->pp_chars[c]->end_hdl >= attr_hdl)) + { + *pp_serv = gs_servs[s]; + *pp_char = gs_servs[s]->pp_chars[c]; + } + } + } +} + +static void desc_write_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t *p_value) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + ret = p_char->pp_descs[d]->decode(p_app_value, (const st_ble_gatt_value_t *)p_value); + + if (NULL != p_char->pp_descs[d]->write_req_cb) + { + p_char->pp_descs[d]->write_req_cb(&p_char->pp_descs[d], conn_hdl, ret, (const void *)p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_REQ), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } +} + +static void desc_read_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(conn_hdl, attr_hdl, &gatt_value); + p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->read_req_cb) + { + p_char->pp_descs[d]->read_req_cb(&p_char->pp_descs[d], conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_READ_REQ), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } +} + +static void ble_gatts_db_app_cb(uint16_t conn_hdl, uint8_t db_op, uint16_t attr_hdl, st_ble_gatt_value_t *p_value) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL == p_serv) || (NULL == p_char)) + { + return; + } + + switch (db_op) + { + case BLE_GATTS_OP_CHAR_PEER_READ_REQ: + { + if (NULL != p_char->read_req_cb) + { + p_char->read_req_cb(p_char, conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_READ_REQ), BLE_SUCCESS, &evt_data); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_WRITE_REQ: + { + if (NULL != p_char->decode) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_char->app_size); + ret = p_char->decode(p_app_value, p_value); + + if (NULL != p_char->write_req_cb) + { + p_char->write_req_cb(p_char, conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_REQ), ret, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_WRITE_CMD: + { + if (NULL != p_char->decode) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_char->app_size); + ret = p_char->decode(p_app_value, p_value); + + if (NULL != p_char->write_cmd_cb) + { + p_char->write_cmd_cb(p_char, conn_hdl, ret, &p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_CMD), ret, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ: + { + desc_write_evt_handler(conn_hdl, attr_hdl, p_value); + } break; + + case BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ: + { + desc_read_evt_handler(conn_hdl, attr_hdl); + } break; + + case BLE_GATTS_OP_CHAR_REQ_AUTHOR: + { + } break; + + default: + { + /* Do nothing. */ + } break; + } +} + +void R_BLE_SERVS_GattsCb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data) +{ + static uint16_t s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + + switch (type) + { + case BLE_GATTS_EVENT_CONN_IND: + case BLE_GATTS_EVENT_DISCONN_IND: + break; + + case BLE_GATTS_EVENT_EX_MTU_REQ: + { + R_BLE_GATTS_RspExMtu(p_data->conn_hdl, BLE_PRF_MTU_SIZE); + } + break; + + case BLE_GATTS_EVENT_HDL_VAL_CNF: + { + const st_ble_gatts_cfm_evt_t *p_cfm_evt_param = + (st_ble_gatts_cfm_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(p_cfm_evt_param->attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if ((p_char->start_hdl + 1) == p_cfm_evt_param->attr_hdl) + { + if (NULL != p_char->hdl_val_cnf_cb) + { + p_char->hdl_val_cnf_cb(p_char, p_data->conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_HDL_VAL_CNF), BLE_SUCCESS, &evt_data); + } + } + } + } break; + + case BLE_GATTS_EVENT_DB_ACCESS_IND: + { + const st_ble_gatts_db_access_evt_t *p_db_access_evt_param = + (st_ble_gatts_db_access_evt_t *)p_data->p_param; + + ble_gatts_db_app_cb(p_data->conn_hdl, + p_db_access_evt_param->p_params->db_op, + p_db_access_evt_param->p_params->attr_hdl, + &p_db_access_evt_param->p_params->value); + } break; + + case BLE_GATTS_EVENT_WRITE_RSP_COMP: + { + st_ble_gatts_write_rsp_evt_t *p_write_rsp_evt_param = + (st_ble_gatts_write_rsp_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(p_write_rsp_evt_param->attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + /* Characteristic */ + if (((p_char->start_hdl + 1) == p_write_rsp_evt_param->attr_hdl) && (NULL != p_char->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->app_size); + + ret = R_BLE_SERVS_GetChar(p_char, p_data->conn_hdl, p_app_value); + + if (NULL != p_char->write_comp_cb) + { + p_char->write_comp_cb(p_char, p_data->conn_hdl, result, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_COMP), ret, &evt_data); + } + + free(p_app_value); + } + /* Descriptor */ + else + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == p_write_rsp_evt_param->attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(p_data->conn_hdl, p_write_rsp_evt_param->attr_hdl, &gatt_value); + + ret = p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->write_comp_cb) + { + p_char->pp_descs[d]->write_comp_cb(&p_char->pp_descs[d], p_data->conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_COMP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } + } + } break; + + case BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP: + { + st_ble_gatts_prepare_write_rsp_evt_t *p_prepare_write_evt_param = + (st_ble_gatts_prepare_write_rsp_evt_t *)p_data->p_param; + + s_write_long_attr_hdl = p_prepare_write_evt_param->attr_hdl; + } break; + + case BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP: + { + st_ble_gatts_exe_write_rsp_evt_t *p_exe_write_evt_param = + (st_ble_gatts_exe_write_rsp_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(s_write_long_attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG == p_exe_write_evt_param->exe_flag) { + /* Characteristic */ + if (((p_char->start_hdl + 1) == s_write_long_attr_hdl) && (NULL != p_char->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->app_size); + + ret = R_BLE_SERVS_GetChar(p_char, p_data->conn_hdl, p_app_value); + + if (NULL != p_char->write_comp_cb) + { + p_char->write_comp_cb(p_char, p_data->conn_hdl, result, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_COMP), ret, &evt_data); + } + + free(p_app_value); + s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + } + /* Descriptor */ + else + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == s_write_long_attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(p_data->conn_hdl, s_write_long_attr_hdl, &gatt_value); + + ret = p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->write_comp_cb) + { + p_char->pp_descs[d]->write_comp_cb(&p_char->pp_descs[d], p_data->conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_COMP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + break; + } + } + } + } + } + } + } break; + + case BLE_GATTS_EVENT_READ_RSP_COMP: + case BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP: + case BLE_GATTS_EVENT_READ_BLOB_RSP_COMP: + case BLE_GATTS_EVENT_READ_MULTI_RSP_COMP: + case BLE_GATTS_EVENT_INVALID: + default: + { + } break; + } +} + +void R_BLE_SERVS_VsCb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t * p_data) +{ + /* unused arg */ + (void)result; + + switch (type) + { + case BLE_VS_EVENT_TX_FLOW_STATE_CHG: + { + st_ble_vs_tx_flow_chg_evt_t *p_tx_flow_chg_param = + (st_ble_vs_tx_flow_chg_evt_t *)p_data->p_param; + + uint32_t buffer_num; + R_BLE_VS_GetTxBufferNum(&buffer_num); + + if (BLE_VS_TX_FLOW_CTL_ON == p_tx_flow_chg_param->state) + { + for (uint8_t s = 0; s < gs_num_of_servs; s++) + { + for (uint8_t c = 0; c < gs_servs[s]->num_of_chars; c++) + { + if (NULL != gs_servs[s]->pp_chars[c]->flow_ctrl_cb) + { + gs_servs[s]->pp_chars[c]->flow_ctrl_cb(gs_servs[s]->pp_chars[c]); + } + } + } + } + } break; + + default: + { + /* Do nothing */ + } break; + } +} + +ble_status_t R_BLE_SERVS_Init(void) +{ + R_BLE_VS_StartTxFlowEvtNtf(); + + return BLE_SUCCESS; +} + +ble_status_t R_BLE_SERVS_RegisterServer(const st_ble_servs_info_t *p_info) +{ + ble_status_t ret; + if( BLE_PRF_MAX_NUM_OF_SERVS > gs_num_of_servs ) + { + gs_servs[gs_num_of_servs++] = p_info; + ret = BLE_SUCCESS; + } + else + { + ret = BLE_ERR_CONTEXT_FULL; + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SendHdlVal(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value, bool is_notify) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_attr->encode) || (NULL == p_attr->pp_descs)) + { + return BLE_ERR_INVALID_PTR; + } + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if (BLE_GAP_INVALID_CONN_HDL == conn_hdl) + { + return BLE_ERR_INVALID_HDL; + } + + /* Check CCCD */ + uint16_t cccd = 0; + R_BLE_SERVS_GetDesc(p_attr->pp_descs[0], conn_hdl, &cccd); + if(0 == cccd) + { + return BLE_ERR_INVALID_OPERATION; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_hdl_value_pair_t hdl_val_data = { + .attr_hdl = (uint16_t)(p_attr->start_hdl + 1), + .value.value_len = p_attr->db_size, + .value.p_value = (uint8_t *)p_gatt_value, + }; + + ret = p_attr->encode(p_app_value, &hdl_val_data.value); + + if (BLE_SUCCESS == ret) + { + if (is_notify) + { + ret = R_BLE_GATTS_Notification(conn_hdl, &hdl_val_data); + } + else + { + ret = R_BLE_GATTS_Indication(conn_hdl, &hdl_val_data); + } + } + + free(p_gatt_value); + + return ret; +} + +ble_status_t R_BLE_SERVS_GetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->decode)) + { + return BLE_ERR_INVALID_PTR; + } + + st_ble_gatt_value_t gatt_value; + + ret = R_BLE_GATTS_GetAttr(conn_hdl, (uint16_t)(p_attr->start_hdl + 1), &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = p_attr->decode(p_app_value, &gatt_value); + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->encode)) + { + return BLE_ERR_INVALID_PTR; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_value_t gatt_value = { + .p_value = p_gatt_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = R_BLE_GATTS_SetAttr(conn_hdl, (uint16_t)(p_attr->start_hdl + 1), &gatt_value); + } + + free(p_gatt_value); + + return ret; +} + +ble_status_t R_BLE_SERVS_GetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->decode)) + { + return BLE_ERR_INVALID_PTR; + } + + st_ble_gatt_value_t gatt_value; + + ret = R_BLE_GATTS_GetAttr(conn_hdl, p_attr->attr_hdl, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = p_attr->decode(p_app_value, &gatt_value); + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->encode)) + { + return BLE_ERR_INVALID_PTR; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_value_t gatt_value = { + .p_value = p_gatt_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = R_BLE_GATTS_SetAttr(conn_hdl, p_attr->attr_hdl, &gatt_value); + } + + free(p_gatt_value); + + return ret; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h new file mode 100644 index 0000000000..b8ec78de3c --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h @@ -0,0 +1,304 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn_ser Profile Common Server Library + * @{ + * @ingroup profile_cmn + * @brief Profile Common Server Library Library + * @details This library provides APIs to implement GATT profile server. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ +#include "r_ble_serv_common.h" + +#ifndef R_BLE_SERVS_IF_H +#define R_BLE_SERVS_IF_H + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** @defgroup profile_cmn_ser_macro Macros + * @{ + * @brief Macro definition + */ + +/* attr_idx:6bit, inst_idx:4bit, type_idx:1bit, evt_idx:5bit */ +/** + * @def BLE_SERVS_MULTI_ATTR_EVENT + * @brief Event type used in callback. This macro is used if same service is used. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] inst_idx Service index. 4bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVS_MULTI_ATTR_EVENT(attr_idx, inst_idx, evt_idx) ((uint16_t)((attr_idx << 10) | (inst_idx << 6) | (evt_idx << 0))) + +/** + * @def BLE_SERVS_ATTR_EVENT + * @brief Event type used in callback. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVS_ATTR_EVENT(attr_idx, evt_idx) BLE_SERVS_MULTI_ATTR_EVENT(attr_idx, 0, evt_idx) + +/*******************************************************************************************************************//** + * @brief Server callback events. +***********************************************************************************************************************/ +typedef enum { + BLE_SERVS_WRITE_REQ = 0x00, /**< Receive a write request */ + BLE_SERVS_WRITE_CMD = 0x01, /**< Receive a write command */ + BLE_SERVS_WRITE_COMP = 0x02, /**< Send a write response */ + BLE_SERVS_READ_REQ = 0x03, /**< Receive a read request */ + BLE_SERVS_HDL_VAL_CNF = 0x04, /**< Receive a confirmation */ +} e_ble_servs_event_t; +/*@}*/ + +/** @defgroup profile_cmn_ser_struct Structures + * @{ + * @brief Structure definition + */ +typedef struct { + uint16_t conn_hdl; /**< Connection handle. */ + uint16_t param_len; /**< Event parameter length. */ + const void *p_param; /**< Event parameter.\n Value is set after decode function is called. */ +} st_ble_servs_evt_data_t; +/*@}*/ + +/** @defgroup profile_cmn_ser_callback Callbacks + * @{ + * @brief Callback definition + */ +/*************************************************************************************************************//** + * @brief Callback invoked when write request received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write request. + * @param[in] p_app_value Characteristic value or descriptor value of write request. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_req_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when write command received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write command. + * @param[in] p_app_value Characteristic value of write command. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_cmd_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when write response sent. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write response. + * @param[in] p_app_value Characteristic value or descriptor value of write response. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_comp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when read request received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_read_req_t)(const void *p_attr, uint16_t conn_hdl); + +/*************************************************************************************************************//** + * @brief Callback invoked when confirmation received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_hdl_val_cnf_t)(const void *p_attr, uint16_t conn_hdl); + +/*************************************************************************************************************//** + * @brief Callback invoked when flow control callback occurred. + * @param[in] p_attr Information structure of characteristic. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_flow_ctrl_t)(const void *p_attr); + +/*************************************************************************************************************//** + * @brief Callback invoked when events defined in service occurred. + * @param[in] type Event type of callback. Refer e_ble_XXX_event_t of each service you will use. + * @param[in] result Result of event. + * @param[in] p_data Event data. +***********************************************************************************************************************/ +typedef void (*ble_servs_app_cb_t)(uint16_t type, ble_status_t result, st_ble_servs_evt_data_t *p_data); +/*@}*/ + +/** @defgroup profile_cmn_ser_func Functions + * @{ + * @brief Function definition + */ +/*************************************************************************************************************//** + * @brief Decode function. Convert data from GATT database value to application data value. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servs_attr_decode_t)(void *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/*************************************************************************************************************//** + * @brief Encode function. Convert data from application data value to GATT database value. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servs_attr_encode_t)(const void *p_app_value, st_ble_gatt_value_t *p_gatt_value); +/*@}*/ + +/** @defgroup profile_cmn_ser_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servs_desc_info_t + * @brief st_ble_servs_desc_info_t includes information about descriptor. + **********************************************************************************************************************/ +typedef struct _st_ble_desc_info_t{ + uint16_t attr_hdl; /**< Attribute handle of descriptor */ + uint8_t desc_idx; /**< Index of descriptor */ + uint8_t inst_idx; /**< Index used if same descriptor is set in one characteristic */ + uint16_t app_size; /**< Descriptor value size used in application. */ + uint16_t db_size; /**< Descriptor value size used in GATT database. */ + ble_servs_attr_write_req_t write_req_cb; /**< Write request callback function. Set function if needed. */ + ble_servs_attr_write_comp_t write_comp_cb; /**< Write response callback function. Set function if needed. */ + ble_servs_attr_read_req_t read_req_cb; /**< Read request callback function. Set function if needed. */ + ble_servs_attr_decode_t decode; /**< Decode function. */ + ble_servs_attr_encode_t encode; /**< Encode function. */ +} st_ble_servs_desc_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servs_char_info_t + * @brief st_ble_servs_char_info_t includes information about characteristic. + **********************************************************************************************************************/ +typedef struct _st_ble_char_info_t { + uint16_t start_hdl; /**< First Attribute handle of this characteristic */ + uint16_t end_hdl; /**< Last Attribute handle of this characteristic */ + uint8_t char_idx; /**< Index of characteristic */ + uint8_t inst_idx; /**< Index used if same characteristic is set in one service */ + uint16_t app_size; /**< Size of characteristic value in Application. */ + uint16_t db_size; /**< Size of characteristic value in GATT database. */ + const st_ble_servs_desc_info_t **pp_descs; /**< Set all descriptor information structure included in this characteristic. */ + uint8_t num_of_descs; /**< Number of descriptors included in this characteristic. */ + ble_servs_attr_write_req_t write_req_cb; /**< Write request callback function. Set function if needed. */ + ble_servs_attr_write_cmd_t write_cmd_cb; /**< Write command callback function. Set function if needed. */ + ble_servs_attr_write_comp_t write_comp_cb; /**< Write response callback function. Set function if needed. */ + ble_servs_attr_read_req_t read_req_cb; /**< Read request callback function. Set function if needed. */ + ble_servs_attr_hdl_val_cnf_t hdl_val_cnf_cb; /**< Confirmation callback function. Set function if needed. */ + ble_servs_attr_flow_ctrl_t flow_ctrl_cb; /**< Flow control callback function. Set function if needed. */ + ble_servs_attr_decode_t decode; /**< Decode function. */ + ble_servs_attr_encode_t encode; /**< Encode function. */ +} st_ble_servs_char_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servs_info_t + * @brief st_ble_servs_info_t includes information about service. + **********************************************************************************************************************/ +typedef struct { + const st_ble_servs_char_info_t **pp_chars; /**< Set all characteristic information structure included in this service. */ + uint8_t num_of_chars; /**< Number of characteristics included in this service. */ + ble_servs_app_cb_t cb; /**< Service event callback function. */ +} st_ble_servs_info_t; +/*@}*/ +/**/ +/** @defgroup profile_cmn_ser_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Initialize profile common server library. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_Init(void); + +/******************************************************************************************************************//** + * @brief Register server service information to profile common server library. + * @param[in] p_serv Server service to be registered. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_RegisterServer(const st_ble_servs_info_t *p_serv); + +/******************************************************************************************************************//** + * @brief Send notification or indication. + * @param[in] p_attr Characteristic sending notification or indication. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on notification or indication. + * @param[in] is_notify Defines notification or indication.\n true = notification\n false = indication + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SendHdlVal(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value, bool is_notify); + +/******************************************************************************************************************//** + * @brief Get characteristic value from GATT database. + * @param[in] p_attr Characteristic getting value. + * @param[in] conn_hdl Connection handle. + * @param[out] p_app_value Characteristic value getting from GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_GetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, void *p_app_value); + +/******************************************************************************************************************//** + * @brief Set characteristic value to GATT database. + * @param[in] p_attr Characteristic setting value. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value setting to GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Get descriptor value from GATT database. + * @param[in] p_attr Descriptor getting value. + * @param[in] conn_hdl Connection handle. + * @param[out] p_app_value Descriptor value getting from GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_GetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, void *p_app_value); + +/******************************************************************************************************************//** + * @brief Set descriptor value to GATT database. + * @param[in] p_attr Descriptor setting value. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Descriptor value setting to GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Callback function used for GATT server event. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function to enable all server callback event included in profile. + **********************************************************************************************************************/ +void R_BLE_SERVS_GattsCb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data); + +/******************************************************************************************************************//** + * @brief Callback function used for vender specific event. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function if you use flow control callback. + **********************************************************************************************************************/ +void R_BLE_SERVS_VsCb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t * p_data); +/*@}*/ + +#endif /* R_BLE_SERVS_IF_H */ +/* @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.c new file mode 100644 index 0000000000..4649739281 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.c @@ -0,0 +1,312 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gapc.c + * Version : 1.0 + * Description : The source file for Generic Access client. + **********************************************************************************************************************/ +#include +#include "r_ble_gapc.h" +#include "profile_cmn/r_ble_servc_if.h" + +static st_ble_servc_info_t gs_client_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Device Name characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_dev_name_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +static ble_status_t decode_st_ble_gapc_dev_name_t(st_ble_gapc_dev_name_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPC_DEV_NAME_LEN < p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memset(p_app_value->name, 0x00, BLE_GAPC_DEV_NAME_LEN); + + strcpy(p_app_value->name, (char *)p_gatt_value->p_value); + p_app_value->length = (uint8_t)p_gatt_value->value_len; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gapc_dev_name_t(const st_ble_gapc_dev_name_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPC_DEV_NAME_LEN < p_app_value->length) + { + return BLE_ERR_INVALID_DATA; + } + + strncpy((char *)p_gatt_value->p_value, p_app_value->name, p_app_value->length); + + return BLE_SUCCESS; +} + +/* Device Name characteristic definition */ +const st_ble_servc_char_info_t gs_dev_name_char = { + .uuid_16 = BLE_GAPC_DEV_NAME_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(st_ble_gapc_dev_name_t), + .db_size = BLE_GAPC_DEV_NAME_LEN, + .char_idx = BLE_GAPC_DEV_NAME_IDX, + .p_attr_hdls = gs_dev_name_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_st_ble_gapc_dev_name_t, + .encode = (ble_servc_attr_encode_t)encode_st_ble_gapc_dev_name_t, +}; + +ble_status_t R_BLE_GAPC_WriteDevName(uint16_t conn_hdl, const st_ble_gapc_dev_name_t *p_value) // @suppress("API function naming") +{ + return R_BLE_SERVC_WriteChar(&gs_dev_name_char, conn_hdl, p_value); +} + +ble_status_t R_BLE_GAPC_ReadDevName(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_dev_name_char, conn_hdl); +} + +void R_BLE_GAPC_GetDevNameAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_dev_name_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_dev_name_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Appearance characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_appearance_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Appearance characteristic definition */ +const st_ble_servc_char_info_t gs_appearance_char = { + .uuid_16 = BLE_GAPC_APPEARANCE_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint16_t), + .db_size = sizeof(uint16_t), + .char_idx = BLE_GAPC_APPEARANCE_IDX, + .p_attr_hdls = gs_appearance_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint16_t, + .encode = (ble_servc_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GAPC_ReadAppearance(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_appearance_char, conn_hdl); +} + +void R_BLE_GAPC_GetAppearanceAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_appearance_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_appearance_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Peripheral Preferred Connection Parameters characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_per_pref_conn_param_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +static ble_status_t decode_st_ble_gapc_per_pref_conn_param_t(st_ble_gapc_per_pref_conn_param_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GAPC_PER_PREF_CONN_PARAM_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->min_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->max_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->slave_latency, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->conn_sup_timeout_multiplier, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gapc_per_pref_conn_param_t(const st_ble_gapc_per_pref_conn_param_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->min_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->max_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->slave_latency); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->conn_sup_timeout_multiplier); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Peripheral Preferred Connection Parameters characteristic definition */ +const st_ble_servc_char_info_t gs_per_pref_conn_param_char = { + .uuid_16 = BLE_GAPC_PER_PREF_CONN_PARAM_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(st_ble_gapc_per_pref_conn_param_t), + .db_size = BLE_GAPC_PER_PREF_CONN_PARAM_LEN, + .char_idx = BLE_GAPC_PER_PREF_CONN_PARAM_IDX, + .p_attr_hdls = gs_per_pref_conn_param_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_st_ble_gapc_per_pref_conn_param_t, + .encode = (ble_servc_attr_encode_t)encode_st_ble_gapc_per_pref_conn_param_t, +}; + +ble_status_t R_BLE_GAPC_ReadPerPrefConnParam(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_per_pref_conn_param_char, conn_hdl); +} + +void R_BLE_GAPC_GetPerPrefConnParamAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_per_pref_conn_param_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_per_pref_conn_param_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Central Address Resolution characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_cent_addr_rslv_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Central Address Resolution characteristic definition */ +const st_ble_servc_char_info_t gs_cent_addr_rslv_char = { + .uuid_16 = BLE_GAPC_CENT_ADDR_RSLV_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint8_t), + .db_size = sizeof(uint8_t), + .char_idx = BLE_GAPC_CENT_ADDR_RSLV_IDX, + .p_attr_hdls = gs_cent_addr_rslv_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint8_t, + .encode = (ble_servc_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPC_ReadCentAddrRslv(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_cent_addr_rslv_char, conn_hdl); +} + +void R_BLE_GAPC_GetCentAddrRslvAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_cent_addr_rslv_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_cent_addr_rslv_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Resolvable Private Address Only characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_rslv_priv_addr_only_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Resolvable Private Address Only characteristic definition */ +const st_ble_servc_char_info_t gs_rslv_priv_addr_only_char = { + .uuid_16 = BLE_GAPC_RSLV_PRIV_ADDR_ONLY_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint8_t), + .db_size = sizeof(uint8_t), + .char_idx = BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, + .p_attr_hdls = gs_rslv_priv_addr_only_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint8_t, + .encode = (ble_servc_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPC_ReadRslvPrivAddrOnly(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_rslv_priv_addr_only_char, conn_hdl); +} + +void R_BLE_GAPC_GetRslvPrivAddrOnlyAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_rslv_priv_addr_only_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_rslv_priv_addr_only_char_ranges[conn_idx]; +} + + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access client +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Access client attribute handles */ +static st_ble_gatt_hdl_range_t gs_gapc_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +const st_ble_servc_char_info_t *gspp_gapc_chars[] = { + &gs_dev_name_char, + &gs_appearance_char, + &gs_per_pref_conn_param_char, + &gs_cent_addr_rslv_char, + &gs_rslv_priv_addr_only_char, +}; + +static st_ble_servc_info_t gs_client_info = { + .pp_chars = gspp_gapc_chars, + .num_of_chars = ARRAY_SIZE(gspp_gapc_chars), + .p_attr_hdls = gs_gapc_ranges, +}; + +ble_status_t R_BLE_GAPC_Init(ble_servc_app_cb_t cb) // @suppress("API function naming") +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_client_info.cb = cb; + + return R_BLE_SERVC_RegisterClient(&gs_client_info); +} + +void R_BLE_GAPC_ServDiscCb(uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param) // @suppress("API function naming") +{ + R_BLE_SERVC_ServDiscCb(&gs_client_info, conn_hdl, serv_idx, type, p_param); +} + +void R_BLE_GAPC_GetServAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gatt_hdl_range_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + *p_hdl = gs_gapc_ranges[conn_idx]; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.h new file mode 100644 index 0000000000..5d87ae5a78 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gapc.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gapc.h + * Version : 1.0 + * Description : The header file for Generic Access client. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gapc Generic Access Client + * @{ + * @ingroup profile + * @brief This is the client for the Generic Access Service. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servc_if.h" + +#ifndef R_BLE_GAPC_H +#define R_BLE_GAPC_H + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_DEV_NAME_UUID (0x2A00) +#define BLE_GAPC_DEV_NAME_LEN (128) +/***************************************************************************//** + * @brief Device Name value structure. +*******************************************************************************/ +typedef struct { + char name[BLE_GAPC_DEV_NAME_LEN]; /**< Name */ + uint8_t length; /**< Length */ +} st_ble_gapc_dev_name_t; + +/***************************************************************************//** + * @brief Device Name attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_dev_name_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Device Name characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadDevName(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Write Device Name characteristic value to remote GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Device Name characteristic value to write. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_WriteDevName(uint16_t conn_hdl, const st_ble_gapc_dev_name_t *p_value); +; +/***************************************************************************//** + * @brief Get Device Name attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetDevNameAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_dev_name_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_APPEARANCE_UUID (0x2A01) +#define BLE_GAPC_APPEARANCE_LEN (2) +/***************************************************************************//** + * @brief Appearance Category enumeration. +*******************************************************************************/ +typedef enum { + BLE_GAPC_APPEARANCE_CATEGORY_UNKNOWN = 0, /**< Unknown */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_PHONE = 64, /**< Generic Phone */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_COMPUTER = 128, /**< Generic Computer */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_WATCH = 192, /**< Generic Watch */ + BLE_GAPC_APPEARANCE_CATEGORY_WATCH_SPORTS_WATCH = 193, /**< Watch: Sports Watch */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_CLOCK = 256, /**< Generic Clock */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_DISPLAY = 320, /**< Generic Display */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_REMOTE_CONTROL = 384, /**< Generic Remote Control */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_EYE_GLASSES = 448, /**< Generic Eye-glasses */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_TAG = 512, /**< Generic Tag */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_KEYRING = 576, /**< Generic Keyring */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_MEDIA_PLAYER = 640, /**< Generic Media Player */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_BARCODE_SCANNER = 704, /**< Generic Barcode Scanner */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_THERMOMETER = 768, /**< Generic Thermometer */ + BLE_GAPC_APPEARANCE_CATEGORY_THERMOMETER_EAR = 769, /**< Thermometer Ear */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_HEART_RATE_SENSOR = 832, /**< Generic Heart rate Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_HEART_RATE_SENSOR_HEART_RATE_BELT = 833, /**< Heart Rate Sensor Heart Rate Belt */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_BLOOD_PRESSURE = 896, /**< Generic Blood Pressure */ + BLE_GAPC_APPEARANCE_CATEGORY_BLOOD_PRESSURE_ARM = 897, /**< Blood Pressure: Arm */ + BLE_GAPC_APPEARANCE_CATEGORY_BLOOD_PRESSURE_WRIST = 898, /**< Blood Pressure: Wrist */ + BLE_GAPC_APPEARANCE_CATEGORY_HUMAN_INTERFACE_DEVICE = 960, /**< Human Interface Device (HID) */ + BLE_GAPC_APPEARANCE_CATEGORY_KEYBOARD = 961, /**< Keyboard */ + BLE_GAPC_APPEARANCE_CATEGORY_MOUSE = 962, /**< Mouse */ + BLE_GAPC_APPEARANCE_CATEGORY_JOYSTICK = 963, /**< Joystick */ + BLE_GAPC_APPEARANCE_CATEGORY_GAMEPAD = 964, /**< Gamepad */ + BLE_GAPC_APPEARANCE_CATEGORY_DIGITIZER_TABLET = 965, /**< Digitizer Tablet */ + BLE_GAPC_APPEARANCE_CATEGORY_CARD_READER = 966, /**< Card Reader */ + BLE_GAPC_APPEARANCE_CATEGORY_DIGITAL_PEN = 967, /**< Digital Pen */ + BLE_GAPC_APPEARANCE_CATEGORY_BARCODE_SCANNER = 968, /**< Barcode Scanner */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_GLUCOSE_METER = 1024, /**< Generic Glucose Meter */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_RUNNING_WALKING_SENSOR = 1088, /**< Generic: Running Walking Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_IN_SHOE = 1089, /**< Running Walking Sensor: In-Shoe */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_SHOE = 1090, /**< Running Walking Sensor: On-Shoe */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_HIP = 1091, /**< Running Walking Sensor: On-Hip */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC__CYCLING = 1152, /**< Generic Cycling */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_CYCLING_COMPUTER = 1153, /**< Cycling Cycling Computer */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_SPEED_SENSOR = 1154, /**< Cycling Speed Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_CADENCE_SENSOR = 1155, /**< Cycling Cadence Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_POWER_SENSOR = 1156, /**< Cycling: Power Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, /**< Cycling Speed and Cadence Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_PULSE_OXIMETER = 3136, /**< Generic Pulse Oximeter */ + BLE_GAPC_APPEARANCE_CATEGORY_FINGERTIP = 3137, /**< Fingertip */ + BLE_GAPC_APPEARANCE_CATEGORY_WRIST_WORN = 3138, /**< Wrist Worn */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC__WEIGHT_SCALE = 3200, /**< Generic Weight Scale */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_OUTDOOR_SPORTS_ACTIVITY = 5184, /**< Generic Outdoor Sports Activity */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_DISPLAY_DEVICE = 5185, /**< Location Display Device */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, /**< Location and Navigation Display Device */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_POD = 5187, /**< Location Pod */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_POD = 5188, /**< Location and Navigation Pod */ +} e_ble_appearance_category_t; + +/***************************************************************************//** + * @brief Appearance attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_appearance_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Appearance characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadAppearance(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Appearance attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetAppearanceAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_appearance_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_PER_PREF_CONN_PARAM_UUID (0x2A04) +#define BLE_GAPC_PER_PREF_CONN_PARAM_LEN (8) +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters value structure. +*******************************************************************************/ +typedef struct { + uint16_t min_conn_intv; /**< Minimum Connection Interval */ + uint16_t max_conn_intv; /**< Maximum Connection Interval */ + uint16_t slave_latency; /**< Slave Latency */ + uint16_t conn_sup_timeout_multiplier; /**< Connection Supervision Timeout Multiplier */ +} st_ble_gapc_per_pref_conn_param_t; + +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_per_pref_conn_param_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Peripheral Preferred Connection Parameters characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadPerPrefConnParam(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Peripheral Preferred Connection Parameters attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetPerPrefConnParamAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_per_pref_conn_param_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_CENT_ADDR_RSLV_UUID (0x2AA6) +#define BLE_GAPC_CENT_ADDR_RSLV_LEN (1) +/***************************************************************************//** + * @brief Central Address Resolution attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_cent_addr_rslv_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Central Address Resolution characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadCentAddrRslv(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Central Address Resolution attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetCentAddrRslvAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_cent_addr_rslv_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_RSLV_PRIV_ADDR_ONLY_UUID (0x2AC9) +#define BLE_GAPC_RSLV_PRIV_ADDR_ONLY_LEN (1) +/***************************************************************************//** + * @brief Resolvable Private Address Only attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_rslv_priv_addr_only_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Resolvable Private Address Only characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadRslvPrivAddrOnly(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Resolvable Private Address Only attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetRslvPrivAddrOnlyAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_rslv_priv_addr_only_attr_hdl_t *p_hdl); + + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access Client +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Access client event data. +*******************************************************************************/ +typedef struct { + uint16_t conn_hdl; /**< Connection handle */ + uint16_t param_len; /**< Event parameter length */ + const void *p_param; /**< Event parameter */ +} st_ble_gapc_evt_data_t; + +/***************************************************************************//** + * @brief Generic Access characteristic ID. +*******************************************************************************/ +typedef enum { + BLE_GAPC_DEV_NAME_IDX, + BLE_GAPC_APPEARANCE_IDX, + BLE_GAPC_PER_PREF_CONN_PARAM_IDX, + BLE_GAPC_CENT_ADDR_RSLV_IDX, + BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, +} st_ble_gapc_char_idx_t; + +/***************************************************************************//** + * @brief Generic Access client event type. +*******************************************************************************/ +typedef enum { + /* Device Name */ + BLE_GAPC_EVENT_DEV_NAME_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_DEV_NAME_IDX, BLE_SERVC_READ_RSP), + BLE_GAPC_EVENT_DEV_NAME_WRITE_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_DEV_NAME_IDX, BLE_SERVC_WRITE_RSP), + /* Appearance */ + BLE_GAPC_EVENT_APPEARANCE_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_APPEARANCE_IDX, BLE_SERVC_READ_RSP), + /* Peripheral Preferred Connection Parameters */ + BLE_GAPC_EVENT_PER_PREF_CONN_PARAM_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_PER_PREF_CONN_PARAM_IDX, BLE_SERVC_READ_RSP), + /* Central Address Resolution */ + BLE_GAPC_EVENT_CENT_ADDR_RSLV_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_CENT_ADDR_RSLV_IDX, BLE_SERVC_READ_RSP), + /* Resolvable Private Address Only */ + BLE_GAPC_EVENT_RSLV_PRIV_ADDR_ONLY_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, BLE_SERVC_READ_RSP), +} e_ble_gapc_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Access client. + * @param[in] cb Client callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_Init(ble_servc_app_cb_t cb); + +/***************************************************************************//** + * @brief Generic Access client discovery callback. + * @param[in] conn_hdl Connection handle + * @param[in] serv_idx Service instance index. + * @param[in] type Service discovery event type. + * @param[in] p_param Service discovery event parameter. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_ServDiscCb(uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param); + +/***************************************************************************//** + * @brief Get Generic Access client attribute handle. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. +*******************************************************************************/ +void R_BLE_GAPC_GetServAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gatt_hdl_range_t *p_hdl); + +#endif /* R_BLE_GAPC_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.c new file mode 100644 index 0000000000..d7ecd40fb7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.c @@ -0,0 +1,251 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gaps.c + * Version : 1.0 + * Description : The source file for Generic Access service. + **********************************************************************************************************************/ +#include +#include "r_ble_gaps.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gaps_dev_name_t(st_ble_gaps_dev_name_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPS_DEV_NAME_NAME_LEN < p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memset(p_app_value->name, 0x00, BLE_GAPS_DEV_NAME_NAME_LEN); + + strcpy(p_app_value->name, (char *)p_gatt_value->p_value); + p_app_value->length = (uint8_t)p_gatt_value->value_len; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gaps_dev_name_t(const st_ble_gaps_dev_name_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPS_DEV_NAME_NAME_LEN < p_app_value->length) + { + return BLE_ERR_INVALID_DATA; + } + + strncpy((char *)p_gatt_value->p_value, p_app_value->name, p_app_value->length); + + return BLE_SUCCESS; +} + +/* Device Name characteristic definition */ +static const st_ble_servs_char_info_t gs_dev_name_char = { + .start_hdl = BLE_GAPS_DEV_NAME_DECL_HDL, + .end_hdl = BLE_GAPS_DEV_NAME_VAL_HDL, + .char_idx = BLE_GAPS_DEV_NAME_IDX, + .app_size = sizeof(st_ble_gaps_dev_name_t), + .db_size = BLE_GAPS_DEV_NAME_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gaps_dev_name_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gaps_dev_name_t, +}; + +ble_status_t R_BLE_GAPS_SetDevName(const st_ble_gaps_dev_name_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_dev_name_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetDevName(st_ble_gaps_dev_name_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_dev_name_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Appearance characteristic definition */ +static const st_ble_servs_char_info_t gs_appearance_char = { + .start_hdl = BLE_GAPS_APPEARANCE_DECL_HDL, + .end_hdl = BLE_GAPS_APPEARANCE_VAL_HDL, + .char_idx = BLE_GAPS_APPEARANCE_IDX, + .app_size = sizeof(uint16_t), + .db_size = BLE_GAPS_APPEARANCE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GAPS_SetAppearance(const uint16_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_appearance_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetAppearance(uint16_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_appearance_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gaps_per_pref_conn_param_t(st_ble_gaps_per_pref_conn_param_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GAPS_PER_PREF_CONN_PARAM_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->min_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->max_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->slave_latency, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->conn_sup_timeout_multiplier, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gaps_per_pref_conn_param_t(const st_ble_gaps_per_pref_conn_param_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->min_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->max_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->slave_latency); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->conn_sup_timeout_multiplier); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Peripheral Preferred Connection Parameters characteristic definition */ +static const st_ble_servs_char_info_t gs_per_pref_conn_param_char = { + .start_hdl = BLE_GAPS_PER_PREF_CONN_PARAM_DECL_HDL, + .end_hdl = BLE_GAPS_PER_PREF_CONN_PARAM_VAL_HDL, + .char_idx = BLE_GAPS_PER_PREF_CONN_PARAM_IDX, + .app_size = sizeof(st_ble_gaps_per_pref_conn_param_t), + .db_size = BLE_GAPS_PER_PREF_CONN_PARAM_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gaps_per_pref_conn_param_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gaps_per_pref_conn_param_t, +}; + +ble_status_t R_BLE_GAPS_SetPerPrefConnParam(const st_ble_gaps_per_pref_conn_param_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_per_pref_conn_param_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetPerPrefConnParam(st_ble_gaps_per_pref_conn_param_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_per_pref_conn_param_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Central Address Resolution characteristic definition */ +static const st_ble_servs_char_info_t gs_cent_addr_rslv_char = { + .start_hdl = BLE_GAPS_CENT_ADDR_RSLV_DECL_HDL, + .end_hdl = BLE_GAPS_CENT_ADDR_RSLV_VAL_HDL, + .char_idx = BLE_GAPS_CENT_ADDR_RSLV_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_GAPS_CENT_ADDR_RSLV_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPS_SetCentAddrRslv(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_cent_addr_rslv_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetCentAddrRslv(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_cent_addr_rslv_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Resolvable Private Address Only characteristic definition */ +static const st_ble_servs_char_info_t gs_rslv_priv_addr_only_char = { + .start_hdl = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_DECL_HDL, + .end_hdl = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_VAL_HDL, + .char_idx = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPS_SetRslvPrivAddrOnly(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_rslv_priv_addr_only_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetRslvPrivAddrOnly(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_rslv_priv_addr_only_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access server +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Access characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_dev_name_char, + &gs_appearance_char, + &gs_per_pref_conn_param_char, + &gs_cent_addr_rslv_char, + &gs_rslv_priv_addr_only_char, +}; + +/* Generic Access service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_GAPS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.h new file mode 100644 index 0000000000..f1d66acb7c --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gaps.h @@ -0,0 +1,245 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gaps.h + * Version : 1.0 + * Description : The header file for Generic Access service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gaps Generic Access Service + * @{ + * @ingroup profile + * @brief The generic_access service contains generic information about the device. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_GAPS_H +#define R_BLE_GAPS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/** Name Length */ +#define BLE_GAPS_DEV_NAME_NAME_LEN (100) + +/***************************************************************************//** + * @brief Device Name value structure. +*******************************************************************************/ +typedef struct { + char name[BLE_GAPS_DEV_NAME_NAME_LEN]; /**< Name */ + uint8_t length; /**< Length */ +} st_ble_gaps_dev_name_t; + +/***************************************************************************//** + * @brief Set Device Name characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetDevName(const st_ble_gaps_dev_name_t *p_value); + +/***************************************************************************//** + * @brief Get Device Name characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetDevName(st_ble_gaps_dev_name_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Appearance Category enumeration. +*******************************************************************************/ +typedef enum { + BLE_GAPS_APPEARANCE_CATEGORY_UNKNOWN = 0, /**< Unknown */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_PHONE = 64, /**< Generic Phone */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_COMPUTER = 128, /**< Generic Computer */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_WATCH = 192, /**< Generic Watch */ + BLE_GAPS_APPEARANCE_CATEGORY_WATCH_SPORTS_WATCH = 193, /**< Watch: Sports Watch */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_CLOCK = 256, /**< Generic Clock */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_DISPLAY = 320, /**< Generic Display */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_REMOTE_CONTROL = 384, /**< Generic Remote Control */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_EYE_GLASSES = 448, /**< Generic Eye-glasses */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_TAG = 512, /**< Generic Tag */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_KEYRING = 576, /**< Generic Keyring */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_MEDIA_PLAYER = 640, /**< Generic Media Player */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_BARCODE_SCANNER = 704, /**< Generic Barcode Scanner */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_THERMOMETER = 768, /**< Generic Thermometer */ + BLE_GAPS_APPEARANCE_CATEGORY_THERMOMETER_EAR = 769, /**< Thermometer Ear */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_HEART_RATE_SENSOR = 832, /**< Generic Heart rate Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_HEART_RATE_SENSOR_HEART_RATE_BELT = 833, /**< Heart Rate Sensor Heart Rate Belt */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_BLOOD_PRESSURE = 896, /**< Generic Blood Pressure */ + BLE_GAPS_APPEARANCE_CATEGORY_BLOOD_PRESSURE_ARM = 897, /**< Blood Pressure: Arm */ + BLE_GAPS_APPEARANCE_CATEGORY_BLOOD_PRESSURE_WRIST = 898, /**< Blood Pressure: Wrist */ + BLE_GAPS_APPEARANCE_CATEGORY_HUMAN_INTERFACE_DEVICE = 960, /**< Human Interface Device (HID) */ + BLE_GAPS_APPEARANCE_CATEGORY_KEYBOARD = 961, /**< Keyboard */ + BLE_GAPS_APPEARANCE_CATEGORY_MOUSE = 962, /**< Mouse */ + BLE_GAPS_APPEARANCE_CATEGORY_JOYSTICK = 963, /**< Joystick */ + BLE_GAPS_APPEARANCE_CATEGORY_GAMEPAD = 964, /**< Gamepad */ + BLE_GAPS_APPEARANCE_CATEGORY_DIGITIZER_TABLET = 965, /**< Digitizer Tablet */ + BLE_GAPS_APPEARANCE_CATEGORY_CARD_READER = 966, /**< Card Reader */ + BLE_GAPS_APPEARANCE_CATEGORY_DIGITAL_PEN = 967, /**< Digital Pen */ + BLE_GAPS_APPEARANCE_CATEGORY_BARCODE_SCANNER = 968, /**< Barcode Scanner */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_GLUCOSE_METER = 1024, /**< Generic Glucose Meter */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_RUNNING_WALKING_SENSOR = 1088, /**< Generic: Running Walking Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_IN_SHOE = 1089, /**< Running Walking Sensor: In-Shoe */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_SHOE = 1090, /**< Running Walking Sensor: On-Shoe */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_HIP = 1091, /**< Running Walking Sensor: On-Hip */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC__CYCLING = 1152, /**< Generic Cycling */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_CYCLING_COMPUTER = 1153, /**< Cycling Cycling Computer */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_SPEED_SENSOR = 1154, /**< Cycling Speed Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_CADENCE_SENSOR = 1155, /**< Cycling Cadence Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_POWER_SENSOR = 1156, /**< Cycling: Power Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, /**< Cycling Speed and Cadence Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_PULSE_OXIMETER = 3136, /**< Generic Pulse Oximeter */ + BLE_GAPS_APPEARANCE_CATEGORY_FINGERTIP = 3137, /**< Fingertip */ + BLE_GAPS_APPEARANCE_CATEGORY_WRIST_WORN = 3138, /**< Wrist Worn */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC__WEIGHT_SCALE = 3200, /**< Generic Weight Scale */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_OUTDOOR_SPORTS_ACTIVITY = 5184, /**< Generic Outdoor Sports Activity */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_DISPLAY_DEVICE = 5185, /**< Location Display Device */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, /**< Location and Navigation Display Device */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_POD = 5187, /**< Location Pod */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_POD = 5188, /**< Location and Navigation Pod */ +} e_ble_appearance_category_t; + +/***************************************************************************//** + * @brief Set Appearance characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetAppearance(const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Appearance characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetAppearance(uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters value structure. +*******************************************************************************/ +typedef struct { + uint16_t min_conn_intv; /**< Minimum Connection Interval */ + uint16_t max_conn_intv; /**< Maximum Connection Interval */ + uint16_t slave_latency; /**< Slave Latency */ + uint16_t conn_sup_timeout_multiplier; /**< Connection Supervision Timeout Multiplier */ +} st_ble_gaps_per_pref_conn_param_t; + +/***************************************************************************//** + * @brief Set Peripheral Preferred Connection Parameters characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetPerPrefConnParam(const st_ble_gaps_per_pref_conn_param_t *p_value); + +/***************************************************************************//** + * @brief Get Peripheral Preferred Connection Parameters characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetPerPrefConnParam(st_ble_gaps_per_pref_conn_param_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set Central Address Resolution characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetCentAddrRslv(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get Central Address Resolution characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetCentAddrRslv(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set Resolvable Private Address Only characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetRslvPrivAddrOnly(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get Resolvable Private Address Only characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetRslvPrivAddrOnly(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Access characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_GAPS_DEV_NAME_IDX, + BLE_GAPS_APPEARANCE_IDX, + BLE_GAPS_PER_PREF_CONN_PARAM_IDX, + BLE_GAPS_CENT_ADDR_RSLV_IDX, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, +} st_ble_gaps_char_idx_t; + +/***************************************************************************//** + * @brief Generic Access event type. +*******************************************************************************/ +typedef enum { + /* Device Name */ + BLE_GAPS_EVENT_DEV_NAME_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_WRITE_REQ), + BLE_GAPS_EVENT_DEV_NAME_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_WRITE_COMP), + BLE_GAPS_EVENT_DEV_NAME_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_READ_REQ), + /* Appearance */ + BLE_GAPS_EVENT_APPEARANCE_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_APPEARANCE_IDX, BLE_SERVS_READ_REQ), + /* Peripheral Preferred Connection Parameters */ + BLE_GAPS_EVENT_PER_PREF_CONN_PARAM_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_PER_PREF_CONN_PARAM_IDX, BLE_SERVS_READ_REQ), + /* Central Address Resolution */ + BLE_GAPS_EVENT_CENT_ADDR_RSLV_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_CENT_ADDR_RSLV_IDX, BLE_SERVS_READ_REQ), + /* Resolvable Private Address Only */ + BLE_GAPS_EVENT_RSLV_PRIV_ADDR_ONLY_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, BLE_SERVS_READ_REQ), +} e_ble_gaps_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Access service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_GAPS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.c new file mode 100644 index 0000000000..65f4e14da7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.c @@ -0,0 +1,137 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gats.c + * Version : 1.0 + * Description : The source file for Generic Attribute service. + **********************************************************************************************************************/ + +#include "r_ble_gats.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed Client Characteristic Configuration descriptor +----------------------------------------------------------------------------------------------------------------------*/ + +static const st_ble_servs_desc_info_t gs_serv_changed_cli_cnfg = { + .attr_hdl = BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL, + .app_size = sizeof(uint16_t), + .desc_idx = BLE_GATS_SERV_CHGED_CLI_CNFG_IDX, + .db_size = BLE_GATS_SERV_CHGED_CLI_CNFG_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GATS_SetServChangedCliCnfg(const uint16_t *p_value) +{ + return R_BLE_SERVS_SetDesc(&gs_serv_changed_cli_cnfg, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GATS_GetServChangedCliCnfg(uint16_t *p_value) +{ + return R_BLE_SERVS_GetDesc(&gs_serv_changed_cli_cnfg, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gats_serv_changed_t(st_ble_gats_serv_changed_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GATS_SERV_CHGED_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->start_hdl, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->end_hdl, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gats_serv_changed_t(const st_ble_gats_serv_changed_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->start_hdl); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->end_hdl); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Service Changed characteristic descriptor definition */ +static const st_ble_servs_desc_info_t *gspp_serv_changed_descs[] = { + &gs_serv_changed_cli_cnfg, +}; + +/* Service Changed characteristic definition */ +static const st_ble_servs_char_info_t gs_serv_changed_char = { + .start_hdl = BLE_GATS_SERV_CHGED_DECL_HDL, + .end_hdl = BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL, + .char_idx = BLE_GATS_SERV_CHGED_IDX, + .app_size = sizeof(st_ble_gats_serv_changed_t), + .db_size = BLE_GATS_SERV_CHGED_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gats_serv_changed_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gats_serv_changed_t, + .pp_descs = gspp_serv_changed_descs, + .num_of_descs = ARRAY_SIZE(gspp_serv_changed_descs), +}; + +ble_status_t R_BLE_GATS_IndicateServChanged(uint16_t conn_hdl, const st_ble_gats_serv_changed_t *p_value) +{ + return R_BLE_SERVS_SendHdlVal(&gs_serv_changed_char, conn_hdl, (const void *)p_value, false); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Attribute server +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Attribute characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_serv_changed_char, +}; + +/* Generic Attribute service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_GATS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.h new file mode 100644 index 0000000000..2ba7f64500 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_gats.h @@ -0,0 +1,105 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gats.h + * Version : 1.0 + * Description : The header file for Generic Attribute service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gats Generic Attribute Service + * @{ + * @ingroup profile + * @brief The Generic Attribute Service contains generic information of the GATT attributes. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_GATS_H +#define R_BLE_GATS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Service Changed value structure. +*******************************************************************************/ +typedef struct { + uint16_t start_hdl; /**< Start of Affected Attribute Handle Range */ + uint16_t end_hdl; /**< End of Affected Attribute Handle Range */ +} st_ble_gats_serv_changed_t; + +/***************************************************************************//** + * @brief Send indication of Service Changed characteristic value to the remote device. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Characteristic value to send. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_IndicateServChanged(uint16_t conn_hdl, const st_ble_gats_serv_changed_t *p_value); + +/***************************************************************************//** + * @brief Set Service Changed cli cnfg descriptor value to the local GATT database. + * @param[in] p_value Descriptor value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_SetServChangedCliCnfg(const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Service Changed cli cnfg descriptor value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_GetServChangedCliCnfg(uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Attribute Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Attribute characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_GATS_SERV_CHGED_IDX, + BLE_GATS_SERV_CHGED_CLI_CNFG_IDX, +} st_ble_gats_char_idx_t; + +/***************************************************************************//** + * @brief Generic Attribute event type. +*******************************************************************************/ +typedef enum { + /* Service Changed */ + BLE_GATS_EVENT_SERV_CHGED_HDL_VAL_CNF = BLE_SERVS_ATTR_EVENT(BLE_GATS_SERV_CHGED_IDX, BLE_SERVS_HDL_VAL_CNF), +} e_ble_gats_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Attribute service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_GATS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.c new file mode 100644 index 0000000000..734cbc9d90 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.c @@ -0,0 +1,132 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_lss.c + * Version : 1.0 + * Description : The source file for LED Switch service. + **********************************************************************************************************************/ + +#include "r_ble_lss.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State Client Characteristic Configuration descriptor +----------------------------------------------------------------------------------------------------------------------*/ + +static const st_ble_servs_desc_info_t gs_switch_state_cli_cnfg = { + .attr_hdl = BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL, + .app_size = sizeof(uint16_t), + .desc_idx = BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, + .db_size = BLE_LSS_SWITCH_STATE_CLI_CNFG_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_LSS_SetSwitchStateCliCnfg(uint16_t conn_hdl, const uint16_t *p_value) +{ + return R_BLE_SERVS_SetDesc(&gs_switch_state_cli_cnfg, conn_hdl, (const void *)p_value); +} + +ble_status_t R_BLE_LSS_GetSwitchStateCliCnfg(uint16_t conn_hdl, uint16_t *p_value) +{ + return R_BLE_SERVS_GetDesc(&gs_switch_state_cli_cnfg, conn_hdl, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Switch State characteristic descriptor definition */ +static const st_ble_servs_desc_info_t *gspp_switch_state_descs[] = { + &gs_switch_state_cli_cnfg, +}; + +/* Switch State characteristic definition */ +static const st_ble_servs_char_info_t gs_switch_state_char = { + .start_hdl = BLE_LSS_SWITCH_STATE_DECL_HDL, + .end_hdl = BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL, + .char_idx = BLE_LSS_SWITCH_STATE_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_LSS_SWITCH_STATE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, + .pp_descs = gspp_switch_state_descs, + .num_of_descs = ARRAY_SIZE(gspp_switch_state_descs), +}; + +ble_status_t R_BLE_LSS_NotifySwitchState(uint16_t conn_hdl, const uint8_t *p_value) +{ + return R_BLE_SERVS_SendHdlVal(&gs_switch_state_char, conn_hdl, (const void *)p_value, true); +} + +/*---------------------------------------------------------------------------------------------------------------------- + LED Blink Rate characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* LED Blink Rate characteristic definition */ +static const st_ble_servs_char_info_t gs_blink_rate_char = { + .start_hdl = BLE_LSS_BLINK_RATE_DECL_HDL, + .end_hdl = BLE_LSS_BLINK_RATE_VAL_HDL, + .char_idx = BLE_LSS_BLINK_RATE_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_LSS_BLINK_RATE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_LSS_SetBlinkRate(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_blink_rate_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_LSS_GetBlinkRate(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_blink_rate_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + LED Switch server +----------------------------------------------------------------------------------------------------------------------*/ + +/* LED Switch characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_switch_state_char, + &gs_blink_rate_char, +}; + +/* LED Switch service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_LSS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.h new file mode 100644 index 0000000000..a1a7607509 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/qe_gen/ble/r_ble_lss.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_lss.h + * Version : 1.0 + * Description : The header file for LED Switch service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup lss LED Switch Service + * @{ + * @ingroup profile + * @brief This service exposes a control point to allow a peer device to control LEDs and switched on the device. + **********************************************************************************************************************/ + +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_LSS_H +#define R_BLE_LSS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Send notification of Switch State characteristic value to the remote device. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Characteristic value to send. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_NotifySwitchState(uint16_t conn_hdl, const uint8_t *p_value); + +/***************************************************************************//** + * @brief Set Switch State cli cnfg descriptor value to the local GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Descriptor value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_SetSwitchStateCliCnfg(uint16_t conn_hdl, const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Switch State cli cnfg descriptor value from the local GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_GetSwitchStateCliCnfg(uint16_t conn_hdl, uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + LED Blink Rate Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set LED Blink Rate characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_SetBlinkRate(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get LED Blink Rate characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_GetBlinkRate(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + LED Switch Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief LED Switch characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_LSS_SWITCH_STATE_IDX, + BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, + BLE_LSS_BLINK_RATE_IDX, +} e_ble_lss_char_idx_t; + +/***************************************************************************//** + * @brief LED Switch event type. +*******************************************************************************/ +typedef enum { + /* Switch State */ + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_WRITE_REQ), + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_WRITE_COMP), + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_READ_REQ), + /* LED Blink Rate */ + BLE_LSS_EVENT_BLINK_RATE_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_WRITE_REQ), + BLE_LSS_EVENT_BLINK_RATE_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_WRITE_COMP), + BLE_LSS_EVENT_BLINK_RATE_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_READ_REQ), +} e_ble_lss_event_t; + +/***************************************************************************//** + * @brief Initialize LED Switch service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_LSS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board.h new file mode 100644 index 0000000000..ddd7c672bf --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA4W1_EK BSP for the EK-RA4W1 + * @brief BSP for the EK-RA4W1 + * + * The EK-RA4W1 is a development kit for the Renesas RA Flex RA4W1 microcontroller. This board has connections + * for PMOD and USB as well as headers for Arduino shield modules. An onboard Bluetooth antenna is available with an + * optional connection for an external antenna. + * + * @note This board does not ship with main or subclock oscillators populated. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA4W1_EK + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS (1000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA4W1_EK) */ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.c new file mode 100644 index 0000000000..79e035fb9f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_EK_RA4W1_INIT + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA4W1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_EK_RA4W1_INIT) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.h new file mode 100644 index 0000000000..1355cd0724 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_init.h @@ -0,0 +1,53 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_EK_RA4W1 + * @defgroup BOARD_EK_RA4W1_INIT + * @brief Board specific code for the EK-RA4W1 + * + * This include file is specific to the EK-RA4W1. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +#endif + +/** @} (end defgroup BOARD_EK_RA4W1_INIT) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c new file mode 100644 index 0000000000..a299d2b08d --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_EK_RA4W1_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA4W1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_01_PIN_06, ///< LED0 + (uint16_t) BSP_IO_PORT_04_PIN_04, ///< LED1 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */ +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_EK_RA4W1_LEDS) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h new file mode 100644 index 0000000000..013d6c63b5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_EK_RA4W1 + * @defgroup BOARD_EK_RA4W1_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EK-RA4W1. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED0 = 0, ///< LED0 + BSP_LED_LED1 = 1, ///< LED1 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +#endif + +/** @} (end defgroup BOARD_EK_RA4W1_LEDS) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/bsp_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/bsp_api.h new file mode 100644 index 0000000000..54e0465e8b --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/bsp_api.h @@ -0,0 +1,101 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "../../inc/fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +/* BSP Common Includes. */ +#include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ +#include "../../src/bsp/mcu/all/bsp_register_protection.h" +#include "../../src/bsp/mcu/all/bsp_irq.h" +#include "../../src/bsp/mcu/all/bsp_io.h" +#include "../../src/bsp/mcu/all/bsp_group_irq.h" +#include "../../src/bsp/mcu/all/bsp_clocks.h" +#include "../../src/bsp/mcu/all/bsp_module_stop.h" + +/* Factory MCU information. */ +#include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ +#include "../../src/bsp/mcu/all/bsp_delay.h" + +#include "../../src/bsp/mcu/all/bsp_mcu_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h new file mode 100644 index 0000000000..61cbae1495 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h @@ -0,0 +1,12575 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup BLE_API BLE Interface + * @brief Interface for Bluetooth Low Energy functions. + * + * @section BLE_API_SUMMARY Summary + * The BLE interface for the Bluetooth Low Energy (BLE) peripheral provides Bluetooth Low Energy functionality. + * + * The Bluetooth Low Energy interface can be implemented by: + * - @ref BLE + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_BLE_API_H +#define R_BLE_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +#include "r_ble_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BLE_API_VERSION_MAJOR (1U) +#define BLE_API_VERSION_MINOR (0U) + +/* =================================================== Main Macro =================================================== */ + +/** + * @def BLE_VERSION_MAJOR + * BLE Module Major Version. + */ +#define BLE_VERSION_MAJOR (0x0000) + +/** + * @def BLE_VERSION_MINOR + * BLE Module Minor Version. + */ +#define BLE_VERSION_MINOR (0x0009) + +/** + * @def BLE_LIB_ALL_FEATS + * BLE Protocol Stack Library All Features type. + */ +#define BLE_LIB_ALL_FEATS (0x00) + +/** + * @def BLE_LIB_BALANCE + * BLE Protocol Stack Library Balance type. + */ +#define BLE_LIB_BALANCE (0x01) + +/** + * @def BLE_LIB_COMPACT + * BLE Protocol Stack Library Compacy type. + */ +#define BLE_LIB_COMPACT (0x02) + +/* =============================================== Spec Error Group ID ============================================== */ +#define BLE_ERR_GROUP_HC (0x1000) +#define BLE_ERR_GROUP_GAP (0x2000) +#define BLE_ERR_GROUP_GATT (0x3000) +#define BLE_ERR_GROUP_L2CAP (0x4000) +#define BLE_ERR_GROUP_VS (0x5000) + +/******************************************************************************************************************//** + * @typedef ble_status_t + **********************************************************************************************************************/ +typedef uint16_t ble_status_t; + +/* error code */ +enum RBLE_STATUS_enum +{ + BLE_SUCCESS = 0x0000, + + /* commom error code */ + BLE_ERR_INVALID_PTR = 0x0001, + BLE_ERR_INVALID_DATA = 0x0002, + BLE_ERR_INVALID_ARG = 0x0003, + BLE_ERR_INVALID_FUNC = 0x0004, + BLE_ERR_INVALID_CHAN = 0x0005, + BLE_ERR_INVALID_MODE = 0x0006, + BLE_ERR_UNSUPPORTED = 0x0007, + BLE_ERR_INVALID_STATE = 0x0008, + BLE_ERR_INVALID_OPERATION = 0x0009, + BLE_ERR_ALREADY_IN_PROGRESS = 0x000A, + BLE_ERR_CONTEXT_FULL = 0x000B, + BLE_ERR_MEM_ALLOC_FAILED = 0x000C, + BLE_ERR_NOT_FOUND = 0x000D, + BLE_ERR_INVALID_HDL = 0x000E, + BLE_ERR_DISCONNECTED = 0x000F, + BLE_ERR_LIMIT_EXCEEDED = 0x0010, + BLE_ERR_RSP_TIMEOUT = 0x0011, + BLE_ERR_NOT_YET_READY = 0x0012, + BLE_ERR_UNSPECIFIED = 0x0013, + + /* HCI Spec Error */ + BLE_ERR_HC_UNKNOWN_HCI_CMD = 0x1001, + BLE_ERR_HC_NO_CONN = 0x1002, + BLE_ERR_HC_HW_FAIL = 0x1003, + BLE_ERR_HC_PAGE_TO = 0x1004, + BLE_ERR_HC_AUTH_FAIL = 0x1005, + BLE_ERR_HC_KEY_MISSING = 0x1006, + BLE_ERR_HC_MEM_FULL = 0x1007, + BLE_ERR_HC_CONN_TO = 0x1008, + BLE_ERR_HC_MAX_NUM_OF_CONN = 0x1009, + BLE_ERR_HC_MAX_NUM_OF_SCO_CONN = 0x100A, + BLE_ERR_HC_ACL_CONN_ALREADY_EXISTS = 0x100B, + BLE_ERR_HC_CMD_DISALLOWED = 0x100C, + BLE_ERR_HC_HOST_REJ_LIMITED_RESRC = 0x100D, + BLE_ERR_HC_HOST_REJ_SEC_REASONS = 0x100E, + BLE_ERR_HC_HOST_REJ_PERSONAL_DEV = 0x100F, + BLE_ERR_HC_HOST_TO = 0x1010, + BLE_ERR_HC_UNSPRT_FEAT_OR_PARAM = 0x1011, + BLE_ERR_HC_INVALID_HCI_CMD_PARAM = 0x1012, + BLE_ERR_HC_OTHER_END_TERM_USER = 0x1013, + BLE_ERR_HC_OTHER_END_TERM_LOW_RESRC = 0x1014, + BLE_ERR_HC_OTHER_END_TERM_PW_OFF = 0x1015, + BLE_ERR_HC_CONN_TERM_BY_LOCAL_HOST = 0x1016, + BLE_ERR_HC_REPEATED_ATTEMPTS = 0x1017, + BLE_ERR_HC_PAIRING_NOT_ALLOWED = 0x1018, + BLE_ERR_HC_UNKNOWN_LMP_PDU = 0x1019, + BLE_ERR_HC_UNSPRT_REM_FEAT = 0x101A, + BLE_ERR_HC_SCO_OFFSET_REJ = 0x101B, + BLE_ERR_HC_SCO_INTERVAL_REJ = 0x101C, + BLE_ERR_HC_SCO_AIR_MODE_REJ = 0x101D, + BLE_ERR_HC_INVALID_LMP_PARAM = 0x101E, + BLE_ERR_HC_UNSPECIFIED_ERR = 0x101F, + BLE_ERR_HC_UNSPRT_LMP_PARAM_VAL = 0x1020, + BLE_ERR_HC_ROLE_CHANGE_NOT_ALLOWED = 0x1021, + BLE_ERR_HC_LMP_RSP_TO = 0x1022, + BLE_ERR_HC_LMP_ERR_TX_COLLISION = 0x1023, + BLE_ERR_HC_LMP_PDU_NOT_ALLOWED = 0x1024, + BLE_ERR_HC_ENC_MODE_NOT_ACCEPTABLE = 0x1025, + BLE_ERR_HC_UNIT_KEY_USED = 0x1026, + BLE_ERR_HC_QOS_IS_NOT_SPRT = 0x1027, + BLE_ERR_HC_INSTANT_PASSED = 0x1028, + BLE_ERR_HC_PAIRING_UNIT_KEY_NOT_SPRT = 0x1029, + BLE_ERR_HC_DIFF_TRANSACTION_COLLISION = 0x102A, + BLE_ERR_HC_QOS_UNACCEPTABLE_PARAM = 0x102C, + BLE_ERR_HC_QOS_REJ = 0x102D, + BLE_ERR_HC_CH_CLASSIFICATION_NOT_SPRT = 0x102E, + BLE_ERR_HC_INSUFFICIENT_SEC = 0x102F, + BLE_ERR_HC_PARAM_OUT_OF_MANDATORY_RANGE = 0x1030, + BLE_ERR_HC_ROLE_SWITCH_PENDING = 0x1032, + BLE_ERR_HC_RESERVED_SLOT_VIOLATION = 0x1034, + BLE_ERR_HC_ROLE_SWITCH_FAIL = 0x1035, + BLE_ERR_HC_EXT_INQUIRY_RSP_TOO_LARGE = 0x1036, + BLE_ERR_HC_SSP_NOT_SPRT_BY_HOST = 0x1037, + BLE_ERR_HC_HOST_BUSY_PAIRING = 0x1038, + BLE_ERR_HC_CONN_REJ_NO_SUIT_CH_FOUND = 0x1039, + BLE_ERR_HC_CTRL_BUSY = 0x103A, + BLE_ERR_HC_UNACCEPTEBALE_CONN_INTERVAL = 0x103B, + BLE_ERR_HC_ADV_TO = 0x103C, + BLE_ERR_HC_CONN_TREM_DUE_TO_MIC_FAIL = 0x103D, + BLE_ERR_HC_CONN_FAIL_TO_BE_EST = 0x103E, + BLE_ERR_HC_MAC_CONN_FAIL = 0x103F, + BLE_ERR_HC_COARSE_CLK_ADJUST_REJ = 0x1040, + BLE_ERR_HC_TYPE0_SUBMAP_NOT_DEFINED = 0x1041, + BLE_ERR_HC_UNKNOWN_ADV_ID = 0x1042, + BLE_ERR_HC_LIMIT_REACHED = 0x1043, + BLE_ERR_HC_OP_CANCELLED_BY_HOST = 0x1044, + + /* SMP Spec Error */ + BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL = 0x2001, + BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE = 0x2002, + BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET = 0x2003, + BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH = 0x2004, + BLE_ERR_SMP_LE_PAIRING_NOT_SPRT = 0x2005, + BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE = 0x2006, + BLE_ERR_SMP_LE_CMD_NOT_SPRT = 0x2007, + BLE_ERR_SMP_LE_UNSPECIFIED_REASON = 0x2008, + BLE_ERR_SMP_LE_REPEATED_ATTEMPTS = 0x2009, + BLE_ERR_SMP_LE_INVALID_PARAM = 0x200A, + BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL = 0x200B, + BLE_ERR_SMP_LE_NUM_COMP_FAIL = 0x200C, + BLE_ERR_SMP_LE_BREDR_PAIRING_IN_PROGRESS = 0x200D, + BLE_ERR_SMP_LE_CT_KEY_GEN_NOT_ALLOWED = 0x200E, + BLE_ERR_SMP_LE_DISCONNECTED = 0x200F, + BLE_ERR_SMP_LE_TO = 0x2011, + BLE_ERR_SMP_LE_LOC_KEY_MISSING = 0x2014, + + /* GATT Spec Error */ + BLE_ERR_GATT_INVALID_HANDLE = 0x3001, + BLE_ERR_GATT_READ_NOT_PERMITTED = 0x3002, + BLE_ERR_GATT_WRITE_NOT_PERMITTED = 0x3003, + BLE_ERR_GATT_INVALID_PDU = 0x3004, + BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION = 0x3005, + BLE_ERR_GATT_REQUEST_NOT_SUPPORTED = 0x3006, + BLE_ERR_GATT_INVALID_OFFSET = 0x3007, + BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION = 0x3008, + BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL = 0x3009, + BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND = 0x300A, + BLE_ERR_GATT_ATTRIBUTE_NOT_LONG = 0x300B, + BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE = 0x300C, + BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN = 0x300D, + BLE_ERR_GATT_UNLIKELY_ERROR = 0x300E, + BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION = 0x300F, + BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE = 0x3010, + BLE_ERR_GATT_INSUFFICIENT_RESOURCES = 0x3011, + + /* defined in CSS */ + BLE_ERR_GATT_WRITE_REQ_REJECTED = 0x30FC, + BLE_ERR_GATT_CCCD_IMPROPERLY_CFG = 0x30FD, + BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS = 0x30FE, + BLE_ERR_GATT_OUT_OF_RANGE = 0x30FF, + + /* L2CAP Spec Error */ + BLE_ERR_L2CAP_PSM_NOT_SUPPORTED = 0x4002, + BLE_ERR_L2CAP_NO_RESOURCE = 0x4004, + BLE_ERR_L2CAP_INSUF_AUTHEN = 0x4005, + BLE_ERR_L2CAP_INSUF_AUTHOR = 0x4006, + BLE_ERR_L2CAP_INSUF_ENC_KEY_SIZE = 0x4007, + BLE_ERR_L2CAP_REFUSE_INSUF_ENC = 0x4008, + BLE_ERR_L2CAP_REFUSE_INVALID_SCID = 0x4009, + BLE_ERR_L2CAP_REFUSE_SCID_ALREADY_ALLOC = 0x400A, + BLE_ERR_L2CAP_REFUSE_UNACCEPTABLE_PARAM = 0x400B, +}; + +/*******************************************************************************************************************//** + * @} (end addtogroup BLE_API) + **********************************************************************************************************************/ + +/* =================================================== GAP Macro ==================================================== */ + +/** @addtogroup GAP_API + * @ingroup BLE + * @{ + */ + +/** + * @ingroup GAP_API + * @def BLE_BD_ADDR_LEN + * Bluetooth Device Address Size + */ +#define BLE_BD_ADDR_LEN (0x06) + +/** + * @def BLE_MASTER + * Master Role. + */ +#define BLE_MASTER (0x00) + +/** + * @def BLE_SLAVE + * Slave Role. + */ +#define BLE_SLAVE (0x01) + +/* Bluetooth Device Address Type */ + +/** + * @def BLE_GAP_ADDR_PUBLIC + * Public Address. + */ +#define BLE_GAP_ADDR_PUBLIC (0x00) + +/** + * @def BLE_GAP_ADDR_RAND + * Random Address. + */ +#define BLE_GAP_ADDR_RAND (0x01) + +/** + * @def BLE_GAP_ADDR_RPA_ID_PUBLIC + * @brief Resolvable Private Address. + * @details If the IRK of local device has not been registered in Resolving List, + * public address is used. + */ +#define BLE_GAP_ADDR_RPA_ID_PUBLIC (0x02) + +/** + * @def BLE_GAP_ADDR_RPA_ID_RANDOM + * @brief Resolvable Private Address. + * @details If the IRK of local device has not been registered in Resolving List, + * random address is used. + */ +#define BLE_GAP_ADDR_RPA_ID_RANDOM (0x03) + +/* Adv Flag */ + +/** + * @def BLE_GAP_AD_FLAGS_LE_LIM_DISC_MODE + * @brief LE Limited Discoverable Mode flag used in AD type. + */ +#define BLE_GAP_AD_FLAGS_LE_LIM_DISC_MODE (0x01) + +/** + * @def BLE_GAP_AD_FLAGS_LE_GEN_DISC_MODE + * @brief LE General Discoverable Mode flag used in AD type. + */ +#define BLE_GAP_AD_FLAGS_LE_GEN_DISC_MODE (0x02) + +/** + * @def BLE_GAP_AD_FLAGS_BR_EDR_NOT_SUPPORTED + * @brief BR/EDR Not Supported flag used in AD type. + */ +#define BLE_GAP_AD_FLAGS_BR_EDR_NOT_SUPPORTED (0x04) + +/** + * @def BLE_GAP_ADV_DATA_MODE + * @brief Advertising data. + */ +#define BLE_GAP_ADV_DATA_MODE (0x00) + +/** + * @def BLE_GAP_SCAN_RSP_DATA_MODE + * @brief Scan response data. + */ +#define BLE_GAP_SCAN_RSP_DATA_MODE (0x01) + +/** + * @def BLE_GAP_PERD_ADV_DATA_MODE + * @brief Periodic advertising data. + */ +#define BLE_GAP_PERD_ADV_DATA_MODE (0x02) + +/* Advertising channel map */ + +/** + * @def BLE_GAP_ADV_CH_37 + * @brief Use 37 CH. + */ +#define BLE_GAP_ADV_CH_37 (0x01) + +/** + * @def BLE_GAP_ADV_CH_38 + * @brief Use 38 CH. + */ +#define BLE_GAP_ADV_CH_38 (0x02) + +/** + * @def BLE_GAP_ADV_CH_39 + * @brief Use 39 CH. + */ +#define BLE_GAP_ADV_CH_39 (0x04) + +/** + * @def BLE_GAP_ADV_CH_ALL + * @brief Use 37 - 39 CH. + */ +#define BLE_GAP_ADV_CH_ALL (0x07) + +/* Scan Type */ + +/** + * @def BLE_GAP_SCAN_PASSIVE + * @brief Passive Scan. + */ +#define BLE_GAP_SCAN_PASSIVE (0x00) + +/** + * @def BLE_GAP_SCAN_ACTIVE + * @brief Active Scan. + */ +#define BLE_GAP_SCAN_ACTIVE (0x01) + +/* Scan interval */ + +/** + * @def BLE_GAP_SCAN_INTV_MIN + * @brief Active Scan. + */ +#define BLE_GAP_SCAN_INTV_MIN (0x0004) + +/* Filter duplicates */ + +/** + * @def BLE_GAP_SCAN_FILT_DUPLIC_DISABLE + * @brief Duplicate filter disabled. + */ +#define BLE_GAP_SCAN_FILT_DUPLIC_DISABLE (0x00) + +/** + * @def BLE_GAP_SCAN_FILT_DUPLIC_ENABLE + * @brief Duplicate filter enabled. + */ +#define BLE_GAP_SCAN_FILT_DUPLIC_ENABLE (0x01) + +/** + * @def BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD + * @brief Duplicate filtering enabled, reset for each scan period. + */ +#define BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD (0x02) + +/* Scan filter policy */ + +/** + * @def BLE_GAP_SCAN_ALLOW_ADV_ALL + * @brief Accept all advertising and scan response PDUs except directed advertising PDUs not addressed to local device. + */ +#define BLE_GAP_SCAN_ALLOW_ADV_ALL (0x00) + +/** + * @def BLE_GAP_SCAN_ALLOW_ADV_WLST + * @brief Accept only advertising and scan response PDUs from remote devices + * whose address is registered in the White List. + * Directed advertising PDUs which are not addressed to local device is ignored. + */ +#define BLE_GAP_SCAN_ALLOW_ADV_WLST (0x01) + +/** + * @def BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED + * @brief Accept all advertising and scan response PDUs except directed advertising PDUs + * whose the target address is identity address but doesn't address local device. + * However directed advertising PDUs whose the target address is the local resolvable private address + * are accepted. + */ +#define BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED (0x02) + +/** + * @def BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST + * @brief Accept all advertising and scan response PDUs.
+ * The following are excluded. + * - Advertising and scan response PDUs where the advertiser's identity address is not in the White List. + * - Directed advertising PDUs whose the target address is identity address + * but doesn't address local device. However directed advertising PDUs + * whose the target address is the local resolvable private address are accepted. + */ +#define BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST (0x03) + +/* Initiator Filter policy */ + +/** + * @def BLE_GAP_INIT_FILT_USE_ADDR + * @brief White List is not used. + */ +#define BLE_GAP_INIT_FILT_USE_ADDR (0x00) + +/** + * @def BLE_GAP_INIT_FILT_USE_WLST + * @brief White List is used. + */ +#define BLE_GAP_INIT_FILT_USE_WLST (0x01) + +/** + * @def BLE_GAP_DATA_0_CLEAR + * @brief Clear the advertising data/scan response data/periodic advertising data in the advertising set. + */ +#define BLE_GAP_DATA_0_CLEAR (0x01) + +/** + * @def BLE_GAP_DATA_0_DID_UPD + * @brief Update Advertising DID without changing advertising data. + */ +#define BLE_GAP_DATA_0_DID_UPD (0x02) + +/* Privacy Mode related Definitions */ + +/** + * @def BLE_GAP_NET_PRIV_MODE + * @brief Network Privacy Mode. + */ +#define BLE_GAP_NET_PRIV_MODE (0x00) + +/** + * @def BLE_GAP_DEV_PRIV_MODE + * @brief Device Privacy Mode. + */ +#define BLE_GAP_DEV_PRIV_MODE (0x01) + +/** + * @def BLE_GAP_REM_FEATURE_SIZE + * @brief The length of the features supported by a remote device. + */ +#define BLE_GAP_REM_FEATURE_SIZE (0x08) + +/* Authorization Flag Definitions */ + +/** + * @def BLE_GAP_NOT_AUTHORIZED + * @brief Not authorize the remote device. + */ +#define BLE_GAP_NOT_AUTHORIZED (0x00) + +/** + * @def BLE_GAP_AUTHORIZED + * @brief Authorize the remote device. + */ +#define BLE_GAP_AUTHORIZED (0x01) + +/* Remove ADV Set related */ + +/** + * @def BLE_GAP_RMV_ADV_SET_REM_OP + * @brief Delete an advertising set. + */ +#define BLE_GAP_RMV_ADV_SET_REM_OP (0x01) + +/** + * @def BLE_GAP_RMV_ADV_SET_CLR_OP + * @brief Delete all the advertising sets. + */ +#define BLE_GAP_RMV_ADV_SET_CLR_OP (0x02) + +/* scan procedure type */ + +/** + * @def BLE_GAP_SC_PROC_GEN + * @brief General Discovery Procedure. + */ +#define BLE_GAP_SC_PROC_GEN (0x02) + +/** + * @def BLE_GAP_SC_PROC_LIM + * @brief Limited Discovery Procedure. + */ +#define BLE_GAP_SC_PROC_LIM (0x01) + +/** + * @def BLE_GAP_SC_PROC_OBS + * @brief Observation Procedure. + */ +#define BLE_GAP_SC_PROC_OBS (0x00) + +/* White List Operation */ +/* Resolvable List Operation */ +/* Periodic advertiser List Operation */ + +/** + * @def BLE_GAP_LIST_ADD_DEV + * @brief Add the device to the list. + */ +#define BLE_GAP_LIST_ADD_DEV (0x01) + +/** + * @def BLE_GAP_LIST_REM_DEV + * @brief Delete the device from the list. + */ +#define BLE_GAP_LIST_REM_DEV (0x02) + +/** + * @def BLE_GAP_LIST_CLR + * @brief Clear the list. + */ +#define BLE_GAP_LIST_CLR (0x03) + +/** + * @def BLE_GAP_WHITE_LIST_MAX_ENTRY + * @brief The maximum entry number of White List. + */ +#define BLE_GAP_WHITE_LIST_MAX_ENTRY (0x04) + +/** + * @def BLE_GAP_RSLV_LIST_MAX_ENTRY + * @brief The maximum entry number of Resolving List. + */ +#define BLE_GAP_RSLV_LIST_MAX_ENTRY (0x08) + +/** + * @def BLE_GAP_PERD_LIST_MAX_ENTRY + * @brief The maximum entry number of Periodic Advertiser List. + */ +#define BLE_GAP_PERD_LIST_MAX_ENTRY (0x04) + +/* Set Address Resolution */ + +/** + * @def BLE_GAP_RPA_DISABLED + * @brief Disable RPA generation/resolution. + */ +#define BLE_GAP_RPA_DISABLED (0x00) + +/** + * @def BLE_GAP_RPA_ENABLED + * @brief Enable RPA generation/resolution. + */ +#define BLE_GAP_RPA_ENABLED (0x01) + +/* Set Local IRK type */ + +/** + * @def BLE_GAP_RL_LOC_KEY_ALL_ZERO + * @brief All-zero IRK. + */ +#define BLE_GAP_RL_LOC_KEY_ALL_ZERO (0x00) + +/** + * @def BLE_GAP_RL_LOC_KEY_REGISTERED + * @brief The IRK registered by R_BLE_GAP_SetLocIdInfo(). + */ +#define BLE_GAP_RL_LOC_KEY_REGISTERED (0x01) + +/* Number of advertising set supported */ + +/** + * @def BLE_MAX_NO_OF_ADV_SETS_SUPPORTED + * @brief The maximum number of advertising set for the Abstraction API. + */ +#define BLE_MAX_NO_OF_ADV_SETS_SUPPORTED (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) + +/* Advertising Properties */ +/* Legacy Advertising PDU */ +#if (BLE_CFG_LIBRARY_TYPE == 0) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_IND + * @brief Connectable and scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_IND (0x0013) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND + * @brief Connectable directed (low duty cycle) Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND (0x0015) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND + * @brief Connectable directed (high duty cycle) Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND (0x001D) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_SCAN_IND + * @brief Scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_SCAN_IND (0x0012) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND + * @brief Non-connectable and non-scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND (0x0010) + +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_IND + * @brief Connectable and scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_IND (0x0000) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND + * @brief Connectable directed (low duty cycle) Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND (0x0004) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND + * @brief Connectable directed (high duty cycle) Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND (0x0001) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_SCAN_IND + * @brief Scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_SCAN_IND (0x0002) + +/** + * @def BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND + * @brief Non-connectable and non-scannable undirected Legacy Advertising Packet. + */ + #define BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND (0x0003) + +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + +/* Extended Advertising PDU */ + +/** + * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT + * @brief Connectable and non-scannable undirected Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT (0x0001) + +/** + * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT + * @brief Connectable and non-scannable directed (low duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT (0x0005) + +/** + * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT + * @brief Connectable and non-scannable directed (high duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT (0x000D) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT + * @brief Non-connectable and scannable undirected Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT (0x0002) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT + * @brief Non-connectable and scannable directed (low duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT (0x0006) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT + * @brief Non-connectable and scannable directed (high duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT (0x000E) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT + * @brief Non-connectable and non-scannable undirected Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT (0x0000) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT + * @brief Non-connectable and non-scannable directed (low duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT (0x0004) + +/** + * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT + * @brief Non-connectable and non-scannable directed (high duty cycle) Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT (0x000C) + +/* Anonymous advertising */ + +/** + * @def BLE_GAP_EXT_PROP_ADV_ANONYMOUS + * @brief Omit the advertiser address from Extended Advertising Packet. + */ +#define BLE_GAP_EXT_PROP_ADV_ANONYMOUS (0x0020) + +/** + * @def BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER + * @brief Indicate that the advertising data includes TX Power. + */ +#define BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER (0x0040) + +/* Advertising Filter Policy */ + +/** + * @def BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY + * @brief Process scan and connection requests from all devices. + */ +#define BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY (0x00) + +/** + * @def BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY + * @brief Process connection requests from all devices and scan requests from only devices that are in the White List. + */ +#define BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY (0x01) + +/** + * @def BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST + * @brief Process scan requests from all devices and connection requests from only devices that are in the White List. + */ +#define BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST (0x02) + +/** + * @def BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST + * @brief Process scan and connection requests from only devices in the White List. + */ +#define BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST (0x03) + +/* Primary & Secondary Advertising PHY */ + +/** + * @def BLE_GAP_ADV_PHY_1M + * @brief Use 1M PHY. + */ +#define BLE_GAP_ADV_PHY_1M (0x01) + +/** + * @def BLE_GAP_ADV_PHY_2M + * @brief Use 2M PHY. + */ +#define BLE_GAP_ADV_PHY_2M (0x02) + +/** + * @def BLE_GAP_ADV_PHY_CD + * @brief Use Coded PHY. + */ +#define BLE_GAP_ADV_PHY_CD (0x03) + +/* Scan Request Notification Enable */ + +/** + * @def BLE_GAP_SCAN_REQ_NTF_DISABLE + * @brief Disable Scan Request Notification. + */ +#define BLE_GAP_SCAN_REQ_NTF_DISABLE (0x00) + +/** + * @def BLE_GAP_SCAN_REQ_NTF_ENABLE + * @brief Enable Scan Request Notification. + */ +#define BLE_GAP_SCAN_REQ_NTF_ENABLE (0x01) + +/* Periodic Advertising Properties */ + +/** + * @def BLE_GAP_PERD_PROP_TX_POWER + * @brief Indicate that periodic advertising data includes Tx Power. + */ +#define BLE_GAP_PERD_PROP_TX_POWER (0x0040) + +/** + * @def BLE_GAP_INVALID_ADV_HDL + * @brief Invalid advertising handle. + */ +#define BLE_GAP_INVALID_ADV_HDL (0xFF) + +/** + * @def BLE_GAP_SET_PHYS_HOST_PREF_1M + * @brief Use 1M PHY. + */ +#define BLE_GAP_SET_PHYS_HOST_PREF_1M (0x01) + +/** + * @def BLE_GAP_SET_PHYS_HOST_PREF_2M + * @brief Use 2M PHY. + */ +#define BLE_GAP_SET_PHYS_HOST_PREF_2M (0x02) + +/** + * @def BLE_GAP_SET_PHYS_HOST_PREF_CD + * @brief Use Coded PHY. + */ +#define BLE_GAP_SET_PHYS_HOST_PREF_CD (0x04) + +/** + * @def BLE_GAP_SET_PHYS_OP_HOST_NO_PREF + * @brief No preferred coding. + */ +#define BLE_GAP_SET_PHYS_OP_HOST_NO_PREF (0x00) + +/** + * @def BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2 + * @brief Use S=2 coding. + */ +#define BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2 (0x01) + +/** + * @def BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8 + * @brief Use S=8 coding. + */ +#define BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8 (0x02) + +/* connection update parameter */ + +/** + * @def BLE_GAP_CONN_UPD_MODE_REQ + * @brief Request for updating the connection parameters. + */ +#define BLE_GAP_CONN_UPD_MODE_REQ (0x01) + +/** + * @def BLE_GAP_CONN_UPD_MODE_RSP + * @brief Reply a connection parameter update request. + */ +#define BLE_GAP_CONN_UPD_MODE_RSP (0x02) + +/* connection update response */ + +/** + * @def BLE_GAP_CONN_UPD_ACCEPT + * @brief Accept the update request. + */ +#define BLE_GAP_CONN_UPD_ACCEPT (0x0000) + +/** + * @def BLE_GAP_CONN_UPD_REJECT + * @brief Reject the update request. + */ +#define BLE_GAP_CONN_UPD_REJECT (0x0001) + +/* channel map size */ + +/** + * @def BLE_GAP_CH_MAP_SIZE + * @brief The size of channel map. + */ +#define BLE_GAP_CH_MAP_SIZE (0x05) + +/** + * @def BLE_GAP_INVALID_CONN_HDL + * @brief Invalid Connection handle. + */ +#define BLE_GAP_INVALID_CONN_HDL (0xFFFF) + +/** + * @def BLE_GAP_NOT_USE_CONN_HDL + * @brief This macro indicates that connection handle is not used. + */ +#define BLE_GAP_NOT_USE_CONN_HDL BLE_GAP_INVALID_CONN_HDL + +/** + * @def BLE_GAP_INIT_CONN_HDL + * @brief Initial Connection handle. + */ +#define BLE_GAP_INIT_CONN_HDL BLE_GAP_INVALID_CONN_HDL + +/** + * @def BLE_GAP_PAIRING_ACCEPT + * @brief Accept a request regarding pairing. + */ +#define BLE_GAP_PAIRING_ACCEPT (0x00) + +/** + * @def BLE_GAP_PAIRING_REJECT + * @brief Reject a request regarding pairing. + */ +#define BLE_GAP_PAIRING_REJECT (0x01) + +/** + * @def BLE_GAP_LTK_REQ_ACCEPT + * @brief Reply for the LTK request. + */ +#define BLE_GAP_LTK_REQ_ACCEPT (0x00) + +/** + * @def BLE_GAP_LTK_REQ_DENY + * @brief Reject the LTK request. + */ +#define BLE_GAP_LTK_REQ_DENY (0x01) + +/** + * @def BLE_GAP_LESC_PASSKEY_ENTRY_STARTED + * @brief Notify that passkey entry started. + */ +#define BLE_GAP_LESC_PASSKEY_ENTRY_STARTED (0x00) + +/** + * @def BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED + * @brief Notify that passkey digit entered. + */ +#define BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED (0x01) + +/** + * @def BLE_GAP_LESC_PASSKEY_DIGIT_ERASED + * @brief Notify that passkey digit erased. + */ +#define BLE_GAP_LESC_PASSKEY_DIGIT_ERASED (0x02) + +/** + * @def BLE_GAP_LESC_PASSKEY_CLEARED + * @brief Notify that passkey cleared. + */ +#define BLE_GAP_LESC_PASSKEY_CLEARED (0x03) + +/** + * @def BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED + * @brief Notify that passkey entry completed. + */ +#define BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED (0x04) + +/** + * @def BLE_GAP_SEC_MITM_BEST_EFFORT + * @brief MITM Protection not required. + */ +#define BLE_GAP_SEC_MITM_BEST_EFFORT (0x00) + +/** + * @def BLE_GAP_SEC_MITM_STRICT + * @brief MITM Protection required. + */ +#define BLE_GAP_SEC_MITM_STRICT (0x01) + +/** + * @def BLE_GAP_KEY_DIST_ENCKEY + * @brief LTK + */ +#define BLE_GAP_KEY_DIST_ENCKEY (0x01) + +/** + * @def BLE_GAP_KEY_DIST_IDKEY + * @brief IRK and Identity Address. + */ +#define BLE_GAP_KEY_DIST_IDKEY (0x02) + +/** + * @def BLE_GAP_KEY_DIST_SIGNKEY + * @brief CSRK + */ +#define BLE_GAP_KEY_DIST_SIGNKEY (0x04) + +/** + * @def BLE_GAP_ID_ADDR_SIZE + * @brief The size of identity address. + */ +#define BLE_GAP_ID_ADDR_SIZE (0x07) + +/** + * @def BLE_GAP_IRK_SIZE + * @brief The size of IRK. + */ +#define BLE_GAP_IRK_SIZE (0x10) + +/** + * @def BLE_GAP_CSRK_SIZE + * @brief The size of CSRK. + */ +#define BLE_GAP_CSRK_SIZE (0x10) + +/** + * @def BLE_GAP_LTK_SIZE + * @brief The size of LTK. + */ +#define BLE_GAP_LTK_SIZE (0x10) + +/** + * @def BLE_GAP_EDIV_SIZE + * @brief The size of EDIV. + */ +#define BLE_GAP_EDIV_SIZE (0x02) + +/** + * @def BLE_GAP_RAND_64_BIT_SIZE + * @brief The size of Rand. + */ +#define BLE_GAP_RAND_64_BIT_SIZE (0x08) + +/** + * @def BLE_GAP_UNAUTH_PAIRING + * @brief Unauthenticated pairing. + */ +#define BLE_GAP_UNAUTH_PAIRING (0x01) + +/** + * @def BLE_GAP_AUTH_PAIRING + * @brief Authenticated pairing. + */ +#define BLE_GAP_AUTH_PAIRING (0x02) + +/** + * @def BLE_GAP_LEGACY_PAIRING + * @brief Legacy pairing. + */ +#define BLE_GAP_LEGACY_PAIRING (0x01) + +/** + * @def BLE_GAP_LESC_PAIRING + * @brief Secure Connections. + */ +#define BLE_GAP_LESC_PAIRING (0x02) + +/** + * @def BLE_GAP_BONDING_NONE + * @brief The device doesn't support Bonding. + */ +#define BLE_GAP_BONDING_NONE (0x00) + +/** + * @def BLE_GAP_BONDING + * @brief The device supports Bonding. + */ +#define BLE_GAP_BONDING (0x01) + +/** + * @def BLE_GAP_IOCAP_DISPLAY_ONLY + * @brief Display Only iocapability. + * @details Output function : Local device has the ability to display a 6 digit decimal number.\n + * Input function : None + */ +#define BLE_GAP_IOCAP_DISPLAY_ONLY (0x00) + +/** + * @def BLE_GAP_IOCAP_DISPLAY_YESNO + * @brief Display Yes/No iocapability. + * @details Output function : Output function : Local device has the ability to display a 6 digit decimal number.\n + * Input function : Local device has the ability to indicate 'yes' or 'no' + */ +#define BLE_GAP_IOCAP_DISPLAY_YESNO (0x01) + +/** + * @def BLE_GAP_IOCAP_KEYBOARD_ONLY + * @brief Keyboard Only iocapability. + * @details Output function : None\n + * Input function : Local device has the ability to input the number '0' - '9'. + */ +#define BLE_GAP_IOCAP_KEYBOARD_ONLY (0x02) + +/** + * @def BLE_GAP_IOCAP_NOINPUT_NOOUTPUT + * @brief No Input No Output iocapability. + * @details Output function : None\n + * Input function : None + */ +#define BLE_GAP_IOCAP_NOINPUT_NOOUTPUT (0x03) + +/** + * @def BLE_GAP_IOCAP_KEYBOARD_DISPLAY + * @brief Keyboard Display iocapability. + * @details Output function : Output function : Local device has the ability to display a 6 digit decimal number.\n + * Input function : Local device has the ability to input the number '0' - '9'. + */ +#define BLE_GAP_IOCAP_KEYBOARD_DISPLAY (0x04) + +/** + * @def BLE_GAP_OOB_DATA_NOT_PRESENT + * @brief Reply that No OOB data has been received when pairing. + */ +#define BLE_GAP_OOB_DATA_NOT_PRESENT (0x00) + +/** + * @def BLE_GAP_OOB_DATA_PRESENT + * @brief Reply that the OOB data has been received when pairing. + */ +#define BLE_GAP_OOB_DATA_PRESENT (0x01) + +/** + * @def BLE_GAP_SC_BEST_EFFORT + * @brief Accept Legacy pairing and Secure Connections. + */ +#define BLE_GAP_SC_BEST_EFFORT (0x00) + +/** + * @def BLE_GAP_SC_STRICT + * @brief Accept only Secure Connections. + */ +#define BLE_GAP_SC_STRICT (0x01) + +/** + * @def BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT + * @brief Not support for Key Press Notification. + */ +#define BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT (0x00) + +/** + * @def BLE_GAP_SC_KEY_PRESS_NTF_SPRT + * @brief Support for Key Press Notification. + */ +#define BLE_GAP_SC_KEY_PRESS_NTF_SPRT (0x01) + +/** + * @def BLE_GAP_LEGACY_OOB_SIZE + * @brief The size of Temporary Key for OOB in legacy pairing. + */ +#define BLE_GAP_LEGACY_OOB_SIZE (0x10) + +/** + * @def BLE_GAP_OOB_CONFIRM_VAL_SIZE + * @brief The size of Confirmation Value for OOB in Secure Connections. + */ +#define BLE_GAP_OOB_CONFIRM_VAL_SIZE (0x10) + +/** + * @def BLE_GAP_OOB_RANDOM_VAL_SIZE + * @brief The size of Rand for OOB in Secure Connections. + */ +#define BLE_GAP_OOB_RANDOM_VAL_SIZE (0x10) + +/** + * @def BLE_GAP_SEC_DEL_LOC_NONE + * @brief Delete no local keys. + */ +#define BLE_GAP_SEC_DEL_LOC_NONE (0x00) + +/** + * @def BLE_GAP_SEC_DEL_LOC_IRK + * @brief Delete local IRK. + */ +#define BLE_GAP_SEC_DEL_LOC_IRK (0x01) + +/** + * @def BLE_GAP_SEC_DEL_LOC_CSRK + * @brief Delete local CSRK. + */ +#define BLE_GAP_SEC_DEL_LOC_CSRK (0x02) + +/** + * @def BLE_GAP_SEC_DEL_LOC_ALL + * @brief Delete all local keys. + */ +#define BLE_GAP_SEC_DEL_LOC_ALL (0x03) + +/** + * @def BLE_GAP_SEC_DEL_REM_NONE + * @brief Delete no remote device keys. + */ +#define BLE_GAP_SEC_DEL_REM_NONE (0x00) + +/** + * @def BLE_GAP_SEC_DEL_REM_SA + * @brief Delete a key specified by the p_addr parameter. + */ +#define BLE_GAP_SEC_DEL_REM_SA (0x01) + +/** + * @def BLE_GAP_SEC_DEL_REM_NOT_CONN + * @brief Delete keys of not connected remote devices. + */ +#define BLE_GAP_SEC_DEL_REM_NOT_CONN (0x02) + +/** + * @def BLE_GAP_SEC_DEL_REM_ALL + * @brief Delete all remote device keys. + */ +#define BLE_GAP_SEC_DEL_REM_ALL (0x03) + +/**@} (end addtogroup GAP_API)*/ + +/* =================================================== GATT Macro =================================================== */ + +/** @addtogroup GATT_SERVER_API + * @ingroup BLE + * @{ + */ + +/* GATT Common Macro */ + +/** + * @ingroup GATT_SERVER_API + * @def BLE_GATT_DEFAULT_MTU + * @brief GATT Default MTU. + */ +#define BLE_GATT_DEFAULT_MTU (23) + +/** + * @def BLE_GATT_16_BIT_UUID_FORMAT + * @brief GATT Identification for 16-bit UUID Format. + */ +#define BLE_GATT_16_BIT_UUID_FORMAT (0x01) + +/** + * @def BLE_GATT_128_BIT_UUID_FORMAT + * @brief GATT Identification for 128-bit UUID Format. + */ +#define BLE_GATT_128_BIT_UUID_FORMAT (0x02) + +/** + * @def BLE_GATT_16_BIT_UUID_SIZE + * @brief GATT 16-bit UUID Size. + */ +#define BLE_GATT_16_BIT_UUID_SIZE (2) + +/** + * @def BLE_GATT_128_BIT_UUID_SIZE + * @brief GATT 128-bit UUID Size. + */ +#define BLE_GATT_128_BIT_UUID_SIZE (16) + +/** + * @def BLE_GATT_INVALID_ATTR_HDL_VAL + * @brief GATT Invalid Attribute Handle Value. + */ +#define BLE_GATT_INVALID_ATTR_HDL_VAL (0x0000) + +/** + * @def BLE_GATT_ATTR_HDL_START_RANGE + * @brief GATT Attribute Handle Start Range. + */ +#define BLE_GATT_ATTR_HDL_START_RANGE (0x0001) + +/** + * @def BLE_GATT_ATTR_HDL_END_RANGE + * @brief GATT Attribute Handle End Range. + */ +#define BLE_GATT_ATTR_HDL_END_RANGE (0xFFFF) + +/* GATT Server Macro */ + +/** + * @def BLE_GATTS_CLI_CNFG_NOTIFICATION + * @brief GATT Client Configuration values. Enable Notification. + */ +#define BLE_GATTS_CLI_CNFG_NOTIFICATION (0x0001) + +/** + * @def BLE_GATTS_CLI_CNFG_INDICATION + * @brief GATT Client Configuration values. Enable Indication. + */ +#define BLE_GATTS_CLI_CNFG_INDICATION (0x0002) + +/** + * @def BLE_GATTS_CLI_CNFG_DEFAULT + * @brief GATT Client Configuration values. Default value or disable notification/indication. + */ +#define BLE_GATTS_CLI_CNFG_DEFAULT (0x0000) + +/** + * @def BLE_GATTS_SER_CNFG_BROADCAST + * @brief GATT Server Configuration values. Enable broadcast. + */ +#define BLE_GATTS_SER_CNFG_BROADCAST (0x0001) + +/** + * @def BLE_GATTS_SER_CNFG_DEFAULT + * @brief GATT Server Configuration values. Default value. + */ +#define BLE_GATTS_SER_CNFG_DEFAULT (0x0000) + +/** + * @def BLE_GATTS_MAX_CB + * @brief GATT Server Callback Number. + */ +#define BLE_GATTS_MAX_CB (15) + +/* GATT Server Operation */ + +/** + * @def BLE_GATTS_OP_CHAR_VALUE_READ_REQ + * @brief Characteristic Value Local Read Operation. + */ +#define BLE_GATTS_OP_CHAR_VALUE_READ_REQ (0x01) + +/** + * @def BLE_GATTS_OP_CHAR_VALUE_WRITE_REQ + * @brief Characteristic Value Local Write Operation. + */ +#define BLE_GATTS_OP_CHAR_VALUE_WRITE_REQ (0x02) + +/** + * @def BLE_GATTS_OP_CHAR_VALUE_WRITE_WITHOUT_REQ + * @brief Characteristic Value Local Write Without Response Operation. + */ +#define BLE_GATTS_OP_CHAR_VALUE_WRITE_WITHOUT_REQ (0x03) + +/** + * @def BLE_GATTS_OP_CHAR_CLI_CNFG_READ_REQ + * @brief Characteristic Client Configuration Local Read Operation. + */ +#define BLE_GATTS_OP_CHAR_CLI_CNFG_READ_REQ (0x11) + +/** + * @def BLE_GATTS_OP_CHAR_CLI_CNFG_WRITE_REQ + * @brief Characteristic Client Configuration Local Write Operation. + */ +#define BLE_GATTS_OP_CHAR_CLI_CNFG_WRITE_REQ (0x12) + +/** + * @def BLE_GATTS_OP_CHAR_SER_CNFG_READ_REQ + * @brief Characteristic Server Configuration Local Read Operation. + */ +#define BLE_GATTS_OP_CHAR_SER_CNFG_READ_REQ (0x21) + +/** + * @def BLE_GATTS_OP_CHAR_SER_CNFG_WRITE_REQ + * @brief Characteristic Server Configuration Local Write Operation. + */ +#define BLE_GATTS_OP_CHAR_SER_CNFG_WRITE_REQ (0x22) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_READ_REQ + * @brief Characteristic Value Peer Read Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_READ_REQ (0x81) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_WRITE_REQ + * @brief Characteristic Value Peer Write Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_WRITE_REQ (0x82) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_WRITE_CMD + * @brief Characteristic Value Peer Write Command. + */ +#define BLE_GATTS_OP_CHAR_PEER_WRITE_CMD (0x84) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ + * @brief Characteristic Client Configuration Peer Read Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ (0x91) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ + * @brief Characteristic Client Configuration Peer Write Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ (0x92) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ + * @brief Characteristic Server Configuration Peer Read Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ (0xA1) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ + * @brief Characteristic Server Configuration Peer Write Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ (0xA2) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ + * @brief Characteristic User Description Peer Read Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ (0xB1) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ + * @brief Characteristic User Description Peer Write Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ (0xB2) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ + * @brief Characteristic Higher Layer Defined Descriptor Peer Read Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ (0xF1) + +/** + * @def BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ + * @brief Characteristic Higher Layer Defined Descriptor Peer Write Operation. + */ +#define BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ (0xF2) + +/** + * @def BLE_GATTS_OP_CHAR_REQ_AUTHOR + * @brief Operation Required Authorization. + */ +#define BLE_GATTS_OP_CHAR_REQ_AUTHOR (0x08) + +/* GATT Database */ + +/** + * @def BLE_GATT_DB_READ + * @brief Allow clients to read. + */ +#define BLE_GATT_DB_READ (0x01) + +/** + * @def BLE_GATT_DB_WRITE + * @brief Allow clients to write. + */ +#define BLE_GATT_DB_WRITE (0x02) + +/** + * @def BLE_GATT_DB_WRITE_WITHOUT_RSP + * @brief Allow clients to write without response. + */ +#define BLE_GATT_DB_WRITE_WITHOUT_RSP (0x04) + +/** + * @def BLE_GATT_DB_READ_WRITE + * @brief Allow clients to access of all. + */ +#define BLE_GATT_DB_READ_WRITE \ + (BLE_GATT_DB_READ | BLE_GATT_DB_WRITE | BLE_GATT_DB_WRITE_WITHOUT_RSP) + +/** + * @def BLE_GATT_DB_NO_AUXILIARY_PROPERTY + * @brief No auxiliary properties. + */ +#define BLE_GATT_DB_NO_AUXILIARY_PROPERTY (0x00) + +/** + * @def BLE_GATT_DB_FIXED_LENGTH_PROPERTY + * @brief Fixed length attribute value. + */ +#define BLE_GATT_DB_FIXED_LENGTH_PROPERTY (0x01) + +/** + * @def BLE_GATT_DB_AUTHORIZATION_PROPERTY + * @brief Attributes requiring authorization. + */ +#define BLE_GATT_DB_AUTHORIZATION_PROPERTY (0x02) + +/** + * @def BLE_GATT_DB_ATTR_DISABLED + * @brief The attribute is disabled. + * If this value is set, the attribute cannot be found and accessed by a GATT Client. + */ +#define BLE_GATT_DB_ATTR_DISABLED (0x10) + +/** + * @def BLE_GATT_DB_128_BIT_UUID_FORMAT + * @brief Attribute with 128 bit UUID. + */ +#define BLE_GATT_DB_128_BIT_UUID_FORMAT (0x20) + +/** + * @def BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY + * @brief Attribute managed by each GATT Client. + */ +#define BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY (0x40) + +/** + * @def BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY + * @brief Fixed attribute value. + */ +#define BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY (0x80) + +/** + * @def BLE_GATT_DB_SER_SECURITY_UNAUTH + * @brief Unauthenticated pairing(Security Mode1 Security Level 2, Security Mode 2 Security Level 1). + * Unauthenticated pairing is required to access the service. + */ +#define BLE_GATT_DB_SER_SECURITY_UNAUTH (0x00000001) + +/** + * @def BLE_GATT_DB_SER_SECURITY_AUTH + * @brief Authenticated pairing(Security Mode1 Security Level 3, Security Mode 2 Security Level 2). + * Authenticated pairing is required to access the service. + */ +#define BLE_GATT_DB_SER_SECURITY_AUTH (0x00000002) + +/** + * @def BLE_GATT_DB_SER_SECURITY_SECONN + * @brief Authenticated LE secure connections that generates 16bytes LTK(Security Mode1 Security Level 4). + * Authenticated LE secure connections pairing that generates 16bytes LTK is required to access the service. + * If this bit is set, bit24-27 are ignored. + */ +#define BLE_GATT_DB_SER_SECURITY_SECONN (0x00000004) + +/** + * @def BLE_GATT_DB_SER_SECURITY_ENC + * @brief Encryption. + * Encryption by the LTK exchanged in pairing is required to access. + */ +#define BLE_GATT_DB_SER_SECURITY_ENC (0x00000010) + +/** + * @def BLE_GATT_DB_SER_NO_SECURITY_PROPERTY + * @brief No Security(Security Mode1 Security Level 1). + */ +#define BLE_GATT_DB_SER_NO_SECURITY_PROPERTY (0x00000000) + +/** + * @def BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE + * @brief 7-byte or larger encryption key. + */ +#define BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE (0x00000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7 + * @brief 7-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7 (0x01000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8 + * @brief 8-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8 (0x02000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9 + * @brief 9-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9 (0x03000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10 + * @brief 10-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10 (0x04000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11 + * @brief 11-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11 (0x05000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12 + * @brief 12-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12 (0x06000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13 + * @brief 13-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13 (0x07000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14 + * @brief 14-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14 (0x08000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15 + * @brief 15-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15 (0x09000000) + +/** + * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16 + * @brief 16-byte encryption key. + */ +#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16 (0x0A000000) + +/******************************************************************************************************************//** + * @enum e_r_ble_gatts_evt_t + * @brief GATT Server Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief MTU Exchange Request has been received. + * @details + * This event notifies the application layer that a MTU Exchange Request PDU has been received from a GATT Client. + * Need to reply to the request by R_BLE_GATTS_RspExMtu(). + * + * ## Event Code: 0x3002 + * + * ## Event Data: + * st_ble_gatts_ex_mtu_req_evt_t + */ + BLE_GATTS_EVENT_EX_MTU_REQ = 0x3002, //!< BLE_GATTS_EVENT_EX_MTU_REQ + + /** + * @brief Read By Type Response has been sent. + * @details + * This event notifies the application layer that a Read By Type Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x3009 + * + * ## Event Data: + * st_ble_gatts_read_by_type_rsp_evt_t + */ + BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP = 0x3009, //!< BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP + + /** + * @brief Read Response has been sent. + * @details + * This event notifies the application layer that a Read Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x300B + * + * ## Event Data: + * st_ble_gatts_read_rsp_evt_t + */ + BLE_GATTS_EVENT_READ_RSP_COMP = 0x300B, //!< BLE_GATTS_EVENT_READ_RSP_COMP + + /** + * @brief Read Blob Response has been sent. + * @details + * This event notifies the application layer that a Read Blob Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x300D + * + * ## Event Data: + * st_ble_gatts_read_blob_rsp_evt_t + */ + BLE_GATTS_EVENT_READ_BLOB_RSP_COMP = 0x300D, //!< BLE_GATTS_EVENT_READ_BLOB_RSP_COMP + + /** + * @brief Read Multiple Response has been sent. + * @details + * This event notifies the application layer that a Read Multiple Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x300F + * + * ## Event Data: + * st_ble_gatts_read_multi_rsp_evt_t + */ + BLE_GATTS_EVENT_READ_MULTI_RSP_COMP = 0x300F, //!< BLE_GATTS_EVENT_READ_MULTI_RSP_COMP + + /** + * @brief Write Response has been sent. + * @details + * This event notifies the application layer that a Write Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x3013 + * + * ## Event Data: + * st_ble_gatts_write_rsp_evt_t + */ + BLE_GATTS_EVENT_WRITE_RSP_COMP = 0x3013, //!< BLE_GATTS_EVENT_WRITE_RSP_COMP + + /** + * @brief Prepare Write Response has been sent. + * @details + * This event notifies the application layer that a Prepare Write Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x3017 + * + * ## Event Data: + * st_ble_gatts_prepare_write_rsp_evt_t + */ + BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP = 0x3017, //!< BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP + + /** + * @brief Execute Write Response has been sent. + * @details + * This event notifies the application layer that a Execute Write Response PDU has been sent + * from GATT Server to the GATT Client. + * + * ## Event Code: 0x3019 + * + * ## Event Data: + * st_ble_gatts_exe_write_rsp_evt_t + */ + BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP = 0x3019, //!< BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP + + /** + * @brief Confirmation has been received. + * @details + * This event notifies the application layer that a Confirmation PDU has been received from a GATT Client. + * + * ## Event Code: 0x301E + * + * ## Event Data: + * st_ble_gatts_cfm_evt_t + */ + BLE_GATTS_EVENT_HDL_VAL_CNF = 0x301E, //!< BLE_GATTS_EVENT_HDL_VAL_CNF + + /** + * @brief The GATT Database has been accessed from a GATT Client. + * @details + * This event notifies the application layer that the GATT Database has been accessed from a GATT Client. + * + * ## Event Code: 0x3040 + * + * ## Event Data: + * st_ble_gatts_db_access_evt_t + */ + BLE_GATTS_EVENT_DB_ACCESS_IND = 0x3040, //!< BLE_GATTS_EVENT_DB_ACCESS_IND + + /** + * @brief A connection has been established. + * @details + * This event notifies the application layer that the link with the GATT Client has been established. + * + * ## Event Code: 0x3081 + * + * ## Event Data: + * st_ble_gatts_conn_evt_t + */ + BLE_GATTS_EVENT_CONN_IND = 0x3081, //!< BLE_GATTS_EVENT_CONN_IND + + /** + * @brief A connection has been disconnected. + * @details + * This event notifies the application layer that the link with the GATT Client has been disconnected. + * + * ## Event Code: 0x3082 + * + * ## Event Data: + * st_ble_gatts_disconn_evt_t + */ + BLE_GATTS_EVENT_DISCONN_IND = 0x3082, //!< BLE_GATTS_EVENT_DISCONN_IND + + /** + * @brief Invalid GATT Server Event. + * + * ## Event Code: 0x30FF + * + * ## Event Data: + * none + */ + BLE_GATTS_EVENT_INVALID = 0x30FF //!< BLE_GATTS_EVENT_INVALID +} e_r_ble_gatts_evt_t; + +/*@}*/ + +/** @addtogroup GATT_CLIENT_API + * @ingroup BLE + * @{ + */ + +/** + * @ingroup GATT_CLIENT_API + * @def BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG + * GATT Execute Write Cancel Flag. + */ +#define BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG (0x00) + +/** + * @def BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG + * GATT Execute Write Execute Flag. + */ +#define BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG (0x01) + +/** + * @def BLE_GATTC_MAX_CB + * @brief GATT Client Callback Number. + */ +#define BLE_GATTC_MAX_CB (15) + +/** + * @def BLE_GATTC_EXEC_AUTO + * @brief Auto execution. + */ +#define BLE_GATTC_EXEC_AUTO (0x01) + +/** + * @def BLE_GATTC_EXEC_NOT_AUTO + * @brief Not auto execution. + */ +#define BLE_GATTC_EXEC_NOT_AUTO (0x02) + +/* To be moved to parameter files */ + +/** + * @def BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR + * @brief Length of the Queue used with Prepare Write procedure to write a characteristic + * whose size is larger than MTU. + */ +#define BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR (10) + +/******************************************************************************************************************//** + * @enum e_r_ble_gattc_evt_t + * @brief GATT Client Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief This event notifies the application layer that a problem has occurred in the GATT Server while + * processing a request from GATT Client. + * @details When GATT Client has received a Error Response PDU from a GATT Server, BLE_GATTC_EVENT_ERROR_RSP + * event is notified the application layer. + * + * ## Event Code: 0x4001 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_err_rsp_evt_t + */ + BLE_GATTC_EVENT_ERROR_RSP = 0x4001, //!< BLE_GATTC_EVENT_ERROR_RSP + + /** + * @brief This event notifies the application layer that a MTU Exchange Response PDU has been received + * from a GATT Server. + * + * ## Event Code: 0x4003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response + * since GATT Client sent a Exchange MTU Request PDU to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_ex_mtu_rsp_evt_t + */ + BLE_GATTC_EVENT_EX_MTU_RSP = 0x4003, //!< BLE_GATTC_EVENT_EX_MTU_RSP + + /** + * @brief When the read of Characteristic specified by UUID has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x4009 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response + * since GATT Client sent a Exchange MTU Request PDU to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP = 0x4009, //!< BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP + + /** + * @brief When the read of Characteristic/Characteristic Descriptor has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x400B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadCharUsingUuid() + * to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_READ_RSP = 0x400B, //!< BLE_GATTC_EVENT_CHAR_READ_RSP + + /** + * @brief After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer + * that the partial contents of Long Characteristic/Long Characteristic Descriptor + * has been received from the GATT Server. + * + * ## Event Code: 0x400D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadLongChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_PART_READ_RSP = 0x400D, //!< BLE_GATTC_EVENT_CHAR_PART_READ_RSP + + /** + * @brief This event notifies the application layer that + * the read of multiple Characteristics has been completed. + * + * ## Event Code: 0x400F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadMultiChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_multi_char_evt_t + */ + BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP = 0x400F, //!< BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP + + /** + * @brief This event notifies the application layer that the write of + * Characteristic/Characteristic Descriptor has been completed. + * + * ## Event Code: 0x4013 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a write response + * since GATT Client sent a request for write by R_BLE_GATTC_WriteChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_wr_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_WRITE_RSP = 0x4013, //!< BLE_GATTC_EVENT_CHAR_WRITE_RSP + + /** + * @brief This event notifies the application layer of the one of the following. + * - A segmentation to be written to Long Characteristic/Long Characteristic Descriptor + * has been sent to the GATT Server. + * - The data written to one Characteristic by Reliable Writes has been sent to the GATT Server. + * + * ## Event Code: 0x4017 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a + * request for segmentation write by R_BLE_GATTC_WriteLongChar(), + * or 1 Characteristic write by R_BLE_GATTC_ReliableWrites() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_part_wr_evt_t + */ + BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP = 0x4017, //!< BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP + + /** + * @brief This event notifies the application layer that a Notification has been received from a GATT Server. + * + * ## Event Code: 0x401B + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_ntf_evt_t + */ + BLE_GATTC_EVENT_HDL_VAL_NTF = 0x401B, //!< BLE_GATTC_EVENT_HDL_VAL_NTF + + /** + * @brief This event notifies the application layer that a Indication has been received from a GATT Server. + * @details When the GATT Client has received a Indication, host stack automatically sends a Confirmation + * to the GATT Server. + * + * ## Event Code: 0x401D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_MEM_ALLOC_FAILED(0x000C)Insufficient resource is needed to generate the confirmation packet.
+ *
+ * + * ## Event Data: + * st_ble_gattc_ind_evt_t + */ + BLE_GATTC_EVENT_HDL_VAL_IND = 0x401D, //!< BLE_GATTC_EVENT_HDL_VAL_IND + + /** + * @brief This event notifies the application layer that the link with the GATT Server has been established. + * + * ## Event Code: 0x4081 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_conn_evt_t + */ + BLE_GATTC_EVENT_CONN_IND = 0x4081, //!< BLE_GATTC_EVENT_CONN_IND + + /** + * @brief This event notifies the application layer that the link with the GATT Server has been disconnected. + * + * ## Event Code: 0x4082 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_disconn_evt_t + */ + BLE_GATTC_EVENT_DISCONN_IND = 0x4082, //!< BLE_GATTC_EVENT_DISCONN_IND + + /** + * @brief This event notifies the application layer that 16-bit UUID Primary Service has been discovered. + * + * ## Event Code: 0x40E0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_16_evt_t + */ + BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND = 0x40E0, //!< BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Primary Service has been discovered. + * + * ## Event Code: 0x40E1 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_128_evt_t + */ + BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND = 0x40E1, //!< BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscAllPrimServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E2 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP = 0x40E2, //!< BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscPrimServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E3 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP = 0x40E3, //!< BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Secondary Service has been discovered. + * + * ## Event Code: 0x40E4 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_16_evt_t + */ + BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND = 0x40E4, //!< BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Secondary Service has been discovered. + * + * ## Event Code: 0x40E5 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_128_evt_t + */ + BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND = 0x40E5, //!< BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscAllSecondServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E6 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP = 0x40E6, //!< BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that Included Service that + * includes 16-bit UUID Service has been discovered. + * + * ## Event Code: 0x40E7 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_inc_serv_16_evt_t + */ + BLE_GATTC_EVENT_INC_SERV_16_DISC_IND = 0x40E7, //!< BLE_GATTC_EVENT_INC_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that Included Service that + * includes 128-bit UUID Service has been discovered. + * + * ## Event Code: 0x40E8 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_inc_serv_128_evt_t + */ + BLE_GATTC_EVENT_INC_SERV_128_DISC_IND = 0x40E8, //!< BLE_GATTC_EVENT_INC_SERV_128_DISC_IND + + /** + * @brief When the Included Service discovery by R_BLE_GATTC_DiscIncServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E9 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_INC_SERV_DISC_COMP = 0x40E9, //!< BLE_GATTC_EVENT_INC_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Characteristic has been discovered. + * + * ## Event Code: 0x40EA + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_16_evt_t + */ + BLE_GATTC_EVENT_CHAR_16_DISC_IND = 0x40EA, //!< BLE_GATTC_EVENT_CHAR_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Characteristic has been discovered. + * + * ## Event Code: 0x40EB + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_128_evt_t + */ + BLE_GATTC_EVENT_CHAR_128_DISC_IND = 0x40EB, //!< BLE_GATTC_EVENT_CHAR_128_DISC_IND + + /** + * @brief When the Characteristic discovery by R_BLE_GATTC_DiscAllChar() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40EC + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP = 0x40EC, //!< BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP + + /** + * @brief When the Characteristic discovery by R_BLE_GATTC_DiscCharByUuid() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40ED + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_CHAR_DISC_COMP = 0x40ED, //!< BLE_GATTC_EVENT_CHAR_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Characteristic Descriptor + * has been discovered. + * + * ## Event Code: 0x40EE + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_desc_16_evt_t + */ + BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND = 0x40EE, //!< BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Characteristic Descriptor + * has been discovered. + * + * ## Event Code: 0x40EF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_desc_128_evt_t + */ + BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND = 0x40EF, //!< BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND + + /** + * @brief When the Characteristic Descriptor discovery by R_BLE_GATTC_DiscAllCharDesc() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40F0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP = 0x40F0, //!< BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP + + /** + * @brief After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer that all of + * the contents of the Characteristic/Long Characteristic Descriptor has been received + * from the GATT Server. + * + * ## Event Code: 0x40F1 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_LONG_CHAR_READ_COMP = 0x40F1, //!< BLE_GATTC_EVENT_LONG_CHAR_READ_COMP + + /** + * @brief This event notifies that the application layer that the write of + * Long Characteristic/Long Characteristic Descriptor has been completed. + * + * ## Event Code: 0x40F2 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent + * a request for write by R_BLE_GATTC_WriteLongChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP = 0x40F2, //!< BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP + + /** + * @brief This event notifies that the application layer that + * the GATT Server has received the data to be written to the Characteristics. + * + * ## Event Code: 0x40F3 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP = 0x40F3, //!< BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP + + /** + * @brief This event notifies the application layer that the Reliable Writes has been completed. + * + * ## Event Code: 0x40F4 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a + * request for execute write by R_BLE_GATTC_ReliableWrites() or + * R_BLE_GATTC_ExecWrite() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_reliable_writes_comp_evt_t + */ + BLE_GATTC_EVENT_RELIABLE_WRITES_COMP = 0x40F4, //!< BLE_GATTC_EVENT_RELIABLE_WRITES_COMP + + /** + * @brief Invalid GATT Client Event. + * + * ## Event Code: 0x40FF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_INVALID = 0x40FF //!< BLE_GATTC_EVENT_INVALID +} e_r_ble_gattc_evt_t; + +/*@}*/ + +/* ================================================== L2CAP Macro =================================================== */ + +/** @addtogroup L2CAP_API + * @ingroup BLE + * @{ + */ + +/** + * @ingroup l2cap_api + * @def BLE_L2CAP_MAX_CBFC_PSM + * @brief The maximum number of callbacks that host stack can register. + */ +#define BLE_L2CAP_MAX_CBFC_PSM (2) + +/** + * @def BLE_L2CAP_CF_RSP_SUCCESS + * @brief Notify the remote device that the connection can be established. + */ +#define BLE_L2CAP_CF_RSP_SUCCESS (0x0000) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH + * @brief Notify the remote device that the connection can not be established because of insufficient authentication. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH (0x0005) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ + * @brief Notify the remote device that the connection can not be established because of insufficient Authorization. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ (0x0006) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY + * @brief Notify the remote device that the connection can not be established because of Encryption Key Size. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY (0x0007) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC + * @brief Notify the remote device that the connection can not be established because of Encryption. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC (0x0008) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM + * @brief Notify the remote device that the connection can not be established + * because the parameters is unacceptable to local device. + */ +#define BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM (0x000B) + +/*@}*/ + +/* ============================================= Vendor Specific Macro ============================================== */ + +/** @addtogroup VS_API + * @ingroup BLE + * @{ + */ + +/** + * @ingroup vs_api + * @def BLE_VS_TX_POWER_HIGH + * @brief High power level. + */ +#define BLE_VS_TX_POWER_HIGH (0x00) + +/** + * @def BLE_VS_TX_POWER_MID + * @brief Middle power level. + */ +#define BLE_VS_TX_POWER_MID (0x01) + +/** + * @def BLE_VS_TX_POWER_LOW + * @brief Low power level. + */ +#define BLE_VS_TX_POWER_LOW (0x02) + +/** + * @def BLE_VS_ADDR_AREA_REG + * @brief Address in register is written or read. + */ +#define BLE_VS_ADDR_AREA_REG (0x00) + +/** + * @def BLE_VS_ADDR_AREA_DATA_FLASH + * @brief Address in DataFlash is written or read. + */ +#define BLE_VS_ADDR_AREA_DATA_FLASH (0x01) + +/** + * @def BLE_VS_EH_TX_PL_PRBS9 + * @brief PRBS9 sequence '11111111100000111101..'. + */ +#define BLE_VS_EH_TX_PL_PRBS9 (0x00) + +/** + * @def BLE_VS_EH_TX_PL_11110000 + * @brief Repeated '11110000' + */ +#define BLE_VS_EH_TX_PL_11110000 (0x01) + +/** + * @def BLE_VS_EH_TX_PL_10101010 + * @brief Repeated '10101010' + */ +#define BLE_VS_EH_TX_PL_10101010 (0x02) + +/** + * @def BLE_VS_EH_TX_PL_PRBS15 + * @brief PRBS15 sequence + */ +#define BLE_VS_EH_TX_PL_PRBS15 (0x03) + +/** + * @def BLE_VS_EH_TX_PL_11111111 + * @brief Repeated '11111111' + */ +#define BLE_VS_EH_TX_PL_11111111 (0x04) + +/** + * @def BLE_VS_EH_TX_PL_00000000 + * @brief Repeated '00000000' + */ +#define BLE_VS_EH_TX_PL_00000000 (0x05) + +/** + * @def BLE_VS_EH_TX_PL_00001111 + * @brief Repeated '00001111' + */ +#define BLE_VS_EH_TX_PL_00001111 (0x06) + +/** + * @def BLE_VS_EH_TX_PL_01010101 + * @brief Repeated '01010101' + */ +#define BLE_VS_EH_TX_PL_01010101 (0x07) + +/** + * @def BLE_VS_EH_TEST_PHY_1M + * @brief 1M PHY used in Transmitter/Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_1M (0x01) + +/** + * @def BLE_VS_EH_TEST_PHY_2M + * @brief 2M PHY used in Transmitter/Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_2M (0x02) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED + * @brief Coded PHY used in Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_CODED (0x03) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED_S_8 + * @brief Coded PHY(S=8) used in Transmitter test. + */ +#define BLE_VS_EH_TEST_PHY_CODED_S_8 (0x03) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED_S_2 + * @brief Coded PHY(S=2) used in Transmitter test. + */ +#define BLE_VS_EH_TEST_PHY_CODED_S_2 (0x04) + +/** + * @def BLE_VS_RF_OFF + * @brief RF power off. + */ +#define BLE_VS_RF_OFF (0x00) + +/** + * @def BLE_VS_RF_ON + * @brief RF power on. + */ +#define BLE_VS_RF_ON (0x01) + +/** + * @def BLE_VS_RF_INIT_PARAM_NOT_CHG + * @brief The parameters are not changed in RF power on. + */ +#define BLE_VS_RF_INIT_PARAM_NOT_CHG (0x00) + +/** + * @def BLE_VS_RF_INIT_PARAM_CHG + * @brief The parameters are changed in RF power on. + */ +#define BLE_VS_RF_INIT_PARAM_CHG (0x01) + +/** + * @def BLE_VS_CS_PRIM_ADV_S_8 + * @brief Coding scheme for Primary Advertising PHY(S=8). + */ +#define BLE_VS_CS_PRIM_ADV_S_8 (0x00) + +/** + * @def BLE_VS_CS_PRIM_ADV_S_2 + * @brief Coding scheme for Primary Advertising PHY(S=2). + */ +#define BLE_VS_CS_PRIM_ADV_S_2 (0x01) + +/** + * @def BLE_VS_CS_SECOND_ADV_S_8 + * @brief Coding scheme for Secondary Advertising PHY(S=8). + */ +#define BLE_VS_CS_SECOND_ADV_S_8 (0x00) + +/** + * @def BLE_VS_CS_SECOND_ADV_S_2 + * @brief Coding scheme for Secondary Advertising PHY(S=2). + */ +#define BLE_VS_CS_SECOND_ADV_S_2 (0x02) + +/** + * @def BLE_VS_CS_CONN_S_8 + * @brief Coding scheme for request for link establishment(S=8). + */ +#define BLE_VS_CS_CONN_S_8 (0x00) + +/** + * @def BLE_VS_CS_CONN_S_2 + * @brief Coding scheme for request for link establishment(S=2). + */ +#define BLE_VS_CS_CONN_S_2 (0x04) + +/** + * @def BLE_VS_TX_FLOW_CTL_ON + * @brief It means that the number of buffer has reached the High Water Mark from flow off state. + */ +#define BLE_VS_TX_FLOW_CTL_ON (0x00) + +/** + * @def BLE_VS_TX_FLOW_CTL_OFF + * @brief It means that the number of buffer has reached the Low Water Mark from flow on state. + */ +#define BLE_VS_TX_FLOW_CTL_OFF (0x01) + +/*@}*/ + +/* ============================================== GAP Type Definitions ============================================== */ + +/** @addtogroup GAP_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @struct st_ble_evt_data_t + * @brief st_ble_evt_data_t is the type of the data notified in a GAP Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The size of GAP Event parameters. + */ + uint16_t param_len; + + /** + * @brief GAP Event parameters. This parameter differs in each GAP Event. + */ + void * p_param; +} st_ble_evt_data_t; + +/******************************************************************************************************************//** + * @struct st_ble_dev_addr_t + * @brief st_ble_dev_addr_t is the type of bluetooth device address(BD_ADDR). + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief BD_ADDR. + */ + uint8_t addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Bluetooth address type. + * @details + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address. | + * | BLE_GAP_ADDR_RAND(0x01) | Random Address. | + */ + uint8_t type; +} st_ble_dev_addr_t; + +/******************************************************************************************************************//** + * @typedef ble_gap_app_cb_t + * @brief ble_gap_app_cb_t is the GAP Event callback function type. + * @param[in] event_type The type of GAP Event. + * @param[in] event_result The result of API call which generates the GAP Event. + * @param[in] p_event_data Data notified in the GAP Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gap_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data); + +/******************************************************************************************************************//** + * @typedef ble_gap_del_bond_cb_t + * @brief ble_gap_del_bond_cb_t is the type of the callback function for delete bonding information + * stored in non-volatile area. \n This type is used in R_BLE_GAP_DeleteBondInfo(). + * @param[in] p_addr The parameter returns the address of the remote device whose keys are deleted + * by R_BLE_GAP_DeleteBondInfo(). \n + * If R_BLE_GAP_DeleteBondInfo() deletes the keys of all remote devices, the parameter returns NULL. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gap_del_bond_cb_t)(st_ble_dev_addr_t * p_addr); + +/* =========================================== GAP API Params Definitions =========================================== */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_adv_param_t + * @brief Advertising parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be set the advertising parameters. + * @details + * Valid range is 0x00 - 0x03.\n + * In the first advertising parameters setting, the advertising set specified by adv_hdl is generated.\n + * The Advertising Set ID(Advertising SID) of the advertising set is same as adv_hdl. + */ + uint8_t adv_hdl; + + /** + * @brief Advertising packet type. + * @details + * Legacy advertising PDU type, or bitwise or of Extended advertising PDU type and Extended advertising option. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
categorymacrodescription
Legacy Advertising PDU typeBLE_GAP_LEGACY_PROP_ADV_IND(0x0013)Connectable and scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND(0x0015)Connectable directed (low duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND(0x001D)Connectable directed (high duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_SCAN_IND(0x0012)Scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND(0x0010)Non-connectable and non-scannable undirected Legacy Advertising Packet
Extended Advertising PDU typeBLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT(0x0001)Connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT(0x0005)Connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT(0x000D)Connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT(0x0002)Non-connectable and scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT(0x0006)Non-connectable and scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT(0x000E)Non-connectable and scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT(0x0000)Non-connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT(0x0004)Non-connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT(0x000C)Non-connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
Extended Advertising OptionBLE_GAP_EXT_PROP_ADV_ANONYMOUS(0x0020)Omit the advertiser address from Extended Advertising Packet.
BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER(0x0040)Indicate that the advertising data includes TX Power.
+ */ + uint16_t adv_prop_type; + + /** + * @brief Minimum advertising interval. + * @details + * Time(ms) = adv_intv_min * 0.625.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t adv_intv_min; + + /** + * @brief Maximum Advertising interval. + * @details + * Time(ms) = adv_intv_max * 0.625.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t adv_intv_max; + + /** + * @brief The adv_ch_map is channels used in advertising with primary advertising channels. + * @details + * It is a bitwise OR of the following values. + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADV_CH_37(0x01) | Use 37 CH. | + * | BLE_GAP_ADV_CH_38(0x02) | Use 38 CH. | + * | BLE_GAP_ADV_CH_39(0x04) | Use 39 CH. | + * | BLE_GAP_ADV_CH_ALL(0x07) | Use 37 - 39 CH. | + */ + uint8_t adv_ch_map; + + /** + * @brief Own BD Address Type. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * the random address specified by the o_addr field is used. + *
+ */ + uint8_t o_addr_type; + + /** + * @brief Random address set to the advertising set, when the o_addr_type field is BLE_GAP_ADDR_RAND. + * @details When the o_addr_type field is other than BLE_GAP_ADDR_RAND, this field is ignored. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t o_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Peer address type. + * @details + * When the Advertising PDU type is other than directed or the o_addr_type is BLE_GAP_ADDR_PUBLIC or + * BLE_GAP_ADDR_RAND,this field is ignored. + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address | + * | BLE_GAP_ADDR_RAND(0x01) | Random Address | + */ + uint8_t p_addr_type; + + /** + * @brief Peer address. + * @details When the Advertising PDU type is other than directed or + * the o_addr_type is BLE_GAP_ADDR_PUBLIC or BLE_GAP_ADDR_RAND,this field is ignored. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t p_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Advertising Filter Policy. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY(0x00)Process scan and connection requests from all devices.
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY(0x01) + * Process connection requests from all devices and scan requests + * from only devices that are in the White List. + *
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST(0x02) + * Process scan requests from all devices and connection requests from + * only devices that are in the White List. + *
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST(0x03)Process scan and connection requests from only devices in the White List.
+ */ + uint8_t filter_policy; + + /** + * @brief Primary ADV PHY. + * @details + * In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADV_PHY_1M(0x01) + * Use 1M PHY as Primary Advertising PHY.
+ * When the adv_prop_type field is Legacy Advertising PDU type,
+ * this field shall be set to BLE_GAP_ADV_PHY_1M. + *
BLE_GAP_ADV_PHY_CD(0x03)Use Coded PHY(S=8) as Primary Advertising PHY. + * Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().
+ */ + uint8_t adv_phy; + + /** + * @brief Secondary ADV Max Skip. + * @details + * Valid range is 0x00 - 0xFF.\n + * When this field is 0x00, AUX_ADV_IND is sent before the next advertising event.\n + * When the adv_prop_type field is Legacy Advertising PDU, this field is ignored. + */ + uint8_t sec_adv_max_skip; + + /** + * @brief Secondary ADV Phy. + * @details + * When the adv_prop_type is Legacy Advertising PDU, this field is ignored. + * | macro | description | + * |:------------------------- |:------------------------------------------------ | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_2M(0x02) | Use 2M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY(S=8) as Secondary Advertising PHY. | + * + * Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). + */ + uint8_t sec_adv_phy; + + /** + * @brief Scan Request Notifications Flag. + * @details + * When the adv_prop_type field is non-scannable Advertising PDU, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_REQ_NTF_DISABLE(0x00)Disable Scan Request Notification.
BLE_GAP_SCAN_REQ_NTF_ENABLE(0x01) + * Enable Scan Request Notification.
+ * When a Scan Request Packet from Scanner has been received, + * the BLE_GAP_EVENT_SCAN_REQ_RECV event is notified. + *
+ */ + uint8_t scan_req_ntf_flag; +} st_ble_gap_ext_adv_param_t; + +/******************************************************************************************************************//** + * @brief Advertising parameters. + * @sa st_ble_gap_ext_adv_param_t + **********************************************************************************************************************/ +typedef st_ble_gap_ext_adv_param_t st_ble_gap_adv_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_data_t + * @brief Advertising data/scan response data/periodic advertising data. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be + * set advertising data/scan response/periodic advertising data. + * @details + * Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief Data type. + * @details + * | macro | description | + * |:---------------------------------- |:-------------------------- | + * | BLE_GAP_ADV_DATA_MODE (0x00) | Advertising data. | + * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data. | + * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data. | + */ + uint8_t data_type; + + /** + * @brief The length of advertising data/scan response data/periodic advertising data (in bytes). + * @details + * In case of Legacy Advertising PDU, the length is 0 - 31 bytes.\n + * In case of Extended Advertising PDU, the length is 0 - 1650 bytes.\n + * Note that the length of the advertising data/scan response data in + * the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of the advertising sets may not exceed + * the buffer size(4250 bytes) in Controller. \n + * \n + * In case of periodic advertising data, the length is 0 - 1650 bytes.\n + * Note that the length of the periodic advertising data in the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of + * the advertising sets may not exceed the buffer size(4306 bytes) in Controller.\n + * \n + * When this field is 0, the operations specified by the zero_length_flag is executed. + */ + uint16_t data_length; + + /** + * @brief Advertising data/scan response data/periodic advertising data. + * @details + * When the data_length field is 0, this field is ignored. + */ + uint8_t * p_data; + + /** + * @brief Operation when the data_length field is 0. + * @details + * If the data_length is other than 0, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_DATA_0_CLEAR(0x01) + * Clear the advertising data/scan response data/periodic advertising data + * in the advertising set. + *
BLE_GAP_DATA_0_DID_UPD(0x02)Update Advertising DID without changing advertising data. + * If the data_type field is BLE_GAP_ADV_DATA_MODE, this value is allowed. + *
+ */ + uint8_t zero_length_flag; +} st_ble_gap_adv_data_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_adv_param_t + * @brief Periodic advertising parameter. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be set periodic advertising parameter. + * @details + * Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief Periodic ADV Properties. + * @details + * The prop_type field is set to the following values.\n + * If the type of the periodic advertising data cannot be applied from the following, set 0x0000. + * | macro | description | + * |:---------------------------------- |:------------------------------------------------------------ | + * | BLE_GAP_PERD_PROP_TX_POWER(0x0040) | Indicate that periodic advertising data includes Tx Power. | + */ + uint16_t prop_type; + + /** + * @brief Minimum Periodic Advertising Interval. + * @details + * Time(ms) = perd_intv_min * 1.25.\n + * Valid range is 0x0006 - 0xFFFF. + */ + uint16_t perd_intv_min; + + /** + * @brief Maximum Periodic Advertising Interval. + * @details + * Time(ms) = perd_intv_max * 1.25.\n + * Valid range is 0x0006 - 0xFFFF. + */ + uint16_t perd_intv_max; +} st_ble_gap_perd_adv_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_phy_param_t + * @brief Scan parameters per scan PHY. + * @details In case of start scanning with both 1M PHY and Coded PHY, + * adjust scan windows and scan intervals according to the following.\n + * ``` p_phy_param_1M->scan_window / p_phy_param_1M->scan_intv + + * p_phy_param_coded->scan_window / p_phy_param_coded->scan_intv <= 1 ``` + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Scan type. + * @details + * | macro | description | + * |:-------------------------------|:--------------------------- | + * | BLE_GAP_SCAN_PASSIVE(0x00) | Passive Scan. | + * | BLE_GAP_SCAN_ACTIVE(0x01) | Active Scan. | + */ + uint8_t scan_type; + + /** + * @brief Scan interval. + * @details + * interval(ms) = scan_intv * 0.625.\n + * Valid range is 0x0000 and 0x0004 - 0xFFFF. + */ + uint16_t scan_intv; + + /** + * @brief Scan window. + * @details + * window(ms) = scan_window * 0.625.\n + * Valid range is 0x0000 and 0x0004 - 0xFFFF. + */ + uint16_t scan_window; +} st_ble_gap_scan_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_scan_param_t + * @brief Scan parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Own BD Address Type. + * @details + * In case of passive scan, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * the random address set by R_BLE_GAP_SetRandAddr() is used. + *
+ */ + uint8_t o_addr_type; + + /** + * @brief Scan Filter Policy. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_ALLOW_ADV_ALL(0x00) + * Accept all advertising and scan response PDUs except directed advertising + * PDUs not addressed to local device. + *
BLE_GAP_SCAN_ALLOW_ADV_WLST(0x01) + * Accept only advertising and scan response PDUs from remote devices + * whose address is registered in the White List.
+ * Directed advertising PDUs which are not addressed to local device is ignored. + *
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED(0x02) + * Accept all advertising and scan response PDUs except directed advertising + * PDUs whose the target address is identity address but doesn't address local device. + * However directed advertising PDUs whose the target address is the local resolvable private address + * are accepted. + *
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST(0x03)Accept all advertising and scan response PDUs.
+ * The following are excluded.
+ *
    + *
  • + * Advertising and scan response PDUs where the advertiser's + * identity address is not in the White List. + *
    • + *
  • + * Directed advertising PDUs whose the target address is identity address + * but doesn't address local device. + * However directed advertising PDUs whose the target address is the local + * resolvable private address are accepted. + *
    • + *
+ *
+ */ + uint8_t filter_policy; + + /** + * @brief Scan parameters 1M PHY. + * @details When this field is NULL, Controller doesn't set the scan parameters for 1M PHY. + */ + st_ble_gap_scan_phy_param_t * p_phy_param_1M; + + /** + * @brief Scan parameters Coded PHY. + * @details When this field is NULL, Controller doesn't set the scan parameters for Coded PHY. + */ + st_ble_gap_scan_phy_param_t * p_phy_param_coded; +} st_ble_gap_ext_scan_param_t; + +/******************************************************************************************************************//** + * @brief Scan parameters. + * @sa st_ble_gap_ext_scan_param_t + **********************************************************************************************************************/ +typedef st_ble_gap_ext_scan_param_t st_ble_gap_scan_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_on_t + * @brief Parameters configured when scanning starts. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Procedure type. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SC_PROC_OBS(0x00) + * Observation Procedure.
+ * Notify all advertising PDUs. + *
BLE_GAP_SC_PROC_LIM(0x01) + * Limited Discovery Procedure.
+ * Notify advertising PDUs from only devices in the limited discoverable mode. + *
BLE_GAP_SC_PROC_GEN(0x02) + * General Discovery Procedure.
+ * Notify advertising PDUs from devices in the limited discoverable mode and + * the general discoverable mode. + *
+ */ + uint8_t proc_type; + + /** + * @brief Filter duplicates. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_FILT_DUPLIC_DISABLE(0x00)Duplicate filter disabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE(0x01)Duplicate filter enabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02)Duplicate filtering enabled, reset for each scan period
+ */ + uint8_t filter_dups; + + /** + * @brief Scan duration. + * @details Time(ms) = duration * 10.\n + * Valid range is 0x0000 - 0xFFFF.\n + * If this field is set to 0x0000, scanning is continued until R_BLE_GAP_StopScan() is called.\n + * When the period field is zero and the time specified the duration field expires, + * BLE_GAP_EVENT_SCAN_TO event notifies the application layer that scanning stops. + */ + uint16_t duration; + + /** + * @brief Scan period. + * @details Time(s) = N * 1.28.\n + * Valid range is 0x0000 - 0xFFFF.\n + * If the duration field is set to 0x0000, this field is ignored. + */ + uint16_t period; +} st_ble_gap_scan_on_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_param_t + * @brief Connection parameters included in connection interval, slave latency, supervision timeout, ce length. + * @details This structure is used in R_BLE_GAP_CreateConn() and R_BLE_GAP_UpdConn(). + * + * Set the fields in this structure to match the following condition. + * + * Supervision_timeout(ms) >= (1 + conn_latency) * conn_intv_max_Time(ms) + * + * conn_intv_max_Time(ms) = conn_intv_max * 1.25 + * Supervision_timeout(ms) = sup_to * 10 + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Minimum connection interval. + * @details + * Time(ms) = conn_intv_min * 1.25.\n + * Valid range is 0x0006 - 0x0C80. + */ + uint16_t conn_intv_min; + + /** + * @brief Maximum connection interval. + * @details + * Time(ms) = conn_intv_max * 1.25.\n + * Valid range is 0x0006 - 0x0C80. + */ + uint16_t conn_intv_max; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Time(ms) = sup_to * 10.\n + * Valid range is 0x000A - 0x0C80. + */ + uint16_t sup_to; + + /** + * @brief Minimum CE Length. + * @details + * Valid range is 0x0000 - 0xFFFF. + */ + uint16_t min_ce_length; + + /** + * @brief Maximum CE Length. + * @details + * Valid range is 0x0000 - 0xFFFF. + */ + uint16_t max_ce_length; +} st_ble_gap_conn_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_phy_param_t + * @brief Connection parameters per PHY. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Scan interval. + * @details + * Time(ms) = scan_intv * 0.625.\n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t scan_intv; + + /** + * @brief Scan window. + * @details + * Time(ms) = scan_window * 0.625.\n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t scan_window; + + /** + * @brief Connection interval, slave latency, supervision timeout, and CE length. + */ + st_ble_gap_conn_param_t * p_conn_param; +} st_ble_gap_conn_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_create_conn_param_t + * @brief Connection parameters used in R_BLE_GAP_CreateConn(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field specifies whether the White List is used or not, when connecting with a remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_INIT_FILT_USE_ADDR(0x00)White List is not used.
+ * The remote device to be connected is specified by the remote_bd_addr field and
+ * the remote_bd_addr_type field is used. + *
BLE_GAP_INIT_FILT_USE_WLST(0x01)White List is used.
+ * The remote device registered in White List is connected with local device.
+ * The remote_bd_addr field and the remote_bd_addr_type field are ignored. + *
+ */ + uint8_t init_filter_policy; + + /** + * @brief Address of the device to be connected. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t remote_bd_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Address type of the device to be connected. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address or Public Identity Address
BLE_GAP_ADDR_RAND(0x01)Random Address or Random (Static) Identity Address
+ */ + uint8_t remote_bd_addr_type; + + /** + * @brief Address type which local device uses in creating a link with the remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.\n + * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.\n + * If the IRK of local device has not been registered in Resolving List, + * the random address set by R_BLE_GAP_SetRandAddr(). + *
+ */ + uint8_t own_addr_type; + + /** + * @brief Connection parameters for 1M PHY. + * @details If this field is set to NULL, 1M PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_1M; + + /** + * @brief Connection parameters for 2M PHY. + * @details If this field is set to NULL, 2M PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_2M; + + /** + * @brief Connection parameters for Coded PHY. + * @details If this field is set to NULL, Coded PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_coded; +} st_ble_gap_create_conn_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_rslv_list_key_set_t + * @brief IRK of a remote device and IRK type of local device used in R_BLE_GAP_ConfRslvList(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief IRK of a remote device to be registered in the Resolving List. + */ + uint8_t remote_irk[BLE_GAP_IRK_SIZE]; + + /** + * @brief IRK type of the local device to be registered in the Resolving List. + * @details + * | macro | description | + * |:------------------------------------- |:-------------------------------------------------- | + * | BLE_GAP_RL_LOC_KEY_ALL_ZERO(0x00) | All-zero IRK. | + * | BLE_GAP_RL_LOC_KEY_REGISTERED(0x01) | The IRK registered by R_BLE_GAP_SetLocIdInfo(). | + */ + uint8_t local_irk_type; +} st_ble_gap_rslv_list_key_set_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_phy_param_t + * @brief PHY configuration parameters used in R_BLE_GAP_SetPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Transmitter PHY preference. + * @details The tx_phys field is set to a bitwise OR of the following values. All other values are ignored. + * | macro | description | + * |:------------------------------------- |:---------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Use 1M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Use 2M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Use Coded PHY for Transmitter PHY. | + */ + uint8_t tx_phys; + + /** + * @brief Receiver PHY preference. + * @details The rx_phys field is set to a bitwise OR of the following values. All other values are ignored. + * | macro | description | + * |:------------------------------------- |:---------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Use 1M PHY for Receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Use 2M PHY for Receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Use Coded PHY for Receiver PHY. | + */ + uint8_t rx_phys; + + /** + * @brief Coding scheme used in Coded PHY. + * @details Select one of the following. + * | macro | description | + * |:---------------------------------------- |:----------------------- | + * | BLE_GAP_SET_PHYS_OP_HOST_NO_PREF(0x00) | No preferred coding. | + * | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2(0x01) | Use S=2 coding. | + * | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8(0x02) | Use S=8 coding. | + */ + uint16_t phy_options; +} st_ble_gap_set_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_def_phy_param_t + * @brief PHY preferences which allows a remote device to set used in R_BLE_GAP_SetDefPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Transmitter PHY preferences which a remote device may change. + * @details The tx_phys field is set to a bitwise OR of the following values. + * All other values are ignored. + * | macro | description | + * |:------------------------------------- |:----------------------------------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Allow a remote device to set 1M PHY for transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Allow a remote device to set 2M PHY for transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Allow a remote device to set Coded PHY for transmitter PHY. | + */ + uint8_t tx_phys; + + /** + * @brief Receiver PHY preferences which a remote device may change. + * @details The rx_phys field is set to a bitwise OR of the following values. + * All other values are ignored. + * | macro | description | + * |:------------------------------------- |:-------------------------------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Allow a remote device to set 1M PHY for receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Allow a remote device to set 2M PHY for receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Allow a remote device to set Coded PHY for receiver PHY. | + */ + uint8_t rx_phys; +} st_ble_gap_set_def_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_auth_info_t + * @brief Pairing parameters required from a remote device or + * information about keys distributed from a remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Security level. + * @details + * | value | description | + * |:--------|:----------------------------------------------------- | + * | 0x01 | The remote device requests Unauthenticated pairing. | + * | 0x02 | The remote device requests Authenticated pairing. | + */ + uint8_t security; + + /** + * @brief Pairing mode. + * @details + * | value | description | + * |:--------|:----------------------------------------------------- | + * | 0x01 | The remote device requests Legacy pairing. | + * | 0x02 | The remote device requests Secure Connections. | + */ + uint8_t pair_mode; + + /** + * @brief Bonding policy. + * @details + * | value | description | + * |:--------|:--------------------------------------------------------------- | + * | 0x00 | The remote device does not store the Bonding information. | + * | 0x01 | The remote device stores the Bonding information. | + */ + uint8_t bonding; + + /** + * @brief Encryption key size. + */ + uint8_t ekey_size; +} st_ble_gap_auth_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_dist_t + * @brief Keys distributed from a remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief LTK. + */ + uint8_t enc_info[BLE_GAP_LTK_SIZE]; + + /** + * @brief Ediv and rand. + * The first two bytes is ediv, the remaining bytes are rand. + */ + uint8_t mid_info[BLE_GAP_EDIV_SIZE + BLE_GAP_RAND_64_BIT_SIZE]; + + /** + * @brief IRK + */ + uint8_t id_info[BLE_GAP_IRK_SIZE]; + + /** + * @brief Identity address. The first byte is address type. The remaining bytes are device address. + */ + uint8_t id_addr_info[BLE_GAP_ID_ADDR_SIZE]; + + /** + * @brief CSRK + */ + uint8_t sign_info[BLE_GAP_CSRK_SIZE]; +} st_ble_gap_key_dist_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_ex_param_t + * @brief This structure includes the distributed keys and negotiated LTK size. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Key information. + */ + st_ble_gap_key_dist_t * p_keys_info; + + /** + * @brief Type of the distributed keys. + * @details + * This field is a bitwise OR of the following values. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Bit Numberdescription
0 + * LTK and Master Identification.
+ * LTK is distributed in Secure Connections, even if the bit is 1. + *
1IRK and Identity Address Information.
2CSRK
+ */ + uint8_t keys; + + /** + * @brief The negotiated LTK size. + */ + uint8_t ekey_size; +} st_ble_gap_key_ex_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_param_t + * @brief Pairing parameters used in R_BLE_GAP_SetPairingParams(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief IO capabilities of local device. + * @details + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_IOCAP_DISPLAY_ONLY(0x00) + * Output function : Local device has the ability to display a 6 digit decimal number.
+ * Input function : None
+ *
BLE_GAP_IOCAP_DISPLAY_YESNO(0x01) + * Output function : Output function : Local device has the ability to + * display a 6 digit decimal number.
+ * Input function : Local device has the ability to indicate 'yes' or 'no'
+ *
BLE_GAP_IOCAP_KEYBOARD_ONLY(0x02) + * Output function : None
+ * Input function : Local device has the ability to input the number '0' - '9'.
+ *
BLE_GAP_IOCAP_NOINPUT_NOOUTPUT(0x03) + * Output function : None
+ * Input function : None
+ *
BLE_GAP_IOCAP_KEYBOARD_DISPLAY(0x04) + * Output function : Output function : Local device has the ability to + * display a 6 digit decimal number.
+ * Input function : Local device has the ability to input the number '0' - '9'.
+ *
+ */ + uint8_t iocap; + + /** + * @brief MITM protection policy. + * @details + * Select one of the following. + * | macro | description | + * |:---------------------------------- |:------------------------------ | + * | BLE_GAP_SEC_MITM_BEST_EFFORT(0x00) | MITM Protection not required. | + * | BLE_GAP_SEC_MITM_STRICT (0x01) | MITM Protection required. | + */ + uint8_t mitm; + + /** + * @brief Bonding policy. + * @details + * | macro | description | + * |:---------------------------------- |:------------------------------------------------- | + * | BLE_GAP_BONDING_NONE(0x00) | Local device doesn't stores Bonding information. | + * | BLE_GAP_BONDING (0x01) | Local device stores Bonding information. | + */ + uint8_t bonding; + + /** + * @brief Maximum LTK size(in bytes). + * @details + * Valid range is 7 - 16.\n + * This field shall be set to a value not less than the min_key_size field. + */ + uint8_t max_key_size; + + /** + * @brief Minimum LTK size(in bytes). + * @details + * Valid range is 7 - 16.\n + * This field shall be set to a value not more than the max_key_size field. + */ + uint8_t min_key_size; + + /** + * @brief Type of keys to be distributed from local device. + * @details + * The loc_key_dist field is set to a bitwise OR of the following values. + * | macro | description | + * |:-------------------------------|:--------------------------- | + * | BLE_GAP_KEY_DIST_ENCKEY(0x01) | LTK | + * | BLE_GAP_KEY_DIST_IDKEY(0x02) | IRK and Identity Address. | + * | BLE_GAP_KEY_DIST_SIGNKEY(0x04) | CSRK | + */ + uint8_t loc_key_dist; + + /** + * @brief Type of keys which local device requests a remote device to distribute. + * @details + * The rem_key_dist field is set to a bitwise OR of the following values. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_KEY_DIST_ENCKEY(0x01) + * LTK. In case of Secure Connections, LTK is notified even if this bit is not set. + *
BLE_GAP_KEY_DIST_IDKEY(0x02) + * IRK and Identity Address. + *
BLE_GAP_KEY_DIST_SIGNKEY(0x04) + * CSRK + *
+ */ + uint8_t rem_key_dist; + + /** + * @brief Support for Key Press Notification in Passkey Entry. + * @details + * | macro | description | + * |:-----------------------------------------|:---------------------------------------- | + * | BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT(0x00) | Not support for Key Press Notification. | + * | BLE_GAP_SC_KEY_PRESS_NTF_SPRT(0x01) | Support for Key Press Notification. | + */ + uint8_t key_notf; + + /** + * @brief Determine whether to accept only Secure Connections or not. + * @details + * | macro | description | + * |:------------------------------|:--------------------------------------------- | + * | BLE_GAP_SC_BEST_EFFORT(0x00) | Accept Legacy pairing and Secure Connections. | + * | BLE_GAP_SC_STRICT(0x01) | Accept only Secure Connections. | + */ + uint8_t sec_conn_only; +} st_ble_gap_pairing_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_oob_data_t + * @brief Oob data received from the remote device. This is used in R_BLE_GAP_SetRemOobData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief OOB data used in Legacy Pairing. + */ + uint8_t legacy_oob[BLE_GAP_LEGACY_OOB_SIZE]; + + /** + * @brief OOB confirmation value used in Secure Connections. + */ + uint8_t sc_cnf_val[BLE_GAP_OOB_CONFIRM_VAL_SIZE]; + + /** + * @brief OOB rand used in Secure Connections. + */ + uint8_t sc_rand[BLE_GAP_OOB_RANDOM_VAL_SIZE]; +} st_ble_gap_oob_data_t; + +/* ============================================== GAP Event Parameters ============================================== */ + +/* Event Code : BLE_GAP_EVENT_STACK_ON : none */ + +/* Event Code : BLE_GAP_EVENT_STACK_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_LOC_VER_INFO : st_ble_gap_loc_dev_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ver_num_t + * @brief Version number of host stack. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Major version number. + */ + uint8_t major; + + /** + * @brief Minor version number. + */ + uint8_t minor; + + /** + * @brief Subminor version number. + */ + uint8_t subminor; +} st_ble_gap_ver_num_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_loc_ver_info_t + * @brief Version number of Controller. + * @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Bluetooth HCI version. + */ + uint8_t hci_ver; + + /** + * @brief Bluetooth HCI revision. + */ + uint16_t hci_rev; + + /** + * @brief Link Layer revision. + */ + uint8_t lmp_ver; + + /** + * @brief Manufacturer ID. + */ + uint16_t mnf_name; + + /** + * @brief Link Layer subversion. + */ + uint16_t lmp_sub_ver; +} st_ble_gap_loc_ver_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_loc_dev_info_evt_t + * @brief Version information of local device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Bluetooth Device Address. + */ + st_ble_dev_addr_t l_dev_addr; + + /** + * @brief Version number of host stack in local device. + */ + st_ble_gap_ver_num_t l_ver_num; + + /** + * @brief Version number of Controller in local device. + */ + st_ble_gap_loc_ver_info_t l_bt_info; +} st_ble_gap_loc_dev_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_HW_ERR : st_ble_gap_hw_err_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_hw_err_evt_t + * @brief Hardware error that is notified from Controller. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The hw_code field indicates the cause of the hardware error. + */ + uint8_t hw_code; +} st_ble_gap_hw_err_evt_t; + +/* Event Code : BLE_GAP_EVENT_CMD_ERR: st_ble_gap_cmd_err_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_cmd_err_evt_t + * @brief HCI Command error. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The opcode of HCI Command which caused the error. + */ + uint16_t op_code; + + /** + * @brief Module ID which caused the error. + */ + uint32_t module_id; +} st_ble_gap_cmd_err_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_REPT_IND: st_ble_gap_adv_rept_evt_t */ +/* ADV report related Event defines */ +/* Legacy ADV Report related structure */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_rept_t + * @brief Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Advertising Reports received. + */ + uint8_t num; + + /** + * @brief Type of Advertising Packet. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuerdescription
0x00Connectable and scannable undirected advertising(ADV_IND).
0x01Connectable directed advertising(ADV_DIRECT_IND).
0x02Scannable undirected advertising(ADV_SCAN_IND).
0x03Non-connectable undirected advertising(ADV_NONCONN_IND).
0x04Scan response(SCAN_RSP).
+ */ + uint8_t adv_type; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_addr; + + /** + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 31. + */ + uint8_t len; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Advertising data/Scan Response Data. + */ + uint8_t * p_data; +} st_ble_gap_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_adv_rept_t + * @brief Extended Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Advertising Reports received. + */ + uint8_t num; + + /** + * @brief Type of Advertising Packet. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Bit Numberdescription
0Connectable advertising.
1Scannable advertising.
2Directed advertising.
3Scan response.
4Legacy advertising PDU.
5-6The status of Advertising Data/Scan Response Data.
+ * Data Status:
+ * 00b = Complete
+ * 01b = Incomplete, more data come
+ * 10b = Incomplete, data truncated, no more to come
+ *
All other bitsReserved for future use
+ */ + uint16_t adv_type; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFF | Anonymous advertisement. | + */ + uint8_t addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_addr; + + /** + * @brief The primary PHY configuration of the advertiser. + * @details + * The primary PHY configuration of the advertiser. + * | value | description | + * |:--------- |:------------------------ | + * | 0x01 | 1M PHY | + * | 0x03 | Coded PHY | + */ + uint8_t adv_phy; + + /** + * @brief The secondary PHY configuration of the advertiser. + * @details + * | value | description | + * |:--------- |:---------------------------------------------------------------- | + * | 0x00 | Nothing has been received with Secondary Advertising Channel. | + * | 0x01 | The Secondary Advertising PHY configuration was 1M PHY. | + * | 0x02 | The Secondary Advertising PHY configuration was 2M PHY. | + * | 0x03 | The Secondary Advertising PHY configuration was Coded PHY. | + */ + uint8_t sec_adv_phy; + + /** + * @brief Advertising SID included in the received Advertising Report. + * @details Valid range is 0 <= adv_sid <= 0x0F and 0xFF.\n + * If the adv_sid is 0xFF, there is no field which includes SID. + */ + uint8_t adv_sid; + + /** + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that Tx power could not be retrieved. + */ + int8_t tx_pwr; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Periodic Advertising interval. + * @details If the perd_adv_intv is 0x0000, it means that this advertising is not periodic advertising.\n + * If the perd_adv_intv is 0x0006 - 0xFFFF, + * it means that this field is the Periodic Advertising interval.\n + * Periodic Advertising interval = per_adv_intr * 1.25ms. + */ + uint16_t perd_adv_intv; + + /** + * @brief The address type of Direct Advertising PDU. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFE | Resolvable Privacy Address which could not be resolved in Controller. | + */ + uint8_t dir_addr_type; + + /** + * @brief Address of Direct Advertising PDU. + * @note The BD address setting format is little endian. + */ + uint8_t * p_dir_addr; + + /** + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 229. + */ + uint8_t len; + + /** + * @brief Advertising data/Scan Response Data. + */ + uint8_t * p_data; +} st_ble_gap_ext_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_adv_rept_t + * @brief Periodic Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle. + * @details Valid range is 0x0000 - 0x0EFF. + */ + uint16_t sync_hdl; + + /** + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If tx_pwr is 127, it means that Tx power could not be retrieved. + */ + int8_t tx_pwr; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= rssi <= 20 and 127.\n + * If rssi is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Reserved for future use. + */ + uint8_t rfu; + + /** + * @brief Reserved for future use. + * @details + * | value | description | + * |:--------- |:------------------------------------------------------- | + * | 0x00 | Data Complete. | + * | 0x01 | Data incomplete, more data to come. | + * | 0x02 | Data incomplete, data truncated, no more to come. | + */ + uint8_t data_status; + + /** + * @brief Length of Periodic Advertising data(in bytes). + * @details Valid range is 0 - 247. + */ + uint8_t len; + + /** + * @brief Periodic Advertising data. + */ + uint8_t * p_data; +} st_ble_gap_perd_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_rept_evt_t + * @brief Advertising report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Data type. + * @details + * | value | description | + * |:-------------------- |:---------------------------------- | + * | 0x00 | Advertising Report. | + * | 0x01 | Extended Advertising Report. | + * | 0x02 | Periodic Advertising Report. | + * + * If the BLE Protocol Stack library type is "all features", + * the adv_rpt_type field in a Legacy Advertising Report event is 0x01. + */ + uint8_t adv_rpt_type; + + /** + * @brief Advertising Report. + */ + union + { + /** + * @brief Advertising Report. + */ + st_ble_gap_adv_rept_t * p_adv_rpt; + + /** + * @brief Extended Advertising Report. + */ + st_ble_gap_ext_adv_rept_t * p_ext_adv_rpt; + + /** + * @brief Periodic Advertising Report. + */ + st_ble_gap_perd_adv_rept_t * p_per_adv_rpt; + } param; +} st_ble_gap_adv_rept_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_OFF : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_set_evt_t + * @brief Advertising handle. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle specifying the advertising set configured advertising parameters. + */ + uint8_t adv_hdl; +} st_ble_gap_adv_set_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_OFF : st_ble_gap_adv_off_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_off_evt_t + * @brief Information about the advertising set which stops advertising. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set which has stopped advertising. + * @details Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief The reason for stopping advertising. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x01 + * Advertising has been stopped by R_BLE_GAP_StopAdv(). + *
0x02 + * Because the duration specified by R_BLE_GAP_StartAdv() was expired, + * advertising has terminated. + *
0x03 + * Because the max_extd_adv_evts parameter specified by R_BLE_GAP_StartAdv() was reached, + * advertising has terminated. + *
0x04 + * Because the connection was established with the remote device, advertising has terminated. + *
+ */ + uint8_t reason; + + /** + * @brief Connection handle. + * @details If the reason field is 0x04, this field indicates connection handle identifying + * the remote device connected with local device. + * If other reasons, ignore this field. + */ + uint16_t conn_hdl; + + /** + * @brief The number of the advertising event that has been received until advertising has terminated. + * @details If max_extd_adv_evts by R_BLE_GAP_StartAdv() is not 0, this parameter is valid. + */ + uint8_t num_comp_ext_adv_evts; +} st_ble_gap_adv_off_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_DATA_UPD_COMP : st_ble_gap_adv_data_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_data_evt_t + * @brief This structure notifies that advertising data has been set to Controller by R_BLE_GAP_SetAdvSresData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to + * which advertising data/scan response data/periodic advertising data is set. + */ + uint8_t adv_hdl; + + /** + * @brief Type of the data set to the advertising set. + * @details + * | value | description | + * |:------------------------------------ |:--------------------------- | + * | BLE_GAP_ADV_DATA_MODE(0x00) | Advertising data | + * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data | + * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data | + */ + uint8_t data_type; +} st_ble_gap_adv_data_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_SET_REMOVE_COMP : st_ble_gap_rem_adv_set_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rem_adv_set_evt_t + * @brief This structure notifies that an advertising set has been removed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field indicates that the advertising set has been removed or cleared. + * @details + * | value | description | + * |:-------- |:--------------------------------------- | + * | 0x01 | The advertising set has been removed. | + * | 0x02 | The advertising set has been cleared. | + */ + uint8_t remove_op; + + /** + * @brief Advertising handle identifying the advertising set which has been removed. + * @details If the advertising set has been cleared, this field is ignored. + */ + uint8_t adv_hdl; +} st_ble_gap_rem_adv_set_evt_t; + +/* Event Code : BLE_GAP_EVENT_SCAN_ON : none */ +/* Event Code : BLE_GAP_EVENT_SCAN_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_CONN_IND : st_ble_gap_conn_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_evt_t + * @brief This structure notifies that a link has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the created link. + */ + uint16_t conn_hdl; + + /** + * @brief The role of the link. + * @details + * | value | description | + * |:-------- |:-------------- | + * | 0x00 | Master | + * | 0x01 | Slave | + */ + uint8_t role; + + /** + * @brief Address type of the remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x00Public Address
0x01Random Address
0x02Public Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + *
0x03Random Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + * 		+ *
+ */ + uint8_t remote_addr_type; + + /** + * @brief Address of the remote device. + * @note The BD address setting format is little endian. + */ + uint8_t remote_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Resolvable private address that local device used in connection procedure. + * @details + * The local device address used in creating the link when the address type was set to + * BLE_GAP_ADDR_RPA_ID_PUBLIC or BLE_GAP_ADDR_RPA_ID_RANDOM by R_BLE_GAP_SetAdvParam() or + * R_BLE_GAP_CreateConn(). + * If the address type was set to other than BLE_GAP_ADDR_RPA_ID_PUBLIC and + * BLE_GAP_ADDR_RPA_ID_RANDOM, this field is set to all-zero. + * @note The BD address setting format is little endian. + */ + uint8_t local_rpa[BLE_BD_ADDR_LEN]; + + /** + * @brief Resolvable private address that the remote device used in connection procedure. + * @details + * This field indicates the remote resolvable private address when remote_addr_type is 0x02 or 0x03. + * If remote_addr_type is other than 0x02 and 0x03, this field is set to all-zero. + * @note The BD address setting format is little endian. + */ + uint8_t remote_rpa[BLE_BD_ADDR_LEN]; + + /** + * @brief Connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.Time(ms) = sup_to * 10. + */ + uint16_t sup_to; + + /** + * @brief Master_Clock_Accuracy. + * @details + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | + */ + uint8_t clk_acc; +} st_ble_gap_conn_evt_t; + +/* Event Code : BLE_GAP_EVENT_DISCONN_IND : st_ble_gap_disconn_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_disconn_evt_t + * @brief This structure notifies that a link has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link disconnected. + */ + uint16_t conn_hdl; + + /** + * @brief The reason for disconnection. + * @details + * Refer Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + */ + uint8_t reason; +} st_ble_gap_disconn_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_CANCEL_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_WHITE_LIST_CONF_COMP : st_ble_gap_white_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RAND_ADDR_SET_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_CH_MAP_RD_COMP : st_ble_gap_rd_ch_map_evt_t */ +/* Read Channel MAP */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_ch_map_evt_t + * @brief This structure notifies that Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link whose Channel Map was retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Channel Map. + */ + uint8_t ch_map[BLE_GAP_CH_MAP_SIZE]; +} st_ble_gap_rd_ch_map_evt_t; + +/* Event Code : BLE_GAP_EVENT_CH_MAP_SET_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_RSSI_RD_COMP : st_ble_gap_rd_rssi_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_rssi_evt_t + * @brief This structure notifies that RSSI has been retrieved by R_BLE_GAP_ReadRssi(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link whose RSSI was retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief RSSI(in dBm). + * @details + * Valid range is -127 < rssi < 20 and 127.\n + * If this field is 127, it indicates that RSSI could not be retrieved. + */ + int8_t rssi; +} st_ble_gap_rd_rssi_evt_t; + +/* Event Code : BLE_GAP_EVENT_GET_REM_DEV_INFO : st_ble_gap_dev_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_dev_info_evt_t + * @brief This structure notifies that information about remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device whose information has been retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Information about the remote device. This field is a bitwise OR of the following values. + * @details + * | Bit Number | description | + * |:-------------------|:------------------------------- | + * | bit0 | Address | + * | bit1 | Version, company_id, subversion | + * | bit2 | Feature | + * | All other bits | Reserved for future use | + */ + uint8_t get_status; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t addr; + + /** + * @brief The version of Link Layer of the remote device. + * @details + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + */ + uint8_t version; + + /** + * @brief The manufacturer ID of the remote device. + * @details + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + */ + uint16_t company_id; + + /** + * @brief The subversion of Link Layer. + */ + uint16_t subversion; + + /** + * @brief LE feature supported in the remote device. + * @details + * Refer to Core Spec Vol 6, Part B 4.6 FEATURE SUPPORT. + */ + uint8_t features[BLE_GAP_REM_FEATURE_SIZE]; +} st_ble_gap_dev_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_COMP : st_ble_gap_conn_upd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_upd_evt_t + * @brief This structure notifies that connection parameters has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the connection whose parameters has been updated. + */ + uint16_t conn_hdl; + + /** + * @brief Updated Connection Interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; + + /** + * @brief Updated slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Updated supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10. + */ + uint16_t sup_to; +} st_ble_gap_conn_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_REQ : st_ble_gap_conn_upd_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_upd_req_evt_t + * @brief This structure notifies that a request for connection parameters update has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that was requested to update connection parameters. + */ + uint16_t conn_hdl; + + /** + * @brief Minimum connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_min * 1.25. + */ + uint16_t conn_intv_min; + + /** + * @brief Maximum connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_max * 1.25. + */ + uint16_t conn_intv_max; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10 + */ + uint16_t sup_to; +} st_ble_gap_conn_upd_req_evt_t; + +/* Event Code : RBLE_GAP_EVENT_CONN_PARAM_UPD_RSP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED : st_ble_gap_conn_hdl_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only connection handle has occurred. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle. + */ + uint16_t conn_hdl; +} st_ble_gap_conn_hdl_evt_t; + +/* Event Code : BLE_GAP_EVENT_DATA_LEN_CHG : st_ble_gap_data_len_chg_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_data_len_chg_evt_t + * @brief This structure notifies that the packet data length has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that updated Data Length. + */ + uint16_t conn_hdl; + + /** + * @brief Updated transmission packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. + */ + uint16_t tx_octets; + + /** + * @brief Updated transmission time(us). + * @details + * Valid range is 0x0148 - 0x4290. + */ + uint16_t tx_time; + + /** + * @brief Updated receive packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. + */ + uint16_t rx_octets; + + /** + * @brief Updated receive time(us). + * @details + * Valid range is 0x0148 - 0x4290. + */ + uint16_t rx_time; +} st_ble_gap_data_len_chg_evt_t; + +/* Event Code : BLE_GAP_EVENT_RSLV_LIST_CONF_COMP : st_ble_gap_rslv_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RPA_EN_COMP : none */ +/* Event Code : BLE_GAP_EVENT_SET_RPA_TO_COMP : none */ +/* Event Code : BLE_GAP_EVENT_RD_RPA_COMP : st_ble_gap_rd_rpa_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_rpa_evt_t + * @brief This structure notifies that the local resolvable private address has been retrieved by R_BLE_GAP_ReadRpa(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The resolvable private address of local device. + */ + st_ble_dev_addr_t addr; +} st_ble_gap_rd_rpa_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_UPD : st_ble_gap_phy_upd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_phy_upd_evt_t + * @brief This structure notifies that PHY for a connection has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been updated. + */ + uint16_t conn_hdl; + + /** + * @brief Transmitter PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + */ + uint8_t tx_phy; + + /** + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | + */ + uint8_t rx_phy; +} st_ble_gap_phy_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_RD_COMP : st_ble_gap_phy_rd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_phy_rd_evt_t + * @brief This structure notifies that the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been retrieved the PHY settings. + */ + uint16_t conn_hdl; + + /** + * @brief Transmitter PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + */ + uint8_t tx_phy; + + /** + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | + */ + uint8_t rx_phy; +} st_ble_gap_phy_rd_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_SET_COMP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SCAN_REQ_RECV : st_ble_gap_scan_req_recv_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_req_recv_evt_t + * @brief This structure notifies that a Scan Request packet has been received from a Scanner. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set that has received the Scan Request. + */ + uint8_t adv_hdl; + + /** + * @brief Address type of the Scanner. + * @details + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t scanner_addr_type; + + /** + * @brief Address of the Scanner. + * @note The BD address setting format is little endian. + */ + uint8_t scanner_addr[BLE_BD_ADDR_LEN]; +} st_ble_gap_scan_req_recv_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_EST : st_ble_gap_sync_est_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sync_est_evt_t + * @brief This structure notifies that a Periodic sync has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle identifying the Periodic Sync that has been established. + */ + uint16_t sync_hdl; + + /** + * @brief Advertising SID identifying the advertising set that has established the Periodic Sync. + */ + uint8_t adv_sid; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t adv_addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_adv_addr; + + /** + * @brief Advertising PHY. + * @details + * | value | description | + * |:-----------|:---------------------------- | + * | 0x01 | Advertiser PHY is 1M PHY. | + * | 0x02 | Advertiser PHY is 2M PHY. | + * | 0x03 | Advertiser PHY is Coded PHY. | + */ + uint8_t adv_phy; + + /** + * @brief Periodic Advertising Interval. + * @details + * Valid range is 0x0006 - 0xFFFF.\n + * Time(ms) = perd_adv_intv * 1.25. + */ + uint16_t perd_adv_intv; + + /** + * @brief Advertiser Clock Accuracy. + * @details + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | + */ + uint8_t adv_clk_acc; +} st_ble_gap_sync_est_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_TERM : st_ble_gap_sync_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SYNC_LOST : st_ble_gap_sync_hdl_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sync_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only sync handle has occurred. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle. + */ + uint16_t sync_hdl; +} st_ble_gap_sync_hdl_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP : none */ +/* Event Code : BLE_GAP_EVENT_PERD_LIST_CONF_COMP : st_ble_gap_perd_list_conf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_white_list_conf_evt_t + * @brief This structure notifies that White List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for White List. + * @details + * | value | description | + * |:---------|:---------------------------------------- | + * | 0x01 | A device was added to White List. | + * | 0x02 | A device was deleted from White List. | + * | 0x03 | White List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from White List. + */ + uint8_t num; +} st_ble_gap_white_list_conf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_rslv_list_conf_evt_t + * @brief This structure notifies that Resolving List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for Resolving List. + * @details + * | value | description | + * |:---------|:-------------------------------------------- | + * | 0x01 | A device was added to Resolving List. | + * | 0x02 | A device was deleted from Resolving List. | + * | 0x03 | Resolving List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from Resolving List. + */ + uint8_t num; +} st_ble_gap_rslv_list_conf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_list_conf_evt_t + * @brief This structure notifies that Periodic Advertiser List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for Periodic Advertiser List. + * @details + * | value | description | + * |:---------|:------------------------------------------------------ | + * | 0x01 | A device was added to Periodic Advertiser List. | + * | 0x02 | A device was deleted from Periodic Advertiser List. | + * | 0x03 | Periodic Advertiser List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from Periodic Advertiser List. + */ + uint8_t num; +} st_ble_gap_perd_list_conf_evt_t; + +/* Event Code : BLE_GAP_EVENT_PRIV_MODE_SET_COMP : st_ble_gap_set_priv_mode_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_priv_mode_evt_t + * @brief This structure notifies that Privacy Mode has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number or devices which have been set privacy mode. + */ + uint8_t num; +} st_ble_gap_set_priv_mode_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_REQ : st_ble_gap_pairing_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_req_evt_t + * @brief This structure notifies that a pairing request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that sent the pairing request. + */ + uint16_t conn_hdl; + + /** + * @brief The address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief The Pairing parameters of the remote device. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_PASSKEY_ENTRY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ : st_ble_gap_passkey_display_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_passkey_display_evt_t + * @brief This structure notifies that a request for Passkey display in pairing has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that requested Passkey display. + */ + uint16_t conn_hdl; + + /** + * @brief Passkey. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t passkey; +} st_ble_gap_passkey_display_evt_t; + +/* Event Code : BLE_GAP_EVENT_NUM_COMP_REQ : st_ble_gap_num_comp_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_num_comp_evt_t + * @brief This structure notifies that a request for Numeric Comparison in pairing has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that requested Numeric Comparison. + */ + uint16_t conn_hdl; + + /** + * @brief The number to be confirmed in Numeric Comparison. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t numeric; +} st_ble_gap_num_comp_evt_t; + +/* Event Code : BLE_GAP_EVENT_KEY_PRESS_NTF : st_ble_gap_key_press_ntf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_press_ntf_evt_t + * @brief This structure notifies that the remote device has input a key in Passkey Entry + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that input a key. + */ + uint16_t conn_hdl; + + /** + * @brief Type of the key that the remote device input. + * @details + * | value | description | + * |:---------|:----------------------------- | + * | 0x00 | Passkey entry started. | + * | 0x01 | Passkey digit entered. | + * | 0x02 | Passkey digit erased. | + * | 0x03 | Passkey cleared. | + * | 0x04 | Passkey entry completed. | + */ + uint8_t key_type; +} st_ble_gap_key_press_ntf_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_COMP : st_ble_gap_pairing_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_info_evt_t + * @brief This structure notifies that the pairing has completed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that the pairing has been done with. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Key information exchanged in pairing. + * @details If local device supports bonding, store the information in non-volatile memory + * in order to set it to host stack after power re-supply. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_ENC_CHG : st_ble_gap_enc_chg_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_enc_chg_evt_t + * @brief This structure notifies that the encryption status of a link has been changed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been changed. + */ + uint16_t conn_hdl; + + /** + * @brief Encryption Status. + * @details + * | value | description | + * |:---------|:-------------------------------------------------------- | + * | 0x00 | Encryption OFF. | + * | 0x01 | Encryption ON. | + * | 0x03 | Encryption updated by Encryption Key Refresh Completed. | + */ + uint8_t enc_status; +} st_ble_gap_enc_chg_evt_t; + +/* Event Code : BLE_GAP_EVENT_PEER_KEY_INFO : st_ble_gap_peer_key_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_peer_key_info_evt_t + * @brief This structure notifies that the remote device has distributed the keys. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that has distributed the keys. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Distributed keys. + * @details + * If local device supports bonding, store the keys in non-volatile memory and + * at power re-supply set to the host stack by R_BLE_GAP_SetBondInfo(). + */ + st_ble_gap_key_ex_param_t key_ex_param; +} st_ble_gap_peer_key_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_EX_KEY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_LTK_REQ : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_req_evt_t + * @brief This structure notifies that a LTK request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device which requests for the LTK. + */ + uint16_t conn_hdl; + + /** + * @brief Ediv. + */ + uint16_t ediv; + + /** + * @brief Rand. + */ + uint8_t * p_peer_rand; +} st_ble_gap_ltk_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_LTK_RSP_COMP : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_rsp_evt_t + * @brief This structure notifies that local device has replied to the LTK request from the remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device to be sent the response to the LTK request. + */ + uint16_t conn_hdl; + + /** + * @brief The response to the LTK request. + * @details + * | value | description | + * |:---------|:----------------------------------------------------------------------- | + * | 0x00 | Local device replied with the stored LTK. | + * | 0x01 | Local device rejected the LTK request, because the LTK was not found. | + */ + uint8_t response; +} st_ble_gap_ltk_rsp_evt_t; + +/* Event Code : BLE_GAP_EVENT_SC_OOB_CREATE_COMP : st_ble_gap_sc_oob_data_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sc_oob_data_evt_t + * @brief This structure notifies that OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Confirmation value(16 bytes) of OOB Data. + */ + uint8_t * p_sc_oob_conf; + + /** + * @brief Rand(16bytes) of OOB Data. + */ + uint8_t * p_sc_oob_rand; +} st_ble_gap_sc_oob_data_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_bond_info_t + * @brief Bonding information used in R_BLE_GAP_SetBondInfo(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the device which exchanged the keys. + */ + st_ble_dev_addr_t * p_addr; + + /** + * @brief Information about the keys. + */ + st_ble_gap_auth_info_t * p_auth_info; + + /** + * @brief Keys distributed from the remote device in paring. + */ + st_ble_gap_key_ex_param_t * p_keys; +} st_ble_gap_bond_info_t; + +/*@}*/ + +/* ================================================= GAP Event Code ================================================= */ + +/** @addtogroup GAP_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @enum e_ble_gap_evt_t + * @brief GAP Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief Invalid GAP Event. + * + * ## Event Code: 0x1001 + * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_INVALID = 0x1001, + + /* Range for Generic events - 0x01 to 0x0F */ + + /** + * @brief Host Stack has been initialized. + * @details + * When initializing host stack by R_BLE_GAP_Init() has been completed, + * BLE_GAP_EVENT_STACK_ON event is notified. + * + * ## Event Code: 0x1002 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_ON, + + /** + * @brief Host Stack has been terminated. + * @details + * When terminating host stack by R_BLE_GAP_Terminate() has been completed, + * BLE_GAP_EVENT_STACK_OFF event is notified. + * + * ## Event Code: 0x1003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008)When function was called, host stack has not yet been initialized.
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_OFF, + + /** + * @brief Version information of local device. + * @details + * When version information of local device has been retrieved by R_BLE_GAP_GetVerInfo(), + * BLE_GAP_EVENT_LOC_VER_INFO event is notified. + * + * ## Event Code: 0x1004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_loc_dev_info_evt_t + */ + BLE_GAP_EVENT_LOC_VER_INFO, + + /** + * @brief Hardware Error. + * @details + * When hardware error has been received from Controller, BLE_GAP_EVENT_HW_ERR event is notified. + * + * ## Event Code: 0x1005 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_hw_err_evt_t + */ + BLE_GAP_EVENT_HW_ERR, + + /** + * @brief Command Status Error. + * @details + * When the error of HCI Command has occurred after a R_BLE GAP API call, BLE_GAP_EVENT_CMD_ERR event is notified. + * + * ## Event Code: 0x1101 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_cmd_err_evt_t + */ + BLE_GAP_EVENT_CMD_ERR = 0x1101, + + /** + * @brief Advertising Report. + * @details + * When advertising PDUs has been received after scanning was started by R_BLE_GAP_StartScan(). + * + * ## Event Code: 0x1102 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_rept_evt_t + */ + BLE_GAP_EVENT_ADV_REPT_IND, + + /** + * @brief Advertising parameters have been set. + * @details + * Advertising parameters have been configured by R_BLE_GAP_SetAdvParam(). + * + * ## Event Code: 0x1103 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising type that doesn't support advertising data/scan response data was + * specified to the advertising set which has already set + * advertising data/scan response data. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - Advertising parameters were configured to the advertising set in advertising.
+ * - The sec_adv_phy field in adv_paran was not specified + * when Periodic Advertising was started. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_PARAM_SET_COMP, + + /** + * @brief Advertising data has been set. + * @details + * This event notifies that Advertising Data/Scan Response Data/Periodic Advertising Data has been + * set to the advertising set by R_BLE_GAP_SetAdvSresData(). + * + * ## Event Code: 0x1104 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - The advertising set that doesn't support advertising data/scan response data + * was set to the data.
+ * - The advertising set that supports legacy advertising was set to + * advertising data/scan response data larger than 31 bytes.
+ * - The advertising set that has advertising data/scan response data greater + * than or equal to 252 bytes was set the data in advertising.
+ * - The advertising set that has periodic advertising data greater than or equal to + * 253 bytes was set the data in advertising. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Length exceeded the length that the advertising set could be set. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetAdvSresData() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_data_evt_t + */ + BLE_GAP_EVENT_ADV_DATA_UPD_COMP, + + /** + * @brief Advertising has started. + * @details + * When advertising has been started by R_BLE_GAP_StartAdv(), this event is notified to the application layer. + * + * ## Event Code: 0x1105 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows.
+ * - The advertising data length set to the advertising set + * for connectable extended advertising was invalid.
+ * - If o_addr_type field in adv_param used in R_BLE_GAP_SetAdvParam() is 0x03, + * the address which is set in o_addr field of adv_param + * has not been registered in Resolving List. + *
BLE_ERR_INVALID_OPERATION(0x0009)Setting of advertising data/scan response data has not been completed.
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StartAdv() has not been created. + *
BLE_ERR_LIMIT_EXCEEDED(0x0010)When the maximum connections are established, a new connectable advertising tried starting.
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_ON, + + /** + * @brief Advertising has stopped. + * @details + * This event notifies the application layer that advertising has stopped. + * + * ## Event Code: 0x1106 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StopAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_off_evt_t + */ + BLE_GAP_EVENT_ADV_OFF, + + /** + * @brief Periodic advertising parameters have been set. + * @details + * This event notifies the application layer that Periodic Advertising Parameters + * has been configured by R_BLE_GAP_SetPerdAdvParam(). + * + * ## Event Code: 0x1107 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising set was the setting for anonymous advertising. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The advertising set was configured to the parameters in periodic advertising. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetPerdAdvParam() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP, + + /** + * @brief Periodic advertising has started. + * @details + * When Periodic Advertising has been started by R_BLE_GAP_StartPerdAdv(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1108 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * The periodic advertising data set in the advertising set has not been completed. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StartPerdAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_ON, + + /** + * @brief Periodic advertising has stopped. + * @details + * When Periodic Advertising has terminated by R_BLE_GAP_StopPerdAdv(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1109 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StopPerdAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_OFF, + + /** + * @brief Advertising set has been deleted. + * @details + * When the advertising set has been removed by R_BLE_GAP_RemoveAdvSet(), + * this event is notified to the application layer. + * + * ## Event Code: 0x110A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When the advertising set was in advertising, R_BLE_GAP_RemoveAdvSet() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_RemoveAdvSet() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rem_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_SET_REMOVE_COMP, + + /** + * @brief Scanning has started. + * @details + * When scanning has started by R_BLE_GAP_StartScan(), + * this event is notified to the application layer. + * + * ## Event Code: 0x110B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows:
+ * - Scan interval or scan window was invalid. + * - When filter_dup field in scan_enable was BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02), + * period field in scan_enable was 0. + * - duration field in scan_enable was larger than period in scan_enable. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * In scanning, R_BLE_GAP_StartScan() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_ON, + + /** + * @brief Scanning has stopped. + * @details + * When scanning has been stopped by R_BLE_GAP_StopScan(), this event is notified to the application layer. + * + * ## Event Code: 0x110C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_OFF, + + /** + * @brief Scanning has stopped, because duration specified by API expired. + * @details + * When the scan duration specified by R_BLE_GAP_StartScan() has expired, + * this event notifies scanning has stopped. + * + * ## Event Code: 0x110D + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_TO, + + /** + * @brief Connection Request has been sent to Controller. + * @details + * This event notifies a request for a connection has been sent to Controller. + * + * ## Event Code: 0x110E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows:
+ * - Scan interval or scan windows specified by R_BLE_GAP_CreateConn() is invalid. + * - Although the own_addr_type field in p_param was set to 0x03, + * random address had not been registered in Resolving List. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * R_BLE_GAP_CreateConn() was called while creating a link + * by previous R_BLE_GAP_CreateConn() call . + *
BLE_ERR_LIMIT_EXCEEDED(0x0010) + * When the maximum connections are established, R_BLE_GAP_CreateConn() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CREATE_CONN_COMP, + + /** + * @brief Link has been established. + * @details + * This event notifies a link has been established. + * + * ## Event Code: 0x110F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_evt_t + */ + BLE_GAP_EVENT_CONN_IND, + + /** + * @brief Link has been disconnected. + * @details + * This event notifies a link has been disconnected. + * + * ## Event Code: 0x1110 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_disconn_evt_t + */ + BLE_GAP_EVENT_DISCONN_IND, + + /** + * @brief Connection Cancel Request has been sent to Controller. + * @details + * This event notifies the request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + * + * ## Event Code: 0x1111 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When a request for a connection has not been sent to Controller, + * R_BLE_GAP_CancelCreateConn() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CONN_CANCEL_COMP, + + /** + * @brief The White List has been configured. + * @details + * When White List has been configured, this event is notified to the application layer. + * + * ## Event Code: 0x1112 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * While doing advertising or scanning or creating a link with the White List, + * R_BLE_GAP_ConfWhiteList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * White List has already registered the maximum number of devices. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_white_list_conf_evt_t + */ + BLE_GAP_EVENT_WHITE_LIST_CONF_COMP, + + /** + * @brief Random address has been set to Controller. + * @details + * This event notifies Controller has been set the random address by R_BLE_GAP_SetRandAddr(). + * + * ## Event Code: 0x1113 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When local device was in legacy advertising, R_BLE_GAP_SetRandAddr() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_RAND_ADDR_SET_COMP, + + /** + * @brief Channel Map has been retrieved. + * @details + * This event notifies Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). + * + * ## Event Code: 0x1114 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_ReadChMap() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_ch_map_evt_t + */ + BLE_GAP_EVENT_CH_MAP_RD_COMP, + + /** + * @brief Channel Map has set. + * @details + * This event notifies Channel Map has been configured by R_BLE_GAP_SetChMap(). + * + * ## Event Code: 0x1115 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The channel map specified by R_BLE_GAP_SetChMap() was all-zero. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CH_MAP_SET_COMP, + + /** + * @brief RSSl has been retrieved. + * @details + * This event notifies RSSI has been retrieved by R_BLE_GAP_ReadRssi(). + * + * ## Event Code: 0x1116 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_ReadRssi() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_rssi_evt_t + */ + BLE_GAP_EVENT_RSSI_RD_COMP, + + /** + * @brief Information about the remote device has been retrieved. + * @details + * This event notifies information about the remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + * + * ## Event Code: 0x1117 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_dev_info_evt_t + */ + BLE_GAP_EVENT_GET_REM_DEV_INFO, + + /** + * @brief Connection parameters has been configured. + * @details + * This event notifies the connection parameters has been updated. + * + * ## Event Code: 0x1118 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_DATA(0x0002) + * Local device rejected the request for updating connection parameters. + *
BLE_ERR_INVALID_ARG(0x0003) + * The remote device rejected the connection parameters suggested from local device. + *
BLE_ERR_UNSUPPORTED(0x0007) + * The remote device doesn't support connection parameters update feature. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_upd_evt_t + */ + BLE_GAP_EVENT_CONN_PARAM_UPD_COMP, + + /** + * @brief Local device has received the request for configuration of connection parameters. + * @details + * This event notifies the request for connection parameters update has been received. + * + * ## Event Code: 0x1119 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_upd_req_evt_t + */ + BLE_GAP_EVENT_CONN_PARAM_UPD_REQ, + + /** + * @brief Authenticated Payload Timeout. + * @details + * This event notifies Authenticated Payload Timeout has occurred. + * + * ## Event Code: 0x111A + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED, + + /** + * @brief The request for update transmission packet size and transmission time have been sent to Controller. + * @details + * This event notifies a request for updating packet data length and transmission timer has been sent to Controller. + * + * ## Event Code: 0x111B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The tx_octets or tx_time parameter specified by R_BLE_GAP_SetDataLen() is invalid. + *
BLE_ERR_UNSUPPORTED(0x0007) + * The remote device does not support updating packet data length and transmission time. + *
BLE_ERR_INVALID_HDL(0x000E) + * When R_BLE_GAP_SetDataLen() was called, the connection was not established. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_SET_DATA_LEN_COMP, + + /** + * @brief Transmission packet size and transmission time have been changed. + * @details + * This event notifies packet data length and transmission time have been updated. + * + * ## Event Code: 0x111C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_data_len_chg_evt_t + */ + BLE_GAP_EVENT_DATA_LEN_CHG, + + /** + * @brief The Resolving List has been configured. + * @details + * When Resolving List has been configured by R_BLE_GAP_ConfRslvList(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, + * before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * While doing advertising or scanning or creating a link with resolvable private address, + * R_BLE_GAP_ConfRslvList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Resolving List has already registered the maximum number of devices. + *
BLE_ERR_INVALID_HDL(0x000E) + * The specified Identity Address was not found in Resolving List. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rslv_list_conf_evt_t + */ + BLE_GAP_EVENT_RSLV_LIST_CONF_COMP, + + /** + * @brief Resolvable private address function has been enabled or disabled. + * @details + * When Resolvable Private Address function in Controller has been enabled by R_BLE_GAP_EnableRpa(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_EnableRpa() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_RPA_EN_COMP, + + /** + * @brief The update time of resolvable private address has been changed. + * @details + * When Resolvable Private Address Timeout in Controller has been updated by R_BLE_GAP_SetRpaTo(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The rpa_timeout parameter specified by R_BLE_GAP_SetRpaTo() is out of range. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SET_RPA_TO_COMP, + + /** + * @brief The resolvable private address of local device has been retrieved. + * @details + * When the resolvable private address of local device has been retrieved by R_BLE_GAP_ReadRpa(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1120 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The identity address specified by R_BLE_GAP_ReadRpa() was not registered in Resolving List. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_rpa_evt_t + */ + BLE_GAP_EVENT_RD_RPA_COMP, + + /** + * @brief PHY for connection has been changed. + * @details + * This event notifies the application layer that PHY for a connection has been updated. + * + * ## Event Code: 0x1121 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_phy_upd_evt_t + */ + BLE_GAP_EVENT_PHY_UPD, + + /** + * @brief The request for updating PHY for connection has been sent to Controller. + * @details + * When Controller has received a request for updating PHY for a connection by R_BLE_GAP_SetPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1122 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_SetPhy() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PHY_SET_COMP, + + /** + * @brief The request for setting default PHY has been sent to Controller. + * @details + * When the PHY preferences which a remote device may change has been configured by R_BLE_GAP_SetDefPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1123 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_DEF_PHY_SET_COMP, + + /** + * @brief PHY configuration has been retrieved. + * @details + * When the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1124 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The link specified by R_BLE_GAP_ReadPhy() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_phy_rd_evt_t + */ + BLE_GAP_EVENT_PHY_RD_COMP, + + /** + * @brief Scan Request has been received. + * @details + * This event notifies the application layer that a Scan Request packet has been received from a Scanner. + * + * ## Event Code: 0x1125 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_scan_req_recv_evt_t + */ + BLE_GAP_EVENT_SCAN_REQ_RECV, + + /** + * @brief The request for establishing a periodic sync has been sent to Controller. + * @details + * This event notifies the application layer that Controller has received a request + * for a Periodic Sync establishment. + * + * ## Event Code: 0x1126 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When R_BLE_GAP_CreateSync() was called, + * this event for previous the API call has not been received. + *
BLE_ERR_ALREADY_IN_PROGRESS(0x000A) + * The advertising set specified by R_BLE_GAP_CreateSync() has already established + * a periodic sync. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CREATE_SYNC_COMP, + + /** + * @brief The periodic advertising sync has been established. + * @details + * This event notifies the application layer that a Periodic sync has been established. + * + * ## Event Code: 0x1127 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_NOT_YET_READY(0x0012) + * The request for a Periodic Sync establishment was cancelled by R_BLE_GAP_CancelCreateSync(). + *
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_est_evt_t + */ + BLE_GAP_EVENT_SYNC_EST, + + /** + * @brief The periodic advertising sync has been terminated. + * @details + * This event notifies the application layer that the Periodic Sync has been terminated + * by R_BLE_GAP_TerminateSync(). + * + * ## Event Code: 0x1128 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * While establishing a Periodic Sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_TerminateSync() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The sync handle specified by R_BLE_GAP_TerminateSync() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_SYNC_TERM, + + /** + * @brief The periodic advertising sync has been lost. + * @details + * This event notifies the application layer that the Periodic Sync has been lost. + * + * ## Event Code: 0x1129 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_SYNC_LOST, + + /** + * @brief The request for cancel of establishing a periodic advertising sync has been sent to Controller. + * @details + * This event notifies the request for a Periodic Sync establishment has been cancelled + * by R_BLE_GAP_CancelCreateSync(). + * + * ## Event Code: 0x112A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When R_BLE_GAP_CancelCreateSync() was called, + * a request for a Periodic Sync establishment by R_BLE_GAP_CreateSync() + * has not been sent to Controller. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP, + + /** + * @brief The Periodic Advertiser list has been configured. + * @details + * When Periodic Advertiser List has been configured by R_BLE_GAP_ConfPerdAdvList(), + * this event is notified to the application layer. + * + * ## Event Code: 0x112B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertiser has already been registered in Periodic Advertiser List. + *
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * When establishing a periodic sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_ConfPerdAdvList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Periodic Advertiser List has already registered the maximum number of devices. + *
BLE_ERR_INVALID_HDL(0x000E) + * The device specified by R_BLE_GAP_ConfPerdAdvList() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_perd_list_conf_evt_t + */ + BLE_GAP_EVENT_PERD_LIST_CONF_COMP, + + /** + * @brief Privacy Mode has been configured. + * @details + * This event notifies the application layer that the Privacy Mode has been configured by R_BLE_GAP_SetPrivMode(). + * + * ## Event Code: 0x112B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)Address type or privacy mode is out of range.
BLE_ERR_INVALID_OPERATION(0x0009) + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_SetPrivMode() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The address specified by R_BLE_GAP_SetPrivMode() has not been registered + * in Resolving List. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_PRIV_MODE_SET_COMP, + + /** + * @brief The pairing request from a remote device has been received. + * @details + * This event notifies the application layer that a pairing request from a remote device has been received. + * + * ## Event Code: 0x1401 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_pairing_info_evt_t + */ + BLE_GAP_EVENT_PAIRING_REQ = 0x1401, + + /** + * @brief The request for input passkey has been received. + * @details + * This event notifies that a request for Passkey input in pairing has been received. + * + * ## Event Code: 0x1402 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PASSKEY_ENTRY_REQ, + + /** + * @brief The request for displaying a passkey has been received. + * @details + * This event notifies that a request for Passkey display in pairing has been received. + * + * ## Event Code: 0x1403 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_passkey_display_evt_t + */ + BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ, + + /** + * @brief The request for confirmation with Numeric Comparison has received. + * @details + * This event notifies that a request for Numeric Comparison in pairing has been received. + * + * ## Event Code: 0x1404 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_num_comp_evt_t + */ + BLE_GAP_EVENT_NUM_COMP_REQ, + + /** + * @brief Key Notification from a remote device has been received. + * @details + * This event notifies the application layer that the remote device has input a key in Passkey Entry. + * + * ## Event Code: 0x1405 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_key_press_ntf_evt_t + */ + BLE_GAP_EVENT_KEY_PRESS_NTF, + + /** + * @brief Pairing has been completed. + * @details + * This event notifies the application layer that the pairing has completed. + * + * ## Event Code: 0x1406 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL(0x2001)PassKey Entry is failed.
BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE(0x2002)OOB Data is not available.
BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET(0x2003)The requested pairing can not be performed because of IO Capability.
BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH(0x2004)Confirmation value does not match.
BLE_ERR_SMP_LE_PAIRING_NOT_SPRT(0x2005)Pairing is not supported.
BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE(0x2006)Encryption Key Size is insufficient.
BLE_ERR_SMP_LE_CMD_NOT_SPRT(0x2007)The pairing command received is not supported.
BLE_ERR_SMP_LE_UNSPECIFIED_REASON(0x2008)Pairing failed with an unspecified reason.
BLE_ERR_SMP_LE_REPEATED_ATTEMPTS(0x2009)The number of repetition exceeded the upper limit.
BLE_ERR_SMP_LE_INVALID_PARAM(0x200A)Invalid parameter is set.
BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL(0x200B)DHKey Check error.
BLE_ERR_SMP_LE_NUM_COMP_FAIL(0x200C)Numeric Comparison failure.
BLE_ERR_SMP_LE_DISCONNECTED(0x200F)Disconnection in pairing.
BLE_ERR_SMP_LE_TO(0x2011) Failure due to timeout.
BLE_ERR_SMP_LE_LOC_KEY_MISSING(0x2014)Pairing/Encryption failure because local device lost the LTK.
+ *
+ * + * ## Event Data: + * st_ble_gap_pairing_info_evt_t + */ + BLE_GAP_EVENT_PAIRING_COMP, + + /** + * @brief Key Notification from a remote device has been received. + * @details + * This event notifies the application layer that the encryption status of a link has been changed. + * + * ## Event Code: 0x1407 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_enc_chg_evt_t + */ + BLE_GAP_EVENT_ENC_CHG, + + /** + * @brief Keys has been received from a remote device. + * @details + * This event notifies the application layer that the remote device has distributed the keys. + * + * ## Event Code: 0x1408 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_peer_key_info_evt_t + */ + BLE_GAP_EVENT_PEER_KEY_INFO, + + /** + * @brief The request for key distribution has been received. + * @details + * When local device has been received a request for key distribution to remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x1409 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_EX_KEY_REQ, + + /** + * @brief LTK has been request from a remote device. + * @details + * When local device has been received a LTK request from a remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x140A + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_ltk_req_evt_t + */ + BLE_GAP_EVENT_LTK_REQ, + + /** + * @brief LTK reply has been sent to Controller. + * @details + * When local device has replied to the LTK request from the remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x140B + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_ltk_rsp_evt_t + */ + BLE_GAP_EVENT_LTK_RSP_COMP, + + /** + * @brief The authentication data to be used in Secure Connections OOB has been created. + * @details + * This event notifies OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + * + * ## Event Code: 0x140C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_sc_oob_data_evt_t + */ + BLE_GAP_EVENT_SC_OOB_CREATE_COMP, +} e_ble_gap_evt_t; + +/*@}*/ + +/* ========================================== GATT Server Type Definitions ========================================== */ + +/** @addtogroup GATT_SERVER_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_value_t + * @brief Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Length of the attribute value. + */ + uint16_t value_len; + + /** + * @brief Attribute Value. + */ + uint8_t * p_value; +} st_ble_gatt_value_t; + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_hdl_value_pair_t + * @brief Attribute handle and attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle + */ + uint16_t attr_hdl; + + /** + * @brief Attribute Value + */ + st_ble_gatt_value_t value; +} st_ble_gatt_hdl_value_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_att_val_t + * @brief Queued writes Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Value for Queued Write . + */ + uint8_t * p_value; + + /** + * @brief Length of the attribute value. + */ + uint16_t value_len; + + /** + * @brief padding. + */ + uint16_t padding; +} st_ble_gatt_queue_att_val_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_pair_t + * @brief Queued writes Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Value for Queued Write + */ + st_ble_gatt_queue_att_val_t queue_value; + + /** + * @brief Attribute Handle + */ + uint16_t attr_hdl; +} st_ble_gatt_queue_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_elm_t + * @brief Prepare Write Queue element for long chracteristic. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Part of Long Characteristic Value and Characteristic Value Handle. + */ + st_ble_gatt_queue_pair_t queue_value_pair; + + /** + * @brief Offset that indicates the location to be written. + */ + uint16_t offset; +} st_ble_gatt_queue_elm_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_pre_queue_t + * @brief Prepare Write Queue for long chracteristic. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Buffer start address for Write Long Characteristic Request. + */ + uint8_t * p_buf_start; + + /** + * @brief Prepare Write Queue for Long Characteristic Value. + */ + st_ble_gatt_queue_elm_t * p_queue; + + /** + * @brief Buffer length. + */ + uint16_t buffer_len; + + /** + * @brief Connection Handle. + */ + uint16_t conn_hdl; + + /** + * @brief Current buffer offset. + */ + uint16_t buf_offset; + + /** + * @brief Number of elements in the prepare write queue. + */ + uint8_t queue_size; + + /** + * @brief Index of Prepare Write Queue. + */ + uint8_t queue_idx; +} st_ble_gatt_pre_queue_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_params_t + * @brief Attribute value to be set to or retrieved from the GATT Database and the access type from the GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute value to be set to or retrieved from the GATT Database. + * Note that the address of the value field in the value field is invalid in case of read access. + */ + st_ble_gatt_value_t value; + + /** + * @brief Attribute handle identifying the attribute to be set or retrieved. + */ + uint16_t attr_hdl; + + /** + * @brief Type of the access to GATT Database from the GATT Client. + * @sa access_type_to_gatt_database + */ + uint8_t db_op; +} st_ble_gatts_db_params_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_conn_hdl_t + * @brief Information about the service or the characteristic that the attribute belongs to. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Client that accesses to the GATT DataBase. + */ + uint16_t conn_hdl; + + /** + * @brief ID of the service that the attribute belongs to. + */ + uint8_t service_id; + + /** + * @brief ID of the Characteristic that the attribute belongs to. + */ + uint8_t char_id; +} st_ble_gatts_db_conn_hdl_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_access_evt_t + * @brief This structure notifies that the GATT Database has been accessed from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Information about the service or the characteristic that the attribute belongs to. + */ + st_ble_gatts_db_conn_hdl_t * p_handle; + + /** + * @brief Attribute value to be set to or retrieved from the GATT Database + * and the access type from the GATT Client. + */ + st_ble_gatts_db_params_t * p_params; +} st_ble_gatts_db_access_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_conn_evt_t + * @brief This structure notifies that the link with the GATT Client has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Client. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gatts_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_disconn_evt_t + * @brief This structure notifies that the link with the GATT Client has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Client. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gatts_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_ex_mtu_req_evt_t + * @brief This structure notifies that a MTU Exchange Request PDU has been received from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Maximum receive MTU size by GATT Client. + */ + uint16_t mtu; +} st_ble_gatts_ex_mtu_req_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_cfm_evt_t + * @brief This structure notifies that a Confirmation PDU has been received from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic sent by the Indication PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_cfm_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_by_type_rsp_evt_t + * @brief This structure notifies that a Read By Type Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read By Type Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_by_type_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_rsp_evt_t + * @brief This structure notifies that a Read Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_blob_rsp_evt_t + * @brief This structure notifies that a Read Blob Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read Blob Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_blob_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_multi_rsp_evt_t + * @brief This structure notifies that a Read Multiple Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of attribute read by the Read Multiple Request PDU. + */ + uint8_t count; + + /** + * @brief The list of attribute read by the Read Multiple Request PDU. + */ + uint16_t * p_attr_hdl_list; +} st_ble_gatts_read_multi_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_write_rsp_evt_t + * @brief This structure notifies that a Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic written by the Write Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_write_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_prepare_write_rsp_evt_t + * @brief This structure notifies that a Prepare Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic written by the Prepare Write Request PDU. + */ + uint16_t attr_hdl; + + /** + * @brief The length of written bytes by the Prepare Write Request PDU. + */ + uint16_t length; + + /** + * @brief The offset of the first octet to be written. + */ + uint16_t offset; +} st_ble_gatts_prepare_write_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_exe_write_rsp_evt_t + * @brief This structure notifies that a Execute Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The flag that indicates whether execution or cancellation. + * @details + * | value | description | + * |:-----------|:----------------- | + * | 0x00 | Cancellation. | + * | 0x01 | Execution. | + */ + uint8_t exe_flag; +} st_ble_gatts_exe_write_rsp_evt_t; + +/* GATT DB Structure */ + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_uuid_cfg_t + * @brief A structure that defines the information on the position where UUIDs are used. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The position of the defined UUID is specified by offset value in uuid_table of st_ble_gatts_db_cfg_t. + */ + uint16_t offset; + + /** + * @brief The attribute handle that indicates the first position in st_ble_gatts_db_attr_cfg_t + * for the defined UUID is specified. + */ + uint16_t first; + + /** + * @brief The attribute handle that indicates the last position in st_ble_gatts_db_attr_cfg_t + * for the defined UUID is specified. + */ + uint16_t last; +} st_ble_gatts_db_uuid_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_attr_cfg_t + * @brief A structure that defines the detailed information of the attributes. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The properties of attribute are specified. + * @details Set the following properties by a bitwise OR. + * | macro | description | + * |:------------------------------------------|:-------------------------------------- | + * | BLE_GATT_DB_READ(0x01) | Allow clients to read. | + * | BLE_GATT_DB_WRITE(0x02) | Allow clients to write. | + * | BLE_GATT_DB_WRITE_WITHOUT_RSP(0x04) | Allow clients to write. | + * | BLE_GATT_DB_READ_WRITE(0x07) | Allow clients to access of all. | + */ + uint8_t desc_prop; + + /** + * @brief The auxiliary properties of attribute are specified. + * @details Set the following properties by a bitwise OR. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_NO_AUXILIARY_PROPERTY(0x00) + * No auxiliary properties.\n + * It is invalid when used with other properties at the same time. + *
BLE_GATT_DB_FIXED_LENGTH_PROPERTY(0x01) + * Fixed length attribute value. + *
BLE_GATT_DB_AUTHORIZATION_PROPERTY(0x02) + * Attributes requiring authorization. + *
BLE_GATT_DB_ATTR_DISABLED(0x10) + * The attribute is disabled. + * If this value is set, the attribute cannot be found and accessed by a GATT Client. + * It is invalid when used with other properties at the same time. + *
BLE_GATT_DB_128_BIT_UUID_FORMAT(0x20) + * Attribute with 128 bit UUID.\n + * If this macro is not set, the attribute value is 16-bits UUID. + *
BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY(0x40) + * Attribute managed by each GATT Client. + *
BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY(0x80) + * Fixed attribute value.\n + * Writing from Client and setting from Server are prohibited. + *
+ */ + uint8_t aux_prop; + + /** + * @brief The length of the attribute value is specified. + */ + uint16_t length; + + /** + * @brief The position of the next attribute with the same UUID + * as the defined attribute is specified by an attribute handle. + */ + uint16_t next; + + /** + * @brief The storage area of attribute value. + * @details UUID of the defined attribute is set by specifying the position of the UUID registered + * in uuid_table of st_ble_gatts_db_cfg_t with the array offset value. + */ + uint16_t uuid_offset; + + /** + * @brief Storage area of attribute value. + * @details The address in the array registered in No.1-No.4 is specified to set the attribute value storage area of the defined attribute. + */ + uint8_t * p_data_offset; +} st_ble_gatts_db_attr_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_attr_list_t + * @brief The number of attributes are stored. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of the services or the characteristics. + */ + uint8_t count; +} st_ble_gatts_db_attr_list_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_char_cfg_t + * @brief A structure that defines the detailed information of the characteristics. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The total number of attributes in the defined characteristic is specified. + */ + st_ble_gatts_db_attr_list_t list; + + /** + * @brief The first attribute handle of the characteristic is specified. + */ + uint16_t start_hdl; + + /** + * @brief The index of service to which the characteristic belongs is specified. + */ + uint8_t service_id; +} st_ble_gatts_db_char_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_serv_cfg_t + * @brief A structure that defines the detailed information of the characteristics. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The total number of service declarations in the defined service is specified. + */ + st_ble_gatts_db_attr_list_t list; + + /** + * @brief The properties of the defined service are specified. + * @details Set the security level, the security mode and the key size with a bitwise OR. + * The bit0-bit3 are specified as the security level. + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_SECURITY_UNAUTH(0x00000001)Unauthenticated pairing(Security Mode1 Security Level 2, Security Mode 2 Security Level 1)
+ * Unauthenticated pairing is required to access the service. + *
BLE_GATT_DB_SER_SECURITY_AUTH(0x00000002)Authenticated pairing(Security Mode1 Security Level 3, Security Mode 2 Security Level 2)
+ * Authenticated pairing is required to access the service. + *
BLE_GATT_DB_SER_SECURITY_SECONN(0x00000004)Authenticated LE secure connections that generates 16bytes LTK(Security Mode1 Security Level 4)
+ * Authenticated LE secure connections pairing that generates 16bytes LTK is required to access the service. If this bit is set, bit24-27 are ignored. + *
+ *
+ * The bit4 is specified as the security mode.
+ * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_SECURITY_ENC(0x00000010)Encryption
+ * Encryption by the LTK exchanged in pairing is required to access.
+ *
+ * If the security requirement of the service is not needed, + * specify the bit0-bit4 to BLE_GATT_DB_SER_NO_SECURITY_PROPERTY(0x00000000).(Security Mode1 Security Level 1)
+ * The bit24-bit27 are specified as the key size required by the defined service.
+ * Select one of the following.
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7(0x01000000)7-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8(0x02000000)8-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9(0x03000000)9-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10(0x04000000)10-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11(0x05000000)11-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12(0x06000000)12-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13(0x07000000)13-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14(0x08000000)14-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15(0x09000000)15-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16(0x0A000000)16-byte encryption key.
BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE(0x00000000)7-byte or larger encryption key.
+ *
+ * Other bits are reserved.
+ */ + uint32_t desc; + + /** + * @brief The start attribute handle of the defined service is specified. + */ + uint16_t start_hdl; + + /** + * @brief The end attribute handle of the defined service is specified. + */ + uint16_t end_hdl; + + /** + * @brief The start index of the characteristic that belongs to the defined service is specified. + */ + uint8_t char_start_idx; + + /** + * @brief The end index of the characteristic that belongs to the defined service is specified. + */ + uint8_t char_end_idx; +} st_ble_gatts_db_serv_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_cfg_t + * @brief This is the structure of GATT Database that is specified in R_BLE_GATTS_SetDbInst(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The array to register the UUID to be used. + */ + const uint8_t * p_uuid_table; + + /** + * @brief The array to register variable attribute values. + */ + uint8_t * p_attr_val_table; + + /** + * @brief The array to register fixed attribute values. + */ + const uint8_t * p_const_attr_val_table; + + /** + * @brief The array to manage the attribute values handled for each GATT client. + */ + uint8_t * p_rem_spec_val_table; + + /** + * @brief The array to register the default of the attribute value handled by each GATT client. + */ + const uint8_t * p_const_rem_spec_val_table; + + /** + * @brief The array to register information on the position where UUIDs are used. + */ + const st_ble_gatts_db_uuid_cfg_t * p_uuid_cfg; + + /** + * @brief The array to register the detailed information of attributes. + */ + const st_ble_gatts_db_attr_cfg_t * p_attr_cfg; + + /** + * @brief The array to register the detailed information of characteristics. + */ + const st_ble_gatts_db_char_cfg_t * p_char_cfg; + + /** + * @brief The array to register the detailed information of services. + */ + const st_ble_gatts_db_serv_cfg_t * p_serv_cfg; + + /** + * @brief The number of services included in the GATT Database. + */ + uint8_t serv_cnt; + + /** + * @brief The number of characteristics included in the GATT Database. + */ + uint8_t char_cnt; + + /** + * @brief The number of UUIDs included in the GATT Database. + */ + uint8_t uuid_type_cnt; + + /** + * @brief The total size of attribute value that needs to be managed for each GATT client. + */ + uint8_t peer_spec_val_cnt; +} st_ble_gatts_db_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_evt_data_t + * @brief st_ble_gatts_evt_data_t is the type of the data notified in a GATT Server Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Client. + */ + uint16_t conn_hdl; + + /** + * @brief The size of GATT Server Event parameters. + */ + uint16_t param_len; + + /** + * @brief GATT Server Event parameters. This parameter differs in each GATT Server Event. + */ + void * p_param; +} st_ble_gatts_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_gatts_app_cb_t + * @brief ble_gatts_app_cb_t is the GATT Server Event callback function type. + * @param[in] event_type The type of GATT Server Event. + * @param[in] event_result The result of GATT Server Event + * @param[in] p_event_data Data notified by GATT Server Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gatts_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gatts_evt_data_t * p_event_data); + +/*@}*/ + +/* ========================================== GATT Client Type Definitions ========================================== */ + +/** @addtogroup GATT_CLIENT_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_hdl_range_t + * @brief Attribute handle range. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Start Attribute Handle. + */ + uint16_t start_hdl; + + /** + * @brief End Attribute Handle. + */ + uint16_t end_hdl; +} st_ble_gatt_hdl_range_t; + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @struct st_ble_gattc_reliable_writes_char_pair_t + * @brief This is used in R_BLE_GATTC_ReliableWrites() to specify the pair of Characteristic Value and + * Characteristic Value Handle. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Pair of Characteristic Value and Characteristic Value Handle. + */ + st_ble_gatt_hdl_value_pair_t write_data; + + /** + * @brief Offset that indicates the location to be written. + * @details Normally, set 0 to this parameter.\n + * If this parameter sets to a value other than 0,Adjust the offset parameter and the length of + * the value to be written not to exceed the length of the Characteristic. + */ + uint16_t offset; +} st_ble_gattc_reliable_writes_char_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_conn_evt_t + * @brief This structure notifies that the link with the GATT Server has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Server. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gattc_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_disconn_evt_t + * @brief This structure notifies that the link with the GATT Server has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Server. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gattc_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ex_mtu_rsp_evt_t + * @brief This structure notifies that a MTU Exchange Response PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief MTU size(in bytes) that GATT Server can receive. + */ + uint16_t mtu; +} st_ble_gattc_ex_mtu_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_serv_16_evt_t + * @brief This structure notifies that a 16-bit UUID Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle range of the 16-bit UUID service. + */ + st_ble_gatt_hdl_range_t range; + + /** + * @brief Service UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_serv_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_serv_128_evt_t + * @brief This structure notifies that a 128-bit UUID Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle range of the 128-bit UUID service. + */ + st_ble_gatt_hdl_range_t range; + + /** + * @brief Service UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_serv_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_inc_serv_16_evt_t + * @brief This structure notifies that a 16-bit UUID Included Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Service Declaration handle of the 16-bit UUID Included Service. + */ + uint16_t decl_hdl; + + /** + * @brief The contents of the Included Service. + */ + st_ble_gattc_serv_16_evt_t service; +} st_ble_gattc_inc_serv_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_inc_serv_128_evt_t + * @brief This structure notifies that a 128-bit UUID Included Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Service Declaration handle of the 128-bit UUID Included Service. + */ + uint16_t decl_hdl; + + /** + * @brief The contents of the Included Service. + */ + st_ble_gattc_serv_128_evt_t service; +} st_ble_gattc_inc_serv_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_16_evt_t + * @brief This structure notifies that a 16-bit UUID Characteristic has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle of Characteristic Declaration. + */ + uint16_t decl_hdl; + + /** + * @brief Characteristic Properties. + * @details It is a bitwise OR of the following values.\n + * Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties" + * regarding the details of the Characteristic Properties. + * | value | description | + * |:-----------|:------------------------------------ | + * | 0x01 | Broadcast property | + * | 0x02 | Read property | + * | 0x04 | Write Without Response property | + * | 0x08 | Write property | + * | 0x10 | Notify property | + * | 0x20 | Indicate property | + * | 0x40 | Authenticated Signed Writes property | + * | 0x80 | Extended Properties property | + */ + uint8_t cproperty; + + /** + * @brief Value Handle of the Characteristic. + */ + uint16_t value_hdl; + + /** + * @brief Characteristic UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_char_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_128_evt_t + * @brief This structure notifies that a 128-bit UUID Characteristic has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Declaration. + */ + uint16_t decl_hdl; + + /** + * @brief Characteristic Properties. + * @details It is a bitwise OR of the following values.\n + * Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties" + * regarding the details of the Characteristic Properties. + * | value | description | + * |:-----------|:------------------------------------ | + * | 0x01 | Broadcast property | + * | 0x02 | Read property | + * | 0x04 | Write Without Response property | + * | 0x08 | Write property | + * | 0x10 | Notify property | + * | 0x20 | Indicate property | + * | 0x40 | Authenticated Signed Writes property | + * | 0x80 | Extended Properties property | + */ + uint8_t cproperty; + + /** + * @brief Value Handle of the Characteristic. + */ + uint16_t value_hdl; + + /** + * @brief Characteristic UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_char_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_desc_16_evt_t + * @brief This structure notifies that a 16-bit UUID Characteristic Descriptor has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Descriptor. + */ + uint16_t desc_hdl; + + /** + * @brief Characteristic Descriptor UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_char_desc_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_desc_128_evt_t + * @brief This structure notifies that a 128-bit UUID Characteristic Descriptor has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Descriptor. + */ + uint16_t desc_hdl; + + /** + * @brief Characteristic Descriptor UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_char_desc_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_err_rsp_evt_t + * @brief This structure notifies that a Error Response PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The op code of the ATT Request that causes the Error Response. + * | op_code | + * |:--------------------------------------| + * | Exchange MTU Request(0x02) | + * | Find Information Request(0x04) | + * | Find By Type Value Request(0x06) | + * | Read By Type Request(0x08) | + * | Read Request(0x0A) | + * | Read Blob Request(0x0C) | + * | Read Multiple Request(0x0E) | + * | Read by Group Type Request(0x10) | + * | Write Request(0x12) | + * | Prepare Write Request(0x16) | + * | Execute Write Request(0x18) | + */ + uint8_t op_code; + + /** + * @brief Attribute handle that is target for the request. + */ + uint16_t attr_hdl; + + /** + * @brief The error codes notified from the GATT Server. + * @details It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined in + * Core Spec and Core Spec Supplement. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred, the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute. + *
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported. + *
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient. + *
0x3080 - 0x309F + * Application Error. + * The upper layer defines the error codes. + *
0x30E0 - 0x30FF + * The error code defined in Common Profile and + * Service Error Core Specification Supplement(CSS).
+ * CSS ver.7 defines the error codes from 0x30FC to 0x30FF. + *
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC) + * The Write Request has not been completed due to the reason other than Permission. + *
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.
+ */ + uint16_t rsp_code; +} st_ble_gattc_err_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ntf_evt_t + * @brief This structure notifies that a Notification PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Characteristic that causes the Notification. + */ + st_ble_gatt_hdl_value_pair_t data; +} st_ble_gattc_ntf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ind_evt_t + * @brief This structure notifies that a Indication PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Characteristic that causes the Indication. + */ + st_ble_gatt_hdl_value_pair_t data; +} st_ble_gattc_ind_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_char_evt_t + * @brief This structure notifies that read response to R_BLE_GATTC_ReadChar() or R_BLE_GATTC_ReadCharUsingUuid() + * has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The contents of the Characteristic that has been read. + */ + st_ble_gatt_hdl_value_pair_t read_data; +} st_ble_gattc_rd_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_wr_char_evt_t + * @brief This structure notifies that write response to R_BLE_GATTC_WriteChar() has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Value Handle of the Characteristic/Characteristic Descriptor that has been written. + */ + uint16_t value_hdl; +} st_ble_gattc_wr_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_multi_char_evt_t + * @brief This structure notifies that read response to R_BLE_GATTC_ReadMultiChar() has been received + * from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Value Handles of the Characteristics that has been read. + */ + uint16_t value_hdl_num; + + /** + * @brief The contents of multiple Characteristics that have been read. + */ + st_ble_gatt_value_t multi_char_val; +} st_ble_gattc_rd_multi_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_part_wr_evt_t + * @brief This structure notifies that write response to R_BLE_GATTC_WriteLongChar() or R_BLE_GATTC_ReliableWrites() + * has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The data to be written to the Characteristic/Long Characteristic/Long Characteristic Descriptor. + */ + st_ble_gatt_hdl_value_pair_t write_data; + + /** + * @brief Offset that indicates the location to be written. + */ + uint16_t offset; +} st_ble_gattc_char_part_wr_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_reliable_writes_comp_evt_t + * @brief This structure notifies that a response to R_BLE_GATTC_ExecWrite() has been received + * from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field indicates the command of the Execute Write that has been done. + * @details + * | value | description | + * |:-----------|:------------------- | + * | 0x00 | Cancel the write. | + * | 0x01 | Execute the write. | + */ + uint8_t exe_flag; +} st_ble_gattc_reliable_writes_comp_evt_t; + +/* RBLE GATT Client Command Parameters */ + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_multi_req_param_t + * @brief This is used in R_BLE_GATTC_ReadMultiChar() to specify multiple Characteristics to be read. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief List of Value Handles that point the Characteristics to be read. + */ + uint16_t * p_hdl_list; + + /** + * @brief The number of Value Handles included in the hdl_list parameter. + */ + uint16_t list_count; +} st_ble_gattc_rd_multi_req_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_evt_data_t + * @brief st_ble_gattc_evt_data_t is the type of the data notified in a GATT Client Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Server. + */ + uint16_t conn_hdl; + + /** + * @brief The size of GATT Client Event parameters. + */ + uint16_t param_len; + + /** + * @brief GATT Client Event parameters. This parameter differs in each GATT Client Event. + */ + void * p_param; +} st_ble_gattc_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_gattc_app_cb_t + * @brief ble_gattc_app_cb_t is the GATT Client Event callback function type. + * @param[in] event_type The type of GATT Client Event. + * @param[in] event_result The result of GATT Client Event + * @param[in] p_event_data Data notified by GATT Client Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gattc_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gattc_evt_data_t * p_event_data); + +/*@}*/ + +/* ============================================= L2CAP Type Definitions ============================================= */ + +/** @addtogroup L2CAP_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @struct st_ble_l2cap_conn_req_param_t + * @brief L2CAP CBFC Channel connection request parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on local device. + */ + uint16_t local_psm; + + /** + * @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on remote device. + */ + uint16_t remote_psm; + + /** + * @brief MTU size(byte) receivable on L2CAP CBFC Channel. + */ + uint16_t mtu; + + /** + * @brief MPS size(byte) receivable on L2CAP CBFC Channel. + */ + uint16_t mps; + + /** + * @brief The number of LE-Frame that local device can receive. + */ + uint16_t credit; +} st_ble_l2cap_conn_req_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_conn_rsp_param_t + * @brief L2CAP CBFC Channel connection response parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel on local device. + * The valid range is 0x40-0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1. + */ + uint16_t lcid; + + /** + * @brief The response to the connection request. Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_L2CAP_CF_RSP_SUCCESS(0x0000)Notify the remote device that the connection can be established.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH(0x0005)Notify the remote device that the connection can not be established + * because of insufficient authentication.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ(0x0006)Notify the remote device that the connection can not be established + * because of insufficient Authorization.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY(0x0007)Notify the remote device that the connection can not be established + * because of Encryption Key Size.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC(0x0008)Notify the remote device that the connection can not be established + * because of Encryption.
BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM(0x000B)Notify the remote device that the connection can not be established + * because the parameters is unacceptable to local device.
+ */ + uint16_t response; + + /** + * @brief MTU(byte) of packet that L2CAP CBFC Channel on local device can receive. + */ + uint16_t mtu; + + /** + * @brief MPS(byte) of packet that L2CAP CBFC Channel on local device can receive. + */ + uint16_t mps; + + /** + * @brief The number of LE-Frame that L2CAP CBFC Channel on local device can receive. + */ + uint16_t credit; +} st_ble_l2cap_conn_rsp_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_conn_evt_t + * @brief L2CAP CBFC Channel connection parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel. + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief MTU of local/remote device. + */ + uint16_t mtu; + + /** + * @brief MPS of local/remote device. + */ + uint16_t mps; + + /** + * @brief Credit of local/remote device. + */ + uint16_t credit; +} st_ble_l2cap_cf_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_data_evt_t + * @brief Sent/Received Data parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel that has sent or received the data . + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief Data length. + */ + uint16_t data_len; + + /** + * @brief Sent/Received data. + */ + uint8_t * p_data; +} st_ble_l2cap_cf_data_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_credit_evt_t + * @brief Credit parameters of local or remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel. + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief Current credit of local/remote device. + */ + uint16_t credit; +} st_ble_l2cap_cf_credit_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_disconn_evt_t + * @brief Disconnection parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel that has been disconnected. + */ + uint16_t cid; +} st_ble_l2cap_cf_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_rej_evt_t + * @brief Command Reject parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The reason that the remote device has sent Command Reject. + */ + uint16_t reason; + + /** + * @brief Optional information about the reason that the remote device has sent Command Reject. + */ + uint16_t data_1; + + /** + * @brief Optional information about the reason that the remote device has sent Command Reject. + */ + uint16_t data_2; +} st_ble_l2cap_rej_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_evt_data_t + * @brief st_ble_l2cap_cf_evt_data_t is the type of the data notified in a L2CAP Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device. + */ + uint16_t conn_hdl; + + /** + * @brief The size of L2CAP Event parameters. + */ + uint16_t param_len; + + /** + * @brief L2CAP Event parameters. This parameter differs in each L2CAP Event. + */ + void * p_param; +} st_ble_l2cap_cf_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_l2cap_cf_app_cb_t + * @brief ble_l2cap_cf_app_cb_t is the L2CAP Event callback function type. + * @param[in] event_type The type of L2CAP Event. + * @param[in] event_result The result of L2CAP Event + * @param[in] p_event_data Data notified by L2CAP Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_l2cap_cf_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_l2cap_cf_evt_data_t * p_event_data); + +/*@}*/ + +/* ================================================ L2CAP Event Code ================================================ */ + +/** @addtogroup L2CAP_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @enum e_r_ble_l2cap_cf_evt_t + * @brief L2CAP Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief After the connection request for L2CAP CBFC Channel has been sent with R_BLE_L2CAP_ReqCfConn(), + * when the L2CAP CBFC Channel connection response has been received, + * BLE_L2CAP_EVENT_CF_CONN_CNF event occurs. + * + * ## Event Code: 0x5001 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)L2CAP Command timeout.
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.
BLE_ERR_L2CAP_NO_RESOURCE(0x4004)No resource for connection.
BLE_ERR_L2CAP_INSUF_AUTHEN(0x4005)Insufficient authentication.
BLE_ERR_L2CAP_INSUF_AUTHOR(0x4006)Insufficient authorization.
BLE_ERR_L2CAP_INSUF_ENC_KEY_SIZE(0x4007)Insufficient encryption key size.
BLE_ERR_L2CAP_REFUSE_INSUF_ENC(0x4008)Insufficient encryption.
BLE_ERR_L2CAP_REFUSE_INVALID_SCID(0x4009) Invalid Source CID.
BLE_ERR_L2CAP_REFUSE_SCID_ALREADY_ALLOC(0x400A)Source CID already allocated.
BLE_ERR_L2CAP_REFUSE_UNACCEPTABLE_PARAM(0x400B)Unacceptable parameters.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_conn_evt_t + */ + BLE_L2CAP_EVENT_CF_CONN_CNF = 0x5001, + + /** + * @brief When a connection request for L2CPA CBFC Channel has been received from a remote device, + * BLE_L2CAP_EVENT_CF_CONN_IND event occurs. + * + * ## Event Code: 0x5002 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_NOT_FOUND(0x000D)CF connection request has not been received or lcid not found.
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_conn_evt_t + */ + BLE_L2CAP_EVENT_CF_CONN_IND = 0x5002, + + /** + * @brief After local device has sent a disconnection request for L2CAP CBFC Channel by + * R_BLE_L2CAP_DisconnectCf(), when the local device has received the response, + * BLE_L2CAP_EVENT_CF_DISCONN_CNF event occurs. + * + * ## Event Code: 0x5003 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_disconn_evt_t + */ + BLE_L2CAP_EVENT_CF_DISCONN_CNF = 0x5003, + + /** + * @brief When local device has received a disconnection request for L2CAP CBFC Channel from the remote device, + * BLE_L2CAP_EVENT_CF_DISCONN_IND event occurs.\n + * Host stack automatically replies the to the disconnection request. + * + * ## Event Code: 0x5004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_disconn_evt_t + */ + BLE_L2CAP_EVENT_CF_DISCONN_IND = 0x5004, + + /** + * @brief When local device has received data on L2CAP CBFC Channel, BLE_L2CAP_EVENT_CF_RX_DATA_IND event occurs. + * + * ## Event Code: 0x5005 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_data_evt_t + */ + BLE_L2CAP_EVENT_CF_RX_DATA_IND = 0x5005, + + /** + * @brief When the credit of the L2CAP CBFC Channel has reached the Low Water Mark, + * BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event occurs. + * + * ## Event Code: 0x5006 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_credit_evt_t + */ + BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND = 0x5006, + + /** + * @brief When local device has received credit from a remote device, BLE_L2CAP_EVENT_CF_TX_CRD_IND event occurs. + * + * ## Event Code: 0x5007 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_credit_evt_t + */ + BLE_L2CAP_EVENT_CF_TX_CRD_IND = 0x5007, + + /** + * @brief When the data transmission has been completed from host stack to Controller, + * BLE_L2CAP_EVENT_CF_TX_DATA_CNF event occurs. + * + * ## Event Code: 0x5008 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_DISCONNECTED(0x000F) While transmitting data, L2CAP CBFC Channel has been disconnected.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_data_evt_t + */ + BLE_L2CAP_EVENT_CF_TX_DATA_CNF = 0x5008, + + /** + * @brief When local device has received Command Reject PDU, BLE_L2CAP_EVENT_CMD_REJ event occurs. + * + * ## Event Code: 0x5009 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_rej_evt_t + */ + BLE_L2CAP_EVENT_CMD_REJ = 0x5009 +} e_r_ble_l2cap_cf_evt_t; + +/*@}*/ + +/* ======================================== Vendor Specific Type Definitions ======================================== */ + +/** @addtogroup VS_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @struct st_ble_vs_tx_test_param_t + * @brief This is the extended transmitter test parameters used in R_BLE_VS_StartTxTest(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Channel used in Tx test. + */ + uint8_t ch; + + /** + * @brief Length(in bytes) of the packet used in Tx Test. + */ + uint8_t test_data_len; + + /** + * @brief Packet Payload. + */ + uint8_t packet_payload; + + /** + * @brief Transmitter PHY used in test. + */ + uint8_t phy; + + /** + * @brief Tx Power Level used in DTM Tx Test. + */ + uint8_t tx_power; + + /** + * @brief Option. + */ + uint8_t option; + + /** + * @brief The number of packet to be sent. + */ + uint16_t num_of_packet; +} st_ble_vs_tx_test_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_rx_test_param_t + * @brief This is the extended receiver test parameters used in R_BLE_VS_StartRxTest(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Channel used in Rx test. + */ + uint8_t ch; + + /** + * @brief Receiver PHY used in the test. + */ + uint8_t phy; +} st_ble_vs_rx_test_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_rf_ctrl_param_t + * @brief This is the RF parameters used in R_BLE_VS_SetRfControl(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief RF power on/off. + */ + uint8_t power; + + /** + * @brief This field indicates whether the parameters change in RF power on. + */ + uint8_t option; + + /** + * @brief RF rapid clock frequency adjust value(OSC internal CL adjust). + */ + uint8_t clval; + + /** + * @brief RF slow clock configurations. + */ + uint8_t slow_clock; + + /** + * @brief Set tx power in power on. + */ + uint8_t tx_power; + + /** + * @brief Set RF option. + */ + uint8_t rf_option; +} st_ble_vs_set_rf_ctrl_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_test_end_evt_t + * @brief This structure notifies that the extended test has been terminated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of packet successfully received in the receiver test. + */ + uint16_t num_of_packet; + + /** + * @brief The number of CRC error packets in the receiver test. + */ + uint16_t num_of_crc_err_packet; + + /** + * @brief Average RSSI(dBm) in the receiver test. + */ + int8_t ave_rssi; + + /** + * @brief Maximum RSSI(dBm) in the receiver test. + */ + int8_t max_rssi; + + /** + * @brief Minimum RSSI(dBm) in the receiver test. + */ + int8_t min_rssi; +} st_ble_vs_test_end_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_tx_pwr_comp_evt_t + * @brief This structure notifies that tx power has been set. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle that identifying the link whose tx power has been set. + */ + uint16_t conn_hdl; + + /** + * @brief Tx power that has been set(dBm). + */ + int8_t curr_tx_pwr; +} st_ble_vs_set_tx_pwr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_tx_pwr_comp_evt_t + * @brief This structure notifies that tx power has been retrieved. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle that identifying the link whose tx power has been retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Current tx power(dBm). + */ + int8_t curr_tx_pwr; + + /** + * @brief Maximum tx power(dBm). + */ + int8_t max_tx_pwr; +} st_ble_vs_get_tx_pwr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_rf_ctrl_comp_evt_t + * @brief This structure notifies that RF has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The result of RF power control. + */ + uint8_t ctrl; +} st_ble_vs_set_rf_ctrl_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_bd_addr_comp_evt_t + * @brief This structure notifies that BD_ADDR has been retrieved. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The area that public/random address has been retrieved. + * | value | description | + * |:------------------------------------|:------------------- | + * | BLE_VS_ADDR_AREA_REG(0x00) | Register. | + * | BLE_VS_ADDR_AREA_DATA_FLASH(0x01) | Data Flash. | + */ + uint8_t area; + + /** + * @brief The address that has been retrieved. + */ + st_ble_dev_addr_t addr; +} st_ble_vs_get_bd_addr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_rand_comp_evt_t + * @brief This structure notifies that random number has been generated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Length of random number. + */ + uint8_t rand_size; + + /** + * @brief Random number. + */ + uint8_t * p_rand; +} st_ble_vs_get_rand_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_tx_flow_chg_evt_t + * @brief This structure notifies that the state transition of TxFlow has been changed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The state of the flow control. + * | value | description | + * |:---------------------------- |:-------------------------------------------------------------------------- | + * | BLE_VS_TX_FLOW_CTL_ON(0x00) | The number of buffer has reached the High Water Mark from flow off state. | + * | BLE_VS_TX_FLOW_CTL_OFF(0x01) | The number of buffer has reached the Low Water Mark from flow on state. | + */ + uint8_t state; + + /** + * @brief The number of the current transmission buffers. + */ + uint32_t buffer_num; +} st_ble_vs_tx_flow_chg_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_evt_data_t + * @brief st_ble_vs_evt_data_t is the type of the data notified in a Vendor Specific Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The size of Vendor Specific Event parameters. + */ + uint16_t param_len; + + /** + * @brief Vendor Specific Event parameters. This parameter differs in each Vendor Specific Event. + */ + void * p_param; +} st_ble_vs_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_vs_app_cb_t + * @brief ble_vs_app_cb_t is the Vendor Specific Event callback function type. + * @param[in] event_type The type of Vendor Specific Event. + * @param[in] event_result The result of API call which generates the Vendor Specific Event. + * @param[in] p_event_data Data notified in the Vendor Specific Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_vs_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_vs_evt_data_t * p_event_data); + +/*@}*/ + +/* =========================================== Vendor Specific Event Code =========================================== */ + +/** @addtogroup VS_API + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @enum e_r_ble_vs_evt_t + * @brief Vendor Specific Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief This event notifies that the tx power has been set by R_BLE_VS_SetTxPower(). + * + * ## Event Code: 0x8001 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The tx_power parameter specified by R_BLE_VS_SetTxPower() is out of range.
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_SetTxPower() is not found.
+ *
+ * + * ## Event Data: + * st_ble_vs_set_tx_pwr_comp_evt_t + */ + BLE_VS_EVENT_SET_TX_POWER = 0x8001, + + /** + * @brief This event notifies that the tx power has been retrieved by R_BLE_VS_GetTxPower(). + * + * ## Event Code: 0x8002 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_GetTxPower() is not found.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_tx_pwr_comp_evt_t + */ + BLE_VS_EVENT_GET_TX_POWER = 0x8002, + + /** + * @brief This event notifies that the extended transmitter test has been started by R_BLE_VS_StartTxTest(). + * + * ## Event Code: 0x8003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartTxTest() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_TX_TEST_START = 0x8003, + + /** + * @brief This event notifies that the number specified by R_BLE_VS_StartTxTest() of packets has been sent. + * + * ## Event Code: 0x8004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_TX_TEST_TERM = 0x8004, + + /** + * @brief This event notifies that the extended receiver test has been started by R_BLE_VS_StartRxTest(). + * + * ## Event Code: 0x8005 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartRxTest() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_RX_TEST_START = 0x8005, + + /** + * @brief This event notifies that the extended test has been terminated by R_BLE_VS_EndTest(). + * + * ## Event Code: 0x8006 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_test_end_evt_t + */ + BLE_VS_EVENT_TEST_END = 0x8006, + + /** + * @brief This event notifies that the coding scheme has been configured by R_BLE_VS_SetCodingScheme(). + * + * ## Event Code: 0x8007 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The coding_scheme parameter specified by R_BLE_VS_SetCodingScheme() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_CODING_SCHEME_COMP = 0x8007, + + /** + * @brief This event notifies that the RF has been configured by R_BLE_VS_SetRfControl(). + * + * ## Event Code: 0x8008 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_SetRfControl() is out of range.
BLE_ERR_INVALID_OPERATION(0x0009)During the power on or the power off, the same power state is specified + * by R_BLE_VS_SetRfControl().
+ *
+ * + * ## Event Data: + * st_ble_vs_set_rf_ctrl_comp_evt_t + */ + BLE_VS_EVENT_RF_CONTROL_COMP = 0x8008, + + /** + * @brief This event notifies that public/random address has been set by R_BLE_VS_SetBdAddr(). + * + * ## Event Code: 0x8009 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified + * by R_BLE_VS_SetBdAddr() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_ADDR_COMP = 0x8009, + + /** + * @brief This event notifies that public/random address has been retrieved by R_BLE_VS_GetBdAddr(). + * + * ## Event Code: 0x800A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified + * by R_BLE_VS_GetBdAddr() is out of range.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_bd_addr_comp_evt_t + */ + BLE_VS_EVENT_GET_ADDR_COMP = 0x800A, + + /** + * @brief This event notifies the application layer that random number has been generated by R_BLE_VS_GetRand(). + * + * ## Event Code: 0x800B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The rand_size parameter specified by R_BLE_VS_GetRand() is out of range.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_rand_comp_evt_t + */ + BLE_VS_EVENT_GET_RAND = 0x800B, + + /** + * @brief This event notifies the application layer of the state transition of TxFlow. + * + * ## Event Code: 0x800C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_tx_flow_chg_evt_t + */ + BLE_VS_EVENT_TX_FLOW_STATE_CHG = 0x800C, + + /** + * @brief This event notifies a failure occurs in RF. After receiving the event, reset MCU or RF. + * + * ## Event Code: 0x800D + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * None + */ + BLE_VS_EVENT_FAIL_DETECT = 0x800D, + + /** + * @brief Invalid VS Event. + * + * ## Event Code: 0x80FF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_INVALID = 0x80FF +} e_r_ble_vs_evt_t; + +/*@}*/ + +/* ============================================= APP Callback Definition ============================================ */ + +typedef void (* ble_app_init_cb_t)(uint8_t param); + +/* ============================================ Event Callback Definition =========================================== */ + +/******************************************************************************************************************//** + * @ingroup BLE + * @typedef ble_event_cb_t + * @brief ble_event_cb_t is the callback function type for R_BLE_SetEvent(). + * @param[in] void + * @return none + **********************************************************************************************************************/ +typedef void (* ble_event_cb_t)(void); + +/* ============================================== MAIN API Declarations ============================================== */ + +/** @addtogroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Open(void) + * @brief Open the BLE protocol stack. + * @details This function should be called once before using the BLE protocol stack. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Open(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Close(void) + * @brief Close the BLE protocol stack. + * @details This function should be called once to close the BLE protocol stack. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Close(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Execute(void) + * @brief Execute the BLE task. + * @details This handles all the task queued in the BLE protocol stack internal task queue and return. + * This function should be called repeatedly in the main loop. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Execute(void); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_IsTaskFree(void) + * @brief Check the BLE task queue is free or not. + * @details This function returns the BLE task queue free status. + * When this function returns 0x0, call R_BLE_Execute() to execute the BLE task. + * @retval 0x0 BLE task queue is not free + * @retval 0x1 BLE task queue is free + **********************************************************************************************************************/ +uint32_t R_BLE_IsTaskFree(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_SetEvent(ble_event_cb_t cb) + * @brief Set event. + * @details This function add an event in the BLE protocol stack internal queue. The event is handled in R_BLE_Execute + * just like Bluetooth event. This function is intended to be called in hardware interrupt context. + * Even if calling this function with the same cb before the cb is invoked, only one event is registered. + * The maximum number of the events can be registered at a time is eight. + * @param cb The callback for the event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) The event already registered with the callback. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) No free slot for the event. + **********************************************************************************************************************/ +ble_status_t R_BLE_SetEvent(ble_event_cb_t cb); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_GetVersion(void) + * @brief Get the BLE FIT module version. + * @details This function returns the BLE FIT module version. \n + * The major version(BLE_VERSION_MAJOR) is contained in the two most significant bytes, + * and the minor version(BLE_VERSION_MINOR) occupies the remaining two bytes. + * @retval "BLE_VERSION_MAJOR | BLE_VERSION_MINOR" + **********************************************************************************************************************/ +uint32_t R_BLE_GetVersion(void); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_GetLibType(void) + * @brief Get the type of BLE protocol stack library. + * @details This function returns the type of BLE protocol stack library. + * @retval BLE_LIB_ALL_FEATS(0x00) All Features + * @retval BLE_LIB_BALANCE(0x01) Balance + * @retval BLE_LIB_COMPACT(0x02) Compact + **********************************************************************************************************************/ +uint32_t R_BLE_GetLibType(void); + +/*@}*/ + +/* ============================================== GAP API Declarations ============================================== */ + +/** @defgroup GAP_API GAP + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GAP_API + * @fn ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb) + * @brief Initialize the Host Stack. + * @details Host stack is initialized with this function. Before using All the R_BLE APIs, + * it's necessary to call this function. A callback function is registered with this function. + * In order to receive the GAP event, it's necessary to register a callback function. + * The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event. + * @param[in] gap_cb A callback function registered with this function. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) gap_cb is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - Host Stack was already initialized. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_Terminate(void) + * @brief Terminate the Host Stack. + * @details Host stack is terminated with this function. + * In order to reset all the Bluetooth functions, it's necessary to call this function. + * The result of this API call is notified in BLE_GAP_EVENT_STACK_OFF event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) Host stack hasn't been initialized. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Terminate(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_UpdConn(uint16_t conn_hdl, + * uint8_t mode, + * uint16_t accept, + * st_ble_gap_conn_param_t * p_conn_updt_param + * ) + * @brief Update the connection parameters. + * @details This function updates the connection parameters or replies a request for + * updating connection parameters notified by BLE_GAP_EVENT_CONN_PARAM_UPD_REQ event. + * When the connection parameters has been updated, + * BLE_GAP_EVENT_CONN_PARAM_UPD_COMP event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link to be updated. + * @param[in] mode Connection parameter update request or response. + * | macro | description | + * |:-------------------------------------- |:---------------------------------------------------- | + * | BLE_GAP_CONN_UPD_MODE_REQ (0x01) | Request for updating the connection parameters. | + * | BLE_GAP_CONN_UPD_MODE_RSP (0x02) | Reply a connection parameter update request. | + * + * @param[in] accept When mode is BLE_GAP_CONN_UPD_MODE_RSP, + * accept or reject the connection parameters update request. + * If mode is BLE_GAP_CONN_UPD_MODE_REQ, accept is ignored. + * | macro | description | + * |:-------------------------------------- |:--------------------------------- | + * | BLE_GAP_CONN_UPD_ACCEPT (0x0000) | Accept the update request. | + * | BLE_GAP_CONN_UPD_REJECT (0x0001) | Reject the update request. | + * + * @param[in] p_conn_updt_param Connection parameters to be updated. + * When mode is BLE_GAP_CONN_UPD_MODE_RSP and + * accept is BLE_GAP_CONN_UPD_REJECT, p_conn_updt_param is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When accept is BLE_GAP_CONN_UPD_ACCEPT, + * p_conn_updt_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following is out of range. + * - mode + * - accept + * - conn_intv_min field in p_conn_updt_param + * - conn_intv_max field in p_conn_updt_param + * - conn_latency in p_conn_updt_param + * - sup_to in p_conn_updt_param + * - conn_hdl + * @retval BLE_ERR_INVALID_STATE(0x0008) Not connected with the remote device. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Sending a L2CAP command, an error occurred. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_UpdConn(uint16_t conn_hdl, + uint8_t mode, + uint16_t accept, + st_ble_gap_conn_param_t * p_conn_updt_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time) + * @brief Update the packet size and the packet transmit time. + * @details This function requests for changing the maximum transmission packet size + * and the maximum packet transmission time. + * When Controller has received the request from host stack, + * BLE_GAP_EVENT_SET_DATA_LEN_COMP event is notified to the application layer. + * When the transmission packet size or the transmission time has been changed, + * BLE_GAP_EVENT_DATA_LEN_CHG event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link whose the transmission packet size or + * the transmission time to be changed. + * @param[in] tx_octets Maximum transmission packet size. + * Valid range is 0x001B - 0x00FB. + * @param[in] tx_time Maximum transmission time(us). + * Valid range is 0x0148 - 0x4290. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason) + * @brief Disconnect the link. + * @details This function disconnects a link. + * When the link has disconnected, BLE_GAP_EVENT_DISCONN_IND event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link to be disconnected. + * @param[in] reason The reason for disconnection. + * Usually, set 0x13 which indicates that a user disconnects the link. + * If setting other than 0x13, refer the error code described + * in Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param) + * @brief Set the phy for connection. + * @details This function sets the PHY preferences for the connection. + * The result of this API call is notified in BLE_GAP_EVENT_PHY_SET_COMP event. + * When the PHY has been updated, BLE_GAP_EVENT_PHY_UPD event is notified to the application layer. + * + * After PHY update, the PHY accept configuration of local device is the same as the values + * in BLE_GAP_EVENT_PHY_UPD event. \n + * For example, after calling R_BLE_GAP_SetPhy(), if tx_phy, + * rx_phy by BLE_GAP_EVENT_PHY_UPD event are updated to 2M PHY, + * the PHY accept configuration is 2M PHY only. \n + * Therefore after receiving BLE_GAP_EVENT_PHY_UPD event, if local device wants to accept the other PHY + * configuration, it needs to call R_BLE_GAP_SetPhy() with the desired PHY accept configuration. + * + * Because the maximum transmission packet size or the maximum transmission time might be updated by + * PHY update, if the same packet size or transmission time as the previous one is desired, + * change the maximum transmission packet size or the maximum transmission time by @ref R_BLE_GAP_SetDataLen(). + * + * @param[in] conn_hdl Connection handle identifying the link whose PHY to be updated. + * @param[in] p_phy_param PHY preferences. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_phy_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl or option field in p_phy_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param) + * @brief Set the default phy which allows remote device to change. + * @details This function sets the PHY preferences which a remote device may change. + * The result of this API call is notified in BLE_GAP_EVENT_DEF_PHY_SET_COMP event. + * @param[in] p_def_phy_param The PHY preference which a remote device may change. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_def_phy_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) tx_phys or tx_phys field in p_def_phy_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr, + * uint8_t * p_privacy_mode, + * uint8_t device_num + * ) + * @brief Set the privacy mode. + * @details This function sets privacy mode for the remote device registered in Resolving List. + * By default, Network Privacy Mode is set.\n + * The result of this API call is notified in BLE_GAP_EVENT_PRIV_MODE_SET_COMP event. + * @param[in] p_addr An array of identity address of the remote device to set privacy mode. + * The number of elements is specified by device_num.\n\n + * @param[in] p_privacy_mode An array of privacy mode to set to remote device. + * The number of elements is specified by device_num.\n + * The following value is set as the privacy mode. + * | macro | description | + * |:-------------------------------------- |:--------------------------------- | + * | BLE_GAP_NET_PRIV_MODE (0x00) | Network Privacy Mode. | + * | BLE_GAP_DEV_PRIV_MODE (0x01) | Device Privacy Mode. | + * @param[in] device_num The number of devices to set privacy mode. + * Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr or p_privacy_mode is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range. + * - The address type in p_addr. + * - The privacy mode specified by p_privacy_mode. + * - device_num + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While configuring privacy mode, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr, uint8_t * p_privacy_mode, uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num) + * @brief Set White List. + * @details This function supports the following operations regarding White List. + * - Add the device to White List. + * - Delete the device from White List. + * - Clear White List. + * + * The total number of White List entries is defined as BLE_GAP_WHITE_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_WHITE_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for White List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of device address to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_WHITE_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV, + * p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating White List, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the White List. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetVerInfo(void) + * @brief Get the version number of the Controller and the host stack. + * @details This function retrieves the version information of local device. + * The result of this API call is notified in BLE_GAP_EVENT_LOC_VER_INFO event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetVerInfo(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl) + * @brief Get the phy settings. + * @details This function gets the PHY settings for the connection. + * The result of this API call is notified in BLE_GAP_EVENT_PHY_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose PHY settings to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfRslvList(uint8_t op_code, + * st_ble_dev_addr_t * p_addr, + * st_ble_gap_rslv_list_key_set_t * p_peer_irk, + * uint8_t device_num + * ) + * @brief Set Resolving List. + * @details This function supports the following operations regarding Resolving List. + * - Add the device to Resolving List. + * - Delete the device from Resolving List. + * - Clear Resolving List. + * + * In order to generate a resolvable private address, + * a local IRK needs to be registered by R_BLE_GAP_SetLocIdInfo(). + * If communicating with the identity address, register all-zero IRK as local IRK. + * In order to resolve resolvable private address of the remote device, + * the IRK distributed from the remote device needs to be added to Resolving List. + * The total number of Resolving List entries is defined as BLE_GAP_RESOLV_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_RSLV_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for Resolving List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of Identity Addresses to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] p_peer_irk The remote IRK and the type of local IRK added to Resolving List. + * If op_code is other than BLE_GAP_LIST_ADD_DEV, p_peer_irk is ignored. + * The number of elements is specified by device_num. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - When added to or deleted from the list, p_addr is specified as NULL. + * - When added to the list, p_peer_irk is specified as NULL. + * + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - op_code is out of range. + * - When op_code is BLE_GAP_LIST_ADD_DEV or + * BLE_GAP_LIST_REM_DEV, device_num is out of range. + * - When op_code is BLE_GAP_LIST_ADD_DEV or + * BLE_GAP_LIST_REM_DEV, address type field in p_addr is out of range. + * + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating Resolving List, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the Resolving List. + * @retval BLE_ERR_INVALID_HDL(0x000E) The specified Identity Address was not found in Resolving List. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfRslvList(uint8_t op_code, + st_ble_dev_addr_t * p_addr, + st_ble_gap_rslv_list_key_set_t * p_peer_irk, + uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable) + * @brief Enable/Disable address resolution and generation of a resolvable private address. + * @details This function enables or disables RPA functionality. The RPA functionality includes the following. + * - Generation of local resolvable private address + * - Resolution of remote resolvable private address + * + * In order to do advertising, scanning or creating a link with local resolvable private address, + * the RPA functionality needs to be enabled. + * After enabling the RPA functionality and the identity address of remote device and + * the IRKs of local/remote device is registered, + * local device can generate own resolvable private address in the time interval set by R_BLE_GAP_SetRpaTo(), + * and can resolve a resolvable private address of a remote device. + * It is recommended that the RPA functionality is called immediately + * after the initialization by R_BLE_GAP_Init(). + * The result of this API call is notified in BLE_GAP_EVENT_RPA_EN_COMP event. + * @param[in] enable Enable or disable address resolution function. + * | macro | description | + * |:------------------------------- |:----------------------------------------- | + * | BLE_GAP_RPA_DISABLED(0x00) | Disable RPA generation/resolution. | + * | BLE_GAP_RPA_ENABLED(0x01) | Enable RPA generation/resolution. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) enable is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout) + * @brief Set the update time of resolvable private address. + * @details This function sets the time interval to update the resolvable private address. + * The result of this API call is notified in BLE_GAP_EVENT_SET_RPA_TO_COMP event. + * @param[in] rpa_timeout Time interval to update resolvable private address in seconds. + * Valid range is 0x003C - 0xA1B8. + * Default is 900s. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr) + * @brief Get the resolvable private address of local device. + * @details This function retrieves the local resolvable private address. + * Before getting the address, enable the resolvable private address function by R_BLE_GAP_EnableRpa(). + * The result of this API call is notified in BLE_GAP_EVENT_RD_RPA_COMP event. + * @param[in] p_addr Identity address registered in Resolving List. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) Address type in p_addr is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows. + * - When retrieving the local resolvable private address, + * this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl) + * @brief Get RSSI. + * @details This function retrieves RSSI. + * The result of this API call is notified in BLE_GAP_EVENT_RSSI_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose RSSI to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl) + * @brief Get the Channel Map. + * @details This function retrieves the channel map. + * The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose channel map to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr) + * @brief Set a random address. + * @details This function sets static address or non-resolvable private address to Controller. + * Refer to Core Specification Vol 6, PartB, + * "1.3.2 Random Device Address" regarding the format of the random address. + * Resolvable private address cannot set by this API. + * The result of this API call is notified in BLE_GAP_EVENT_RAND_ADDR_SET_COMP event. + * @param[in] p_random_addr Static address or non-resolvable private address. \n + * The BD address setting format is little endian. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_random_addr is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param) + * @brief Set advertising parameters. + * @details This function sets advertising parameters. + * It's possible to do advertising where the advertising parameters are different every each advertising set. + * The number of advertising set in the Controller is defined as BLE_MAX_NO_OF_ADV_SETS_SUPPORTED. + * Each advertising set is identified with advertising handle (0x00-0x03). + * Create an advertising set with this function before start advertising, + * setting periodic advertising parameters, start periodic advertising, + * setting advertising data/scan response data/periodic advertising data. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_PARAM_SET_COMP event. + * @param[in] p_adv_param Advertising parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_adv_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The below p_adv_param field value is out of range. + * - adv_handle + * - adv_intv_min/adv_intv_max + * - adv_ch_map + * - o_addr_type + * - p_addr_type + * - adv_phy + * - sec_adv_phy + * - scan_req_ntf_flag + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data) + * @brief Set advertising data/scan response data/periodic advertising data. + * @details This function sets advertising data/scan response data/periodic advertising data to the advertising set. + * It is necessary to create an advertising set by R_BLE_GAP_SetAdvParam(), before calling this function. + * Set advertising data/scan response data/periodic advertising data, after allocating the memory for the data. + * The following shall be applied regarding the adv_prop_type field and the data_type field in + * st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam(). + * + * The following shall be applied regarding the adv_prop_type field and the data_type field in + * st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam(). + * - When adv_prop_type is Legacy Advertising PDU type, + * - it's possible to set advertising data/scan response data up to 31 bytes. + * - advertising data/scan response data can be updated by this function in advertising. + * - When adv_prop_type is Extended Advertising PDU type, + * - it's possible to set at most 1650 bytes of data as advertising data/scan response data + * per 1 advertising set. + * - the total buffer size in Controller for advertising data/scan response data is 4250 bytes. + * Therefore please note that more than 4250 bytes of advertising data/scan response data + * can not be set to all the advertising sets. + * Please refer to Figure 1.1 and Figure 1.2 about examples of setting advertising data/scan response data. + * - it's possible to update advertising data/scan response data in advertising, + * if the data_length field in st_ble_gap_adv_data_t parameter is up to 251 bytes. + * @image html "adv_data_alloc_fail_en.svg" "Figure 1.1" width=700px + * @image html "adv_data_alloc_success_en.svg" "Figure 1.2" width=700px + * - When periodic advertising data is set, + * - At most 1650 bytes of data can be set to 1 advertising set. + * - The total buffer size in Controller for periodic advertising data is 4306 bytes. + * Therefore please note that more than 4306 bytes of periodic advertising data can not be + * set to all the advertising sets. + * - it's possible to update periodic advertising data in advertising, + * if the data_length field in st_ble_gap_adv_data_t parameter is up to 252 bytes. + * + * The result of this API call is notified in @ref BLE_GAP_EVENT_ADV_DATA_UPD_COMP event. + * + * @param[in] p_adv_srsp_data Advertising data/scan response data/periodic advertising data. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_adv_srsp_data is specified as NULL. + * - data_length field in p_adv_srsp_data parameter is not 0 and p_data field is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in p_adv_srsp_data parameter is out of range. + * - adv_hdl + * - data_type + * - data_length + * - zero_length_flag + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts) + * @brief Start advertising. + * @details This function starts advertising. + * Create the advertising set specified with adv_hdl by R_BLE_GAP_SetAdvParam(), + * before calling this function. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_ON event. + * @param[in] adv_hdl + * The advertising handle pointing to the advertising set which starts advertising. + * The valid range is 0x00 - 0x03. + * @param[in] duration + * The duration for which the advertising set identified by adv_hdl is enabled. + * Time = duration * 10ms. + * When the duration expires, BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped. + * The valid range is 0x0000 - 0xFFFF. + * The duration parameter is ignored when the value is set to 0x0000. + * @param[in] max_extd_adv_evts + * The maximum number of advertising events that be sent during advertising. + * When all the advertising events(max_extd_adv_evts) have been sent, + * BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped. + * The max_extd_adv_evts parameter is ignored when the value is set to 0x00. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl) + * @brief Stop advertising. + * @details This function stops advertising. The result of this API call is notified in BLE_GAP_EVENT_ADV_OFF event. + * @param[in] adv_hdl + * The advertising handle pointing to the advertising set which stops advertising. + * The valid range is 0x00 - 0x03. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param) + * @brief Set periodic advertising parameters. + * @details This function sets periodic advertising parameters. + * Create the advertising set which supports Non-Connectable, + * Non-Scannable advertising by R_BLE_GAP_SetAdvParam() before setting periodic advertising parameters. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP event. + * @param[in] p_perd_adv_param Periodic advertising parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_perd_adv_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in the p_perd_adv_param parameter is out of range. + * - adv_hdl + * - perd_intv_min or perd_intv_max + * - prop_type is neither 0x0000 nor 0x0040(BLE_GAP_PERD_PROP_TX_POWER) + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl) + * @brief Start periodic advertising. + * @details This function starts periodic advertising. + * Set periodic advertising parameters to the advertising set, before starting periodic advertising. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_ON event. + * @param[in] adv_hdl Advertising handle identifying the advertising set which starts periodic advertising. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl) + * @brief Stop periodic advertising. + * @details This function stops periodic advertising. + * If the return value of this API is BLE_SUCCESS, the result is notified in BLE_GAP_EVENT_PERD_ADV_OFF event. + * @param[in] adv_hdl Specify the handle of Advertising Set to stop Periodic Advertising. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size, + * uint16_t * p_remain_perd_adv_data_size + * ) + * @brief Get buffer size for advertising data/scan response data/periodic advertising data in the Controller. + * @details This function gets the total size of advertising data/scan response data/periodic advertising data + * which can be currently set to Controller(all of the advertising sets). + * The application layer gets the data sizes via the parameters. + * By this API function call, no events occur. + * @param[out] p_remain_adv_data_size + * The free buffer size of Controller to which advertising data/scan response data can be currently set. + * @param[out] p_remain_perd_adv_data_size + * The free buffer size of Controller to which periodic advertising data can be currently set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_remain_adv_data_size or p_remain_perd_adv_data_size is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size, uint16_t * p_remain_perd_adv_data_size); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl) + * @brief Delete advertising set. + * @details This function deletes an advertising set or deletes all the advertising sets. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_SET_REMOVE_COMP event. + * @param[in] op_code The operation for delete or clear. + * | macro | description | + * |:-------------------------------- |:-------------------------------- | + * | BLE_GAP_RMV_ADV_SET_REM_OP(0x01) | Delete an advertising set. | + * | BLE_GAP_RMV_ADV_SET_CLR_OP(0x02) | Delete all the advertising sets. | + * @param[in] adv_hdl + * Advertising handle identifying the advertising set deleted. + * If op_code is BLE_GAP_RMV_ADV_SET_CLR_OP, adv_hdl is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - op_code is out of range. + * - When op_code is BLE_GAP_RMV_ADV_SET_REM_OP(0x01), adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param) + * @brief Request for a link establishment. + * @details This function sends a connection request to a remote device to create a link. + * When Controller has received a request for establishment of a link from host stack, + * BLE_GAP_EVENT_CREATE_CONN_COMP event is notified to the application layer. + * When the link is established, BLE_GAP_EVENT_CONN_IND event is notified to the application layer. + * @param[in] p_param Connection parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_param is specified as NULL. + * - p_conn_param_1M field and p_conn_param_2M and + * p_conn_param_coded field in p_param are specified as NULL. + * - When creating a link with 1M PHY, p_conn_param + * in p_conn_param_1M field in p_param is specified as NULL. + * - When creating a link with 2M PHY, + * p_conn_param in p_conn_param_2M field in p_param is specified as NULL. + * - When creating a link with coded MPHY, + * p_conn_param in p_conn_param_coded field in p_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - init_filter_policy in p_param is out of range. + * - remote_bd_addr_type field or own_addr_type address field + * in p_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CancelCreateConn(void) + * @brief Cancel the request for a link establishment. + * @details This function cancels a request for establishing a link. + * When Controller has received the cancel request from host stack, + * BLE_GAP_EVENT_CONN_CANCEL_COMP event is notified to the application layer. + * When the cancel procedure has completed, + * BLE_GAP_EVENT_CONN_IND event is notified to the application layer. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CancelCreateConn(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map) + * @brief Set the Channel Map. + * @details This function sets the channel map. + * The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_SET_COMP event. + * @param[in] p_channel_map Channel map. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_channel_map is specified as NULL. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param, + * st_ble_gap_scan_on_t * p_scan_enable + * ) + * @brief Set scan parameter and start scan. + * @details This function starts scanning. + * When scanning for the first time, set the p_scan_param. + * Setting scan parameters can be omitted by specifying p_scan_param as NULL after next time. + * The result of this API call is notified in BLE_GAP_EVENT_SCAN_ON event. + * Advertising report is notified in BLE_GAP_EVENT_ADV_REPT_IND event. + * Figure 1.3 shows the relationship between scan period, scan duration, scan interval and scan window. + * @image html "scan_period_en.svg" "Figure 1.3" + * + * When scan duration is non-zero, scan period is zero and scan duration expires, + * BLE_GAP_EVENT_SCAN_TO event is notified to the application layer. + * @param[in] p_scan_param + * Scan parameter. + * When p_scan_param is specified as NULL, + * host stack doesn't set scan parameters and start scanning with the previous parameters. + * @param[in] p_scan_enable + * Scan period, scan duration, duplicate filter and procedure type. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_scan_enable is specified as NULL. + * - p_phy_param_1M field and p_phy_param_coded field in + * p_scan_param are specified as NULL. + * + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - proc_type field in p_scan_enable is out of range. + * - filter_dups in p_scan_enable is out of range. + * - o_addr_type in p_scan_param is out of range. + * - filter_policy in p_scan_param is out of range. + * - scan_type of p_scan_param's p_phy_param_1M or p_phy_param_coded is out of range. + * + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param, st_ble_gap_scan_on_t * p_scan_enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopScan(void) + * @brief Stop scan. + * @details This function stops scanning. + * The result of this API call is notified in BLE_GAP_EVENT_SCAN_OFF event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopScan(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr, + * uint8_t adv_sid, + * uint16_t skip, + * uint16_t sync_to + * ) + * @brief Request for a periodic sync establishment. + * @details This function sends a request for establishment of a periodic sync to a advertiser. + * In order to create a periodic sync, scan needs to be starting by R_BLE_GAP_StartScan(). + * When Controller has received the request from host stack, + * BLE_GAP_EVENT_CREATE_SYNC_COMP event is notified to the application layer. + * When the periodic sync is established, BLE_GAP_EVENT_SYNC_EST event is notified to the application layer. + * @param[in] p_addr + * The address of periodic advertiser.When p_addr is specified as NULL, + * local device creates a periodic sync with the advertiser registered in Periodic Advertiser List. + * @param[in] adv_sid + * Advertising SID. When p_addr is specified as NULL, adv_sid is ignored. + * Valid range is 0x00 - 0x0F. + * @param[in] skip + * The number of consecutive periodic advertising packets + * that local device may skip after receiving a periodic advertising packet. + * Valid range is 0x0000 - 0x01F3. + * @param[in] sync_to + * The maximum permitted time between successful receives.When sync_to expires, + * the periodic sync is lost. + * Time(ms) = sync_to * 10. + * Valid range is 0x000A - 0x4000. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range. + * - address type in p_addr + * - adv_sid + * - skip + * - sync_to + * + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr, uint8_t adv_sid, uint16_t skip, uint16_t sync_to); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CancelCreateSync(void) + * @brief Cancel the request for a periodic sync establishment. + * @details This function cancels a request for establishing a periodic sync. + * The result of this API call is notified in BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CancelCreateSync(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl) + * @brief Terminate the periodic sync. + * @details This function terminates a periodic sync. + * The result of this API call is notified in BLE_GAP_EVENT_SYNC_TERM event. + * @param[in] sync_hdl Sync handle identifying the periodic sync to be terminated. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) sync_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t op_code, + * st_ble_dev_addr_t * p_addr, + * uint8_t * p_adv_sid_set, + * uint8_t device_num + * ) + * @brief Set Periodic Advertiser List. + * @details This function supports the following operations regarding Periodic Advertiser List. + * - Add the device to Periodic Advertiser List. + * - Delete the device from Periodic Advertiser List. + * - Clear Periodic Advertiser List. + * + * The total number of Periodic Advertiser List entries is defined as BLE_GAP_PERD_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for Periodic Advertiser List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of device address to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] p_adv_sid_set An array of SID of the advertiser to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_adv_sid_set is ignored. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_PERD_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV, + * p_addr or p_adv_sid_set is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr or p_adv_sid_set or + * device_num is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating Periodic Advertiser List, this function was called. + * - The task for host stack is not running. + * + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating periodic advertiser. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t op_code, + st_ble_dev_addr_t * p_addr, + uint8_t * p_adv_sid_set, + uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag) + * @brief Authorize a remote device. + * @details User authorizes a remote device by this function. + * This function is used when a remote device accesses a GATT Characteristic + * in local device which requests user authorization. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device to be authorized or not by user. + * @param[in] author_flag Authorize or not the remote device. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_NOT_AUTHORIZED(0x00) | Not authorize the remote device. | + * | BLE_GAP_AUTHORIZED(0x01) | Authorize the remote device. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) author_flag is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl) + * @brief Get the information about remote device. + * @details This function retrieves information about the remote device. + * The information includes BD_ADDR, the version number and LE features. + * The result of this API call is notified in BLE_GAP_EVENT_GET_REM_DEV_INFO event. + * @param[in] conn_hdl Connection handle identifying the remote device whose information to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param) + * @brief Set the parameters using pairing. + * @details This function sets the parameters used in pairing. + * The parameters set by this API are sent to the remote device when pairing occurred. + * The result of this API call is returned by a return value. + * @param[in] p_pair_param Pairing parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in p_pair_param is out of range. + * - iocap + * - max_key_size + * - mitm + * - bonding + * - key_notf + * - sec_conn_only + * + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk) + * @brief Set the IRK and the identity address distributed to a remote device. + * @details This function registers local IRK and identity address of local device in host stack. + * The IRK and the identity address are distributed to a remote device in pairing. + * The result of this API call is returned by a return value. + * @param[in] p_lc_id_addr Identity address to be registered in host stack. + * @param[in] p_lc_irk IRK to be registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_lc_id_addr or p_lc_irk is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) Address type field in p_lc_id_addr is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk) + * @brief Set the CSRK distributed to a remote device. + * @details This function registers local CSRK in host stack. + * The CSRK is distributed to a remote device in pairing. + * The result of this API call is returned by a return value. + * @param[in] p_local_csrk CSRK to be registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_local_csrk is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl) + * @brief Start pairing. + * @details This function starts pairing with a remote device. + * The result of this API call is returned by a return value. + * The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event. + * @param[in] conn_hdl Connection handle identifying the remote device which local device starts pairing with. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) While pairing, this function was called. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response) + * @brief Reply the pairing request from a remote device. + * @details This function replies to the pairing request from the remote device. + * The pairing request from the remote device is notified in BLE_GAP_EVENT_PAIRING_REQ event. + * The result of this API call is returned by a return value. + * The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event. + * @param[in] conn_hdl Connection handle identifying the remote device which local device starts pairing with. + * @param[in] response Accept or reject the pairing request from the remote device. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_PAIRING_ACCEPT(0x00) | Accept the pairing request. | + * | BLE_GAP_PAIRING_REJECT(0x01) | Reject the pairing request. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, + * host stack has not yet received BLE_GAP_EVENT_PAIRING_REQ event. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl) + * @brief Encryption the link. + * @details This function starts encryption of the link. + * In case of master device, the local device requests for the encryption to a remote device. + * In case of slave device, the local device sends a Security Request to a remote device. + * After receiving the Security Request, the remote device requests for the encryption to the local device. + * The result of the encryption is returned in BLE_GAP_EVENT_ENC_CHG event. + * @param[in] conn_hdl Connection handle identifying the link which is encrypted. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - Pairing has not been completed. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response) + * @brief Reply the passkey entry request. + * @details When BLE_GAP_EVENT_PASSKEY_ENTRY_REQ event is notified, + * the response to passkey entry is sent by this function. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device which the reply to passkey entry is sent. + * @param[in] passkey Passkey. + * The valid range is 000000 - 999999 in decimal. + * @param[in] response Active or negative reply to passkey entry. + * | macro | description | + * |:----------------------------- |:---------------------------------- | + * | BLE_GAP_PAIRING_ACCEPT(0x00) | Accept the passkey entry pairing. | + * | BLE_GAP_PAIRING_REJECT(0x01) | Reject the passkey entry pairing. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) passkey or response is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response) + * @brief Reply the numeric comparison request. + * @details When BLE_GAP_EVENT_NUM_COMP_REQ event is notified, + * the response to Numeric Comparison is sent by this function. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device which the reply to Numeric Comparison is sent. + * @param[in] response Active or negative reply in Numeric Comparison. + * | macro | description | + * |:-------------------------- |:----------------------------------------------------------------------- | + * |BLE_GAP_PAIRING_ACCEPT(0x00)| The number displayed in the local is the same as the one of the remote. | + * |BLE_GAP_PAIRING_REJECT(0x01)| The number displayed in the local is differs from the one of the remote.| + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) When this function was called, + * host stack has not yet received @ref BLE_GAP_EVENT_NUM_COMP_REQ event. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press) + * @brief Notify the input key type which a remote device inputs in the passkey entry. + * @details This function notifies the input key type to the remote device in passkey entry. + * The result is returned from this API. + * @param[in] conn_hdl Connection handle identifying the remote device to which the key notification is sent. + * @param[in] key_press Input key type. + * | macro | description | + * |:------------------------------------------ |:------------------------------------- | + * | BLE_GAP_LESC_PASSKEY_ENTRY_STARTED(0x00) | Notify that passkey entry started. | + * | BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED(0x01) | Notify that passkey digit entered. | + * | BLE_GAP_LESC_PASSKEY_DIGIT_ERASED(0x02) | Notify that passkey digit erased. | + * | BLE_GAP_LESC_PASSKEY_CLEARED(0x03) | Notify that passkey cleared. | + * | BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED(0x04) | Notify that passkey entry completed. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) key_press parameter is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info) + * @brief Get the security information about the remote device. + * @details This function gets the parameters which has been negotiated with the remote device in pairing. + * The parameters can be retrieved after pairing. + * The result is returned by p_sec_info. + * @param[in] conn_hdl Connection handle identifying the remote device whose bonding information is retrieved. + * @param[in] p_sec_info Return the security information which has been negotiated in pairing. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_sec_info is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The remote device bonding information has not been set to host stack. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl) + * @brief Distribute the keys of local device. + * @details When key exchange request is notified by BLE_GAP_EVENT_EX_KEY_REQ event at pairing, + * keys of the local device are distributed. + * The result is returned from this API. + * @param[in] conn_hdl Connection handle identifying the remote device to which the key is distributed. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRemOobData( st_ble_dev_addr_t * p_addr, + * uint8_t oob_data_flag, + * st_ble_gap_oob_data_t * p_oob + * ) + * @brief Set the oob data from a remote device. + * @details This function registers the OOB data received from a remote device. + * When oob_data_flag indicates that the OOB data has been received, + * the setting regarding OOB data is reflected in pairing. + * In order to do OOB pairing, set the OOB data received from the remote device before pairing. + * The result is returned from this API. + * @param[in] p_addr The remote device address. + * @param[in] oob_data_flag This parameter indicates whether the local device has received the OOB data + * from the remote device or not. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_OOB_DATA_NOT_PRESENT(0x00)| Reply that No OOB data has been received when pairing. | + * | BLE_GAP_OOB_DATA_PRESENT(0x01) | Reply that the OOB data has been received when pairing. | + * @param[in] p_oob The OOB data received from the remote device. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows. + * - p_addr is specified as NULL. + * - oob_data_flag is BLE_GAP_OOB_DATA_PRESENT and p_oob is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) oob_data_flag is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) There is no room to register the OOB data received from a remote device. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRemOobData(st_ble_dev_addr_t * p_addr, uint8_t oob_data_flag, st_ble_gap_oob_data_t * p_oob); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateScOobData(void) + * @brief Create data for oob in secure connection. + * @details This function generates the OOB data distributed to a remote device in Secure Connections. + * The result of this API call is notified in BLE_GAP_EVENT_SC_OOB_CREATE_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - This function was called in pairing. + * - The task for host stack is not running. + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) This function was called in creating OOB data. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateScOobData(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info, + * uint8_t device_num, + * uint8_t * p_set_num + * ) + * @brief Set the bonding information stored in non-volatile memory to the host stack. + * @details Set the bonding information of the remote device in the host stack. + * After power re-supply, when the remote device bonding information stored in non-volatile memory is + * set to host stack, this function is used. + * Host stack can be set the number specified by the device_num parameter of bonding information. + * @param[in] p_bond_info An array of bonding information. The number of elements is specified by device_num. + * @param[in] device_num The number of the devices of which host stack registers bonding information. + * @param[in] p_set_num The number of the devices whose bonding information was registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_bond_info or p_set_num is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) device_num is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack already has the maximum number of bonding information. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info, uint8_t device_num, uint8_t * p_set_num); + +/******************************************************************************************************************//** + * @fn void R_BLE_GAP_DeleteBondInfo(int32_t local, + * int32_t remote, + * st_ble_dev_addr_t * p_addr, + * ble_gap_del_bond_cb_t gap_del_bond_cb) + * @brief This function deletes the bonding information in Host Stack.\n + * When a function for deleting the bonding information stored in non-volatile area is registered by the + * gap_del_bond_cb parameter, it is deleted as well as the bonding information in Host Stack. + * + * @param[in] local The type of the local bonding information to be deleted. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_SEC_DEL_LOC_NONE(0x00) | Delete no local keys. | + * | BLE_GAP_SEC_DEL_LOC_IRK(0x01) | Delete local IRK and identity address. | + * | BLE_GAP_SEC_DEL_LOC_CSRK(0x02) | Delete local CSRK. | + * | BLE_GAP_SEC_DEL_LOC_ALL(0x03) | Delete all local keys. | + * @param[in] remote The type of the remote bonding information to be deleted. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_SEC_DEL_REM_NONE(0x00) | Delete no remote device keys. | + * | BLE_GAP_SEC_DEL_REM_SA(0x01) | Delete the keys specified by the p_addr parameter. | + * | BLE_GAP_SEC_DEL_REM_NOT_CONN(0x02)| Delete keys of not connected remote devices. | + * | BLE_GAP_SEC_DEL_REM_ALL(0x03) | Delete all remote device keys. | + * \n\n + * @param[in] p_addr p_addr is specified as the address of the remote device whose keys are deleted + * when the rem_info parameter is set to @ref BLE_GAP_SEC_DEL_REM_SA(0x01). + * \n\n + * @param[in] gap_del_bond_cb This parameter is a callback function which deletes the bonding information stored + * in non-volatile area. \n After deleting the bonding information stored in Host Stack, + * the callback function is called. If no bonding information is stored in + * non-volatile area, specify the parameter as NULL. + * @retval none + **********************************************************************************************************************/ +void R_BLE_GAP_DeleteBondInfo(int32_t local, + int32_t remote, + st_ble_dev_addr_t * p_addr, + ble_gap_del_bond_cb_t gap_del_bond_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, + * uint16_t ediv, + * uint8_t * p_peer_rand, + * uint8_t response + * ) + * @brief Reply the LTK request from a remote device. + * @details This function replies to the LTK request in BLE_GAP_EVENT_LTK_REQ event from a remote device. + * The result of the LTK reply is returned in BLE_GAP_EVENT_LTK_RSP_COMP event. + * When the link encryption has completed, BLE_GAP_EVENT_ENC_CHG event is notified. + * @param[in] conn_hdl Connection handle identifying the remote device which sent the LTK request. + * @param[in] ediv Ediv notified in BLE_GAP_EVENT_LTK_REQ event. + * @param[in] p_peer_rand Rand notified in BLE_GAP_EVENT_LTK_REQ event. + * @param[in] response Response to the LTK request. + * If "BLE_GAP_LTK_REQ_ACCEPT" is specified, + * when no LTK has been exchanged in pairing, reject the LTK request. + * | macro | description | + * |:----------------------------- |:---------------------------------- | + * | BLE_GAP_LTK_REQ_ACCEPT(0x00) | Reply for the LTK request. | + * | BLE_GAP_LTK_REQ_DENY(0x01) | Reject the LTK request. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_peer_rand is specified as NULL in case of legacy pairing. + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, uint16_t ediv, uint8_t * p_peer_rand, uint8_t response); + +/*@}*/ + +/* ========================================== GATT Common API Declarations ========================================== */ + +/** @defgroup GATT_COMMON_API GATT_COMMON + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_COMMON_API + * @fn ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu) + * @brief This function gets the current MTU used in GATT communication. + * @details Both GATT server and GATT Client can use this function. \n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the GATT Server or the GATT Client. + * @param[in] p_mtu The Current MTU. Before MTU exchange, this parameter is 23 bytes. \n + * After MTU exchange, this parameter is the negotiated MTU. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The mtu parameter is NULL. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server or the GATT Client specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu); + +/*@}*/ + +/* ========================================== GATT Server API Declarations ========================================== */ + +/** @defgroup GATT_SERVER_API GATT_SERVER + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @fn ble_status_t R_BLE_GATTS_Init(uint8_t cb_num) + * @brief This function initializes the GATT Server and registers the number of the callbacks for GATT Server event. + * @details Specify the cb_num parameter to a value between 1 and BLE_GATTS_MAX_CB.\n + * R_BLE_GATTS_RegisterCb() registers the callback.\n + * The result of this API call is returned by a return value. + * @param[in] cb_num The number of callbacks to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Init(uint8_t cb_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst) + * @brief This function sets GATT Database to host stack. + * @details The result of this API call is returned by a return value. + * @param[in] p_db_inst GATT Database to be set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows. + * - The db_inst parameter is specified as NULL. + * - The array in the db_inst is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority) + * @brief This function registers a callback for GATT Server event. + * @details The number of the callback that may be registered by this function is the value specified + * by R_BLE_GATTS_Init().\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for GATT Server event. + * @param[in] priority The priority of the callback function.\n + * Valid range is 1 <= priority <= BLE_GATTS_MAX_CB.\n + * A lower priority number means a higher priority level. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb) + * @brief This function deregisters the callback function for GATT Server event. + * @details The result of this API call is returned by a return value. + * @param[in] cb The callback function to be deregistered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data) + * @brief This function sends a notification of an attribute's value. + * @details The maximum length of the attribute value that can be sent with notification is MTU-3.\n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the notification. + * @param[in] p_ntf_data The attribute value to send. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_ntf_data parameter or the value field in the value field in + * the p_ntf_data parameter is NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ntf_data parameter is 0 + * or the attr_hdl field in the p_ntf_data parameters is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data) + * @brief This function sends a indication of an attribute's value. + * @details The maximum length of the attribute value that can be sent with indication is MTU-3.\n + * The result of this API call is returned by a return value.\n + * The remote device that receives a indication sends a confirmation.\n + * BLE_GATTS_EVENT_HDL_VAL_CNF event notifies the application layer that the confirmation has been received. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the indication. + * @param[in] p_ind_data The attribute value to send. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_ind_data parameter or the value field in the value field in + * the p_ind_data parameter is NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ind_data parameter is 0 + * or the attr_hdl field in the p_ind_data parameters is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value) + * @brief This function gets a attribute value from the GATT Database. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved, + * specify the remote device with the conn_hdl parameter. + * When information about the remote device is not required, + * set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL. + * @param[in] attr_hdl The attribute handle of the attribute value to be retrieved. + * @param[out] p_value The attribute value to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_value parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle + * of GATT Database. + * @retval BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be read. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be read. + * @retval BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to + * any services or characteristics. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value) + * @brief This function sets an attribute value to the GATT Database. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved, + * specify the remote device with the conn_hdl parameter. + * When information about the remote device is not required, + * set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL. + * @param[in] attr_hdl The attribute handle of the attribute value to be set. + * @param[in] p_value The attribute value to be set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_value parameter is specified as NULL. + * @retval BLE_ERR_INVALID_DATA(0x0002) The write size is larger than the length of the attribute value. + * @retval BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle + * of GATT Database. + * @retval BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be written. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be written. + * @retval BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to + * any services or characteristics. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code) + * @brief This function sends an error response to a remote device. + * @details The result is returned from the API.\n + * The error code specified in the callback is notified as Error Response to the remote device.\n + * The result of this API call is returned by a return value. + * @param[in] error_code The error codes to be notified the client.\n + * It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined + * in Core Spec and Core Spec Supplement. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred, the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute. + *
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported. + *
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient. + *
0x3080 - 0x309FApplication Error. + * The upper layer defines the error codes.
0x30E0 - 0x30FF + * The error code defined in Common Profile and Service Error + * Core Specification Supplement(CSS).
+ * CSS ver.7 defines the error codes from 0x30FC to 0x30FF. + *
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC)The Write Request has not been completed due to the reason other than Permission. + *
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.
+ * + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The Group ID of the error_code parameter is not 0x3000, or it is 0x3000. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other error response,this function was called. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu) + * @brief This function replies to a MTU Exchange Request from a remote device. + * @details BLE_GATTS_EVENT_EX_MTU_REQ event notifies the application layer + * that a MTU Exchange Request has been received. + * Therefore when the callback has received the event, call this function.\n + * The new MTU is the minimum of the mtu parameter specified by this function + * and the mtu field in BLE_GATTS_EVENT_EX_MTU_REQ event.\n + * Default MTU size is 23 bytes.\n + * The result of this API call is returned by a return value.\n + * @param[in] conn_hdl Connection handle identifying the remote device to be sent MTU Exchange Response. + * @param[in] mtu The maximum size(in bytes) of the GATT PDU that GATT Server can receive.\n + * Valid range is 23 <= mtu <= 247. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num) + * @brief Register prepare queue and buffer in Host Stack. + * @details This function registers the prepare queue and buffer for long chracteristic write and reliable writes. + * The result of this API call is returned by a return value.\n + * @param[in] p_pre_queues The prepare write queues to be registered. + * @param[in] queue_num The number of prepare write queues to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_pre_queue parameter is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num); + +/*@}*/ + +/* ========================================== GATT Client API Declarations ========================================== */ + +/** @defgroup GATT_CLIENT_API GATT_CLIENT + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @fn ble_status_t R_BLE_GATTC_Init(uint8_t cb_num) + * @brief This function initializes the GATT Client and registers the number of the callbacks for GATT Client event. + * @details Specify the cb_num parameter to a value between 1 and BLE_GATTC_MAX_CB.\n + * R_BLE_GATTC_RegisterCb() registers the callback.\n + * The result of this API call is returned by a return value. + * @param[in] cb_num The number of callbacks to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_Init(uint8_t cb_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority) + * @brief This function registers a callback function for GATT Client event. + * @details The number of the callback that may be registered by this function is the value specified + * by R_BLE_GATTC_Init().\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for GATT Client event. + * @param[in] priority The priority of the callback function.\n + * Valid range is 1 <= priority <= BLE_GATTC_MAX_CB.\n + * A lower priority number means a higher priority level. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb) + * @brief This function deregisters the callback function for GATT Client event. + * @details The result of this API call is returned by a return value. + * @param[in] cb The callback function to be deregistered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu) + * @brief This function sends a MTU Exchange Request PDU to a GATT Server in order to change the current MTU. + * @details MTU Exchange Response is notified by BLE_GATTC_EVENT_EX_MTU_RSP event.\n + * The new MTU is the minimum value of the mtu parameter specified by this function and + * the mtu field in BLE_GATTC_EVENT_EX_MTU_RSP event. + * Default MTU size is 23 bytes.\n + * The result of this API call is returned by a return value.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be sent. + * @param[in] mtu The maximum size(in bytes) of the GATT PDU that GATT Client can receive. \n + * Valid range is 23 <= mtu <= 247. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl) + * @brief This function discovers all Primary Services in a GATT Server. + * @details When 16-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event + * is notified to the application layer.\n + * When the Primary Service discovery has been completed, BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type) + * @brief This function discovers Primary Service specified by p_uuid in a GATT Server. + * @details When Primary Service whose uuid is the same as the specified uuid has been discovered, + * BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event or BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event is + * notified to the application layer.\n + * When the Primary Service discovery has been completed, BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_uuid UUID of Primary Service to be discovered. + * @param[in] uuid_type UUID type(16-bit or 128-bit). + * | macro | description | + * |:---------------------------------- |:---------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | 16-bit UUID | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | 128-bit UUID | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllSecondServ( uint16_t conn_hdl) + * @brief This function discovers all Secondary Services in a GATT Server. + * @details When a 16-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND event + * is notified to the application layer.\n + * When a 128-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND event + * is notified to the application layer.\n + * When the Secondary Service discovery has been completed, BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllSecondServ(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Included Services within the specified attribute handle range in a GATT Server. + * @details When Included Service that includes 16-bit UUID Service has been discovered, + * BLE_GATTC_EVENT_INC_SERV_16_DISC_IND event is notified to the application layer.\n + * When Included Service that includes 128-bit UUID Service has been discovered, + * BLE_GATTC_EVENT_INC_SERV_128_DISC_IND event is notified to the application layer.\n + * When the Included Service discovery has been completed, + * BLE_GATTC_EVENT_INC_SERV_DISC_COMP event is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Included Service. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Characteristic within the specified attribute handle range in a GATT Server. + * @details When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event + * is notified to the application layer.\n + * When the Characteristic discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t conn_hdl, + * uint8_t * p_uuid, + * uint8_t uuid_type, + * st_ble_gatt_hdl_range_t * p_range + * ) + * @brief This function discovers Characteristic specified by uuid within the specified attribute handle range + * in a GATT Server. + * @details When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event + * is notified to the application layer.\n + * When the Characteristic discovery has been completed, BLE_GATTC_EVENT_CHAR_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_uuid UUID of Characteristic to be discovered. + * @param[in] uuid_type UUID type of Characteristic to be discovered. + * | macro | description | + * |:---------------------------------- |:------------------------------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | The p_uuid parameter is 16-bit UUID. | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. | + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t conn_hdl, + uint8_t * p_uuid, + uint8_t uuid_type, + st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Characteristic Descriptor within the specified attribute handle range + * in a GATT Server. + * @details When 16-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND + * event is notified to the application layer. + * When 128-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND + * event is notified to the application layer. + * When the Characteristic Descriptor discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP + * event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Characteristic Descriptor. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl) + * @brief This function reads a Characteristic/Characteristic Descriptor in a GATT Server. + * @details The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_RSP event. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be read. + * @param[in] value_hdl Value handle of the Characteristic/Characteristic Descriptor to be read. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t conn_hdl, + * uint8_t * p_uuid, + * uint8_t uuid_type, + * st_ble_gatt_hdl_range_t * p_range + * ); + * @brief This function reads a Characteristic in a GATT Server using a specified UUID. + * @details The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP event. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_uuid UUID of the Characteristic to be read. + * @param[in] uuid_type UUID type of the Characteristic to be read. + * | macro | description | + * |:---------------------------------- |:------------------------------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | The p_uuid parameter is 16-bit UUID. | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. | + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t conn_hdl, + uint8_t * p_uuid, + uint8_t uuid_type, + st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset) + * @brief This function reads a Long Characteristic in a GATT Server. + * @details The contents of the Long Characteristic that has been read is notified every MTU-1 bytes to + * the application layer by BLE_GATTC_EVENT_CHAR_READ_RSP event.\n + * When all of the contents has been received in GATT Client, BLE_GATTC_EVENT_LONG_CHAR_READ_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be read. + * @param[in] value_hdl Value handle of the Long Characteristic to be read. + * @param[in] offset Offset that indicates the location to be read.\n + * Normally, set 0 to this parameter. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list) + * @brief This function reads multiple Characteristics in a GATT Server. + * @details The contents of the multiple Characteristics that has been read is notified to the application layer + * by BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP event. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_list List of Value Handles that point the Characteristics to be read. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_list parameter or the p_hdl_list field in the p_list parameter is + * specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the list_count field in the p_list parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes a Characteristic in a GATT Server without response. + * @details The result is returned from the API. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_write_data Value to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the p_value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes Signed Data to a Characteristic in a GATT Server without response. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Signed Data to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or Signed Data. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes a Characteristic in a GATT Server. + * @details The result of the write is notified in BLE_GATTC_EVENT_CHAR_WRITE_RSP event. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Value to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl, + * st_ble_gatt_hdl_value_pair_t * p_write_data, + * uint16_t offset + * ) + * @brief This function writes a Long Characteristic in a GATT Server. + * @details The result of a write that has been done every segmentation is notified to the application layer + * in BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP event.\n + * The maximum writable size to a Long Characteristic with this function is 512 bytes.\n + * When all of the contents has been written to the Long Characteristic, BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP + * event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Value to be written to the Long Characteristic. + * @param[in] offset Offset that indicates the location to be written. + * Normally, set 0 to this parameter.\n + * If this parameter sets to a value other than 0, adjust the offset parameter and + * the length of the value to be written not to exceed the length of the Long Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field in + * the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - The value_len field in the value field in the p_write_data parameter is 0. + * - The sum of the value_len field in the value field in the p_write_data parameter + * and the offset parameter larger than 512. + * - The attr_hdl field in the p_write_data parameter is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data, uint16_t offset); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t conn_hdl, + * st_ble_gattc_reliable_writes_char_pair_t * p_char_pair, + * uint8_t pair_num, + * uint8_t auto_flag + * ) + * @brief This function performs the Reliable Writes procedure described in GATT Specification. + * @details When the data written to the Characteristic has been transmitted, BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP + * event is notified to the application layer.\n + * If the data included in the event is different from the data that GATT Client has sent, + * host stack automatically cancels the Reliable Writes.\n + * After all of the contents has been sent to the GATT Server, if the auto_flag parameter has been set to + * BLE_GATTC_EXEC_AUTO, the GATT Server automatically writes the data to the Characteristic.\n + * If the auto_flag parameter has been set to BLE_GATTC_EXEC_NOT_AUTO, BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP + * event notifies the application layer in GATT Client that all of the contents has been sent to + * the GATT Server. Then GATT Client requests for writing the data to the Characteristic to the GATT Server + * with R_BLE_GATTC_ExecWrite().\n + * When the write has been done, BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event is notified to + * the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_char_pair Pair of Characteristic Value and Characteristic Value Handle identifying the Characteristic + * to be written by Reliable Writes. + * @param[in] pair_num The number of the pairs specified by the p_char_pair parameter.\n + * Valid range is 0 < pair_num <= BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR. + * @param[in] auto_flag The flag that indicates whether auto execution or not. + * | macro | description | + * |:------------------------------ |:------------------- | + * | BLE_GATTC_EXEC_AUTO(0x01) | Auto execution. | + * | BLE_GATTC_EXEC_NOT_AUTO (0x02) | Not auto execution. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - The p_char_pair parameter is specified as NULL. + * - The p_value field in the value field in the write_data field in the p_char_pair parameter + * is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - The pair_num parameter or the auto_flag parameter is out of range. + * - The value_len field in the value field in the write_data field in the p_char_pair parameter is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or + * to store the temporary write data. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t conn_hdl, + st_ble_gattc_reliable_writes_char_pair_t * p_char_pair, + uint8_t pair_num, + uint8_t auto_flag); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag) + * @brief If the auto execute of Reliable Writes is not specified by R_BLE_GATTC_ReliableWrites(), + * this function is used to execute a write to Characteristic. + * @details When all of the contents has been sent to the GATT Server, BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP event + * notifies the application layer.\n + * After this event has been received, execute the write by this function.\n + * The result of the write is notified by BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event. + * @param[in] conn_hdl Connection handle identifying the target GATT Server. + * @param[in] exe_flag The flag that indicates whether execution or cancellation. + * | macro | description | + * |:------------------------------------------- |:------------------- | + * | BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG(0x00) | Execute the write. | + * | BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG(0x01) | Cancel the write. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The exe_flag parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The reason for this error is as follows: + * - GATT Client has not requested for Reliable Writes by R_BLE_GATTC_ReliableWrites(). + * - Although auto execution has been specified by R_BLE_GATTC_ReliableWrites(), this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag); + +/*@}*/ + +/* ============================================= L2CAP API Declarations ============================================= */ + +/** @defgroup L2CAP_API L2CAP + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @fn ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm) + * @brief This function registers PSM that uses L2CAP CBFC Channel and a callback for L2CAP event. + * @details Only one callback is available per PSM. Configure in each PSM the Low Water Mark of the LE-Frames + * that the local device can receive.\n + * When the number of the credit reaches the Low Water Mark, BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event is + * notified to the application layer.\n + * The number of PSM is defined as BLE_L2CAP_MAX_CBFC_PSM.\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for L2CAP event. + * @param[in] psm Identifier indicating the protocol/profile that uses L2CAP CBFC Channel. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
typerangedescription
Fixed, SIG assigned0x0001 - 0x007FPSM defined by SIG. For more information on PSM, refer Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers). + *
Dynamic0x0080 - 0x00FF + * Statically allocated PSM by custom protocol or dynamically allocated PSM by GATT Service. + *
+ * @param[in] lwm Low Water Mark that indicates the LE-Frame numbers that the local device can receive. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The psm parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) More than BLE_L2CAP_MAX_CBFC_PSM+1 PSMs, callbacks has been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm) + * @brief This function stops the use of the L2CAP CBFC Channel specified by the psm parameter and + * deregisters the callback function for L2CAP event. + * @details The result of this API call is returned by a return value. + * @param[in] psm PSM that is to be stopped to use the L2CAP CBFC Channel.\n + * Set the PSM registered by R_BLE_L2CAP_RegisterCfPsm(). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback function allocated by the psm parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param) + * @brief This function sends a connection request for L2CAP CBFC Channel. + * @details The connection response is notified by BLE_L2CAP_EVENT_CF_CONN_CNF event.\n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device that the connection request is sent to. + * @param[in] p_conn_req_param Connection request parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_conn_req_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter or the mps parameter is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) New CF Channel can not be registered or other L2CAP Command is processing. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) The psm parameter is not registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param) + * @brief This function replies to the connection request for L2CAP CBFC Channel from the remote device. + * @details The connection request is notified by BLE_L2CAP_EVENT_CF_CONN_IND event. + * The result of this API call is returned by a return value. + * @param[in] p_conn_rsp_param Connection response parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_conn_rsp_param parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) A connection request for L2CAP CBFC Channel has not been received, + * or CID specified by the lcid field in the p_conn_rsp_param parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid) + * @brief This function sends a disconnection request for L2CAP CBFC Channel. + * @details When L2CAP CBFC Channel has been disconnected, + * BLE_L2CAP_EVENT_CF_DISCONN_CNF event is notified to the application layer. + * @param[in] lcid CID identifying the L2CAP CBFC Channel that has been disconnected.\n + * The valid range is 0x40 - (0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) CF Channel connection has not been established. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + * @retval BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit) + * @brief This function sends credit to a remote device. + * @details In L2CAP CBFC communication, if credit is 0, the remote device stops data transmission.\n + * Therefore when processing the received data has been completed and local device affords to receive data, + * the remote device is notified of the number of LE-Frame that local device can receive + * by this function and local device can continue to receive data from the remote device.\n + * The result of this API call is returned by a return value. + * @param[in] lcid CID identifying the L2CAP CBFC Channel on local device that sends credit. + * @param[in] credit Credit to be sent to the remote device. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The credit parameter is set to 0. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu) + * @brief This function sends the data to a remote device via L2CAP CBFC Channel. + * @details When the data transmission to Controller has been completed, + * BLE_L2CAP_EVENT_CF_TX_DATA_CNF event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the data. + * @param[in] lcid CID identifying the L2CAP CBFC Channel on local device used in the data transmission. + * @param[in] data_len Length of the data. + * @param[in] p_sdu Service Data Unit. \n + * Input the data length specified by the data_len parameter to the first 2 bytes (Little Endian). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The length parameter is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established or the data whose length + * exceeds the MTU has been sent. + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) Data transmission has been already started. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) L2CAP task queue is full. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + * @retval BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu); + +/*@}*/ + +/* ======================================== Vendor Specific API Declarations ======================================== */ + +/** @defgroup VS_API VS + * @ingroup BLE + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @fn ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb) + * @brief This function initializes Vendor Specific API and registers a callback function for Vendor Specific Event. + * @details The result of this API call is returned by a return value. + * @param[in] vs_cb Callback function to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The vs_cb parameter is specified as NULL. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Callback function has already been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param) + * @brief This function starts extended Transmitter Test. + * @details The following extended transmitter test functions of DTM Tx are supported by this function. + * - Tx Power + * - Tx Modulation Enable/Modulation Disable + * - Tx packet transmission/continuous transmission + * - Tx packets count + * + * The result of this API call is notified in BLE_VS_EVENT_TX_TEST_START event.\n + * If the num_of_packet field in the p_tx_test_param parameter is other than 0x0000, + * BLE_VS_EVENT_TX_TEST_TERM event notifies the application layer that the number of packet has been sent.\n + * If R_BLE_VS_EndTest() is called before the specified number of packets completions, + * BLE_VS_EVENT_TX_TEST_TERM event is not notified to the application layer. + * + * The condition that phy field in the p_tx_test_param parameter is @ref BLE_VS_EH_TEST_PHY_CODED_S_8(0x03) + * and option field is modulation(bit0:0) & continuous transmission(bit1:1) is not supported. + * + * @param[in] p_tx_test_param Tx Test parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_tx_test_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param) + * @brief This function starts extended Receiver Test. + * @details The result of this API call is notified in BLE_VS_EVENT_RX_TEST_START event. + * The following extended receiver test functions of DTM Rx are supported by this function. + * - Calculating the maximum, the minimum and the average of RSSI in the receiver test. + * - The number of CRC error packets in the receiver test. + * + * The transmitter is configured to one of the following, the receiver can't receive the packets by this function.\n + * - Tx Non-Modulation Enable + * - Tx continuous transmission + * \n + * After R_BLE_VS_EndTest() has been called, + * the receiver test result value are notified in BLE_VS_EVENT_TEST_END event. + * + * @param[in] p_rx_test_param The extended receiver test parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_rx_test_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_EndTest(void) + * @brief This function terminates the extended transmitter or receiver test. + * @details The result of this API call is notified in BLE_VS_EVENT_TEST_END event. + * In case of extended receiver test, this event notifies the application layer of + * the result of the extended receiver test. + * + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_EndTest(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power) + * @brief This function configures transmit power. + * @details This function configures the following transmit power. + * - The transmit power used in sending advertising PDU, scan request PDU, + * connection request PDU (in not connected state) + * - The transmit power used in sending PDU in connected state. + * When configuring the transmit power used in not connected state, set the conn_hdl parameter + * to BLE_GAP_INIT_CONN_HDL(0xFFFF).\n + * When the transmit power used in connected state is configured, set the conn_hdl parameter + * to the connection handle of the link.\n + * Select one of the following transmit power levels. + * - High + * - Middle + * - Low + * + * Max transmit power of "High" is dependent on the configuration of the firmware. + * The result of this API call is notified in BLE_VS_EVENT_SET_TX_POWER event. + * + * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be configured. + * If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF). + * @param[in] tx_power Transmission power. Select one of the following. + * - BLE_VS_TX_POWER_HIGH(0x00) + * - BLE_VS_TX_POWER_MID(0x01) + * - BLE_VS_TX_POWER_LOW(0x02) + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl) + * @brief This function gets transmit power. + * @details This function gets the following transmit power. + * - The transmit power used in sending advertising PDU, scan request PDU, + * connection request PDU (in not connected state) + * - The transmit power used in sending PDU in connected state. + * When getting the transmit power used in not connected state, set the conn_hdl parameter to + * BLE_GAP_INIT_CONN_HDL(0xFFFF).\n + * When the transmit power used in connected state is retrieved, set the conn_hdl parameter to + * the connection handle of the link. + * The result of this API call is notified in BLE_VS_EVENT_GET_TX_POWER event. + * + * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be retrieved. + * If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme) + * @brief This function configure default Coding scheme(S=8 or S=2) that is used in the case of selecting Coded PHY + * in Primary advertising PHY or Secondary advertising PHY advertising or request for link establishment. + * @details After setting the default Coding scheme by this function, configure the advertising parameters + * by R_BLE_GAP_SetAdvParam() or send a request for link establishment.\n + * The result of this API call is notified in BLE_VS_EVENT_SET_CODING_SCHEME_COMP event. + * @param[in] coding_scheme Coding scheme for Primary advertising PHY, Secondary advertising PHY, + * request for link establishment.The coding_scheme field is set to a bitwise OR + * of the following values. + * | bit | description | + * |:-------------- |:-------------------------------------------------------------- | + * | bit0 | Coding scheme for Primary Advertising PHY(0:S=8/1:S=2). | + * | bit1 | Coding scheme for Secondary Advertising PHY(0:S=8/1:S=2). | + * | bit2 | Coding scheme for request for link establishment(0:S=8/1:S=2). | + * | All other bits | Reserved for future use. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl) + * @brief This function performs power control on RF. + * @details If BLE communication is not used for a long time, RF reduces the power consumption by moving to + * the RF Power-Down Mode.\n + * When RF power on, RF initialization processing is executed.\n + * After RF power off by this function, API functions other than this are not available + * until RF power on again.\n + * The result of this API call is notified in BLE_VS_EVENT_RF_CONTROL_COMP event. + * After RF power on again with this function, call R_BLE_GAP_Terminate(), + * R_BLE_GAP_Init() in order to restart the host stack. + * @param[in] p_rf_ctrl RF parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_rf_ctrl parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr) + * @brief This function sets public/random address of local device to the area specified by the parameter. + * @details If the address is written in non-volatile area, the address is used as default address + * on the next MCU reset.\n + * For more information on the random address, refer to Core Specification Vol 6, PartB, + * "1.3.2 Random Device Address".\n + * The result of this API call is notified in BLE_VS_EVENT_SET_ADDR_COMP event. + * @param[in] area The area that the address is to be written in.\n + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_VS_ADDR_AREA_REG(0x00) + * Address writing to non-volatile area is not performed.
+ * Only the address in register is written. + *
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Address wiring to DataFlash area is performed.
+ * @param[in] p_addr The address to be set to the area. + * Set BLE_GAP_ADDR_PUBLIC(0x00) or BLE_GAP_ADDR_RAND(0x01) to the type field in the p_addr parameter. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_addr parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type) + * @brief This function gets currently configured public/random address. + * @details The area parameter specifies the place where this function retrieves public/random address.\n + * The result of this API call is notified in BLE_VS_EVENT_GET_ADDR_COMP event. + * @param[in] area The area that the address is to be retrieved.\n + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_VS_ADDR_AREA_REG(0x00)Retrieve the address in register.
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Retrieve the address in DataFlash area.
+ * @param[in] addr_type The address type that is type of the address to be retrieved. + * | macro | description | + * |:------------------------- |:------------------ | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public address. | + * | BLE_GAP_ADDR_RAND(0x01) | Random address. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetRand(uint8_t rand_size) + * @brief This function generates 4-16 bytes of random number used in creating keys. + * @details The result of this API call is notified in BLE_VS_EVENT_GET_RAND event. + * @param[in] rand_size Length of the random number (byte).\n + * The valid range is 4<=rand_size<=16. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetRand(uint8_t rand_size); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void) + * @brief This function starts the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of + * the state transition of TxFlow. + * @details If the number of the available transmission packet buffers is the following, + * BLE_VS_EVENT_TX_FLOW_STATE_CHG event notifies the application layer of the state of the TxFlow. + * - The number of the available transmission packet buffers is less than Low Water Mark. + * - The number of the available transmission packet buffers is more than High Water Mark. + * The result of this API call is returned by a return value. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void) + * @brief This function stops the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of + * the state transition of TxFlow. + * @details The result of this API call is returned by a return value. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num) + * @brief This function retrieves the number of the available transmission packet buffers. + * @details The maximum number of the available buffers is 10.\n + * The result of this API call is returned by a return value. + * @param[out] p_buffer_num The number of the available transmission packet buffers. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_buffer_num parameter is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm) + * @brief This function sets the threshold for notifying the application layer of the TxFlow state. + * @details Call this function before the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) has been started + * by R_BLE_VS_StartTxFlowEvtNtf(). \n + * The result is returned from this API.\n + * Vendor Specific API supports the flow control function(TxFlow) for the transmission + * on L2CAP fixed channel in Basic Mode such as GATT.\n + * Host stack has 10 transmission packet buffers for the transmission.\n + * When the number of the available transmission packet buffers has been less than Low Water Mark, + * the state of TxFlow transmits into the TxFlow OFF state from the TxFlow ON state + * that is the initial state and host stack notifies the application layer of + * timing to stop packet transmission.\n + * When host stack has sent the transmission packets to Controller and the number of the available + * transmission packet buffers has been more than High Water Mark, the state of TxFlow transmits into + * the TxFlow ON state from the TxFlow OFF state and host stack notifies the application layer of + * timing to restart packet transmission.\n + * It is possible to perform flow control on a fixed channel by using the event notification. + * @param[in] tx_queue_lwm Low Water Mark. + * Set 0-9 less than tx_queue_hwm to the parameter. + * When the number of the available transmission packet buffers has been less than the value + * specified by the tx_queue_lwm parameter, host stack notifies the application layer of + * the timing to stop packet transmission. + * @param[in] tx_queue_hwm High Water Mark. + * Set 1-10 more than tx_queue_lwm to the parameter. + * When the number of the available transmission packet buffers has been more than + * the value specified by the tx_queue_hwm parameter, host stack notifies + * the application layer of the timing to restart packet transmission. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The tx_queue_lwm parameter or the tx_queue_hwm parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm); + +/*@}*/ + +/*******************************************************************************************************************//** + * @} (end addtogroup BLE_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h new file mode 100644 index 0000000000..6e86d0e2fb --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h @@ -0,0 +1,356 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CGC_API_H +#define R_CGC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup CGC_API CGC Interface + * @brief Interface for clock generation. + * + * @section CGC_API_SUMMARY Summary + * + * The CGC interface provides the ability to configure and use all of the CGC module's capabilities. Among the + * capabilities is the selection of several clock sources to use as the system clock source. Additionally, the + * system clocks can be divided down to provide a wide range of frequencies for various system and peripheral needs. + * + * Clock stability can be checked and clocks may also be stopped to save power when not needed. The API has a function + * to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect + * when the main oscillator has stopped, with the option of calling a user provided callback function. + * + * The CGC interface is implemented by: + * - @ref CGC + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Version Number of API. */ +#define CGC_API_VERSION_MAJOR (1U) +#define CGC_API_VERSION_MINOR (0U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events that can trigger a callback function */ +typedef enum e_cgc_event +{ + CGC_EVENT_OSC_STOP_DETECT ///< Oscillator stop detection has caused the event +} cgc_event_t; + +/** Callback function parameter data */ +typedef struct st_cgc_callback_args +{ + cgc_event_t event; ///< The event can be used to identify what caused the callback + void const * p_context; ///< Placeholder for user data +} cgc_callback_args_t; + +/** System clock source identifiers - The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock + * divider */ +typedef enum e_cgc_clock +{ + CGC_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + CGC_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + CGC_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + CGC_CLOCK_MAIN_OSC = 3, ///< The main oscillator + CGC_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + CGC_CLOCK_PLL = 5, ///< The PLL oscillator +} cgc_clock_t; + +/** PLL divider values */ +typedef enum e_cgc_pll_div +{ + CGC_PLL_DIV_1 = 0, ///< PLL divider of 1 + CGC_PLL_DIV_2 = 1, ///< PLL divider of 2 + CGC_PLL_DIV_3 = 2, ///< PLL divider of 3 (S7, S5 only) + CGC_PLL_DIV_4 = 3, ///< PLL divider of 4 (S3 only) +} cgc_pll_div_t; + +/** PLL multiplier values */ +typedef enum e_cgc_pll_mul +{ + CGC_PLL_MUL_8_0 = 0xF, ///< PLL multiplier of 8.0 + CGC_PLL_MUL_9_0 = 0x11, ///< PLL multiplier of 9.0 + CGC_PLL_MUL_10_0 = 0x13, ///< PLL multiplier of 10.0 + CGC_PLL_MUL_10_5 = 0x14, ///< PLL multiplier of 10.5 + CGC_PLL_MUL_11_0 = 0x15, ///< PLL multiplier of 11.0 + CGC_PLL_MUL_11_5 = 0x16, ///< PLL multiplier of 11.5 + CGC_PLL_MUL_12_0 = 0x17, ///< PLL multiplier of 12.0 + CGC_PLL_MUL_12_5 = 0x18, ///< PLL multiplier of 12.5 + CGC_PLL_MUL_13_0 = 0x19, ///< PLL multiplier of 13.0 + CGC_PLL_MUL_13_5 = 0x1A, ///< PLL multiplier of 13.5 + CGC_PLL_MUL_14_0 = 0x1B, ///< PLL multiplier of 14.0 + CGC_PLL_MUL_14_5 = 0x1D, ///< PLL multiplier of 14.5 + CGC_PLL_MUL_15_0 = 0x1D, ///< PLL multiplier of 15.0 + CGC_PLL_MUL_15_5 = 0x1E, ///< PLL multiplier of 15.5 + CGC_PLL_MUL_16_0 = 0x1F, ///< PLL multiplier of 16.0 + CGC_PLL_MUL_16_5 = 0x20, ///< PLL multiplier of 16.5 + CGC_PLL_MUL_17_0 = 0x21, ///< PLL multiplier of 17.0 + CGC_PLL_MUL_17_5 = 0x22, ///< PLL multiplier of 17.5 + CGC_PLL_MUL_18_0 = 0x23, ///< PLL multiplier of 18.0 + CGC_PLL_MUL_18_5 = 0x24, ///< PLL multiplier of 18.5 + CGC_PLL_MUL_19_0 = 0x25, ///< PLL multiplier of 19.0 + CGC_PLL_MUL_19_5 = 0x26, ///< PLL multiplier of 19.5 + CGC_PLL_MUL_20_0 = 0x27, ///< PLL multiplier of 20.0 + CGC_PLL_MUL_20_5 = 0x28, ///< PLL multiplier of 20.5 + CGC_PLL_MUL_21_0 = 0x29, ///< PLL multiplier of 21.0 + CGC_PLL_MUL_21_5 = 0x2A, ///< PLL multiplier of 21.5 + CGC_PLL_MUL_22_0 = 0x2B, ///< PLL multiplier of 22.0 + CGC_PLL_MUL_22_5 = 0x2C, ///< PLL multiplier of 22.5 + CGC_PLL_MUL_23_0 = 0x2D, ///< PLL multiplier of 23.0 + CGC_PLL_MUL_23_5 = 0x2E, ///< PLL multiplier of 23.5 + CGC_PLL_MUL_24_0 = 0x2F, ///< PLL multiplier of 24.0 + CGC_PLL_MUL_24_5 = 0x30, ///< PLL multiplier of 24.5 + CGC_PLL_MUL_25_0 = 0x31, ///< PLL multiplier of 25.0 + CGC_PLL_MUL_25_5 = 0x32, ///< PLL multiplier of 25.5 + CGC_PLL_MUL_26_0 = 0x33, ///< PLL multiplier of 26.0 + CGC_PLL_MUL_26_5 = 0x34, ///< PLL multiplier of 26.5 + CGC_PLL_MUL_27_0 = 0x35, ///< PLL multiplier of 27.0 + CGC_PLL_MUL_27_5 = 0x36, ///< PLL multiplier of 27.5 + CGC_PLL_MUL_28_0 = 0x37, ///< PLL multiplier of 28.0 + CGC_PLL_MUL_28_5 = 0x38, ///< PLL multiplier of 28.5 + CGC_PLL_MUL_29_0 = 0x39, ///< PLL multiplier of 29.0 + CGC_PLL_MUL_29_5 = 0x3A, ///< PLL multiplier of 29.5 + CGC_PLL_MUL_30_0 = 0x3B, ///< PLL multiplier of 30.0 + CGC_PLL_MUL_31_0 = 0x3D, ///< PLL multiplier of 31.0 +} cgc_pll_mul_t; + +/** System clock divider vlues - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 +} cgc_sys_clock_div_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ +typedef struct st_cgc_pll_cfg +{ + cgc_clock_t source_clock; ///< PLL source clock (main oscillator or HOCO) + cgc_pll_div_t divider; ///< PLL divider + cgc_pll_mul_t multiplier; ///< PLL multiplier +} cgc_pll_cfg_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet + * functions. */ +typedef union u_cgc_divider_cfg +{ + uint32_t sckdivcr_w; ///< (@ 0x4001E020) System clock Division control register + + /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in FSP code. */ + struct + { + cgc_sys_clock_div_t pclkd_div : 3; ///< Divider value for PCLKD + uint32_t : 1; + cgc_sys_clock_div_t pclkc_div : 3; ///< Divider value for PCLKC + uint32_t : 1; + cgc_sys_clock_div_t pclkb_div : 3; ///< Divider value for PCLKB + uint32_t : 1; + cgc_sys_clock_div_t pclka_div : 3; ///< Divider value for PCLKA + uint32_t : 1; + cgc_sys_clock_div_t bclk_div : 3; ///< Divider value for BCLK + uint32_t : 5; + cgc_sys_clock_div_t iclk_div : 3; ///< Divider value for ICLK + uint32_t : 1; + cgc_sys_clock_div_t fclk_div : 3; ///< Divider value for FCLK + }; +} cgc_divider_cfg_t; + +/** USB clock divider values */ +typedef enum e_cgc_usb_clock_div +{ + CGC_USB_CLOCK_DIV_3 = 2, ///< Divide USB source clock by 3 + CGC_USB_CLOCK_DIV_4 = 3, ///< Divide USB source clock by 4 + CGC_USB_CLOCK_DIV_5 = 4, ///< Divide USB source clock by 5 +} cgc_usb_clock_div_t; + +/** Clock options */ +typedef enum e_cgc_clock_change +{ + CGC_CLOCK_CHANGE_START = 0, ///< Start the clock + CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock + CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock +} cgc_clock_change_t; + +/** CGC control block. Allocate an instance specific control block to pass into the CGC API calls. + * @par Implemented as + * - cgc_instance_ctrl_t + */ +typedef void cgc_ctrl_t; + +/** Configuration options. */ +typedef struct s_cgc_cfg +{ + void (* p_callback)(cgc_callback_args_t * p_args); +} cgc_cfg_t; + +/** Clock configuration */ +typedef struct st_cgc_clocks_cfg +{ + cgc_clock_t system_clock; ///< System clock source enumeration + cgc_pll_cfg_t pll_cfg; ///< PLL configuration structure + cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure + cgc_clock_change_t loco_state; ///< State of LOCO + cgc_clock_change_t moco_state; ///< State of MOCO + cgc_clock_change_t hoco_state; ///< State of HOCO + cgc_clock_change_t mainosc_state; ///< State of Main oscillator + cgc_clock_change_t pll_state; ///< State of PLL +} cgc_clocks_cfg_t; + +/** CGC functions implemented at the HAL layer follow this API. */ +typedef struct +{ + /** Initial configuration + * @par Implemented as + * - @ref R_CGC_Open() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration + */ + fsp_err_t (* open)(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg); + + /** Configure all system clocks. + * @par Implemented as + * - @ref R_CGC_ClocksCfg() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_clock_cfg Pointer to desired configuration of system clocks + */ + fsp_err_t (* clocksCfg)(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg); + + /** Start a clock. + * @par Implemented as + * - @ref R_CGC_ClockStart() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to start + * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL + */ + fsp_err_t (* clockStart)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_pll_cfg_t const * const p_pll_cfg); + + /** Stop a clock. + * @par Implemented as + * - @ref R_CGC_ClockStop() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source The clock source to stop + */ + fsp_err_t (* clockStop)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Check the stability of the selected clock. + * @par Implemented as + * - @ref R_CGC_ClockCheck() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Which clock source to check for stability + */ + fsp_err_t (* clockCheck)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Set the system clock. + * @par Implemented as + * - @ref R_CGC_SystemClockSet() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to set as system clock + * @param[in] p_divider_cfg Pointer to the clock divider configuration + */ + fsp_err_t (* systemClockSet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_divider_cfg_t const * const p_divider_cfg); + + /** Get the system clock information. + * @par Implemented as + * - @ref R_CGC_SystemClockGet() + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_clock_source Returns the current system clock + * @param[out] p_divider_cfg Returns the current system clock dividers + */ + fsp_err_t (* systemClockGet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t * const p_clock_source, + cgc_divider_cfg_t * const p_divider_cfg); + + /** Enable and optionally register a callback for Main Oscillator stop detection. + * @par Implemented as + * - @ref R_CGC_OscStopDetectEnable() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_callback Callback function that will be called by the NMI interrupt when an oscillation stop is + * detected. If the second argument is "false", then this argument can be NULL. + * @param[in] enable Enable/disable Oscillation Stop Detection + */ + fsp_err_t (* oscStopDetectEnable)(cgc_ctrl_t * const p_ctrl); + + /** Disable Main Oscillator stop detection. + * @par Implemented as + * - @ref R_CGC_OscStopDetectDisable() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopDetectDisable)(cgc_ctrl_t * const p_ctrl); + + /** Clear the oscillator stop detection flag. + * @par Implemented as + * - @ref R_CGC_OscStopStatusClear() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl); + + /** Close the CGC driver. + * @par Implemented as + * - @ref R_CGC_Close() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* close)(cgc_ctrl_t * const p_ctrl); + + /** Gets the CGC driver version. + * @par Implemented as + * - @ref R_CGC_VersionGet() + * @param[out] p_version Code and API version used + */ + fsp_err_t (* versionGet)(fsp_version_t * p_version); +} cgc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_cgc_instance +{ + cgc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + cgc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + cgc_api_t const * p_api; ///< Pointer to the API structure for this instance +} cgc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CGC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CGC_API_H diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h new file mode 100644 index 0000000000..604616768c --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup EXTERNAL_IRQ_API External IRQ Interface + * @brief Interface for detecting external interrupts. + * + * @section EXTERNAL_IRQ_API_Summary Summary + * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an + * external IRQ pin. + * + * The External IRQ Interface can be implemented by: + * - @ref ICU + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_EXTERNAL_IRQ_API_H +#define R_EXTERNAL_IRQ_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#define EXTERNAL_IRQ_API_VERSION_MAJOR (1U) ///< EXTERNAL IRQ API version number (Major) +#define EXTERNAL_IRQ_API_VERSION_MINOR (0U) ///< EXTERNAL IRQ API version number (Minor) + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Callback function parameter data */ +typedef struct st_external_irq_callback_args +{ + /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */ + void const * p_context; + uint32_t channel; ///< The physical hardware channel that caused the interrupt. +} external_irq_callback_args_t; + +/** Condition that will trigger an interrupt when detected. */ +typedef enum e_external_irq_trigger +{ + EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger + EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger + EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger + EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger +} external_irq_trigger_t; + +/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger + * conditions that are shorter than 3 periods of the filter clock. + */ +typedef enum e_external_irq_pclk_div +{ + EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1 + EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8 + EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32 + EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64 +} external_irq_pclk_div_t; + +/** User configuration structure, used in open function */ +typedef struct st_external_irq_cfg +{ + uint8_t channel; ///< Hardware channel used. + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< NVIC interrupt number assigned to this instance + external_irq_trigger_t trigger; ///< Trigger setting. + external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting. + bool filter_enable; ///< Digital filter enable/disable setting. + + /** Callback provided external input trigger occurs. */ + void (* p_callback)(external_irq_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< External IRQ hardware dependent configuration. +} external_irq_cfg_t; + +/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. + * @par Implemented as + * - icu_instance_ctrl_t + */ +typedef void external_irq_ctrl_t; + +/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */ +typedef struct st_external_irq_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_ICU_ExternalIrqOpen() + * + * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. + */ + fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); + + /** Enable callback when an external trigger condition occurs. + * @par Implemented as + * - @ref R_ICU_ExternalIrqEnable() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); + + /** Disable callback when external trigger condition occurs. + * @par Implemented as + * - @ref R_ICU_ExternalIrqDisable() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); + + /** Allow driver to be reconfigured. May reduce power consumption. + * @par Implemented as + * - @ref R_ICU_ExternalIrqClose() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl); + + /** Get version and store it in provided pointer p_version. + * @par Implemented as + * - @ref R_ICU_ExternalIrqVersionGet() + * + * @param[out] p_version Code and API version used. */ + fsp_err_t (* versionGet)(fsp_version_t * const p_version); +} external_irq_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_external_irq_instance +{ + external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance +} external_irq_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end defgroup EXTERNAL_IRQ_API) + **********************************************************************************************************************/ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h new file mode 100644 index 0000000000..417985d959 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h @@ -0,0 +1,358 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup FLASH_API Flash Interface + * @brief Interface for the Flash Memory. + * + * @section FLASH_API_SUMMARY Summary + * + * The Flash interface provides the ability to read, write, erase, and blank check the code flash and data flash + * regions. + * + * The Flash interface is implemented by: + * - @ref FLASH_LP + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_FLASH_API_H +#define R_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/* Version Number of API. */ +#define FLASH_API_VERSION_MAJOR (1U) +#define FLASH_API_VERSION_MINOR (0U) + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Result type for certain operations */ +typedef enum e_flash_result +{ + FLASH_RESULT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_NOT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_BGO_ACTIVE ///< Flash is configured for BGO mode. Result is returned in callback. +} flash_result_t; + +/** Parameter for specifying the startup area swap being requested by startupAreaSelect() */ +typedef enum e_flash_startup_area_swap +{ + FLASH_STARTUP_AREA_BTFLG = 0, ///< Startup area will be set based on the value of the BTFLG + FLASH_STARTUP_AREA_BLOCK0 = 0x2, ///< Startup area will be set to Block 0 + FLASH_STARTUP_AREA_BLOCK1 = 0x3, ///< Startup area will be set to Block 1 +} flash_startup_area_swap_t; + +/** Event types returned by the ISR callback when used in Data Flash BGO mode */ +typedef enum e_flash_event +{ + FLASH_EVENT_ERASE_COMPLETE, ///< Erase operation successfully completed + FLASH_EVENT_WRITE_COMPLETE, ///< Write operation successfully completed + FLASH_EVENT_BLANK, ///< Blank check operation successfully completed. Specified area is blank + FLASH_EVENT_NOT_BLANK, ///< Blank check operation successfully completed. Specified area is NOT blank + FLASH_EVENT_ERR_DF_ACCESS, ///< Data Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CF_ACCESS, ///< Code Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CMD_LOCKED, ///< Operation failed, FCU is in Locked state (often result of an illegal command) + FLASH_EVENT_ERR_FAILURE, ///< Erase or Program Operation failed + FLASH_EVENT_ERR_ONE_BIT ///< A 1-bit error has been corrected when reading the flash memory area by the sequencer. +} flash_event_t; + +/** ID Code Modes for writing to ID code registers */ +typedef enum e_flash_id_code_mode +{ + FLASH_ID_CODE_MODE_UNLOCKED = 0, ///< ID code is ignored + FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT = 0xC000U, ///< ID code is checked. All erase is available. + FLASH_ID_CODE_MODE_LOCKED = 0x8000U ///< ID code is checked. +} flash_id_code_mode_t; + +/** Flash status */ +typedef enum e_flash_status +{ + FLASH_STATUS_IDLE, ///< The flash is idle. + FLASH_STATUS_BUSY ///< The flash is currently processing a command. +} flash_status_t; + +/** Flash block details stored in factory flash. */ +typedef struct st_flash_block_info +{ + uint32_t block_section_st_addr; ///< Starting address for this block section (blocks of this size) + uint32_t block_section_end_addr; ///< Ending address for this block section (blocks of this size) + uint32_t block_size; ///< Flash erase block size + uint32_t block_size_write; ///< Flash write block size +} flash_block_info_t; + +/** Flash block details */ +typedef struct st_flash_regions +{ + uint32_t num_regions; ///< Length of block info array + flash_block_info_t const * p_block_array; ///< Block info array base address +} flash_regions_t; + +/** Information about the flash blocks */ +typedef struct st_flash_info +{ + flash_regions_t code_flash; ///< Information about the code flash regions + flash_regions_t data_flash; ///< Information about the code flash regions +} flash_info_t; + +/** Flash control block. Allocate an instance specific control block to pass into the flash API calls. + * @par Implemented as + * - flash_lp_instance_ctrl_t + * - flash_hp_instance_ctrl_t + */ +typedef void flash_ctrl_t; + +/** Callback function parameter data */ +typedef struct st_flash_user_cb_data +{ + flash_event_t event; ///< Event can be used to identify what caused the callback (flash ready or error). + void const * p_context; ///< Placeholder for user data. Set in @ref flash_api_t::open function in::flash_cfg_t. +} flash_callback_args_t; + +/** FLASH Configuration */ +typedef struct st_flash_cfg +{ + bool data_flash_bgo; ///< True if BGO (Background Operation) is enabled for Data Flash. + + /* Configuration for FLASH Event processing */ + void (* p_callback)(flash_callback_args_t * p_args); ///< Callback provided when a Flash interrupt ISR occurs. + + /* Pointer to FLASH peripheral specific configuration */ + void const * p_extend; ///< FLASH hardware dependent configuration + void const * p_context; ///< Placeholder for user data. Passed to user callback in @ref flash_callback_args_t. + uint8_t ipl; ///< Flash ready interrupt priority + IRQn_Type irq; ///< Flash ready interrupt number + uint8_t err_ipl; ///< Flash error interrupt priority (unused in r_flash_lp) + IRQn_Type err_irq; ///< Flash error interrupt number (unused in r_flash_lp) +} flash_cfg_t; + +/** Shared Interface definition for FLASH */ +typedef struct st_flash_api +{ + /** Open FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Open() + * - @ref R_FLASH_HP_Open() + * + * @param[out] p_ctrl Pointer to FLASH device control. Must be declared by user. Value set here. + * @param[in] flash_cfg_t Pointer to FLASH configuration structure. All elements of this structure + * must be set by the user. + */ + fsp_err_t (* open)(flash_ctrl_t * const p_ctrl, flash_cfg_t const * const p_cfg); + + /** Write FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Write() + * - @ref R_FLASH_HP_Write() + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] src_address Address of the buffer containing the data to write to Flash. + * @param[in] flash_address Code Flash or Data Flash address to write. The address must be on a + * programming line boundary. + * @param[in] num_bytes The number of bytes to write. This number must be a multiple + * of the programming size. For Code Flash this is FLASH_MIN_PGM_SIZE_CF. + * For Data Flash this is FLASH_MIN_PGM_SIZE_DF. + * @warning Specifying a number that is not a multiple of the programming size + * will result in SF_FLASH_ERR_BYTES being returned and no data written. + */ + fsp_err_t (* write)(flash_ctrl_t * const p_ctrl, uint32_t const src_address, uint32_t const flash_address, + uint32_t const num_bytes); + + /** Erase FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Erase() + * - @ref R_FLASH_HP_Erase() + * + * @param[in] p_ctrl Control for the FLASH device. + * @param[in] address The block containing this address is the first block erased. + * @param[in] num_blocks Specifies the number of blocks to be erased, the starting block determined + * by the block_erase_address. + */ + fsp_err_t (* erase)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_blocks); + + /** Blank check FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_BlankCheck() + * - @ref R_FLASH_HP_BlankCheck() + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * See the specific handler for details. + * @param[out] p_blank_check_result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. In this case FLASH_RESULT_BGO_ACTIVE will + * be returned in p_blank_check_result. + */ + fsp_err_t (* blankCheck)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_bytes, + flash_result_t * const p_blank_check_result); + + /** Close FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_InfoGet() + * - @ref R_FLASH_HP_InfoGet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_info Pointer to FLASH info structure. + */ + fsp_err_t (* infoGet)(flash_ctrl_t * const p_ctrl, flash_info_t * const p_info); + + /** Close FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Close() + * - @ref R_FLASH_HP_Close() + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* close)(flash_ctrl_t * const p_ctrl); + + /** Get Status for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_StatusGet() + * - @ref R_FLASH_HP_StatusGet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_ctrl Pointer to the current flash status. + */ + fsp_err_t (* statusGet)(flash_ctrl_t * const p_ctrl, flash_status_t * const p_status); + + /** Set Access Window for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_AccessWindowSet() + * - @ref R_FLASH_HP_AccessWindowSet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. This address will not be + * within the access window. + */ + fsp_err_t (* accessWindowSet)(flash_ctrl_t * const p_ctrl, uint32_t const start_addr, uint32_t const end_addr); + + /** Clear any existing Code Flash access window for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_AccessWindowClear() + * - @ref R_FLASH_HP_AccessWindowClear() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + */ + fsp_err_t (* accessWindowClear)(flash_ctrl_t * const p_ctrl); + + /** Set ID Code for FLASH device. Setting the ID code can restrict access to the device. The ID code will be + * required to connect to the device. Bits 126 and 127 are set based on the mode. + * + * For example, uint8_t id_bytes[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + * 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x00}; + * with mode FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT + * will result in an ID code of 00112233445566778899aabbccddeec0 + * + * With mode FLASH_ID_CODE_MODE_LOCKED, it + * will result in an ID code of 00112233445566778899aabbccddee80 + * + * @par Implemented as + * - @ref R_FLASH_LP_IdCodeSet() + * - @ref R_FLASH_HP_IdCodeSet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] p_id_bytes Ponter to the ID Code to be written. + * @param[in] mode Mode used for checking the ID code. + */ + fsp_err_t (* idCodeSet)(flash_ctrl_t * const p_ctrl, uint8_t const * const p_id_bytes, flash_id_code_mode_t mode); + + /** Reset function for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Reset() + * - @ref R_FLASH_HP_Reset() + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* reset)(flash_ctrl_t * const p_ctrl); + + /** Update Flash clock frequency (FCLK) and recalculate timeout values + * @par Implemented as + * - @ref R_FLASH_LP_UpdateFlashClockFreq() + * - @ref R_FLASH_HP_UpdateFlashClockFreq() + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* updateFlashClockFreq)(flash_ctrl_t * const p_ctrl); + + /** Select which block - Default (Block 0) or Alternate (Block 1) is used as the start-up area block. + * @par Implemented as + * - @ref R_FLASH_LP_StartUpAreaSelect() + * - @ref R_FLASH_HP_StartUpAreaSelect() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] swap_type FLASH_STARTUP_AREA_BLOCK0, FLASH_STARTUP_AREA_BLOCK1 or FLASH_STARTUP_AREA_BTFLG. + * @param[in] is_temporary True or false. See table below. + * + * | swap_type | is_temporary | Operation | + * |-----------------------|-----------------|-------------| + * | FLASH_STARTUP_AREA_BLOCK0 | false | On next reset Startup area will be Block 0. | + * | FLASH_STARTUP_AREA_BLOCK1 | true | Startup area is immediately, but temporarily switched to Block 1. | + * | FLASH_STARTUP_AREA_BTFLG | true | Startup area is immediately, but temporarily switched to the Block determined by the Configuration BTFLG. | + * + */ + fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type, + bool is_temporary); + + /** Get Flash driver version. + * @par Implemented as + * - @ref R_FLASH_LP_VersionGet() + * - @ref R_FLASH_HP_VersionGet() + * + * @param[out] p_version Returns version. + */ + fsp_err_t (* versionGet)(fsp_version_t * p_version); +} flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_flash_instance +{ + flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} flash_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup FLASH_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h new file mode 100644 index 0000000000..245774889a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,362 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * IOPORT Interface description: @ref IOPORT + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IOPORT_API_VERSION_MAJOR (1U) +#define IOPORT_API_VERSION_MINOR (0U) + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size on this device + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Marks end of enum - used by parameter checking */ + IOPORT_PERIPHERAL_END +} ioport_peripheral_t; + +/** Superset of Ethernet channels. */ +typedef enum e_ioport_eth_ch +{ + IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0 + IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1 + IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking +} ioport_ethernet_channel_t; + +/** Superset of Ethernet PHY modes. */ +typedef enum e_ioport_eth_mode +{ + IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII + IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII + IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking +} ioport_ethernet_mode_t; + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high + IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up + IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput + IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port + IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin +} ioport_cfg_options_t; + +/* PFS writing enable/disable. */ +typedef enum e_ioport_pwpr +{ + IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access + IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access +} ioport_pwpr_t; + +/** Pin identifier and pin PFS pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + * @par Implemented as + * - ioport_instance_ctrl_t + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * @par Implemented as + * - @ref R_IOPORT_Open() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * @par Implemented as + * - @ref R_IOPORT_Close() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * @par Implemented as + * - @ref R_IOPORT_PinsCfg() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * @par Implemented as + * - @ref R_IOPORT_PinCfg() + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * @par Implemented as + * - @ref R_IOPORT_PinEventInputRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * @par Implemented as + * - @ref R_IOPORT_PinEventOutputWrite() + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Configure the PHY mode of the Ethernet channels. + * @par Implemented as + * - @ref R_IOPORT_EthernetModeCfg() + * @param[in] channel Channel configuration will be set for. + * @param[in] mode PHY mode to set the channel to. + */ + fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel, + ioport_ethernet_mode_t mode); + + /** Read level of a pin. + * @par Implemented as + * - @ref R_IOPORT_PinRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * @par Implemented as + * - @ref R_IOPORT_PinWrite() + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortDirectionSet() + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input). + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventInputRead() + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventOutputWrite() + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * @par Implemented as + * - @ref R_IOPORT_PortRead() + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortWrite() + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + + /** Return the version of the IOPort driver. + * @par Implemented as + * - @ref R_IOPORT_VersionGet() + * @param[out] p_data Memory address to return version information to. + */ + fsp_err_t (* versionGet)(fsp_version_t * p_data); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h new file mode 100644 index 0000000000..5703366216 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_TIMER_API_H +#define R_TIMER_API_H + +/*******************************************************************************************************************//** + * @defgroup TIMER_API Timer Interface + * @ingroup RENESAS_INTERFACES + * @brief Interface for timer functions. + * + * @section TIMER_API_SUMMARY Summary + * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output, + * and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered. + * + * If an instance supports output compare mode, it is provided in the extension configuration + * timer_on__cfg_t defined in r_.h. + * + * Implemented by: + * - @ref GPT + * - @ref AGT + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standard violation. */ +#define TIMER_API_VERSION_MAJOR (1U) +#define TIMER_API_VERSION_MINOR (1U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events that can trigger a callback function */ +typedef enum e_timer_event +{ + TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around + TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only) + TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A + TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B + TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only +} timer_event_t; + +/** Timer variant types. */ +typedef enum e_timer_variant +{ + TIMER_VARIANT_32_BIT, ///< 32-bit timer + TIMER_VARIANT_16_BIT ///< 16-bit timer +} timer_variant_t; + +/** Callback function parameter data */ +typedef struct st_timer_callback_args +{ + /** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */ + void const * p_context; + timer_event_t event; ///< The event can be used to identify what caused the callback. + + /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */ + uint32_t capture; +} timer_callback_args_t; + +/** Timer control block. Allocate an instance specific control block to pass into the timer API calls. + * @par Implemented as + * - gpt_instance_ctrl_t + * - agt_instance_ctrl_t + */ +typedef void timer_ctrl_t; + +/** Possible status values returned by @ref timer_api_t::statusGet. */ +typedef enum e_timer_state +{ + TIMER_STATE_STOPPED = 0, ///< Timer is stopped + TIMER_STATE_COUNTING = 1, ///< Timer is running +} timer_state_t; + +/** Timer operational modes */ +typedef enum e_timer_mode +{ + TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses. + TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses. + TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output. + TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output. + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output. +} timer_mode_t; + +/** Direction of timer count */ +typedef enum e_timer_direction +{ + TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up + TIMER_DIRECTION_UP = 1 ///< Timer count goes down +} timer_direction_t; + +/** PCLK divisors */ +typedef enum e_timer_source_div +{ + TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 + TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2 + TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4 + TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8 + TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16 + TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32 + TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64 + TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128 + TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256 + TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024 +} timer_source_div_t; + +/** Timer information structure to store various information for a timer resource */ +typedef struct st_timer_info +{ + timer_direction_t count_direction; ///< Clock counting direction of the timer. + uint32_t clock_frequency; ///< Clock frequency of the timer counter. + + /** Period in raw timer counts. + * @note For triangle wave PWM modes, the full period is double this value. + */ + uint32_t period_counts; +} timer_info_t; + +/** Current timer status. */ +typedef struct st_timer_status +{ + uint32_t counter; ///< Current counter value + timer_state_t state; ///< Current timer state (running or stopped) +} timer_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_timer_cfg +{ + timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t + + /* Period in raw timer counts. + * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period. + */ + uint32_t period_counts; ///< Period in raw timer counts + timer_source_div_t source_div; ///< Source clock divider + uint32_t duty_cycle_counts; ///< Duty cycle in counts + + /** Select a channel corresponding to the channel number of the hardware. */ + uint8_t channel; + uint8_t cycle_end_ipl; ///< Cycle end interrupt priority + IRQn_Type cycle_end_irq; ///< Cycle end interrupt + + /** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(timer_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} timer_cfg_t; + +/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */ +typedef struct st_timer_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_GPT_Open() + * - @ref R_AGT_Open() + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); + + /** Start the counter. + * @par Implemented as + * - @ref R_GPT_Start() + * - @ref R_AGT_Start() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* start)(timer_ctrl_t * const p_ctrl); + + /** Stop the counter. + * @par Implemented as + * - @ref R_GPT_Stop() + * - @ref R_AGT_Stop() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl); + + /** Reset the counter to the initial value. + * @par Implemented as + * - @ref R_GPT_Reset() + * - @ref R_AGT_Reset() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl); + + /** Enables input capture. + * @par Implemented as + * - @ref R_GPT_Enable() + * - @ref R_AGT_Enable() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl); + + /** Disables input capture. + * @par Implemented as + * - @ref R_GPT_Disable() + * - @ref R_AGT_Disable() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl); + + /** Set the time until the timer expires. See implementation for details of period update timing. + * + * @par Implemented as + * - @ref R_GPT_PeriodSet() + * - @ref R_AGT_PeriodSet() + * + * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in + * @ref timer_api_t::open. + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_period Time until timer should expire. + */ + fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period); + + /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is + * reflected after the next timer expiration. + * + * @par Implemented as + * - @ref R_GPT_DutyCycleSet() + * - @ref R_AGT_DutyCycleSet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] duty_cycle_counts Time until duty cycle should expire. + * @param[in] pin Which output pin to update. See implementation for details. + */ + fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); + + /** Stores timer information in p_info. + * @par Implemented as + * - @ref R_GPT_InfoGet() + * - @ref R_AGT_InfoGet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_info Collection of information for this timer. + */ + fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); + + /** Get the current counter value and timer state and store it in p_status. + * @par Implemented as + * - @ref R_GPT_StatusGet() + * - @ref R_AGT_StatusGet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_status Current status of this timer. + */ + fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); + + /** Allows driver to be reconfigured and may reduce power consumption. + * @par Implemented as + * - @ref R_GPT_Close() + * - @ref R_AGT_Close() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* close)(timer_ctrl_t * const p_ctrl); + + /** Get version and store it in provided pointer p_version. + * @par Implemented as + * - @ref R_GPT_VersionGet() + * - @ref R_AGT_VersionGet() + * + * @param[out] p_version Code and API version used. + */ + fsp_err_t (* versionGet)(fsp_version_t * const p_version); +} timer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_timer_instance +{ + timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + timer_api_t const * p_api; ///< Pointer to the API structure for this instance +} timer_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup TIMER_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h new file mode 100644 index 0000000000..d41cc08f3b --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h @@ -0,0 +1,867 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RM_BLE_ABS_API_H +#define RM_BLE_ABS_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup BLE_ABS_API BLE ABS Interface + * @brief Interface for Bluetooth Low Energy Abstraction functions. + * + * @section BLE_ABS_API_Summary Summary + * The BLE ABS interface for the Bluetooth Low Energy Abstraction (BLE ABS) peripheral provides Bluetooth Low Energy Abstraction functionality. + * + * The Bluetooth Low Energy Abstraction interface can be implemented by: + * - @ref BLE_ABS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_ble_api.h" +#include "r_flash_api.h" +#include "r_timer_api.h" + +#include "fsp_common_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BLE_ABS_API_VERSION_MAJOR (1U) +#define BLE_ABS_API_VERSION_MINOR (0U) + +#define BLE_ABS_ADVERTISING_PHY_LEGACY (0x00) ///< Non-Connectable Legacy Advertising phy setting. + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Advertising Filter Policy */ +typedef enum e_ble_abs_advertising_filter +{ + BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY = 0x00, ///< Receive a connect request from all devices. + BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST = 0x01, ///< Receive a connect request from only the devices registered in White List. +} ble_abs_advertising_filter_t; + +#define BLE_BD_ADDR_LEN (0x06) + +/** st_ble_device_address is the type of bluetooth device address(BD_ADDR). */ +typedef struct st_ble_device_address +{ + uint8_t addr[BLE_BD_ADDR_LEN]; ///< bluetooth device address. + uint8_t type; ///< the type of bluetooth device address. +} ble_device_address_t; + +/** ble_gap_application_callback_t is the GAP Event callback function type. */ +typedef void (* ble_gap_application_callback_t)(uint16_t event_type, ble_status_t event_result, + st_ble_evt_data_t * p_event_data); + +/** ble_vendor_specific_application_callback_t is the Vendor Specific Event callback function type. */ +typedef void (* ble_vendor_specific_application_callback_t)(uint16_t event_type, ble_status_t event_result, + st_ble_vs_evt_data_t * p_event_data); + +/** ble_gatt_server_application_callback_t is the GATT Server Event callback function type. */ +typedef void (* ble_gatt_server_application_callback_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gatts_evt_data_t * p_event_data); + +/** ble_gatt_client_application_callback_t is the GATT Server Event callback function type. */ +typedef void (* ble_gatt_client_application_callback_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gattc_evt_data_t * p_event_data); + +/** ble_gap_connection_parameter_t is Connection parameters included in connection interval, slave latency, supervision timeout, ce length. */ +typedef struct st_ble_gap_connection_parameter +{ + uint16_t conn_intv_min; ///< Minimum connection interval. + uint16_t conn_intv_max; ///< Maximum connection interval. + uint16_t conn_latency; ///< Slave latency. + uint16_t sup_to; ///< Supervision timeout. + uint16_t min_ce_length; ///< Minimum CE Length. + uint16_t max_ce_length; ///< Maximum CE Length. +} ble_gap_connection_parameter_t; + +/** ble_gap_connection_phy_parameter_t is Connection parameters per PHY. */ +typedef struct st_ble_gap_connection_phy_parameter +{ + uint16_t scan_intv; ///< Scan interval. + uint16_t scan_window; ///< Scan window. + ble_gap_connection_parameter_t * p_conn_param; ///< Connection interval, slave latency, supervision timeout, and CE length. +} ble_gap_connection_phy_parameter_t; + +/** Scan parameters per scan PHY. */ +typedef struct st_ble_gap_scan_phy_parameter +{ + uint8_t scan_type; ///< Scan type. + uint16_t scan_intv; ///< Scan interval. + uint16_t scan_window; ///< Scan window. +} ble_gap_scan_phy_parameter_t; + +/** Parameters configured when scanning starts. */ +typedef struct st_ble_gap_scan_on +{ + uint8_t proc_type; ///< Procedure type. + uint8_t filter_dups; ///< Filter duplicates. + uint16_t duration; ///< Scan duration. + uint16_t period; ///< Scan period. +} ble_gap_scan_on_t; + +/** Callback function parameter data */ +typedef struct st_ble_abs_callback_args +{ + uint32_t channel; ///< Select a channel corresponding to the channel number of the hardware. + ble_event_cb_t ble_abs_event; ///< The event can be used to identify what caused the callback. + void const * p_context; ///< Placeholder for user data. Set in ble_abs_api_t::open function in ::ble_abs_cfg_t. +} ble_abs_callback_args_t; + +/** BLE ABS control block. Allocate an instance specific control block to pass into the BLE ABS API calls. + * @par Implemented as + * - ble_abs_instance_ctrl_t + */ +typedef void ble_abs_ctrl_t; + +/** st_ble_abs_pairing_parameter_t includes the pairing parameters. */ +typedef struct st_ble_abs_pairing_parameter +{ + uint8_t io_capabilitie_local_device; ///< IO capabilities of local device. + uint8_t mitm_protection_policy; ///< MITM protection policy. + uint8_t secure_connection_only; ///< Determine whether to accept only Secure Connections or not. + uint8_t local_key_distribute; ///< Type of keys to be distributed from local device. + uint8_t remote_key_distribute; ///< Type of keys which local device requests a remote device to distribute. + uint8_t maximum_key_size; ///< Maximum LTK size. + uint8_t padding[2]; ///< padding +} ble_abs_pairing_parameter_t; + +/** GATT Server callback function and the priority. */ +typedef struct st_ble_abs_gatt_server_callback_set +{ + ble_gatt_server_application_callback_t gatt_server_callback_function; ///< GATT Server callback function. + uint8_t gatt_server_callback_priority; ///< The priority number of GATT Server callback function. +} ble_abs_gatt_server_callback_set_t; + +/** GATT Client callback function and the priority. */ +typedef struct st_ble_abs_gatt_client_callback_set +{ + ble_gatt_client_application_callback_t gatt_client_callback_function; ///< GATT Client callback function. + uint8_t gatt_client_callback_priority; ///< The priority number of GATT Client callback function. +} ble_abs_gatt_client_callback_set_t; + +/** st_ble_abs_legacy_advertising_parameter_t is the parameters for legacy advertising. */ +typedef struct st_ble_abs_legacy_advertising_parameter +{ + /** + * @brief The remote device address.\n + * If the p_peer_address parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n + * If the p_peer_address parameter is NULL, Undirect Connectable Advertising is performed according to \n + * the advertising filter policy specified by the filter parameter. + */ + ble_device_address_t * p_peer_address; + + /** + * @brief Advertising Data. \n + * If the p_advertising_data is specified as NULL, Advertising Data is not included in the advertising PDU. + */ + uint8_t * p_advertising_data; + + /** + * @brief Scan Response Data. \n + * If the p_scan_response_data is specified as NULL, Scan Response Data is not included in the advertising PDU. + */ + uint8_t * p_scan_response_data; + + /** + * @brief Advertising with the fast_advertising_interval parameter continues for the period specified \n + * by the fast_period parameter.\n + * Time(ms) = fast_advertising_interval * 0.625. \n + * If the fast_period parameter is 0, this parameter is ignored.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t fast_advertising_interval; + + /** + * @brief After the elapse of the fast_period, advertising with the slow_advertising_interval parameter continues \n + * for the period specified by the slow_advertising_interval parameter.\n + * Time(ms) = slow_advertising_interval * 0.625. \n + * If the slow_advertising_interval parameter is 0, this parameter is ignored.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t slow_advertising_interval; + + /** + * @brief The period which advertising with the fast_advertising_interval parameter continues for. \n + * Time = duration * 10ms.\n + * After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped.\n + * Valid range is 0x0000 - 0xFFFF. \n + * If the fast_advertising_period parameter is 0x0000, advertising with the fast_advertising_interval parameter is not performed. + */ + uint16_t fast_advertising_period; + + /** + * @brief The period which advertising with the slow_advertising_interval parameter continues for. Time = duration * 10ms. \n + * After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the slow_advertising_period parameter is 0x0000, the advertising continues. + */ + uint16_t slow_advertising_period; + + /** + * @brief Advertising data length(byte). \n + * Valid range is 0-31. \n + * If the advertising_data_length is 0, Advertising Data is not included in the advertising PDU. + */ + uint16_t advertising_data_length; + + /** + * @brief Scan response data length (in bytes). \n + * Scan Response Data(byte). \n + * Valid range is 0-31. \n + * If the scan_response_data_length is 0, Scan Response Data is not included in the advertising PDU. + */ + uint16_t scan_response_data_length; + + /** + * @brief The channel map used for the advertising packet transmission. \n + * It is a bitwise OR of the following values.\n + * | macro | description | + * |:--------------------------|:--------------- | + * | BLE_GAP_ADV_CH_37(0x01) | Use 37 CH. | + * | BLE_GAP_ADV_CH_38(0x02) | Use 38 CH. | + * | BLE_GAP_ADV_CH_39(0x04) | Use 38 CH. | + * | BLE_GAP_ADV_CH_ALL(0x07) | Use 37 - 39 CH. | + */ + uint8_t advertising_channel_map; + + /** + * @brief Advertising filter policy. \n + * If the p_peer_address parameter is NULL, the advertising is performed according to the advertising filter policy. \n + * If the p_peer_address parameter is not NULL, this parameter is ignored. \n + * | macro | description | + * |:----------------------------------------------------|:------------------------------------------------------------------------- | + * | BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY(0x00) | Process scan and connection requests from all devices. | + * | BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST(0x01) | Process scan and connection requests from only devices in the White List. | + */ + uint8_t advertising_filter_policy; + + /** + * @brief Own Bluetooth address type. \n Select one of the following. + * | macro | description | + * |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address | + * | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. | + */ + uint8_t own_bluetooth_address_type; + uint8_t own_bluetooth_address[6]; ///< Own Bluetooth address. + uint8_t padding[3]; ///< padding +} ble_abs_legacy_advertising_parameter_t; + +/** st_ble_abs_extend_advertising_parameter_t is the parameters for extended advertising. */ +typedef struct st_ble_abs_extend_advertising_parameter +{ + /** + * @brief The remote device address. \n + * If the p_addr parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n + * If the p_addr parameter is NULL, Undirect Connectable Advertising is performed \n + * according to the advertising filter policy specified by the filter parameter. + */ + ble_device_address_t * p_peer_address; + + /** + * @brief Advertising data. If p_adv_data is specified as NULL, advertising data is not set. + */ + uint8_t * p_advertising_data; + + /** + * @brief Advertising with the fast_advertising_interval parameter continues for \n + * the period specified by the fast_advertising_period parameter. \n + * Time(ms) = fast_advertising_interval * 0.625. \n + * If the fast_advertising_period parameter is 0, this parameter is ignored. \n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t fast_advertising_interval; + + /** + * @brief After the elapse of the fast_advertising_period, advertising with the slow_advertising_interval parameter \n + * continues for the period specified by the slow_advertising_period parameter. \n + * Time(ms) = fast_advertising_interval * 0.625. \n + * If the fast_advertising_period parameter is 0, this parameter is ignored. \n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t slow_advertising_interval; + + /** + * @brief The period which advertising with the fast_advertising_interval parameter continues for. \n + * Time = duration * 10ms. \n + * After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the fast_advertising_period parameter is 0x0000, the fast_advertising_interval parameter is ignored. + */ + uint16_t fast_advertising_period; + + /** + * @brief The period which advertising with the slow_advertising_interval parameter continues for. \n + * Time = duration * 10ms. \n + * After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the slow_advertising_period parameter is 0x0000, the advertising continues. + */ + uint16_t slow_advertising_period; + + /** + * @brief Advertising data length (in bytes). \n + * Valid range is 0-229. \n + * If the adv_data_length is 0, Advertising Data is not included in the advertising PDU. + */ + uint16_t advertising_data_length; + + /** + * @brief The channel map used for the advertising packet transmission. \n + * It is a bitwise OR of the following values. + * | macro | description | + * |:--------------------------|:--------------- | + * | BLE_GAP_ADV_CH_37(0x01) | Use 37 CH. | + * | BLE_GAP_ADV_CH_38(0x02) | Use 38 CH. | + * | BLE_GAP_ADV_CH_39(0x04) | Use 38 CH. | + * | BLE_GAP_ADV_CH_ALL(0x07) | Use 37 - 39 CH. | + */ + uint8_t advertising_channel_map; + + /** + * @brief Advertising filter policy. \n + * If the p_peer_address parameter is NULL, the advertising is performed according to the advertising filter policy. \n + * If the p_peer_address parameter is not NULL, this parameter is ignored. \n + * | macro | description | + * |:----------------------------------------------------|:------------------------------------------------------------------------- | + * | BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY(0x00) | Process scan and connection requests from all devices. | + * | BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST(0x01) | Process scan and connection requests from only devices in the White List. | + */ + uint8_t advertising_filter_policy; + + /** + * @brief Own Bluetooth address type. Select one of the following. \n + * | macro | description | + * |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address | + * | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. | + */ + uint8_t own_bluetooth_address_type; + uint8_t own_bluetooth_address[6]; ///< Own Bluetooth address. + + /** + * @brief Primary advertising PHY. \n + * In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. \n + * | macro | description | + * |:-------------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Primary Advertising PHY. \n When the adv_prop_type field is Legacy Advertising PDU type, this field shall be set to BLE_GAP_ADV_PHY_1M.| + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY as Primary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). | + * + */ + uint8_t primary_advertising_phy; + + /** + * @brief Secondary advertising Phy. Select one of the following. + * | macro | description | + * |:---------------------------|:------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_2M(0x02) | Use 2M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). | + */ + uint8_t secondary_advertising_phy; + uint8_t padding[3]; ///< padding +} ble_abs_extend_advertising_parameter_t; + +/** st_ble_abs_non_connectable_advertising_parameter_t is the parameters for non-connectable advertising. */ +typedef struct st_ble_abs_non_connectable_advertising_parameter +{ + /** + * @brief The remote device address. \n + * If the p_peer_address parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n + * If the p_peer_address parameter is NULL, Undirect Connectable Advertising is performed \n + * according to the advertising filter policy specified by the filter parameter. + */ + ble_device_address_t * p_peer_address; + + /** + * @brief Advertising data. If p_adv_data is specified as NULL, advertising data is not set. + */ + uint8_t * p_advertising_data; + + /** + * @brief Advertising with the advertising_interval parameter continues for the period specified by the duration parameter.\n + * Time(ms) = advertising_interval * 0.625. \n + * If the duration parameter is 0x0000, the advertising with the advertising_interval parameter continue. \n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t advertising_interval; + + /** + * @brief The period which advertising with the advertising_interval parameter continues for. \n + * Time = advertising_duration * 10ms.\n + * After the elapse of the advertising_duration, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the advertising_duration parameter is 0x0000, the advertising continues. + */ + uint16_t advertising_duration; + + /** + * @brief Advertising data length (in bytes).\n + * If the primary_advertising_phy parameter is @ref BLE_ABS_ADVERTISING_PHY_LEGACY(0x00), the valid range is 0-31. \n + * If the primary_advertising_phy parameter is the other values, the valid range is 0-1650. \n + * If the advertising_data_length parameter is 0, Advertising Data is not included in the advertising PDU. + */ + uint16_t advertising_data_length; + + /** + * @brief The channel map used for the advertising packet transmission. \n + * It is a bitwise OR of the following values. + * | macro | description | + * |:--------------------------|:--------------- | + * | BLE_GAP_ADV_CH_37(0x01) | Use 37 CH. | + * | BLE_GAP_ADV_CH_38(0x02) | Use 38 CH. | + * | BLE_GAP_ADV_CH_39(0x04) | Use 38 CH. | + * | BLE_GAP_ADV_CH_ALL(0x07) | Use 37 - 39 CH. | + */ + uint8_t advertising_channel_map; + + /** + * @brief Own Bluetooth address type. Select one of the following. \n + * | macro | description | + * |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address | + * | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. | + */ + uint8_t own_bluetooth_address_type; + uint8_t own_bluetooth_address[6]; ///< Own Bluetooth address. + + /** + * @brief Primary advertising PHY. \n + * In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. \n + * | macro | description | + * |:-------------------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | + * | BLE_ABS_ADVERTISING_PHY_LEGACY(0x00) | Use 1M PHY as Primary Advertising PHY for Non-Connectable Legacy Advertising. \n If Periodic Advertising is performed, this value shall not set to the adv_phy parameter. | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Primary Advertising PHY. \n When the adv_prop_type field is Legacy Advertising PDU type, this field shall be set to BLE_GAP_ADV_PHY_1M. | + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY as Primary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). | + */ + uint8_t primary_advertising_phy; + + /** + * @brief Secondary advertising Phy. Select one of the following. + * | macro | description | + * |:---------------------------|:------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_2M(0x02) | Use 2M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). | + */ + uint8_t secondary_advertising_phy; + uint8_t padding[2]; ///< padding +} ble_abs_non_connectable_advertising_parameter_t; + +/** st_ble_abs_periodic_advertising_parameter_t is the parameters for periodic advertising. */ +typedef struct st_ble_abs_periodic_advertising_parameter +{ + /** + * @brief Advertising parameters. + */ + ble_abs_non_connectable_advertising_parameter_t advertising_parameter; + + /** + * @brief Periodic advertising data. If p_perd_adv_data is specified as NULL, periodic advertising data is not set. + */ + uint8_t * p_periodic_advertising_data; + + /** + * @brief Periodic advertising interval. \n + * Time(ms) = periodic_advertising_interval * 1.25. \n + * Valid range is 0x0006 - 0xFFFF. + */ + uint16_t periodic_advertising_interval; + + /** + * @brief Periodic advertising data length (in bytes). \n + * Valid range is 0 - 1650. \n + * If the periodic_advertising_data_length is 0, Periodic Advertising Data is not included in the advertising PDU. + */ + uint16_t periodic_advertising_data_length; +} ble_abs_periodic_advertising_parameter_t; + +/** st_ble_abs_scan_phy_parameter_t is the phy parameters for scan. */ +typedef struct st_ble_abs_scan_phy_parameter +{ + /** + * @brief Fast scan interval. \n + * Interval(ms) = fast_scan_interval * 0.625. \n + * Valid range is 0x0004 - 0xFFFF. + * + */ + uint16_t fast_scan_interval; + + /** + * @brief Slow Scan interval. \n + * Slow Scan interval(ms) = slow_scan_interval * 0.625. \n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t slow_scan_interval; + + /** + * @brief Fast Scan window. \n + * Fast Scan window(ms) = fast_scan_window * 0.625. \n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t fast_scan_window; + + /** + * @brief Slow Scan window. \n + * Slow Scan window(ms) = slow_scan_window * 0.625. \n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t slow_scan_window; + + /** + * @brief Scan type. + * | macro | description | + * |:-----------------------------|:--------------- | + * | BLE_GAP_SCAN_PASSIVE(0x00) | Passive Scan. | + * | BLE_GAP_SCAN_ACTIVE(0x01) | Active Scan. | + */ + uint8_t scan_type; + + /** + * @brief padding. + */ + uint8_t padding[3]; +} ble_abs_scan_phy_parameter_t; + +/** st_ble_abs_scan_parameter_t is the parameters for scan. */ +typedef struct st_ble_abs_scan_parameter +{ + /** + * @brief Scan parameters for receiving the advertising packets in 1M PHY. \n + * In case of not receiving the advertising packets in 1M PHY, this field is specified as NULL. \n + * p_phy_parameter_1M or p_phy_parameter_coded field shall be set to scan parameters. + */ + ble_abs_scan_phy_parameter_t * p_phy_parameter_1M; + + /** + * @brief Scan parameters for receiving the advertising packets in Coded PHY. \n + * In case of not receiving the advertising packets in Coded PHY, this field is specified as NULL. \n + * p_phy_parameter_1M or p_phy_parameter_coded field shall be set to scan parameters. + */ + ble_abs_scan_phy_parameter_t * p_phy_parameter_coded; + + /** + * @brief Data for Advertising Data filtering. \n + * The p_filter_data parameter is used for the advertising data in single advertising report. \n + * The advertising data composed of multiple advertising reports is not filtered by this parameter. \n + * If the p_filter_data parameter is specified as NULL, the filtering is not done. + */ + uint8_t * p_filter_data; + + /** + * @brief The period which scan with the fast scan interval/fast scan window continues for. \n + * Time(ms) = fast_scan_period * 10. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the fast_scan_period parameter is 0x0000, scan with the fast scan interval/fast scan window is not performed. \n + * After the elapse of the fast_scan_period, @ref BLE_GAP_EVENT_SCAN_TO event notifies that the scan has stopped. + */ + uint16_t fast_scan_period; + + /** + * @brief The period which scan with the slow scan interval/slow scan window continues for. \n + * Time = slow_scan_period * 10ms. \n + * Valid range is 0x0000 - 0xFFFF. \n + * If the slow_scan_period parameter is 0x0000, the scan continues. \n + * After the elapse of the slow_scan_period, @ref BLE_GAP_EVENT_SCAN_TO event notifies that the scan has stopped. + */ + uint16_t slow_scan_period; + + /** + * @brief The length of the data specified by the p_filter_data parameter. \n + * Valid range is 0x0000-0x0010. \n + * If the filter_data_length parameter is 0, the filtering is not done. + */ + uint16_t filter_data_length; + + /** + * @brief Scan Filter Policy. Select one of the following. + * | macro | description | + * |:--------------------------------------------------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_SCAN_ALLOW_ADV_ALL(0x00) | Accept all advertising and scan response PDUs except directed advertising PDUs not addressed to local device. | + * | BLE_GAP_SCAN_ALLOW_ADV_WLST(0x01) | Accept only advertising and scan response PDUs from remote devices whose address is registered in the White List. \n Directed advertising PDUs which are not addressed to local device is ignored. | + * | BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED(0x02) | Accept all advertising and scan response PDUs except directed advertising PDUs whose the target address is identity address but doesn't address local device. However directed advertising PDUs whose the target address is the local resolvable private address are accepted. | + * | BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST(0x03) | Accept all advertising and scan response PDUs. The following are excluded. \n \arg Advertising and scan response PDUs where the advertiser's identity address is not in the White List. \n \arg Directed advertising PDUs whose the target address is identity address but doesn't address local device. However directed advertising PDUs whose the target address is the local resolvable private address are accepted. | + */ + uint8_t device_scan_filter_policy; + + /** + * @brief Filter duplicates. \n + * Maximum number of filtered devices is 8. \n + * The 9th and subsequent devices are not filtered by this parameter. \n + * | macro | description | + * |:--------------------------------------------------|:-------------------------------------------------------- | + * | BLE_GAP_SCAN_FILT_DUPLIC_DISABLE(0x00) | Duplicate filter disabled. | + * | BLE_GAP_SCAN_FILT_DUPLIC_ENABLE(0x01) | Duplicate filter enabled. | + * | BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02)) | Duplicate filtering enabled, reset for each scan period. | + * + */ + uint8_t filter_duplicate; + + /** + * @brief The AD type of the data specified by the p_filter_data parameter.\n + * The AD type identifier values are defined in Bluetooth SIG Assigned Number \n + * (https://www.bluetooth.com/specifications/assigned-numbers). + */ + uint8_t filter_ad_type; + + /** + * @brief Padding + */ + uint8_t padding[3]; +} ble_abs_scan_parameter_t; + +/** st_ble_abs_connection_phy_parameter_t is the phy parameters for create connection. */ +typedef struct st_ble_abs_connection_phy_parameter +{ + /** + * @brief Connection interval. \n + * Time(ms) = connection_interval * 1.25. \n + * Valid range is 0x0006 - 0x0C80. + */ + uint16_t connection_interval; + + /** + * @brief Slave latency. \n + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t connection_slave_latency; + + /** + * @brief Supervision timeout. \n + * Time(ms) = supervision_timeout * 10. \n + * Valid range is 0x000A - 0x0C80. + */ + uint16_t supervision_timeout; + + /** + * @brief Padding + */ + uint8_t padding[2]; +} ble_abs_connection_phy_parameter_t; + +/** st_ble_abs_connection_parameter_t is the parameters for create connection. */ +typedef struct st_ble_abs_connection_parameter +{ + /** + * @brief Connection interval, slave latency, supervision timeout for 1M PHY. \n + * The p_connection_phy_parameter_1M is specified as NULL, a connection request is not sent with 1M PHY. + */ + ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_1M; + + /** + * @brief Connection interval, slave latency, supervision timeout for 2M PHY. \n + * The p_connection_phy_parameter_2M is specified as NULL, a connection request is not sent with 2M PHY. + */ + ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_2M; + + /** + * @brief Connection interval, slave latency, supervision timeout for Coded PHY. \n + * The p_connection_phy_parameter_coded is specified as NULL, a connection request is not sent with Coded PHY. + */ + ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_coded; + + /** + * @brief Address of the device to be connected. \n + * If the filter field is @ref BLE_GAP_INIT_FILT_USE_WLST(0x01), this parameter is ignored. + */ + ble_device_address_t * p_device_address; + + /** + * @brief The filter field specifies whether the White List is used or not, when connecting with a remote device.\n + * | macro | description | + * |:---------------------------------|:---------------------------------------------------------------------------------------------------------------------------------- | + * | BLE_GAP_INIT_FILT_USE_ADDR(0x00) | White List is not used. \n The remote device to be connected is specified by the p_addr field is used. | + * | BLE_GAP_INIT_FILT_USE_WLST(0x01) | White List is used. \n The remote device registered in White List is connected with local device. \n The p_addr field is ignored. | + */ + uint8_t filter_parameter; + + /** + * @brief The time(sec) to cancel the create connection request. \n + * Valid range is 0 <= connection_timeout <= 10. \n + * If the connection_timeout field is 0, the create connection request is not canceled. \n + */ + uint8_t connection_timeout; + + /** + * @brief Padding + */ + uint8_t padding[2]; +} ble_abs_connection_parameter_t; + +/** BLE ABS configuration parameters. */ +typedef struct st_ble_abs_cfg +{ + /** the parameters for initialization. */ + uint32_t channel; ///< Select a channel corresponding to the channel number of the hardware. + ble_gap_application_callback_t gap_callback; ///< GAP callback function. + ble_vendor_specific_application_callback_t vendor_specific_callback; ///< Vendor Specific callback function. + ble_abs_gatt_server_callback_set_t * p_gatt_server_callback_list; ///< GATT Server callback set. + uint8_t gatt_server_callback_list_number; ///< The number of GATT Server callback functions. + ble_abs_gatt_client_callback_set_t * p_gatt_client_callback_list; ///< GATT Client callback set. + uint8_t gatt_client_callback_list_number; ///< The number of GATT Client callback functions. + ble_abs_pairing_parameter_t * p_pairing_parameter; ///< Pairing parameters. + + flash_instance_t const * p_flash_instance; ///< Pointer to flash instance. + timer_instance_t const * p_timer_instance; ///< Pointer to timer instance. + + void (* p_callback)(ble_abs_callback_args_t * p_args); ///< Callback provided when a BLE ISR occurs. + void const * p_context; ///< Placeholder for user data. Passed to the user callback in ble_abs_callback_args_t. + void const * p_extend; ///< Placeholder for user extension. +} ble_abs_cfg_t; + +/** BLE ABS functions implemented at the HAL layer will follow this API. */ +typedef struct st_ble_abs_api +{ + /** Initialize the BLE ABS in register start mode. + * @par Implemented as + * - RM_BLE_ABS_Open() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg); + + /** Close the BLE ABS. + * @par Implemented as + * - RM_BLE_ABS_Close() + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ble_abs_ctrl_t * const p_ctrl); + + /** Close the BLE ABS. + * @par Implemented as + * - RM_BLE_ABS_Reset() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] init_callback callback function to initialize Host Stack. + */ + fsp_err_t (* reset)(ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback); + + /** Return the version of the driver. + * @par Implemented as + * - RM_BLE_ABS_VersionGet() + * @param[out] p_data Memory address to return version information to. + */ + fsp_err_t (* versionGet)(fsp_version_t * const p_data); + + /** Start Legacy Connectable Advertising. + * @par Implemented as + * - RM_BLE_ABS_StartLegacyAdvertising() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_advertising_parameter Pointer to Advertising parameters for Legacy Advertising. + */ + fsp_err_t (* startLegacyAdvertising)(ble_abs_ctrl_t * const p_ctrl, + ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter); + + /** Start Extended Connectable Advertising. + * @par Implemented as + * - RM_BLE_ABS_StartExtendedAdvertising() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_advertising_parameter Pointer to Advertising parameters for extend Advertising. + */ + fsp_err_t (* startExtendedAdvertising)(ble_abs_ctrl_t * const p_ctrl, + ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter); + + /** Start Non-Connectable Advertising. + * @par Implemented as + * - RM_BLE_ABS_StartNonConnectableAdvertising() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_advertising_parameter Pointer to Advertising parameters for non-connectable Advertising. + */ + fsp_err_t (* startNonConnectableAdvertising)(ble_abs_ctrl_t * const p_ctrl, + ble_abs_non_connectable_advertising_parameter_t const * const + p_advertising_parameter); + + /** Start Periodic Advertising. + * @par Implemented as + * - RM_BLE_ABS_StartPeriodicAdvertising() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_advertising_parameter Pointer to Advertising parameters for periodic Advertising. + */ + fsp_err_t (* startPeriodicAdvertising)(ble_abs_ctrl_t * const p_ctrl, + ble_abs_periodic_advertising_parameter_t const * const + p_advertising_parameter); + + /** Start scanning. + * @par Implemented as + * - RM_BLE_ABS_StartScanning() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_scan_parameter Pointer to scan parameter. + */ + fsp_err_t (* startScanning)(ble_abs_ctrl_t * const p_ctrl, ble_abs_scan_parameter_t const * const p_scan_parameter); + + /** Request create connection. + * @par Implemented as + * - RM_BLE_ABS_CreateConnection() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_connection_parameter Pointer to connection parameter. + */ + fsp_err_t (* createConnection)(ble_abs_ctrl_t * const p_ctrl, + ble_abs_connection_parameter_t const * const p_connection_parameter); + + /** Configure local device privacy. + * @par Implemented as + * - RM_BLE_ABS_SetLocalPrivacy() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_lc_irk Pointer to IRK to be registered in the resolving list. + * @param[in] privacy_mode privacy_mode privacy mode. + */ + fsp_err_t (* setLocalPrivacy)(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk, uint8_t privacy_mode); + + /** Start pairing or encryption. + * @par Implemented as + * - RM_BLE_ABS_StartAuthentication() + * @param[in] p_ctrl Pointer to control structure. + * @param[in] connection_handle Connection handle identifying the remote device. + */ + fsp_err_t (* startAuthentication)(ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle); +} ble_abs_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ble_abs_instance +{ + ble_abs_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ble_abs_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ble_abs_api_t const * p_api; ///< Pointer to the API structure for this instance +} ble_abs_instance_t; + +/*******************************************************************************************************************//** + * @} (end addtogroup BLE_ABS_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_common_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_common_api.h new file mode 100644 index 0000000000..d86714a407 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_common_api.h @@ -0,0 +1,342 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +/*LDRA_INSPECTED 340 s */ +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ +} fsp_err_t; + +/** Common version structure */ +typedef union st_fsp_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters */ + struct + { + uint8_t code_version_minor; ///< Code minor version + uint8_t code_version_major; ///< Code major version + uint8_t api_version_minor; ///< API minor version + uint8_t api_version_major; ///< API major version + }; +} fsp_version_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_features.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_features.h new file mode 100644 index 0000000000..c9a7918230 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_features.h @@ -0,0 +1,285 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CFLASH = 0, ///< Code Flash + FSP_IP_DFLASH = 1, ///< Data Flash + FSP_IP_RAM = 2, ///< RAM + FSP_IP_LVD = 3, ///< Low Voltage Detection + FSP_IP_CGC = 3, ///< Clock Generation Circuit + FSP_IP_LPM = 3, ///< Low Power Modes + FSP_IP_FCU = 4, ///< Flash Control Unit + FSP_IP_ICU = 6, ///< Interrupt Control Unit + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_DTC = 8, ///< Data Transfer Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_PFS = 10, ///< Pin Function Select + FSP_IP_ELC = 11, ///< Event Link Controller + FSP_IP_MPU = 13, ///< Memory Protection Unit + FSP_IP_MSTP = 14, ///< Module Stop + FSP_IP_MMF = 15, ///< Memory Mirror Function + FSP_IP_KEY = 16, ///< Key Interrupt Function + FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit + FSP_IP_DOC = 18, ///< Data Operation Circuit + FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator + FSP_IP_SCI = 20, ///< Serial Communications Interface + FSP_IP_IIC = 21, ///< I2C Bus Interface + FSP_IP_SPI = 22, ///< Serial Peripheral Interface + FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit + FSP_IP_SCE = 24, ///< Secure Cryptographic Engine + FSP_IP_SLCDC = 25, ///< Segment LCD Controller + FSP_IP_AES = 26, ///< Advanced Encryption Standard + FSP_IP_TRNG = 27, ///< True Random Number Generator + FSP_IP_FCACHE = 30, ///< Flash Cache + FSP_IP_SRAM = 31, ///< SRAM + FSP_IP_ADC = 32, ///< A/D Converter + FSP_IP_DAC = 33, ///< 12-Bit D/A Converter + FSP_IP_TSN = 34, ///< Temperature Sensor + FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit + FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator + FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator + FSP_IP_OPAMP = 38, ///< Operational Amplifier + FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter + FSP_IP_RTC = 40, ///< Real Time Clock + FSP_IP_WDT = 41, ///< Watch Dog Timer + FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer + FSP_IP_GPT = 43, ///< General PWM Timer + FSP_IP_POEG = 44, ///< Port Output Enable for GPT + FSP_IP_OPS = 45, ///< Output Phase Switch + FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer + FSP_IP_CAN = 48, ///< Controller Area Network + FSP_IP_IRDA = 49, ///< Infrared Data Association + FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface + FSP_IP_USBFS = 51, ///< USB Full Speed + FSP_IP_SDHI = 52, ///< SD/MMC Host Interface + FSP_IP_SRC = 53, ///< Sampling Rate Converter + FSP_IP_SSI = 54, ///< Serial Sound Interface + FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface + FSP_IP_ETHER = 64, ///< Ethernet MAC Controller + FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller + FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller + FSP_IP_PDC = 66, ///< Parallel Data Capture Unit + FSP_IP_GLCDC = 67, ///< Graphics LCD Controller + FSP_IP_DRW = 68, ///< 2D Drawing Engine + FSP_IP_JPEG = 69, ///< JPEG + FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter + FSP_IP_USBHS = 71, ///< USB High Speed +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH + FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH + FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END + FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B + FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A + FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B + FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ + FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ + FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A + FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B + FSP_SIGNAL_AGT_INT, ///< AGT INT + FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR + FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END + FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW + FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR + FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX + FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX + FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX + FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX + FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP + FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST + FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 + FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 + FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD + FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT + FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT + FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT + FSP_SIGNAL_CTSU_END = 0, ///< CTSU END + FSP_SIGNAL_CTSU_READ, ///< CTSU READ + FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE + FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI + FSP_SIGNAL_DALI_CLI, ///< DALI CLI + FSP_SIGNAL_DALI_SDI, ///< DALI SDI + FSP_SIGNAL_DALI_BPI, ///< DALI BPI + FSP_SIGNAL_DALI_FEI, ///< DALI FEI + FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI + FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT + FSP_SIGNAL_DOC_INT = 0, ///< DOC INT + FSP_SIGNAL_DRW_INT = 0, ///< DRW INT + FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE + FSP_SIGNAL_DTC_END, ///< DTC END + FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT + FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 + FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 + FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS + FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT + FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT + FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL + FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE + FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL + FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE + FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL + FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE + FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL + FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE + FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL + FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE + FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL + FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE + FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR + FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI + FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT + FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 + FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 + FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A + FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B + FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C + FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D + FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E + FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F + FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW + FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW + FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A + FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B + FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE + FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 + FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 + FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 + FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 + FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 + FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 + FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 + FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 + FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 + FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 + FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 + FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 + FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 + FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 + FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 + FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 + FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL + FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI + FSP_SIGNAL_IIC_RXI, ///< IIC RXI + FSP_SIGNAL_IIC_TEI, ///< IIC TEI + FSP_SIGNAL_IIC_TXI, ///< IIC TXI + FSP_SIGNAL_IIC_WUI, ///< IIC WUI + FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 + FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 + FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 + FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 + FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW + FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI + FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI + FSP_SIGNAL_KEY_INT = 0, ///< KEY INT + FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END + FSP_SIGNAL_PDC_INT, ///< PDC INT + FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY + FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT + FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT + FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM + FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD + FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY + FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY + FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY + FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG + FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY + FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 + FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 + FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK + FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY + FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 + FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 + FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 + FSP_SIGNAL_SCI_AM = 0, ///< SCI AM + FSP_SIGNAL_SCI_ERI, ///< SCI ERI + FSP_SIGNAL_SCI_RXI, ///< SCI RXI + FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI + FSP_SIGNAL_SCI_TEI, ///< SCI TEI + FSP_SIGNAL_SCI_TXI, ///< SCI TXI + FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI + FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND + FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND + FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS + FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD + FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ + FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO + FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI + FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE + FSP_SIGNAL_SPI_RXI, ///< SPI RXI + FSP_SIGNAL_SPI_TEI, ///< SPI TEI + FSP_SIGNAL_SPI_TXI, ///< SPI TXI + FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END + FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY + FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL + FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW + FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW + FSP_SIGNAL_SSI_INT = 0, ///< SSI INT + FSP_SIGNAL_SSI_RXI, ///< SSI RXI + FSP_SIGNAL_SSI_TXI, ///< SSI TXI + FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI + FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ + FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 + FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 + FSP_SIGNAL_USB_INT, ///< USB INT + FSP_SIGNAL_USB_RESUME, ///< USB RESUME + FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_version.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_version.h new file mode 100644 index 0000000000..cffdc0235e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/fsp_version.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_VERSION_H +#define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ +#define FSP_VERSION_MAJOR (1U) + +/** FSP pack minor version. */ +#define FSP_VERSION_MINOR (1U) + +/** FSP pack patch version. */ +#define FSP_VERSION_PATCH (1U) + +/** FSP pack version build number (currently unused). */ +#define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ +#define FSP_VERSION_STRING ("1.1.1") + +/** Unique FSP version ID. */ +#define FSP_VERSION_BUILD_STRING ("Built with Renesas Arm Flexible Software Package version 1.1.1") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters, little endian order. */ + /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in FSP code. */ + struct + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + }; +} fsp_pack_version_t; + +/** @} */ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_agt.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_agt.h new file mode 100644 index 0000000000..a57bc248af --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_agt.h @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_AGT_H +#define R_AGT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_agt_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standards violation. */ +#define AGT_CODE_VERSION_MAJOR (1U) +#define AGT_CODE_VERSION_MINOR (1U) + +/** Maximum number of clock counts in 16 bit timer. */ +#define AGT_MAX_CLOCK_COUNTS (UINT16_MAX) + +/** Maximum period value allowed for AGT. */ +#define AGT_MAX_PERIOD (UINT16_MAX + 1U) + +/*******************************************************************************************************************//** + * @addtogroup AGT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Count source */ +typedef enum e_agt_clock +{ + AGT_CLOCK_PCLKB = 0x00, ///< PCLKB count source, division by 1, 2, or 8 allowed + AGT_CLOCK_LOCO = 0x40, ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_AGT0_UNDERFLOW = 0x50, ///< Underflow event signal from AGT0, division must be 1 + AGT_CLOCK_SUBCLOCK = 0x60, ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_P402 = 0x92, ///< Counts events on P402, events are counted in deep software standby mode + AGT_CLOCK_P403 = 0x93, ///< Counts events on P403, events are counted in deep software standby mode + AGT_CLOCK_AGTIO = 0x80, ///< Counts events on AGTIOn, events are not counted in software standby modes +} agt_clock_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_measure +{ + AGT_MEASURE_DISABLED = 1U, ///< AGT used as a counter + AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL = 3U, ///< AGT used to measure low level pulse width + AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL = 0x13U, ///< AGT used to measure high level pulse width + AGT_MEASURE_PULSE_PERIOD = 4U, ///< AGT used to measure pulse period +} agt_measure_t; + +/** Input filter, applies AGTIO in pulse period measurement, pulse width measurement, or event counter mode. The filter + * requires the signal to be at the same level for 3 successive reads at the specified filter frequency. */ +typedef enum e_agt_agtio_filter +{ + AGT_AGTIO_FILTER_NONE = 0x00U, ///< No filter + AGT_AGTIO_FILTER_PCLKB = 0x10U, ///< Filter at PCLKB + AGT_AGTIO_FILTER_PCLKB_DIV_8 = 0x20U, ///< Filter at PCLKB / 8 + AGT_AGTIO_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32 +} agt_agtio_filter_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_enable_pin +{ + AGT_ENABLE_PIN_NOT_USED = 0U, ///< AGTEE is not used + AGT_ENABLE_PIN_ACTIVE_LOW = 0x40U, ///< Events are only counted when AGTEE is low + AGT_ENABLE_PIN_ACTIVE_HIGH = 0x44U, ///< Events are only counted when AGTEE is high +} agt_enable_pin_t; + +/** Trigger edge for pulse period measurement mode and event counting mode. */ +typedef enum e_agt_trigger_edge +{ + AGT_TRIGGER_EDGE_RISING = 0U, ///< Measurement starts or events are counted on rising edge + AGT_TRIGGER_EDGE_FALLING = 1U, ///< Measurement starts or events are counted on falling edge + AGT_TRIGGER_EDGE_BOTH = 8U, ///< Events are counted on both edges (n/a for pulse period mode) +} agt_trigger_edge_t; + +/** Output pins, used to select which duty cycle to update in R_AGT_DutyCycleSet(). */ +typedef enum e_agt_output_pin +{ + AGT_OUTPUT_PIN_AGTOA = 0, ///< GTIOCA + AGT_OUTPUT_PIN_AGTOB = 1, ///< GTIOCB +} agt_output_pin_t; + +/** Level of AGT pin */ +typedef enum e_agt_pin_cfg +{ + AGT_PIN_CFG_DISABLED = 0, ///< Not used as output pin + AGT_PIN_CFG_START_LEVEL_LOW = 3, ///< Pin level low + AGT_PIN_CFG_START_LEVEL_HIGH = 7, ///< Pin level high +} agt_pin_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_agt_instance_ctrl +{ + uint32_t open; ///< Whether or not channel is open + const timer_cfg_t * p_cfg; ///< Pointer to initial configurations + R_AGT0_Type * p_reg; ///< Base register for this channel + uint32_t period; ///< Current timer period (counts) +} agt_instance_ctrl_t; + +/** Optional AGT extension data structure.*/ +typedef struct st_agt_extended_cfg +{ + agt_clock_t count_source; ///< AGT channel clock source. Valid values are: AGT_CLOCK_PCLKB, AGT_CLOCK_LOCO, AGT_CLOCK_FSUB + + /* Output pin settings. */ + union + { + uint8_t agtoab_settings; + struct + { + agt_pin_cfg_t agtoa : 3; ///< Configure AGTOA pin + uint8_t : 1; + agt_pin_cfg_t agtob : 3; ///< Configure AGTOB pin + }; + }; + agt_pin_cfg_t agto : 3; ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO + + /* Input pin settings. */ + agt_measure_t measurement_mode; ///< Measurement mode + agt_agtio_filter_t agtio_filter; ///< Input filter for AGTIO + agt_enable_pin_t enable_pin; ///< Enable pin (event counting only) + agt_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event +} agt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_agt; + +/** @endcond */ + +fsp_err_t R_AGT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_AGT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_AGT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_AGT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_AGT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_AGT_VersionGet(fsp_version_t * const p_version); + +/*******************************************************************************************************************//** + * @} (end defgroup AGT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + +FSP_FOOTER + +#endif // R_AGT_H diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h new file mode 100644 index 0000000000..d66a22db74 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h @@ -0,0 +1,141 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#ifndef R_FLASH_LP_H +#define R_FLASH_LP_H + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_flash_api.h" +#include "r_flash_lp_cfg.h" + +/*******************************************************************************************************************//** + * @ingroup HAL_Library + * @addtogroup FLASH_LP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define FLASH_LP_CODE_VERSION_MAJOR (1U) +#define FLASH_LP_CODE_VERSION_MINOR (1U) + +/* If Code Flash programming is enabled, then code flash functions must execute out of RAM. */ +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if defined(__ICCARM__) + #pragma section=".code_in_ram" + #endif + #if defined(__ARMCC_VERSION) + #define PLACE_IN_RAM_SECTION BSP_PLACE_IN_SECTION(".code_in_ram") __attribute__((noinline)) + #else + #define PLACE_IN_RAM_SECTION BSP_PLACE_IN_SECTION(".code_in_ram") + #endif +#else + #define PLACE_IN_RAM_SECTION +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Possible Flash operation states */ +typedef enum e_flash_bgo_operation +{ + FLASH_OPERATION_NON_BGO, + FLASH_OPERATION_DF_BGO_WRITE, + FLASH_OPERATION_DF_BGO_ERASE, + FLASH_OPERATION_DF_BGO_BLANKCHECK, +} flash_bgo_operation_t; + +/** Flash instance control block. DO NOT INITIALIZE. Initialization occurs when R_FLASH_LP_Open() is called. */ +typedef struct st_flash_lp_instance_ctrl +{ + uint32_t opened; // To check whether api has been opened or not. + flash_cfg_t const * p_cfg; // Pointer to the flash configuration block. + uint32_t system_clock_frequency; // System clock frequency + uint32_t flash_clock_frequency; // FlashIF clock frequency + uint32_t timeout_write_cf; // Timeout for writing code flash data + uint32_t timeout_write_df; // Timeout for writing data flash data + uint32_t timeout_blank_check; // Timeout for blank check operations + uint32_t timeout_erase_cf_block; // Timeout for erasing a code flash block + uint32_t timeout_erase_df_block; // Timeout for erasing a data flash block + uint32_t timeout_write_extra_area; // Timeout for writing to the configuration area + uint32_t source_start_address; // Source/Start address of in progress operation + uint32_t dest_end_address; // Destination/End address of in progress operation + uint32_t operations_remaining; // Number of operations remaining + flash_bgo_operation_t current_operation; // Type of BGO operation in progress. +} flash_lp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const flash_api_t g_flash_on_flash_lp; + +/** @endcond */ + +fsp_err_t R_FLASH_LP_Open(flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg); +fsp_err_t R_FLASH_LP_Write(flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes); +fsp_err_t R_FLASH_LP_Erase(flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks); +fsp_err_t R_FLASH_LP_BlankCheck(flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * blank_check_result); +fsp_err_t R_FLASH_LP_Close(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_FLASH_LP_StatusGet(flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status); +fsp_err_t R_FLASH_LP_AccessWindowSet(flash_ctrl_t * const p_api_ctrl, uint32_t const start_addr, + uint32_t const end_addr); +fsp_err_t R_FLASH_LP_AccessWindowClear(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_FLASH_LP_IdCodeSet(flash_ctrl_t * const p_api_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode); +fsp_err_t R_FLASH_LP_Reset(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_FLASH_LP_StartUpAreaSelect(flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary); +fsp_err_t R_FLASH_LP_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_FLASH_LP_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_FLASH_LP_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info); + +/*******************************************************************************************************************//** + * @} (end addtogroup FLASH_LP) + **********************************************************************************************************************/ + +/* This will generate a build error if this file is included and the target MCU used is NOT one of the following. */ +#if !BSP_FEATURE_FLASH_LP_VERSION + #error "r_flash_lp is not a supported module for this board type." +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h new file mode 100644 index 0000000000..0348d328dc --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h @@ -0,0 +1,358 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_GPT_H +#define R_GPT_H + +/*******************************************************************************************************************//** + * @addtogroup GPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define GPT_CODE_VERSION_MAJOR (1U) +#define GPT_CODE_VERSION_MINOR (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ +typedef enum e_gpt_io_pin +{ + GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA + GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB + GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB +} gpt_io_pin_t; + +/** Level of GPT pin */ +typedef enum e_gpt_pin_level +{ + GPT_PIN_LEVEL_LOW = 0, ///< Pin level low + GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high +} gpt_pin_level_t; + +/** GPT PWM shortest pin level */ +typedef enum e_gpt_shortest_level +{ + /** 1 extra PCLK in ON time. Minimum ON time will be limited to 2 PCLK raw counts. */ + GPT_SHORTEST_LEVEL_OFF = 0, + + /** 1 extra PCLK in OFF time. Minimum ON time will be limited to 1 PCLK raw counts. */ + GPT_SHORTEST_LEVEL_ON = 1, +} gpt_shortest_level_t; + +/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent + * a bitmask. Multiple sources can be ORed together. */ +typedef enum e_gpt_source +{ + /** No active event sources. */ + GPT_SOURCE_NONE = 0U, + + /** Action performed on GTETRGA rising edge. **/ + GPT_SOURCE_GTETRGA_RISING = (1U << 0), + + /** Action performed on GTETRGA falling edge. **/ + GPT_SOURCE_GTETRGA_FALLING = (1U << 1), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGB_RISING = (1U << 2), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGB_FALLING = (1U << 3), + + /** Action performed on GTETRGC rising edge. **/ + GPT_SOURCE_GTETRGC_RISING = (1U << 4), + + /** Action performed on GTETRGC falling edge. **/ + GPT_SOURCE_GTETRGC_FALLING = (1U << 5), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGD_RISING = (1U << 6), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGD_FALLING = (1U << 7), + + /** Action performed when GTIOCA input rises while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), + + /** Action performed when GTIOCA input rises while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), + + /** Action performed when GTIOCA input falls while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), + + /** Action performed when GTIOCA input falls while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), + + /** Action performed when GTIOCB input rises while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), + + /** Action performed when GTIOCB input rises while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), + + /** Action performed when GTIOCB input falls while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), + + /** Action performed when GTIOCB input falls while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), + + /** Action performed on ELC GPTA event. **/ + GPT_SOURCE_GPT_A = (1U << 16), + + /** Action performed on ELC GPTB event. **/ + GPT_SOURCE_GPT_B = (1U << 17), + + /** Action performed on ELC GPTC event. **/ + GPT_SOURCE_GPT_C = (1U << 18), + + /** Action performed on ELC GPTD event. **/ + GPT_SOURCE_GPT_D = (1U << 19), + + /** Action performed on ELC GPTE event. **/ + GPT_SOURCE_GPT_E = (1U << 20), + + /** Action performed on ELC GPTF event. **/ + GPT_SOURCE_GPT_F = (1U << 21), + + /** Action performed on ELC GPTG event. **/ + GPT_SOURCE_GPT_G = (1U << 22), + + /** Action performed on ELC GPTH event. **/ + GPT_SOURCE_GPT_H = (1U << 23), +} gpt_source_t; + +/** Configurations for output pins. */ +typedef struct s_gpt_output_pin +{ + bool output_enabled; ///< Set to true to enable output, false to disable output + gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t +} gpt_output_pin_t; + +/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. + * The noise filter samples the external signal at intervals of the PCLK divided by one of the values. + * When 3 consecutive samples are at the same level (high or low), then that level is passed on as + * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. + */ +typedef enum e_gpt_capture_filter +{ + GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering + GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling + GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4 + GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16 + GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling +} gpt_capture_filter_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_trigger +{ + GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match +} gpt_adc_trigger_t; + +/** POEG channel to link to this channel. */ +typedef enum e_gpt_poeg_link +{ + GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) + GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) + GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) + GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) +} gpt_poeg_link_t; + +/** Select trigger to send output disable request to POEG. */ +typedef enum e_gpt_output_disable +{ + GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request + GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time +} gpt_output_disable_t; + +/** Disable level options for GTIOC pins. */ +typedef enum e_gpt_gtioc_disable +{ + GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable + GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled + GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled + GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled +} gpt_gtioc_disable_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_compare_match +{ + GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A + GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B +} gpt_adc_compare_match_t; + +/** Interrupt skipping modes */ +typedef enum e_gpt_interrupt_skip_source +{ + GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts + + /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, + + /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, +} gpt_interrupt_skip_source_t; + +/** Number of interrupts to skip between events */ +typedef enum e_gpt_interrupt_skip_count +{ + GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt + GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts + GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts + GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts + GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts + GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts + GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts +} gpt_interrupt_skip_count_t; + +/** ADC events to skip during interrupt skipping */ +typedef enum e_gpt_interrupt_skip_adc +{ + GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events + GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events + GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events + GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events +} gpt_interrupt_skip_adc_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_gpt_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT0_Type * p_reg; // Base register for this channel + uint32_t channel_mask; // Channel bitmask + timer_variant_t variant; // Timer variant +} gpt_instance_ctrl_t; + +/** GPT extension for advanced PWM features. */ +typedef struct st_gpt_extended_pwm_cfg +{ + uint8_t trough_ipl; ///< Trough interrupt priority + IRQn_Type trough_irq; ///< Trough interrupt + gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel + gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG + gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion + uint32_t dead_time_count_up; ///< Set a dead time value for counting up + uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only) + uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_A + uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_B + gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping + gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events + gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled + gpt_gtioc_disable_t gtioca_disable_setting; ///< Select how to configure GTIOCA when output is disabled + gpt_gtioc_disable_t gtiocb_disable_setting; ///< Select how to configure GTIOCB when output is disabled +} gpt_extended_pwm_cfg_t; + +/** GPT extension configures the output pins for GPT. */ +typedef struct st_gpt_extended_cfg +{ + gpt_output_pin_t gtioca; ///< Configuration for GPT I/O pin A + gpt_output_pin_t gtiocb; ///< Configuration for GPT I/O pin B + gpt_shortest_level_t shortest_pwm_signal; ///< Shortest PWM signal level + gpt_source_t start_source; ///< Event sources that trigger the timer to start + gpt_source_t stop_source; ///< Event sources that trigger the timer to stop + gpt_source_t clear_source; ///< Event sources that trigger the timer to clear + gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA + gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB + + /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_up_source; + + /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_down_source; + + /* Debounce filter for GTIOCxA input signal pin. */ + gpt_capture_filter_t capture_filter_gtioca; + + /* Debounce filter for GTIOCxB input signal pin. */ + gpt_capture_filter_t capture_filter_gtiocb; + + uint8_t capture_a_ipl; ///< Capture A interrupt priority + uint8_t capture_b_ipl; ///< Capture B interrupt priority + IRQn_Type capture_a_irq; ///< Capture A interrupt + IRQn_Type capture_b_irq; ///< Capture B interrupt + gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional +} gpt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_gpt; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); +fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, + gpt_adc_compare_match_t which_compare_match, + uint32_t compare_match_value); +fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_VersionGet(fsp_version_t * const p_version); + +/*******************************************************************************************************************//** + * @} (end defgroup GPT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_icu.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_icu.h new file mode 100644 index 0000000000..0089ebb226 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_icu.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup ICU + * @{ + **********************************************************************************************************************/ + +#ifndef R_ICU_H +#define R_ICU_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_external_irq_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ICU_CODE_VERSION_MAJOR (1U) +#define ICU_CODE_VERSION_MINOR (0U) + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ +typedef struct st_icu_instance_ctrl +{ + uint32_t open; ///< Used to determine if channel control block is in use + IRQn_Type irq; ///< NVIC interrupt number + uint8_t channel; ///< Channel + + /** Callback provided when a external IRQ ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(external_irq_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ + void const * p_context; +} icu_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const external_irq_api_t g_external_irq_on_icu; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg); + +fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqVersionGet(fsp_version_t * const p_version); + +fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ICU) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ICU_H diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h new file mode 100644 index 0000000000..fe48ab6e4e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h @@ -0,0 +1,311 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#include "r_ioport_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IOPORT_CODE_VERSION_MAJOR (1U) +#define IOPORT_CODE_VERSION_MINOR (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; + void const * p_context; +} ioport_instance_ctrl_t; + +/* This typedef is here temporarily. See SWFLEX-144 for details. */ +/** Superset list of all possible IO port pins. */ +typedef enum e_ioport_port_pin_t +{ + IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 +} ioport_port_pin_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl, + ioport_ethernet_channel_t channel, + ioport_ethernet_mode_t mode); +fsp_err_t R_IOPORT_VersionGet(fsp_version_t * p_data); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h new file mode 100644 index 0000000000..97652a2b43 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h @@ -0,0 +1,258 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BLE_ABS BLE_ABS + * @{ + **********************************************************************************************************************/ + +#ifndef RM_BLE_ABS_H +#define RM_BLE_ABS_H + +#include "bsp_api.h" + +#include "rm_ble_abs_cfg.h" +#include "rm_ble_abs_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BLE_ABS_CODE_VERSION_MAJOR (1U) +#define BLE_ABS_CODE_VERSION_MINOR (0U) + +#define BLE_ABS_EVENT_NOTIFY_CONNECTION_START_POS (0) +#define BLE_ABS_EVENT_NOTIFY_ADVERTISING_POS (1) +#define BLE_ABS_EVENT_NOTIFY_SCANNING_POS (2) +#define BLE_ABS_EVENT_NOTIFY_INITIATING_START_POS (3) +#define BLE_ABS_EVENT_NOTIFY_CONNECTION_CLOSE_POS (4) +#define BLE_ABS_EVENT_NOTIFY_ADVERTISING_CLOSE_POS (5) +#define BLE_ABS_EVENT_NOTIFY_SCANNING_CLOSE_POS (6) +#define BLE_ABS_EVENT_NOTIFY_INITIATING_CLOSE_POS (7) +#define BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_START_POS (8) +#define BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP_POS (9) + +#define BLE_EVENT_NOTIFY_ENABLE_VAL ( \ + ((BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_CONNECTION_START_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_CONNECTION_CLOSE_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_ADVERTISING_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_ADVERTISING_CLOSE_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_SCANNING_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_SCANNING_CLOSE_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_INITIATING_START_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_INITIATING_CLOSE_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_START_POS) | \ + ((BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP & 0x1U) << BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP_POS) | \ + (0x0)) + +/** The timer type. */ +typedef enum +{ + BLE_TIMER_ONE_SHOT, /**< One shot timer type */ + BLE_TIMER_PERIODIC /**< Periodic timer type */ +} e_ble_timer_type_t; + +/** The timer callback invoked when the timer expired. */ +typedef void (* ble_abs_timer_cb_t)(uint32_t timer_hdl); + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** advertising set parameters structure */ +typedef struct st_abs_advertising_parameter +{ + union + { + ble_abs_legacy_advertising_parameter_t legacy_advertising_parameter; ///< Legacy advertising parameters. + ble_abs_extend_advertising_parameter_t extend_advertising_parameter; ///< Extended advertising parameters. + ble_abs_non_connectable_advertising_parameter_t non_connectable_advertising_parameter; ///< Non-Connectable advertising parameters. + ble_abs_periodic_advertising_parameter_t periodic_advertising_parameter; ///< Periodic advertising parameters. + } advertising_parameter; ///< Advertising parameters. + + uint32_t advertising_status; ///< Advertising status. + + ble_device_address_t remote_device_address; ///< Remote device address for direct advertising. +} abs_advertising_parameter_t; + +/** scan parameters structure */ +typedef struct st_abs_scan_parameter +{ + ble_abs_scan_parameter_t scan_parameter; ///< Scan parameters. + ble_abs_scan_phy_parameter_t scan_phy_parameter_1M; ///< 1M phy parameters for scan. + ble_abs_scan_phy_parameter_t scan_phy_parameter_coded; ///< Coded phy parameters for scan. */ + uint32_t scan_status; /* Scan status. */ +} abs_scan_parameter_t; + +typedef enum +{ + BLE_TIMER_STATUS_FREE, + BLE_TIMER_STATUS_IDLE, + BLE_TIMER_STATUS_STARTED, + BLE_TIMER_STATUS_EXPIRED, +} ble_abs_timer_status_t; + +typedef struct st_ble_abs_timer +{ + uint8_t status; + uint32_t timer_hdl; + uint32_t timeout_ms; + uint32_t remaining_time_ms; + uint8_t type; + ble_abs_timer_cb_t cb; +} ble_abs_timer_t; + +/** BLE ABS private control block. DO NOT MODIFY. Initialization occurs when RM_BLE_ABS_Open() is called. */ +typedef struct st_ble_abs_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + void const * p_context; ///< Placeholder for user data. Passed to the user callback in ble_abs_callback_args_t. + ble_gap_application_callback_t abs_gap_callback; ///< GAP callback function + ble_vendor_specific_application_callback_t abs_vendor_specific_callback; ///< Vendor specific callback function + uint32_t connection_timer_handle; ///< Cancel a request for connection timer. + uint32_t advertising_timer_handle; ///< Advertising timer for legacy advertising + abs_advertising_parameter_t advertising_sets[BLE_MAX_NO_OF_ADV_SETS_SUPPORTED]; ///< Advertising set information. + abs_scan_parameter_t abs_scan; ///< Scan information. + st_ble_dev_addr_t loc_bd_addr; ///< Local device address. + uint8_t privacy_mode; ///< Privacy mode. + uint32_t set_privacy_status; ///< Local privacy status. + ble_abs_timer_t timer[BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT]; + + uint32_t current_timeout_ms; ///< Current timeout. + uint32_t elapsed_timeout_ms; ///< Elapsed timeout. + + ble_abs_cfg_t const * p_cfg; ///< Pointer to the BLE ABS configuration block. +} ble_abs_instance_ctrl_t; + +/******************************************************************************************************************//** + * @typedef ble_mcu_clock_change_cb_t + * @brief ble_mcu_clock_change_cb_t is the callback function type to use CLKOUT_RF as the MCU main clock source. + * @param none + * @return none + **********************************************************************************************************************/ +typedef void (* ble_mcu_clock_change_cb_t)(void); + +/******************************************************************************************************************//** + * @typedef ble_rf_notify_cb_t + * @brief ble_rf_notify_cb_t is the RF event notify callback function type. + * @param[in] uint32_t The infomation of RF event notification. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_rf_notify_cb_t)(uint32_t); + +/******************************************************************************************************************//** + * @struct st_ble_rf_notify_t + * @brief This structure is RF event notify management. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Set enable/disable of each RF event notification + * @details + * Bit0 Notify Connection event start(0:Disable/1:Enable)\n + * Bit1 Notify Advertising event start(0:Disable/1:Enable)\n + * Bit2 Notify Scanning event start(0:Disable/1:Enable)\n + * Bit3 Notify Initiating event start(0:Disable/1:Enable)\n + * Bit4 Notify Connection event close(0:Disable/1:Enable)\n + * Bit5 Notify Advertising event close(0:Disable/1:Enable)\n + * Bit6 Notify Scanning event close(0:Disable/1:Enable)\n + * Bit7 Notify Initiating event close(0:Disable/1:Enable)\n + * Bit8 Notify RF_DEEP_SLEEP event start(0:Disable/1:Enable)\n + * Bit9 Notify RF_DEEP_SLEEP event close(0:Disable/1:Enable)\n + * Other Bit: Reserved for future use.\n + */ + uint32_t enable; + + /** + * @brief Set callback function pointer for RF event start + */ + ble_rf_notify_cb_t start_cb; + + /** + * @brief Set callback function pointer for RF event close + */ + ble_rf_notify_cb_t close_cb; + + /** + * @brief Set callback function pointer for RF_DEEP_SLEEP + */ + ble_rf_notify_cb_t dsleep_cb; +} st_ble_rf_notify_t; + +/* prototype */ +void r_ble_rf_notify_event_start(uint32_t param); +void r_ble_rf_notify_event_close(uint32_t param); +void r_ble_rf_notify_deep_sleep(uint32_t param); + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ble_abs_api_t g_ble_abs_on_ble; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_Open(ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg); + +fsp_err_t RM_BLE_ABS_Close(ble_abs_ctrl_t * const p_ctrl); + +fsp_err_t RM_BLE_ABS_Reset(ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback); + +fsp_err_t RM_BLE_ABS_VersionGet(fsp_version_t * const p_version); + +fsp_err_t RM_BLE_ABS_StartLegacyAdvertising(ble_abs_ctrl_t * const p_ctrl, + ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter); + +fsp_err_t RM_BLE_ABS_StartExtendedAdvertising(ble_abs_ctrl_t * const p_ctrl, + ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter); + +fsp_err_t RM_BLE_ABS_StartNonConnectableAdvertising( + ble_abs_ctrl_t * const p_ctrl, + ble_abs_non_connectable_advertising_parameter_t const * const p_advertising_parameter); + +fsp_err_t RM_BLE_ABS_StartPeriodicAdvertising(ble_abs_ctrl_t * const p_ctrl, + ble_abs_periodic_advertising_parameter_t const * const p_advertising_parameter); + +fsp_err_t RM_BLE_ABS_StartScanning(ble_abs_ctrl_t * const p_ctrl, + ble_abs_scan_parameter_t const * const p_scan_parameter); + +fsp_err_t RM_BLE_ABS_CreateConnection(ble_abs_ctrl_t * const p_ctrl, + ble_abs_connection_parameter_t const * const p_connection_parameter); + +fsp_err_t RM_BLE_ABS_SetLocalPrivacy(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk, + uint8_t privacy_mode); + +fsp_err_t RM_BLE_ABS_StartAuthentication(ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // RM_BLE_ABS_H + +/*******************************************************************************************************************//** + * @} (end addtogroup BLE_ABS) + **********************************************************************************************************************/ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a new file mode 100644 index 0000000000..44b6a0dd2d Binary files /dev/null and b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a differ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 0000000000..72b1b2c6a8 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,26568 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if __ARM_ARCH_7EM__ + #define RENESAS_CORTEX_M4 + #elif __ARM_ARCH_6M__ + #define RENESAS_CORTEX_M0PLUS + #elif __ARM_ARCH_8M_BASE__ + #define RENESAS_CORTEX_M23 + #elif __ARM_ARCH_8M_MAIN__ + #define RENESAS_CORTEX_M33 + #else + #warning Unsupported Architecture + #endif + +/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */ + #ifdef RENESAS_CORTEX_M4 + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M0PLUS) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M23) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */ + #endif + + #include "system.h" /*!< System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the start time of the pulse output timer in nanoseconds. */ + } STTRU_b; + }; + + union + { + __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the start time of the pulse output timer in nanoseconds. */ + } STTRL_b; + }; + + union + { + __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */ + + struct + { + __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in + * nanoseconds. Set a value that is equivalent to at least + * four cycles of the STCA clock. */ + uint32_t : 2; + } CYCR_b; + }; + + union + { + __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */ + + struct + { + __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse + * signal from the timer in nanoseconds. Set a value that + * is equivalent to at least two cycles of the STCA clock. */ + uint32_t : 3; + } PLSR_b; + }; +} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRU_b; + }; + + union + { + __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRL_b; + }; +} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + */ +typedef struct +{ + union + { + __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + uint16_t : 13; + } C_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: + * The low-order 2 bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination.NOTE: The low-order + * 2 bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } CTL_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[63]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + __IM uint32_t RESERVED3[63]; + __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ +} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) + */ +typedef struct +{ + union + { + __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + + struct + { + uint16_t : 2; + __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ + __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ + __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ + __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ + __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ + __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ + uint16_t : 4; + __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ + __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit + * is read as 1. The write value should be 1.) */ + __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ + __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ + } R_b; + }; + __IM uint16_t RESERVED; +} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) + */ +typedef struct +{ + __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ + __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ + __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ +} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ + +/** + * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ + + struct + { + __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ + uint8_t : 3; + } P_b; + }; + + union + { + __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ + + struct + { + __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ + uint8_t : 3; + } N_b; + }; +} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..11]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 2; + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 2; + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 4; + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint16_t RESERVED2[7]; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + __IM uint16_t RESERVED3[9]; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + __IM uint16_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 13; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + __IM uint16_t RESERVED6; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[23]; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED17; + __IM uint16_t RESERVED18; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[82]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + uint16_t : 4; + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + uint16_t : 4; + } ADPGAGS0_b; + }; + __IM uint16_t RESERVED21[6]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 2; + } ADPGADCR0_b; + }; +} R_ADC0_Type; /*!< Size = 434 (0x1b2) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + uint16_t : 15; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; +} R_CTSU_Type; /*!< Size = 30 (0x1e) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU2) + */ + +typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ +{ + union + { + union + { + __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ + __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ + __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ + __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */ + __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */ + __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ + __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ + __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ + __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ + __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ + __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ + __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ + __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */ + __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ + __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ + __IOM uint32_t FCMODE : 1; /*!< [23..23] CTSU SUCLK Control */ + __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ + __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ + __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ + } CTSUCRA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ + }; + }; + __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ + __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */ + __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */ + __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */ + uint32_t : 8; + __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */ + uint32_t : 1; + __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */ + uint32_t : 2; + } CTSUCRB_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ + }; + }; + + union + { + __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ + + struct + { + __IM uint8_t RESERVED; + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ + uint32_t : 2; + __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ + uint32_t : 2; + __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ + uint32_t : 12; + } CTSUMCH_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ + }; + }; + + union + { + __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ + uint32_t : 2; + __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ + } CTSUCHACA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + + struct + { + __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ + uint32_t : 28; + } CTSUCHACB_b; + }; + __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ + uint32_t : 2; + __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ + } CTSUCHTRCA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + + struct + { + __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ + uint32_t : 28; + } CTSUCHTRCB_b; + }; + __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + }; + + union + { + union + { + __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ + uint32_t : 3; + __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ + __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ + __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ + __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ + uint32_t : 1; + __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ + __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ + uint32_t : 1; + __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ + __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ + uint32_t : 10; + } CTSUSR_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ + }; + }; + + union + { + __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ + __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ + __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ + uint32_t : 2; + __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */ + __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ + } CTSUSO_b; + }; + + struct + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + + struct + { + __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ + uint32_t : 16; + } CTSUSCNT_b; + }; + __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + }; + + union + { + union + { + __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */ + __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Calibration Setting Bit 1 */ + uint32_t : 2; + __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */ + __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Calibration Setting Bit 2 */ + uint32_t : 1; + __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */ + __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */ + __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */ + uint32_t : 10; + __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */ + uint32_t : 2; + __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */ + uint32_t : 1; + __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */ + __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */ + __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */ + __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */ + uint32_t : 1; + } CTSUCALIB_b; + }; + + struct + { + __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + }; + }; + + union + { + __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + + struct + { + __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + + struct + { + __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKB_b; + }; + + struct + { + __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + + struct + { + __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ + uint32_t : 16; + } CTSUCFCCNT_b; + }; + __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + }; +} R_CTSU2_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 8-Bit D/A Converter (R_DAC8) + */ + +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ +{ + union + { + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + + struct + { + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + + struct + { + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + + struct + { + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; + }; + + union + { + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; + }; +} R_DAC8_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_DALI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Digital Addressable Lighting Interface (R_DALI0) + */ + +typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */ +{ + union + { + __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register + * 1 */ + + struct + { + __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing + * violation threshold value 1.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 1; + __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing + * violation threshold value 2.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR1_b; + }; + + union + { + __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register + * 2 */ + + struct + { + __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing + * violation threshold value 3.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing + * violation threshold value 4.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR2_b; + }; + + union + { + __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register + * 3 */ + + struct + { + __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing + * violation threshold value 5.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 8; + } BTVTHR3_b; + }; + + union + { + __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register + * 4 */ + + struct + { + __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing + * violation threshold value 6.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 7; + } BTVTHR4_b; + }; + + union + { + __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */ + + struct + { + __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold + * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold + * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + } COLTHR1_b; + }; + + union + { + __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */ + + struct + { + __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold + * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold + * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR2_b; + }; + + union + { + __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */ + + struct + { + __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold + * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold + * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR3_b; + }; + + union + { + __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */ + + struct + { + __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold + * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold + * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + } COLTHR4_b; + }; + + union + { + __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */ + + struct + { + __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold + * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 8; + } COLTHR5_b; + }; + + union + { + __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */ + + struct + { + __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */ + __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */ + uint16_t : 2; + __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */ + uint16_t : 1; + } CNFR1_b; + }; + + union + { + __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */ + + struct + { + __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only + * when the DALI0.STR1.BBF bit is 0. */ + uint16_t : 10; + } CNFR2_b; + }; + + union + { + __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */ + + struct + { + __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */ + uint16_t : 9; + } TXWR1_b; + }; + __IM uint16_t RESERVED[3]; + + union + { + __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */ + + struct + { + __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */ + } TDR1H_b; + }; + + union + { + __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */ + + struct + { + __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */ + } TDR1L_b; + }; + + union + { + __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */ + + struct + { + __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */ + uint16_t : 15; + } TRSTR1_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */ + + struct + { + __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */ + __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */ + uint16_t : 6; + __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */ + __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */ + __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */ + __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */ + __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */ + uint16_t : 3; + } CTR1_b; + }; + + union + { + __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */ + + struct + { + __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + uint16_t : 14; + } TXDCTR1_b; + }; + __IM uint16_t RESERVED2[2]; + + union + { + __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */ + + struct + { + __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */ + } RDR1H_b; + }; + + union + { + __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */ + + struct + { + __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */ + } RDR1L_b; + }; + + union + { + __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */ + + struct + { + __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */ + __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */ + __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */ + __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */ + __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */ + __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */ + __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */ + __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */ + __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */ + __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */ + __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length + * for data received successfully */ + } STR1_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */ + + struct + { + __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */ + __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */ + uint16_t : 5; + __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */ + __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after + * the DRX0 pin is synchronized */ + __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */ + __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */ + uint16_t : 2; + } COLR1_b; + }; + __IM uint16_t RESERVED4; + + union + { + __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */ + + struct + { + __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */ + __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */ + __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */ + __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */ + __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */ + __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF + * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */ + __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */ + __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */ + __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */ + __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */ + uint16_t : 6; + } FECR1_b; + }; + + union + { + __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */ + + struct + { + __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software + * reset. */ + uint16_t : 15; + } SWRR1_b; + }; +} R_DALI0_Type; /*!< Size = 62 (0x3e) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 6; + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; +} R_DMA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + uint16_t : 2; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + uint16_t : 1; + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + uint16_t : 1; + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED3; +} R_DMAC0_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; +} R_DRW_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; +} R_DTC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ +} R_ELC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + */ + +typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +{ + union + { + __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ + __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ + uint32_t : 14; + } SYSR_b; + }; + + union + { + __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ + __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ + uint32_t : 14; + } SYIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address. */ + uint32_t : 8; + } SYMACRU_b; + }; + + union + { + __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the local MAC address. */ + uint32_t : 8; + } SYMACRL_b; + }; + + union + { + __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ + + struct + { + __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the + * control field in the LLC sublayer when generating IEEE802.3 + * frames. */ + uint32_t : 24; + } SYLLCCTLR_b; + }; + + union + { + __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + + struct + { + __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ + } SYIPADDRR_b; + }; + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + + struct + { + __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the + * versionPTP field value of the PTP v2 header.When a message + * is received, this value is compared with the versionPTP + * field of the received frame.In generating messages, the + * value is used for the versionPTP field of the frame for + * transmission.Set these bits to 0010b (PTP v2). */ + __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set + * the transportSpecific field value of the PTP v2 header.When + * a message is received, this value is compared with the + * transportSpecific field of the received frame.In generating + * messages, the value is used for the transportSpecific field + * of the frame for transmission.Set these bits to 0000b (IEEE + * 1588). */ + uint32_t : 24; + } SYSPVRR_b; + }; + + union + { + __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + + struct + { + __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to + * set the domainNumber field value of the PTP v2 header.When + * a message is received, this value is compared with the + * domainNumber field of the received frame as a condition + * for PTP reception processing.In generating messages, the + * value is used for the domainNumber field of the frame for + * transmission. */ + uint32_t : 24; + } SYDOMR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + + struct + { + __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the + * leap61 member of timePropertiesDS. */ + __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the + * leap59 member of timePropertiesDS. */ + __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical + * value of the currentUtcOffsetValid member of timePropertiesDS. */ + __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value + * of the ptpTimescale member of timePropertiesDS. */ + __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value + * of the timeTraceable member of timePropertiesDS. */ + __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical + * value of the frequencyTraceable member of timePropertiesDS. */ + uint32_t : 2; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + uint32_t : 1; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } ANFR_b; + }; + + union + { + __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } SYNFR_b; + }; + + union + { + __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRQFR_b; + }; + + union + { + __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRPFR_b; + }; + + union + { + __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of your port. */ + } SYCIDRU_b; + }; + + union + { + __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of your port. */ + } SYCIDRL_b; + }; + + union + { + __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting + * for the port number of the local port. */ + uint32_t : 16; + } SYPNUMR_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + + struct + { + __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ + __OM uint32_t STUP : 1; /*!< [1..1] State Update */ + __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ + uint32_t : 29; + } SYRVLDR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + + struct + { + __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ + __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ + uint32_t : 2; + __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ + __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ + __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ + uint32_t : 1; + __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ + __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ + __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ + uint32_t : 1; + __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ + __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ + __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ + __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ + __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ + uint32_t : 1; + } SYRFL1R_b; + }; + + union + { + __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + + struct + { + __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ + __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ + uint32_t : 2; + __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ + __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ + uint32_t : 22; + __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ + __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ + uint32_t : 2; + } SYRFL2R_b; + }; + + union + { + __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + + struct + { + __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ + uint32_t : 19; + } SYTRENR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of the master clock. */ + } MTCIDU_b; + }; + + union + { + __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of the master clock. */ + } MTCIDL_b; + }; + + union + { + __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the + * setting for the port number of the master clock. */ + uint32_t : 16; + } MTPID_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + + struct + { + __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits + * set the interval for the transmission of Announce messages. */ + __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits + * set the interval for the transmission of Sync messages. + * The setting is also placed in the logMessageInterval field + * of transmitted Sync messages. */ + __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req + * Transmission Interval SettingThe bits set the average interval + * for the transmission of Delay_Req messages and the interval + * for the transmission of Pdelay_Req messages.The setting + * is also placed in the logMessageInterval field of Delay_Resp + * messages. */ + uint32_t : 8; + } SYTLIR_b; + }; + + union + { + __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication + * Register */ + + struct + { + __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Announce message. */ + __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Sync message. */ + __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Delay_Resp message. */ + uint32_t : 8; + } SYRLIR_b; + }; + + union + { + __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated offsetFromMaster value. */ + } OFMRU_b; + }; + + union + { + __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * offsetFromMaster value. */ + } OFMRL_b; + }; + + union + { + __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated meanPathDelay value. */ + } MPDRU_b; + }; + + union + { + __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * meanPathDelay value. */ + } MPDRL_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + + struct + { + __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are + * used to set the value of the grandmasterPriority2 fields + * of Announce messages. */ + uint32_t : 8; + __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits + * are used to set the value of the grandmasterPriority1 fields + * of Announce messages. */ + uint32_t : 8; + } GMPR_b; + }; + + union + { + __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + + struct + { + __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality + * fields of Announce messages. The correspondence between + * bits and the grandmasterClockQuality fields is as listed + * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 + * to b0: offsetScaledLogVariance */ + } GMCQR_b; + }; + + union + { + __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the value of the grandmasterIdentity fields of + * Announce messages. */ + } GMIDRU_b; + }; + + union + { + __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the value of the grandmasterIdentity fields of Announce + * messages. */ + } GMIDRL_b; + }; + + union + { + __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + + struct + { + __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the + * timeSource fields of Announce messages. */ + uint32_t : 8; + __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value + * of the currentUtcOffset fields of Announce messages. */ + } CUOTSR_b; + }; + + union + { + __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + + struct + { + __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value + * of the stepsRemoved fields of Announce messages. */ + uint32_t : 16; + } SRR_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRU_b; + }; + + union + { + __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRL_b; + }; + + union + { + __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRU_b; + }; + + union + { + __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRL_b; + }; + + union + { + __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + + struct + { + __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the + * setting for the EtherType field value for frames in the + * Ethernet II format. */ + uint32_t : 16; + } PETYPER_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPprimary messages. */ + } PPIPR_b; + }; + + union + { + __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPpdelay messages. */ + } PDIPR_b; + }; + + union + { + __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + + struct + { + __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold + * the setting for the value of the TOS field within the IPv4 + * headers of PTP event messages. */ + uint32_t : 24; + } PETOSR_b; + }; + + union + { + __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + + struct + { + __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits + * hold the setting for the value of the TOS field within + * the IPv4 headers of PTP general messages. */ + uint32_t : 24; + } PGTOSR_b; + }; + + union + { + __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + + struct + { + __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits + * hold the setting for the value of the TTL field within + * the IPv4 headers of PTP-primary messages. */ + uint32_t : 24; + } PPTTLR_b; + }; + + union + { + __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + + struct + { + __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the + * setting for the value of the TTL field within the IPv4 + * headers of PTP-pdelay messages. */ + uint32_t : 24; + } PDTTLR_b; + }; + + union + { + __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese + * bits hold the setting for the value of the destination + * port number field within the UDP headers of PTP event messages. */ + uint32_t : 16; + } PEUDPR_b; + }; + + union + { + __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits + * hold the setting for the value of the destination port + * number field within the UDP headers of PTP general messages. */ + uint32_t : 16; + } PGUDPR_b; + }; + + union + { + __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these + * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ + __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0 and ENB=1. */ + __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0. */ + uint32_t : 13; + __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ + uint32_t : 15; + } FFLTR_b; + }; + __IM uint32_t RESERVED10[31]; + + union + { + __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the asymmetric delay value. */ + uint32_t : 16; + } DASYMRU_b; + }; + + union + { + __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the asymmetric delay value. */ + } DASYMRL_b; + }; + + union + { + __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + + struct + { + __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the input + * ports. */ + __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the output + * ports. */ + } TSLATR_b; + }; + + union + { + __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + + struct + { + __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are + * used to set the time from the completion of one transmission + * to the start of the next in cycles of the transmission + * clock. A value n in these bits means that a transmission + * interval of n cycles will be secured.No interval is secured + * if the setting is 00h.We recommend the setting 28h (40 + * cycles). */ + uint32_t : 4; + __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ + uint32_t : 3; + __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ + uint32_t : 3; + __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ + uint32_t : 11; + } SYCONFR_b; + }; + + union + { + __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + + struct + { + __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ + __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ + uint32_t : 30; + } SYFORMR_b; + }; + + union + { + __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + + struct + { + __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response + * message not being received within n x 1024 (ns), where + * n is the setting, is judged to represent a timeout. */ + } RSTOUTR_b; + }; +} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) + */ + +typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ +{ + union + { + __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + + struct + { + __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ + uint32_t : 31; + } PTRSTR_b; + }; + + union + { + __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + + struct + { + __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ + uint32_t : 5; + __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ + uint32_t : 21; + } STCSELR_b; + }; + + union + { + __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + + struct + { + __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ + uint32_t : 15; + __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ + uint32_t : 15; + } BYPASS_b; + }; +} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + */ + +typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +{ + union + { + __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + + struct + { + __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ + __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ + __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ + __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ + uint32_t : 10; + } MIESR_b; + }; + + union + { + __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + + struct + { + __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ + __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ + __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ + __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt + * Request Permission */ + uint32_t : 10; + } MIEIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission + * Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + } ELIPPR_b; + }; + + union + { + __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic + * Clearing Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ + uint32_t : 7; + } ELIPACR_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ + __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ + uint32_t : 27; + } STSR_b; + }; + + union + { + __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ + __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ + uint32_t : 27; + } STIPR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + + struct + { + __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ + uint32_t : 30; + } STCFR_b; + }; + + union + { + __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + + struct + { + __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ + uint32_t : 5; + __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ + uint32_t : 1; + __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ + __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ + __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ + uint32_t : 4; + __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ + __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ + uint32_t : 2; + } STMR_b; + }; + + union + { + __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + + struct + { + __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), + * where n is the setting, leads to a timeout for reception + * of Sync messages, leading to the STSR.SYNTOUT flag being + * set to 1. */ + } SYNTOR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ + __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ + __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ + __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ + __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ + __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ + uint32_t : 26; + } IPTSELR_b; + }; + + union + { + __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ + uint32_t : 26; + } MITSELR_b; + }; + + union + { + __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + + struct + { + __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ + __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ + __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ + __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ + __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ + __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ + uint32_t : 26; + } ELTSELR_b; + }; + + union + { + __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + + struct + { + __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the + * value of this bit while the SYNSTARTR.STR bit is 1. */ + uint32_t : 31; + } STCHSELR_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + + struct + { + __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ + uint32_t : 31; + } SYNSTARTR_b; + }; + + union + { + __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive + * Register */ + + struct + { + __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ + uint32_t : 31; + } LCIVLDR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of loss of synchronization. */ + } SYNTDARU_b; + }; + + union + { + __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of loss of synchronization. */ + } SYNTDARL_b; + }; + + union + { + __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of synchronization. */ + } SYNTDBRU_b; + }; + + union + { + __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of synchronization. */ + } SYNTDBRL_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the integer portion of the initial value for the + * local timer counter. */ + uint32_t : 16; + } LCIVRU_b; + }; + + union + { + __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the integer portion of the initial value for the local + * timer counter. */ + } LCIVRM_b; + }; + + union + { + __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion + * of the initial value of the local timer counter in nanoseconds. */ + } LCIVRL_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + + struct + { + __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ + uint32_t : 31; + } GETW10R_b; + }; + + union + { + __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the positive gradient. */ + uint32_t : 1; + } PLIMITRU_b; + }; + + union + { + __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the positive gradient. */ + } PLIMITRM_b; + }; + + union + { + __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the positive gradient. */ + } PLIMITRL_b; + }; + + union + { + __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the negative gradient. */ + uint32_t : 1; + } MLIMITRU_b; + }; + + union + { + __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the negative gradient. */ + } MLIMITRM_b; + }; + + union + { + __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the negative gradient. */ + } MLIMITRL_b; + }; + + union + { + __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + + struct + { + __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching + * is directed, values of various statistical information + * read before completion of information fetching are not + * guaranteed. */ + uint32_t : 31; + } GETINFOR_b; + }; + __IM uint32_t RESERVED8[11]; + + union + { + __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits + * of the integer portion of the local timer counter's value. */ + uint32_t : 16; + } LCCVRU_b; + }; + + union + { + __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the integer portion of the local timer counter's value. */ + } LCCVRM_b; + }; + + union + { + __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of + * the local timer counter's value (in nanoseconds). */ + } LCCVRL_b; + }; + __IM uint32_t RESERVED9[37]; + + union + { + __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the positive gradient value. */ + } PW10VRU_b; + }; + + union + { + __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the positive gradient value. */ + } PW10VRM_b; + }; + + union + { + __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the positive gradient value. */ + } PW10VRL_b; + }; + __IM uint32_t RESERVED10[45]; + + union + { + __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the negative gradient value. */ + } MW10RU_b; + }; + + union + { + __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the negative gradient value. */ + } MW10RM_b; + }; + + union + { + __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the negative gradient value. */ + } MW10RL_b; + }; + __IM uint32_t RESERVED11[9]; + __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ + __IM uint32_t RESERVED12[7]; + + union + { + __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + + struct + { + __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ + __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ + __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ + __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ + __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ + __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ + uint32_t : 26; + } TMSTARTR_b; + }; + __IM uint32_t RESERVED13[32]; + + union + { + __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ + __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ + uint32_t : 2; + } PRSR_b; + }; + + union + { + __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ + __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ + uint32_t : 2; + } PRIPR_b; + }; + __IM uint32_t RESERVED14[2]; + __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ + + union + { + __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + + struct + { + __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ + uint32_t : 30; + } TRNDISR_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + + struct + { + __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ + uint32_t : 7; + __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ + __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ + uint32_t : 22; + } TRNMR_b; + }; + + union + { + __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + + struct + { + __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read + * data from the relay FIFO in cut-through mode (specified + * as the number of bytes)NOTE1: A value cannot be set in + * the lower-order 2 bits. These bits are fixed to 0.NOTE2: + * A value of less than 96 bytes cannot be set. */ + uint32_t : 21; + } TRNCTTDR_b; + }; +} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is "1". Writing to these bits in FRDY = "0" is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in "Blank Check" command. These + * bits can be written when FRDY bit of FSTATR register is + * "1". Writing to these bits in FRDY = "0" is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[18]; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 2; + __IM uint32_t TBLCRCT : 1; /*!< [2..2] Table Area ECC 1-Bit Error Correction Monitoring Bit */ + __IM uint32_t TBLDTCT : 1; /*!< [3..3] Table Area ECC 2-Bit Error Detection Monitoring Bit */ + __IM uint32_t CFGCRCT : 1; /*!< [4..4] Config Area ECC 1-Bit Error Correction Monitoring Bit */ + __IM uint32_t CFGDTCT : 1; /*!< [5..5] Config Area ECC 2-Bit Error Detection Monitoring Bit */ + __IM uint32_t FHVEERR : 1; /*!< [6..6] "fhve" Error */ + __IM uint32_t FCUERR : 1; /*!< [7..7] FCU Error */ + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + __IM uint32_t OTPCRCT : 1; /*!< [16..16] OTP Bit ECC 1-Bit Error Correction Monitoring Bit */ + __IM uint32_t OTPDTCT : 1; /*!< [17..17] OTP Bit ECC 2-Bit Error Detection Monitoring Bit */ + __IM uint32_t EBFULL : 1; /*!< [18..18] FDMYECC Buffer Full */ + uint32_t : 13; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED17; + __IM uint16_t RESERVED18; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in "Blank Check" + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and "Config Clear" + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED21; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is "1". + * Writing to this bit in FRDY = "0" is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED22; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED23; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_FCACHE_Type; /*!< Size = 288 (0x120) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + uint32_t : 7; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + uint32_t : 8; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + uint32_t : 8; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 5; + __IOM uint32_t TPCS : 3; /*!< [26..24] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + uint32_t : 1; + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + uint32_t : 1; + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; +} R_GPT0_Type; /*!< Size = 164 (0xa4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + uint16_t : 3; + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + uint16_t : 3; + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + uint16_t : 3; + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + uint16_t : 3; + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + __IM uint32_t RESERVED10[23]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED13[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief JPEG Codec (R_JPEG) + */ + +typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +{ + union + { + __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ + + struct + { + __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ + __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between + * processing for compression and for decompression, be sure + * to reset this module in advance by setting the JCUSRST + * bit in the software reset control register 2 (SWRSTCR2) + * of the power-downmodes. */ + uint8_t : 4; + } JCMOD_b; + }; + + union + { + __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ + + struct + { + __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, + * set this bit to 1. Do not write this bit to 1 again while + * this module is in operation. */ + __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped + * state caused by requests to read the image size and pixel + * format (enabled by the INT3 bit in JINTE0), set this bit + * to 1. */ + __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only + * for the interrupt sources corresponding to bits INS6, INS5, + * and INS3 in JINTS0. To clear an interrupt request, set + * this bit to 1 */ + uint8_t : 4; + __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the + * bus reset command should not be issued. */ + } JCCMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + + struct + { + __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component + * NOTE: Read-only in Decompression. */ + uint8_t : 2; + } JCQTN_b; + }; + + union + { + __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + + struct + { + __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: + * Read-only in Decompression. */ + uint8_t : 2; + } JCHTN_b; + }; + + union + { + __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + + struct + { + __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRIU_b; + }; + + union + { + __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ + + struct + { + __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRID_b; + }; + + union + { + __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + + struct + { + __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZU_b; + }; + + union + { + __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + + struct + { + __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZD_b; + }; + + union + { + __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + + struct + { + __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZU_b; + }; + + union + { + __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + + struct + { + __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZD_b; + }; + + union + { + __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + + struct + { + __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed + * The values of this register are reset before compression + * starts.NOTE: Read-only in Decompression. */ + } JCDTCU_b; + }; + + union + { + __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + + struct + { + __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts. + * NOTE: Read-only in Decompression. */ + } JCDTCM_b; + }; + + union + { + __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + + struct + { + __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts.NOTE: + * Read-only in Decompression. */ + } JCDTCD_b; + }; + + union + { + __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it + * has been determined that the image size and the subsampling + * setting of the compressed data can be read through analyzing + * the data. */ + uint8_t : 1; + __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the + * final number of MCU data in the Huffman-coding segment + * is not correct in decompression. When this bit is not set + * to enable interrupt generation, an error code is not returned. */ + __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the + * total number of data in the Huffman-coding segment is not + * correct in decompression. When this bit is not set to enable + * interrupt generation, an error code is not returned. */ + __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the + * number of data in the restart interval of the Huffman-coding + * segment is not correct in decompression.When this bit is + * not set to enable interrupt generation, an error code is + * not returned. */ + } JINTE0_b; + }; + + union + { + __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format + * can be read. When an interrupt occurs, this module stops + * processing and the state is indicated by the JCRST register. + * To make this module resume processing, set the JPEG core + * process stop clear command bit (JRST) in JCCMD. */ + uint8_t : 1; + __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ + __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression + * process normally. */ + uint8_t : 1; + } JINTS0_b; + }; + + union + { + __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + + struct + { + __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error + * which has occurred in the compressed data analysis for + * decompression. */ + uint8_t : 4; + } JCDERR_b; + }; + + union + { + __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + + struct + { + __IM uint8_t RST : 1; /*!< [0..0] Operating State */ + uint8_t : 7; + } JCRST_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[11]; + + union + { + __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + + struct + { + __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ + uint32_t : 1; + __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ + __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the input of image + * data lines is on. Setting this bit to 1 resumes reading + * input image data. This bit is always read as 0. */ + __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data + * Lines This bit is only valid when the count mode for stopping + * the input of image data lines is on. Set this bit before + * writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression + * is swapped. */ + uint32_t : 21; + } JIFECNT_b; + }; + + union + { + __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + + struct + { + __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFESA_b; + }; + + union + { + __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + + struct + { + __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower + * three bits should be set to 0. */ + uint32_t : 17; + } JIFESOFST_b; + }; + + union + { + __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address + * Register */ + + struct + { + __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFEDA_b; + }; + + union + { + __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count + * Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line + * units) The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFESLC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ + + struct + { + __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is + * swapped. */ + uint32_t : 1; + __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ + __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the output of image + * data lines is on. Setting this bit to 1 resumes writing + * image data. This bit is always read as 0. */ + __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image + * Data Lines This bit is only valid when the count mode for + * stopping the output of image data lines is on. Set this + * bit before writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression + * is swapped. */ + uint32_t : 1; + __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ + __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only + * when the count mode for stopping the input of coded data + * is on. Setting this bit to 1 resumes reading input coded + * data. This bit is always read as 0. */ + __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed + * This bit is only valid when the count mode for stopping + * the input of coded data is on. Set this bit before writing + * 1 to the data resume command bit. */ + uint32_t : 9; + __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ + __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output + * image data. */ + __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image + * data. */ + uint32_t : 2; + } JIFDCNT_b; + }; + + union + { + __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + + struct + { + __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source + * Address (in 8-byte units) The lower three bits should be + * set to 0. */ + } JIFDSA_b; + }; + + union + { + __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + + struct + { + __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + uint32_t : 17; + } JIFDDOFST_b; + }; + + union + { + __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address + * Register */ + + struct + { + __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) + * The lower three bits should be set to 0. */ + } JIFDDA_b; + }; + + union + { + __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count + * Register */ + + struct + { + __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) + * The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFDSDC_b; + }; + + union + { + __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line + * Count Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three + * bits should be set to 0. These bits are read as0.Number + * of input image data lines to be read, in 8-line units. */ + uint32_t : 16; + } JIFDDLC_b; + }; + + union + { + __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + + struct + { + __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + uint32_t : 24; + } JIFDADT_b; + }; + __IM uint32_t RESERVED4[6]; + + union + { + __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DOUTLF bit in JINTS1 is set to + * 1 */ + __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt + * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ + __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ + uint32_t : 2; + __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ + __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt + * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ + uint32_t : 25; + } JINTE1_b; + }; + + union + { + __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number + * of lines of output image data indicated by JIFDDLC have + * been written. This bit is only valid when the DOUTLC bit + * in JIFDCNT is set to 1. */ + __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data + * indicated by JIFDSDC is read in decompression. This bit + * is valid only when the JINC bit in JIFDCNT is set to 1. */ + __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data + * is written in decompression. */ + uint32_t : 2; + __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data + * lines indicated by JIFESLC is read in compression. This + * bit is valid only when the DINLC bit in JIFECNT is set + * to 1. */ + __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data + * is written in compression. */ + uint32_t : 25; + } JINTS1_b; + }; + __IM uint32_t RESERVED5[27]; + __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ + __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ + __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ + __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ + __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ + __IM uint32_t RESERVED6; + __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[11]; + __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ + __IM uint32_t RESERVED9; + __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ + __IM uint16_t RESERVED10; +} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Slave MPU (R_MPU_SMPU) + */ + +typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ +{ + union + { + __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting + * of the PROTECT and OAD bit. */ + } SMPUCTL_b; + }; + __IM uint16_t RESERVED[7]; + __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ +} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000000) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] I2C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000004) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + uint32_t : 8; + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 13; + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x00000008) Module Stop Control Register D */ + + struct + { + uint32_t : 2; + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT ch0 Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT ch6 - ch1 Module Stop */ + uint32_t : 7; + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 7; + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; +} R_MSTP_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Operational Amplifier (R_OPAMP) + */ + +typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */ +{ + __IM uint8_t RESERVED[8]; + + union + { + __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ + + struct + { + __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ + uint8_t : 4; + __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ + } AMPMC_b; + }; + + union + { + __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + + struct + { + __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger + * control */ + } AMPTRM_b; + }; + + union + { + __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select + * Register */ + + struct + { + __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the + * AMPTRS register after setting the AMPTRM register. */ + uint8_t : 6; + } AMPTRS_b; + }; + + union + { + __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ + + struct + { + __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ + __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ + __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ + __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ + uint8_t : 3; + __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference + * current circuit */ + } AMPC_b; + }; + + union + { + __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + + struct + { + __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ + __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ + __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ + __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ + uint8_t : 4; + } AMPMON_b; + }; + __IM uint8_t RESERVED1; + __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier + * [0..3] */ + + union + { + __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control + * register */ + + struct + { + __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ + __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ + __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ + uint8_t : 5; + } AMPCPC_b; + }; + __IM uint8_t RESERVED2[4]; + + union + { + __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable + * Register */ + + struct + { + __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ + __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ + __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ + uint8_t : 5; + } AMPUOTE_b; + }; + __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ +} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Data Capture Unit (R_PDC) + */ + +typedef struct /*!< (@ 0x40094000) R_PDC Structure */ +{ + union + { + __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + + struct + { + __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ + __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ + __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ + __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ + __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ + __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ + __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ + __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ + __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ + __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ + __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ + __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ + __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ + uint32_t : 17; + } PCCR0_b; + }; + + union + { + __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + + struct + { + __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ + uint32_t : 31; + } PCCR1_b; + }; + + union + { + __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + + struct + { + __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ + __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ + __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ + __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ + __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ + __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ + __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ + uint32_t : 25; + } PCSR_b; + }; + + union + { + __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + + struct + { + __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ + __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ + uint32_t : 30; + } PCMONR_b; + }; + + union + { + __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + + struct + { + __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the + * storage of captured data. The PCDR register is a 4-byte + * space to which the FIFO is mapped, and four bytes of data + * are read from the PCDR register at a time. */ + } PCDR_b; + }; + + union + { + __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + + struct + { + __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line + * where capture is to start. */ + uint32_t : 4; + __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ + uint32_t : 4; + } VCR_b; + }; + + union + { + __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + + struct + { + __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position + * in bytes where capture is to start. */ + uint32_t : 4; + __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture + * horizontally. */ + uint32_t : 4; + } HCR_b; + }; +} R_PDC_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[12]; /*!< (@ 0x00000000) Port [0..11] */ +} R_PFS_Type; /*!< Size = 768 (0x300) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; +} R_PMISC_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + uint8_t : 1; + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 5; + } SPTR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; +} R_SCI0_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_SDADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_SDADC0 (R_SDADC0) + */ + +typedef struct /*!< (@ 0x4009C000) R_SDADC0 Structure */ +{ + union + { + __IOM uint16_t STC1; /*!< (@ 0x00000000) Startup Control Register 1 */ + + struct + { + __IOM uint16_t CLKDIV : 4; /*!< [3..0] SDADC24 Reference Clock Division */ + uint16_t : 3; + __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select */ + __IOM uint16_t VSBIAS : 4; /*!< [11..8] Reference voltage select */ + uint16_t : 3; + __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select */ + } STC1_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t STC2; /*!< (@ 0x00000004) Startup Control Register 2 */ + + struct + { + __IOM uint8_t BGRPON : 1; /*!< [0..0] BGR part power control */ + __IOM uint8_t ADCPON : 1; /*!< [1..1] ADREG forced power-down */ + __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part */ + uint8_t : 5; + } STC2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint32_t PGAC[5]; /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register */ + + struct + { + __IOM uint32_t PGAGC : 5; /*!< [4..0] Gain selection of a programmable gain instrumentation + * amplifier ( Gset1, Gset2, Gtotal ) */ + __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select */ + __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select */ + uint32_t : 1; + __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select */ + __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select */ + __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged */ + __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing */ + __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select */ + uint32_t : 1; + __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable */ + __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of + * A/D conversions in ADSCAN */ + } PGAC_b[5]; + }; + + union + { + __IOM uint32_t ADC1; /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1 */ + + struct + { + __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode */ + uint32_t : 3; + __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal */ + uint32_t : 3; + __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer */ + uint32_t : 3; + __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection */ + __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting */ + uint32_t : 2; + __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable */ + uint32_t : 11; + } ADC1_b; + }; + + union + { + __IOM uint8_t ADC2; /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2 */ + + struct + { + __IOM uint8_t SDADST : 1; /*!< [0..0] Control of A/D conversion */ + uint8_t : 7; + } ADC2_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint32_t ADCR; /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register */ + + struct + { + __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result */ + __IM uint32_t SDADCRS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADCRC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADCR_b; + }; + + union + { + __IM uint32_t ADAR; /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register */ + + struct + { + __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value */ + __IM uint32_t SDADMVS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADMVC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADAR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t CLBC; /*!< (@ 0x00000030) Calibration Control Register */ + + struct + { + __IOM uint8_t CLBMD : 2; /*!< [1..0] These bits are read as 0. The write value should be 0. */ + uint8_t : 6; + } CLBC_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t CLBSTR; /*!< (@ 0x00000034) Calibration Start Control Register */ + + struct + { + __IOM uint8_t CLBST : 1; /*!< [0..0] Calibration start control */ + uint8_t : 7; + } CLBSTR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IM uint8_t CLBSSR; /*!< (@ 0x0000003C) Calibration Status Register */ + + struct + { + __IM uint8_t CLBSS : 1; /*!< [0..0] Calibration status */ + uint8_t : 7; + } CLBSSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; +} R_SDADC0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Segment LCD Controller/Driver (R_SLCDC) + */ + +typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */ +{ + union + { + __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */ + + struct + { + __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */ + __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */ + __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */ + __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */ + } LCDM0_b; + }; + + union + { + __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */ + + struct + { + __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */ + uint8_t : 2; + __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */ + __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */ + __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation + * enable/disable */ + __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */ + __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */ + } LCDM1_b; + }; + + union + { + __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */ + + struct + { + __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */ + uint8_t : 2; + } LCDC0_b; + }; + + union + { + __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */ + + struct + { + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 3; + } VLCD_b; + }; + __IM uint8_t RESERVED[252]; + + union + { + __IOM uint8_t SEG[38]; /*!< (@ 0x00000100) LCD Display Data Array */ + + struct + { + __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */ + __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */ + } SEG_b[38]; + }; +} R_SLCDC_Type; /*!< Size = 294 (0x126) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + uint8_t : 4; + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + uint8_t : 1; + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + uint8_t : 2; + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + uint8_t : 3; + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint8_t : 7; + } SPDCR2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_SPI0_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + + struct + { + __IOM uint8_t ECCRAMWRWTEN : 1; /*!< [0..0] ECCRAM Write Wait Enable */ + __IOM uint8_t ECCRAMRDWTEN : 1; /*!< [1..1] ECCRAM Read wait enable */ + __IOM uint8_t SRAM0WTEN : 1; /*!< [2..2] SRAM0 Wait Enable */ + __IOM uint8_t SRAM1WTEN : 1; /*!< [3..3] SRAM1 Wait Enable */ + __IOM uint8_t SRAMHSWTEN : 1; /*!< [4..4] SRAMHS Wait Enable */ + uint8_t : 3; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2[183]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED3[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED4[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 8; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + uint8_t : 2; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED13[3]; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[11]; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED22; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED23[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED24[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint32_t RESERVED26[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 3; + } RSTSR1_b; + }; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28[3]; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED31[198]; + __IM uint16_t RESERVED32; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + uint16_t : 4; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED33; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 5; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + uint8_t : 5; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED34; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED35; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + __IM uint8_t RESERVED37; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint16_t RESERVED38; + __IM uint8_t RESERVED39; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED40[24]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED41; + __IM uint32_t RESERVED42[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED43; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED44; + __IM uint32_t RESERVED45[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + __IM uint32_t RESERVED49[16]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A)Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the + * selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + } PIPEBUF_b; /*!< BitSize */ + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not + * provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [10:7] are not provided.) */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + } DEVADD_b[10]; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + } LPSTS_b; + }; + __IM uint32_t RESERVED18[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + } BCCTRL_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150)PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7]PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8]HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12]terminating resistance offset value setting.Offset value for + * adjusting the terminating resistance. */ + } PHYTRIM1_b; /*!< BitSize */ + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152)PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0]Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7]HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8]HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12]Disconnect Detection Level */ + } PHYTRIM2_b; /*!< BitSize */ + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_CTSU2_BASE 0x40082000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DAC8_BASE 0x4009E000UL + #define R_DALI0_BASE 0x4008F000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DRW_BASE 0x400E4000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_ETHERC0_BASE 0x40064100UL + #define R_ETHERC_EDMAC_BASE 0x40064000UL + #define R_ETHERC_EPTPC_BASE 0x40065800UL + #define R_ETHERC_EPTPC1_BASE 0x40065C00UL + #define R_ETHERC_EPTPC_CFG_BASE 0x40064500UL + #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GLCDC_BASE 0x400E0000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_JPEG_BASE 0x400E6000UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SMPU_BASE 0x40000C00UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40047000UL + #define R_OPAMP_BASE 0x40086000UL + #define R_OPAMP2_BASE 0x400867F8UL + #define R_PDC_BASE 0x40094000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDADC0_BASE 0x4009C000UL + #define R_SDHI0_BASE 0x40062000UL + #define R_SDHI1_BASE 0x40062400UL + #define R_SLCDC_BASE 0x40082000UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_USB_HS0_BASE 0x40060000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) + #else + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #endif + #define R_CTSU2 ((R_CTSU2_Type *) R_CTSU2_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) + #define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) + #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE) + #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) + #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U) + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE) + #else + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) + #endif + #define R_PDC ((R_PDC_Type *) R_PDC_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ TM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STTRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos (0UL) /*!< TMSTTRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STTRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos (0UL) /*!< TMSTTRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CYCR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos (0UL) /*!< TMCYCR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos (0UL) /*!< TMPLSR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ PR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MACRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos (0UL) /*!< PRMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff) */ +/* ========================================================= MACRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos (0UL) /*!< PRMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== C =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== R =========================================================== */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ AMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OS =========================================================== */ +/* ========================================================== PS =========================================================== */ +/* ========================================================== MS =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ AMPOT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_OPAMP_AMPOT_P_TRMP_Pos (0UL) /*!< TRMP (Bit 0) */ + #define R_OPAMP_AMPOT_P_TRMP_Msk (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f) */ +/* =========================================================== N =========================================================== */ + #define R_OPAMP_AMPOT_N_TRMN_Pos (0UL) /*!< TRMN (Bit 0) */ + #define R_OPAMP_AMPOT_N_TRMN_Msk (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCRA ======================================================== */ + #define R_CTSU2_CTSUCRA_STRT_Pos (0UL) /*!< STRT (Bit 0) */ + #define R_CTSU2_CTSUCRA_STRT_Msk (0x1UL) /*!< STRT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CAP_Pos (1UL) /*!< CAP (Bit 1) */ + #define R_CTSU2_CTSUCRA_CAP_Msk (0x2UL) /*!< CAP (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_SNZ_Pos (2UL) /*!< SNZ (Bit 2) */ + #define R_CTSU2_CTSUCRA_SNZ_Msk (0x4UL) /*!< SNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CFCON_Pos (3UL) /*!< CFCON (Bit 3) */ + #define R_CTSU2_CTSUCRA_CFCON_Msk (0x8UL) /*!< CFCON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_INIT_Pos (4UL) /*!< INIT (Bit 4) */ + #define R_CTSU2_CTSUCRA_INIT_Msk (0x10UL) /*!< INIT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_PUMPON_Pos (5UL) /*!< PUMPON (Bit 5) */ + #define R_CTSU2_CTSUCRA_PUMPON_Msk (0x20UL) /*!< PUMPON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Pos (6UL) /*!< TXVSEL (Bit 6) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Msk (0xc0UL) /*!< TXVSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_PON_Pos (8UL) /*!< PON (Bit 8) */ + #define R_CTSU2_CTSUCRA_PON_Msk (0x100UL) /*!< PON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CSW_Pos (9UL) /*!< CSW (Bit 9) */ + #define R_CTSU2_CTSUCRA_CSW_Msk (0x200UL) /*!< CSW (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Pos (10UL) /*!< ATUNE0 (Bit 10) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Msk (0x400UL) /*!< ATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Pos (11UL) /*!< ATUNE1 (Bit 11) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Msk (0x800UL) /*!< ATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CLK_Pos (12UL) /*!< CLK (Bit 12) */ + #define R_CTSU2_CTSUCRA_CLK_Msk (0x3000UL) /*!< CLK (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_MD0_Pos (14UL) /*!< MD0 (Bit 14) */ + #define R_CTSU2_CTSUCRA_MD0_Msk (0x4000UL) /*!< MD0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD1_Pos (15UL) /*!< MD1 (Bit 15) */ + #define R_CTSU2_CTSUCRA_MD1_Msk (0x8000UL) /*!< MD1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD2_Pos (16UL) /*!< MD2 (Bit 16) */ + #define R_CTSU2_CTSUCRA_MD2_Msk (0x10000UL) /*!< MD2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Pos (17UL) /*!< ATUNE2 (Bit 17) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Msk (0x20000UL) /*!< ATUNE2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_LOAD_Pos (18UL) /*!< LOAD (Bit 18) */ + #define R_CTSU2_CTSUCRA_LOAD_Msk (0xc0000UL) /*!< LOAD (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_POSEL_Pos (20UL) /*!< POSEL (Bit 20) */ + #define R_CTSU2_CTSUCRA_POSEL_Msk (0x300000UL) /*!< POSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Pos (22UL) /*!< SDPSEL (Bit 22) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Msk (0x400000UL) /*!< SDPSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_FCMODE_Pos (23UL) /*!< FCMODE (Bit 23) */ + #define R_CTSU2_CTSUCRA_FCMODE_Msk (0x800000UL) /*!< FCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_STCLK_Pos (24UL) /*!< STCLK (Bit 24) */ + #define R_CTSU2_CTSUCRA_STCLK_Msk (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUCRA_DCMODE_Pos (30UL) /*!< DCMODE (Bit 30) */ + #define R_CTSU2_CTSUCRA_DCMODE_Msk (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_DCBACK_Pos (31UL) /*!< DCBACK (Bit 31) */ + #define R_CTSU2_CTSUCRA_DCBACK_Msk (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCRAL ======================================================== */ +/* ======================================================== CTSUCR0 ======================================================== */ +/* ======================================================== CTSUCR1 ======================================================== */ +/* ======================================================== CTSUCR2 ======================================================== */ +/* ======================================================== CTSUCR3 ======================================================== */ +/* ======================================================== CTSUCRB ======================================================== */ + #define R_CTSU2_CTSUCRB_PRRATIO_Pos (0UL) /*!< PRRATIO (Bit 0) */ + #define R_CTSU2_CTSUCRB_PRRATIO_Msk (0xfUL) /*!< PRRATIO (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUCRB_PRMODE_Pos (4UL) /*!< PRMODE (Bit 4) */ + #define R_CTSU2_CTSUCRB_PRMODE_Msk (0x30UL) /*!< PRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRB_SOFF_Pos (6UL) /*!< SOFF (Bit 6) */ + #define R_CTSU2_CTSUCRB_SOFF_Msk (0x40UL) /*!< SOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_PROFF_Pos (7UL) /*!< PROFF (Bit 7) */ + #define R_CTSU2_CTSUCRB_PROFF_Msk (0x80UL) /*!< PROFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_SST_Pos (8UL) /*!< SST (Bit 8) */ + #define R_CTSU2_CTSUCRB_SST_Msk (0xff00UL) /*!< SST (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUCRB_SSMOD_Pos (24UL) /*!< SSMOD (Bit 24) */ + #define R_CTSU2_CTSUCRB_SSMOD_Msk (0x7000000UL) /*!< SSMOD (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUCRB_SSCNT_Pos (28UL) /*!< SSCNT (Bit 28) */ + #define R_CTSU2_CTSUCRB_SSCNT_Msk (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= CTSUCRBL ======================================================== */ +/* ======================================================= CTSUSDPRS ======================================================= */ +/* ======================================================== CTSUSST ======================================================== */ +/* ======================================================= CTSUCRBH ======================================================== */ +/* ======================================================= CTSUDCLKC ======================================================= */ +/* ======================================================== CTSUMCH ======================================================== */ + #define R_CTSU2_CTSUMCH_MCH0_Pos (0UL) /*!< MCH0 (Bit 0) */ + #define R_CTSU2_CTSUMCH_MCH0_Msk (0x3fUL) /*!< MCH0 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCH1_Pos (8UL) /*!< MCH1 (Bit 8) */ + #define R_CTSU2_CTSUMCH_MCH1_Msk (0x3f00UL) /*!< MCH1 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCA0_Pos (16UL) /*!< MCA0 (Bit 16) */ + #define R_CTSU2_CTSUMCH_MCA0_Msk (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA1_Pos (17UL) /*!< MCA1 (Bit 17) */ + #define R_CTSU2_CTSUMCH_MCA1_Msk (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA2_Pos (18UL) /*!< MCA2 (Bit 18) */ + #define R_CTSU2_CTSUMCH_MCA2_Msk (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA3_Pos (19UL) /*!< MCA3 (Bit 19) */ + #define R_CTSU2_CTSUMCH_MCA3_Msk (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUMCHL ======================================================== */ +/* ======================================================= CTSUMCH0 ======================================================== */ +/* ======================================================= CTSUMCH1 ======================================================== */ +/* ======================================================= CTSUMCHH ======================================================== */ +/* ======================================================= CTSUMFAF ======================================================== */ +/* ======================================================= CTSUCHACA ======================================================= */ + #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */ + #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Msk (0x20UL) /*!< CHAC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Pos (6UL) /*!< CHAC06 (Bit 6) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Msk (0x40UL) /*!< CHAC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Pos (7UL) /*!< CHAC07 (Bit 7) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Msk (0x80UL) /*!< CHAC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Pos (8UL) /*!< CHAC08 (Bit 8) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Msk (0x100UL) /*!< CHAC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Pos (9UL) /*!< CHAC09 (Bit 9) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Msk (0x200UL) /*!< CHAC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Pos (10UL) /*!< CHAC10 (Bit 10) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Msk (0x400UL) /*!< CHAC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Pos (11UL) /*!< CHAC11 (Bit 11) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Msk (0x800UL) /*!< CHAC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Pos (12UL) /*!< CHAC12 (Bit 12) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Msk (0x1000UL) /*!< CHAC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Pos (13UL) /*!< CHAC13 (Bit 13) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Msk (0x2000UL) /*!< CHAC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Pos (14UL) /*!< CHAC14 (Bit 14) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Msk (0x4000UL) /*!< CHAC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Pos (15UL) /*!< CHAC15 (Bit 15) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Msk (0x8000UL) /*!< CHAC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Pos (16UL) /*!< CHAC16 (Bit 16) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Msk (0x10000UL) /*!< CHAC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Pos (17UL) /*!< CHAC17 (Bit 17) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Msk (0x20000UL) /*!< CHAC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Pos (18UL) /*!< CHAC18 (Bit 18) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Msk (0x40000UL) /*!< CHAC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Pos (21UL) /*!< CHAC21 (Bit 21) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Msk (0x200000UL) /*!< CHAC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Pos (22UL) /*!< CHAC22 (Bit 22) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Msk (0x400000UL) /*!< CHAC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Pos (23UL) /*!< CHAC23 (Bit 23) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Msk (0x800000UL) /*!< CHAC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Pos (24UL) /*!< CHAC24 (Bit 24) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Msk (0x1000000UL) /*!< CHAC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Pos (25UL) /*!< CHAC25 (Bit 25) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Msk (0x2000000UL) /*!< CHAC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Pos (26UL) /*!< CHAC26 (Bit 26) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Msk (0x4000000UL) /*!< CHAC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Pos (27UL) /*!< CHAC27 (Bit 27) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Msk (0x8000000UL) /*!< CHAC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Pos (28UL) /*!< CHAC28 (Bit 28) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Msk (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Pos (29UL) /*!< CHAC29 (Bit 29) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Msk (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Pos (30UL) /*!< CHAC30 (Bit 30) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Msk (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Pos (31UL) /*!< CHAC31 (Bit 31) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Msk (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACAL ======================================================= */ +/* ======================================================= CTSUCHAC0 ======================================================= */ +/* ======================================================= CTSUCHAC1 ======================================================= */ +/* ====================================================== CTSUCHACAH ======================================================= */ +/* ======================================================= CTSUCHAC2 ======================================================= */ +/* ======================================================= CTSUCHAC3 ======================================================= */ +/* ======================================================= CTSUCHACB ======================================================= */ + #define R_CTSU2_CTSUCHACB_CHAC32_Pos (0UL) /*!< CHAC32 (Bit 0) */ + #define R_CTSU2_CTSUCHACB_CHAC32_Msk (0x1UL) /*!< CHAC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Pos (1UL) /*!< CHAC33 (Bit 1) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Msk (0x2UL) /*!< CHAC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Pos (2UL) /*!< CHAC34 (Bit 2) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Msk (0x4UL) /*!< CHAC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Pos (3UL) /*!< CHAC35 (Bit 3) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Msk (0x8UL) /*!< CHAC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACBL ======================================================= */ +/* ======================================================= CTSUCHAC4 ======================================================= */ +/* ====================================================== CTSUCHTRCA ======================================================= */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk (0x20UL) /*!< CHTRC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos (6UL) /*!< CHTRC06 (Bit 6) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk (0x40UL) /*!< CHTRC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos (7UL) /*!< CHTRC07 (Bit 7) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk (0x80UL) /*!< CHTRC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos (8UL) /*!< CHTRC08 (Bit 8) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk (0x100UL) /*!< CHTRC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos (9UL) /*!< CHTRC09 (Bit 9) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk (0x200UL) /*!< CHTRC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos (10UL) /*!< CHTRC10 (Bit 10) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk (0x400UL) /*!< CHTRC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos (11UL) /*!< CHTRC11 (Bit 11) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk (0x800UL) /*!< CHTRC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos (12UL) /*!< CHTRC12 (Bit 12) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk (0x1000UL) /*!< CHTRC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos (13UL) /*!< CHTRC13 (Bit 13) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk (0x2000UL) /*!< CHTRC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos (14UL) /*!< CHTRC14 (Bit 14) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk (0x4000UL) /*!< CHTRC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos (15UL) /*!< CHTRC15 (Bit 15) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk (0x8000UL) /*!< CHTRC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos (16UL) /*!< CHTRC16 (Bit 16) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk (0x10000UL) /*!< CHTRC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos (17UL) /*!< CHTRC17 (Bit 17) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk (0x20000UL) /*!< CHTRC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos (18UL) /*!< CHTRC18 (Bit 18) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk (0x40000UL) /*!< CHTRC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos (21UL) /*!< CHTRC21 (Bit 21) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk (0x200000UL) /*!< CHTRC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos (22UL) /*!< CHTRC22 (Bit 22) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk (0x400000UL) /*!< CHTRC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos (23UL) /*!< CHTRC23 (Bit 23) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk (0x800000UL) /*!< CHTRC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos (24UL) /*!< CHTRC24 (Bit 24) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk (0x1000000UL) /*!< CHTRC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos (25UL) /*!< CHTRC25 (Bit 25) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk (0x2000000UL) /*!< CHTRC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos (26UL) /*!< CHTRC26 (Bit 26) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk (0x4000000UL) /*!< CHTRC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos (27UL) /*!< CHTRC27 (Bit 27) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk (0x8000000UL) /*!< CHTRC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos (28UL) /*!< CHTRC28 (Bit 28) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos (29UL) /*!< CHTRC29 (Bit 29) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos (30UL) /*!< CHTRC30 (Bit 30) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos (31UL) /*!< CHTRC31 (Bit 31) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCAL ====================================================== */ +/* ====================================================== CTSUCHTRC0 ======================================================= */ +/* ====================================================== CTSUCHTRC1 ======================================================= */ +/* ====================================================== CTSUCHTRCAH ====================================================== */ +/* ====================================================== CTSUCHTRC2 ======================================================= */ +/* ====================================================== CTSUCHTRC3 ======================================================= */ +/* ====================================================== CTSUCHTRCB ======================================================= */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos (0UL) /*!< CHTRC32 (Bit 0) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk (0x1UL) /*!< CHTRC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos (1UL) /*!< CHTRC33 (Bit 1) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk (0x2UL) /*!< CHTRC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos (2UL) /*!< CHTRC34 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk (0x4UL) /*!< CHTRC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos (3UL) /*!< CHTRC35 (Bit 3) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk (0x8UL) /*!< CHTRC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCBL ====================================================== */ +/* ====================================================== CTSUCHTRC4 ======================================================= */ +/* ======================================================== CTSUSR ========================================================= */ + #define R_CTSU2_CTSUSR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_CTSU2_CTSUSR_MFC_Msk (0x3UL) /*!< MFC (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Pos (5UL) /*!< ICOMPRST (Bit 5) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Msk (0x20UL) /*!< ICOMPRST (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP1_Pos (6UL) /*!< ICOMP1 (Bit 6) */ + #define R_CTSU2_CTSUSR_ICOMP1_Msk (0x40UL) /*!< ICOMP1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP0_Pos (7UL) /*!< ICOMP0 (Bit 7) */ + #define R_CTSU2_CTSUSR_ICOMP0_Msk (0x80UL) /*!< ICOMP0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_STC_Pos (8UL) /*!< STC (Bit 8) */ + #define R_CTSU2_CTSUSR_STC_Msk (0x700UL) /*!< STC (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUSR_DTSR_Pos (12UL) /*!< DTSR (Bit 12) */ + #define R_CTSU2_CTSUSR_DTSR_Msk (0x1000UL) /*!< DTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_SENSOVF_Pos (13UL) /*!< SENSOVF (Bit 13) */ + #define R_CTSU2_CTSUSR_SENSOVF_Msk (0x2000UL) /*!< SENSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_CTSU2_CTSUSR_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Pos (16UL) /*!< CFCRDCH (Bit 16) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Msk (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f) */ +/* ======================================================== CTSUSRL ======================================================== */ +/* ======================================================== CTSUSR0 ======================================================== */ +/* ======================================================== CTSUST ========================================================= */ +/* ======================================================== CTSUSRH ======================================================== */ +/* ======================================================== CTSUSR2 ======================================================== */ +/* ======================================================== CTSUSO ========================================================= */ + #define R_CTSU2_CTSUSO_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUSO_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUSO_SNUM_Pos (10UL) /*!< SNUM (Bit 10) */ + #define R_CTSU2_CTSUSO_SNUM_Msk (0x3fc00UL) /*!< SNUM (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSO_SSDIV_Pos (20UL) /*!< SSDIV (Bit 20) */ + #define R_CTSU2_CTSUSO_SSDIV_Msk (0xf00000UL) /*!< SSDIV (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUSO_SDPA_Pos (24UL) /*!< SDPA (Bit 24) */ + #define R_CTSU2_CTSUSO_SDPA_Msk (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSO0 ======================================================== */ +/* ======================================================== CTSUSO1 ======================================================== */ +/* ======================================================= CTSUSCNT ======================================================== */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Pos (0UL) /*!< SENSCNT (Bit 0) */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Msk (0xffffUL) /*!< SENSCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSUSC ========================================================= */ +/* ======================================================= CTSUCALIB ======================================================= */ + #define R_CTSU2_CTSUCALIB_TSOD_Pos (2UL) /*!< TSOD (Bit 2) */ + #define R_CTSU2_CTSUCALIB_TSOD_Msk (0x4UL) /*!< TSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DRV_Pos (3UL) /*!< DRV (Bit 3) */ + #define R_CTSU2_CTSUCALIB_DRV_Msk (0x8UL) /*!< DRV (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos (6UL) /*!< SUCLKEN (Bit 6) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk (0x40UL) /*!< SUCLKEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_TSOC_Pos (7UL) /*!< TSOC (Bit 7) */ + #define R_CTSU2_CTSUCALIB_TSOC_Msk (0x80UL) /*!< TSOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_IOC_Pos (9UL) /*!< IOC (Bit 9) */ + #define R_CTSU2_CTSUCALIB_IOC_Msk (0x200UL) /*!< IOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos (10UL) /*!< CFCRDMD (Bit 10) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Msk (0x400000UL) /*!< CFCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Pos (25UL) /*!< DACCARRY (Bit 25) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Msk (0x2000000UL) /*!< DACCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Pos (27UL) /*!< SUCARRY (Bit 27) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Msk (0x8000000UL) /*!< SUCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Pos (28UL) /*!< DACCLK (Bit 28) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Msk (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Pos (29UL) /*!< CCOCLK (Bit 29) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Msk (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos (30UL) /*!< CCOCALIB (Bit 30) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDBGR0 ======================================================= */ +/* ======================================================= CTSUDBGR1 ======================================================= */ +/* ====================================================== CTSUSUCLKA ======================================================= */ +/* ====================================================== CTSUSUCLK0 ======================================================= */ +/* ====================================================== CTSUSUCLK1 ======================================================= */ +/* ====================================================== CTSUSUCLKB ======================================================= */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos (0UL) /*!< SUADJ2 (Bit 0) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk (0xffUL) /*!< SUADJ2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos (8UL) /*!< SUMULTI2 (Bit 8) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk (0xff00UL) /*!< SUMULTI2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos (16UL) /*!< SUADJ3 (Bit 16) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk (0xff0000UL) /*!< SUADJ3 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos (24UL) /*!< SUMULTI3 (Bit 24) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTSUSUCLK2 ======================================================= */ +/* ====================================================== CTSUSUCLK3 ======================================================= */ +/* ====================================================== CTSUCFCCNT ======================================================= */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUCFCCNTL ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DAM ========================================================== */ + #define R_DAC8_DAM_DACE1_Pos (5UL) /*!< DACE1 (Bit 5) */ + #define R_DAC8_DAM_DACE1_Msk (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DACE0_Pos (4UL) /*!< DACE0 (Bit 4) */ + #define R_DAC8_DAM_DACE0_Msk (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD1_Pos (1UL) /*!< DAMD1 (Bit 1) */ + #define R_DAC8_DAM_DAMD1_Msk (0x2UL) /*!< DAMD1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD0_Pos (0UL) /*!< DAMD0 (Bit 0) */ + #define R_DAC8_DAM_DAMD0_Msk (0x1UL) /*!< DAMD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= DACS ========================================================== */ + #define R_DAC8_DACS_DACS_Pos (0UL) /*!< DACS (Bit 0) */ + #define R_DAC8_DACS_DACS_Msk (0xffUL) /*!< DACS (Bitfield-Mask: 0xff) */ +/* ======================================================= DACADSCR ======================================================== */ + #define R_DAC8_DACADSCR_DACADST_Pos (0UL) /*!< DACADST (Bit 0) */ + #define R_DAC8_DACADSCR_DACADST_Msk (0x1UL) /*!< DACADST (Bitfield-Mask: 0x01) */ +/* ========================================================= DACPC ========================================================= */ + #define R_DAC8_DACPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC8_DACPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DALI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BTVTHR1 ======================================================== */ + #define R_DALI0_BTVTHR1_BTV2_Pos (8UL) /*!< BTV2 (Bit 8) */ + #define R_DALI0_BTVTHR1_BTV2_Msk (0xff00UL) /*!< BTV2 (Bitfield-Mask: 0xff) */ + #define R_DALI0_BTVTHR1_BTV1_Pos (0UL) /*!< BTV1 (Bit 0) */ + #define R_DALI0_BTVTHR1_BTV1_Msk (0x7fUL) /*!< BTV1 (Bitfield-Mask: 0x7f) */ +/* ======================================================== BTVTHR2 ======================================================== */ + #define R_DALI0_BTVTHR2_BTV4_Pos (8UL) /*!< BTV4 (Bit 8) */ + #define R_DALI0_BTVTHR2_BTV4_Msk (0xff00UL) /*!< BTV4 (Bitfield-Mask: 0xff) */ + #define R_DALI0_BTVTHR2_BTV3_Pos (0UL) /*!< BTV3 (Bit 0) */ + #define R_DALI0_BTVTHR2_BTV3_Msk (0xffUL) /*!< BTV3 (Bitfield-Mask: 0xff) */ +/* ======================================================== BTVTHR3 ======================================================== */ + #define R_DALI0_BTVTHR3_BTV5_Pos (0UL) /*!< BTV5 (Bit 0) */ + #define R_DALI0_BTVTHR3_BTV5_Msk (0xffUL) /*!< BTV5 (Bitfield-Mask: 0xff) */ +/* ======================================================== BTVTHR4 ======================================================== */ + #define R_DALI0_BTVTHR4_BTV6_Pos (0UL) /*!< BTV6 (Bit 0) */ + #define R_DALI0_BTVTHR4_BTV6_Msk (0x1ffUL) /*!< BTV6 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== COLTHR1 ======================================================== */ + #define R_DALI0_COLTHR1_COL2_Pos (8UL) /*!< COL2 (Bit 8) */ + #define R_DALI0_COLTHR1_COL2_Msk (0x3f00UL) /*!< COL2 (Bitfield-Mask: 0x3f) */ + #define R_DALI0_COLTHR1_COL1_Pos (0UL) /*!< COL1 (Bit 0) */ + #define R_DALI0_COLTHR1_COL1_Msk (0x3fUL) /*!< COL1 (Bitfield-Mask: 0x3f) */ +/* ======================================================== COLTHR2 ======================================================== */ + #define R_DALI0_COLTHR2_COL4_Pos (8UL) /*!< COL4 (Bit 8) */ + #define R_DALI0_COLTHR2_COL4_Msk (0x7f00UL) /*!< COL4 (Bitfield-Mask: 0x7f) */ + #define R_DALI0_COLTHR2_COL3_Pos (0UL) /*!< COL3 (Bit 0) */ + #define R_DALI0_COLTHR2_COL3_Msk (0x7fUL) /*!< COL3 (Bitfield-Mask: 0x7f) */ +/* ======================================================== COLTHR3 ======================================================== */ + #define R_DALI0_COLTHR3_COL6_Pos (8UL) /*!< COL6 (Bit 8) */ + #define R_DALI0_COLTHR3_COL6_Msk (0x7f00UL) /*!< COL6 (Bitfield-Mask: 0x7f) */ + #define R_DALI0_COLTHR3_COL5_Pos (0UL) /*!< COL5 (Bit 0) */ + #define R_DALI0_COLTHR3_COL5_Msk (0x7fUL) /*!< COL5 (Bitfield-Mask: 0x7f) */ +/* ======================================================== COLTHR4 ======================================================== */ + #define R_DALI0_COLTHR4_COL8_Pos (8UL) /*!< COL8 (Bit 8) */ + #define R_DALI0_COLTHR4_COL8_Msk (0xff00UL) /*!< COL8 (Bitfield-Mask: 0xff) */ + #define R_DALI0_COLTHR4_COL7_Pos (0UL) /*!< COL7 (Bit 0) */ + #define R_DALI0_COLTHR4_COL7_Msk (0xffUL) /*!< COL7 (Bitfield-Mask: 0xff) */ +/* ======================================================== COLTHR5 ======================================================== */ + #define R_DALI0_COLTHR5_COL9_Pos (0UL) /*!< COL9 (Bit 0) */ + #define R_DALI0_COLTHR5_COL9_Msk (0xffUL) /*!< COL9 (Bitfield-Mask: 0xff) */ +/* ========================================================= CNFR1 ========================================================= */ + #define R_DALI0_CNFR1_CHL_Pos (12UL) /*!< CHL (Bit 12) */ + #define R_DALI0_CNFR1_CHL_Msk (0x7000UL) /*!< CHL (Bitfield-Mask: 0x07) */ + #define R_DALI0_CNFR1_CKS_Pos (8UL) /*!< CKS (Bit 8) */ + #define R_DALI0_CNFR1_CKS_Msk (0x300UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_DALI0_CNFR1_BR_Pos (0UL) /*!< BR (Bit 0) */ + #define R_DALI0_CNFR1_BR_Msk (0xffUL) /*!< BR (Bitfield-Mask: 0xff) */ +/* ========================================================= CNFR2 ========================================================= */ + #define R_DALI0_CNFR2_CDM0_Pos (5UL) /*!< CDM0 (Bit 5) */ + #define R_DALI0_CNFR2_CDM0_Msk (0x20UL) /*!< CDM0 (Bitfield-Mask: 0x01) */ + #define R_DALI0_CNFR2_CDE_Pos (4UL) /*!< CDE (Bit 4) */ + #define R_DALI0_CNFR2_CDE_Msk (0x10UL) /*!< CDE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CNFR2_TXWE_Pos (3UL) /*!< TXWE (Bit 3) */ + #define R_DALI0_CNFR2_TXWE_Msk (0x8UL) /*!< TXWE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CNFR2_SGA_Pos (2UL) /*!< SGA (Bit 2) */ + #define R_DALI0_CNFR2_SGA_Msk (0x4UL) /*!< SGA (Bitfield-Mask: 0x01) */ + #define R_DALI0_CNFR2_BTVM_Pos (1UL) /*!< BTVM (Bit 1) */ + #define R_DALI0_CNFR2_BTVM_Msk (0x2UL) /*!< BTVM (Bitfield-Mask: 0x01) */ + #define R_DALI0_CNFR2_BTVE_Pos (0UL) /*!< BTVE (Bit 0) */ + #define R_DALI0_CNFR2_BTVE_Msk (0x1UL) /*!< BTVE (Bitfield-Mask: 0x01) */ +/* ========================================================= TXWR1 ========================================================= */ + #define R_DALI0_TXWR1_TXLW_Pos (0UL) /*!< TXLW (Bit 0) */ + #define R_DALI0_TXWR1_TXLW_Msk (0x7fUL) /*!< TXLW (Bitfield-Mask: 0x7f) */ +/* ========================================================= TDR1H ========================================================= */ + #define R_DALI0_TDR1H_DTDR_Pos (0UL) /*!< DTDR (Bit 0) */ + #define R_DALI0_TDR1H_DTDR_Msk (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TDR1L ========================================================= */ + #define R_DALI0_TDR1L_DTDR_Pos (0UL) /*!< DTDR (Bit 0) */ + #define R_DALI0_TDR1L_DTDR_Msk (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== TRSTR1 ========================================================= */ + #define R_DALI0_TRSTR1_TRST_Pos (0UL) /*!< TRST (Bit 0) */ + #define R_DALI0_TRSTR1_TRST_Msk (0x1UL) /*!< TRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CTR1 ========================================================== */ + #define R_DALI0_CTR1_FEIE_Pos (12UL) /*!< FEIE (Bit 12) */ + #define R_DALI0_CTR1_FEIE_Msk (0x1000UL) /*!< FEIE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_BPIE_Pos (11UL) /*!< BPIE (Bit 11) */ + #define R_DALI0_CTR1_BPIE_Msk (0x800UL) /*!< BPIE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_CLIE_Pos (10UL) /*!< CLIE (Bit 10) */ + #define R_DALI0_CTR1_CLIE_Msk (0x400UL) /*!< CLIE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_DEIE_Pos (9UL) /*!< DEIE (Bit 9) */ + #define R_DALI0_CTR1_DEIE_Msk (0x200UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_SDIE_Pos (8UL) /*!< SDIE (Bit 8) */ + #define R_DALI0_CTR1_SDIE_Msk (0x100UL) /*!< SDIE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_RE_Pos (1UL) /*!< RE (Bit 1) */ + #define R_DALI0_CTR1_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_DALI0_CTR1_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_DALI0_CTR1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ +/* ======================================================== TXDCTR1 ======================================================== */ + #define R_DALI0_TXDCTR1_TXASE_Pos (1UL) /*!< TXASE (Bit 1) */ + #define R_DALI0_TXDCTR1_TXASE_Msk (0x2UL) /*!< TXASE (Bitfield-Mask: 0x01) */ + #define R_DALI0_TXDCTR1_TXAS_Pos (0UL) /*!< TXAS (Bit 0) */ + #define R_DALI0_TXDCTR1_TXAS_Msk (0x1UL) /*!< TXAS (Bitfield-Mask: 0x01) */ +/* ========================================================= RDR1H ========================================================= */ + #define R_DALI0_RDR1H_DRDR_Pos (0UL) /*!< DRDR (Bit 0) */ + #define R_DALI0_RDR1H_DRDR_Msk (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= RDR1L ========================================================= */ + #define R_DALI0_RDR1L_DRDR_Pos (0UL) /*!< DRDR (Bit 0) */ + #define R_DALI0_RDR1L_DRDR_Msk (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= STR1 ========================================================== */ + #define R_DALI0_STR1_RDBL_Pos (10UL) /*!< RDBL (Bit 10) */ + #define R_DALI0_STR1_RDBL_Msk (0xfc00UL) /*!< RDBL (Bitfield-Mask: 0x3f) */ + #define R_DALI0_STR1_DAF_Pos (9UL) /*!< DAF (Bit 9) */ + #define R_DALI0_STR1_DAF_Msk (0x200UL) /*!< DAF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_CDF_Pos (8UL) /*!< CDF (Bit 8) */ + #define R_DALI0_STR1_CDF_Msk (0x100UL) /*!< CDF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_O32F_Pos (7UL) /*!< O32F (Bit 7) */ + #define R_DALI0_STR1_O32F_Msk (0x80UL) /*!< O32F (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_BPDF_Pos (6UL) /*!< BPDF (Bit 6) */ + #define R_DALI0_STR1_BPDF_Msk (0x40UL) /*!< BPDF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_BBF_Pos (5UL) /*!< BBF (Bit 5) */ + #define R_DALI0_STR1_BBF_Msk (0x20UL) /*!< BBF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_TENDF_Pos (4UL) /*!< TENDF (Bit 4) */ + #define R_DALI0_STR1_TENDF_Msk (0x10UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_RDRF_Pos (3UL) /*!< RDRF (Bit 3) */ + #define R_DALI0_STR1_RDRF_Msk (0x8UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_BTVF_Pos (2UL) /*!< BTVF (Bit 2) */ + #define R_DALI0_STR1_BTVF_Msk (0x4UL) /*!< BTVF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_DALI0_STR1_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_DALI0_STR1_MFEF_Pos (0UL) /*!< MFEF (Bit 0) */ + #define R_DALI0_STR1_MFEF_Msk (0x1UL) /*!< MFEF (Bitfield-Mask: 0x01) */ +/* ========================================================= COLR1 ========================================================= */ + #define R_DALI0_COLR1_TXDCV_Pos (13UL) /*!< TXDCV (Bit 13) */ + #define R_DALI0_COLR1_TXDCV_Msk (0x2000UL) /*!< TXDCV (Bitfield-Mask: 0x01) */ + #define R_DALI0_COLR1_RXDCEG_Pos (12UL) /*!< RXDCEG (Bit 12) */ + #define R_DALI0_COLR1_RXDCEG_Msk (0x1000UL) /*!< RXDCEG (Bitfield-Mask: 0x01) */ + #define R_DALI0_COLR1_RXDMON_Pos (11UL) /*!< RXDMON (Bit 11) */ + #define R_DALI0_COLR1_RXDMON_Msk (0x800UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_DALI0_COLR1_CLDAF_Pos (10UL) /*!< CLDAF (Bit 10) */ + #define R_DALI0_COLR1_CLDAF_Msk (0x400UL) /*!< CLDAF (Bitfield-Mask: 0x01) */ + #define R_DALI0_COLR1_CDTF1_Pos (4UL) /*!< CDTF1 (Bit 4) */ + #define R_DALI0_COLR1_CDTF1_Msk (0x10UL) /*!< CDTF1 (Bitfield-Mask: 0x01) */ + #define R_DALI0_COLR1_CFTF2_Pos (0UL) /*!< CFTF2 (Bit 0) */ + #define R_DALI0_COLR1_CFTF2_Msk (0xfUL) /*!< CFTF2 (Bitfield-Mask: 0x0f) */ +/* ========================================================= FECR1 ========================================================= */ + #define R_DALI0_FECR1_DAFC_Pos (9UL) /*!< DAFC (Bit 9) */ + #define R_DALI0_FECR1_DAFC_Msk (0x200UL) /*!< DAFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_CDFC_Pos (8UL) /*!< CDFC (Bit 8) */ + #define R_DALI0_FECR1_CDFC_Msk (0x100UL) /*!< CDFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_O32FC_Pos (7UL) /*!< O32FC (Bit 7) */ + #define R_DALI0_FECR1_O32FC_Msk (0x80UL) /*!< O32FC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_BPDFC_Pos (6UL) /*!< BPDFC (Bit 6) */ + #define R_DALI0_FECR1_BPDFC_Msk (0x40UL) /*!< BPDFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_BBFC_Pos (5UL) /*!< BBFC (Bit 5) */ + #define R_DALI0_FECR1_BBFC_Msk (0x20UL) /*!< BBFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_TENDFC_Pos (4UL) /*!< TENDFC (Bit 4) */ + #define R_DALI0_FECR1_TENDFC_Msk (0x10UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_RDRFC_Pos (3UL) /*!< RDRFC (Bit 3) */ + #define R_DALI0_FECR1_RDRFC_Msk (0x8UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_BTVFC_Pos (2UL) /*!< BTVFC (Bit 2) */ + #define R_DALI0_FECR1_BTVFC_Msk (0x4UL) /*!< BTVFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_OVFC_Pos (1UL) /*!< OVFC (Bit 1) */ + #define R_DALI0_FECR1_OVFC_Msk (0x2UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_DALI0_FECR1_MFEFC_Pos (0UL) /*!< MFEFC (Bit 0) */ + #define R_DALI0_FECR1_MFEFC_Msk (0x1UL) /*!< MFEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SWRR1 ========================================================= */ + #define R_DALI0_SWRR1_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_DALI0_SWRR1_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRB_Pos (0UL) /*!< DMCRB (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRB_Msk (0xffffUL) /*!< DMCRB (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SYSR ========================================================== */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ========================================================= SYIPR ========================================================= */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ======================================================== SYMACRU ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos (0UL) /*!< SYMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk (0xffffffUL) /*!< SYMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SYMACRL ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos (0UL) /*!< SYMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk (0xffffffUL) /*!< SYMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================= SYLLCCTLR ======================================================= */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos (0UL) /*!< CTL (Bit 0) */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk (0xffUL) /*!< CTL (Bitfield-Mask: 0xff) */ +/* ======================================================= SYIPADDRR ======================================================= */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos (0UL) /*!< SYIPADDRR (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYSPVRR ======================================================== */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos (4UL) /*!< TRSP (Bit 4) */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk (0xf0UL) /*!< TRSP (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYDOMR ========================================================= */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos (0UL) /*!< DNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk (0xffUL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ========================================================= ANFR ========================================================== */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos (5UL) /*!< FLAG5 (Bit 5) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk (0x20UL) /*!< FLAG5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos (4UL) /*!< FLAG4 (Bit 4) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk (0x10UL) /*!< FLAG4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos (3UL) /*!< FLAG3 (Bit 3) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk (0x8UL) /*!< FLAG3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos (2UL) /*!< FLAG2 (Bit 2) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk (0x4UL) /*!< FLAG2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos (1UL) /*!< FLAG1 (Bit 1) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk (0x2UL) /*!< FLAG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos (0UL) /*!< FLAG0 (Bit 0) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk (0x1UL) /*!< FLAG0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SYNFR ========================================================= */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRQFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRPFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYCIDRU ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos (0UL) /*!< SYCIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYCIDRL ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos (0UL) /*!< SYCIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYPNUMR ======================================================== */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYRVLDR ======================================================== */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos (2UL) /*!< ANUP (Bit 2) */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk (0x4UL) /*!< ANUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos (1UL) /*!< STUP (Bit 1) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk (0x2UL) /*!< STUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos (0UL) /*!< BMUP (Bit 0) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk (0x1UL) /*!< BMUP (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL1R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos (30UL) /*!< PDFUP2 (Bit 30) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos (29UL) /*!< PDFUP1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos (28UL) /*!< PDFUP0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos (26UL) /*!< PDRP2 (Bit 26) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk (0x4000000UL) /*!< PDRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos (25UL) /*!< PDRP1 (Bit 25) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk (0x2000000UL) /*!< PDRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos (24UL) /*!< PDRP0 (Bit 24) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk (0x1000000UL) /*!< PDRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos (22UL) /*!< PDRQ2 (Bit 22) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk (0x400000UL) /*!< PDRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos (21UL) /*!< PDRQ1 (Bit 21) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk (0x200000UL) /*!< PDRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos (20UL) /*!< PDRQ0 (Bit 20) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk (0x100000UL) /*!< PDRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos (18UL) /*!< DRP2 (Bit 18) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk (0x40000UL) /*!< DRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos (17UL) /*!< DRP1 (Bit 17) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk (0x20000UL) /*!< DRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos (16UL) /*!< DRP0 (Bit 16) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk (0x10000UL) /*!< DRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos (14UL) /*!< DRQ2 (Bit 14) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk (0x4000UL) /*!< DRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos (13UL) /*!< DRQ1 (Bit 13) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk (0x2000UL) /*!< DRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos (12UL) /*!< DRQ0 (Bit 12) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk (0x1000UL) /*!< DRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos (10UL) /*!< FUP2 (Bit 10) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk (0x400UL) /*!< FUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos (9UL) /*!< FUP1 (Bit 9) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk (0x200UL) /*!< FUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos (8UL) /*!< FUP0 (Bit 8) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk (0x100UL) /*!< FUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos (6UL) /*!< SYNC2 (Bit 6) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk (0x40UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos (5UL) /*!< SYNC1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk (0x20UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos (4UL) /*!< SYNC0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk (0x10UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos (1UL) /*!< ANCE1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk (0x2UL) /*!< ANCE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos (0UL) /*!< ANCE0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk (0x1UL) /*!< ANCE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL2R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos (29UL) /*!< ILL1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos (28UL) /*!< ILL0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos (5UL) /*!< SIG1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk (0x20UL) /*!< SIG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos (4UL) /*!< SIG0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk (0x10UL) /*!< SIG0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos (1UL) /*!< MAN1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk (0x2UL) /*!< MAN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos (0UL) /*!< MAN0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk (0x1UL) /*!< MAN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYTRENR ======================================================== */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos (12UL) /*!< PDRQ (Bit 12) */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk (0x1000UL) /*!< PDRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos (8UL) /*!< DRQ (Bit 8) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk (0x100UL) /*!< DRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos (4UL) /*!< SYNC (Bit 4) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk (0x10UL) /*!< SYNC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk (0x1UL) /*!< ANCE (Bitfield-Mask: 0x01) */ +/* ======================================================== MTCIDU ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos (0UL) /*!< MTCIDU (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTCIDL ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos (0UL) /*!< MTCIDL (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTPID ========================================================= */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYTLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos (16UL) /*!< DREQ (Bit 16) */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk (0xff0000UL) /*!< DREQ (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ======================================================== SYRLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos (16UL) /*!< DRESP (Bit 16) */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk (0xff0000UL) /*!< DRESP (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ========================================================= OFMRU ========================================================= */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos (0UL) /*!< OFMRU (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= OFMRL ========================================================= */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos (0UL) /*!< OFMRL (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRU ========================================================= */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos (0UL) /*!< MPDRU (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRL ========================================================= */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos (0UL) /*!< MPDRL (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GMPR ========================================================== */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos (16UL) /*!< GMPR1 (Bit 16) */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk (0xff0000UL) /*!< GMPR1 (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos (0UL) /*!< GMPR2 (Bit 0) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk (0xffUL) /*!< GMPR2 (Bitfield-Mask: 0xff) */ +/* ========================================================= GMCQR ========================================================= */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos (0UL) /*!< GMCQR (Bit 0) */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRU ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos (0UL) /*!< GMIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRL ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos (0UL) /*!< GMIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CUOTSR ========================================================= */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos (16UL) /*!< CUTO (Bit 16) */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos (0UL) /*!< TSRC (Bit 0) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk (0xffUL) /*!< TSRC (Bitfield-Mask: 0xff) */ +/* ========================================================== SRR ========================================================== */ + #define R_ETHERC_EPTPC_SRR_SRMV_Pos (0UL) /*!< SRMV (Bit 0) */ + #define R_ETHERC_EPTPC_SRR_SRMV_Msk (0xffffUL) /*!< SRMV (Bitfield-Mask: 0xffff) */ +/* ======================================================== PPMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos (0UL) /*!< PPMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk (0xffffffUL) /*!< PPMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PPMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos (0UL) /*!< PPMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk (0xffffffUL) /*!< PPMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos (0UL) /*!< PDMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk (0xffffffUL) /*!< PDMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos (0UL) /*!< PDMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk (0xffffffUL) /*!< PDMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PETYPER ======================================================== */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk (0xffffUL) /*!< TYPE (Bitfield-Mask: 0xffff) */ +/* ========================================================= PPIPR ========================================================= */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos (0UL) /*!< PPIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PDIPR ========================================================= */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos (0UL) /*!< PDIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PETOSR ========================================================= */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos (0UL) /*!< EVTO (Bit 0) */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk (0xffUL) /*!< EVTO (Bitfield-Mask: 0xff) */ +/* ======================================================== PGTOSR ========================================================= */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos (0UL) /*!< GETO (Bit 0) */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk (0xffUL) /*!< GETO (Bitfield-Mask: 0xff) */ +/* ======================================================== PPTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos (0UL) /*!< PRTL (Bit 0) */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk (0xffUL) /*!< PRTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PDTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos (0UL) /*!< PDTL (Bit 0) */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk (0xffUL) /*!< PDTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PEUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos (0UL) /*!< EVUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk (0xffffUL) /*!< EVUPT (Bitfield-Mask: 0xffff) */ +/* ======================================================== PGUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos (0UL) /*!< GEUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk (0xffffUL) /*!< GEUPT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FFLTR ========================================================= */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos (16UL) /*!< EXTPRM (Bit 16) */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk (0x10000UL) /*!< EXTPRM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Pos (2UL) /*!< ENB (Bit 2) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Msk (0x4UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Pos (1UL) /*!< PRT (Bit 1) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Msk (0x2UL) /*!< PRT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DASYMRU ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos (0UL) /*!< DASYMRU (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk (0xffffUL) /*!< DASYMRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== DASYMRL ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos (0UL) /*!< DASYMRL (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSLATR ========================================================= */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Pos (16UL) /*!< INGP (Bit 16) */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Msk (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Pos (0UL) /*!< EGP (Bit 0) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Msk (0xffffUL) /*!< EGP (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYCONFR ======================================================== */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos (20UL) /*!< TCMOD (Bit 20) */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk (0x100000UL) /*!< TCMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos (16UL) /*!< FILDIS (Bit 16) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk (0x10000UL) /*!< FILDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos (12UL) /*!< SBDIS (Bit 12) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk (0x1000UL) /*!< SBDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos (0UL) /*!< TCYC (Bit 0) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk (0xffUL) /*!< TCYC (Bitfield-Mask: 0xff) */ +/* ======================================================== SYFORMR ======================================================== */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos (1UL) /*!< FORM1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk (0x2UL) /*!< FORM1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos (0UL) /*!< FORM0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk (0x1UL) /*!< FORM0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTOUTR ======================================================== */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos (0UL) /*!< RSTOUTR (Bit 0) */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTRSTR ========================================================= */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos (0UL) /*!< RESET (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk (0x1UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ======================================================== STCSELR ======================================================== */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos (8UL) /*!< SCLKSEL (Bit 8) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk (0x700UL) /*!< SCLKSEL (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos (0UL) /*!< SCLKDIV (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk (0x7UL) /*!< SCLKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== BYPASS ========================================================= */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos (16UL) /*!< BYPASS1 (Bit 16) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos (0UL) /*!< BYPASS0 (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk (0x1UL) /*!< BYPASS0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MIESR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIEIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPACR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ========================================================= STSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos (0UL) /*!< STCF (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk (0x3UL) /*!< STCF (Bitfield-Mask: 0x03) */ +/* ========================================================= STMR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos (29UL) /*!< ALEN1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos (28UL) /*!< ALEN0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos (20UL) /*!< DVTH (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk (0xf00000UL) /*!< DVTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos (16UL) /*!< SYTH (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk (0xf0000UL) /*!< SYTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos (15UL) /*!< W10S (Bit 15) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk (0x8000UL) /*!< W10S (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos (13UL) /*!< CMOD (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk (0x2000UL) /*!< CMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos (0UL) /*!< WINT (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk (0xffUL) /*!< WINT (Bitfield-Mask: 0xff) */ +/* ======================================================== SYNTOR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos (0UL) /*!< SYNTOR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== IPTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos (5UL) /*!< IPTSEL5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk (0x20UL) /*!< IPTSEL5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos (4UL) /*!< IPTSEL4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk (0x10UL) /*!< IPTSEL4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos (3UL) /*!< IPTSEL3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk (0x8UL) /*!< IPTSEL3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos (2UL) /*!< IPTSEL2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk (0x4UL) /*!< IPTSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos (1UL) /*!< IPTSEL1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk (0x2UL) /*!< IPTSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos (0UL) /*!< IPTSEL0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk (0x1UL) /*!< IPTSEL0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MITSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos (5UL) /*!< MINTEN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk (0x20UL) /*!< MINTEN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos (4UL) /*!< MINTEN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk (0x10UL) /*!< MINTEN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos (3UL) /*!< MINTEN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk (0x8UL) /*!< MINTEN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos (2UL) /*!< MINTEN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk (0x4UL) /*!< MINTEN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos (1UL) /*!< MINTEN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk (0x2UL) /*!< MINTEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos (0UL) /*!< MINTEN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk (0x1UL) /*!< MINTEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos (5UL) /*!< ELTDIS5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk (0x20UL) /*!< ELTDIS5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos (4UL) /*!< ELTDIS4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk (0x10UL) /*!< ELTDIS4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos (3UL) /*!< ELTDIS3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk (0x8UL) /*!< ELTDIS3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos (2UL) /*!< ELTDIS2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk (0x4UL) /*!< ELTDIS2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos (1UL) /*!< ELTDIS1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk (0x2UL) /*!< ELTDIS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos (0UL) /*!< ELTDIS0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk (0x1UL) /*!< ELTDIS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= STCHSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos (0UL) /*!< SYSEL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk (0x1UL) /*!< SYSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNSTARTR ======================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ======================================================== LCIVLDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk (0x1UL) /*!< LOAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNTDARU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos (0UL) /*!< SYNTDARU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDARL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos (0UL) /*!< SYNTDARL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos (0UL) /*!< SYNTDBRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos (0UL) /*!< SYNTDBRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos (0UL) /*!< LCIVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk (0xffffUL) /*!< LCIVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCIVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos (0UL) /*!< LCIVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos (0UL) /*!< LCIVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GETW10R ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos (0UL) /*!< GW10 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk (0x1UL) /*!< GW10 (Bitfield-Mask: 0x01) */ +/* ======================================================= PLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos (0UL) /*!< PLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= PLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos (0UL) /*!< PLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos (0UL) /*!< PLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos (0UL) /*!< MLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= MLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos (0UL) /*!< MLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos (0UL) /*!< MLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GETINFOR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos (0UL) /*!< INFO (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk (0x1UL) /*!< INFO (Bitfield-Mask: 0x01) */ +/* ======================================================== LCCVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos (0UL) /*!< LCCVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk (0xffffUL) /*!< LCCVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCCVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos (0UL) /*!< LCCVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCCVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos (0UL) /*!< LCCVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos (0UL) /*!< PW10VRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos (0UL) /*!< PW10VRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos (0UL) /*!< PW10VRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos (0UL) /*!< MW10RU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos (0UL) /*!< MW10RM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos (0UL) /*!< MW10RL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TMSTARTR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos (5UL) /*!< EN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos (4UL) /*!< EN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos (3UL) /*!< EN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos (2UL) /*!< EN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRNDISR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos (0UL) /*!< TDIS (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk (0x3UL) /*!< TDIS (Bitfield-Mask: 0x03) */ +/* ========================================================= TRNMR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos (9UL) /*!< FWD1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk (0x200UL) /*!< FWD1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos (8UL) /*!< FWD0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk (0x100UL) /*!< FWD0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk (0x1UL) /*!< MOD (Bitfield-Mask: 0x01) */ +/* ======================================================= TRNCTTDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos (0UL) /*!< THVAL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk (0x7ffUL) /*!< THVAL (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_EBFULL_Pos (18UL) /*!< EBFULL (Bit 18) */ + #define R_FACI_HP_FSTATR_EBFULL_Msk (0x40000UL) /*!< EBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTPDTCT_Pos (17UL) /*!< OTPDTCT (Bit 17) */ + #define R_FACI_HP_FSTATR_OTPDTCT_Msk (0x20000UL) /*!< OTPDTCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTPCRCT_Pos (16UL) /*!< OTPCRCT (Bit 16) */ + #define R_FACI_HP_FSTATR_OTPCRCT_Msk (0x10000UL) /*!< OTPCRCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FCUERR_Pos (7UL) /*!< FCUERR (Bit 7) */ + #define R_FACI_HP_FSTATR_FCUERR_Msk (0x80UL) /*!< FCUERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FHVEERR_Pos (6UL) /*!< FHVEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FHVEERR_Msk (0x40UL) /*!< FHVEERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_CFGDTCT_Pos (5UL) /*!< CFGDTCT (Bit 5) */ + #define R_FACI_HP_FSTATR_CFGDTCT_Msk (0x20UL) /*!< CFGDTCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_CFGCRCT_Pos (4UL) /*!< CFGCRCT (Bit 4) */ + #define R_FACI_HP_FSTATR_CFGCRCT_Msk (0x10UL) /*!< CFGCRCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_TBLDTCT_Pos (3UL) /*!< TBLDTCT (Bit 3) */ + #define R_FACI_HP_FSTATR_TBLDTCT_Msk (0x8UL) /*!< TBLDTCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_TBLCRCT_Pos (2UL) /*!< TBLCRCT (Bit 2) */ + #define R_FACI_HP_FSTATR_TBLCRCT_Msk (0x4UL) /*!< TBLCRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (24UL) /*!< TPCS (Bit 24) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7000000UL) /*!< TPCS (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_DLLMOD_Pos (8UL) /*!< DLLMOD (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_DLLMOD_Msk (0x100UL) /*!< DLLMOD (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= JCMOD ========================================================= */ + #define R_JPEG_JCMOD_DSP_Pos (3UL) /*!< DSP (Bit 3) */ + #define R_JPEG_JCMOD_DSP_Msk (0x8UL) /*!< DSP (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCMOD_REDU_Pos (0UL) /*!< REDU (Bit 0) */ + #define R_JPEG_JCMOD_REDU_Msk (0x7UL) /*!< REDU (Bitfield-Mask: 0x07) */ +/* ========================================================= JCCMD ========================================================= */ + #define R_JPEG_JCCMD_BRST_Pos (7UL) /*!< BRST (Bit 7) */ + #define R_JPEG_JCCMD_BRST_Msk (0x80UL) /*!< BRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JEND_Pos (2UL) /*!< JEND (Bit 2) */ + #define R_JPEG_JCCMD_JEND_Msk (0x4UL) /*!< JEND (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JRST_Pos (1UL) /*!< JRST (Bit 1) */ + #define R_JPEG_JCCMD_JRST_Msk (0x2UL) /*!< JRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JSRT_Pos (0UL) /*!< JSRT (Bit 0) */ + #define R_JPEG_JCCMD_JSRT_Msk (0x1UL) /*!< JSRT (Bitfield-Mask: 0x01) */ +/* ========================================================= JCQTN ========================================================= */ + #define R_JPEG_JCQTN_QT3_Pos (4UL) /*!< QT3 (Bit 4) */ + #define R_JPEG_JCQTN_QT3_Msk (0x30UL) /*!< QT3 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT2_Pos (2UL) /*!< QT2 (Bit 2) */ + #define R_JPEG_JCQTN_QT2_Msk (0xcUL) /*!< QT2 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT1_Pos (0UL) /*!< QT1 (Bit 0) */ + #define R_JPEG_JCQTN_QT1_Msk (0x3UL) /*!< QT1 (Bitfield-Mask: 0x03) */ +/* ========================================================= JCHTN ========================================================= */ + #define R_JPEG_JCHTN_HTA3_Pos (5UL) /*!< HTA3 (Bit 5) */ + #define R_JPEG_JCHTN_HTA3_Msk (0x20UL) /*!< HTA3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD3_Pos (4UL) /*!< HTD3 (Bit 4) */ + #define R_JPEG_JCHTN_HTD3_Msk (0x10UL) /*!< HTD3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA2_Pos (3UL) /*!< HTA2 (Bit 3) */ + #define R_JPEG_JCHTN_HTA2_Msk (0x8UL) /*!< HTA2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD2_Pos (2UL) /*!< HTD2 (Bit 2) */ + #define R_JPEG_JCHTN_HTD2_Msk (0x4UL) /*!< HTD2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA1_Pos (1UL) /*!< HTA1 (Bit 1) */ + #define R_JPEG_JCHTN_HTA1_Msk (0x2UL) /*!< HTA1 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD1_Pos (0UL) /*!< HTD1 (Bit 0) */ + #define R_JPEG_JCHTN_HTD1_Msk (0x1UL) /*!< HTD1 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDRIU ========================================================= */ + #define R_JPEG_JCDRIU_DRIU_Pos (0UL) /*!< DRIU (Bit 0) */ + #define R_JPEG_JCDRIU_DRIU_Msk (0xffUL) /*!< DRIU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDRID ========================================================= */ + #define R_JPEG_JCDRID_DRID_Pos (0UL) /*!< DRID (Bit 0) */ + #define R_JPEG_JCDRID_DRID_Msk (0xffUL) /*!< DRID (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZU ========================================================= */ + #define R_JPEG_JCVSZU_VSZU_Pos (0UL) /*!< VSZU (Bit 0) */ + #define R_JPEG_JCVSZU_VSZU_Msk (0xffUL) /*!< VSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZD ========================================================= */ + #define R_JPEG_JCVSZD_VSZD_Pos (0UL) /*!< VSZD (Bit 0) */ + #define R_JPEG_JCVSZD_VSZD_Msk (0xffUL) /*!< VSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZU ========================================================= */ + #define R_JPEG_JCHSZU_HSZU_Pos (0UL) /*!< HSZU (Bit 0) */ + #define R_JPEG_JCHSZU_HSZU_Msk (0xffUL) /*!< HSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZD ========================================================= */ + #define R_JPEG_JCHSZD_HSZD_Pos (0UL) /*!< HSZD (Bit 0) */ + #define R_JPEG_JCHSZD_HSZD_Msk (0xffUL) /*!< HSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCU ========================================================= */ + #define R_JPEG_JCDTCU_DCU_Pos (0UL) /*!< DCU (Bit 0) */ + #define R_JPEG_JCDTCU_DCU_Msk (0xffUL) /*!< DCU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCM ========================================================= */ + #define R_JPEG_JCDTCM_DCM_Pos (0UL) /*!< DCM (Bit 0) */ + #define R_JPEG_JCDTCM_DCM_Msk (0xffUL) /*!< DCM (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCD ========================================================= */ + #define R_JPEG_JCDTCD_DCD_Pos (0UL) /*!< DCD (Bit 0) */ + #define R_JPEG_JCDTCD_DCD_Msk (0xffUL) /*!< DCD (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE0 ========================================================= */ + #define R_JPEG_JINTE0_INT7_Pos (7UL) /*!< INT7 (Bit 7) */ + #define R_JPEG_JINTE0_INT7_Msk (0x80UL) /*!< INT7 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT6_Pos (6UL) /*!< INT6 (Bit 6) */ + #define R_JPEG_JINTE0_INT6_Msk (0x40UL) /*!< INT6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT5_Pos (5UL) /*!< INT5 (Bit 5) */ + #define R_JPEG_JINTE0_INT5_Msk (0x20UL) /*!< INT5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT3_Pos (3UL) /*!< INT3 (Bit 3) */ + #define R_JPEG_JINTE0_INT3_Msk (0x8UL) /*!< INT3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS0 ========================================================= */ + #define R_JPEG_JINTS0_INS6_Pos (6UL) /*!< INS6 (Bit 6) */ + #define R_JPEG_JINTS0_INS6_Msk (0x40UL) /*!< INS6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS5_Pos (5UL) /*!< INS5 (Bit 5) */ + #define R_JPEG_JINTS0_INS5_Msk (0x20UL) /*!< INS5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS3_Pos (3UL) /*!< INS3 (Bit 3) */ + #define R_JPEG_JINTS0_INS3_Msk (0x8UL) /*!< INS3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDERR ========================================================= */ + #define R_JPEG_JCDERR_ERR_Pos (0UL) /*!< ERR (Bit 0) */ + #define R_JPEG_JCDERR_ERR_Msk (0xfUL) /*!< ERR (Bitfield-Mask: 0x0f) */ +/* ========================================================= JCRST ========================================================= */ + #define R_JPEG_JCRST_RST_Pos (0UL) /*!< RST (Bit 0) */ + #define R_JPEG_JCRST_RST_Msk (0x1UL) /*!< RST (Bitfield-Mask: 0x01) */ +/* ======================================================== JIFECNT ======================================================== */ + #define R_JPEG_JIFECNT_JOUTSWAP_Pos (8UL) /*!< JOUTSWAP (Bit 8) */ + #define R_JPEG_JIFECNT_JOUTSWAP_Msk (0x700UL) /*!< JOUTSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFECNT_DINRINI_Pos (6UL) /*!< DINRINI (Bit 6) */ + #define R_JPEG_JIFECNT_DINRINI_Msk (0x40UL) /*!< DINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINRCMD_Pos (5UL) /*!< DINRCMD (Bit 5) */ + #define R_JPEG_JIFECNT_DINRCMD_Msk (0x20UL) /*!< DINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINLC_Pos (4UL) /*!< DINLC (Bit 4) */ + #define R_JPEG_JIFECNT_DINLC_Msk (0x10UL) /*!< DINLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINSWAP_Pos (0UL) /*!< DINSWAP (Bit 0) */ + #define R_JPEG_JIFECNT_DINSWAP_Msk (0x7UL) /*!< DINSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFESA ========================================================= */ + #define R_JPEG_JIFESA_ESA_Pos (0UL) /*!< ESA (Bit 0) */ + #define R_JPEG_JIFESA_ESA_Msk (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFESOFST ======================================================= */ + #define R_JPEG_JIFESOFST_ESMW_Pos (0UL) /*!< ESMW (Bit 0) */ + #define R_JPEG_JIFESOFST_ESMW_Msk (0x7fffUL) /*!< ESMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFEDA ========================================================= */ + #define R_JPEG_JIFEDA_EDA_Pos (0UL) /*!< EDA (Bit 0) */ + #define R_JPEG_JIFEDA_EDA_Msk (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFESLC ======================================================== */ + #define R_JPEG_JIFESLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFESLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDCNT ======================================================== */ + #define R_JPEG_JIFDCNT_VINTER_Pos (28UL) /*!< VINTER (Bit 28) */ + #define R_JPEG_JIFDCNT_VINTER_Msk (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_HINTER_Pos (26UL) /*!< HINTER (Bit 26) */ + #define R_JPEG_JIFDCNT_HINTER_Msk (0xc000000UL) /*!< HINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_OPF_Pos (24UL) /*!< OPF (Bit 24) */ + #define R_JPEG_JIFDCNT_OPF_Msk (0x3000000UL) /*!< OPF (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_JINRINI_Pos (14UL) /*!< JINRINI (Bit 14) */ + #define R_JPEG_JIFDCNT_JINRINI_Msk (0x4000UL) /*!< JINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINRCMD_Pos (13UL) /*!< JINRCMD (Bit 13) */ + #define R_JPEG_JIFDCNT_JINRCMD_Msk (0x2000UL) /*!< JINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINC_Pos (12UL) /*!< JINC (Bit 12) */ + #define R_JPEG_JIFDCNT_JINC_Msk (0x1000UL) /*!< JINC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINSWAP_Pos (8UL) /*!< JINSWAP (Bit 8) */ + #define R_JPEG_JIFDCNT_JINSWAP_Msk (0x700UL) /*!< JINSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Pos (6UL) /*!< DOUTRINI (Bit 6) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Msk (0x40UL) /*!< DOUTRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Pos (5UL) /*!< DOUTRCMD (Bit 5) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Msk (0x20UL) /*!< DOUTRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTLC_Pos (4UL) /*!< DOUTLC (Bit 4) */ + #define R_JPEG_JIFDCNT_DOUTLC_Msk (0x10UL) /*!< DOUTLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Pos (0UL) /*!< DOUTSWAP (Bit 0) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Msk (0x7UL) /*!< DOUTSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFDSA ========================================================= */ + #define R_JPEG_JIFDSA_DSA_Pos (0UL) /*!< DSA (Bit 0) */ + #define R_JPEG_JIFDSA_DSA_Msk (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFDDOFST ======================================================= */ + #define R_JPEG_JIFDDOFST_DDMW_Pos (0UL) /*!< DDMW (Bit 0) */ + #define R_JPEG_JIFDDOFST_DDMW_Msk (0x7fffUL) /*!< DDMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFDDA ========================================================= */ + #define R_JPEG_JIFDDA_DDA_Pos (0UL) /*!< DDA (Bit 0) */ + #define R_JPEG_JIFDDA_DDA_Msk (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFDSDC ======================================================== */ + #define R_JPEG_JIFDSDC_JDATAS_Pos (0UL) /*!< JDATAS (Bit 0) */ + #define R_JPEG_JIFDSDC_JDATAS_Msk (0xffffUL) /*!< JDATAS (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDDLC ======================================================== */ + #define R_JPEG_JIFDDLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFDDLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDADT ======================================================== */ + #define R_JPEG_JIFDADT_ALPHA_Pos (0UL) /*!< ALPHA (Bit 0) */ + #define R_JPEG_JIFDADT_ALPHA_Msk (0xffUL) /*!< ALPHA (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE1 ========================================================= */ + #define R_JPEG_JINTE1_CBTEN_Pos (6UL) /*!< CBTEN (Bit 6) */ + #define R_JPEG_JINTE1_CBTEN_Msk (0x40UL) /*!< CBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DINLEN_Pos (5UL) /*!< DINLEN (Bit 5) */ + #define R_JPEG_JINTE1_DINLEN_Msk (0x20UL) /*!< DINLEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DBTEN_Pos (2UL) /*!< DBTEN (Bit 2) */ + #define R_JPEG_JINTE1_DBTEN_Msk (0x4UL) /*!< DBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_JINEN_Pos (1UL) /*!< JINEN (Bit 1) */ + #define R_JPEG_JINTE1_JINEN_Msk (0x2UL) /*!< JINEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DOUTLEN_Pos (0UL) /*!< DOUTLEN (Bit 0) */ + #define R_JPEG_JINTE1_DOUTLEN_Msk (0x1UL) /*!< DOUTLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS1 ========================================================= */ + #define R_JPEG_JINTS1_CBTF_Pos (6UL) /*!< CBTF (Bit 6) */ + #define R_JPEG_JINTS1_CBTF_Msk (0x40UL) /*!< CBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DINLF_Pos (5UL) /*!< DINLF (Bit 5) */ + #define R_JPEG_JINTS1_DINLF_Msk (0x20UL) /*!< DINLF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DBTF_Pos (2UL) /*!< DBTF (Bit 2) */ + #define R_JPEG_JINTS1_DBTF_Msk (0x4UL) /*!< DBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_JINF_Pos (1UL) /*!< JINF (Bit 1) */ + #define R_JPEG_JINTS1_JINF_Msk (0x2UL) /*!< JINF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DOUTLF_Pos (0UL) /*!< DOUTLF (Bit 0) */ + #define R_JPEG_JINTS1_DOUTLF_Msk (0x1UL) /*!< DOUTLF (Bitfield-Mask: 0x01) */ +/* ======================================================== JCQTBL0 ======================================================== */ +/* ======================================================== JCQTBL1 ======================================================== */ +/* ======================================================== JCQTBL2 ======================================================== */ +/* ======================================================== JCQTBL3 ======================================================== */ +/* ======================================================== JCHTBD0 ======================================================== */ +/* ======================================================== JCHTBD1 ======================================================== */ +/* ======================================================== JCHTBA0 ======================================================== */ +/* ======================================================== JCHTBA1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SMPUCTL ======================================================== */ + #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AMPMC ========================================================= */ + #define R_OPAMP_AMPMC_AMPSP_Pos (7UL) /*!< AMPSP (Bit 7) */ + #define R_OPAMP_AMPMC_AMPSP_Msk (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPMC_AMPPC_Pos (0UL) /*!< AMPPC (Bit 0) */ + #define R_OPAMP_AMPMC_AMPPC_Msk (0x1UL) /*!< AMPPC (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPTRM ========================================================= */ + #define R_OPAMP_AMPTRM_AMPTRM_Pos (0UL) /*!< AMPTRM (Bit 0) */ + #define R_OPAMP_AMPTRM_AMPTRM_Msk (0x3UL) /*!< AMPTRM (Bitfield-Mask: 0x03) */ +/* ======================================================== AMPTRS ========================================================= */ + #define R_OPAMP_AMPTRS_AMPTRS_Pos (0UL) /*!< AMPTRS (Bit 0) */ + #define R_OPAMP_AMPTRS_AMPTRS_Msk (0x3UL) /*!< AMPTRS (Bitfield-Mask: 0x03) */ +/* ========================================================= AMPC ========================================================== */ + #define R_OPAMP_AMPC_IREFE_Pos (7UL) /*!< IREFE (Bit 7) */ + #define R_OPAMP_AMPC_IREFE_Msk (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPC_AMPE_Pos (0UL) /*!< AMPE (Bit 0) */ + #define R_OPAMP_AMPC_AMPE_Msk (0x1UL) /*!< AMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPMON ========================================================= */ + #define R_OPAMP_AMPMON_AMPMON_Pos (0UL) /*!< AMPMON (Bit 0) */ + #define R_OPAMP_AMPMON_AMPMON_Msk (0x1UL) /*!< AMPMON (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPCPC ========================================================= */ + #define R_OPAMP_AMPCPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_OPAMP_AMPCPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPUOTE ======================================================== */ + #define R_OPAMP_AMPUOTE_AMPTE_Pos (0UL) /*!< AMPTE (Bit 0) */ + #define R_OPAMP_AMPUOTE_AMPTE_Msk (0x1UL) /*!< AMPTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCCR0 ========================================================= */ + #define R_PDC_PCCR0_EDS_Pos (14UL) /*!< EDS (Bit 14) */ + #define R_PDC_PCCR0_EDS_Msk (0x4000UL) /*!< EDS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKDIV_Pos (11UL) /*!< PCKDIV (Bit 11) */ + #define R_PDC_PCCR0_PCKDIV_Msk (0x3800UL) /*!< PCKDIV (Bitfield-Mask: 0x07) */ + #define R_PDC_PCCR0_PCKOE_Pos (10UL) /*!< PCKOE (Bit 10) */ + #define R_PDC_PCCR0_PCKOE_Msk (0x400UL) /*!< PCKOE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HERIE_Pos (9UL) /*!< HERIE (Bit 9) */ + #define R_PDC_PCCR0_HERIE_Msk (0x200UL) /*!< HERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VERIE_Pos (8UL) /*!< VERIE (Bit 8) */ + #define R_PDC_PCCR0_VERIE_Msk (0x100UL) /*!< VERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_UDRIE_Pos (7UL) /*!< UDRIE (Bit 7) */ + #define R_PDC_PCCR0_UDRIE_Msk (0x80UL) /*!< UDRIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_OVIE_Pos (6UL) /*!< OVIE (Bit 6) */ + #define R_PDC_PCCR0_OVIE_Msk (0x40UL) /*!< OVIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_FEIE_Pos (5UL) /*!< FEIE (Bit 5) */ + #define R_PDC_PCCR0_FEIE_Msk (0x20UL) /*!< FEIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_DFIE_Pos (4UL) /*!< DFIE (Bit 4) */ + #define R_PDC_PCCR0_DFIE_Msk (0x10UL) /*!< DFIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PRST_Pos (3UL) /*!< PRST (Bit 3) */ + #define R_PDC_PCCR0_PRST_Msk (0x8UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HPS_Pos (2UL) /*!< HPS (Bit 2) */ + #define R_PDC_PCCR0_HPS_Msk (0x4UL) /*!< HPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VPS_Pos (1UL) /*!< VPS (Bit 1) */ + #define R_PDC_PCCR0_VPS_Msk (0x2UL) /*!< VPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKE_Pos (0UL) /*!< PCKE (Bit 0) */ + #define R_PDC_PCCR0_PCKE_Msk (0x1UL) /*!< PCKE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCCR1 ========================================================= */ + #define R_PDC_PCCR1_PCE_Pos (0UL) /*!< PCE (Bit 0) */ + #define R_PDC_PCCR1_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCSR ========================================================== */ + #define R_PDC_PCSR_HERF_Pos (6UL) /*!< HERF (Bit 6) */ + #define R_PDC_PCSR_HERF_Msk (0x40UL) /*!< HERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_VERF_Pos (5UL) /*!< VERF (Bit 5) */ + #define R_PDC_PCSR_VERF_Msk (0x20UL) /*!< VERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_PDC_PCSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_OVRF_Pos (3UL) /*!< OVRF (Bit 3) */ + #define R_PDC_PCSR_OVRF_Msk (0x8UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEF_Pos (2UL) /*!< FEF (Bit 2) */ + #define R_PDC_PCSR_FEF_Msk (0x4UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEMPF_Pos (1UL) /*!< FEMPF (Bit 1) */ + #define R_PDC_PCSR_FEMPF_Msk (0x2UL) /*!< FEMPF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FBSY_Pos (0UL) /*!< FBSY (Bit 0) */ + #define R_PDC_PCSR_FBSY_Msk (0x1UL) /*!< FBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PCMONR ========================================================= */ + #define R_PDC_PCMONR_HSYNC_Pos (1UL) /*!< HSYNC (Bit 1) */ + #define R_PDC_PCMONR_HSYNC_Msk (0x2UL) /*!< HSYNC (Bitfield-Mask: 0x01) */ + #define R_PDC_PCMONR_VSYNC_Pos (0UL) /*!< VSYNC (Bit 0) */ + #define R_PDC_PCMONR_VSYNC_Msk (0x1UL) /*!< VSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PCDR ========================================================== */ + #define R_PDC_PCDR_PCDR_Pos (0UL) /*!< PCDR (Bit 0) */ + #define R_PDC_PCDR_PCDR_Msk (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== VCR ========================================================== */ + #define R_PDC_VCR_VSZ_Pos (16UL) /*!< VSZ (Bit 16) */ + #define R_PDC_VCR_VSZ_Msk (0xfff0000UL) /*!< VSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_VCR_VST_Pos (0UL) /*!< VST (Bit 0) */ + #define R_PDC_VCR_VST_Msk (0xfffUL) /*!< VST (Bitfield-Mask: 0xfff) */ +/* ========================================================== HCR ========================================================== */ + #define R_PDC_HCR_HSZ_Pos (16UL) /*!< HSZ (Bit 16) */ + #define R_PDC_HCR_HSZ_Msk (0xfff0000UL) /*!< HSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_HCR_HST_Pos (0UL) /*!< HST (Bit 0) */ + #define R_PDC_HCR_HST_Msk (0xfffUL) /*!< HST (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STC1 ========================================================== */ + #define R_SDADC0_STC1_VSBIAS_Pos (8UL) /*!< VSBIAS (Bit 8) */ + #define R_SDADC0_STC1_VSBIAS_Msk (0xf00UL) /*!< VSBIAS (Bitfield-Mask: 0x0f) */ + #define R_SDADC0_STC1_CLKDIV_Pos (0UL) /*!< CLKDIV (Bit 0) */ + #define R_SDADC0_STC1_CLKDIV_Msk (0xfUL) /*!< CLKDIV (Bitfield-Mask: 0x0f) */ + #define R_SDADC0_STC1_SDADLPM_Pos (7UL) /*!< SDADLPM (Bit 7) */ + #define R_SDADC0_STC1_SDADLPM_Msk (0x80UL) /*!< SDADLPM (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC1_VREFSEL_Pos (15UL) /*!< VREFSEL (Bit 15) */ + #define R_SDADC0_STC1_VREFSEL_Msk (0x8000UL) /*!< VREFSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= STC2 ========================================================== */ + #define R_SDADC0_STC2_BGRPON_Pos (0UL) /*!< BGRPON (Bit 0) */ + #define R_SDADC0_STC2_BGRPON_Msk (0x1UL) /*!< BGRPON (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC2_ADFPWDS_Pos (2UL) /*!< ADFPWDS (Bit 2) */ + #define R_SDADC0_STC2_ADFPWDS_Msk (0x4UL) /*!< ADFPWDS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC2_ADCPON_Pos (1UL) /*!< ADCPON (Bit 1) */ + #define R_SDADC0_STC2_ADCPON_Msk (0x2UL) /*!< ADCPON (Bitfield-Mask: 0x01) */ +/* ========================================================= PGAC ========================================================== */ + #define R_SDADC0_PGAC_PGAASN_Pos (31UL) /*!< PGAASN (Bit 31) */ + #define R_SDADC0_PGAC_PGAASN_Msk (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGACVE_Pos (30UL) /*!< PGACVE (Bit 30) */ + #define R_SDADC0_PGAC_PGACVE_Msk (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAREV_Pos (28UL) /*!< PGAREV (Bit 28) */ + #define R_SDADC0_PGAC_PGAREV_Msk (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAAVE_Pos (26UL) /*!< PGAAVE (Bit 26) */ + #define R_SDADC0_PGAC_PGAAVE_Msk (0xc000000UL) /*!< PGAAVE (Bitfield-Mask: 0x03) */ + #define R_SDADC0_PGAC_PGAAVN_Pos (24UL) /*!< PGAAVN (Bit 24) */ + #define R_SDADC0_PGAC_PGAAVN_Msk (0x3000000UL) /*!< PGAAVN (Bitfield-Mask: 0x03) */ + #define R_SDADC0_PGAC_PGACTN_Pos (21UL) /*!< PGACTN (Bit 21) */ + #define R_SDADC0_PGAC_PGACTN_Msk (0xe00000UL) /*!< PGACTN (Bitfield-Mask: 0x07) */ + #define R_SDADC0_PGAC_PGACTM_Pos (16UL) /*!< PGACTM (Bit 16) */ + #define R_SDADC0_PGAC_PGACTM_Msk (0x1f0000UL) /*!< PGACTM (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_PGAC_PGASEL_Pos (15UL) /*!< PGASEL (Bit 15) */ + #define R_SDADC0_PGAC_PGASEL_Msk (0x8000UL) /*!< PGASEL (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAPOL_Pos (14UL) /*!< PGAPOL (Bit 14) */ + #define R_SDADC0_PGAC_PGAPOL_Msk (0x4000UL) /*!< PGAPOL (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAOFS_Pos (8UL) /*!< PGAOFS (Bit 8) */ + #define R_SDADC0_PGAC_PGAOFS_Msk (0x1f00UL) /*!< PGAOFS (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_PGAC_PGAOSR_Pos (5UL) /*!< PGAOSR (Bit 5) */ + #define R_SDADC0_PGAC_PGAOSR_Msk (0xe0UL) /*!< PGAOSR (Bitfield-Mask: 0x07) */ + #define R_SDADC0_PGAC_PGAGC_Pos (0UL) /*!< PGAGC (Bit 0) */ + #define R_SDADC0_PGAC_PGAGC_Msk (0x1fUL) /*!< PGAGC (Bitfield-Mask: 0x1f) */ +/* ========================================================= ADC1 ========================================================== */ + #define R_SDADC0_ADC1_PGASLFT_Pos (20UL) /*!< PGASLFT (Bit 20) */ + #define R_SDADC0_ADC1_PGASLFT_Msk (0x100000UL) /*!< PGASLFT (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_PGADISC_Pos (17UL) /*!< PGADISC (Bit 17) */ + #define R_SDADC0_ADC1_PGADISC_Msk (0x20000UL) /*!< PGADISC (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_PGADISA_Pos (16UL) /*!< PGADISA (Bit 16) */ + #define R_SDADC0_ADC1_PGADISA_Msk (0x10000UL) /*!< PGADISA (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_SDADBMP_Pos (8UL) /*!< SDADBMP (Bit 8) */ + #define R_SDADC0_ADC1_SDADBMP_Msk (0x1f00UL) /*!< SDADBMP (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_ADC1_SDADTMD_Pos (4UL) /*!< SDADTMD (Bit 4) */ + #define R_SDADC0_ADC1_SDADTMD_Msk (0x10UL) /*!< SDADTMD (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_SDADSCM_Pos (0UL) /*!< SDADSCM (Bit 0) */ + #define R_SDADC0_ADC1_SDADSCM_Msk (0x1UL) /*!< SDADSCM (Bitfield-Mask: 0x01) */ +/* ========================================================= ADC2 ========================================================== */ + #define R_SDADC0_ADC2_SDADST_Pos (0UL) /*!< SDADST (Bit 0) */ + #define R_SDADC0_ADC2_SDADST_Msk (0x1UL) /*!< SDADST (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCR ========================================================== */ + #define R_SDADC0_ADCR_SDADCRC_Pos (25UL) /*!< SDADCRC (Bit 25) */ + #define R_SDADC0_ADCR_SDADCRC_Msk (0xe000000UL) /*!< SDADCRC (Bitfield-Mask: 0x07) */ + #define R_SDADC0_ADCR_SDADCRS_Pos (24UL) /*!< SDADCRS (Bit 24) */ + #define R_SDADC0_ADCR_SDADCRS_Msk (0x1000000UL) /*!< SDADCRS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADCR_SDADCRD_Pos (0UL) /*!< SDADCRD (Bit 0) */ + #define R_SDADC0_ADCR_SDADCRD_Msk (0xffffffUL) /*!< SDADCRD (Bitfield-Mask: 0xffffff) */ +/* ========================================================= ADAR ========================================================== */ + #define R_SDADC0_ADAR_SDADMVC_Pos (25UL) /*!< SDADMVC (Bit 25) */ + #define R_SDADC0_ADAR_SDADMVC_Msk (0xe000000UL) /*!< SDADMVC (Bitfield-Mask: 0x07) */ + #define R_SDADC0_ADAR_SDADMVS_Pos (24UL) /*!< SDADMVS (Bit 24) */ + #define R_SDADC0_ADAR_SDADMVS_Msk (0x1000000UL) /*!< SDADMVS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADAR_SDADMVD_Pos (0UL) /*!< SDADMVD (Bit 0) */ + #define R_SDADC0_ADAR_SDADMVD_Msk (0xffffffUL) /*!< SDADMVD (Bitfield-Mask: 0xffffff) */ +/* ========================================================= CLBC ========================================================== */ + #define R_SDADC0_CLBC_CLBMD_Pos (0UL) /*!< CLBMD (Bit 0) */ + #define R_SDADC0_CLBC_CLBMD_Msk (0x3UL) /*!< CLBMD (Bitfield-Mask: 0x03) */ +/* ======================================================== CLBSTR ========================================================= */ + #define R_SDADC0_CLBSTR_CLBST_Pos (0UL) /*!< CLBST (Bit 0) */ + #define R_SDADC0_CLBSTR_CLBST_Msk (0x1UL) /*!< CLBST (Bitfield-Mask: 0x01) */ +/* ======================================================== CLBSSR ========================================================= */ + #define R_SDADC0_CLBSSR_CLBSS_Pos (0UL) /*!< CLBSS (Bit 0) */ + #define R_SDADC0_CLBSSR_CLBSS_Msk (0x1UL) /*!< CLBSS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LCDM0 ========================================================= */ + #define R_SLCDC_LCDM0_MDSET_Pos (6UL) /*!< MDSET (Bit 6) */ + #define R_SLCDC_LCDM0_MDSET_Msk (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03) */ + #define R_SLCDC_LCDM0_LWAVE_Pos (5UL) /*!< LWAVE (Bit 5) */ + #define R_SLCDC_LCDM0_LWAVE_Msk (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM0_LDTY_Pos (2UL) /*!< LDTY (Bit 2) */ + #define R_SLCDC_LCDM0_LDTY_Msk (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07) */ + #define R_SLCDC_LCDM0_LBAS_Pos (0UL) /*!< LBAS (Bit 0) */ + #define R_SLCDC_LCDM0_LBAS_Msk (0x3UL) /*!< LBAS (Bitfield-Mask: 0x03) */ +/* ========================================================= LCDM1 ========================================================= */ + #define R_SLCDC_LCDM1_LCDON_Pos (7UL) /*!< LCDON (Bit 7) */ + #define R_SLCDC_LCDM1_LCDON_Msk (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_SCOC_Pos (6UL) /*!< SCOC (Bit 6) */ + #define R_SLCDC_LCDM1_SCOC_Msk (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_VLCON_Pos (5UL) /*!< VLCON (Bit 5) */ + #define R_SLCDC_LCDM1_VLCON_Msk (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_BLON_Pos (4UL) /*!< BLON (Bit 4) */ + #define R_SLCDC_LCDM1_BLON_Msk (0x10UL) /*!< BLON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDSEL_Pos (3UL) /*!< LCDSEL (Bit 3) */ + #define R_SLCDC_LCDM1_LCDSEL_Msk (0x8UL) /*!< LCDSEL (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDVLM_Pos (0UL) /*!< LCDVLM (Bit 0) */ + #define R_SLCDC_LCDM1_LCDVLM_Msk (0x1UL) /*!< LCDVLM (Bitfield-Mask: 0x01) */ +/* ========================================================= LCDC0 ========================================================= */ + #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */ + #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */ +/* ========================================================= VLCD ========================================================== */ + #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */ + #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */ +/* ========================================================== SEG ========================================================== */ + #define R_SLCDC_SEG_A_Pos (0UL) /*!< A (Bit 0) */ + #define R_SLCDC_SEG_A_Msk (0xfUL) /*!< A (Bitfield-Mask: 0x0f) */ + #define R_SLCDC_SEG_B_Pos (4UL) /*!< B (Bit 4) */ + #define R_SLCDC_SEG_B_Msk (0xf0UL) /*!< B (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_SRAMHSWTEN_Pos (4UL) /*!< SRAMHSWTEN (Bit 4) */ + #define R_SRAM_SRAMWTSC_SRAMHSWTEN_Msk (0x10UL) /*!< SRAMHSWTEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMWTSC_SRAM1WTEN_Pos (3UL) /*!< SRAM1WTEN (Bit 3) */ + #define R_SRAM_SRAMWTSC_SRAM1WTEN_Msk (0x8UL) /*!< SRAM1WTEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMWTSC_SRAM0WTEN_Pos (2UL) /*!< SRAM0WTEN (Bit 2) */ + #define R_SRAM_SRAMWTSC_SRAM0WTEN_Msk (0x4UL) /*!< SRAM0WTEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMWTSC_ECCRAMRDWTEN_Pos (1UL) /*!< ECCRAMRDWTEN (Bit 1) */ + #define R_SRAM_SRAMWTSC_ECCRAMRDWTEN_Msk (0x2UL) /*!< ECCRAMRDWTEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMWTSC_ECCRAMWRWTEN_Pos (0UL) /*!< ECCRAMWRWTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_ECCRAMWRWTEN_Msk (0x1UL) /*!< ECCRAMWRWTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 0000000000..1f8d6c4398 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd new file mode 100644 index 0000000000..231b936f36 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd @@ -0,0 +1,75474 @@ + + + Renesas + Renesas + RA + All Chips + x.xx + Renesas RA All MCU + 8 + 32 + + + R_ACMPHS0 + High-Speed Analog Comparator + 0x40085000 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + 0x0000000C + 0x01 + registers + + + 0x00000010 + 0x01 + registers + + + + CMPCTL + Comparator Control Register + 0x000 + 8 + read-write + 0x00 + 0xFF + + + HCMPON + Comparator operation control + 7 + 7 + read-write + + + 0 + Operation stopped (the comparator outputs a low-level signal) + #0 + + + 1 + Operation enabled (input to the comparator pins is enabled + #1 + + + + + CDFS + Noise filter selection + 5 + 6 + read-write + + + 00 + Noise filter not used. + #00 + + + 01 + Noise filter sampling frequency is 2^3/PCLKB. + #01 + + + 10 + Noise filter sampling frequency is 2^4/PCLKB. + #10 + + + 11 + Noise filter sampling frequency is 2^5/PCLKB. + #11 + + + + + CEG + Selection of valid edge (Edge selector) + 3 + 4 + read-write + + + 00 + No edge selection. + #00 + + + 01 + Rising edge selection. + #01 + + + 10 + Falling edge selection + #10 + + + 11 + Both-edge selection + #11 + + + + + CSTEN + Interrupt Select + 2 + 2 + read-write + + + 0 + Output via the Edge selector + #0 + + + 1 + Direct output + #1 + + + + + COE + Comparator output enable + 1 + 1 + read-write + + + 0 + Comparator output disabled (the output signal is low level). + #0 + + + 1 + Comparator output enabled + #1 + + + + + CINV + Comparator output polarity selection + 0 + 0 + read-write + + + 0 + Comparator output not inverted + #0 + + + 1 + Comparator output inverted + #1 + + + + + + + CMPSEL0 + Comparator Input Select Register + 0x004 + 8 + read-write + 0x00 + 0xFF + + + CMPSEL + Comparator Input Selection + [3:0] + read-write + + + 0000 + Do not input + 0 + + + 0001 + Select IVCMP0 + 1 + + + 0010 + Select IVCMP1 + 2 + + + 0100 + Select IVCMP2 + 4 + + + 1000 + Select IVCMP3 + 8 + + + + + + + CMPSEL1 + Comparator Reference Voltage Select Register + 0x008 + 8 + read-write + 0x00 + 0xFF + + + CRVS + Reference Voltage Selection + [5:0] + read-write + + + 0000 + Do not input + 0 + + + 0001 + Select IVREF0 + 1 + + + 0010 + Select IVREF1 + 2 + + + 0100 + Select IVREF2 + 4 + + + 1000 + Select IVREF3 + 8 + 010000 + Select IVREF4 + 16 + 100000 + Select IVREF5 + 32 + + + + + + + CMPMON + Comparator Output Monitor Register + 0x00C + 8 + read-only + 0x00 + 0xFF + + + CMPMON + Comparator output monitor + 0 + 0 + read-only + + + 0 + Comparator output Low + #0 + + + 1 + Comparator output High + #1 + + + + + + + CPIOC + Comparator Output Control Register + 0x010 + 8 + read-write + 0x00 + 0xFF + + + VREFEN + Internal Vref enable + 7 + 7 + read-write + + + 0 + Internal Vref disable + #0 + + + 1 + Internal Vref enable + #1 + + + + + CPOE + Comparator output selection + 0 + 0 + read-write + + + 0 + VCOUT pin output of the comparator is disabled (the output signal is low level). + #0 + + + 1 + VCOUT pin output of the comparator is enabled + #1 + + + + + + + + + R_ACMPHS1 + 0x40085100 + + + R_ACMPHS2 + 0x40085200 + + + R_ACMPHS3 + 0x40085300 + + + R_ACMPHS4 + 0x40085400 + + + R_ACMPHS5 + 0x40085500 + + + R_ACMPLP + Low-Power Analog Comparator + 0x40085E00 + + 0x00000000 + 0x003 + registers + + + 0x00000004 + 0x002 + registers + + + + COMPMDR + ACMPLP Mode Setting Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + C1MON + ACMPLP1 Monitor Flag + 7 + 7 + read-only + + + 0 + CMPIN1 < CMPREF1, CMPIN1 < internal reference voltage, or ACMPLP1 operation disabled.(When the window function is disabled)/CMPIN1 < VRFL, CMPIN1 > VRFH, or ACMPLP1 operation disabled.(When the window function is enabled) + #0 + + + 1 + CMPIN1 > CMPREF1, or CMPIN1 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN1 < VRFH.(When the window function is enabled) + #1 + + + + + C1VRF + ACMPLP1 Reference Voltage Selection + 6 + 6 + read-write + + + 0 + Select CMPREF1 input as ACMPLP1 reference voltage. + #0 + + + 1 + Select internal reference voltage (Vref) as ACMPLP1 reference voltage. + #1 + + + + + C1WDE + ACMPLP1 Window Function Mode Enable + 5 + 5 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + C1ENB + ACMPLP1 Operation Enable + 4 + 4 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + C0MON + ACMPLP0 Monitor Flag + 3 + 3 + read-only + + + 0 + CMPIN0 < CMPREF0, CMPIN0 < internal reference voltage, or ACMPLP0 operation disabled.(When the window function is disabled)/CMPIN0 < VRFL, CMPIN0 > VRFH, or ACMPLP0 operation disabled.(When the window function is enabled) + #0 + + + 1 + CMPIN0 > CMPREF0, or CMPIN0 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN0 < VRFH.(When the window function is enabled) + #1 + + + + + C0WDE + ACMPLP0 Window Function Mode Enable + 1 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + C0VRF + ACMPLP0 Reference Voltage Selection + 2 + 2 + read-write + + + 0 + Select CMPREF0 input as ACMPLP0 reference voltage. + #0 + + + 1 + Select internal reference voltage (Vref) as ACMPLP0 reference voltage. + #1 + + + + + C0ENB + ACMPLP0 Operation Enable + 0 + 0 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + COMPFIR + ACMPLP Filter Control Register + 0x01 + 8 + read-write + 0x00 + 0xFF + + + C1EDG + ACMPLP1 Edge Detection Selection + 7 + 7 + read-write + + + 0 + Interrupt and ELC event request by one-edge detection + #0 + + + 1 + Interrupt and ELC event request by both-edge detection + #1 + + + + + C1EPO + ACMPLP1 Edge Polarity Switching + 6 + 6 + read-write + + + 0 + Interrupt and ELC event request at rising edge + #0 + + + 1 + Interrupt and ELC event request at falling edge + #1 + + + + + C1FCK + ACMPLP1 Filter Select + 4 + 5 + read-write + + + 00 + No Sampling (bypass) + #00 + + + 01 + Sampling at PCLK + #01 + + + 10 + Sampling at PCLK/8 + #10 + + + 11 + Sampling at PCLK/32 + #11 + + + + + C0EDG + ACMPLP0 Edge Detection Selection + 3 + 3 + read-write + + + 0 + Interrupt and ELC event request by one-edge detection + #0 + + + 1 + Interrupt and ELC event request by both-edge detection + #1 + + + + + C0EPO + ACMPLP0 Edge Polarity Switching + 2 + 2 + read-write + + + 0 + Interrupt and ELC event request at rising edge + #0 + + + 1 + Interrupt and ELC event request at falling edge + #1 + + + + + C0FCK + ACMPLP0 Filter Select + 0 + 1 + read-write + + + 00 + No Sampling (bypass) + #00 + + + 01 + Sampling at PCLK + #01 + + + 10 + Sampling at PCLK/8 + #10 + + + 11 + Sampling at PCLK/32 + #11 + + + + + + + COMPOCR + ACMPLP Output Control Register + 0x02 + 8 + read-write + 0x00 + 0xFF + + + SPDMD + ACMPLP0/ACMPLP1 Speed Selection + 7 + 7 + read-write + + + 0 + Comparator low-speed mode + #0 + + + 1 + Comparator high-speed mode + #1 + + + + + C1OP + ACMPLP1 VCOUT Output Polarity Selection + 6 + 6 + read-write + + + 0 + Non inverted + #0 + + + 1 + Inverted + #1 + + + + + C1OE + ACMPLP1 VCOUT Pin Output Enable + 5 + 5 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + C0OP + ACMPLP0 VCOUT Output Polarity Selection + 2 + 2 + read-write + + + 0 + Non inverted + #0 + + + 1 + Inverted + #1 + + + + + C0OE + ACMPLP0 VCOUT Pin Output Enable + 1 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + COMPSEL0 + Comparator Input Select Register + 0x04 + 8 + read-write + 0x11 + 0xFF + + + IVCMP1 + ACMPLP1 Input (IVCMP1) Selection + 4 + 6 + read-write + + + 00 + No input + #00 + + + 01 + CMPIN1 input selected + #01 + + + 10 + AMP1O output selected + #10 + + + + + IVCMP0 + ACMPLP0 Input (IVCMP0) Selection + 0 + 2 + read-write + + + 00 + No input + #00 + + + 01 + CMPIN0 input selected + #01 + + + 10 + AMP0O output selected + #10 + + + + + + + COMPSEL1 + Comparator Reference voltage Select Register + 0x05 + 8 + read-write + 0x91 + 0xFF + + + C1VRF2 + ACMPLP1 Reference Voltage Selection + 7 + 7 + read-write + + + 0 + IVREF0 selected + #0 + + + 1 + IVREF1 selected + #1 + + + + + IVREF1 + ACMPLP1 Reference Voltage(IVREF1) Selection + 4 + 6 + read-write + + + 00 + No reference voltage + #00 + + + 01 + CMPREF1 selected + #01 + + + 10 + DA8_1 output selected + #10 + + + + + IVREF0 + ACMPLP0 Reference Voltage (IVREF0) Selection + 0 + 2 + read-write + + + 00 + No reference voltage + #00 + + + 01 + CMPREF0 selected + #01 + + + 10 + DA8_0 output selected + #10 + + + + + + + + + R_ADC0 + A/D Converter + 0x4005C000 + + 0x00000000 + 0x02 + registers + + + 0x00000004 + 0x009 + registers + + + 0x0000000E + 0x04A + registers + + + 0x00000066 + 0x02 + registers + + + 0x0000007A + 0x01 + registers + + + 0x0000007C + 0x002 + registers + + + 0x00000080 + 0x02 + registers + + + 0x00000084 + 0x004 + registers + + + 0x0000008A + 0x01 + registers + + + 0x0000008C + 0x01 + registers + + + 0x00000090 + 0x015 + registers + + + 0x000000A6 + 0x01 + registers + + + 0x000000A8 + 0x005 + registers + + + 0x000000DD + 0x016 + registers + + + 0x000000F4 + 0x01 + registers + + + 0x000000F8 + 0x003 + registers + + + 0x000001A0 + 0x004 + registers + + + 0x000001B0 + 0x02 + registers + + + + ADCSR + A/D Control Register + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + ADST + A/D Conversion Start + 15 + 15 + read-write + modify + + + 0 + Stops A/D conversion process. + #0 + + + 1 + Starts A/D conversion process. + #1 + + + + + ADCS + Scan Mode Select + 13 + 14 + read-write + + + 00 + Single scan mode + #00 + + + 01 + Group scan mode + #01 + + + 10 + Continuous scan mode + #10 + + + 11 + Setting prohibited + #11 + + + + + ADHSC + A/D Conversion Operation Mode Select + 10 + 10 + read-write + + + 0 + High speed A/D conversion mode + #0 + + + 1 + Low current A/D conversion mode + #1 + + + + + TRGE + Trigger Start Enable + 9 + 9 + read-write + + + 0 + Disables A/D conversion to be started by the synchronous or asynchronous trigger. + #0 + + + 1 + Enables A/D conversion to be started by the synchronous or asynchronous trigger. + #1 + + + + + EXTRG + Trigger Select + 8 + 8 + read-write + + + 0 + A/D conversion is started by the synchronous trigger (ELC). + #0 + + + 1 + A/D conversion is started by the asynchronous trigger (ADTRG0#). + #1 + + + + + DBLE + Double Trigger Mode Select + 7 + 7 + read-write + + + 0 + Double trigger mode non-selection + #0 + + + 1 + Double trigger mode selection + #1 + + + + + GBADIE + Group B Scan End Interrupt Enable + 6 + 6 + read-write + + + 0 + Disables S12GBADI0 interrupt generation upon group B scan completion. + #0 + + + 1 + Enables S12GBADI0 interrupt generation upon group B scan completion. + #1 + + + + + DBLANS + Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. + 0 + 4 + read-write + + + + + 2 + 0x2 + ADANSA[%s] + A/D Channel Select Register + 0x004 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + ANSA%s + AN Input Select + 0 + 0 + read-write + + + 0 + AN Input is not subjected to conversion. + #0 + + + 1 + AN Input is subjected to conversion. + #1 + + + + + + + 2 + 0x2 + ADADS[%s] + A/D-Converted Value Addition/Average Channel Select Register + 0x008 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + ADS%s + A/D-Converted Value Addition/Average Channel Select + 0 + 0 + read-write + + + 0 + AN Input is not selected. + #0 + + + 1 + AN Input is selected. + #1 + + + + + + + ADADC + A/D-Converted Value Addition/Average Count Select Register + 0x00C + 8 + read-write + 0x00 + 0xFF + + + ADC + Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) + 0 + 2 + read-write + + + 000 + 1-time conversion (no addition; same as normal conversion) + #000 + + + 001 + 2-time conversion (addition once) + #001 + + + 010 + 3-time conversion (addition twice) + #010 + + + 011 + 4-time conversion (addition three times) + #011 + + + 101 + 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. + #101 + + + others + Setting prohibited + true + + + + + AVEE + Average Mode Enable. NOTE:When average mode is deselected by setting the ADADC.AVEE bit to 0, set the addition count to 1, 2, 3, 4 or 16-time conversion. 16-time conversion can only be used with 12-bit accuracy selected. NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) + 7 + 7 + read-write + + + 0 + Disable average mode + #0 + + + 1 + Enable average mode + #1 + + + + + + + ADCER + A/D Control Extended Register + 0x00E + 16 + read-write + 0x0000 + 0xFFFF + + + ADRFMT + A/D Data Register Format Select + 15 + 15 + read-write + + + 0 + Flush-right is selected for the A/D data register format. + #0 + + + 1 + Flush-left is selected for the A/D data register format. + #1 + + + + + ADINV + Single-Ended Input A/D Converted Data Inversion Select + 14 + 14 + read-write + + + 0 + Data is stored in a range of -32768 to 0. + #0 + + + 1 + Data is stored in a range of 0 to 32767. + #1 + + + + + DIAGM + Self-Diagnosis Enable + 11 + 11 + read-write + + + 0 + Disables self-diagnosis of A/D converter. + #0 + + + 1 + Enables self-diagnosis of A/D converter. + #1 + + + + + DIAGLD + Self-Diagnosis Mode Select + 10 + 10 + read-write + + + 0 + Rotation mode for self-diagnosis voltage + #0 + + + 1 + Fixed mode for self-diagnosis voltage + #1 + + + + + DIAGVAL + Self-Diagnosis Conversion Voltage Select + 8 + 9 + read-write + + + 00 + When the self-diagnosis fixation mode is selected, it set prohibits it. + #00 + + + 01 + The self-diagnosis by using the voltage of 0V. + #01 + + + 10 + The self-diagnosis by using the voltage of reference supply x 1/2. + #10 + + + 11 + The self-diagnosis by using the voltage of the reference supply. + #11 + + + + + ACE + A/D Data Register Automatic Clearing Enable + 5 + 5 + read-write + + + 0 + Disables automatic clearing. + #0 + + + 1 + Enables automatic clearing. + #1 + + + + + ADPRC + A/D Conversion Accuracy Specify + 1 + 2 + read-write + + + 00 + A/D conversion is performed with 12-bit accuracy. + #00 + + + 01 + A/D conversion is performed with 10-bit accuracy. + #01 + + + 10 + A/D conversion is performed with 8-bit accuracy. + #10 + + + 11 + A/D conversion is performed with 14-bit accuracy. + #11 + + + + + + + ADSTRGR + A/D Conversion Start Trigger Select Register + 0x010 + 16 + read-write + 0x0000 + 0xFFFF + + + TRSA + A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. + 8 + 13 + read-write + + + TRSB + A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. + 0 + 5 + read-write + + + + + ADEXICR + A/D Conversion Extended Input Control Register + 0x012 + 16 + read-write + 0x0000 + 0xFFFF + + + OCSB + Internal Reference Voltage A/D Conversion Select for Group B in group scan mode. + 11 + 11 + read-write + + + 0 + The internal reference voltage is not selected for group B in group scan mode. + #0 + + + 1 + The internal reference voltage is selected for group B in group scan mode. + #1 + + + + + TSSB + Temperature Sensor Output A/D Conversion Select for Group B in group scan mode. + 10 + 10 + read-write + + + 0 + The temperature sensor output is not selected for group B in group scan mode. + #0 + + + 1 + The temperature sensor output is selected for group B in group scan mode. + #1 + + + + + OCSA + Internal Reference Voltage A/D Conversion Select + 9 + 9 + read-write + + + 0 + The internal reference voltage is not selected. + #0 + + + 1 + The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. + #1 + + + + + TSSA + Temperature Sensor Output A/D Conversion Select + 8 + 8 + read-write + + + 0 + The temperature sensor output is not selected. + #0 + + + 1 + The temperature sensor output is selected. + #1 + + + + + OCSAD + Internal Reference Voltage A/D converted Value Addition/Average Mode Select + 1 + 1 + read-write + + + 0 + Internal reference voltage A/D-converted value addition/average mode is not selected. + #0 + + + 1 + Internal reference voltage A/D-converted value addition/average mode is selected. + #1 + + + + + TSSAD + Temperature Sensor Output A/D converted Value Addition/Average Mode Select + 0 + 0 + read-write + + + 0 + Temperature sensor output A/D-converted value addition/average mode is not selected. + #0 + + + 1 + Temperature sensor output A/D-converted value addition/average mode is selected. + #1 + + + + + + + 2 + 2 + ADANSB[%s] + A/D Channel Select Register B + 0x014 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + ANSB%s + AN Input Select + 0 + 0 + read-write + + + 0 + Input is not subjected to conversion. + #0 + + + 1 + Input is subjected to conversion. + #1 + + + + + + + ADDBLDR + A/D Data Duplication Register + 0x018 + 16 + read-only + 0x0000 + 0xFFFF + + + ADDBLDR + This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. + 0 + 15 + read-only + + + + + ADTSDR + A/D Temperature Sensor Data Register + 0x01A + 16 + read-only + 0x0000 + 0xFFFF + + + ADTSDR + This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. + 0 + 15 + read-only + + + + + ADOCDR + A/D Internal Reference Voltage Data Register + 0x01C + 16 + read-only + 0x0000 + 0xFFFF + + + ADOCDR + This is a 16-bit read-only register for storing the A/D result of internal reference voltage. + 0 + 15 + read-only + + + + + ADRD_RIGHT + A/D Self-Diagnosis Data Register Right Justified + 0x01E + 16 + read-only + 0x0000 + 0xFFFF + + + DIAGST + Self-Diagnosis Status + 14 + 15 + read-only + + + 00 + Self-diagnosis has never been executed since power-on. + #00 + + + 01 + Self-diagnosis using the voltage of 0 V has been executed. + #01 + + + 10 + Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. + #10 + + + 11 + Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. + #11 + + + + + AD + A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC. + 0 + 13 + read-only + + + + + ADRD_LEFT + A/D Self-Diagnosis Data Register Left Justified + ADRD_RIGHT + 0x01E + 16 + read-only + 0x0000 + 0xFFFF + + + AD + A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC. + 2 + 15 + read-only + + + DIAGST + Self-Diagnosis Status + 0 + 1 + read-only + + + 00 + Self-diagnosis has never been executed since power-on. + #00 + + + 01 + Self-diagnosis using the voltage of 0 V has been executed. + #01 + + + 10 + Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. + #10 + + + 11 + Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. + #11 + + + + + + + 28 + 0x2 + ADDR[%s] + A/D Data Register + 0x020 + 16 + read-only + 0x0000 + 0xFFFF + + + ADDR + The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. + 0 + 15 + read-only + + + + + ADSHCR + A/D Sample and Hold Circuit Control Register + 0x066 + 16 + read-write + 0x0018 + 0xFFFF + + + SHANS2 + AN002 sample-and-hold circuit Select + 10 + 10 + read-write + + + 0 + Bypass the sample-and-hold circuit. + #0 + + + 1 + Use the sample-and-hold circuit. + #1 + + + + + SHANS1 + AN001 sample-and-hold circuit Select + 9 + 9 + read-write + + + 0 + Bypass the sample-and-hold circuit. + #0 + + + 1 + Use the sample-and-hold circuit. + #1 + + + + + SHANS0 + AN000 sample-and-hold circuit Select + 8 + 8 + read-write + + + 0 + Bypass the sample-and-hold circuit. + #0 + + + 1 + Use the sample-and-hold circuit. + #1 + + + + + SSTSH + Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting Set the sampling time (4 to 255 states) + 0 + 7 + read-write + + + 0x04 + 0xFF + + + + + + + ADDISCR + A/D Disconnection Detection Control Register + 0x07A + 8 + read-write + 0x00 + 0xFF + + + CHARGE + Selection of Precharge or Discharge + 4 + 4 + read-write + + + 0 + Discharge + #0 + + + 1 + Precharge + #1 + + + + + ADNDIS + The charging time + 0 + 3 + read-write + + + 0000 + Disconnection detection is disabled + #0000 + + + 0001 + Setting prohibited + #0001 + + + others + ( 1 / ADCLK ) x ADNDIS + true + + + + + + + ADSHMSR + A/D Sample and Hold Operation Mode Select Register + 0x07C + 8 + read-write + 0x00 + 0xFF + + + SHMD + Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select + 0 + 0 + read-write + + + 0 + Sampling by channel-dedicated sample-and-hold circuit is disable. + #0 + + + 1 + Sampling by channel-dedicated sample-and-hold circuit is enable. + #1 + + + + + + + ADGSPCR + A/D Group Scan Priority Control Register + 0x080 + 16 + read-write + 0x0000 + 0xFFFF + + + GBRP + Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. + 15 + 15 + read-write + + + 0 + Single scan for group B is not continuously activated. + #0 + + + 1 + Single scan for group B is continuously activated. + #1 + + + + + GBRSCN + Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) + 1 + 1 + read-write + + + 0 + Scanning for group B is not restarted after having been discontinued due to group A priority control. + #0 + + + 1 + Scanning for group B is restarted after having been discontinued due to group A priority control. + #1 + + + + + PGS + Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. + 0 + 0 + read-write + + + 0 + Operation is without group A priority control + #0 + + + 1 + Operation is with group A priority control + #1 + + + + + + + ADICR + A/D Interrupt Control Register + 0x7D + 8 + read-write + 0x00 + 0xFF + + + ADIC + A/D Interrupt Control + 0 + 1 + read-write + + + 00 + ADC_ADI is generated at end of A/D Scan + #00 + + + 11 + ADC_ADI is generated at end of calibration + #11 + + + + + + + ADDBLDRA + A/D Data Duplexing Register A + 0x084 + 16 + read-only + 0x0000 + 0xFFFF + + + ADDBLDRA + This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. + 0 + 15 + read-only + + + + + ADDBLDRB + A/D Data Duplexing Register B + 0x086 + 16 + read-only + 0x0000 + 0xFFFF + + + ADDBLDRB + This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. + 0 + 15 + read-only + + + + + ADHVREFCNT + A/D High-Potential/Low-Potential Reference Voltage Control Register + 0x08A + 8 + read-write + 0x00 + 0xFF + + + ADSLP + Sleep + 7 + 7 + read-write + + + 0 + Normal operation + #0 + + + 1 + Standby state. + #1 + + + + + LVSEL + Low-Potential Reference Voltage Select + 4 + 4 + read-write + + + 0 + AVSS0 is selected as the low-potential reference voltage + #0 + + + 1 + VREFL0 is selected as the low-potential reference voltage. + #1 + + + + + HVSEL + High-Potential Reference Voltage Select + 0 + 1 + read-write + + + 00 + AVCC0 is selected as the high-potential reference voltage + #00 + + + 01 + VREFH0 is selected as the high-potential reference voltage + #01 + + + 10 + Internal reference voltage is selected as the high-potential reference voltage + #10 + + + 11 + Internal node discharge. No reference voltage pin is selected. + #11 + + + + + + + ADWINMON + A/D Compare Function Window A/B Status Monitor Register + 0x08C + 8 + read-only + 0x00 + 0xFF + + + MONCMPB + Comparison Result Monitor B + 5 + 5 + read-only + + + 0 + Window B comparison conditions are not met. + #0 + + + 1 + Window B comparison conditions are met. + #1 + + + + + MONCMPA + Comparison Result Monitor A + 4 + 4 + read-only + + + 0 + Window A comparison conditions are not met. + #0 + + + 1 + Window A comparison conditions are met. + #1 + + + + + MONCOMB + Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. + 0 + 0 + read-only + + + 0 + Window A / window B composite conditions are not met. + #0 + + + 1 + Window A / window B composite conditions are met. + #1 + + + + + + + ADCMPCR + A/D Compare Function Control Register + 0x090 + 16 + read-write + 0x0000 + 0xFFFF + + + CMPAIE + Compare A Interrupt Enable + 15 + 15 + read-write + + + 0 + ADC_CMPAI interrupt is disabled when comparison conditions (window A) are met. + #0 + + + 1 + ADC_CMPAI interrupt is enabled when comparison conditions (window A) are met. + #1 + + + + + WCMPE + Window Function Setting + 14 + 14 + read-write + + + 0 + Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. + #0 + + + 1 + Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. + #1 + + + + + CMPBIE + Compare B Interrupt Enable + 13 + 13 + read-write + + + 0 + ADC_CMPAI interrupt is disabled when comparison conditions (window B) are met. + #0 + + + 1 + ADC_CMPAI interrupt is enabled when comparison conditions (window B) are met. + #1 + + + + + CMPAE + Compare Window A Operation Enable + 11 + 11 + read-write + + + 0 + Compare window A operation is disabled. ADC_WCMPM and ADC_WCMPUM outputs are disabled. + #0 + + + 1 + Compare window A operation is enabled. + #1 + + + + + CMPBE + Compare Window B Operation Enable + 9 + 9 + read-write + + + 0 + Compare window B operation is disabled. ADC_WCMPM and ADC_WCMPUM outputs are disabled. + #0 + + + 1 + Compare window B operation is enabled. + #1 + + + + + CMPAB + Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). + 0 + 1 + read-write + + + 00 + ADC_WCMPM is output when window A comparison conditions are met OR window B comparison conditions are met. ADC_WCMPUM is output in other cases. + #00 + + + 01 + ADC_WCMPM is output when window A comparison conditions are met EXOR window B comparison conditions are met. ADC_WCMPUM is output in other cases. + #01 + + + 10 + ADC140_WCMPM is output when window A comparison conditions are met and window B comparison conditions are met. ADC140_WCMPUM is output in other cases. + #10 + + + 11 + Setting prohibited. + #11 + + + + + + + ADCMPANSER + A/D Compare Function Window A Extended Input Select Register + 0x092 + 8 + read-write + 0x00 + 0xFF + + + CMPOCA + Internal reference voltage Compare selection bit. + 1 + 1 + read-write + + + 0 + Excludes the internal reference voltage from the compare window A target range. + #0 + + + 1 + Includes the internal reference voltage in the compare window A target range. + #1 + + + + + CMPTSA + Temperature sensor output Compare selection bit. + 0 + 0 + read-write + + + 0 + Excludes the temperature sensor output from the compare window A target range. + #0 + + + 1 + Includes the temperature sensor output in the compare window A target range. + #1 + + + + + + + ADCMPLER + A/D Compare Function Window A Extended Input Comparison Condition Setting Register + 0x093 + 8 + read-write + 0x00 + 0xFF + + + CMPLOCA + Compare Window A Internal Reference Voltage ComparisonCondition Select + 1 + 1 + read-write + + + 0 + ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) + #0 + + + 1 + ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) + #1 + + + + + CMPLTSA + Compare Window A Temperature Sensor Output Comparison Condition Select + 0 + 0 + read-write + + + 0 + ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). + #0 + + + 1 + ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). + #1 + + + + + + + 2 + 0x2 + ADCMPANSR[%s] + A/D Compare Function Window A Channel Select Register + 0x094 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + CMPCHA%s + AN Input Select + 0 + 0 + read-write + + + 0 + Excludes Input from the compare window A target range. + #0 + + + 1 + Includes Input from the compare window A target range. + #1 + + + + + + + 2 + 0x2 + ADCMPLR[%s] + A/D Compare Function Window A Comparison Condition Setting Register + 0x098 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + CMPLCHA%s + Comparison condition of input + 0 + 0 + read-write + + + 0 + ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) + #0 + + + 1 + ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). + #1 + + + + + + + ADCMPDR0 + A/D Compare Function Window A Lower-Side Level Setting Register + 0x09C + 16 + read-write + 0x0000 + 0xFFFF + + + ADCMPDR0 + The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. + 0 + 15 + read-write + + + + + ADCMPDR1 + A/D Compare Function Window A Upper-Side Level Setting Register + 0x09E + 16 + read-write + 0x0000 + 0xFFFF + + + ADCMPDR1 + The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. + 0 + 15 + read-write + + + + + 2 + 0x2 + ADCMPSR[%s] + A/D Compare Function Window A Channel Status Register + 0x0A0 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + CMPSTCHA%s + Compare window A flag of input + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Comparison conditions are not met. + #0 + + + 1 + Comparison conditions are met. + #1 + + + + + + + ADCMPSER + A/D Compare Function Window A Extended Input Channel Status Register + 0x0A4 + 8 + read-write + 0x00 + 0xFF + + + CMPSTOCA + Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Comparison conditions are not met. + #0 + + + 1 + Comparison conditions are met. + #1 + + + + + CMPSTTSA + Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Comparison conditions are not met. + #0 + + + 1 + Comparison conditions are met. + #1 + + + + + + + ADCMPBNSR + A/D Compare Function Window B Channel Selection Register + 0x0A6 + 8 + read-write + 0x00 + 0xFF + + + CMPLB + Compare window B Compare condition setting bit. + 7 + 7 + read-write + + + 0 + CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) + #0 + + + 1 + CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) + #1 + + + + + CMPCHB + Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. + 0 + 5 + read-write + + + 0x00 + AN000 + 0x00 + + + 0x01 + AN001 + 0x01 + + + 0x02 + AN002 + 0x02 + + + 0x03 + AN003 + 0x03 + + + 0x04 + AN004 + 0x04 + + + 0x05 + AN005 + 0x05 + + + 0x06 + AN006 + 0x06 + + + 0x07 + AN007 + 0x07 + + + 0x08 + AN008 + 0x08 + + + 0x09 + AN009 + 0x09 + + + 0x0A + AN010 + 0x0A + + + 0x0B + AN011 + 0x0B + + + 0x0C + AN012 + 0x0C + + + 0x0D + AN013 + 0x0D + + + 0x0E + AN014 + 0x0E + + + 0x0F + AN015 + 0x0F + + + 0x10 + AN016 + 0x10 + + + 0x11 + AN017 + 0x11 + + + 0x12 + AN018 + 0x12 + + + 0x13 + AN019 + 0x13 + + + 0x14 + AN020 + 0x14 + + + 0x15 + AN021 + 0x15 + + + 0x16 + AN022 + 0x16 + + + 0x17 + AN023 + 0x17 + + + 0x18 + AN024 + 0x18 + + + 0x19 + AN025 + 0x19 + + + 0x1A + AN026 + 0x1A + + + 0x1B + AN027 + 0x1B + + + 0x20 + Temperature sensor + 0x20 + + + 0x21 + Internal reference voltage + 0x21 + + + 0x3F + No channel is selected + 0x3F + + + others + Setting prohibited + true + + + + + + + ADWINLLB + A/D Compare Function Window B Lower-Side Level Setting Register + 0x0A8 + 16 + read-write + 0x0000 + 0xFFFF + + + ADWINLLB + This register is used to compare A window function is used to set the lower level of the window B. + 0 + 15 + read-write + + + + + ADWINULB + A/D Compare Function Window B Upper-Side Level Setting Register + 0x0AA + 16 + read-write + 0x0000 + 0xFFFF + + + ADWINULB + This register is used to compare A window function is used to set the higher level of the window B. + 0 + 15 + read-write + + + + + ADCMPBSR + A/D Compare Function Window B Status Register + 0x0AC + 8 + read-write + 0x00 + 0xFF + + + CMPSTB + Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN027, temperature sensor, and internal reference voltage) made the object of window B relation condition. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Comparison conditions are not met. + #0 + + + 1 + Comparison conditions are met. + #1 + + + + + + + ADSSTRL + A/D Sampling State Register L + 0x0DD + 8 + read-write + 0x0B + 0xFF + + + SST + Sampling Time Setting (AN016-AN027) + 0 + 7 + read-write + + + 0x05 + 0xFF + + + + + + + ADSSTRT + A/D Sampling State Register T + 0x0DE + 8 + read-write + 0x0B + 0xFF + + + SST + Sampling Time Setting (temperature sensor output) + 0 + 7 + read-write + + + 0x05 + 0xFF + + + + + + + ADSSTRO + A/D Sampling State Register O + 0x0DF + 8 + read-write + 0x0B + 0xFF + + + SST + Sampling Time Setting (Internal reference voltage) + 0 + 7 + read-write + + + 0x05 + 0xFF + + + + + + + 16 + 0x1 + ADSSTR[%s] + A/D Sampling State Registers + 0x0E0 + 8 + read-write + 0x0B + 0xFF + + + SST + Sampling time setting + 0 + 7 + read-write + + + 0x05 + 0xFF + + + + + + + ADPGACR + A/D Programmable Gain Amplifier Control Register + 0x1A0 + 16 + read-write + 0x9999 + 0xFFFF + + + P002GEN + PGA P002 gain setting and enable bit + 11 + 11 + read-write + + + 0 + The gain setting is invalidated (AIN is not input in PGA). + #0 + + + 1 + The gain setting is effectively done (AIN is input in PGA). + #1 + + + + + P002ENAMP + Amplifier enable bit for PGA P002 + 10 + 10 + read-write + + + 0 + The amplifier in PGA is not used. + #0 + + + 1 + The amplifier in PGA is used. + #1 + + + + + P002SEL1 + The amplifier passing is enable for PGA P002 + 9 + 9 + read-write + + + 0 + By way of the amplifier in PGA. + #0 + + + 1 + Note 1 that by way of amplifier in PGA + #1 + + + + + P002SEL0 + A through amplifier is enable for PGA P002 + 8 + 8 + read-write + + + 0 + Not through the PGA in amplifier + #0 + + + 1 + I will through in the PGA amplifier. + #1 + + + + + P001GEN + PGA P001 gain setting and enable bit + 7 + 7 + + + P001ENAMP + Amplifier enable bit for PGA P001 + 6 + 6 + + + P001SEL1 + The amplifier passing is enable for PGA P001 + 5 + 5 + + + P001SEL0 + A through amplifier is enable for PGA P001 + 4 + 4 + + + P000GEN + PGA P000 gain setting and enable bit + 3 + 3 + + + P000ENAMP + Amplifier enable bit for PGA P000 + 2 + 2 + + + P000SEL1 + The amplifier passing is enable for PGA P000 + 1 + 1 + + + P000SEL0 + A through amplifier is enable for PGA P000 + 0 + 0 + + + + + ADRD + A/D Self-Diagnosis Data Register + 0xF8 + 16 + read-write + 0x0000 + 0xFFFF + + + AD + Converted Value 15 to 0 + 0 + 15 + read-only + + + + + ADRST + A/D Self-Diagnostic Status Register + 0xFA + 8 + read-only + + + DIAGST + Self-Diagnosis Status + 0 + 1 + + + 00 + Self-diagnosis has not been executed since power-on + #00 + + + 01 + Self-diagnosis was executed under a condition that the ideal value of the A/D conversion result was 8000h + #01 + + + 10 + Self-diagnosis was executed under a condition that an ideal value of the A/D conversion result was 0000h + #10 + + + 11 + Self-diagnosis was executed under a condition than an ideal value of the A/D conversion result is 7FFFh + #11 + + + + + + + VREFAMPCNT + A/D Dedicated Reference Voltage Circuit Control Register + 0xF4 + 8 + read-write + + + VREFADCG + VREFADC Output Voltage Control + 1 + 2 + + + 0x + 1.5 V + #00 + + + 10 + 2.0 V + #10 + + + 11 + 2.5 V + #11 + + + + + VREFADCEN + VREFADCG Enable + 3 + 3 + read-write + + + 0 + Disable the VREFADC output + #0 + + + 1 + Enable the VREFADC output + #1 + + + + + ADSLP + Sleep + 7 + 7 + read-write + + + 0 + Normal operation + #0 + + + 1 + Standby + #1 + + + + + OLDETEN + OLDET Enable + 0 + 0 + read-write + + + 0 + Disable the over current detection. + #0 + + + 1 + Enable the over current detection. + true + + + + + BGREN + BGR Enable + 4 + 4 + read-write + + + 0 + Turn off power of BGR + #0 + + + 1 + Turn on power of BGR + true + + + + + + + ADCALEXE + A/D Calibration Execution Register + 0xF2 + 8 + read-write + 0x00 + 0xFF + + + CALEXE + Calibration Start + 7 + 7 + read-write + + + 0 + Calibration does not start + #0 + + + 1 + Calibration starts + #1 + + + + + CALMON + Calibration Status Flag + 6 + 6 + read-only + + + 0 + Calibration not in progress + #0 + + + 1 + Calibration in progress + #1 + + + + + + + ADANIM + A/D Channel Input Mode Select Register + 0xF0 + 16 + read-write + 0x0000 + 0xFFFF + + + 4 + 1 + ANIM%s + Analog Channel Input Mode Select + 0 + 0 + read-write + + + 0 + Single-end mode + #0 + + + 1 + Differential mode + #1 + + + + + + + ADPGAGS0 + A/D Programmable Gain Amplifier Gain Setting Register 0 + 0x1A2 + 16 + read-write + 0x0000 + 0xFFFF + + + P002GAIN + PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0. + 8 + 11 + read-write + + + 0000 + x 2.000 (ADPGADDCR0.P002DEN=0) + #0000 + + + 0001 + x 2.500 (ADPGADDCR0.P002DEN=0) / x 1.500 (ADPGADDCR0.P002DEN=1) + #0001 + + + 0010 + x 2.667 (ADPGADDCR0.P002DEN=0) + #0010 + + + 0011 + x 2.857 (ADPGADDCR0.P002DEN=0) + #0011 + + + 0100 + x 3.077 (ADPGADDCR0.P002DEN=0) + #0100 + + + 0101 + x 3.333 (ADPGADDCR0.P002DEN=0) / x 2.333 (ADPGADDCR0.P002DEN=1) + #0101 + + + 0110 + x 3.636 (ADPGADDCR0.P002DEN=0) + #0110 + + + 0111 + x 4.000 (ADPGADDCR0.P002DEN=0) + #0111 + + + 1000 + x 4.444 (ADPGADDCR0.P002DEN=0) + #1000 + + + 1001 + x 5.000 (ADPGADDCR0.P002DEN=0) / x 4.00 (ADPGADDCR0.P002DEN=1) + #1001 + + + 1010 + x 5.714 (ADPGADDCR0.P002DEN=0) + #1010 + + + 1011 + x 6.667 (ADPGADDCR0.P002DEN=0) / x 5.667 (ADPGADDCR0.P002DEN=1) + #1011 + + + 1100 + x 8.000 (ADPGADDCR0.P002DEN=0) + #1100 + + + 1101 + x 10.000 (ADPGADDCR0.P002DEN=0) + #1101 + + + 1110 + x 13.333 (ADPGADDCR0.P002DEN=0) + #1110 + + + 1111 + x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0) + #1111 + + + + + P001GAIN + PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0. + 4 + 7 + + + P000GAIN + PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0. + 0 + 3 + + + + + ADPGADCR0 + A/D Programmable Gain Amplifier Differential Input Control Register + 0x1B0 + 16 + read-write + 0x0000 + 0xFFFF + + + P003DG + P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. + 12 + 13 + read-write + + + 00 + x 1.5 + #00 + + + 01 + x 2.333 + #01 + + + 10 + x 4.0 + #10 + + + 11 + x 5.667 + #11 + + + + + P002DEN + P002 Differential Input Enable + 11 + 11 + read-write + + + 0 + Differential input is disabled. + #0 + + + 1 + Differential input is enabled. + #1 + + + + + P002DG + P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. + 8 + 9 + read-write + + + 00 + x 1.5 + #00 + + + 01 + x 2.333 + #01 + + + 10 + x 4.0 + #10 + + + 11 + x 5.667 + #11 + + + + + P001DEN + P001 Differential Input Enable + 7 + 7 + read-write + + + 0 + Differential input is disabled. + #0 + + + 1 + Differential input is enabled. + #1 + + + + + P001DG + P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b. + 4 + 5 + read-write + + + 00 + x 1.5 + #00 + + + 01 + x 2.333 + #01 + + + 10 + x 4.0 + #10 + + + 11 + x 5.667 + #11 + + + + + P000DEN + P000 Differential Input Enable + 3 + 3 + read-write + + + 0 + Differential input is disabled. + #0 + + + 1 + Differential input is enabled. + #1 + + + + + P000DG + P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b. + 0 + 1 + read-write + + + 00 + x 1.5 + #00 + + + 01 + x 2.333 + #01 + + + 10 + x 4.0 + #10 + + + 11 + x 5.667 + #11 + + + + + + + + + R_ADC1 + 0x4005C200 + + + R_AGT0 + Asynchronous General Purpose Timer + 0x40084000 + + 0x00000000 + 0x006 + registers + + + 0x00000008 + 0x003 + registers + + + 0x0000000C + 0x004 + registers + + + + AGT + AGT Counter Register + 0x00 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGT + 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. + 0 + 15 + read-write + + + + + AGTCMA + AGT Compare Match A Register + 0x02 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGTCMA + AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH + 0 + 15 + read-write + + + + + AGTCMB + AGT Compare Match B Register + 0x04 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGTCMB + AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH + 0 + 15 + read-write + + + + + AGTCR + AGT Control Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + TCMBF + Compare match B flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TCMAF + Compare match A flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TUNDF + Underflow flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TEDGF + Active edge judgment flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No active edge received + #0 + + + 1 + Active edge received. + #1 + + + + + TSTOP + AGT count forced stop + 2 + 2 + write-only + + + 0 + Writing is invalid + #0 + + + 1 + The count is forcibly stopped. + #1 + + + + + TCSTF + AGT count status flag + 1 + 1 + read-only + + + 0 + Count stops + #0 + + + 1 + Count in progress. + #1 + + + + + TSTART + AGT count start + 0 + 0 + read-write + + + 0 + Count stops + #0 + + + 1 + Count starts. + #1 + + + + + + + AGTMR1 + AGT Mode Register 1 + 0x09 + 8 + read-write + 0x00 + 0xFF + + + TCK + Count source + 4 + 6 + read-write + + + 000 + PCLKB + #000 + + + 001 + PCLKB/8 + #001 + + + 011 + PCLKB/2 + #011 + + + 100 + Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register + #100 + + + 101 + Underflow event signal from AGT0*6 + #101 + + + 110 + Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. + #110 + + + others + settings are prohibited. + true + + + + + TEDGPL + Edge polarity + 3 + 3 + read-write + + + 0 + Single-edge + #0 + + + 1 + Both-edge. + #1 + + + + + TMOD + Operating mode + 0 + 2 + read-write + + + 000 + Timer mode + #000 + + + 001 + Pulse output mode + #001 + + + 010 + Event counter mode + #010 + + + 011 + Pulse width measurement mode + #011 + + + 100 + Pulse period measurement mode. + #100 + + + others + settings are prohibited + true + + + + + + + AGTMR2 + AGT Mode Register 2 + 0x0A + 8 + read-write + 0x00 + 0xFF + + + LPM + Low Power Mode + 7 + 7 + read-write + + + 0 + Normal mode + #0 + + + 1 + Low Power mode + #1 + + + + + CKS + AGTLCLK/AGTSCLK count source clock frequency division ratio + 0 + 2 + read-write + + + 000 + 1/1 + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + 110 + 1/64 + #110 + + + 111 + 1/128. + #111 + + + + + + + AGTIOC + AGT I/O Control Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + TIOGT + Count control + 6 + 7 + read-write + + + 00 + Event is always counted + #00 + + + 01 + Event is counted during polarity period specified for AGTEEn. + #01 + + + others + settings are prohibited. + true + + + + + TIPF + Input filter + 4 + 5 + read-write + + + 00 + No filter + #00 + + + 01 + Filter sampled at PCLKB + #01 + + + 10 + Filter sampled at PCLKB/8 + #10 + + + 11 + Filter sampled at PCLKB/32 + #11 + + + + + TOE + AGTOn output enable + 2 + 2 + read-write + + + 0 + AGTOn output disabled + #0 + + + 1 + AGTOn output enabled. + #1 + + + + + TEDGSEL + I/O polarity switchFunction varies depending on the operating mode. + 0 + 0 + read-write + + + + + AGTISR + AGT Event Pin Select Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + EEPS + AGTEE polarty selection + 2 + 2 + read-write + + + 0 + An event is counted during the low-level period + #0 + + + 1 + An event is counted during the high-level period + #1 + + + + + + + AGTCMSR + AGT Compare Match Function Select Register + 0x0E + 8 + read-write + 0x00 + 0xFF + + + TOPOLB + AGTOB polarity select + 6 + 6 + read-write + + + 0 + AGTOB Output is started at low + #0 + + + 1 + AGTOB Output is started at high + #1 + + + + + TOEB + AGTOB output enable + 5 + 5 + read-write + + + 0 + AGTOB output disabled (port) + #0 + + + 1 + AGTOB output enabled + #1 + + + + + TCMEB + Compare match B register enable + 4 + 4 + read-write + + + 0 + Disable compare match B register + #0 + + + 1 + Enable compare match B register + #1 + + + + + TOPOLA + AGTOA polarity select + 2 + 2 + read-write + + + 0 + AGTOA Output is started at low + #0 + + + 1 + AGTOA Output is started at high + #1 + + + + + TOEA + AGTOA output enable + 1 + 1 + read-write + + + 0 + AGTOA output disabled (port) + #0 + + + 1 + AGTOA output enabled + #1 + + + + + TCMEA + Compare match A register enable + 0 + 0 + read-write + + + 0 + Disable compare match A register + #0 + + + 1 + Enable compare match A register + #1 + + + + + + + AGTIOSEL + AGT Pin Select Register + 0x0F + 8 + read-write + 0x00 + 0xFF + + + TIES + AGTIO input enable + 4 + 4 + read-write + + + 0 + External event input is disabled during Software Standby mode + #0 + + + 1 + External event input is enabled during Software Standby mode. + #1 + + + + + + + + + R_AGT1 + 0x40084100 + + + R_BUS + Bus Interface + 0x40003000 + + 0x00000002 + 0x00A + registers + + + 0x00000012 + 0x00A + registers + + + 0x00000022 + 0x00A + registers + + + 0x00000032 + 0x00A + registers + + + 0x00000042 + 0x00A + registers + + + 0x00000052 + 0x00A + registers + + + 0x00000062 + 0x00A + registers + + + 0x00000072 + 0x00A + registers + + + 0x00000802 + 0x02 + registers + + + 0x0000080A + 0x02 + registers + + + 0x00000812 + 0x02 + registers + + + 0x0000081A + 0x02 + registers + + + 0x00000822 + 0x02 + registers + + + 0x0000082A + 0x02 + registers + + + 0x00000832 + 0x02 + registers + + + 0x0000083A + 0x02 + registers + + + 0x00000842 + 0x02 + registers + + + 0x0000084A + 0x02 + registers + + + 0x00000852 + 0x02 + registers + + + 0x0000085A + 0x02 + registers + + + 0x00000862 + 0x02 + registers + + + 0x0000086A + 0x02 + registers + + + 0x00000872 + 0x02 + registers + + + 0x0000087A + 0x02 + registers + + + 0x00000880 + 0x02 + registers + + + 0x00000C00 + 0x003 + registers + + + 0x00000C10 + 0x01 + registers + + + 0x00000C14 + 0x003 + registers + + + 0x00000C20 + 0x01 + registers + + + 0x00000C24 + 0x02 + registers + + + 0x00000C40 + 0x01 + registers + + + 0x00000C44 + 0x006 + registers + + + 0x00000C50 + 0x01 + registers + + + 0x00001000 + 0x02 + registers + + + 0x00001004 + 0x02 + registers + + + 0x00001008 + 0x02 + registers + + + 0x0000100C + 0x02 + registers + + + 0x00001010 + 0x02 + registers + + + 0x00001014 + 0x02 + registers + + + 0x00001100 + 0x02 + registers + + + 0x00001104 + 0x02 + registers + + + 0x00001108 + 0x02 + registers + + + 0x0000110C + 0x02 + registers + + + 0x00001110 + 0x02 + registers + + + 0x00001114 + 0x02 + registers + + + 0x00001118 + 0x02 + registers + + + 0x0000111C + 0x02 + registers + + + 0x00001120 + 0x02 + registers + + + 0x00001124 + 0x02 + registers + + + 0x00001128 + 0x02 + registers + + + 0x0000112C + 0x02 + registers + + + 0x00001130 + 0x02 + registers + + + 0x00001134 + 0x02 + registers + + + 0x00001138 + 0x02 + registers + + + 0x0000113C + 0x02 + registers + + + 0x00001800 + 0x005 + registers + + + 0x00001810 + 0x005 + registers + + + 0x00001820 + 0x005 + registers + + + 0x00001830 + 0x005 + registers + + + 0x00001840 + 0x005 + registers + + + 0x00001850 + 0x005 + registers + + + 0x00001860 + 0x005 + registers + + + 0x00001870 + 0x005 + registers + + + 0x00001880 + 0x005 + registers + + + 0x00001890 + 0x005 + registers + + + 0x000018A0 + 0x005 + registers + + + + 8 + 0x10 + CSa[%s] + CS Registers + 0x0000 + + MOD + Mode Register + 0x0002 + 16 + read-write + 0x0000 + 0xFFFF + + + PRMOD + Page Read Access Mode Select + 15 + 15 + read-write + + + 0 + Normal access compatible mode + #0 + + + 1 + External data read continuous assertion mode + #1 + + + + + PWENB + Page Write Access Enable + 9 + 9 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + PRENB + Page Read Access Enable + 8 + 8 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + EWENB + External Wait Enable + 3 + 3 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + WRMOD + Write Access Mode Select + 0 + 0 + read-write + + + 0 + Byte strobe mode + #0 + + + 1 + Single write strobe mode + #1 + + + + + + + WCR1 + Wait Control Register 1 + 0x0004 + 32 + read-write + 0x07070707 + 0xFFFFFFFF + + + CSRWAIT + Normal Read Cycle Wait Select + 24 + 28 + read-write + + + 0x00 + No wait is inserted. + 0x00 + + + others + Wait with a length of CSRWAIT clock cycle is inserted. + true + + + + + CSWWAIT + Normal Write Cycle Wait Select + 16 + 20 + read-write + + + 0x00 + No wait is inserted. + 0x00 + + + others + Wait with a length of CSWWAIT clock cycle is inserted. + true + + + + + CSPRWAIT + Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. + 8 + 10 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSPRWAIT clock cycle is inserted. + true + + + + + CSPWWAIT + Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. + 0 + 2 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSPWWAIT clock cycle is inserted. + true + + + + + + + WCR2 + Wait Control Register 2 + 0x0008 + 32 + read-write + 0x00000007 + 0xFFFFFFFF + + + CSON + CS Assert Wait Select + 28 + 30 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSON clock cycle is inserted. + true + + + + + WDON + Write Data Output Wait Select + 24 + 26 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of WDON clock cycle is inserted. + true + + + + + WRON + WR Assert Wait Select + 20 + 22 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of WRON clock cycle is inserted. + true + + + + + RDON + RD Assert Wait Select + 16 + 18 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of RDON clock cycle is inserted. + true + + + + + AWAIT + CS Assert Wait Select + 12 + 13 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of AWAIT clock cycle is inserted. + true + + + + + WDOFF + Write Data Output Extension Cycle Select + 8 + 10 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of WDOFF clock cycle is inserted. + true + + + + + CSWOFF + Write-Access CS Extension Cycle Select + 4 + 6 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSWOFF clock cycle is inserted. + true + + + + + CSROFF + Read-Access CS Extension Cycle Select + 0 + 2 + read-write + + + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSROFF clock cycle is inserted. + true + + + + + + + + 8 + 0x10 + CSb[%s] + CS Registers + 0x0800 + + CR + Control Register + 0x002 + 16 + read-write + 0x0000 + 0xFFFF + + + MPXEN + Address/Data Multiplexed I/O Interface Select + 12 + 12 + read-write + + + 0 + Separate bus interface is selected for area n + #0 + + + 1 + Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) + #1 + + + + + EMODE + Endian Mode + 8 + 8 + read-write + + + 0 + Little Endian + #0 + + + 1 + Big Endian + #1 + + + + + BSIZE + External Bus Width Select + 4 + 5 + read-write + + + 00 + A 16-bit bus space + #00 + + + 01 + Setting prohibited + #01 + + + 10 + An 8-bit bus space + #10 + + + 11 + Setting prohibited + #11 + + + + + EXENB + Operation Enable + 0 + 0 + read-write + + + 0 + Disable operation + #0 + + + 1 + Enable operation + #1 + + + + + + + REC + Recovery Cycle Register + 0x00A + 16 + read-write + 0x0000 + 0xFFFF + + + WRCV + Write Recovery + 8 + 11 + read-write + + + 0x0 + No recovery cycle is inserted. + 0x0 + + + others + WRCV recovery cycle is inserted. + true + + + + + RRCV + Read Recovery + 0 + 3 + read-write + + + 0x0 + No recovery cycle is inserted. + 0x0 + + + others + RRCV recovery cycle is inserted. + true + + + + + + + + SDRAM + SDRAM Registers + 0x0C00 + + SDCCR + SDC Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + BSIZE + SDRAM Bus Width Select + 4 + 5 + read-write + + + 00 + A 16-bit bus space + #00 + + + 01 + Setting prohibited + #01 + + + 10 + An 8-bit bus space + #10 + + + 11 + Setting prohibited + #11 + + + + + EXENB + Operation Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + SDCMOD + SDC Mode Register + 0x01 + 8 + read-write + 0x00 + 0xFF + + + EMODE + Endian Mode + 0 + 0 + read-write + + + 0 + Endian order of SDRAM address space is the same as the endian order of the operating mode + #0 + + + 1 + Endian order of SDRAM address space is not the endian order of the operating mode. + #1 + + + + + + + SDAMOD + SDRAM Access Mode Register + 0x02 + 8 + read-write + 0x00 + 0xFF + + + BE + Continuous Access Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable. + #1 + + + + + + + SDSELF + SDRAM Self-Refresh Control Register + 0x10 + 8 + read-write + 0x00 + 0xFF + + + SFEN + SDRAM Self-Refresh Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + SDRFCR + SDRAM Refresh Control Register + 0x14 + 16 + read-write + 0x0001 + 0xFFFF + + + REFW + Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) + 12 + 15 + read-write + + + RFC + Auto-Refresh Request Interval Setting + 0 + 11 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + RFC+1 cycles inserted + true + + + + + + + SDRFEN + SDRAM Auto-Refresh Control Register + 0x16 + 8 + read-write + 0x00 + 0xFF + + + RFEN + Auto-Refresh Operation Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + SDICR + SDRAM Initialization Sequence Control Register + 0x20 + 8 + read-write + 0x00 + 0xFF + + + INIRQ + Initialization Sequence Start + 0 + 0 + read-write + + + 0 + Invalid + #0 + + + 1 + Initialization sequence starts + #1 + + + + + + + SDIR + SDRAM Initialization Register + 0x24 + 16 + read-write + 0x0010 + 0xFFFF + + + PRC + Initialization Precharge Cycle Count ( PRF+3 cycles ) + 8 + 10 + read-write + + + ARFC + Initialization Auto-Refresh Count + 4 + 7 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + ARFC+1 times + true + + + + + ARFI + Initialization Auto-Refresh Interval ( PRF+3 cycles ) + 0 + 3 + read-write + + + + + SDADR + SDRAM Address Register + 0x40 + 8 + read-write + 0x00 + 0xFF + + + MXC + Address Multiplex Select + 0 + 1 + read-write + + + 00 + 8-bit shift + #00 + + + 01 + 9-bit shift + #01 + + + 10 + 10-bit shift + #10 + + + 11 + 11-bit shift + #11 + + + + + + + SDTR + SDRAM Timing Register + 0x44 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + RAS + Row Active Interval + 16 + 18 + read-write + + + 000 + 1 cycle + #000 + + + 001 + 2 cycles + #001 + + + 010 + 3 cycles + #010 + + + 011 + 4 cycles + #011 + + + 100 + 5 cycles + #100 + + + 101 + 6 cycles + #101 + + + 110 + 7 cycles + #110 + + + 111 + Setting prohibited + #111 + + + + + RCD + Row Column Latency ( RCD+1 cycles ) + 12 + 13 + read-write + + + RP + Row Precharge Interval ( RP+1 cycles ) + 9 + 11 + read-write + + + WR + Write Recovery Interval + 8 + 8 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + + + CL + SDRAMC Column Latency + 0 + 2 + read-write + + + 001 + 1 cycle + #001 + + + 010 + 2 cycles + #010 + + + 011 + 3 cycles + #011 + + + others + Setting prohibited + true + + + + + + + SDMOD + SDRAM Mode Register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + MR + Mode Register SettingWriting to these bits: Mode register set command is issued. + 0 + 14 + read-write + + + + + SDSR + SDRAM Status Register + 0x50 + 8 + read-only + 0x00 + 0xFF + + + SRFST + Self-Refresh Transition/Recovery Status + 4 + 4 + read-only + + + 0 + Transition/recovery not in progress + #0 + + + 1 + Transition/recovery in progress + #1 + + + + + INIST + Initialization Status + 3 + 3 + read-only + + + 0 + Initialization sequence not in progress + #0 + + + 1 + Initialization sequence in progress + #1 + + + + + MRSST + Mode Register Setting Status + 0 + 0 + read-only + + + 0 + Mode register setting not in progress + #0 + + + 1 + Mode register setting in progress + #1 + + + + + + + + 11 + 0x10 + + + BUS1 + BUS1 + 0 + + + BUS2 + BUS2 + 1 + + + BUS3 + BUS3 + 2 + + + BUS4 + BUS4 + 3 + + + BUS5 + BUS5 + 4 + + + BUS6 + BUS6 + 5 + + + BUS7 + BUS7 + 6 + + + BUS8 + BUS8 + 7 + + + BUS9 + BUS9 + 8 + + + BUS10 + BUS10 + 9 + + + BUS11 + BUS11 + 10 + + + BUSERR[%s] + Bus Error Registers + 0x1800 + + ADD + Bus Error Address Register + 0x00 + 32 + read-only + 0x00000000 + 0x00000000 + + + BERAD + Bus Error AddressWhen a bus error occurs, It stores an error address. + 0 + 31 + read-only + + + + + STAT + Bus Error Status Register + 0x04 + 8 + read-only + 0x00 + 0xFE + + + ERRSTAT + Bus Error StatusWhen bus error assert, error flag occurs. + 7 + 7 + read-only + + + 0 + No bus error occurred + #0 + + + 1 + Bus error occurred + #1 + + + + + ACCSTAT + Error access statusThe status at the time of the error + 0 + 0 + read-only + + + 0 + Read access + #0 + + + 1 + Write Access + #1 + + + + + + + + 6 + 0x4 + + + M4I + M4I + 0 + + + M4D + M4D + 1 + + + SYS + SYS + 2 + + + DMA + DMA + 3 + + + EDM + EDM + 4 + + + GPX + GPX + 5 + + + BUSM[%s] + Master Bus Control Register Array + 0x1000 + + CNT + Master Bus Control Register + 0x0 + 16 + read-write + 0x0000 + 0xFFFF + + + IERES + Ignore Error Responses + 15 + 15 + read-write + + + 0 + Bus error will be reported. + #0 + + + 1 + Bus error will not be reported. + #1 + + + + + + + + 16 + 0x4 + + + FLI + FLI + 0 + + + RAMH + RAMH + 1 + + + MBIU + MBIU + 2 + + + RAM0 + RAM0 + 3 + + + RAM1 + RAM1 + 4 + + + P0B + P0B + 5 + + + P2B + P2B + 6 + + + P3B + P3B + 7 + + + P4B + P4B + 8 + + + PxB + PxB + 9 + + + P6B + P6B + 10 + + + P7B + P7B + 11 + + + FBU + FBU + 12 + + + EXT + EXT + 13 + + + EXT2 + EXT2 + 14 + + + GPX + GPX + 15 + + + BUSS[%s] + Slave Bus Control Register Array + 0x1100 + + CNT + Slave Bus Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + ARBMET + Arbitration MethodSpecify the priority between groups + 4 + 5 + read-write + + + 00 + fixed priority + #00 + + + 01 + round-robin + #01 + + + others + Setting prohibited + true + + + + + + + + CSRECEN + CS Recovery Cycle Insertion Enable Register + 0x0880 + 16 + read-write + 0x3E3E + 0xFFFF + + + 8 + 1 + RCVENM%s + Multiplexed Bus Recovery Cycle Insertion Enable + 8 + 8 + read-write + + + 0 + Recovery cycle insertion is disabled. + #0 + + + 1 + Recovery cycle insertion is enabled. + #1 + + + + + 8 + 1 + RCVEN%s + Separate Bus Recovery Cycle Insertion Enable + 0 + 0 + read-write + + + 0 + Recovery cycle insertion is disabled. + #0 + + + 1 + Recovery cycle insertion is enabled. + #1 + + + + + + + + + R_CAC + Clock Frequency Accuracy Measurement Circuit + 0x40044600 + + 0x00000000 + 0x005 + registers + + + 0x00000006 + 0x006 + registers + + + + CACR0 + CAC Control Register 0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CFME + Clock Frequency Measurement Enable. + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CACR1 + CAC Control Register 1 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + EDGES + Valid Edge Select + 6 + 7 + read-write + + + 00 + Rising edge + #00 + + + 01 + Falling edge + #01 + + + 10 + Both rising and falling edges + #10 + + + 11 + Setting prohibited + #11 + + + + + TCSS + Measurement Target Clock Frequency Division Ratio Select + 4 + 5 + read-write + + + 00 + No division + #00 + + + 01 + x 1/4 clock + #01 + + + 10 + x 1/8 clock + #10 + + + 11 + x 1/32 clock + #11 + + + + + FMCS + Measurement Target Clock Select + 1 + 3 + read-write + + + 000 + Main clock + #000 + + + 001 + Sub-clock + #001 + + + 010 + HOCO clock + #010 + + + 011 + MOCO clock + #011 + + + 100 + LOCO clock + #100 + + + 101 + Peripheral module clock(PCLKB) + #101 + + + 110 + IWDTCLK clock + #110 + + + 111 + Setting prohibited + #111 + + + + + CACREFE + CACREF Pin Input Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CACR2 + CAC Control Register 2 + 0x02 + 8 + read-write + 0x00 + 0xFF + + + DFS + Digital Filter Selection + 6 + 7 + read-write + + + 00 + Digital filtering is disabled. + #00 + + + 01 + The sampling clock for the digital filter is the frequency measuring clock. + #01 + + + 10 + The sampling clock for the digital filter is the frequency measuring clock divided by 4. + #10 + + + 11 + The sampling clock for the digital filter is the frequency measuring clock divided by 16. + #11 + + + + + RCDS + Measurement Reference Clock Frequency Division Ratio Select + 4 + 5 + read-write + + + 00 + 1/32 clock + #00 + + + 01 + 1/128 clock + #01 + + + 10 + 1/1024 clock + #10 + + + 11 + 1/8192 clock + #11 + + + + + RSCS + Measurement Reference Clock Select + 1 + 3 + read-write + + + 000 + Main clock + #000 + + + 001 + Sub-clock + #001 + + + 010 + HOCO clock + #010 + + + 011 + MOCO clock + #011 + + + 100 + LOCO clock + #100 + + + 101 + Peripheral module clock(PCLKB) + #101 + + + 110 + IWDTCLK clock + #110 + + + 111 + Setting prohibited + #111 + + + + + RPS + Reference Signal Select + 0 + 0 + read-write + + + 0 + CACREF pin input + #0 + + + 1 + Internal clock (internally generated signal) + #1 + + + + + + + CAICR + CAC Interrupt Control Register + 0x03 + 8 + read-write + 0x00 + 0xFF + + + OVFFCL + OVFF Clear + 6 + 6 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the OVFF flag + #1 + + + + + MENDFCL + MENDF Clear + 5 + 5 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the MENDF flag + #1 + + + + + FERRFCL + FERRF Clear + 4 + 4 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the FERRF flag + #1 + + + + + OVFIE + Overflow Interrupt Request Enable + 2 + 2 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + MENDIE + Measurement End Interrupt Request Enable + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + FERRIE + Frequency Error Interrupt Request Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CASTR + CAC Status Register + 0x04 + 8 + read-only + 0x00 + 0xFF + + + OVFF + Counter Overflow Flag + 2 + 2 + read-only + + + 0 + The counter has not overflowed. + #0 + + + 1 + The counter has overflowed. + #1 + + + + + MENDF + Measurement End Flag + 1 + 1 + read-only + + + 0 + Measurement is in progress. + #0 + + + 1 + Measurement has ended. + #1 + + + + + FERRF + Frequency Error Flag + 0 + 0 + read-only + + + 0 + The clock frequency is within the range corresponding to the settings. + #0 + + + 1 + The clock frequency has deviated beyond the range corresponding to the settings (frequency error). + #1 + + + + + + + CAULVR + CAC Upper-Limit Value Setting Register + 0x06 + 16 + read-write + 0x0000 + 0xFFFF + + + CAULVR + CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. + 0 + 15 + read-write + + + + + CALLVR + CAC Lower-Limit Value Setting Register + 0x08 + 16 + read-write + 0x0000 + 0xFFFF + + + CALLVR + CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. + 0 + 15 + read-write + + + + + CACNTBR + CAC Counter Buffer Register + 0x0A + 16 + read-only + 0x0000 + 0xFFFF + + + CACNTBR + CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input + 0 + 15 + read-only + + + + + + + R_CAN0 + Controller Area Network (CAN) Module + 0x40050000 + + 0x00000200 + 0x230 + registers + + + 0x00000820 + 0x039 + registers + + + + 32 + 0x10 + MB[%s] + Mailbox + 0x200 + + ID + Mailbox ID Register + 0x0 + 32 + read-write + 0x00000000 + 0x00000000 + + + IDE + ID Extension + 31 + 31 + read-write + + + 0 + Standard ID + #0 + + + 1 + Extended ID + #1 + + + + + RTR + Remote Transmission Request + 30 + 30 + read-write + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + + + + + DL + Mailbox DLC Register + 0x4 + 16 + read-write + 0x0000 + 0x0000 + + + DLC + Data Length Code + 0 + 3 + read-write + + + 0000 + Data length = 0 byte + #0000 + + + 0001 + Data length = 1 byte + #0001 + + + 0010 + Data length = 2 bytes + #0010 + + + 0011 + Data length = 3 bytes + #0011 + + + 0100 + Data length = 4 bytes + #0100 + + + 0101 + Data length = 5 bytes + #0101 + + + 0110 + Data length = 6 bytes + #0110 + + + 0111 + Data length = 7 bytes + #0111 + + + others + Data length = 8 bytes + true + + + + + + + 8 + 0x01 + D[%s] + Mailbox Data Register + 0x6 + 8 + read-write + 0x00 + 0x00 + + + DATA + DATA0 to DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB-first, and transmission or reception starts from bit 7 + 0 + 7 + read-write + + + + + TS + Mailbox Timestamp Register + 0xE + 16 + read-write + 0x0000 + 0x0000 + + + TSH + Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. + 8 + 15 + read-write + + + TSL + Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. + 0 + 7 + read-write + + + + + + 8 + 0x4 + MKR[%s] + Mask Register + 0x400 + 32 + read-write + 0x00000000 + 0x00000000 + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + + + + + 2 + 0x4 + FIDCR[%s] + FIFO Received ID Compare Registers + 0x420 + 32 + read-write + 0x00000000 + 0x00000000 + + + IDE + ID Extension + 31 + 31 + read-write + + + 0 + Standard ID + #0 + + + 1 + Extended ID + #1 + + + + + RTR + Remote Transmission Request + 30 + 30 + read-write + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + + + + + MKIVLR + Mask Invalid Register + 0x428 + 32 + read-write + 0x00000000 + 0x00000000 + + + MB31 + mailbox 31 Mask Invalid + 31 + 31 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB30 + mailbox 30 Mask Invalid + 30 + 30 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB29 + mailbox 29 Mask Invalid + 29 + 29 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB28 + mailbox 28 Mask Invalid + 28 + 28 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB27 + mailbox 27 Mask Invalid + 27 + 27 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB26 + mailbox 26 Mask Invalid + 26 + 26 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB25 + mailbox 25 Mask Invalid + 25 + 25 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB24 + mailbox 24 Mask Invalid + 24 + 24 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB23 + mailbox 23 Mask Invalid + 23 + 23 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB22 + mailbox 22 Mask Invalid + 22 + 22 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB21 + mailbox 21 Mask Invalid + 21 + 21 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB20 + mailbox 20 Mask Invalid + 20 + 20 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB19 + mailbox 19 Mask Invalid + 19 + 19 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB18 + mailbox 18 Mask Invalid + 18 + 18 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB17 + mailbox 17 Mask Invalid + 17 + 17 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB16 + mailbox 16 Mask Invalid + 16 + 16 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB15 + mailbox 15 Mask Invalid + 15 + 15 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB14 + mailbox 14 Mask Invalid + 14 + 14 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB13 + mailbox 13 Mask Invalid + 13 + 13 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB12 + mailbox 12 Mask Invalid + 12 + 12 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB11 + mailbox 11 Mask Invalid + 11 + 11 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB10 + mailbox 10 Mask Invalid + 10 + 10 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB9 + mailbox 9 Mask Invalid + 9 + 9 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB8 + mailbox 8 Mask Invalid + 8 + 8 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB7 + mailbox 7 Mask Invalid + 7 + 7 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB6 + mailbox 6 Mask Invalid + 6 + 6 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB5 + mailbox 5 Mask Invalid + 5 + 5 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB4 + mailbox 4 Mask Invalid + 4 + 4 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB3 + mailbox 3 Mask Invalid + 3 + 3 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB2 + mailbox 2 Mask Invalid + 2 + 2 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB1 + mailbox 1 Mask Invalid + 1 + 1 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB0 + mailbox 0 Mask Invalid + 0 + 0 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + + + MIER + Mailbox Interrupt Enable Register + 0x42C + 32 + read-write + 0x00000000 + 0x00000000 + + + MB31 + mailbox 31 Interrupt Enable + 31 + 31 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB30 + mailbox 30 Interrupt Enable + 30 + 30 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB29 + mailbox 29 Interrupt Enable + 29 + 29 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB28 + mailbox 28 Interrupt Enable + 28 + 28 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB27 + mailbox 27 Interrupt Enable + 27 + 27 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB26 + mailbox 26 Interrupt Enable + 26 + 26 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB25 + mailbox 25 Interrupt Enable + 25 + 25 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB24 + mailbox 24 Interrupt Enable + 24 + 24 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB23 + mailbox 23 Interrupt Enable + 23 + 23 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB22 + mailbox 22 Interrupt Enable + 22 + 22 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB21 + mailbox 21 Interrupt Enable + 21 + 21 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB20 + mailbox 20 Interrupt Enable + 20 + 20 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB19 + mailbox 19 Interrupt Enable + 19 + 19 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB18 + mailbox 18 Interrupt Enable + 18 + 18 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB17 + mailbox 17 Interrupt Enable + 17 + 17 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB16 + mailbox 16 Interrupt Enable + 16 + 16 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB15 + mailbox 15 Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB14 + mailbox 14 Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB13 + mailbox 13 Interrupt Enable + 13 + 13 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB12 + mailbox 12 Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB11 + mailbox 11 Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB10 + mailbox 10 Interrupt Enable + 10 + 10 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB9 + mailbox 9 Interrupt Enable + 9 + 9 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB8 + mailbox 8 Interrupt Enable + 8 + 8 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB7 + mailbox 7 Interrupt Enable + 7 + 7 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB6 + mailbox 6 Interrupt Enable + 6 + 6 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB5 + mailbox 5 Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB4 + mailbox 4 Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB3 + mailbox 3 Interrupt Enable + 3 + 3 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB2 + mailbox 2 Interrupt Enable + 2 + 2 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB1 + mailbox 1 Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB0 + mailbox 0 Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + + + MIER_FIFO + Mailbox Interrupt Enable Register for FIFO Mailbox Mode + MIER + 0x42C + 32 + read-write + 0x00000000 + 0x00000000 + + + MB29 + Receive FIFO Interrupt Generation Timing Control + 29 + 29 + read-write + + + 0 + Every time reception is completed + #0 + + + 1 + When the receive FIFO becomes buffer warning by completion of reception + #1 + + + + + MB28 + Receive FIFO Interrupt Enable + 28 + 28 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB25 + Transmit FIFO Interrupt Generation Timing Control + 25 + 25 + read-write + + + 0 + Every time transmission is completed + #0 + + + 1 + When the transmit FIFO becomes empty due to completion of transmission + #1 + + + + + MB24 + Transmit FIFO Interrupt Enable + 24 + 24 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB23 + mailbox 23 Interrupt Enable + 23 + 23 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB22 + mailbox 22 Interrupt Enable + 22 + 22 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB21 + mailbox 21 Interrupt Enable + 21 + 21 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB20 + mailbox 20 Interrupt Enable + 20 + 20 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB19 + mailbox 19 Interrupt Enable + 19 + 19 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB18 + mailbox 18 Interrupt Enable + 18 + 18 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB17 + mailbox 17 Interrupt Enable + 17 + 17 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB16 + mailbox 16 Interrupt Enable + 16 + 16 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB15 + mailbox 15 Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB14 + mailbox 14 Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB13 + mailbox 13 Interrupt Enable + 13 + 13 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB12 + mailbox 12 Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB11 + mailbox 11 Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB10 + mailbox 10 Interrupt Enable + 10 + 10 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB9 + mailbox 9 Interrupt Enable + 9 + 9 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB8 + mailbox 8 Interrupt Enable + 8 + 8 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB7 + mailbox 7 Interrupt Enable + 7 + 7 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB6 + mailbox 6 Interrupt Enable + 6 + 6 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB5 + mailbox 5 Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB4 + mailbox 4 Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB3 + mailbox 3 Interrupt Enable + 3 + 3 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB2 + mailbox 2 Interrupt Enable + 2 + 2 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB1 + mailbox 1 Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB0 + mailbox 0 Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + + + 32 + 0x1 + MCTL_TX[%s] + Message Control Register for Transmit + 0x820 + 8 + read-write + 0x00 + 0xFF + + + TRMREQ + Transmit Mailbox Request + 7 + 7 + read-write + + + 0 + Not configured for transmission + #0 + + + 1 + Configured for transmission + #1 + + + + + RECREQ + Receive Mailbox Request + 6 + 6 + read-write + + + 0 + Not configured for reception + #0 + + + 1 + Configured for reception + #1 + + + + + ONESHOT + One-Shot Enable + 4 + 4 + read-write + + + 0 + One-shot reception or one-shot transmission disabled + #0 + + + 1 + One-shot reception or one-shot transmission enabled + #1 + + + + + TRMABT + Transmission Abort Complete Flag (Transmit mailbox setting enabled) + 2 + 2 + read-write + + + 0 + Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested + #0 + + + 1 + Transmission abort is completed + #1 + + + + + TRMACTIVE + Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) + 1 + 1 + read-only + + + 0 + Transmission is pending or transmission is not requested + #0 + + + 1 + From acceptance of transmission request to completion of transmission, or error/arbitration-lost + #1 + + + + + SENTDATA + Transmission Complete Flag + 0 + 0 + read-write + + + 0 + Transmission is not completed + #0 + + + 1 + Transmission is completed + #1 + + + + + + + 32 + 0x1 + MCTL_RX[%s] + Message Control Register for Receive + MCTL_TX[%s] + 0x820 + 8 + read-write + 0x00 + 0xFF + + + TRMREQ + Transmit Mailbox Request + 7 + 7 + read-write + + + 0 + Not configured for transmission + #0 + + + 1 + Configured for transmission + #1 + + + + + RECREQ + Receive Mailbox Request + 6 + 6 + read-write + + + 0 + Not configured for reception + #0 + + + 1 + Configured for reception + #1 + + + + + ONESHOT + One-Shot Enable + 4 + 4 + read-write + + + 0 + One-shot reception or one-shot transmission disabled + #0 + + + 1 + One-shot reception or one-shot transmission enabled + #1 + + + + + MSGLOST + Message Lost Flag(Receive mailbox setting enabled) + 2 + 2 + read-write + + + 0 + Message is not overwritten or overrun + #0 + + + 1 + Message is overwritten or overrun + #1 + + + + + INVALDATA + Reception-in-Progress Status Flag (Receive mailbox setting enabled) + 1 + 1 + read-only + + + 0 + Message valid + #0 + + + 1 + Message being updated + #1 + + + + + NEWDATA + Reception Complete Flag + 0 + 0 + read-write + + + 0 + No data has been received or 0 is written to the NEWDATA bit + #0 + + + 1 + A new message is being stored or has been stored to the mailbox + #1 + + + + + + + CTLR + Control Register + 0x840 + 16 + read-write + 0x0500 + 0xFFFF + + + RBOC + Forcible Return From Bus-Off + 13 + 13 + read-write + + + 0 + Nothing occurred + #0 + + + 1 + Forcible return from bus-off + #1 + + + + + BOM + Bus-Off Recovery Mode by a program request + 11 + 12 + read-write + + + 00 + Normal mode (ISO11898-1 compliant) + #00 + + + 01 + Entry to CAN halt mode automatically at bus-off entry + #01 + + + 10 + Entry to CAN halt mode automatically at bus-off end + #10 + + + 11 + Entry to CAN halt mode (during bus-off recovery period) + #11 + + + + + SLPM + CAN Sleep Mode + 10 + 10 + read-write + + + 0 + Other than CAN sleep mode + #0 + + + 1 + CAN sleep mode + #1 + + + + + CANM + CAN Operating Mode Select + 8 + 9 + read-write + + + 00 + CAN operation mode + #00 + + + 01 + CAN reset mode + #01 + + + 10 + CAN halt mode + #10 + + + 11 + CAN reset mode (forcible transition) + #11 + + + + + TSPS + Time Stamp Prescaler Select + 6 + 7 + read-write + + + 00 + Every bit time + #00 + + + 01 + Every 2-bit time + #01 + + + 10 + Every 4-bit time + #10 + + + 11 + Every 8-bit time + #11 + + + + + TSRC + Time Stamp Counter Reset Command + 5 + 5 + read-write + + + 0 + Nothing occurred + #0 + + + 1 + Reset + #1 + + + + + TPM + Transmission Priority Mode Select + 4 + 4 + read-write + + + 0 + ID priority transmit mode + #0 + + + 1 + Mailbox number priority transmit mode + #1 + + + + + MLM + Message Lost Mode Select + 3 + 3 + read-write + + + 0 + Overwrite mode + #0 + + + 1 + Overrun mode + #1 + + + + + IDFM + ID Format Mode Select + 1 + 2 + read-write + + + 00 + Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. + #00 + + + 01 + Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. + #01 + + + 10 + Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. + #10 + + + 11 + Do not use this combination + #11 + + + + + MBM + CAN Mailbox Mode Select + 0 + 0 + read-write + + + 0 + Normal mailbox mode + #0 + + + 1 + FIFO mailbox mode + #1 + + + + + + + STR + Status Register + 0x842 + 16 + read-only + 0x0500 + 0xFFFF + + + RECST + Receive Status Flag (receiver) + 14 + 14 + read-only + + + 0 + Bus idle or transmission in progress + #0 + + + 1 + Reception in progress + #1 + + + + + TRMST + Transmit Status Flag (transmitter) + 13 + 13 + read-only + + + 0 + Bus idle or reception in progress + #0 + + + 1 + Transmission in progress or in bus-off state + #1 + + + + + BOST + Bus-Off Status Flag + 12 + 12 + read-only + + + 0 + Not in bus-off state + #0 + + + 1 + In bus-off state + #1 + + + + + EPST + Error-Passive Status Flag + 11 + 11 + read-only + + + 0 + Not in error-passive state + #0 + + + 1 + In error-passive state + #1 + + + + + SLPST + CAN Sleep Status Flag + 10 + 10 + read-only + + + 0 + Not in CAN sleep mode + #0 + + + 1 + In CAN sleep mode + #1 + + + + + HLTST + CAN Halt Status Flag + 9 + 9 + read-only + + + 0 + Not in CAN halt mode + #0 + + + 1 + In CAN halt mode + #1 + + + + + RSTST + CAN Reset Status Flag + 8 + 8 + read-only + + + 0 + Not in CAN reset mode + #0 + + + 1 + In CAN reset mode + #1 + + + + + EST + Error Status Flag + 7 + 7 + read-only + + + 0 + No error occurred + #0 + + + 1 + Error occurred + #1 + + + + + TABST + Transmission Abort Status Flag + 6 + 6 + read-only + + + 0 + No mailbox with TRMABT bit = 1 + #0 + + + 1 + Mailbox(es) with TRMABT bit = 1 + #1 + + + + + FMLST + FIFO Mailbox Message Lost Status Flag + 5 + 5 + read-only + + + 0 + RFMLF bit = 0 + #0 + + + 1 + RFMLF bit = 1 + #1 + + + + + NMLST + Normal Mailbox Message Lost Status Flag + 4 + 4 + read-only + + + 0 + No mailbox with MSGLOST bit = 1 + #0 + + + 1 + Mailbox(es) with MSGLOST bit = 1 + #1 + + + + + TFST + Transmit FIFO Status Flag + 3 + 3 + read-only + + + 0 + Transmit FIFO is full + #0 + + + 1 + Transmit FIFO is not full + #1 + + + + + RFST + Receive FIFO Status Flag + 2 + 2 + read-only + + + 0 + No message in receive FIFO (empty) + #0 + + + 1 + Message in receive FIFO + #1 + + + + + SDST + SENTDATA Status Flag + 1 + 1 + read-only + + + 0 + No mailbox with SENTDATA bit = 1 + #0 + + + 1 + Mailbox(es) with SENTDATA bit = 1 + #1 + + + + + NDST + NEWDATA Status Flag + 0 + 0 + read-only + + + 0 + No mailbox with NEWDATA bit = 1 + #0 + + + 1 + Mailbox(es) with NEWDATA bit = 1 + #1 + + + + + + + BCR + Bit Configuration Register + 0x844 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSEG1 + Time Segment 1 Control + 28 + 31 + read-write + + + 0000 + Setting prohibited + #0000 + + + 0001 + Setting prohibited + #0001 + + + 0010 + Setting prohibited + #0010 + + + 0011 + 4 Tq + #0011 + + + 0100 + 5 Tq + #0100 + + + 0101 + 6 Tq + #0101 + + + 0110 + 7 Tq + #0110 + + + 0111 + 8 Tq + #0111 + + + 1000 + 9 Tq + #1000 + + + 1001 + 10 Tq + #1001 + + + 1010 + 11 Tq + #1010 + + + 1011 + 12 Tq + #1011 + + + 1100 + 13 Tq + #1100 + + + 1101 + 14 Tq + #1101 + + + 1110 + 15 Tq + #1110 + + + 1111 + 16 Tq + #1111 + + + + + BRP + Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). + 16 + 25 + read-write + + + SJW + Resynchronization Jump Width Control + 12 + 13 + read-write + + + 00 + 1 Tq + #00 + + + 01 + 2 Tq + #01 + + + 10 + 3 Tq + #10 + + + 11 + 4 Tq + #11 + + + + + TSEG2 + Time Segment 2 Control + 8 + 10 + read-write + + + 000 + Setting prohibited + #000 + + + 001 + 2 Tq + #001 + + + 010 + 3 Tq + #010 + + + 011 + 4 Tq + #011 + + + 100 + 5 Tq + #100 + + + 101 + 6 Tq + #101 + + + 110 + 7 Tq + #110 + + + 111 + 8 Tq + #111 + + + + + CCLKS + CAN Clock Source Selection + 0 + 0 + read-write + + + 0 + PCLK (generated by the PLL clock) + #0 + + + 1 + CANMCLK (generated by the main clock) + #1 + + + + + + + RFCR + Receive FIFO Control Register + 0x848 + 8 + read-write + 0x80 + 0xFF + + + RFEST + Receive FIFO Empty Status Flag + 7 + 7 + read-only + + + 0 + Unread message in receive FIFO + #0 + + + 1 + No unread message in receive FIFO + #1 + + + + + RFWST + Receive FIFO Buffer Warning Status Flag + 6 + 6 + read-only + + + 0 + Receive FIFO is not buffer warning + #0 + + + 1 + Receive FIFO is buffer warning (3 unread messages) + #1 + + + + + RFFST + Receive FIFO Full Status Flag + 5 + 5 + read-only + + + 0 + Receive FIFO is not full + #0 + + + 1 + Receive FIFO is full (4 unread messages) + #1 + + + + + RFMLF + Receive FIFO Message Lost Flag + 4 + 4 + read-write + + + 0 + No receive FIFO message lost has occurred + #0 + + + 1 + Receive FIFO message lost has occurred + #1 + + + + + RFUST + Receive FIFO Unread Message Number Status + 1 + 3 + read-only + + + 000 + No unread message + #000 + + + 001 + 1 unread message + #001 + + + 010 + 2 unread messages + #010 + + + 011 + 3 unread messages + #011 + + + 100 + 4 unread messages + #100 + + + others + Setting prohibited + true + + + + + RFE + Receive FIFO Enable + 0 + 0 + read-write + + + 0 + Receive FIFO disabled + #0 + + + 1 + Receive FIFO enabled + #1 + + + + + + + RFPCR + Receive FIFO Pointer Control Register + 0x849 + 8 + write-only + 0x00 + 0x00 + + + RFPCR + The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. + 0 + 7 + write-only + + + + + TFCR + Transmit FIFO Control Register + 0x84A + 8 + read-write + 0x80 + 0xFF + + + TFEST + Transmit FIFO Empty Status + 7 + 7 + read-only + + + 0 + Unsent message in transmit FIFO + #0 + + + 1 + No unsent message in transmit FIFO + #1 + + + + + TFFST + Transmit FIFO Full Status + 6 + 6 + read-only + + + 0 + Transmit FIFO is not full + #0 + + + 1 + Transmit FIFO is full (4 unsent messages) + #1 + + + + + TFUST + Transmit FIFO Unsent Message Number Status + 1 + 3 + read-only + + + 000 + No unsent message + #000 + + + 001 + 1 unsent message + #001 + + + 010 + 2 unsent messages + #010 + + + 011 + 3 unsent messages + #011 + + + 100 + 4 unsent messages + #100 + + + others + Setting prohibited + true + + + + + TFE + Transmit FIFO Enable + 0 + 0 + read-write + + + 0 + Transmit FIFO disabled + #0 + + + 1 + Transmit FIFO enabled + #1 + + + + + + + TFPCR + Transmit FIFO Pointer Control Register + 0x84B + 8 + write-only + 0x00 + 0x00 + + + TFPCR + The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. + 0 + 7 + write-only + + + + + EIER + Error Interrupt Enable Register + 0x84C + 8 + read-write + 0x00 + 0xFF + + + BLIE + Bus Lock Interrupt Enable + 7 + 7 + read-write + + + 0 + Bus lock interrupt disabled + #0 + + + 1 + Bus lock interrupt enabled + #1 + + + + + OLIE + Overload Frame Transmit Interrupt Enable + 6 + 6 + read-write + + + 0 + Overload frame transmit interrupt disabled + #0 + + + 1 + Overload frame transmit interrupt enabled + #1 + + + + + ORIE + Overrun Interrupt Enable + 5 + 5 + read-write + + + 0 + Receive overrun interrupt disabled + #0 + + + 1 + Receive overrun interrupt enabled + #1 + + + + + BORIE + Bus-Off Recovery Interrupt Enable + 4 + 4 + read-write + + + 0 + Bus-off recovery interrupt disabled + #0 + + + 1 + Bus-off recovery interrupt enabled + #1 + + + + + BOEIE + Bus-Off Entry Interrupt Enable + 3 + 3 + read-write + + + 0 + Bus-off entry interrupt disabled + #0 + + + 1 + Bus-off entry interrupt enabled + #1 + + + + + EPIE + Error-Passive Interrupt Enable + 2 + 2 + read-write + + + 0 + Error-passive interrupt disabled + #0 + + + 1 + Error-passive interrupt enabled + #1 + + + + + EWIE + Error-Warning Interrupt Enable + 1 + 1 + read-write + + + 0 + Error-warning interrupt disabled + #0 + + + 1 + Error-warning interrupt enabled + #1 + + + + + BEIE + Bus Error Interrupt Enable + 0 + 0 + read-write + + + 0 + Bus error interrupt disabled + #0 + + + 1 + Bus error interrupt enabled + #1 + + + + + + + EIFR + Error Interrupt Factor Judge Register + 0x84D + 8 + read-write + 0x00 + 0xFF + + + BLIF + Bus Lock Detect Flag + 7 + 7 + read-write + + + 0 + No bus lock detected + #0 + + + 1 + Bus lock detected + #1 + + + + + OLIF + Overload Frame Transmission Detect Flag + 6 + 6 + read-write + + + 0 + No overload frame transmission detected + #0 + + + 1 + Overload frame transmission detected + #1 + + + + + ORIF + Receive Overrun Detect Flag + 5 + 5 + read-write + + + 0 + No receive overrun detected + #0 + + + 1 + Receive overrun detected + #1 + + + + + BORIF + Bus-Off Recovery Detect Flag + 4 + 4 + read-write + + + 0 + No bus-off recovery detected + #0 + + + 1 + Bus-off recovery detected + #1 + + + + + BOEIF + Bus-Off Entry Detect Flag + 3 + 3 + read-write + + + 0 + No bus-off entry detected + #0 + + + 1 + Bus-off entry detected + #1 + + + + + EPIF + Error-Passive Detect Flag + 2 + 2 + read-write + + + 0 + No error-passive detected + #0 + + + 1 + Error-passive detected + #1 + + + + + EWIF + Error-Warning Detect Flag + 1 + 1 + read-write + + + 0 + No error-warning detected + #0 + + + 1 + Error-warning detected + #1 + + + + + BEIF + Bus Error Detect Flag + 0 + 0 + read-write + + + 0 + No bus error detected + #0 + + + 1 + Bus error detected + #1 + + + + + + + RECR + Receive Error Count Register + 0x84E + 8 + read-only + 0x00 + 0xFF + + + RECR + Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception. + 0 + 7 + read-only + + + + + TECR + Transmit Error Count Register + 0x84F + 8 + read-only + 0x00 + 0xFF + + + TECR + Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission. + 0 + 7 + read-only + + + + + ECSR + Error Code Store Register + 0x850 + 8 + read-write + 0x00 + 0xFF + + + EDPM + Error Display Mode Select + 7 + 7 + read-write + + + 0 + Output of first detected error code + #0 + + + 1 + Output of accumulated error code + #1 + + + + + ADEF + ACK Delimiter Error Flag + 6 + 6 + read-write + + + 0 + No ACK delimiter error detected + #0 + + + 1 + ACK delimiter error detected + #1 + + + + + BE0F + Bit Error (dominant) Flag + 5 + 5 + read-write + + + 0 + No bit error (dominant) detected + #0 + + + 1 + Bit error (dominant) detected + #1 + + + + + BE1F + Bit Error (recessive) Flag + 4 + 4 + read-write + + + 0 + No bit error (recessive) detected + #0 + + + 1 + Bit error (recessive) detected + #1 + + + + + CEF + CRC Error Flag + 3 + 3 + read-write + + + 0 + No CRC error detected + #0 + + + 1 + CRC error detected + #1 + + + + + AEF + ACK Error Flag + 2 + 2 + read-write + + + 0 + No ACK error detected + #0 + + + 1 + ACK error detected + #1 + + + + + FEF + Form Error Flag + 1 + 1 + read-write + + + 0 + No form error detected + #0 + + + 1 + Form error detected + #1 + + + + + SEF + Stuff Error Flag + 0 + 0 + read-write + + + 0 + No stuff error detected + #0 + + + 1 + Stuff error detected + #1 + + + + + + + CSSR + Channel Search Support Register + 0x851 + 8 + read-write + 0x00 + 0x00 + + + CSSR + When the value for the channel search is input, the channel number is output to MSSR. + 0 + 7 + read-write + + + + + MSSR + Mailbox Search Status Register + 0x852 + 8 + read-only + 0x80 + 0xFF + + + SEST + Search Result Status + 7 + 7 + read-only + + + 0 + Search result found + #0 + + + 1 + No search result + #1 + + + + + MBNST + Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. + 0 + 4 + read-only + + + + + MSMR + Mailbox Search Mode Register + 0x853 + 8 + read-write + 0x00 + 0xFF + + + MBSM + Mailbox Search Mode Select + 0 + 1 + read-write + + + 00 + Receive mailbox search mode + #00 + + + 01 + Transmit mailbox search mode + #01 + + + 10 + Message lost search mode + #10 + + + 11 + Channel search mode + #11 + + + + + + + TSR + Time Stamp Register + 0x854 + 16 + read-only + 0x0000 + 0xFFFF + + + TSR + Free-running counter value for the time stamp function + 0 + 15 + read-only + + + + + AFSR + Acceptance Filter Support Register + 0x856 + 16 + read-write + 0x0000 + 0x0000 + + + AFSR + After the standard ID of a received message is written, the value converted for data table search can be read. + 0 + 15 + read-write + + + + + TCR + Test Control Register + 0x858 + 8 + read-write + 0x00 + 0xFF + + + TSTM + CAN Test Mode Select + 1 + 2 + read-write + + + 00 + Other than CAN test mode + #00 + + + 01 + Listen-only mode + #01 + + + 10 + Self-test mode 0 (external loopback) + #10 + + + 11 + Self-test mode 1 (internal loopback) + #11 + + + + + TSTE + CAN Test Mode Enable + 0 + 0 + read-write + + + 0 + CAN test mode disabled + #0 + + + 1 + CAN test mode enabled + #1 + + + + + + + + + R_CAN1 + 0x40051000 + + + R_CRC + Cyclic Redundancy Check (CRC) Calculator + 0x40074000 + + 0x00000000 + 0x002 + registers + + + 0x00000004 + 0x00A + registers + + + + CRCCR0 + CRC Control Register0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + DORCLR + CRCDOR Register Clear + 7 + 7 + write-only + + + 0 + No effect. + #0 + + + 1 + Clears the CRCDOR register. + #1 + + + + + LMS + CRC Calculation Switching + 6 + 6 + read-write + + + 0 + Generates CRC for LSB first communication. + #0 + + + 1 + Generates CRC for MSB first communication. + #1 + + + + + GPS + CRC Generating Polynomial Switching + 0 + 2 + read-write + + + 000 + No calculation is executed. + #000 + + + 001 + 8-bit CRC-8 (X8 + X2 + X + 1) + #001 + + + 010 + 16-bit CRC-16 (X16 + X15 + X2 + 1) + #010 + + + 011 + 16-bit CRC-CCITT (X16 + X12 + X5 + 1) + #011 + + + 100 + 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) + #100 + + + 101 + 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) + #101 + + + others + No calculation is executed. + true + + + + + + + CRCCR1 + CRC Control Register1 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + CRCSEN + Snoop enable bit + 7 + 7 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + CRCSWR + Snoop-on-write/read switch bit + 6 + 6 + read-write + + + 0 + Snoop-on-read + #0 + + + 1 + Snoop-on-write + #1 + + + + + + + CRCDIR + CRC Data Input Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRCDIR + Calculation input Data (Case of CRC-32, CRC-32C ) + 0 + 31 + read-write + + + + + CRCDIR_BY + CRC Data Input Register (byte access) + CRCDIR + 0x04 + 8 + read-write + 0x00 + 0xFF + + + CRCDIR_BY + Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) + 0 + 7 + read-write + + + + + CRCDOR + CRC Data Output Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CRCDOR + Calculation output Data (Case of CRC-32, CRC-32C ) + 0 + 31 + read-write + + + + + CRCDOR_HA + CRC Data Output Register (halfword access) + CRCDOR + 0x08 + 16 + read-write + 0x0000 + 0xFFFF + + + CRCDOR_HA + Calculation output Data (Case of CRC-16 or CRC-CCITT ) + 0 + 15 + read-write + + + + + CRCDOR_BY + CRC Data Output Register(byte access) + CRCDOR + 0x08 + 8 + read-write + 0x00 + 0xFF + + + CRCDOR_BY + Calculation output Data (Case of CRC-8 ) + 0 + 7 + read-write + + + + + CRCSAR + Snoop Address Register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + CRCSA + snoop address bitSet the I/O register address to snoop + 0 + 13 + read-write + + + 0x0003 + SCI0.TDR + 0x0003 + + + 0x0005 + SCI0.RDR + 0x0005 + + + 0x0023 + SCI1.TDR + 0x0023 + + + 0x0025 + SCI1.RDR + 0x0025 + + + 0x0043 + SCI2.TDR + 0x0043 + + + 0x0045 + SCI2.RDR + 0x0045 + + + 0x0063 + SCI3.TDR + 0x0063 + + + 0x0065 + SCI3.RDR + 0x0065 + + + 0x0083 + SCI4.TDR + 0x0083 + + + 0x0085 + SCI4.RDR + 0x0085 + + + 0x00A3 + SCI5.TDR + 0x00A3 + + + 0x00A5 + SCI5.RDR + 0x00A5 + + + 0x00C3 + SCI6.TDR + 0x00C3 + + + 0x00C5 + SCI6.RDR + 0x00C5 + + + 0x00E3 + SCI7.TDR + 0x00E3 + + + 0x00E5 + SCI7.RDR + 0x00E5 + + + 0x0103 + SCI8.TDR + 0x0103 + + + 0x0105 + SCI8.RDR + 0x0105 + + + 0x0123 + SCI9.TDR + 0x0123 + + + 0x0125 + SCI9.RDR + 0x0125 + + + others + Settings other than above are prohibited. + true + + + + + + + + + R_CTSU + Capacitive Touch Sensing Unit + 0x40081000 + + 0x00000000 + 0x01E + registers + + + + CTSUCR0 + CTSU Control Register 0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CTSUTXVSEL + CTSU Transmission power supply selection + 7 + 7 + read-write + + + 0 + Select Vcc + #0 + + + 1 + Select internal logic power supply + #1 + + + + + CTSUINIT + CTSU Control Block Initialization + 4 + 4 + read-write + + + 0 + Writing a 0 has no effect, this bit is read as 0. + #0 + + + 1 + initializes the CTSU control block and registers. + #1 + + + + + CTSUIOC + CTSU Transmit Pin Control + 3 + 3 + read-write + + + 0 + Low-level output from transmit channel non-measurement pin. + #0 + + + 1 + High-level output from transmit channel non-measurement pin. + #1 + + + + + CTSUSNZ + CTSU Wait State Power-Saving Enable + 2 + 2 + read-write + + + 0 + Power-saving function during wait state is disabled. + #0 + + + 1 + Power-saving function during wait state is enabled. + #1 + + + + + CTSUCAP + CTSU Measurement Operation Start Trigger Select + 1 + 1 + read-write + + + 0 + Software trigger. + #0 + + + 1 + External trigger. + #1 + + + + + CTSUSTRT + CTSU Measurement Operation Start + 0 + 0 + read-write + + + 0 + Measurement operation stops. + #0 + + + 1 + Measurement operation starts. + #1 + + + + + + + CTSUCR1 + CTSU Control Register 1 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + CTSUMD + CTSU Measurement Mode Select + 6 + 7 + read-write + + + 00 + Self-capacitance single scan mode + #00 + + + 01 + Self-capacitance multi-scan mode + #01 + + + 10 + Mutual capacitance simple scan mode + #10 + + + 11 + Mutual capacitance full scan mode + #11 + + + + + CTSUCLK + CTSU Operating Clock Select + 4 + 5 + read-write + + + 00 + PCLK + #00 + + + 01 + PCLK/2 (PCLK divided by 2) + #01 + + + 10 + PCLK/2 (PCLK divided by 4) + #10 + + + 11 + Setting prohibited + #11 + + + + + CTSUATUNE1 + CTSU Power Supply Capacity Adjustment + 3 + 3 + read-write + + + 0 + Normal output + #0 + + + 1 + High-current output + #1 + + + + + CTSUATUNE0 + CTSU Power Supply Operating Mode Setting + 2 + 2 + read-write + + + 0 + Normal operating mode + #0 + + + 1 + Low-voltage operating mode + #1 + + + + + CTSUCSW + CTSU LPF Capacitance Charging Control + 1 + 1 + read-write + + + 0 + Turned off capacitance switch + #0 + + + 1 + Turned on capacitance switch + #1 + + + + + CTSUPON + CTSU Power Supply Enable + 0 + 0 + read-write + + + 0 + Powered off the CTSU + #0 + + + 1 + Powered on the CTSU + #1 + + + + + + + CTSUSDPRS + CTSU Synchronous Noise Reduction Setting Register + 0x02 + 8 + read-write + 0x00 + 0xFF + + + CTSUSOFF + CTSU High-Pass Noise Reduction Function Off Setting + 6 + 6 + read-write + + + 0 + High-pass noise reduction function turned on + #0 + + + 1 + High-pass noise reduction function turned off + #1 + + + + + CTSUPRMODE + CTSU Base Period and Pulse Count Setting + 4 + 5 + read-write + + + 00 + 510 pulses + #00 + + + 01 + 126 pulses + #01 + + + 10 + 62 pulses (recommended setting value) + #10 + + + 11 + Setting prohibited + #11 + + + + + CTSUPRRATIO + CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b) + 0 + 3 + read-write + + + + + CTSUSST + CTSU Sensor Stabilization Wait Control Register + 0x03 + 8 + read-write + 0x00 + 0xFF + + + CTSUSST + CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b. + 0 + 7 + read-write + + + + + CTSUMCH0 + CTSU Measurement Channel Register 0 + 0x04 + 8 + read-write + 0x3F + 0xFF + + + CTSUMCH0 + CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped. + 0 + 5 + read-write + + + TS0 + measured TS0 + 0 + + + TS1 + measured TS1 + 1 + + + TS2 + measured TS2 + 2 + + + TS3 + measured TS3 + 3 + + + TS4 + measured TS4 + 4 + + + TS5 + measured TS5 + 5 + + + TS6 + measured TS6 + 6 + + + TS7 + measured TS7 + 7 + + + TS8 + measured TS8 + 8 + + + TS9 + measured TS9 + 9 + + + TS10 + measured TS10 + 10 + + + TS11 + measured TS11 + 11 + + + TS12 + measured TS12 + 12 + + + TS13 + measured TS13 + 13 + + + TS14 + measured TS14 + 14 + + + TS15 + measured TS15 + 15 + + + TS16 + measured TS16 + 16 + + + TS17 + measured TS17 + 17 + + + TS18 + measured TS18 + 18 + + + TS19 + measured TS19 + 19 + + + TS20 + measured TS20 + 20 + + + TS21 + measured TS21 + 21 + + + TS22 + measured TS22 + 22 + + + TS23 + measured TS23 + 23 + + + TS24 + measured TS24 + 24 + + + TS25 + measured TS25 + 25 + + + TS26 + measured TS26 + 26 + + + TS27 + measured TS27 + 27 + + + TS28 + measured TS28 + 28 + + + TS29 + measured TS29 + 29 + + + TS30 + measured TS30 + 30 + + + TS31 + measured TS31 + 31 + + + TS32 + measured TS32 + 32 + + + TS33 + measured TS33 + 33 + + + TS34 + measured TS34 + 34 + + + TS35 + measured TS35 + 35 + + + STOP + Conversion Stopped + #111111 + + + + + + + CTSUMCH1 + CTSU Measurement Channel Register 1 + 0x05 + 8 + read-write + 0x3F + 0xFF + + + CTSUMCH1 + CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped. + 0 + 5 + read-only + + + TS0 + measured TS0 + 0 + + + TS1 + measured TS1 + 1 + + + TS2 + measured TS2 + 2 + + + TS3 + measured TS3 + 3 + + + TS4 + measured TS4 + 4 + + + TS5 + measured TS5 + 5 + + + TS6 + measured TS6 + 6 + + + TS7 + measured TS7 + 7 + + + TS8 + measured TS8 + 8 + + + TS9 + measured TS9 + 9 + + + TS10 + measured TS10 + 10 + + + TS11 + measured TS11 + 11 + + + TS12 + measured TS12 + 12 + + + TS13 + measured TS13 + 13 + + + TS14 + measured TS14 + 14 + + + TS15 + measured TS15 + 15 + + + TS16 + measured TS16 + 16 + + + TS17 + measured TS17 + 17 + + + TS18 + measured TS18 + 18 + + + TS19 + measured TS19 + 19 + + + TS20 + measured TS20 + 20 + + + TS21 + measured TS21 + 21 + + + TS22 + measured TS22 + 22 + + + TS23 + measured TS23 + 23 + + + TS24 + measured TS24 + 24 + + + TS25 + measured TS25 + 25 + + + TS26 + measured TS26 + 26 + + + TS27 + measured TS27 + 27 + + + TS28 + measured TS28 + 28 + + + TS29 + measured TS29 + 29 + + + TS30 + measured TS30 + 30 + + + TS31 + measured TS31 + 31 + + + TS32 + measured TS32 + 32 + + + TS33 + measured TS33 + 33 + + + TS34 + measured TS34 + 34 + + + TS35 + measured TS35 + 35 + + + STOP + Conversion Stopped + #111111 + + + + + + + 5 + 1 + CTSUCHAC[%s] + CTSU Channel Enable Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + TS%s + CTSU Channel Enable Control + 0 + 0 + read-write + + + 0 + Do not measure + 0 + + + 1 + Measure + 1 + + + + + + + 5 + 1 + CTSUCHTRC[%s] + CTSU Channel Transmit/Receive Control Register + 0x0B + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + TS%s + CTSU Channel Transmit/Receive Control + 0 + 0 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + + + CTSUDCLKC + CTSU High-Pass Noise Reduction Control Register + 0x10 + 8 + read-write + 0x00 + 0xFF + + + CTSUSSCNT + CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b. + 4 + 5 + read-write + + + CTSUSSMOD + CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b. + 0 + 1 + read-write + + + + + CTSUST + CTSU Status Register + 0x11 + 8 + read-write + 0x00 + 0xFF + + + CTSUPS + CTSU Mutual Capacitance Status Flag + 7 + 7 + read-only + + + 0 + First measurement + #0 + + + 1 + Second measurement + #1 + + + + + CTSUROVF + CTSU Reference Counter Overflow Flag + 6 + 6 + read-write + + + 0 + No overflow + #0 + + + 1 + An overflow + #1 + + + + + CTSUSOVF + CTSU Sensor Counter Overflow Flag + 5 + 5 + read-write + + + 0 + No overflow + #0 + + + 1 + An overflow + #1 + + + + + CTSUDTSR + CTSU Data Transfer Status Flag + 4 + 4 + read-only + + + 0 + Measurement result has been read + #0 + + + 1 + Measurement result has not been read + #1 + + + + + CTSUSTC + CTSU Measurement Status Counter + 0 + 2 + read-only + + + 000 + Status 0 + #000 + + + 001 + Status 1 + #001 + + + 010 + Status 2 + #010 + + + 011 + Status 3 + #011 + + + 100 + Status 4 + #100 + + + 101 + Status 5 + #101 + + + + + + + CTSUSSC + CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register + 0x12 + 16 + read-write + 0x0000 + 0xFFFF + + + CTSUSSDIV + CTSU Spectrum Diffusion Frequency Division Setting + 8 + 11 + read-write + + + 0000 + 4.00 <= fb + #0000 + + + 0001 + 2.00 <= fb < 4.00 + #0001 + + + 0010 + 1.33 <= fb < 2.00 + #0010 + + + 0011 + 1.00 <= fb < 1.33 + #0011 + + + 0100 + 0.80 <= fb < 1.00 + #0100 + + + 0101 + 0.67 <= fb < 0.80 + #0101 + + + 0110 + 0.57 <= fb < 0.67 + #0110 + + + 0111 + 0.50 <= fb < 0.57 + #0111 + + + 1000 + 0.44 <= fb < 0.50 + #1000 + + + 1001 + 0.40 <= fb < 0.44 + #1001 + + + 1010 + 0.36 <= fb < 0.40 + #1010 + + + 1011 + 0.33 <= fb < 0.36 + #1011 + + + 1100 + 0.31 <= fb < 0.33 + #1100 + + + 1101 + 0.29 <= fb < 0.31 + #1101 + + + 1110 + 0.27 <= fb < 0.29 + #1110 + + + 1111 + fb < 0.27 + #1111 + + + + + + + CTSUSO0 + CTSU Sensor Offset Register 0 + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + CTSUSNUM + CTSU Measurement Count Setting + 10 + 15 + read-write + + + CTSUSO + CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 ) + 0 + 9 + read-write + + + + + CTSUSO1 + CTSU Sensor Offset Register 1 + 0x16 + 16 + read-write + 0x0000 + 0xFFFF + + + CTSUICOG + CTSU ICO Gain Adjustment + 13 + 14 + read-write + + + 00 + 100 percent gain + #00 + + + 01 + 66 percent gain + #01 + + + 10 + 50 percent gain + #10 + + + 11 + 40 percent gain + #11 + + + + + CTSUSDPA + CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2 + 8 + 12 + read-write + + + CTSURICOA + CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 ) + 0 + 7 + read-write + + + + + CTSUSC + CTSU Sensor Counter + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + CTSUSC + CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. + 0 + 15 + read-only + + + + + CTSURC + CTSU Reference Counter + 0x1A + 16 + read-only + 0x0000 + 0xFFFF + + + CTSURC + CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs. + 0 + 15 + read-only + + + + + CTSUERRS + CTSU Error Status Register + 0x1C + 16 + read-only + 0x0000 + 0xFFFF + + + CTSUICOMP + TSCAP Voltage Error Monitor + 15 + 15 + read-only + + + 0 + Normal TSCAP voltage + #0 + + + 1 + Abnormal TSCAP voltage + #1 + + + + + + + + + R_CTSU2 + Capacitive Touch Sensing Unit + 0x40082000 + + 0x00 + 12 + registers + + + 0x0C + 8 + registers + + + 0x14 + 8 + registers + + + 0x1C + 4 + registers + + + 0x20 + 8 + registers + + + 0x28 + 16 + registers + + + + CTSUCRA + CTSU Control Register A + 0x00 + 32 + read-write + 0x00000000 + 0xffffffff + + + STRT + CTSU Measurement Operation Start + 0 + 0 + read-write + + + 0 + Stop measurement operation + #0 + + + 1 + Start measurement operation + #1 + + + + + CAP + CTSU Measurement Operation Start Trigger Select + 1 + 1 + read-write + + + 0 + Software trigger + #0 + + + 1 + External trigger + #1 + + + + + SNZ + CTSU Wait State Power-Saving Enable + 2 + 2 + read-write + + + 0 + Disable power-saving function during wait state + #0 + + + 1 + Enable power-saving function during wait state + #1 + + + + + CFCON + CTSU CFC Power on Control + 3 + 3 + read-write + + + 0 + CFC power off + #0 + + + 1 + CFC power on + #1 + + + + + INIT + CTSU Control Block Initialization + 4 + 4 + write-only + + + PUMPON + CTSU Boost Circuit Control + 5 + 5 + read-write + + + 0 + Boost circuit off + #0 + + + 1 + Boost circuit on + #1 + + + + + TXVSEL + CTSU Transmission Power Supply Selection + 6 + 7 + read-write + + + 00 + VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method. + #00 + + + 01 + VCC is selected as the power supply for the transmit pins in self-capacitance method. + #01 + + + 10 + VCL is selected as the power-supply voltage for the transmit pins. + #10 + + + 11 + Setting prohibited + #11 + + + + + PON + CTSU Power Supply Enable + 8 + 8 + read-write + + + 0 + Power off the CTSU + #0 + + + 1 + Power on the CTSU + #1 + + + + + CSW + CTSU LPF Capacitance Charging Control + 9 + 9 + read-write + + + 0 + Turn off capacitance switch + #0 + + + 1 + Turn on capacitance switch + #1 + + + + + ATUNE0 + CTSU Power Supply Operating Mode Setting + 10 + 10 + read-write + + + 0 + VCC ≥ 2.4 V: Normal operating mode + VCC < 2.4 V: Setting prohibited + + #0 + + + 1 + Low-voltage operating mode + #1 + + + + + ATUNE1 + CTSU Current Range Adjustment + 11 + 11 + read-write + + + 0 + 40 µA when CTSUATUNE2 = 0 + 20 µA when CTSUATUNE2 = 1 + + #0 + + + 1 + 80 µA when CTSUATUNE2 = 0 + 160 µA when CTSUATUNE2 = 1 + + #1 + + + + + CLK + CTSU Operating Clock Select + 12 + 13 + read-write + + + 00 + PCLKB + #00 + + + 01 + PCLKB/2 (PCLKB divided by 2) + #01 + + + 10 + PCLKB/4 (PCLKB divided by 4) + #10 + + + 11 + PCLKB/8 (PCLKB divided by 8) + #11 + + + + + MD0 + CTSU Measurement Mode Select 0 + 14 + 14 + read-write + + + 0 + Single scan mode + #0 + + + 1 + Multi-scan mode + #1 + + + + + MD1 + CTSU Measurement Mode Select 1 + 15 + 15 + read-write + + + 0 + Single scan mode + #0 + + + 1 + Multi-scan mode + #1 + + + + + MD2 + CTSU Measurement Mode Select 2 + 16 + 16 + read-write + + + 0 + Measure the current that flows through the switched capacitor. + #0 + + + 1 + Measure the transfer charge in CFC circuit (high speed measurement) + #1 + + + + + ATUNE2 + CTSU Current Range Adjustment + 17 + 17 + read-write + + + 0 + 40 µA when CTSUATUNE1 = 0 + 80 µA when CTSUATUNE2 = 1 + + #0 + + + 1 + 20 µA when CTSUATUNE1 = 0 + 160 µA when CTSUATUNE2 = 1 + + #1 + + + + + LOAD + CTSU Measurement Load Control + 18 + 19 + read-write + + + 00 + Normal measurement mode + #00 + + + 01 + Load off mode + #01 + + + 10 + Current load mode + #10 + + + 11 + Resistance load mode + #11 + + + + + POSEL + CTSU Non-measured Channel Output Select + 20 + 21 + read-write + + + 00 + Output low through GPIO + #00 + + + 01 + Hi-Z + #01 + + + 10 + Output low through the power setting in the TXVSEL[1:0] bits + #10 + + + 11 + Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits + #11 + + + + + SDPSEL + CTSU Sensor Drive Pulse Select + 22 + 22 + read-write + + + 0 + Random pulse mode + #0 + + + 1 + High resolution pulse mode + #1 + + + + + FCMODE + CTSU SUCLK Control + 23 + 23 + read-write + + + 0 + SUCLK is used as frequency diffusion clock + #0 + + + 1 + SUCLK is used as recovery clock for multi-clock measurement + #1 + + + + + STCLK + CTSU STCLK Select + 24 + 29 + read-write + + + DCMODE + CTSU Current Measurement Mode Select + 30 + 30 + read-write + + + 0 + Normal mode + #0 + + + 1 + Current measurement mode + #1 + + + + + DCBACK + CTSU Current Measurement Feedback Select + 31 + 31 + read-write + + + 0 + TSCAP pin is selected + #0 + + + 1 + Measurement pin is selected + #1 + + + + + + + CTSUCRAL + CTSU Control Register A + CTSUCRA + 0x00 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCR0 + CTSU Control Register A + CTSUCRA + 0x00 + 8 + read-write + 0x00 + 0xff + + + CTSUCR1 + CTSU Control Register A + CTSUCRA + 0x01 + 8 + read-write + 0x00 + 0xff + + + CTSUCR2 + CTSU Control Register A + CTSUCRAH + 0x02 + 8 + read-write + 0x00 + 0xff + + + CTSUCR3 + CTSU Control Register A + CTSUCRA + 0x03 + 8 + read-write + 0x00 + 0xff + + + CTSUCRB + CTSU Control Register B + 0x04 + 32 + read-write + 0x00000000 + 0xffffffff + + + PRRATIO + CTSU Measurement Time and Pulse Count Adjustment + 0 + 3 + read-write + + + PRMODE + CTSU Base Period and Pulse Count Setting + 4 + 5 + read-write + + + 00 + 510 pulses (512 pulses when PROFF bit is 1) + #00 + + + 01 + 126 pulses (128 pulses when PROFF bit is 1) + #01 + + + 10 + 62 pulses (recommended setting) (64 pulses when PROFF bit is 1) + #10 + + + 11 + Setting prohibited + #11 + + + + + SOFF + CTSU High-Pass Noise Reduction Function Off Setting + 6 + 6 + read-write + + + 0 + Turn spectrum diffusion on. + #0 + + + 1 + Turn spectrum diffusion off. + #1 + + + + + PROFF + CTSU Random Number Off Control + 7 + 7 + read-write + + + 0 + There is random number control. + #0 + + + 1 + There is no random number control. + #1 + + + + + SST + CTSU Sensor Stabilization Wait Control + 8 + 15 + read-write + + + SSMOD + CTSU SUCLK Diffusion Mode Select + 24 + 26 + read-write + + + SSCNT + CTSU SUCLK Diffusion Control + 28 + 29 + read-write + + + + + CTSUCRBL + CTSU Control Register B + CTSUCRB + 0x04 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSDPRS + CTSU Control Register B + CTSUCRB + 0x04 + 8 + read-write + 0x00 + 0xff + + + CTSUSST + CTSU Control Register B + CTSUCRB + 0x05 + 8 + read-write + 0x00 + 0xff + + + CTSUCRBH + CTSU Control Register B + CTSUCRB + 0x06 + 16 + read-write + 0x0000 + 0xffff + + + CTSUDCLKC + CTSU Control Register B + CTSUCRB + 0x07 + 8 + read-write + 0x00 + 0xff + + + CTSUMCH + CTSU Measurement Channel Register + 0x08 + 32 + read-write + 0x00003f3f + 0xffffffff + + + MCH0 + CTSU Measurement Channel 0 + 0 + 5 + read-write + + + 0x00 + TS00 + 0x00 + + + 0x02 + TS02 + 0x02 + + + 0x04 + TS04 + 0x04 + + + 0x05 + TS05 + 0x05 + + + 0x06 + TS06 + 0x06 + + + 0x07 + TS07 + 0x07 + + + 0x08 + TS08 + 0x08 + + + 0x09 + TS09 + 0x09 + + + 0x0A + TS10 + 0x0a + + + 0x0B + TS11 + 0x0b + + + 0x0C + TS12 + 0x0c + + + 0x0D + TS13 + 0x0d + + + 0x0E + TS14 + 0x0e + + + 0x0F + TS15 + 0x0f + + + 0x10 + TS16 + 0x10 + + + 0x11 + TS17 + 0x11 + + + 0x12 + TS18 + 0x12 + + + 0x15 + TS21 + 0x15 + + + 0x16 + TS22 + 0x16 + + + 0x17 + TS23 + 0x17 + + + 0x18 + TS24 + 0x18 + + + 0x19 + TS25 + 0x19 + + + 0x1A + TS26 + 0x1a + + + 0x1B + TS27 + 0x1b + + + 0x1C + TS28 + 0x1c + + + 0x1D + TS29 + 0x1d + + + 0x1E + TS30 + 0x1e + + + 0x1F + TS31 + 0x1f + + + 0x20 + TS32 + 0x20 + + + 0x21 + TS33 + 0x21 + + + 0x22 + TS34 + 0x22 + + + 0x23 + TS35 + 0x23 + + + 0x3F + Measurement is being stopped. + 0x3f + + + + + MCH1 + CTSU Measurement Channel 1 + 8 + 13 + read-write + + + 0x00 + TS00 + 0x00 + + + 0x02 + TS02 + 0x02 + + + 0x04 + TS04 + 0x04 + + + 0x05 + TS05 + 0x05 + + + 0x06 + TS06 + 0x06 + + + 0x07 + TS07 + 0x07 + + + 0x08 + TS08 + 0x08 + + + 0x09 + TS09 + 0x09 + + + 0x0A + TS10 + 0x0a + + + 0x0B + TS11 + 0x0b + + + 0x0C + TS12 + 0x0c + + + 0x0D + TS13 + 0x0d + + + 0x0E + TS14 + 0x0e + + + 0x0F + TS15 + 0x0f + + + 0x10 + TS16 + 0x10 + + + 0x11 + TS17 + 0x11 + + + 0x12 + TS18 + 0x12 + + + 0x15 + TS21 + 0x15 + + + 0x16 + TS22 + 0x16 + + + 0x17 + TS23 + 0x17 + + + 0x18 + TS24 + 0x18 + + + 0x19 + TS25 + 0x19 + + + 0x1A + TS26 + 0x1a + + + 0x1B + TS27 + 0x1b + + + 0x1C + TS28 + 0x1c + + + 0x1D + TS29 + 0x1d + + + 0x1E + TS30 + 0x1e + + + 0x1F + TS31 + 0x1f + + + 0x20 + TS32 + 0x20 + + + 0x21 + TS33 + 0x21 + + + 0x22 + TS34 + 0x22 + + + 0x23 + TS35 + 0x23 + + + 0x3F + Measurement is being stopped. + 0x3f + + + + + MCA0 + CTSU Multiple Valid Clock Control + 16 + 16 + read-write + + + 0 + Valid + #0 + + + 1 + Invalid + #1 + + + + + MCA1 + CTSU Multiple Valid Clock Control + 17 + 17 + read-write + + + 0 + Valid + #0 + + + 1 + Invalid + #1 + + + + + MCA2 + CTSU Multiple Valid Clock Control + 18 + 18 + read-write + + + 0 + Valid + #0 + + + 1 + Invalid + #1 + + + + + MCA3 + CTSU Multiple Valid Clock Control + 19 + 19 + read-write + + + 0 + Valid + #0 + + + 1 + Invalid + #1 + + + + + + + CTSUMCHL + CTSU Measurement Channel Register + CTSUMCH + 0x08 + 16 + read-write + 0x0000 + 0xffff + + + CTSUMCH0 + CTSU Measurement Channel Register + CTSUMCH + 0x08 + 8 + read-write + 0x00 + 0xff + + + CTSUMCH1 + CTSU Measurement Channel Register + CTSUMCH + 0x09 + 8 + read-write + 0x00 + 0xff + + + CTSUMCHH + CTSU Measurement Channel Register + CTSUMCH + 0x0A + 16 + read-write + 0x3f3f + 0xffff + + + CTSUMFAF + CTSU Measurement Channel Register + CTSUMCHH + 0x0A + 8 + read-write + 0x3f + 0xff + + + CTSUCHACA + CTSU Channel Enable Control Register A + 0x0C + 32 + read-write + 0x00000000 + 0xffffffff + + + CHAC00 + CTSU Channel Enable Control A + 0 + 0 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC02 + CTSU Channel Enable Control A + 2 + 2 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC04 + CTSU Channel Enable Control A + 4 + 4 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC05 + CTSU Channel Enable Control A + 5 + 5 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC06 + CTSU Channel Enable Control A + 6 + 6 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC07 + CTSU Channel Enable Control A + 7 + 7 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC08 + CTSU Channel Enable Control A + 8 + 8 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC09 + CTSU Channel Enable Control A + 9 + 9 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC10 + CTSU Channel Enable Control A + 10 + 10 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC11 + CTSU Channel Enable Control A + 11 + 11 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC12 + CTSU Channel Enable Control A + 12 + 12 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC13 + CTSU Channel Enable Control A + 13 + 13 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC14 + CTSU Channel Enable Control A + 14 + 14 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC15 + CTSU Channel Enable Control A + 15 + 15 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC16 + CTSU Channel Enable Control A + 16 + 16 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC17 + CTSU Channel Enable Control A + 17 + 17 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC18 + CTSU Channel Enable Control A + 18 + 18 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC21 + CTSU Channel Enable Control A + 21 + 21 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC22 + CTSU Channel Enable Control A + 22 + 22 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC23 + CTSU Channel Enable Control A + 23 + 23 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC24 + CTSU Channel Enable Control A + 24 + 24 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC25 + CTSU Channel Enable Control A + 25 + 25 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC26 + CTSU Channel Enable Control A + 26 + 26 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC27 + CTSU Channel Enable Control A + 27 + 27 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC28 + CTSU Channel Enable Control A + 28 + 28 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC29 + CTSU Channel Enable Control A + 29 + 29 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC30 + CTSU Channel Enable Control A + 30 + 30 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC31 + CTSU Channel Enable Control A + 31 + 31 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + + + CTSUCHACAL + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0C + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHAC0 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0C + 8 + read-write + 0x00 + 0xff + + + CTSUCHAC1 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0D + 8 + read-write + 0x00 + 0xff + + + CTSUCHACAH + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0E + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHAC2 + CTSU Channel Enable Control Register A + CTSUCHACAH + 0x0E + 8 + read-write + 0x00 + 0xff + + + CTSUCHAC3 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0F + 8 + read-write + 0x00 + 0xff + + + CTSUCHACB + CTSU Channel Enable Control Register B + 0x10 + 32 + read-write + 0x00000000 + 0xffffffff + + + CHAC32 + CTSU Channel Enable Control B + 0 + 0 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC33 + CTSU Channel Enable Control B + 1 + 1 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC34 + CTSU Channel Enable Control B + 2 + 2 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC35 + CTSU Channel Enable Control B + 3 + 3 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + + + CTSUCHACBL + CTSU Channel Enable Control Register B + CTSUCHACB + 0x10 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHAC4 + CTSU Channel Enable Control Register B + CTSUCHACB + 0x10 + 8 + read-write + 0x00 + 0xff + + + CTSUCHTRCA + CTSU Channel Transmit/Receive Control Register A + 0x14 + 32 + read-write + 0x00000000 + 0xffffffff + + + CHTRC + CTSU Channel Transmit/Receive Control A + 0 + 0 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC02 + CTSU Channel Transmit/Receive Control A + 2 + 2 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC04 + CTSU Channel Transmit/Receive Control A + 4 + 4 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC05 + CTSU Channel Transmit/Receive Control A + 5 + 5 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC06 + CTSU Channel Transmit/Receive Control A + 6 + 6 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC07 + CTSU Channel Transmit/Receive Control A + 7 + 7 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC08 + CTSU Channel Transmit/Receive Control A + 8 + 8 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC09 + CTSU Channel Transmit/Receive Control A + 9 + 9 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC10 + CTSU Channel Transmit/Receive Control A + 10 + 10 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC11 + CTSU Channel Transmit/Receive Control A + 11 + 11 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC12 + CTSU Channel Transmit/Receive Control A + 12 + 12 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC13 + CTSU Channel Transmit/Receive Control A + 13 + 13 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC14 + CTSU Channel Transmit/Receive Control A + 14 + 14 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC15 + CTSU Channel Transmit/Receive Control A + 15 + 15 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC16 + CTSU Channel Transmit/Receive Control A + 16 + 16 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC17 + CTSU Channel Transmit/Receive Control A + 17 + 17 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC18 + CTSU Channel Transmit/Receive Control A + 18 + 18 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC21 + CTSU Channel Transmit/Receive Control A + 21 + 21 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC22 + CTSU Channel Transmit/Receive Control A + 22 + 22 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC23 + CTSU Channel Transmit/Receive Control A + 23 + 23 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC24 + CTSU Channel Transmit/Receive Control A + 24 + 24 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC25 + CTSU Channel Transmit/Receive Control A + 25 + 25 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC26 + CTSU Channel Transmit/Receive Control A + 26 + 26 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC27 + CTSU Channel Transmit/Receive Control A + 27 + 27 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC28 + CTSU Channel Transmit/Receive Control A + 28 + 28 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC29 + CTSU Channel Transmit/Receive Control A + 29 + 29 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC30 + CTSU Channel Transmit/Receive Control A + 30 + 30 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC31 + CTSU Channel Transmit/Receive Control A + 31 + 31 + read-write + + + 0 + Reception + #0 + + + 1 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#1 + + + + + CHTRC33 + CTSU Channel Transmit/Receive Control B + 1 + 1 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC34 + CTSU Channel Transmit/Receive Control B + 2 + 2 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + CHTRC35 + CTSU Channel Transmit/Receive Control B + 3 + 3 + read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + + + + + + CTSUCHTRCBL + CTSU Channel Transmit/Receive Control Register B + CTSUCHTRCB + 0x18 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHTRC4 + CTSU Channel Transmit/Receive Control Register B + CTSUCHTRCB + 0x18 + 8 + read-write + 0x00 + 0xff + + + CTSUSR + CTSU Status Register + 0x1C + 32 + read-write + 0x00000000 + 0xffffffff + + + MFC + CTSU Multi-clock Counter + 0 + 1 + read-write + + + 00 + Multi-clock 0 + #00 + + + 01 + Multi-clock 1 + #01 + + + 10 + Multi-clock 2 + #10 + + + 11 + Multi-clock 3 + #11 + + + + + ICOMPRST + CTSU CTSUICOMP1 Flag Reset + 5 + 5 + write-only + + + ICOMP1 + CTSU Sense Current Error Monitor + 6 + 6 + read-only + + + 0 + Normal sensor current + #0 + + + 1 + Abnormal sensor current + #1 + + + + + ICOMP0 + TSCAP Voltage Error Monitor + 7 + 7 + read-only + + + 0 + Normal TSCAP voltage + #0 + + + 1 + Abnormal TSCAP voltage + #1 + + + + + STC + CTSU Measurement Status Counter + 8 + 10 + read-only + + + 000 + Status 0 + #000 + + + 001 + Status 1 + #001 + + + 010 + Status 2 + #010 + + + 011 + Status 3 + #011 + + + 100 + Status 4 + #100 + + + 101 + Status 5 + #101 + + + + + DTSR + CTSU Data Transfer Status Flag + 12 + 12 + read-only + + + 0 + Read + #0 + + + 1 + Not read + #1 + + + + + SENSOVF + CTSU Sensor Counter Overflow Flag + 13 + 13 + read-write + + + 0 + No overflow occurred + #0 + + + 1 + Overflow occurred + #1 + + + + + PS + CTSU Mutual Capacitance Status Flag + 15 + 15 + read-only + + + 0 + First measurement + #0 + + + 1 + Second measurement + #1 + + + + + CFCRDCH + CTSU CFC Read Channel Select + 16 + 21 + read-write + + + 0x00 + TS00 + 0x00 + + + 0x02 + TS02 (CFC) + 0x02 + + + 0x04 + TS04 + 0x04 + + + 0x05 + TS05 + 0x05 + + + 0x06 + TS06 + 0x06 + + + 0x07 + TS07 + 0x07 + + + 0x08 + TS08 (CFC) + 0x08 + + + 0x09 + TS09 (CFC) + 0x09 + + + 0x0A + TS10 (CFC) + 0x0a + + + 0x0B + TS11 (CFC) + 0x0b + + + 0x0C + TS12 (CFC) + 0x0c + + + 0x0D + TS13 (CFC) + 0x0d + + + 0x0E + TS14 (CFC) + 0x0e + + + 0x0F + TS15 (CFC) + 0x0f + + + 0x10 + TS16 (CFC) + 0x10 + + + 0x11 + TS17 + 0x11 + + + 0x12 + TS18 + 0x12 + + + 0x15 + TS21 + 0x15 + + + 0x16 + TS22 + 0x16 + + + 0x17 + TS23 + 0x17 + + + 0x18 + TS24 + 0x18 + + + 0x19 + TS25 + 0x19 + + + 0x1A + TS26 (CFC) + 0x1a + + + 0x1B + TS27 (CFC) + 0x1b + + + 0x1C + TS28 (CFC) + 0x1c + + + 0x1D + TS29 (CFC) + 0x1d + + + 0x1E + TS30 (CFC) + 0x1e + + + 0x1F + TS31 (CFC) + 0x1f + + + 0x20 + TS32 (CFC) + 0x20 + + + 0x21 + TS33 (CFC) + 0x21 + + + 0x22 + TS34 (CFC) + 0x22 + + + 0x23 + TS35 (CFC) + 0x23 + + + + + + + CTSUSRL + CTSU Status Register + CTSUSR + 0x1C + 16 + read-write + 0x0000 + 0xffff + + + CTSUSR0 + CTSU Status Register + CTSUSR + 0x1C + 8 + read-write + 0x00 + 0xff + + + CTSUST + CTSU Status Register + CTSUSR + 0x1D + 8 + read-write + 0x00 + 0xff + + + CTSUSRH + CTSU Status Register + CTSUSR + 0x1E + 16 + read-write + 0x0000 + 0xffff + + + CTSUSR2 + CTSU Status Register + CTSUSRH + 0x1E + 8 + read-write + 0x00 + 0xff + + + CTSUSO + CTSU Sensor Offset Register + 0x20 + 32 + read-write + 0x00000000 + 0xffffffff + + + SO + CTSU Sensor Offset Adjustment + 0 + 9 + read-write + + + SNUM + CTSU Measurement Count Setting + 10 + 17 + read-write + + + SSDIV + CTSU Spectrum Diffusion Frequency Division Setting + 20 + 23 + read-write + + + SDPA + CTSU Base Clock Setting + 24 + 31 + read-write + + + + + CTSUSO0 + CTSU Sensor Offset Register + CTSUSO + 0x20 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSO1 + CTSU Sensor Offset Register + CTSUSO + 0x22 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSCNT + CTSU Sensor Counter Register + 0x24 + 32 + read-only + 0x00000000 + 0xffffffff + + + SENSCNT + CTSU Sensor Counter + 0 + 15 + read-only + + + + + CTSUSC + CTSU Sensor Counter Register + CTSUSCNT + 0x24 + 16 + read-only + 0x0000 + 0xffff + + + CTSUCALIB + CTSU Calibration Register + 0x28 + 32 + read-write + 0x00000000 + 0xffffffff + + + TSOD + CTSU TS Pins Fixed Output Select + 2 + 2 + read-write + + + 0 + Electrostatic capacitance measurement mode + #0 + + + 1 + TS pins fix output (High output/Low output). + #1 + + + + + DRV + CTSU Calibration Setting Bit 1 + 3 + 3 + read-write + + + 0 + Electrostatic capacitance measurement mode + #0 + + + 1 + Calibration setting 1 + #1 + + + + + SUCLKEN + CTSU SUCLK Enable Control + 6 + 6 + read-write + + + 0 + SUCLK operation is disabled. + #0 + + + 1 + SUCLK operation is enabled. + #1 + + + + + TSOC + CTSU Calibration Setting Bit 2 + 7 + 7 + read-write + + + 0 + Electrostatic capacitance measurement mode + #0 + + + 1 + Calibration setting 2 + #1 + + + + + IOC + CTSU Transfer Pins Control + 9 + 9 + read-write + + + 0 + Low level + #0 + + + 1 + High level + #1 + + + + + CFCRDMD + CTSU CFC Counter Read Mode Select + 10 + 10 + read-write + + + 0 + Read by DTC + #0 + + + 1 + Read by CPU + #1 + + + + + DCOFF + CTSU Down Converter Control + 11 + 11 + read-write + + + 0 + Normal operation mode + #0 + + + 1 + The down converter is off. + #1 + + + + + CFCMODE + CTSU CFC Current Source Switching + 22 + 22 + read-write + + + 0 + CFC current measurement (normal mode) + #0 + + + 1 + External current measurement for calibration + #1 + + + + + DACCARRY + CTSU DAC Upper Current Source Carry Control + 25 + 25 + read-write + + + 0 + Do not carry + #0 + + + 1 + Carry + #1 + + + + + SUCARRY + CTSU CCO Carry Control + 27 + 27 + read-write + + + 0 + Do not carry + #0 + + + 1 + Carry + #1 + + + + + DACCLK + CTSU DAC Modulation Circuit Clock Select + 28 + 28 + read-write + + + 0 + Divided PCLK specified by CTSUCRA.CLK[1:0] bits + #0 + + + 1 + SUCLK + #1 + + + + + CCOCLK + CTSU CCO Modulation Circuit Clock Select + 29 + 29 + read-write + + + 0 + Divided PCLK specified by CTSUCRA.CLK[1:0] bits + #0 + + + 1 + SUCLK + #1 + + + + + CCOCALIB + CTSU CCO Calibration Mode Select + 30 + 30 + read-write + + + 0 + Normal mode + #0 + + + 1 + Oscillator calibration mode + #1 + + + + + + + CTSUDBGR0 + CTSU Calibration Register + CTSUCALIB + 0x28 + 16 + read-write + 0x0000 + 0xffff + + + CTSUDBGR1 + CTSU Calibration Register + CTSUCALIB + 0x2A + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLKA + CTSU Sensor Unit Clock Control Register A + 0x2C + 32 + read-write + 0x00000000 + 0xffffffff + + + CTSUSUCLK0 + CTSU Sensor Unit Clock Control Register A + CTSUSUCLKA + 0x2C + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLK1 + CTSU Sensor Unit Clock Control Register A + CTSUSUCLKA + 0x2E + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLKB + CTSU Sensor Unit Clock Control Register B + 0x30 + 32 + read-write + 0x00000000 + 0xffffffff + + + SUADJ2 + CTSU SUCLK Frequency Adjustment + 0 + 7 + read-write + + + SUMULTI2 + CTSU SUCLK Multiplier Rate Setting + 8 + 15 + read-write + + + SUADJ3 + CTSU SUCLK Frequency Adjustment + 16 + 23 + read-write + + + SUMULTI3 + CTSU SUCLK Multiplier Rate Setting + 24 + 31 + read-write + + + + + CTSUSUCLK2 + CTSU Sensor Unit Clock Control Register B + CTSUSUCLKB + 0x30 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLK3 + CTSU Sensor Unit Clock Control Register B + CTSUSUCLKB + 0x32 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCFCCNT + CTSU CFC Counter Register + 0x34 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFCCNT + CTSU CFC Counter + 0 + 15 + read-only + + + + + CTSUCFCCNTL + CTSU CFC Counter Register + CTSUCFCCNT + 0x34 + 16 + read-only + 0x0000 + 0xffff + + + + + R_DAC + D/A Converter + 0x4005E000 + + 0x00000000 + 0x00A + registers + + + + DACR + D/A Control Register + 0x04 + 8 + read-write + 0x1F + 0xFF + + + DAE + D/A Enable + 5 + 5 + read-write + + + 0 + Control D/A conversion of channels 0 and 1 individually + #0 + + + + + 2 + 1 + DAOE%s + D/A Output Enable 0 + 6 + 6 + read-write + + + 0 + Analog output of channel 0 (DA0) is disabled. + #0 + + + 1 + D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. + #1 + + + + + + + 2 + 2 + DADR[%s] + D/A Data Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + DADR + D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. + 0 + 15 + read-write + + + + + DADPR + DADR0 Format Select Register + 0x05 + 8 + read-write + 0x00 + 0xFF + + + DPSEL + DADRm Format Select + 7 + 7 + read-write + + + 0 + Right justified format. + #0 + + + 1 + Left justified format. + #1 + + + + + + + DAADSCR + D/A-A/D Synchronous Start Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + + + DAADST + D/A-A/D Synchronous Conversion + 7 + 7 + read-write + + + 0 + D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). + #0 + + + 1 + D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). + #1 + + + + + + + DAVREFCR + D/A VREF Control Register + 0x07 + 8 + read-write + 0x00 + 0xFF + + + REF + D/A Reference Voltage Select + 0 + 2 + read-write + + + 000 + Not selected + #000 + + + 001 + AVCC0/AVSS0 + #001 + + + 011 + Internal reference voltage/AVSS0 + #011 + + + 110 + VREFH/VREFL + #110 + + + others + Setting prohibited + true + + + + + + + DAPC + D/A Switch Charge Pump Control Register + 0x09 + 8 + read-write + 0x00 + 0xFF + + + PUMPEN + Charge Pump Enable + 0 + 0 + read-write + + + 0 + Charge pump disabled + #0 + + + 1 + Charge pump enabled + #1 + + + + + + + DAAMPCR + D/A Output Amplifier Control Register + 0x08 + 8 + read-write + 0x1F + 0xFF + + + 2 + 1 + DAAMP%s + Amplifier Control + 6 + 6 + read-write + + + 0 + Do not use channel output amplifier + #0 + + + + + + + DAASWCR + D/A Amplifier Stabilization Wait Control Register + 0x1C + 8 + read-write + 0x00 + 0xFF + + + DAASW1 + Set the DAASW1 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 1. When DAASW1 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 1. When the DAASW1 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 1 is output through the output amplifier. + 7 + 7 + read-write + + + 0 + Amplifier stabilization wait off (output) for channel 1 + #0 + + + 1 + Amplifier stabilization wait on (high-Z) for channel 1 + #1 + + + + + DAASW0 + Set the DAASW0 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 0. When DAASW0 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 0. When the DAASW0 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 0 is output through the output amplifier. + 6 + 6 + read-write + + + 0 + Amplifier stabilization wait off (output) for channel 0 + #0 + + + 1 + Amplifier stabilization wait on (high-Z) for channel 0 + #1 + + + + + + + DAADUSR + D/A A/D Synchronous Unit Select Register + 0x10C0 + 8 + read-write + 0x00 + 0xFF + + + AMADSEL1 + The DAADUSR register selects the target ADC12 unit for D/A and A/D synchronous conversions. Set bit [1] to 1 to select unit 1 as the target synchronous unit for the MCU. When setting the DAADSCR.DAADST bit to 1 for synchronous conversions, select the target unit in this register in advance. Only set the DAADUSR register while the ADCSR.ADST bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit is set to 0. + 6 + 6 + read-write + + + 0 + Do not select unit 1 + #0 + + + 1 + Select unit 1 + #1 + + + + + + + + + R_DAC8 + 8-Bit D/A Converter + 0x4009E000 + + 0x00000000 + 0x002 + registers + + + 0x00000003 + 0x01 + registers + + + 0x00000006 + 0x002 + registers + + + + DAM + D/A Converter Mode Register + 0x03 + 8 + read-write + 0x00 + 0xFF + + + DACE1 + D/A operation enable 1 + 5 + 5 + read-write + + + 0 + D/A conversion disabled for channel 1 + #0 + + + 1 + D/A conversion enabled for channel 1 + #1 + + + + + DACE0 + D/A operation enable 0 + 4 + 4 + read-write + + + 0 + D/A conversion disabled for channel 0 + #0 + + + 1 + D/A conversion enabled for channel 0 + #1 + + + + + DAMD1 + D/A operation mode select 1 + 1 + 1 + read-write + + + 0 + Channel 1 for normal operation mode + #0 + + + 1 + Channel 1 for real-time output mode(event link) + #1 + + + + + DAMD0 + D/A operation mode select 0 + 0 + 0 + read-write + + + 0 + Channel 0 for normal operation mode + #0 + + + 1 + Channel 0 for real-time output mode(event link) + #1 + + + + + + + 2 + 0x01 + DACS[%s] + D/A Conversion Value Setting Register %s + 0x00 + 8 + read-write + 0x00 + 0xFF + + + DACS + DACS D/A conversion store data + 0 + 7 + read-write + + + + + DACADSCR + D/A A/D Synchronous Start Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + + + DACADST + D/A A/D Synchronous Conversion + 0 + 0 + read-write + + + 0 + Do not synchronize DAC8 with ADC16 operation (disable interference reduction between D/A and A/D conversion) + #0 + + + 1 + Synchronize DAC8 with ADC16 operation (enable interference reduction between D/A and A/D conversion). + #1 + + + + + + + DACPC + D/A SW Charge Pump Control Register + 0x07 + 8 + read-write + 0x00 + 0xFF + + + PUMPEN + Charge pump enable + 0 + 0 + read-write + + + 0 + Charge pump disable + #0 + + + 1 + Charge pump enable + #1 + + + + + + + + + R_DALI0 + Digital Addressable Lighting Interface + 0x4008F000 + + 0x00000000 + 0x018 + registers + + + 0x0000001E + 0x006 + registers + + + 0x00000026 + 0x004 + registers + + + 0x0000002E + 0x006 + registers + + + 0x00000036 + 0x02 + registers + + + 0x0000003A + 0x004 + registers + + + + BTVTHR1 + DALI Bit Timing Violation Threshold Register 1 + 0x000 + 16 + read-write + 0x4F00 + 0xFFFF + + + BTV2 + Bit Timing Violation Threshold 2Specifies the bit timing violation threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + + + BTV1 + Bit Timing Violation Threshold 1Specifies the bit timing violation threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + BTVTHR2 + DALI Bit Timing Violation Threshold Register 2 + 0x002 + 16 + read-write + 0x654F + 0xFFFF + + + BTV4 + Bit Timing Violation Threshold 4Specifies the bit timing violation threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + + + BTV3 + Bit Timing Violation Threshold 3Specifies the bit timing violation threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + BTVTHR3 + DALI Bit Timing Violation Threshold Register 3 + 0x004 + 16 + read-write + 0x009D + 0xFFFF + + + BTV5 + Bit Timing Violation Threshold 5Specifies the bit timing violation threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + BTVTHR4 + DALI Bit Timing Violation Threshold Register 4 + 0x006 + 16 + read-write + 0x00DB + 0xFFFF + + + BTV6 + Bit Timing Violation Threshold 6Specifies the bit timing violation threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 8 + read-write + + + + + COLTHR1 + DALI Collision Threshold Register 1 + 0x008 + 16 + read-write + 0x380F + 0xFFFF + + + COL2 + Collision Threshold 2Specifies the collision threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 13 + read-write + + + COL1 + Collision Threshold 1Specifies the collision threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 5 + read-write + + + + + COLTHR2 + DALI Collision Threshold Register 2 + 0x00A + 16 + read-write + 0x443C + 0xFFFF + + + COL4 + Collision Threshold 4Specifies the collision threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 14 + read-write + + + COL3 + Collision Threshold 3Specifies the collision threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + COLTHR3 + DALI Collision Threshold Register 3 + 0x00C + 16 + read-write + 0x7148 + 0xFFFF + + + COL6 + Collision Threshold 6Specifies the collision threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 14 + read-write + + + COL5 + Collision Threshold 5Specifies the collision threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + COLTHR4 + DALI Collision Threshold Register 4 + 0x00E + 16 + read-write + 0x8879 + 0xFFFF + + + COL8 + Collision Threshold 8Specifies the collision threshold value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + + + COL7 + Collision Threshold 7Specifies the collision threshold value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + COLTHR5 + DALI Collision Threshold Register 5 + 0x010 + 16 + read-write + 0x008E + 0xFFFF + + + COL9 + Collision Threshold 9Specifies the collision threshold value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + CNFR1 + DALI Configuration Register 1 + 0x012 + 16 + read-write + 0x00FF + 0xFFFF + + + CHL + Character Length + 12 + 14 + read-write + + + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 24 bits + #010 + + + 011 + 32 bits + #011 + + + 100 + 20 bits + #100 + + + 101 + 17 bits + #101 + + + others + Setting prohibited + true + + + + + CKS + Clock Select + 8 + 9 + read-write + + + 00 + PCLK clock (x = 0) + #00 + + + 01 + PCLK/4 clock (x = 1) + #01 + + + 10 + PCLK/16 clock (x = 2) + #10 + + + 11 + PCLK/64 clock (x = 3) + #11 + + + + + BR + Clock SelectBit rate setting example is shown in Table + 0 + 7 + read-write + + + + + CNFR2 + DALI Configuration Register 2 + 0x014 + 16 + read-write + 0x0000 + 0xFFFF + + + CDM0 + Collision Detect ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 5 + 5 + read-write + + + 0 + Destroy area + #0 + + + 1 + Destroy area and avoidance area (edge) + #1 + + + + + CDE + Collision Detect EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 4 + 4 + read-write + + + 0 + Collision detection is disabled. + #0 + + + 1 + Collision detection is enabled. + #1 + + + + + TXWE + DTX Width Modulation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 3 + 3 + read-write + + + 0 + The width of DTX0 waveform is not modulated. + #0 + + + 1 + The width of DTX0 waveform is modulated. + #1 + + + + + SGA + Save an Edge of Gray Area ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 2 + 2 + read-write + + + 0 + The edge allowable area of the DRX0 input signal is the default. + #0 + + + 1 + The edge allowable area of the DRX0 input signal is extended. + #1 + + + + + BTVM + Bit Timing Violation ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 1 + 1 + read-write + + + 0 + Edge in gray area between half bit and 2-half bit is not detected as bit timing violation. + #0 + + + 1 + Edge in gray area between half bit and 2-half bit is detected as bit timing violation. + #1 + + + + + BTVE + Bit Timing Violation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 0 + 0 + read-write + + + 0 + Bit timing violation function is disabled. + #0 + + + 1 + Bit timing violation function is enabled. + #1 + + + + + + + TXWR1 + DALI DTX Width Register 1 + 0x016 + 16 + read-write + 0x003F + 0xFFFF + + + TXLW + DTX Low WidthDTX0 pin low level width + 0 + 6 + read-write + + + + + TDR1H + DALI Transmit Data Register 1H + 0x01E + 16 + read-write + 0x0000 + 0xFFFF + + + DTDR + Upper 16-bit DALI transmit data + 0 + 15 + read-write + + + + + TDR1L + DALI Transmit Data Register 1L + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + DTDR + Lower 16-bit DALI transmit data + 0 + 15 + read-write + + + + + TRSTR1 + DALI Transmit Control Register 1 + SPDR + 0x022 + 16 + write-only + 0x0000 + 0xFFFF + + + TRST + Transmission Start Trigger + 0 + 0 + write-only + + + 0 + No effect + #0 + + + 1 + Transmission Start + #1 + + + + + + + CTR1 + DALI Control Register 1 + 0x026 + 16 + read-write + 0x0000 + 0xFFFF + + + FEIE + DALI_FEI Output Enabling + 12 + 12 + read-write + + + 0 + DALI_FEI output is disabled. + #0 + + + 1 + DALI_FEI output is enabled. + #1 + + + + + BPIE + DALI_BPI Output Enabling + 11 + 11 + read-write + + + 0 + DALI_BPI output is disabled. + #0 + + + 1 + DALI_BPI output is enabled. + #1 + + + + + CLIE + DALI_CLI Output Enabling + 10 + 10 + read-write + + + 0 + DALI_CLI output is disabled. + #0 + + + 1 + DALI_CLI output is enabled. + #1 + + + + + DEIE + DALI_DEI Output Enabling + 9 + 9 + read-write + + + 0 + DALI_DEI output is disabled. + #0 + + + 1 + DALI_DEI output is enabled. + #1 + + + + + SDIE + DALI_SDI Output Enabling + 8 + 8 + read-write + + + 0 + DALI_SDI output is disabled. + #0 + + + 1 + DALI_SDI output is enabled. + #1 + + + + + RE + Receive Enabling + 1 + 1 + read-write + + + 0 + Storing received data is disabled. + #0 + + + 1 + Storing received data is enabled. + #1 + + + + + TE + Transmit Enabling + 0 + 0 + read-write + + + 0 + Transmit operation is disabled. + #0 + + + 1 + Transmit operation is enabled. + #1 + + + + + + + TXDCTR1 + DALI DTX Control Register 1 + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + TXASE + DTX Assert EnablingNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. + 1 + 1 + read-write + + + 0 + An internal transmit data is output to the DTX0 pin. + #0 + + + 1 + The level specified by TXAS bit is output to the DTX0 pin. + #1 + + + + + TXAS + DTX Assert LevelNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. + 0 + 0 + read-write + + + 0 + The DTX0 pin is driven low. + #0 + + + 1 + The DTX0 pin is driven high. + #1 + + + + + + + RDR1H + DALI Reception Data Register 1H + 0x02E + 16 + read-only + 0x0000 + 0xFFFF + + + DRDR + Upper 16-bit of DALI receive data + 0 + 15 + read-only + + + + + RDR1L + DALI Reception Data Register 1L + 0x030 + 16 + read-only + 0x0000 + 0xFFFF + + + DRDR + Lower 16-bit of DALI receive data + 0 + 15 + read-only + + + + + STR1 + DALI Status Register 1 + 0x032 + 16 + read-only + 0x0000 + 0xFFFF + + + RDBL + Receive Data Bit LengthThese bits store the bit length for data received successfully + 10 + 15 + read-only + + + DAF + Destroy Area Flag + 9 + 9 + read-only + + + 0 + The collision did not occur in the destroy area or 1 was written to the DALI0.FECR1.DAFC bit. + #0 + + + 1 + The collision occurred in the destroy area. + #1 + + + + + CDF + Collision Detect Flag + 8 + 8 + read-only + + + 0 + No collision occurred or 1 was written to the DALI0.FECR1.CDFC bit. + #0 + + + 1 + A collision occurred. + #1 + + + + + O32F + Over 32-Bit Data Reception Flag + 7 + 7 + read-only + + + 0 + Receive data is 32 bits or less, or 1 was written to the DALI0.FECR1.O32FC bit. + #0 + + + 1 + Receive data is 33 bits or more. + #1 + + + + + BPDF + Bus Power Down Flag + 6 + 6 + read-only + + + 0 + No effected + #0 + + + 1 + Bus power down detected + #1 + + + + + BBF + Bus BUSY Flag + 5 + 5 + read-only + + + 0 + DALI bus is IDLE + #0 + + + 1 + DALI bus is BUSY + #1 + + + + + TENDF + Transmit End Flag + 4 + 4 + read-only + + + 0 + 1 was written to the DALI0.FECR1.TENDFC bit. + #0 + + + 1 + Frame transmission has been completed. + #1 + + + + + RDRF + Receive Data Register Full Flag + 3 + 3 + read-only + + + 0 + The DALI0.RDR1L register was read or 1 was written to the DALI0.FECR1.RDRFC. + #0 + + + 1 + Receive data is stored in the DALI0.RDR1L or DALI0.RDR1H register. + #1 + + + + + BTVF + Bit Timing Violation Flag + 2 + 2 + read-only + + + 0 + No bit timing violation occurred or 1 was written to the DALI0.FECR1.BTVFC bit. + #0 + + + 1 + Bit timing violation occurred + #1 + + + + + OVF + Overrun Error Flag + 1 + 1 + read-only + + + 0 + No overrun error occurred or 1 was written to the DALI0.FECR1.OVFC bit. + #0 + + + 1 + An overrun error occurred. + #1 + + + + + MFEF + Manchester Flaming Error Flag + 0 + 0 + read-only + + + 0 + No MFE occurred or 1 was written to the DALI0.FECR1.MFEFC bit. + #0 + + + 1 + An MFE occurred. + #1 + + + + + + + COLR1 + DALI Collision Register 1 + 0x036 + 16 + read-only + 0x0800 + 0xFFFF + + + TXDCV + DTX Collision Value + 13 + 13 + read-only + + + 0 + Low + #0 + + + 1 + High + #1 + + + + + RXDCEG + DRX Collision Edge + 12 + 12 + read-only + + + 0 + Falling edge + #0 + + + 1 + Rising edge + #1 + + + + + RXDMON + DRX MonitorThis bit monitors the DRX0 pin value after the DRX0 pin is synchronized + 11 + 11 + read-only + + + CLDAF + Collision Last Destroy Area Flag + 10 + 10 + read-only + + + 0 + Collision detected is caused by a DRX0 edge occurrence. + #0 + + + 1 + Collision detected is not caused by a DRX0 edge occurrence. (Last destroy area) + #1 + + + + + CDTF1 + Collision Detect Timing Flag 1 + 4 + 4 + read-only + + + 0 + Collision detection started at the edge on a bit period boundary. + #0 + + + 1 + Collision detection started at the edge in the middle of a bit period. + #1 + + + + + CFTF2 + Collision Detect Timing Flag 2 + 0 + 3 + read-only + + + 0000 + After reset is released + #0000 + + + 0001 + Collision detection timing 1 + #0001 + + + 0010 + Collision detection timing 2 + #0010 + + + 0011 + Collision detection timing 3 + #0011 + + + 0100 + Collision detection timing 4 + #0100 + + + 0101 + Collision detection timing 5 + #0101 + + + 0110 + Collision detection timing 6 + #0110 + + + 0111 + Collision detection timing 7 *1 + #0111 + + + 1000 + Collision detection timing 8 *1 + #1000 + + + 1001 + Collision detection timing 9 *1 + #1001 + + + 1010 + Collision detection timing 10 *1 + #1010 + + + others + Setting prohibited + true + + + + + + + FECR1 + DALI Flag Error Clear Register 1 + 0x03A + 16 + write-only + 0x0000 + 0xFFFF + + + DAFC + Destroy Area Flag Clear + 9 + 9 + write-only + + + 0 + DALI0.STR1.DAF bit is not cleared. + #0 + + + 1 + DALI0.STR1.DAF bit is cleared. + #1 + + + + + CDFC + Collision Detect Flag Clear + 8 + 8 + write-only + + + 0 + DALI0.STR1.CDF bit is not cleared. + #0 + + + 1 + DALI0.STR1.CDF bit is cleared. + #1 + + + + + O32FC + Over 32-Bit Data Reception Flag Clear + 7 + 7 + write-only + + + 0 + DALI0.STR1.O32F bit is not cleared. + #0 + + + 1 + DALI0.STR1.O32F bit is cleared + #1 + + + + + BPDFC + Bus Power Down Flag Clear + 6 + 6 + write-only + + + 0 + DALI0.STR1.BPDF bit is not cleared. + #0 + + + 1 + DALI0.STR1.BPDF bit is cleared. + #1 + + + + + BBFC + Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. + 5 + 5 + write-only + + + 0 + DALI0.STR1.BBF bit is not cleared. + #0 + + + 1 + DALI0.STR1.BBF bit is cleared + #1 + + + + + TENDFC + Transmit End Flag Clear + 4 + 4 + write-only + + + 0 + DALI0.STR1.TENDF bit is not cleared. + #0 + + + 1 + DALI0.STR1.TENDF bit is cleared + #1 + + + + + RDRFC + Receive Data Register Full Flag Clear + 3 + 3 + write-only + + + 0 + DALI0.STR1.RDRF bit is not cleared. + #0 + + + 1 + DALI0.STR1.RDRF bit is cleared. + #1 + + + + + BTVFC + Bit Timing Violation Flag Clear + 2 + 2 + write-only + + + 0 + DALI0.STR1.BTVF bit is not cleared. + #0 + + + 1 + DALI0.STR1.BTVF bit is cleared. + #1 + + + + + OVFC + Overrun Error Flag Clear + 1 + 1 + write-only + + + 0 + DALI0.STR1.OVF bit is not cleared. + #0 + + + 1 + DALI0.STR1.OVF bit is cleared + #1 + + + + + MFEFC + Manchester Flaming Error Flag Clear + 0 + 0 + write-only + + + 0 + DALI0.STR1.MFEF bit is not cleared. + #0 + + + 1 + DALI0.STR1.MFEF bit is cleared + #1 + + + + + + + SWRR1 + DALI Software Reset Register 1 + 0x03C + 16 + write-only + 0x0000 + 0xFFFF + + + SWR + Software ResetWriting 1 to this bit causes a software reset. + 0 + 0 + write-only + + + + + + + R_DEBUG + Debug Function + 0x4001B000 + + 0x00000000 + 0x04 + registers + + + 0x00000010 + 0x04 + registers + + + + DBGSTR + Debug Status Register + 0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + CDBGPWRUPREQ + Debug power-up request + 28 + 28 + read-only + + + 0 + 0: OCD is not requesting debug power up + #0 + + + 1 + 0: OCD is requesting debug power up + #1 + + + + + CDBGPWRUPACK + Debug power-up acknowledge + 29 + 29 + + + 0 + Debug power-up request is not acknowledged + #0 + + + 1 + Debug power-up request is acknowledged + #1 + + + + + + + DBGSTOPCR + Debug Stop Control Register + 0x10 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + + + DBGSTOP_RPER + Mask bit for SRAM parity error + 24 + 24 + + + 3 + 1 + DBGSTOP_LVD%s + Mask bit for LVD reset/interupt + 16 + 16 + read-write + + + 0 + Enable reset/interupt on corresponding LVD + #0 + + + 1 + Mask reset/interupt on corresponding LVD + #1 + + + + + DBGSTOP_RECCR + Mask bit for SRAM ECC error + 25 + 25 + + + DBGSTOP_IWDT + Mask bit for IWDT reset/interrupt + 0 + 0 + + + DBGSTOP_WDT + Mask bit for WDT reset/interrupt + 1 + 1 + + + + + + + R_DMA + DMA Controller Common + 0x40005200 + + 0x00000000 + 0x01 + registers + + + + DMAST + DMAC Module Activation Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + DMST + DMAC Operation Enable + 0 + 0 + read-write + + + 0 + Disabled. + #0 + + + 1 + Enabled. + #1 + + + + + + + + + R_DMAC0 + DMA Controller + 0x40005000 + + 0x00000000 + 0x00E + registers + + + 0x00000010 + 0x02 + registers + + + 0x00000013 + 0x003 + registers + + + 0x00000018 + 0x007 + registers + + + + DMSAR + DMA Source Address Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMSAR + Specifies the transfer source start address. + 0 + 31 + read-write + + + + + DMDAR + DMA Destination Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMDAR + Specifies the transfer destination start address. + 0 + 31 + read-write + + + + + DMCRA + DMA Transfer Count Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMCRAH + Upper bits of transfer count + 16 + 25 + read-write + + + DMCRAL + Lower bits of transfer count + 0 + 15 + read-write + + + + + DMCRB + DMA Block Transfer Count Register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DMCRB + Specifies the number of block transfer operations or repeat transfer operations. + 0 + 15 + read-write + + + 0000 + 65,536 blocks + #0000 + + + others + DMCRB blocks + true + + + + + + + DMTMD + DMA Transfer Mode Register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + + + MD + Transfer Mode Select + 14 + 15 + read-write + + + 00 + Normal transfer + #00 + + + 01 + Repeat transfer + #01 + + + 10 + Block transfer + #10 + + + 11 + Setting prohibited + #11 + + + + + DTS + Repeat Area Select + 12 + 13 + read-write + + + 00 + The destination is specified as the repeat area or block area. + #00 + + + 01 + The source is specified as the repeat area or block area. + #01 + + + 10 + The repeat area or block area is not specified. + #10 + + + 11 + Setting prohibited + #11 + + + + + SZ + Transfer Data Size Select + 8 + 9 + read-write + + + 00 + 8 bits + #00 + + + 01 + 16 bits + #01 + + + 10 + 32 bits + #10 + + + 11 + Setting prohibited + #11 + + + + + DCTG + Transfer Request Source Select + 0 + 1 + read-write + + + 00 + Software + #00 + + + 01 + Interrupts*1 from peripheral modules or external interrupt input pins + #01 + + + 10 + Setting prohibited + #10 + + + 11 + Setting prohibited + #11 + + + + + + + DMINT + DMA Interrupt Setting Register + 0x13 + 8 + read-write + 0x00 + 0xFF + + + DTIE + Transfer End Interrupt Enable + 4 + 4 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + ESIE + Transfer Escape End Interrupt Enable + 3 + 3 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + RPTIE + Repeat Size End Interrupt Enable + 2 + 2 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + SARIE + Source Address Extended Repeat Area Overflow Interrupt Enable + 1 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + DARIE + Destination Address Extended Repeat Area Overflow Interrupt Enable + 0 + 0 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + DMAMD + DMA Address Mode Register + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + SM + Source Address Update Mode + 14 + 15 + read-write + + + 00 + Fixed address + #00 + + + 01 + Offset addition + #01 + + + 10 + Incremented address + #10 + + + 11 + Decremented address. + #11 + + + + + SARA + Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. + 8 + 12 + read-write + + + DM + Destination Address Update Mode + 6 + 7 + read-write + + + 00 + Fixed address + #00 + + + 01 + Offset addition + #01 + + + 10 + Incremented address + #10 + + + 11 + Decremented address. + #11 + + + + + DARA + Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. + 0 + 4 + read-write + + + + + DMOFR + DMA Offset Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMOFR + Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. + 0 + 31 + read-write + + + + + DMCNT + DMA Transfer Enable Register + 0x1C + 8 + read-write + 0x00 + 0xFF + + + DTE + DMA Transfer Enable + 0 + 0 + read-write + modify + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + + + DMREQ + DMA Software Start Register + 0x1D + 8 + read-write + 0x00 + 0xFF + + + CLRS + DMA Software Start Bit Auto Clear Select + 4 + 4 + read-write + + + 0 + SWREQ bit is cleared after DMA transfer is started by software. + #0 + + + 1 + SWREQ bit is not cleared after DMA transfer is started by software. + #1 + + + + + SWREQ + DMA Software Start + 0 + 0 + read-write + modify + + + 0 + DMA transfer is not requested. + #0 + + + 1 + DMA transfer is requested. + #1 + + + + + + + DMSTS + DMA Status Register + 0x1E + 8 + read-write + 0x00 + 0xFF + + + ACT + DMA Active Flag + 7 + 7 + read-only + + + 0 + DMAC operation suspended + #0 + + + 1 + DMAC operating. + #1 + + + + + DTIF + Transfer End Interrupt Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No interrupt + #0 + + + 1 + Interrupt occurred. + #1 + + + + + ESIF + Transfer Escape End Interrupt Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No interrupt + #0 + + + 1 + Interrupt occurred. + #1 + + + + + + + + + R_DMAC1 + 0x40005040 + + + R_DMAC2 + 0x40005080 + + + R_DMAC3 + 0x400050C0 + + + R_DMAC4 + 0x40005100 + + + R_DMAC5 + 0x40005140 + + + R_DMAC6 + 0x40005180 + + + R_DMAC7 + 0x400051C0 + + + R_DOC + Data Operation Circuit + 0x40054100 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x004 + registers + + + + DOCR + DOC Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + DOPCFCL + DOPCF Clear + 6 + 6 + read-write + + + 0 + Maintains the DOPCF flag state. + #0 + + + 1 + Clears the DOPCF flag. + #1 + + + + + DOPCF + Data Operation Circuit Flag + 5 + 5 + read-only + + + DCSEL + Detection Condition Select + 2 + 2 + read-write + + + 0 + DOPCF is set when data mismatch is detected. + #0 + + + 1 + DOPCF is set when data match is detected. + #1 + + + + + OMS + Operating Mode Select + 0 + 1 + read-write + + + 00 + Data comparison mode + #00 + + + 01 + Data addition mode + #01 + + + 10 + Data subtraction mode + #10 + + + 11 + Setting prohibited + #11 + + + + + + + DODIR + DOC Data Input Register + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + DODIR + 16-bit read-write register in which 16-bit data for use in the operations are stored. + 0 + 15 + read-write + + + + + DODSR + DOC Data Setting Register + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + DODSR + This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. + 0 + 15 + read-write + + + + + + + R_DRW + 2D Drawing Engine + 0x400E4000 + + 0x00000000 + 0x008 + registers + + + 0x00000010 + 0x050 + registers + + + 0x00000064 + 0x008 + registers + + + 0x00000074 + 0x010 + registers + + + 0x00000090 + 0x020 + registers + + + 0x000000B4 + 0x024 + registers + + + 0x000000DC + 0x010 + registers + + + + CONTROL + Geometry Control Register + 0x00 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SPANSTORE + Nextline span start is always equal or left to current-line span start + 23 + 23 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + SPANABORT + Shape is horizontally convex, only a single span per scanline + 22 + 22 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + UNIONCD + Combine outputs C & D as union (output is final) + 21 + 21 + write-only + + + 0 + minimum/intersect + #0 + + + 1 + maximum/union + #1 + + + + + UNIONAB + Combine outputs A & B as union (output is called C) + 20 + 20 + write-only + + + 0 + minimum/intersect + #0 + + + 1 + maximum/union + #1 + + + + + UNION56 + Combine limter 5 & 6 as union (output is called D) + 19 + 19 + write-only + + + 0 + minimum/intersect + #0 + + + 1 + maximum/union + #1 + + + + + UNION34 + Combine limter 3 & 4 as union (output is called B) + 18 + 18 + write-only + + + 0 + minimum/intersect + #0 + + + 1 + maximum/union + #1 + + + + + UNION12 + Combine limter 1 & 2 as union (output is called A) + 17 + 17 + write-only + + + 0 + minimum/intersect + #0 + + + 1 + maximum/union + #1 + + + + + BAND2ENABLE + Enable band postprocess for limiter 1 (see L1BAND) + 16 + 16 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + BAND1ENABLE + Enable band postprocess for limiter 1 (see L1BAND) + 15 + 15 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM6THRESHOLD + Enable limiter 6 threshold mode + 14 + 14 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM5THRESHOLD + Enable limiter 5 threshold mode + 13 + 13 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM4THRESHOLD + Enable limiter 4 threshold mode + 12 + 12 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM3THRESHOLD + Enable limiter 3 threshold mode + 11 + 11 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM2THRESHOLD + Enable limiter 2 threshold mode + 10 + 10 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM1THRESHOLD + Enable limiter 1 threshold mode + 9 + 9 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + QUAD3ENABLE + Enable quadratic coupling of limiters 5 and 6 + 8 + 8 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + QUAD2ENABLE + Enable quadratic coupling of limiters 3 and 4 + 7 + 7 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + QUAD1ENABLE + Enable quadratic coupling of limiters 1 and 2 + 6 + 6 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM6ENABLE + Enable limiter 6 + 5 + 5 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM5ENABLE + Enable limiter 5 + 4 + 4 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM4ENABLE + Enable limiter 4 + 3 + 3 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM3ENABLE + Enable limiter 3 + 2 + 2 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM2ENABLE + Enable limiter 2 + 1 + 1 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + LIM1ENABLE + Enable limiter 1 + 0 + 0 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + + + CONTROL2 + Surface Control Register + 0x04 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + RLEPIXELWIDTH + Texel width for RLE unit + 30 + 31 + write-only + + + 00 + 1 byte per texel + #00 + + + 01 + 2 byte per texel + #01 + + + 10 + 3 byte per texel + #10 + + + 11 + 4 byte per texel + #11 + + + + + BDIA + Blend destination factor inverted in alpha channel (USEACB = 1) + 29 + 29 + write-only + + + 0 + use blend factor as specified through BDFA + #0 + + + 1 + invert blend destination factor (1-x) + #1 + + + + + BSIA + Blend source factor inverted in alpha channel (USEACB = 1) + 28 + 28 + write-only + + + 0 + use blend factor as specified through BSFA + #0 + + + 1 + invert blend source factor (1-x) + #1 + + + + + CLUTFORMAT + Format of the CLUT + 27 + 27 + write-only + + + 0 + aRGB(8888) + #0 + + + 1 + RGB(565) + #1 + + + + + COLKEYENABLE + color keying enable + 26 + 26 + write-only + + + 0 + color keying disabled + #0 + + + 1 + color keying enabled + #1 + + + + + CLUTENABLE + CLUT enable + 25 + 25 + write-only + + + 0 + CLUT disabled + #0 + + + 1 + CLUT enabled + #1 + + + + + RLEENABLE + RLE enable + 24 + 24 + write-only + + + 0 + RLE disabled + #0 + + + 1 + RLE enabled + #1 + + + + + WRITEALPHA + Writeback alpha source for framebufferSet the 'alpha source' for the framebuffer(USEACB = 0)Blend alpha in color 2 instead of framebuffer alpha((USEACB = 1))In not alpha channel blending mode (USEACB = 0):Set the 'alpha source' for the framebuffer.In alpha channel blending mode (USEACB = 1):Blend alpha in color 2 instead of framebuffer alpha00B: BC2A = 1: use alpha from framebuffer as destination (DST_A)else: BC2A = 0: use alpha in color 2 as destination (DST_A) + 22 + 23 + write-only + + + 00 + use alpha from color 2 + #00 + + + 01 + use source alpha (pixel coverage) + #01 + + + 10 + use 0.0 as alpha + #10 + + + 11 + use alpha from framebuffer + #11 + + + + + WRITEFORMAT10 + Pixel format of the framebuffer + 20 + 21 + write-only + + + 00 + 8bpp a(8)0 + #00 + + + 01 + 16bpp RGB(565) + #01 + + + 10 + 32bpp aRGB(8888) + #10 + + + 11 + 16bpp aRGB(4444) + #11 + + + + + READFORMAT10 + Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance + 18 + 19 + write-only + + + 00 + 8 bpp a(8) (READFORMAT32=00) / 16 bpp aRGB(1555) (READFORMAT32=01) / 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance (READFORMAT32=11) + #00 + + + 01 + 16 bpp RGB(565) (READFORMAT32=00) / 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color (READFORMAT32=01) / 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance (READFORMAT32=10) + #01 + + + 10 + 32 bpp aRGB(8888) (READFORMAT32=00) / 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance (READFORMAT32=10) + #10 + + + 11 + 16 bpp aRGB(4444) (READFORMAT32=00) / 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance (READFORMAT32=10) + #11 + + + + + TEXTUREFILTERY + Linear filtering on texture V axis + 17 + 17 + write-only + + + 0 + no filtering on texture V axis + #0 + + + 1 + linear filtering on texture V axis + #1 + + + + + TEXTUREFILTERX + Linear filtering on texture U axis + 16 + 16 + write-only + + + 0 + no filtering on texture U axis + #0 + + + 1 + linear filtering on texture U axis + #1 + + + + + TEXTURECLAMPY + Calculating V limiter outside use textureThe bit describes what happens if the V limiter (y direction in texture space) calculates a V value outside of the used texture + 15 + 15 + write-only + + + 0 + Texture wrap mode: The integer part of the calculated value from the v limiter is anded with TEXVMASK. This results in a repetition of the texture in y/v direction. + #0 + + + 1 + Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in y/v direction. + #1 + + + + + TEXTURECLAMPX + Calculating U limiter outside use textureThe bit describes what happens if the U limiter (x direction in texture space) calculates a U value outside of the used texture + 14 + 14 + write-only + + + 0 + Texture wrap mode: The integer part of the calculated value from the u limiter is anded with TEXUMASK. This results in a repetition of the texture in x/u direction. + #0 + + + 1 + Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in x/u direction. + #1 + + + + + BC2 + Blend color 2 instead of framebuffer pixel + 13 + 13 + write-only + + + 0 + use pixel from framebuffer as destination (DST) + #0 + + + 1 + use color 2 as destination (DST) + #1 + + + + + BDI + Blend destination factor is inverteddst factor will be inverted (meaning 1-a or 1-1 depending on BDF) + 12 + 12 + write-only + + + 0 + use blend factor as specified through BDF + #0 + + + 1 + invert blend destinationfactor (1-x) + #1 + + + + + BSI + Blend source factor is invertedsrc factor will be inverted (meaning 1-a or 1-1 depending on BSF) + 11 + 11 + write-only + + + 0 + use blend factor as specified through BSF + #0 + + + 1 + invert blend source factor (1-x) + #1 + + + + + BDF + Blend destination factordst factor is alpha (factor is 1 per default) + 10 + 10 + write-only + + + 0 + use 1.0 as blend destination factor + #0 + + + 1 + use alpha as blend destination factor + #1 + + + + + BSF + Blend source factorsrc factor is alpha (factor is 1 per default) + 9 + 9 + write-only + + + 0 + use 1.0 as blend source factor + #0 + + + 1 + use alpha as blend source factor + #1 + + + + + WRITEFORMAT2 + Bit 3 of framebuffer pixel formatSee WRITEFORMAT above description. + 8 + 8 + write-only + + + BDFA + Blend destinetion factor for alpha channel in alpha channel blending mode (USEACB = 1) + 7 + 7 + write-only + + + 0 + use 1.0 as blend destination factor for alpha channel + #0 + + + 1 + use alpha as blend destination factor for alpha channel + #1 + + + + + BSFA + Blend source factor for alpha channel in alpha channel blending mode (USEACB = 1) + 6 + 6 + write-only + + + 0 + use 1.0 as blend source factor for alpha channel + #0 + + + 1 + use alpha as blend source factor for alpha channel + #1 + + + + + READFORMAT32 + Bit 4 and 3 of the texture buffer format.See READFORMAT above for description + 4 + 5 + write-only + + + USEACB + Alpha blend mode + 3 + 3 + write-only + + + 0 + use WRITEALPHA[1:0] mode + #0 + + + 1 + use full alpha channel blending mode + #1 + + + + + PATTERNSOURCEL5 + Limiter 5 is used as pattern index instead of the default U limiter.Limiter 5 can be combined with limiter 6 to form a quadratic limiter which can be used to make quadratic pattern functions to draw radial patterns. + 2 + 2 + write-only + + + TEXTUREENABLE + Pixel source is read from texture and used as an alpha to blend between COLOR1 and COLOR2 + 1 + 1 + write-only + + + 0 + disabled texture + #0 + + + 1 + enabled texture + #1 + + + + + PATTERNENABLE + Pixel source is a pattern color (blend of COLOR1 and COLOR2 depending on PATTERN and pattern index) + 0 + 0 + write-only + + + 0 + disabled pattern + #0 + + + 1 + enabled pattern + #1 + + + + + + + IRQCTL + Interrupt Control Register + 0xC0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + BUSIRQCLR + Clear bus error interrupt BUSIRQ + 5 + 5 + write-only + + + 0 + no BUSIRQCLR clear + #0 + + + 1 + clear BUSIRQCLR + #1 + + + + + BUSIRQEN + BUSIRQ interrupt mask enable + 4 + 4 + write-only + + + 0 + disable (mask) BUSIRQ + #0 + + + 1 + enable (unmask) BUSIRQ + #1 + + + + + DLISTIRQCLR + Clear display list interrupt DLISTIRQ + 3 + 3 + write-only + + + 0 + no DLISTRQCLR clear + #0 + + + 1 + clear DLISTRQCLR + #1 + + + + + ENUMIRQCLR + Clear enumeration interrupt ENUMIRQ + 2 + 2 + write-only + + + 0 + no ENUMIRQCLR clear + #0 + + + 1 + clear ENUMIRQCLR + #1 + + + + + DLISTIRQEN + DLISTIRQ interrupt mask enable + 1 + 1 + write-only + + + 0 + disable (mask) DLISTIRQ + #0 + + + 1 + enable (unmask) DLISTIRQ + #1 + + + + + ENUMIRQEN + ENUMIRQ interrupt mask enable + 0 + 0 + write-only + + + 0 + disable (mask) ENUMIRQ + #0 + + + 1 + enable (unmask) ENUMIRQ + #1 + + + + + + + CACHECTL + Cache Control Register + 0xC4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + CFLUSHTX + Flush texture cache + 3 + 3 + write-only + + + 0 + do not flush the texture cache + #0 + + + 1 + flush the texture cache + #1 + + + + + CENABLETX + Texture cache enable + 2 + 2 + write-only + + + 0 + disable the texture cache + #0 + + + 1 + enable the texture cache + #1 + + + + + CFLUSHFX + Flush framebuffer cache + 1 + 1 + write-only + + + 0 + do not flush the framebuffer cache + #0 + + + 1 + flush the framebuffer cache + #1 + + + + + CENABLEFX + Framebuffer cache enable + 0 + 0 + write-only + + + 0 + disable the framebuffer cache + #0 + + + 1 + enable the framebuffer cache + #1 + + + + + + + STATUS + Status Control Register + CONTROL + 0x00 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + BUSERRMDL + display list bus error interrupt triggered + 10 + 10 + read-only + + + 0 + no display list bus error occurred or interrupt disabled + #0 + + + 1 + display list bus error interrupt triggered + #1 + + + + + BUSERRMTXMRL + texture bus error interrupt triggered + 9 + 9 + read-only + + + 0 + no texture bus error occurred or interrupt disabled + #0 + + + 1 + texture bus error interrupt triggered + #1 + + + + + BUSERRMFB + framebuffer bus error interrupt triggered + 8 + 8 + read-only + + + 0 + no framebuffer bus error occured or interrupt disabled + #0 + + + 1 + framebuffer bus error interrupt triggered + #1 + + + + + BUSIRQ + bus error interrupt triggered + 6 + 6 + read-only + + + 0 + no bus error occurred or interrupt disabled + #0 + + + 1 + bus error interrupt triggered + #1 + + + + + DLISTIRQ + display list finished interrupt triggered + 5 + 5 + read-only + + + 0 + display list not finished or interrupt disabled + #0 + + + 1 + display list finished interrupt triggered + #1 + + + + + ENUMIRQ + enumeration finished interrupt triggered + 4 + 4 + read-only + + + 0 + enumeration not finished or interrupt disabled + #0 + + + 1 + enumeration finished interrupt triggered + #1 + + + + + DLISTACTIVE + Display list reader status + 3 + 3 + read-only + + + 0 + display list reader is idle + #0 + + + 1 + display list reader busy, no direct write access to registers allowed + #1 + + + + + CACHEDIRTY + Framebuffer cache status + 2 + 2 + read-only + + + 0 + framebuffer cache is not dirty + #0 + + + 1 + framebuffer cache is dirty, frame should not be flipped + #1 + + + + + BUSYWRITE + Framebuffer writeback status + 1 + 1 + read-only + + + 0 + framebuffer writeback finished + #0 + + + 1 + framebuffer writeback busy, framebuffer type can not be changed + #1 + + + + + BUSYENUM + Enumeration unit status + 0 + 0 + read-only + + + 0 + enumeration unit idle + #0 + + + 1 + enumeration unit busy, new primitive can not be started + #1 + + + + + + + HWREVISION + Hardware Version and Feature Set ID Register + CONTROL2 + 0x04 + 32 + read-only + 0x0FBE0107 + 0xFFFFFFFF + + + ACBLEND + Alpha channel blending feature + 27 + 27 + read-only + + + 0 + Alpha channel blending unavailable + #0 + + + 1 + Alpha channel blending available + #1 + + + + + COLORKEY + Colorkey feature + 25 + 25 + read-only + + + 0 + Colorkey unavailable + #0 + + + 1 + Colorkey available + #1 + + + + + TEXCLUT256 + Texture CLUT feature + 24 + 24 + read-only + + + 0 + Texture CLUT unavailable + #0 + + + 1 + Texture CLUT available + #1 + + + + + RLEUNIT + RLE unit feature + 23 + 23 + read-only + + + 0 + RLE unit unavailable + #0 + + + 1 + RLE unit available + #1 + + + + + TEXCLU + Texture CLUT with 16 or 256 entries feature + 21 + 21 + read-only + + + 0 + Texture CLUT with 16 or 256 entries unavailable + #0 + + + 1 + Texture CLUT with 16 or 256 entries available + #1 + + + + + PERFCOUNT + Two performance counter feature + 20 + 20 + read-only + + + 0 + Two performance counter unavailable + #0 + + + 1 + Two performance counter available + #1 + + + + + TXCACHE + Texture cache feature + 19 + 19 + read-only + + + 0 + Texture cache unavailable + #0 + + + 1 + Texture cache available + #1 + + + + + FBCACHE + Framebuffer cache feature + 18 + 18 + read-only + + + 0 + Framebuffer cache unavailable + #0 + + + 1 + Framebuffer cache available + #1 + + + + + DLR + Display list reader feature + 17 + 17 + read-only + + + 0 + Display list reader unavailable + #0 + + + 1 + Display list reader available + #1 + + + + + REV + Revision number + 0 + 11 + read-only + + + + + COLOR1 + Base Color Register + 0x64 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + COLOR1A + Alpha channel of color 1(0x00: transparent. . . 0xFF: opaque) + 24 + 31 + write-only + + + COLOR1R + Red channel of color 1 + 16 + 23 + write-only + + + COLOR1G + Green channel of color 1 + 8 + 15 + write-only + + + COLOR1B + Blue channel of color 1 + 0 + 7 + write-only + + + + + COLOR2 + Secondary Color Register + 0x68 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + COLOR2A + Alpha channel of color 2(0x00: transparent. . . 0xFF: opaque) + 24 + 31 + write-only + + + COLOR2R + Red channel of color 2 + 16 + 23 + write-only + + + COLOR2G + Green channel of color 2 + 8 + 15 + write-only + + + COLOR2B + Blue channel of color 2 + 0 + 7 + write-only + + + + + PATTERN + Pattern Register + 0x74 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + PATTERN + Bitmap of the pattern + 0 + 7 + write-only + + + + + 6 + 0x4 + 1-6 + L%sSTART + Limiter %s Start Value Register + 0x10 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LSTART + Start value of the n'th limiter(n=1-6) + 0 + 31 + write-only + + + + + 6 + 0x4 + 1-6 + L%sXADD + Limiter %s X-Axis Increment Register + 0x28 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LXADD + X-axis increment + 0 + 31 + write-only + + + + + 6 + 0x4 + 1-6 + L%sYADD + Limiter %s Y-Axis Increment Register + 0x40 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LYADD + Y-axis increment + 0 + 31 + write-only + + + + + 2 + 0x4 + 1,2 + L%sBAND + Limiter %s Band Width Parameter Register + 0x58 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LBAND + Limiter m band width parameter + 0 + 31 + write-only + + + + + TEXORIGIN + Texture Base Address Register + 0xBC + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXORIGIN + Texture base address + 0 + 31 + write-only + + + + + TEXPITCH + Texels Per Texture Line Register + 0xB4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXPITCH + Texels per texture linevalid range: 0 to 2048 + 0 + 31 + write-only + + + + + TEXMASK + Texture Size or Texture Address Mask Register + 0xB8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXVMASK + V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = 0): texture_height must be a power of 2In texture clamping mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 are allowed. + 11 + 31 + write-only + + + TEXUMASK + U maskSet TEXUMASK[10:0] = texture_width -1In texture wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX = 1):all widths up to 2048 are allowed. + 0 + 10 + write-only + + + + + LUSTART + U Limiter Start Value Register + 0x90 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LUSTART + U limiter start value + 0 + 31 + write-only + + + + + LUXADD + U Limiter X-Axis Increment Register + 0x94 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LUXADD + U limiter x-axis increment + 0 + 31 + write-only + + + + + LUYADD + U Limiter Y-Axis Increment Register + 0x98 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LUYADD + U limiter y-axis increment + 0 + 31 + write-only + + + + + LVSTARTI + V Limiter Start Value Integer Part Register + 0x9C + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LVSTARTI + V limiter start value integer part + 0 + 31 + write-only + + + + + LVSTARTF + V Limiter Start Value Fractional Part Register + 0xA0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LVSTARTF + V limiter start value fractional part + 0 + 15 + write-only + + + + + LVXADDI + V Limiter X-Axis Increment Integer Part Register + 0xA4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LVXADDI + V limiter x-axis increment integer part + 0 + 31 + write-only + + + + + LVYADDI + V Limiter Y-Axis Increment Integer Part Register + 0xA8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LVYADDI + V limiter y-axis increment integer part + 0 + 31 + write-only + + + + + LVYXADDF + V Limiter Increment Fractional Parts Register + 0xAC + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LVYADDF + V y limiter increment fractional part + 16 + 31 + write-only + + + LVXADDF + V xlimiter increment fractional part + 0 + 15 + write-only + + + + + TEXCLADDR + CLUT Start Address Register + 0xDC + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLADDR + Texture CLUT start address for indexed texture format + 0 + 7 + write-only + + + + + TEXCLDATA + CLUT Data Register + 0xE0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLDATA + Texture CLUT data for Indexed texture format + 0 + 31 + write-only + + + + + TEXCLOFFSET + CLUT Offset Register + 0xE4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + CLOFFSET + Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] is or'ed with the original index + 0 + 7 + write-only + + + + + COLKEY + Color Key Register + 0xE8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + COLKEYR + Red channel of color key + 16 + 23 + write-only + + + COLKEYG + Green channel of color key + 8 + 15 + write-only + + + COLKEYB + Blue channel of color key + 0 + 7 + write-only + + + + + SIZE + Bounding Box Dimension Register + 0x78 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SIZEY + Height of the bounding box in pixelsvalid range: 0 to 1024 + 16 + 31 + write-only + + + SIZEX + Width of the bounding box in pixelsvalid range: 0 to 1024 + 0 + 15 + write-only + + + + + PITCH + Framebuffer Pitch And Spanstore Delay Register + 0x7C + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SSD + Spanstore delay + 16 + 31 + write-only + + + PITCH + pitch of the framebuffer. A negative width can be used to render bottom-up instead of top-down + 0 + 15 + write-only + + + + + ORIGIN + Framebuffer Base Address Register + 0x80 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + ORIGIN + Address of the first pixel in framebuffer + 0 + 31 + write-only + + + + + DLISTSTART + Display List Start Address Register + 0xC8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + DLISTSTART + Display list start address + 0 + 31 + write-only + + + + + PERFTRIGGER + Performance Counters Control Register + 0xD4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + PERFTRIGGER2 + Selects the internal event that will increment PERFCOUNT2 register + 16 + 31 + write-only + + + 0x00 + disable performance counter + 0x00 + + + 0x01 + 2D Drawing Engine active cycles + 0x01 + + + 0x02 + framebuffer read access + 0x02 + + + 0x03 + framebuffer write access + 0x03 + + + 0x04 + texture read access + 0x04 + + + 0x05 + invisible pixels (enumerated but selected with alpha 0percent) + 0x05 + + + 0x06 + invisible pixels while internal FIFO is empty (lost cycles) + 0x06 + + + 0x07 + display list reader active cycles + 0x07 + + + 0x08 + framebuffer read hits + 0x08 + + + 0x09 + framebuffer read misses + 0x09 + + + 0x0A + framebuffer write hits + 0x0A + + + 0x0B + framebuffer write misses + 0x0B + + + 0x0C + texture read hits + 0x0C + + + 0x0D + texture read misses + 0x0D + + + 0x1F + every clock cycle (for use as timer) + 0x1F + + + others + Setting prohibited + true + + + + + PERFTRIGGER1 + Selects the internal event that will increment PERFCOUNT1 register. + 0 + 15 + write-only + + + 0x00 + disable performance counter + 0x00 + + + 0x01 + 2D Drawing Engine active cycles + 0x01 + + + 0x02 + framebuffer read access + 0x02 + + + 0x03 + framebuffer write access + 0x03 + + + 0x04 + texture read access + 0x04 + + + 0x05 + invisible pixels (enumerated but selected with alpha 0percent) + 0x05 + + + 0x06 + invisible pixels while internal FIFO is empty (lost cycles) + 0x06 + + + 0x07 + display list reader active cycles + 0x07 + + + 0x08 + framebuffer read hits + 0x08 + + + 0x09 + framebuffer read misses + 0x09 + + + 0x0A + framebuffer write hits + 0x0A + + + 0x0B + framebuffer write misses + 0x0B + + + 0x0C + texture read hits + 0x0C + + + 0x0D + texture read misses + 0x0D + + + 0x1F + every clock cycle (for use as timer) + 0x1F + + + others + Setting prohibited + true + + + + + + + 2 + 0x4 + 1,2 + PERFCOUNT%s + Performance Counter %s + 0xCC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PERFCOUNT + Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H. + 0 + 31 + read-write + + + + + + + R_DTC + Data Transfer Controller + 0x40005400 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x04 + registers + + + 0x0000000C + 0x01 + registers + + + 0x0000000E + 0x02 + registers + + + + DTCCR + DTC Control Register + 0x00 + 8 + read-write + 0x08 + 0xFF + + + RRS + DTC Transfer Information Read Skip Enable. + 4 + 4 + read-write + + + 0 + Do not skip transfer information read + #0 + + + 1 + Skip transfer information read when vector numbers match + #1 + + + + + + + DTCVBR + DTC Vector Base Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTCVBR + DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. + 0 + 31 + read-write + + + + + DTCST + DTC Module Start Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + DTCST + DTC Module Start + 0 + 0 + read-write + + + 0 + DTC module stop + #0 + + + 1 + DTC module start + #1 + + + + + + + DTCSTS + DTC Status Register + 0x0E + 16 + read-only + 0x0000 + 0xFFFF + + + ACT + DTC Active Flag + 15 + 15 + read-only + + + 0 + DTC transfer operation is not in progress. + #0 + + + 1 + DTC transfer operation is in progress. + #1 + + + + + VECN + DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) + 0 + 7 + read-only + + + + + + + R_ELC + Event Link Controller + 0x40041000 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000010 + 0x02 + registers + + + 0x00000014 + 0x02 + registers + + + 0x00000018 + 0x02 + registers + + + 0x0000001C + 0x02 + registers + + + 0x00000020 + 0x02 + registers + + + 0x00000024 + 0x02 + registers + + + 0x00000028 + 0x02 + registers + + + 0x0000002C + 0x02 + registers + + + 0x00000030 + 0x02 + registers + + + 0x00000034 + 0x02 + registers + + + 0x00000038 + 0x02 + registers + + + 0x0000003C + 0x02 + registers + + + 0x00000040 + 0x02 + registers + + + 0x00000044 + 0x02 + registers + + + 0x00000048 + 0x02 + registers + + + 0x0000004C + 0x02 + registers + + + 0x00000050 + 0x02 + registers + + + 0x00000054 + 0x02 + registers + + + 0x00000058 + 0x02 + registers + + + 0x0000005C + 0x02 + registers + + + 0x00000060 + 0x02 + registers + + + 0x00000064 + 0x02 + registers + + + 0x00000068 + 0x02 + registers + + + + 2 + 0x2 + ELSEGR[%s] + Event Link Software Event Generation Register + 0x02 + + BY + Event Link Software Event Generation Register + 0x00 + 8 + read-write + 0x80 + 0xFF + + + WI + ELSEGR Register Write Disable + 7 + 7 + write-only + + + 0 + Write to ELSEGR register is enabled. + #0 + + + 1 + Write to ELSEGR register is disabled. + #1 + + + + + WE + SEG Bit Write Enable + 6 + 6 + read-write + + + 0 + Write to SEG bit is disabled. + #0 + + + 1 + Write to SEG bit is enabled. + #1 + + + + + SEG + Software Event Generation + 0 + 0 + write-only + + + 0 + Normal operation + #0 + + + 1 + Software event is generated. + #1 + + + + + + + + 23 + 0x4 + + + GPTA + GPTA + 0 + + + GPTB + GPTB + 1 + + + GPTC + GPTC + 2 + + + GPTD + GPTD + 3 + + + GPTE + GPTE + 4 + + + GPTF + GPTF + 5 + + + GPTG + GPTG + 6 + + + GPTH + GPTH + 7 + + + ADCA0 + ADCA0 + 8 + + + ADCB0 + ADCB0 + 9 + + + ADCA1 + ADCA1 + 10 + + + ADCB1 + ADCB1 + 11 + + + DA0 + DA0 + 12 + + + DA1 + DA1 + 13 + + + PORT1 + PORT1 + 14 + + + PORT2 + PORT2 + 15 + + + PORT3 + PORT3 + 16 + + + PORT4 + PORT4 + 17 + + + CTSU + CTSU + 18 + + + DA80 + DA80 + 19 + + + DA81 + DA81 + 20 + + + DA82 + DA82 + 21 + + + SDADC0 + SDADC0 + 22 + + + ELSR[%s] + Event Link Setting Register %s + 0x10 + + HA + Event Link Setting Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + ELS + Event Link Select + 0 + 8 + read-write + + + 0x000 + Event output to the corresponding peripheral module is disabled. + 0x000 + + + others + Set the number for the event signal to be linked. + true + + + + + + + + ELCR + Event Link Controller Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + ELCON + All Event Link Enable + 7 + 7 + read-write + + + 0 + ELC function is disabled. + #0 + + + 1 + ELC function is enabled. + #1 + + + + + + + + + R_ETHERC0 + Ethernet MAC Controller + 0x40064100 + + 0x00000000 + 0x04 + registers + + + 0x00000008 + 0x04 + registers + + + 0x00000010 + 0x04 + registers + + + 0x00000018 + 0x04 + registers + + + 0x00000020 + 0x04 + registers + + + 0x00000028 + 0x04 + registers + + + 0x00000040 + 0x04 + registers + + + 0x00000050 + 0x00C + registers + + + 0x00000060 + 0x010 + registers + + + 0x000000C0 + 0x04 + registers + + + 0x000000C8 + 0x04 + registers + + + 0x000000D0 + 0x010 + registers + + + 0x000000E4 + 0x018 + registers + + + + ECMR + ETHERC Mode Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPC + PAUSE Frame Transmit + 20 + 20 + read-write + + + 0 + PAUSE frame is transmitted even during a PAUSE period. + #0 + + + 1 + PAUSE frame is not transmitted during a PAUSE period. + #1 + + + + + ZPF + 0 Time PAUSE Frame Enable + 19 + 19 + read-write + + + 0 + PAUSE frame that contains the pause_time parameter of 0 is not used. + #0 + + + 1 + PAUSE frame that contains the pause_time parameter of 0 is used. + #1 + + + + + PFR + PAUSE Frame Receive Mode + 18 + 18 + read-write + + + 0 + PAUSE frame is not transferred to the EDMAC. + #0 + + + 1 + PAUSE frame is transferred to the EDMAC. + #1 + + + + + RXF + Receive Flow Control Operating Mode + 17 + 17 + read-write + + + 0 + PAUSE frame detection is disabled. + #0 + + + 1 + PAUSE frame detection is enabled. + #1 + + + + + TXF + Transmit Flow Control Operating Mode + 16 + 16 + read-write + + + 0 + Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.) + #0 + + + 1 + Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.) + #1 + + + + + PRCEF + CRC Error Frame Receive Mode + 12 + 12 + read-write + + + 0 + EDMAC is notified of a CRC error. + #0 + + + 1 + EDMAC is not notified of a CRC error. + #1 + + + + + MPDE + Magic Packet Detection Enable + 9 + 9 + read-write + + + 0 + Magic Packet detection is disabled. + #0 + + + 1 + Magic Packet detection is enabled. + #1 + + + + + RE + Reception Enable + 6 + 6 + read-write + + + 0 + Receive function is disabled. + #0 + + + 1 + Receive function is enabled. + #1 + + + + + TE + Transmission Enable + 5 + 5 + read-write + + + 0 + Transmit function is disabled. + #0 + + + 1 + Transmit function is enabled. + #1 + + + + + ILB + Internal Loopback Mode + 3 + 3 + read-write + + + 0 + Normal data transmission or reception is performed. + #0 + + + 1 + Data is looped back in the ETHERC when full-duplex mode is selected. + #1 + + + + + RTM + Bit Rate + 2 + 2 + read-write + + + 0 + 10 Mbps + #0 + + + 1 + 100 Mbps + #1 + + + + + DM + Duplex Mode + 1 + 1 + read-write + + + 0 + Half-duplex mode + #0 + + + 1 + Full-duplex mode + #1 + + + + + PRM + Promiscuous Mode + 0 + 0 + read-write + + + 0 + Promiscuous mode is disabled. + #0 + + + 1 + Promiscuous mode is enabled. + #1 + + + + + + + RFLR + Receive Frame Maximum Length Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RFL + Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes. + 0 + 11 + read-write + + + + + ECSR + ETHERC Status Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BFR + Continuous Broadcast Frame Reception Flag + 5 + 5 + read-write + oneToClear + modify + + + 0 + Continuous reception of broadcast frames has not been detected. + #0 + + + 1 + Continuous reception of broadcast frames has been detected. + #1 + + + + + PSRTO + PAUSE Frame Retransmit Over Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + PAUSE frame retransmit count has not reached the upper limit. + #0 + + + 1 + PAUSE frame retransmit count has reached the upper limit. + #1 + + + + + LCHNG + LCHNG Link Signal Change Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + Change in the ETn_LINKSTA signal has not been detected. + #0 + + + 1 + Change in the ETn_LINKSTA signal has been detected (high to low, or low to high). + #1 + + + + + MPD + Magic Packet Detect Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + Magic Packet has not been detected. + #0 + + + 1 + Magic Packet has been detected. + #1 + + + + + ICD + False Carrier Detect Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + PHY-LSI has not detected a false carrier on the line. + #0 + + + 1 + PHY-LSI has detected a false carrier on the line. + #1 + + + + + + + ECSIPR + ETHERC Interrupt Enable Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BFSIPR + Continuous Broadcast Frame Reception Interrupt Enable + 5 + 5 + read-write + + + 0 + Notification of continuous broadcast frame reception interrupt is disabled. + #0 + + + 1 + Notification of continuous broadcast frame reception interrupt is enabled. + #1 + + + + + PSRTOIP + PAUSE Frame Retransmit Over Interrupt Enable + 4 + 4 + read-write + + + 0 + Notification of PAUSE frame retransmit over interrupt is disabled. + #0 + + + 1 + Notification of PAUSE frame retransmit over interrupt is enabled. + #1 + + + + + LCHNGIP + LINK Signal Change Interrupt Enable + 2 + 2 + read-write + + + 0 + Notification of ETn_LINKSTA signal change interrupt is disabled. + #0 + + + 1 + Notification of ETn_LINKSTA signal change interrupt is enabled. + #1 + + + + + MPDIP + Magic Packet Detect Interrupt Enable + 1 + 1 + read-write + + + 0 + Notification of the Magic Packet detect interrupt is disabled. + #0 + + + 1 + Notification of the Magic Packet detect interrupt is enabled. + #1 + + + + + ICDIP + False Carrier Detect Interrupt Enable + 0 + 0 + read-write + + + 0 + Notification of the false carrier detect interrupt is disabled. + #0 + + + 1 + Notification of the false carrier detect interrupt is enabled. + #1 + + + + + + + PIR + PHY Interface Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFF7 + + + MDI + MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0. + 3 + 3 + read-only + + + MDO + MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read). + 2 + 2 + read-write + + + MMD + MII/RMII Management Mode + 1 + 1 + read-write + + + 0 + Read + #0 + + + 1 + Write + #1 + + + + + MDC + MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII. + 0 + 0 + read-write + + + + + PSR + PHY Status Register + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFE + + + LMON + ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI. + 0 + 0 + read-only + + + + + RDMLR + Random Number Generation Counter Upper Limit Setting Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RMD + Random Number Generation Counter + 0 + 19 + read-write + + + 00000h + Normal operation + 0x00000 + + + others + Setting prohibited + true + + + + + + + IPGR + IPG Register + 0x50 + 32 + read-write + 0x00000014 + 0xFFFFFFFF + + + IPG + Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" + 0 + 4 + read-write + + + 14h + 96 bit time (initial value) + 0x14 + + + others + (IPGx4+16) bit time + true + + + + + + + APR + Automatic PAUSE Frame Register + 0x54 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AP + Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. + 0 + 15 + read-write + + + + + MPR + Manual PAUSE Frame Register + 0x58 + 32 + write-only + 0x00000000 + 0xFFFF0000 + + + MP + Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined. + 0 + 15 + write-only + + + + + RFCF + Received PAUSE Frame Counter + 0x60 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RPAUSE + Received PAUSE Frame CountNumber of received PAUSE frames + 0 + 7 + read-only + + + + + TPAUSER + PAUSE Frame Retransmit Count Setting Register + 0x64 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPAUSE + Automatic PAUSE Frame Retransmit Setting + 0 + 15 + read-write + + + 0x0000 + Number of retransmissions is unlimited + 0x0000 + + + others + Maximum number of retransmissions is (TPAUSE) + true + + + + + + + TPAUSECR + PAUSE Frame Retransmit Counter + 0x68 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + + BCFRR + Broadcast Frame Receive Count Setting Register + 0x6C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCF + Broadcast Frame Continuous Receive Count Setting + 0 + 15 + read-write + + + 0000h + Number of receptions is unlimited. + 0x0000 + + + others + Receive (BFC) frame. + true + + + + + + + MAHR + MAC Address Upper Bit Register + 0xC0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MAHR + MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address. + 0 + 31 + read-write + + + + + MALR + MAC Address Lower Bit Register + 0xC8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MALR + MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address. + 0 + 15 + read-write + + + + + TROCR + Transmit Retry Over Counter Register + 0xD0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TROCR + Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted. + 0 + 31 + read-write + clear + + + + + CDCR + Late Collision Detect Counter Register + 0xD4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + LCCR + Lost Carrier Counter Register + 0xD8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCCR + Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission. + 0 + 31 + read-write + clear + + + + + CNDCR + Carrier Not Detect Counter Register + 0xDC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNDCR + Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission. + 0 + 31 + read-write + clear + + + + + CEFCR + CRC Error Frame Receive Counter Register + 0xE4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CEFCR + CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected. + 0 + 31 + read-write + clear + + + + + FRECR + Frame Receive Error Counter Register + 0xE8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRECR + Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred. + 0 + 31 + read-write + clear + + + + + TSFRCR + Too-Short Frame Receive Counter Register + 0xEC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSFRCR + Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received. + 0 + 31 + read-write + clear + + + + + TLFRCR + Too-Long Frame Receive Counter Register + 0xF0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TLFRCR + Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received. + 0 + 31 + read-write + clear + + + + + RFCR + Received Alignment Error Frame Counter Register + 0xF4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RFCR + Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets). + 0 + 31 + read-write + clear + + + + + MAFCR + Multicast Address Frame Receive Counter Register + 0xF8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MAFCR + Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received. + 0 + 31 + read-write + clear + + + + + + + R_ETHERC_EDMAC + Ethernet DMA Controller + 0x40064000 + + 0x00000000 + 0x04 + registers + + + 0x00000008 + 0x04 + registers + + + 0x00000010 + 0x04 + registers + + + 0x00000018 + 0x04 + registers + + + 0x00000020 + 0x04 + registers + + + 0x00000028 + 0x04 + registers + + + 0x00000030 + 0x04 + registers + + + 0x00000038 + 0x04 + registers + + + 0x00000040 + 0x04 + registers + + + 0x00000048 + 0x04 + registers + + + 0x00000050 + 0x04 + registers + + + 0x00000058 + 0x04 + registers + + + 0x00000064 + 0x010 + registers + + + 0x00000078 + 0x008 + registers + + + 0x000000C8 + 0x008 + registers + + + 0x000000D4 + 0x008 + registers + + + + EDMR + EDMAC Mode Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DE + Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers. + 6 + 6 + read-write + + + 0 + Big endian mode + #0 + + + 1 + Little endian mode + #1 + + + + + DL + Transmit/Receive DescriptorLength + 4 + 5 + read-write + + + 00 + 16 bytes + #00 + + + 01 + 32 bytes + #01 + + + 10 + 64 bytes + #10 + + + 11 + 16 bytes + #11 + + + + + SWR + Software Reset + 0 + 0 + write-only + + + 0 + no effect. + #0 + + + 1 + the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset. + #1 + + + + + + + EDTRR + EDMAC Transmit Request Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TR + Transmit Request + 0 + 0 + write-only + + + 0 + no effect. + #0 + + + 1 + When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. + #1 + + + + + + + EDRRR + EDMAC Receive Request Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RR + Receive Request + 0 + 0 + read-write + + + 0 + Receive function is disabled. + #0 + + + 1 + Receive descriptor is read, and the receive function is enabled. + #1 + + + + + + + TDLAR + Transmit Descriptor List Start Address Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDLAR + The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b + 0 + 31 + read-write + + + + + RDLAR + Receive Descriptor List Start Address Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RDLAR + The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b + 0 + 31 + read-write + + + + + EESR + ETHERC/EDMAC Status Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TWB + Write-Back Complete Flag + 30 + 30 + read-write + oneToClear + modify + + + 0 + Write-back has not been completed, or no transmission has been requested. + #0 + + + 1 + Write-back to the transmit descriptor has been completed. + #1 + + + + + TABT + Transmit Abort Detect Flag + 26 + 26 + read-write + oneToClear + modify + + + 0 + Frame transmission has not been aborted or no transmission has been requested. + #0 + + + 1 + Frame transmission has been aborted. + #1 + + + + + RABT + Receive Abort Detect Flag + 25 + 25 + read-write + oneToClear + modify + + + 0 + Frame reception has not been aborted or no reception has been requested. + #0 + + + 1 + Frame reception has been aborted. + #1 + + + + + RFCOF + Receive Frame Counter Overflow Flag + 24 + 24 + read-write + oneToClear + modify + + + 0 + Receive frame counter has not overflowed. + #0 + + + 1 + Receive frame counter has overflowed. + #1 + + + + + ADE + Address Error Flag + 23 + 23 + read-write + oneToClear + modify + + + 0 + Invalid memory address has not been detected (normal operation). + #0 + + + 1 + Invalid memory address has been detected. + #1 + + + + + ECI + ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared. + 22 + 22 + read-only + + + 0 + ETHERC status interrupt source has not been detected. + #0 + + + 1 + ETHERC status interrupt source has been detected. + #1 + + + + + TC + Frame Transfer Complete Flag + 21 + 21 + read-write + oneToClear + modify + + + 0 + Transfer have not been completed, or no transfer has been requested. + #0 + + + 1 + All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO. + #1 + + + + + TDE + Transmit Descriptor Empty Flag + 20 + 20 + read-write + oneToClear + modify + + + 0 + The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1. + #0 + + + 1 + The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0. + #1 + + + + + TFUF + Transmit FIFO Underflow Flag + 19 + 19 + read-write + oneToClear + modify + + + 0 + Underflow has not occurred. + #0 + + + 1 + Underflow has occurred. + #1 + + + + + FR + Frame Receive Flag + 18 + 18 + read-write + oneToClear + modify + + + 0 + Frame has not been received. + #0 + + + 1 + Frame has been received. Update of the receive descriptor is complete. + #1 + + + + + RDE + Receive Descriptor Empty Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1. + #0 + + + 1 + The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0. + #1 + + + + + RFOF + Receive FIFO Overflow Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + Overflow has not occurred. + #0 + + + 1 + Overflow has occurred. + #1 + + + + + CND + Carrier Not Detect Flag + 11 + 11 + read-write + oneToClear + modify + + + 0 + A carrier has been detected when transmission starts. + #0 + + + 1 + A carrier has not been detected during preamble transmission. + #1 + + + + + DLC + Loss of Carrier Detect Flag + 10 + 10 + read-write + oneToClear + modify + + + 0 + Loss of carrier has not been detected. + #0 + + + 1 + Loss of carrier has been detected during frame transmission. + #1 + + + + + CD + Late Collision Detect Flag + 9 + 9 + read-write + oneToClear + modify + + + 0 + Late collision has not been detected. + #0 + + + 1 + Late collision has been detected during frame transmission. + #1 + + + + + TRO + Transmit Retry Over Flag + 8 + 8 + read-write + oneToClear + modify + + + 0 + Transmit retry-over condition has not been detected. + #0 + + + 1 + Transmit retry-over condition has been detected. + #1 + + + + + RMAF + Multicast Address Frame Receive Flag + 7 + 7 + read-write + oneToClear + modify + + + 0 + Multicast address frame has not been received. + #0 + + + 1 + Multicast address frame has been received. + #1 + + + + + RRF + Alignment Error Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + Alignment error has not been detected. + #0 + + + 1 + Alignment error has been detected. + #1 + + + + + RTLF + Frame-Too-Long Error Flag + 3 + 3 + read-write + oneToClear + modify + + + 0 + Frame-too-long error has not been detected. + #0 + + + 1 + Frame-too-long error has been detected. + #1 + + + + + RTSF + Frame-Too-Short Error Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + Frame-too-short error has not been detected. + #0 + + + 1 + Frame-too-short error has been detected. + #1 + + + + + PRE + PHY-LSI Receive Error Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + PHY-LSI receive error has not been detected. + #0 + + + 1 + PHY-LSI receive error has been detected. + #1 + + + + + CERF + CRC Error Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + CRC error has not been detected. + #0 + + + 1 + CRC error has been detected. + #1 + + + + + + + EESIPR + ETHERC/EDMAC Status Interrupt Enable Register + 0x30 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TWBIP + Write-Back Complete Interrupt Request Enable + 30 + 30 + read-write + + + 0 + Write-back complete interrupt request is disabled. + #0 + + + 1 + Write-back complete interrupt request is enabled. + #1 + + + + + TABTIP + Transmit Abort Detect Interrupt Request Enable + 26 + 26 + read-write + + + 0 + Transmit abort detect interrupt request is disabled. + #0 + + + 1 + Transmit abort detect interrupt request is enabled. + #1 + + + + + RABTIP + Receive Abort Detect Interrupt Request Enable + 25 + 25 + read-write + + + 0 + Receive abort detect interrupt request is disabled. + #0 + + + 1 + Receive abort detect interrupt request is enabled. + #1 + + + + + RFCOFIP + Receive Frame Counter Overflow Interrupt Request Enable + 24 + 24 + read-write + + + 0 + Receive frame counter overflow interrupt request is disabled. + #0 + + + 1 + Receive frame counter overflow interrupt request is enabled. + #1 + + + + + ADEIP + Address Error Interrupt Request Enable + 23 + 23 + read-write + + + 0 + Address error interrupt request is disabled. + #0 + + + 1 + Address error interrupt request is enabled. + #1 + + + + + ECIIP + ETHERC Status Register Source Interrupt Request Enable + 22 + 22 + read-write + + + 0 + ETHERC status interrupt request is disabled. + #0 + + + 1 + ETHERC status interrupt request is enabled. + #1 + + + + + TCIP + Frame Transfer Complete Interrupt Request Enable + 21 + 21 + read-write + + + 0 + Frame transmission complete interrupt request is disabled. + #0 + + + 1 + Frame transmission complete interrupt request is enabled. + #1 + + + + + TDEIP + Transmit Descriptor Empty Interrupt Request Enable + 20 + 20 + read-write + + + 0 + Transmit descriptor empty interrupt request is disabled. + #0 + + + 1 + Transmit descriptor empty interrupt request is enabled. + #1 + + + + + TFUFIP + Transmit FIFO Underflow Interrupt Request Enable + 19 + 19 + read-write + + + 0 + Underflow interrupt request is disabled. + #0 + + + 1 + Underflow interrupt request is enabled. + #1 + + + + + FRIP + Frame Receive Interrupt Request Enable + 18 + 18 + read-write + + + 0 + Frame reception interrupt request is disabled. + #0 + + + 1 + Frame reception interrupt request is enabled. + #1 + + + + + RDEIP + Receive Descriptor Empty Interrupt Request Enable + 17 + 17 + read-write + + + 0 + Receive descriptor empty interrupt request is disabled. + #0 + + + 1 + Receive descriptor empty interrupt request is enabled. + #1 + + + + + RFOFIP + Receive FIFO Overflow Interrupt Request Enable + 16 + 16 + read-write + + + 0 + Overflow interrupt request is disabled. + #0 + + + 1 + Overflow interrupt request is enabled. + #1 + + + + + CNDIP + Carrier Not Detect Interrupt Request Enable + 11 + 11 + read-write + + + 0 + Carrier not detect interrupt request is disabled. + #0 + + + 1 + Carrier not detect interrupt request is enabled. + #1 + + + + + DLCIP + Loss of Carrier Detect Interrupt Request Enable + 10 + 10 + read-write + + + 0 + Loss of carrier detect interrupt request is disabled. + #0 + + + 1 + Loss of carrier detect interrupt request is enabled. + #1 + + + + + CDIP + Late Collision Detect Interrupt Request Enable + 9 + 9 + read-write + + + 0 + Late collision detect interrupt request is disabled. + #0 + + + 1 + Late collision detect interrupt request is enabled. + #1 + + + + + TROIP + Transmit Retry Over Interrupt Request Enable + 8 + 8 + read-write + + + 0 + Transmit retry over interrupt request is disabled. + #0 + + + 1 + Transmit retry over interrupt request is enabled. + #1 + + + + + RMAFIP + Multicast Address Frame Receive Interrupt Request Enable + 7 + 7 + read-write + + + 0 + Multicast address frame receive interrupt request is disabled. + #0 + + + 1 + Multicast address frame receive interrupt request is enabled. + #1 + + + + + RRFIP + Alignment Error Interrupt Request Enable + 4 + 4 + read-write + + + 0 + Alignment error interrupt request is disabled. + #0 + + + 1 + Alignment error interrupt request is enabled. + #1 + + + + + RTLFIP + Frame-Too-Long Error Interrupt Request Enable + 3 + 3 + read-write + + + 0 + Frame-too-long error interrupt request is disabled. + #0 + + + 1 + Frame-too-long error interrupt request is enabled. + #1 + + + + + RTSFIP + Frame-Too-Short Error Interrupt Request Enable + 2 + 2 + read-write + + + 0 + Frame-too-short error interrupt request is disabled. + #0 + + + 1 + Frame-too-short error interrupt request is enabled. + #1 + + + + + PREIP + PHY-LSI Receive Error Interrupt Request Enable + 1 + 1 + read-write + + + 0 + PHY-LSI receive error interrupt request is disabled. + #0 + + + 1 + PHY-LSI receive error interrupt request is enabled. + #1 + + + + + CERFIP + CRC Error Interrupt Request Enable + 0 + 0 + read-write + + + 0 + CRC error interrupt request is disabled. + #0 + + + 1 + CRC error interrupt request is enabled. + #1 + + + + + + + TRSCER + ETHERC/EDMAC Transmit/Receive Status Copy Enable Register + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RMAFCE + RMAF Flag Copy Enable + 7 + 7 + read-write + + + 0 + The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor. + #0 + + + 1 + The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor. + #1 + + + + + RRFCE + RRF Flag Copy Enable + 4 + 4 + read-write + + + 0 + The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor. + #0 + + + 1 + The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor. + #1 + + + + + + + RMFCR + Missed-Frame Counter Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MFC + Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception. + 0 + 15 + read-write + clear + + + + + TFTR + Transmit FIFO Threshold Register + 0x48 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFT + Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes + 0 + 10 + read-write + + + 0x000 + 0x200 + + + + + 0x000 + Store and forward mode + 0x000 + + + others + The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited) + true + + + + + + + FDR + Transmit FIFO Threshold Register + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFD + Receive FIFO Depth + 8 + 12 + read-write + + + 01111 + 4096 bytes + #01111 + + + others + Settings other than above are prohibited. + true + + + + + RFD + Transmit FIFO Depth + 0 + 4 + read-write + + + 00111 + 2048 bytes + #00111 + + + others + Settings other than above are prohibited. + true + + + + + + + RMCR + Receive Method Control Register + 0x58 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RNR + Receive Request Reset + 0 + 0 + read-write + + + 0 + EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received. + #0 + + + 1 + EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received. + #1 + + + + + + + TFUCR + Transmit FIFO Underflow Counter + 0x64 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + UNDER + Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh. + 0 + 15 + read-write + + + + + RFOCR + Receive FIFO Overflow Counter + 0x68 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + OVER + Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh. + 0 + 15 + read-write + + + + + IOSR + Independent Output Signal Setting Register + 0x6C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ELB + External Loopback Mode + 0 + 0 + read-write + + + 0 + The ETn_EXOUT pin outputs low. + #0 + + + 1 + The ETn_EXOUT pin outputs high. + #1 + + + + + + + FCFTR + Flow Control Start FIFO Threshold Setting Register + 0x70 + 32 + read-write + 0x00070007 + 0xFFFFFFFF + + + RFFO + Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.) + 16 + 18 + read-write + + + 000 + When 2 receive frames have been stored in the receive FIFO. + #000 + + + 001 + When 4 receive frames have been stored in the receive FIFO. + #001 + + + 010 + When 6 receive frames have been stored in the receive FIFO. + #010 + + + 011 + When 8 receive frames have been stored in the receive FIFO. + #011 + + + 100 + When 10 receive frames have been stored in the receive FIFO. + #100 + + + 101 + When 12 receive frames have been stored in the receive FIFO. + #101 + + + 110 + When 14 receive frames have been stored in the receive FIFO. + #110 + + + 111 + When 16 receive frames have been stored in the receive FIFO. + #111 + + + + + RFDO + Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.) + 0 + 2 + read-write + + + 000 + When 224 ( 256 - 32) bytes of data is stored in the receive FIFO. + #000 + + + 001 + When 480 ( 512 - 32) bytes of data is stored in the receive FIFO. + #001 + + + 010 + When 736 ( 768 - 32) bytes of data is stored in the receive FIFO. + #010 + + + 011 + When 992 (1024 - 32) bytes of data is stored in the receive FIFO. + #011 + + + 100 + When 1248 (1280 - 32) bytes of data is stored in the receive FIFO. + #100 + + + 101 + When 1504 (1536 - 32) bytes of data is stored in the receive FIFO. + #101 + + + 110 + When 1760 (1792 - 32) bytes of data is stored in the receive FIFO. + #110 + + + 111 + When 2016 (2048 - 32) bytes of data is stored in the receive FIFO. + #111 + + + + + + + RPADIR + Receive Data Padding Insert Register + 0x78 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PADS + Padding Size + 16 + 17 + read-write + + + 00 + No padding is inserted. + #00 + + + 01 + 1 byte is inserted. + #01 + + + 10 + 2 bytes are inserted. + #10 + + + 11 + 3 bytes are inserted. + #11 + + + + + PADR + Padding Slot + 0 + 5 + read-write + + + 00h + Padding is inserted at the head of received data. + 0x00 + + + others + Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data. + true + + + + + + + TRIMD + Transmit Interrupt Setting Register + 0x07C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM + Transmit Interrupt Mode + 4 + 4 + read-write + + + 0 + Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. + #0 + + + 1 + Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed. + #1 + + + + + TIS + Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt. + 0 + 0 + read-write + + + 0 + Transmit Interrupt is disabled. + #0 + + + 1 + Transmit Interrupt is enabled. + #1 + + + + + + + RBWAR + Receive Buffer Write Address Register + 0xC8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RBWAR + Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception. + 0 + 31 + read-only + + + + + RDFAR + Receive Descriptor Fetch Address Register + 0xCC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RDFAR + Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception. + 0 + 31 + read-only + + + + + TBRAR + Transmit Buffer Read Address Register + 0x0D4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TBRAR + Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register. + 0 + 31 + read-only + + + + + TDFAR + Transmit Descriptor Fetch Address Register + 0xD8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + TDFAR + Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register. + 0 + 31 + read-only + + + + + + + R_ETHERC_EPTPC + Ethernet PTP Controller + 0x40065800 + + 0x00000000 + 0x008 + registers + + + 0x00000010 + 0x010 + registers + + + 0x00000040 + 0x008 + registers + + + 0x00000050 + 0x01C + registers + + + 0x00000080 + 0x04 + registers + + + 0x00000090 + 0x00C + registers + + + 0x000000A0 + 0x00C + registers + + + 0x000000C0 + 0x018 + registers + + + 0x000000E0 + 0x018 + registers + + + 0x00000100 + 0x014 + registers + + + 0x00000120 + 0x024 + registers + + + 0x00000160 + 0x018 + registers + + + 0x000001C0 + 0x018 + registers + + + + 2 + 0x8 + F[%s] + Frame Reception Filter Setting Registers + 0x160 + + 2 + 0x8 + 0-1 + MACRU + Frame Reception Filter MAC Address Setting Registers + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames. + 0 + 23 + read-write + + + + + 2 + 0x8 + 0-1 + MACRL + Frame Reception Filter MAC Address Setting Registers + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames. + 0 + 23 + read-write + + + + + + SYSR + SYNFP Status Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GENDN + Generation Stop Completion Detection Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + Stopping generation has not been completed. + #0 + + + 1 + Stopping generation has been completed. + #1 + + + + + RESDN + Response Stop Completion Detection Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + Stopping responses has not been completed. + #0 + + + 1 + Stopping responses has been completed. + #1 + + + + + INFABT + Control Information Abnormality Detection Flag + 14 + 14 + read-write + oneToClear + modify + + + 0 + No abnormality in control information + #0 + + + 1 + Abnormality in control information + #1 + + + + + RECLP + Loop Reception Detection Flag + 12 + 12 + read-write + oneToClear + modify + + + 0 + A received message has not returned through a loop. + #0 + + + 1 + A received message has returned through a loop. + #1 + + + + + DRQOVR + Delay_Req Reception FIFO Overflow Detection Flag + 6 + 6 + read-write + oneToClear + modify + + + 0 + The received Delay_Req has not caused the reception FIFO to overflow. + #0 + + + 1 + The received Delay_Req has caused the reception FIFO to overflow. + #1 + + + + + INTDEV + Receive logMessageInterval Value Out-of-Range Flag + 5 + 5 + read-write + oneToClear + modify + + + 0 + The received logMessageInterval value is within the range. + #0 + + + 1 + The received logMessageInterval value is out of the range. + #1 + + + + + DRPTO + Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + A Delay_Resp/Pdelay_Resp timeout has not occurred. + #0 + + + 1 + A Delay_Resp/Pdelay_Resp timeout has occurred. + #1 + + + + + MPDUD + meanPathDelay Value Update Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + The meanPathDelay value has not been updated. + #0 + + + 1 + The meanPathDelay value has been updated. + #1 + + + + + INTCHG + Receive logMessageInterval Value Change Detection Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + No change in the received logMessageInterval value. + #0 + + + 1 + A change in the received logMessageInterval value. + #1 + + + + + OFMUD + offsetFromMaster Value Update Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + The offsetFromMaster value has not been updated. + #0 + + + 1 + The offsetFromMaster value has been updated. + #1 + + + + + + + SYIPR + SYNFP Status Notification Permission Register + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GENDN + SYSR.GENDN Status Notification Permission + 17 + 17 + read-write + + + 0 + Prohibits notification of the state of SYSR.GENDN. + #0 + + + 1 + Permits notification of the state of SYSR.GENDN. + #1 + + + + + RESDN + SYSR.RESDN Status Notification Permission + 16 + 16 + read-write + + + 0 + Prohibits notification of the state of SYSR.RESDN. + #0 + + + 1 + Permits notification of the state of SYSR.RESDN. + #1 + + + + + INFABT + SYSR.INFABT Status Notification Permission + 14 + 14 + read-write + + + 0 + Prohibits notification of the state of SYSR.INFABT. + #0 + + + 1 + Permits notification of the state of SYSR.INFABT. + #1 + + + + + RECLP + SYSR.RECLP Status Notification Permission + 12 + 12 + read-write + + + 0 + Prohibits notification of the state of SYSR.RECLP. + #0 + + + 1 + Permits notification of the state of SYSR.RECLP. + #1 + + + + + DRQOVR + SYSR.DRQOVR Status Notification Permission + 6 + 6 + read-write + + + 0 + Prohibits notification of the state of SYSR.DRQOVR. + #0 + + + 1 + Permits notification of the state of SYSR.DRQOVR. + #1 + + + + + INTDEV + SYSR.INTDEV Status Notification Permission + 5 + 5 + read-write + + + 0 + Prohibits notification of the state of SYSR.INTDEV. + #0 + + + 1 + Permits notification of the state of SYSR.INTDEV. + #1 + + + + + DRPTO + SYSR.DRPTO Status Notification Permission + 4 + 4 + read-write + + + 0 + Prohibits notification of the state of SYSR.DRPTO. + #0 + + + 1 + Permits notification of the state of SYSR.DRPTO. + #1 + + + + + MPDUD + SYSR.MPDUD Status Notification Permission + 2 + 2 + read-write + + + 0 + Prohibits notification of the state of SYSR.MPDUD. + #0 + + + 1 + Permits notification of the state of SYSR.MPDUD. + #1 + + + + + INTCHG + SYSR.INTCHG Status Notification Permission + 1 + 1 + read-write + + + 0 + Prohibits notification of the state of SYSR.INTCHG. + #0 + + + 1 + Permits notification of the state of SYSR.INTCHG. + #1 + + + + + OFMUD + SYSR.OFMUD Status Notification Permission + 0 + 0 + read-write + + + 0 + Prohibits notification of the state of SYSR.OFMUD. + #0 + + + 1 + Permits notification of the state of SYSR.OFMUD. + #1 + + + + + + + SYMACRU + SYNFP MAC Address Registers + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYMACRU + These bits hold the setting for the higher-order 24 bits of the local MAC address. + 0 + 23 + read-write + + + + + SYMACRL + SYNFP MAC Address Registers + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYMACRL + These bits hold the setting for the lower-order 24 bits of the local MAC address. + 0 + 23 + read-write + + + + + SYLLCCTLR + SYNFP LLC-CTL Value Register + 0x018 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + + + CTL + LLC-CTL FieldThese bits specify the value used for the control field in the LLC sublayer when generating IEEE802.3 frames. + 0 + 7 + read-write + + + + + SYIPADDRR + SYNFP Local IP Address Register + 0x01C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYIPADDRR + These bits hold the setting for the local IP address. + 0 + 31 + read-write + + + + + SYSPVRR + SYNFP Specification Version Setting Register + 0x040 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + TRSP + transportSpecific Field ValueThese bits are used to set the transportSpecific field value of the PTP v2 header.When a message is received, this value is compared with the transportSpecific field of the received frame.In generating messages, the value is used for the transportSpecific field of the frame for transmission.Set these bits to 0000b (IEEE 1588). + 4 + 7 + read-write + + + VER + versionPTP Field ValueThese bits are used to set the versionPTP field value of the PTP v2 header.When a message is received, this value is compared with the versionPTP field of the received frame.In generating messages, the value is used for the versionPTP field of the frame for transmission.Set these bits to 0010b (PTP v2). + 0 + 3 + read-write + + + + + SYDOMR + SYNFP Domain Number Setting Register + 0x044 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DNUM + domainNumber Field Value SettingThese bits are used to set the domainNumber field value of the PTP v2 header.When a message is received, this value is compared with the domainNumber field of the received frame as a condition for PTP reception processing.In generating messages, the value is used for the domainNumber field of the frame for transmission. + 0 + 7 + read-write + + + + + ANFR + Announce Message Flag Field Setting Register + 0x050 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + FLAG5 + frequencyTraceableThis bit is used to set the logical value of the frequencyTraceable member of timePropertiesDS. + 5 + 5 + read-write + + + 0 + frequencyTraceable is set to FALSE. + #0 + + + 1 + frequencyTraceable is set to TRUE. + #1 + + + + + FLAG4 + timeTraceableThis bit is used to set the logical value of the timeTraceable member of timePropertiesDS. + 4 + 4 + read-write + + + 0 + timeTraceable is set to FALSE. + #0 + + + 1 + timeTraceable is set to TRUE. + #1 + + + + + FLAG3 + ptpTimescaleThis bit is used to set the logical value of the ptpTimescale member of timePropertiesDS. + 3 + 3 + read-write + + + 0 + ptpTimescale is set to FALSE. + #0 + + + 1 + ptpTimescale is set to TRUE. + #1 + + + + + FLAG2 + currentUtcOffsetValidThis bit is used to set the logical value of the currentUtcOffsetValid member of timePropertiesDS. + 2 + 2 + read-write + + + 0 + currentUtcOffsetValid is set to FALSE. + #0 + + + 1 + currentUtcOffsetValid is set to TRUE. + #1 + + + + + FLAG1 + leap59This bit is used to set the logical value of the leap59 member of timePropertiesDS. + 1 + 1 + read-write + + + 0 + leap59 is set to FALSE. + #0 + + + 1 + leap59 is set to TRUE. + #1 + + + + + FLAG0 + leap61This bit is used to set the logical value of the leap61 member of timePropertiesDS. + 0 + 0 + read-write + + + 0 + leap61 is set to FALSE. + #0 + + + 1 + leap61 is set to TRUE. + #1 + + + + + + + SYNFR + Sync Message Flag Field Setting Register + 0x054 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG9 + twoStepFlag + 9 + 9 + read-write + + + 0 + Set this bit to 0 (FALSE). + #0 + + + 1 + Setting prohibited + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + + + DYRQFR + Delay_Req Message Flag Field Setting Register + 0x058 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRULE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRULE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRULE. + #1 + + + + + + + DYRPFR + Delay_Resp Message Flag Field Setting Register + 0x05C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG9 + woStepFlag + 9 + 9 + read-write + + + 0 + Set this bit to 0 (FALSE). + #0 + + + 1 + Setting prohibited + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + + + SYCIDRU + SYNFP Local Clock ID Registers + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYCIDRU + These bits hold the setting for the higher-order 32 bits of the clock-ID of your port. + 0 + 31 + read-write + + + + + SYCIDRL + SYNFP Local Clock ID Registers + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYCIDRL + These bits hold the setting for the lower-order 32 bits of the clock-ID of your port. + 0 + 31 + read-write + + + + + SYPNUMR + SYNFP Local Port Number Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PNUM + Local Port Number SettingThese bits hold the setting for the port number of the local port. + 0 + 15 + read-write + + + + + SYRVLDR + SYNFP Register Value Load Directive Register + 0x080 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + ANUP + Announce Message Generation Information Update + 2 + 2 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages. + #1 + + + + + STUP + State Update + 1 + 1 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages. + #1 + + + + + BMUP + BMC Update + 0 + 0 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information. + #1 + + + + + + + SYRFL1R + SYNFP Reception Filter Register 1 + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDFUP2 + Pdelay_Resp_Follow_Up Message Processing + 30 + 30 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP does not process messages. + #1 + + + + + PDFUP1 + Pdelay_Resp_Follow_Up Message Processing + 29 + 29 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDFUP0 + Pdelay_Resp_Follow_Up Message Processing + 28 + 28 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + PDRP2 + Pdelay_Resp Message Processing + 26 + 26 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + PDRP1 + Pdelay_Resp Message Processing + 25 + 25 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDRP0 + Pdelay_Resp Message Processing + 24 + 24 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + PDRQ2 + Pdelay_Req Message Processing + 22 + 22 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + PDRQ1 + Pdelay_Req Message Processing + 21 + 21 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDRQ0 + Pdelay_Req Message Processing + 20 + 20 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + DRP2 + Delay_Resp Message Processing + 18 + 18 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + DRP1 + Delay_Resp Message Processing + 17 + 17 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + DRP0 + Delay_Resp Message Processing + 16 + 16 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + DRQ2 + Delay_Req Message Processing + 14 + 14 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + DRQ1 + Delay_Req Message Processing + 13 + 13 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + DRQ0 + Delay_Req Message Processing + 12 + 12 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + FUP2 + Follow_Up Message Processing + 10 + 10 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + FUP1 + Follow_Up Message Processing + 9 + 9 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + FUP0 + Follow_Up Message Processing + 8 + 8 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + SYNC2 + Sync Message Processing + 6 + 6 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + SYNC1 + Sync Message Processing + 5 + 5 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + SYNC0 + Sync Message Processing + 4 + 4 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + ANCE1 + Announce Message Processing + 1 + 1 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + ANCE0 + Announce Message Processing + 0 + 0 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + + + SYRFL2R + SYNFP Reception Filter Register 2 + 0x094 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ILL1 + Illegal Message Processing Setting + 29 + 29 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + ILL0 + Illegal Message Processing Setting + 28 + 28 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + SIG1 + Signaling Message Processing Setting + 5 + 5 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + SIG0 + Signaling Message Processing Setting + 4 + 4 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + MAN1 + Management Message Processing Setting + 1 + 1 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + MAN0 + Management Message Processing Setting + 0 + 0 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + + + SYTRENR + SYNFP Transmission Enable Register + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDRQ + Pdelay_Req Message Transmission Enable + 12 + 12 + read-write + + + 0 + Pdelay_Req messages are not transmitted. + #0 + + + 1 + Pdelay_Req messages are transmitted. + #1 + + + + + DRQ + Delay_Req Message Transmission Enable + 8 + 8 + read-write + + + 0 + Delay_Req messages are not transmitted. + #0 + + + 1 + Delay_Req messages are transmitted. + #1 + + + + + SYNC + Sync Message Transmission Enable + 4 + 4 + read-write + + + 0 + Sync messages are not transmitted. + #0 + + + 1 + Sync messages are transmitted. + #1 + + + + + ANCE + Announce Message Transmission Enable + 0 + 0 + read-write + + + 0 + Announce messages are not transmitted. + #0 + + + 1 + Announce messages are transmitted. + #1 + + + + + + + MTCIDU + Master Clock ID Registers + 0x0A0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MTCIDU + These bits hold the setting for the higher-order 32 bits of the clock-ID of the master clock. + 0 + 31 + read-write + + + + + MTCIDL + Master Clock ID Registers + 0x0A4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MTCIDL + These bits hold the setting for the lower-order 32 bits of the clock-ID of the master clock. + 0 + 31 + read-write + + + + + MTPID + Master clock port number register + 0x0A8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PNUM + Master Clock Port Number SettingThese bits hold the setting for the port number of the master clock. + 0 + 15 + read-write + + + + + SYTLIR + SYNFP Transmission Interval Setting Register + 0x0C0 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + DREQ + Delay_Req Transmission Interval Average Value/ Pdelay_Req Transmission Interval SettingThe bits set the average interval for the transmission of Delay_Req messages and the interval for the transmission of Pdelay_Req messages.The setting is also placed in the logMessageInterval field of Delay_Resp messages. + 16 + 23 + read-write + + + SYNC + Sync Message Transmission Interval SettingThese bits set the interval for the transmission of Sync messages. The setting is also placed in the logMessageInterval field of transmitted Sync messages. + 8 + 15 + read-write + + + ANCE + Announce Message Transmission Interval SettingThese bits set the interval for the transmission of Announce messages. + 0 + 7 + read-write + + + + + SYRLIR + SYNFP Received logMessageInterval Value Indication Register + 0x0C4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + DRESP + Delay_Resp Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Delay_Resp message. + 16 + 23 + read-only + + + SYNC + Sync Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Sync message. + 8 + 15 + read-only + + + ANCE + Announce Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Announce message. + 0 + 7 + read-only + + + + + OFMRU + offsetFromMaster Value Registers + 0x0C8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + OFMRU + These bits indicate the higher-order 32 bits of the calculated offsetFromMaster value. + 0 + 31 + read-only + + + + + OFMRL + offsetFromMaster Value Registers + 0x0CC + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + OFMRL + These bits indicate the lower-order 32 bits of the calculated offsetFromMaster value. + 0 + 31 + read-only + + + + + MPDRU + meanPathDelay Value Registers + 0x0D0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MPDRU + These bits indicate the higher-order 32 bits of the calculated meanPathDelay value. + 0 + 31 + read-only + + + + + MPDRL + meanPathDelay Value Registers + 0x0D4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MPDRL + These bits indicate the lower-order 32 bits of the calculated meanPathDelay value. + 0 + 31 + read-only + + + + + GMPR + grandmasterPriority Field Setting Register + 0x0E0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMPR1 + grandmasterPriority1 Field Value SettingThese bits are used to set the value of the grandmasterPriority1 fields of Announce messages. + 16 + 23 + read-write + + + GMPR2 + grandmasterPriority2 Field Value SettingThese bits are used to set the value of the grandmasterPriority2 fields of Announce messages. + 0 + 7 + read-write + + + + + GMCQR + grandmasterClockQuality Field Setting Register + 0x0E4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMCQR + These bits are used to set the value of the grandmasterClockQuality fields of Announce messages. The correspondence between bits and the grandmasterClockQuality fields is as listed below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 to b0: offsetScaledLogVariance + 0 + 31 + read-write + + + + + GMIDRU + grandmasterIdentity Field Setting Registers + 0x0E8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMIDRU + These bits hold the setting for the higher-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. + 0 + 31 + read-write + + + + + GMIDRL + grandmasterIdentity Field Setting Registers + 0x0EC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMIDRL + These bits hold the setting for the lower-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. + 0 + 31 + read-write + + + + + CUOTSR + currentUtcOffset/timeSource Field Setting Register + 0x0F0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CUTO + currentUtcOffset Field SettingThese bits set the value of the currentUtcOffset fields of Announce messages. + 16 + 31 + read-write + + + TSRC + timeSource Field SettingThese bits set the value of the timeSource fields of Announce messages. + 0 + 7 + read-write + + + + + SRR + stepsRemoved Field Setting Register + 0x0F4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SRMV + stepsRemoved Field Value SettingThese bits set the value of the stepsRemoved fields of Announce messages. + 0 + 15 + read-write + + + + + PPMACRU + PTP-primary Message Destination MAC Address Setting Registers + 0x100 + 32 + read-write + 0x00011B19 + 0xFFFFFFFF + + + PPMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-primary messages. + 0 + 23 + read-write + + + + + PPMACRL + PTP-primary Message Destination MAC Address Setting Registers + 0x104 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PPMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-primary messages. + 0 + 23 + read-write + + + + + PDMACRU + PTP-pdelay Message MAC Address Setting Registers + 0x108 + 32 + read-write + 0x000180C2 + 0xFFFFFFFF + + + PDMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-pdelay messages. + 0 + 23 + read-write + + + + + PDMACRL + PTP-pdelay Message MAC Address Setting Registers + 0x10C + 32 + read-write + 0x0000000E + 0xFFFFFFFF + + + PDMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages. + 0 + 23 + read-write + + + + + PETYPER + PTP Message EtherType Setting Register + 0x110 + 32 + read-write + 0x000088F7 + 0xFFFFFFFF + + + TYPE + PTP Message EtherType Value SettingThese bits hold the setting for the EtherType field value for frames in the Ethernet II format. + 0 + 15 + read-write + + + + + PPIPR + PTP-primary Message Destination IP Address Setting Register + 0x120 + 32 + read-write + 0xE0000181 + 0xFFFFFFFF + + + PPIPR + These bits hold the setting for the destination IP address for PTPprimary messages. + 0 + 31 + read-write + + + + + PDIPR + PTP-pdelay Message Destination IP Address Setting Register + 0x124 + 32 + read-write + 0xE000006B + 0xFFFFFFFF + + + PDIPR + These bits hold the setting for the destination IP address for PTPpdelay messages. + 0 + 31 + read-write + + + + + PETOSR + PTP Event Message TOS Setting Register + 0x128 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EVTO + PTP Event Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP event messages. + 0 + 7 + read-write + + + + + PGTOSR + PTP general Message TOS Setting Register + 0x12C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GETO + PTP general Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP general messages. + 0 + 7 + read-write + + + + + PPTTLR + PTP-primary Message TTL Setting Register + 0x130 + 32 + read-write + 0x00000080 + 0xFFFFFFFF + + + PRTL + PTP-primary Message TTL Field Value SettingThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-primary messages. + 0 + 7 + read-write + + + + + PDTTLR + PTP-pdelay Message TTL Setting Register + 0x134 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + PDTL + PTP-pdelay Message TTL Field ValueThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-pdelay messages. + 0 + 7 + read-write + + + + + PEUDPR + PTP Event Message UDP Destination Port Number Setting Register + 0x138 + 32 + read-write + 0x0000013F + 0xFFFFFFFF + + + EVUPT + PTP Event Message Destination Port Number SettingThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP event messages. + 0 + 15 + read-write + + + + + PGUDPR + PTP general Message UDP Destination Port Number Setting Register + 0x13C + 32 + read-write + 0x00000140 + 0xFFFFFFFF + + + GEUPT + PTP general Message Destination Port NumberThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP general messages. + 0 + 15 + read-write + + + + + FFLTR + Frame Reception Filter Setting Register + 0x140 + 32 + read-write + 0x00010000 + 0xFFFFFFFF + + + EXTPRM + Extended Promiscuous ModeSetting + 16 + 16 + read-write + + + 0 + Normal operation (unicast frames addressed to the EPTPC are received, filtering of PTP frames is applied, multicast filtering is applied, and all broadcast frames are received). + #0 + + + 1 + Extended promiscuous mode (all frames are received) + #1 + + + + + ENB + Reception Filter EnableNOTE: The setting of these bits is only effective when EXTPRM=0. + 2 + 2 + read-write + + + 0 + Filtering is disabled (all multicast frames are received). + #0 + + + 1 + See PRT and SEL bit. + #1 + + + + + PRT + Frame Reception EnableNOTE: The setting of these bits is only effective when EXTPRM=0 and ENB=1. + 1 + 1 + read-write + + + 0 + Do not receive multicast frames. + #0 + + + 1 + See SEL bit. + #1 + + + + + SEL + Receive MAC Address SelectNOTE: The setting of these bits is only effective when EXTPRM=0, ENB=1and RPT=1. + 0 + 0 + read-write + + + 0 + Only receive multicast frames matching the MAC address setting in FMAC0R(U/L). + #0 + + + 1 + Only receive multicast frames matching the MAC address setting in FMAC1R(U/L). + #1 + + + + + + + DASYMRU + Asymmetric Delay Setting Registers + 0x1C0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DASYMRU + These bits hold the setting for the higher-order 16 bits of the asymmetric delay value. + 0 + 15 + read-write + + + + + DASYMRL + Asymmetric Delay Setting Registers + 0x1C4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DASYMRL + These bits hold the setting for the lower-order 32 bits of the asymmetric delay value. + 0 + 31 + read-write + + + + + TSLATR + Timestamp Latency Setting Register + 0x1C8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INGP + Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports. + 16 + 31 + read-write + + + EGP + Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports. + 0 + 15 + read-write + + + + + SYCONFR + SYNFP Operation Setting Register + 0x1CC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TCMOD + TC Mode Setting + 20 + 20 + read-write + + + 0 + E2E TC + #0 + + + 1 + P2P TC + #1 + + + + + FILDIS + Receive Message domainNumber Filter Disable + 16 + 16 + read-write + + + 0 + Filtering conditions for the reception of PTP messages include comparison with the domainNumber field. + #0 + + + 1 + Filtering conditions for the reception of PTP messages do not include comparison with the domainNumber field. + #1 + + + + + SBDIS + Sync Message Transmission Bandwidth Securing Disable + 12 + 12 + read-write + + + 0 + Securing of the bandwidth for the transmission of SYNC messages is enabled (transfer by the EDMAC is given lower priority). + #0 + + + 1 + Securing of the bandwidth for the transmission of SYNC messages is disabled (transfer by the EDMAC is given higher priority). + #1 + + + + + TCYC + PTP Message Transmission Interval SettingThese bits are used to set the time from the completion of one transmission to the start of the next in cycles of the transmission clock. A value n in these bits means that a transmission interval of n cycles will be secured.No interval is secured if the setting is 00h.We recommend the setting 28h (40 cycles). + 0 + 7 + read-write + + + + + SYFORMR + SYNFP Frame Format Setting Register + 0x1D0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FORM1 + Ethernet Frame Format Setting + 1 + 1 + read-write + + + 0 + Set this bit to 0 (Ethernet II frame format). + #0 + + + 1 + Setting prohibited + #1 + + + + + FORM0 + Ethernet/UDP Encapsulation + 0 + 0 + read-write + + + 0 + PTP directly over Ethernet + #0 + + + 1 + PTP over UDP/IPv4 + #1 + + + + + + + RSTOUTR + Response Message Reception Timeout Register + 0x1D4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RSTOUTR + Response Message Reception Timeout Time SettingA response message not being received within n x 1024 (ns), where n is the setting, is judged to represent a timeout. + 0 + 31 + read-write + + + + + + + R_ETHERC_EPTPC1 + 0x40065C00 + + + R_ETHERC_EPTPC_CFG + Ethernet PTP Configuration + 0x40064500 + + 0x00000000 + 0x00C + registers + + + + PTRSTR + EPTPC Reset Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + EPTPC Software Reset + 0 + 0 + read-write + + + 0 + Do not reset the EPTPC + #0 + + + 1 + Reset the EPTPC. Do not access the EPTPC-related registers other than this register while a software reset is being issued. + #1 + + + + + + + STCSELR + STCA Clock Select Register + 0x04 + 32 + read-write + 0x00000006 + 0xFFFFFFFF + + + SCLKSEL + STCA Clock Select + 8 + 10 + read-write + + + 000 + PCLKA clock divided by 1 to 6 + #000 + + + 010 + Input clock from the REF50CK0 pin + #010 + + + 011 + Input clock from the REF50CK1 pin + #011 + + + others + Settings other than above are prohibited. + true + + + + + SCLKDIV + PCLKA Clock Frequency Division + 0 + 2 + read-write + + + 001 + 1 + #001 + + + 010 + 1/2 + #010 + + + 011 + 1/3 + #011 + + + 100 + 1/4 + #100 + + + 101 + 1/5 + #101 + + + 110 + 1/6 + #110 + + + others + Settings other than above are prohibited. + true + + + + + + + BYPASS + Bypass 1588 module Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BYPASS1 + Bypass 1588 module for Ether 1ch + 16 + 16 + read-write + + + 0 + to use 1588 module for Ether 1ch + #0 + + + 1 + to bypass 1588 module for Ether 1ch + #1 + + + + + BYPASS0 + Bypass 1588 module for Ether 0ch + 0 + 0 + read-write + + + 0 + to use 1588 module for Ether 0ch + #0 + + + 1 + to bypass 1588 module for Ether 0ch + #1 + + + + + + + + + R_ETHERC_EPTPC_COMMON + Ethernet PTP Controller Common + 0x40065000 + + 0x00000000 + 0x008 + registers + + + 0x00000010 + 0x008 + registers + + + 0x00000040 + 0x008 + registers + + + 0x00000050 + 0x00C + registers + + + 0x00000060 + 0x010 + registers + + + 0x00000080 + 0x008 + registers + + + 0x00000090 + 0x010 + registers + + + 0x000000B0 + 0x00C + registers + + + 0x00000124 + 0x020 + registers + + + 0x00000170 + 0x00C + registers + + + 0x00000210 + 0x00C + registers + + + 0x000002D0 + 0x00C + registers + + + 0x00000300 + 0x060 + registers + + + 0x0000037C + 0x04 + registers + + + 0x00000400 + 0x008 + registers + + + 0x00000410 + 0x014 + registers + + + 0x00000430 + 0x008 + registers + + + + 6 + 0x10 + TM[%s] + Timer Setting Registers + 0x300 + + STTRU + Timer Start Time Setting Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TMSTTRU + These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds. + 0 + 31 + read-write + + + + + STTRL + Timer Start Time Setting Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TMSTTRL + These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds. + 0 + 31 + read-write + + + + + CYCR + Timer Cycle Setting Registers + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TMCYCR + These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock. + 0 + 29 + read-write + + + + + PLSR + Timer Pulse Width Setting Register + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TMPLSR + These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock. + 0 + 28 + read-write + + + + + + 2 + 0x8 + PR[%s] + Local MAC Address Registers + 0x410 + + MACRU + Channel Local MAC Address Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRMACRU + These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. + 0 + 23 + read-write + + + + + MACRL + Channel Local MAC Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRMACRL + These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. + 0 + 23 + read-write + + + + + + MIESR + MINT Interrupt Source Status Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CYC5 + Pulse Output Timer 5 Rising Edge Detection Flag + 21 + 21 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 5 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 5 is detected. + #1 + + + + + CYC4 + Pulse Output Timer 4 Rising Edge Detection Flag + 20 + 20 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 4 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 4 is detected. + #1 + + + + + CYC3 + Pulse Output Timer 3 Rising Edge Detection Flag + 19 + 19 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 3 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 3 is detected. + #1 + + + + + CYC2 + Pulse Output Timer 2 Rising Edge Detection Flag + 18 + 18 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 2 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 2 is detected. + #1 + + + + + CYC1 + Pulse Output Timer 1 Rising Edge Detection Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 1 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 1 is detected. + #1 + + + + + CYC0 + Pulse Output Timer 0 Rising Edge Detection Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 0 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 0 is detected. + #1 + + + + + PRC + PRC-TC Status Flag + 3 + 3 + read-only + + + 0 + No change in the state of the PRC-TC module + #0 + + + 1 + A change in the state of the PRC-TC module + #1 + + + + + SY1 + SYNFP1 Status Flag + 2 + 2 + read-only + + + 0 + No change in the state of the SYNFP1 module + #0 + + + 1 + A change in the state of the SYNFP1 module + #1 + + + + + SY0 + SYNFP0 Status Flag + 1 + 1 + read-only + + + 0 + No change in the state of the SYNFP0 module + #0 + + + 1 + A change in the state of the SYNFP0 module + #1 + + + + + ST + STCA Status Flag + 0 + 0 + read-only + + + 0 + No change in the state of the STCA module + #0 + + + 1 + A change in the state of the STCA module + #1 + + + + + + + MIEIPR + MINT Interrupt Request Permission Register + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CYC5 + Pulse Output Timer 5 Rising Edge Detection Interrupt Request Permission + 21 + 21 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. + #1 + + + + + CYC4 + Pulse Output Timer 4 Rising Edge Detection Interrupt Request Permission + 20 + 20 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. + #1 + + + + + CYC3 + Pulse Output Timer 3 Rising Edge Detection Interrupt Request Permission + 19 + 19 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. + #1 + + + + + CYC2 + Pulse Output Timer 2 Rising Edge Detection Interrupt Request Permission + 18 + 18 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. + #1 + + + + + CYC1 + Pulse Output Timer 1 Rising Edge Detection Interrupt Request Permission + 17 + 17 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. + #1 + + + + + CYC0 + Pulse Output Timer 0 Rising Edge Detection Interrupt Request Permission + 16 + 16 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. + #1 + + + + + PRC + PRC-TC Status Interrupt Request Permission + 3 + 3 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the PRC-TC status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the PRCTC status flag. + #1 + + + + + SY1 + SYNFP1 Status Interrupt Request Permission + 2 + 2 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the SYNFP1 status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the SYNFP1 status flag. + #1 + + + + + SY0 + SYNFP0 Status Interrupt Request Permission + 1 + 1 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the SYNFP0 status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the SYNFP0 status flag. + #1 + + + + + ST + STCA Status Interrupt Request Permission + 0 + 0 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the STCA status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the STCA status flag. + #1 + + + + + + + ELIPPR + ELC Output/ETHER_IPLS Interrupt Request Permission Register + 0x010 + 32 + read-write + 0x00003F3F + 0xFFFFFFFF + + + PLSN + Pulse Output Timer Falling Edge Detection IPLS Interrupt Request Permission + 24 + 24 + read-write + + + 0 + Prohibits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. + #0 + + + 1 + Permits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. + #1 + + + + + PLSP + Pulse Output Timer Rising Edge Detection IPLS Interrupt Request Permission + 16 + 16 + read-write + + + 0 + Prohibits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. + #0 + + + 1 + Permits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. + #1 + + + + + CYCN5 + Pulse Output Timer 5 Falling Edge Detection Event Output Enable + 13 + 13 + read-write + + + 0 + Falling edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. + #1 + + + + + CYCN4 + Pulse Output Timer 4 Falling Edge Detection Event Output Enable + 12 + 12 + read-write + + + 0 + Falling edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. + #1 + + + + + CYCN3 + Pulse Output Timer 3 Falling Edge Detection Event Output Enable + 11 + 11 + read-write + + + 0 + Falling edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. + #1 + + + + + CYCN2 + Pulse Output Timer 2 Falling Edge Detection Event Output Enable + 10 + 10 + read-write + + + 0 + Falling edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. + #1 + + + + + CYCN1 + Pulse Output Timer 1 Falling Edge Detection Event Output Enable + 9 + 9 + read-write + + + 0 + Falling edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. + #1 + + + + + CYCN0 + Pulse Output Timer 0 Falling Edge Detection Event Output Enable + 8 + 8 + read-write + + + 0 + Falling edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. + #1 + + + + + CYCP5 + Pulse Output Timer 5 Rising Edge Detection Event Output Enable + 5 + 5 + read-write + + + 0 + Rising edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. + #1 + + + + + CYCP4 + Pulse Output Timer 4 Rising Edge Detection Event Output Enable + 4 + 4 + read-write + + + 0 + Rising edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. + #1 + + + + + CYCP3 + Pulse Output Timer 3 Rising Edge Detection Event Output Enable + 3 + 3 + read-write + + + 0 + Rising edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. + #1 + + + + + CYCP2 + Pulse Output Timer 2 Rising Edge Detection Event Output Enable + 2 + 2 + read-write + + + 0 + Rising edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. + #1 + + + + + CYCP1 + Pulse Output Timer 1 Rising Edge Detection Event Output Enable + 1 + 1 + read-write + + + 0 + Rising edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. + #1 + + + + + CYCP0 + Pulse Output Timer 0 Rising Edge Detection Event Output Enable + 0 + 0 + read-write + + + 0 + Rising edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. + #1 + + + + + + + ELIPACR + ELC Output/IPLS Interrupt Permission Automatic Clearing Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLSN + ELIPPR.PLSN Bit Automatic Clearing + 24 + 24 + read-write + + + 0 + Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #0 + + + 1 + Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #1 + + + + + PLSP + ELIPPR.PLSP Bit Automatic Clearing + 16 + 16 + read-write + + + 0 + Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #0 + + + 1 + Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #1 + + + + + CYCN5 + ELIPPR.CYCN5 Bit Automatic Clearing + 13 + 13 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. + #1 + + + + + CYCN4 + ELIPPR.CYCN4 Bit Automatic Clearing + 12 + 12 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. + #1 + + + + + CYCN3 + ELIPPR.CYCN3 Bit Automatic Clearing + 11 + 11 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. + #1 + + + + + CYCN2 + ELIPPR.CYCN2 Bit Automatic Clearing + 10 + 10 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. + #1 + + + + + CYCN1 + ELIPPR.CYCN1 Bit Automatic Clearing + 9 + 9 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. + #1 + + + + + CYCN0 + ELIPPR.CYCN0 Bit Automatic Clearing + 8 + 8 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. + #1 + + + + + CYCP5 + ELIPPR.CYCP5 Bit Automatic Clearing + 5 + 5 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. + #1 + + + + + CYCP4 + ELIPPR.CYCP4 Bit Automatic Clearing + 4 + 4 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. + #1 + + + + + CYCP3 + ELIPPR.CYCP3 Bit Automatic Clearing + 3 + 3 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. + #1 + + + + + CYCP2 + ELIPPR.CYCP2 Bit Automatic Clearing + 2 + 2 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. + #1 + + + + + CYCP1 + ELIPPR.CYCP1 Bit Automatic Clearing + 1 + 1 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. + #1 + + + + + CYCP0 + ELIPPR.CYCP0 Bit Automatic Clearing + 0 + 0 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. + #1 + + + + + + + STSR + STCA Status Register + 0x040 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + W10D + Worst 10 Acquisition Completion Flag + 4 + 4 + read-write + oneToClear + + + 0 + Ten worst values not acquired yet + #0 + + + 1 + Ten worst values acquired + #1 + + + + + SYNTOUT + Sync Message Reception Timeout Detection Flag + 3 + 3 + read-write + oneToClear + + + 0 + Sync message reception timeout not detected + #0 + + + 1 + Sync message reception timeout detected + #1 + + + + + SYNCOUT + Synchronization Loss Detection Flag + 1 + 1 + read-write + oneToClear + + + 0 + Loss of synchronization not detected + #0 + + + 1 + Loss of synchronization detected + #1 + + + + + SYNC + Synchronized State Detection Flag + 0 + 0 + read-write + oneToClear + + + 0 + Synchronization not detected + #0 + + + 1 + Synchronization detected + #1 + + + + + + + STIPR + STCA Status Notification Permission Register + 0x044 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + W10D + W10D Status Notification Enable + 4 + 4 + read-write + + + 0 + Disable notification of the STSR.W10D state + #0 + + + 1 + Enable notification of the STSR.W10D state + #1 + + + + + SYNTOUT + SYNTOUT Status Notification Enable + 3 + 3 + read-write + + + 0 + Disable notification of the STSR.SYNTOUT state + #0 + + + 1 + Enable notification of the STSR.SYNTOUT state + #1 + + + + + SYNCOUT + SYNCOUT Status Notification Enable + 1 + 1 + read-write + + + 0 + Disable notification of the STSR.SYNCOUT state + #0 + + + 1 + Enable notification of the STSR.SYNCOUT state + #1 + + + + + SYNC + SYNC Status Notification Enable + 0 + 0 + read-write + + + 0 + Disable notification of the STSR.SYNC state + #0 + + + 1 + Enable notification of the STSR.SYNC state + #1 + + + + + + + STCFR + STCA Clock Frequency Setting Register + 0x050 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + STCF + STCA Clock Frequency + 0 + 1 + read-write + + + 00 + 20MHz + #00 + + + 01 + 25MHz + #01 + + + 10 + 50MHz + #10 + + + 11 + 100 MHz + #11 + + + + + + + STMR + STCA Operating Mode Register + 0x054 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALEN1 + Alarm Detection Enable 1 + 29 + 29 + read-write + + + 0 + The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. + #0 + + + 1 + The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. + #1 + + + + + ALEN0 + Alarm Detection Enable 0 + 28 + 28 + read-write + + + 0 + The STSR.SYNC or SYNCOUT flag is not set to 1 on detection of synchronization or loss of synchronization. + #0 + + + 1 + The STSR.SYNC or SYNCOUT flag is set to 1 on detection of synchronization or loss of synchronization. + #1 + + + + + DVTH + Synchronization Loss Detection Threshold Setting + 20 + 23 + read-write + + + 0x0 + None + 0x0 + + + others + (DVTH) time + true + + + + + SYTH + Synchronized State Detection Threshold Setting + 16 + 19 + read-write + + + 0x0 + None + 0x0 + + + others + (SYTH) time + true + + + + + W10S + Worst 10 Acquisition Control Select + 15 + 15 + read-write + + + 0 + Measurement is started by hardware and the value acquired in the PW10VR or MW10R register is used as the limit for filtering. + #0 + + + 1 + Measurement is started by the GETW10R.GW10 bit. Also, the value set in the PLIMITR or MLIMITR register is used as the limit for filtering. + #1 + + + + + CMOD + Time Synchronization Correction Mode + 13 + 13 + read-write + + + 0 + Mode 1 + #0 + + + 1 + Mode 2 + #1 + + + + + WINT + Worst 10 Acquisition Time + 0 + 7 + read-write + + + 0x00 + The worst 10 values are not acquired. + 0x00 + + + others + Sync message reception: (WINT) time + true + + + + + + + SYNTOR + Sync Message Reception Timeout Register + 0x058 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTOR + A Sync message not being received within 1024 x n (ns), where n is the setting, leads to a timeout for reception of Sync messages, leading to the STSR.SYNTOUT flag being set to 1. + 0 + 31 + read-write + + + + + IPTSELR + IPLS Interrupt Request Timer Select Register + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + IPTSEL5 + Pulse Output Timer 5 Select + 5 + 5 + read-write + + + 0 + Pulse output timer 5 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 5 is selected as a source of IPLS interrupt requests. + #1 + + + + + IPTSEL4 + Pulse Output Timer 4 Select + 4 + 4 + read-write + + + 0 + Pulse output timer 4 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 4 is selected as a source of IPLS interrupt requests. + #1 + + + + + IPTSEL3 + Pulse Output Timer 3 Select + 3 + 3 + read-write + + + 0 + Pulse output timer 3 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 3 is selected as a source of IPLS interrupt requests. + #1 + + + + + IPTSEL2 + Pulse Output Timer 2 Select + 2 + 2 + read-write + + + 0 + Pulse output timer 2 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 2 is selected as a source of IPLS interrupt requests. + #1 + + + + + IPTSEL1 + Pulse Output Timer 1 Select + 1 + 1 + read-write + + + 0 + Pulse output timer 1 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 1 is selected as a source of IPLS interrupt requests. + #1 + + + + + IPTSEL0 + Pulse Output Timer 0 Select + 0 + 0 + read-write + + + 0 + Pulse output timer 0 is not selected as a source of IPLS interrupt requests. + #0 + + + 1 + Pulse output timer 0 is selected as a source of IPLS interrupt requests. + #1 + + + + + + + MITSELR + MINT Interrupt Request Timer Select Register + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MINTEN5 + Pulse Output Timer 5 MINT Interrupt Output Enable + 5 + 5 + read-write + + + 0 + Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source. + #1 + + + + + MINTEN4 + Pulse Output Timer 4 MINT Interrupt Output Enable + 4 + 4 + read-write + + + 0 + Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source. + #1 + + + + + MINTEN3 + Pulse Output Timer 3 MINT Interrupt Output Enable + 3 + 3 + read-write + + + 0 + Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source. + #1 + + + + + MINTEN2 + Pulse Output Timer 2 MINT Interrupt Output Enable + 2 + 2 + read-write + + + 0 + Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source. + #1 + + + + + MINTEN1 + Pulse Output Timer 1 MINT Interrupt Output Enable + 1 + 1 + read-write + + + 0 + Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source. + #1 + + + + + MINTEN0 + Pulse Output Timer 0 MINT Interrupt Output Enable + 0 + 0 + read-write + + + 0 + Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source. + #0 + + + 1 + Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source. + #1 + + + + + + + ELTSELR + ELC Output Timer Select Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ELTDIS5 + Pulse Output Timer 5 Event Generation Disable + 5 + 5 + read-write + + + 0 + Pulse output timer 5 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 5 is not used for the generation of event signals for the ELC. + #1 + + + + + ELTDIS4 + Pulse Output Timer 4 Event Generation Disable + 4 + 4 + read-write + + + 0 + Pulse output timer 4 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 4 is not used for the generation of event signals for the ELC. + #1 + + + + + ELTDIS3 + Pulse Output Timer 3 Event Generation Disable + 3 + 3 + read-write + + + 0 + Pulse output timer 3 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 3 is not used for the generation of event signals for the ELC. + #1 + + + + + ELTDIS2 + Pulse Output Timer 2 Event Generation Disable + 2 + 2 + read-write + + + 0 + Pulse output timer 2 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 2 is not used for the generation of event signals for the ELC. + #1 + + + + + ELTDIS1 + Pulse Output Timer 1 Event Generation Disable + 1 + 1 + read-write + + + 0 + Pulse output timer 1 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 1 is not used for the generation of event signals for the ELC. + #1 + + + + + ELTDIS0 + Pulse Output Timer 0 Event Generation Disable + 0 + 0 + read-write + + + 0 + Pulse output timer 0 is used for the generation of event signals for the ELC. + #0 + + + 1 + Pulse output timer 0 is not used for the generation of event signals for the ELC. + #1 + + + + + + + STCHSELR + Time Synchronization Channel Select Register + 0x06C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYSEL + Timer Information Input SelectNOTE: Do not change the value of this bit while the SYNSTARTR.STR bit is 1. + 0 + 0 + read-write + + + 0 + Time information from synchronization from the SYNFP0 module is used. + #0 + + + 1 + Time information from synchronization from the SYNFP1 module is used. + #1 + + + + + + + SYNSTARTR + Slave Time Synchronization Start Register + 0x080 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + STR + Slave Time Synchronization Control + 0 + 0 + read-write + + + 0 + Slave time synchronization is stopped. + #0 + + + 1 + Slave time synchronization is started. + #1 + + + + + + + LCIVLDR + Local Time Counter Initial Value Load Directive Register + 0x084 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LOAD + Local Time Counter Initial Value Load Directive + 0 + 0 + write-only + + + 0 + The initial value is not loaded into the local time counter. + #0 + + + 1 + The initial value is loaded into the local time counter. + #1 + + + + + + + SYNTDARU + Synchronization Loss Detection Threshold Registers + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDARU + These bits hold the setting for the higher-order 32 bits of the threshold for detection of loss of synchronization. + 0 + 31 + read-write + + + + + SYNTDARL + Synchronization Loss Detection Threshold Registers + 0x094 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDARL + These bits hold the setting for the lower-order 32 bits of the threshold for detection of loss of synchronization. + 0 + 31 + read-write + + + + + SYNTDBRU + Synchronization Detection Threshold Registers + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDBRU + These bits hold the setting for the higher-order 32 bits of the threshold for detection of synchronization. + 0 + 31 + read-write + + + + + SYNTDBRL + Synchronization Detection Threshold Registers + 0x09C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDBRL + These bits hold the setting for the lower-order 32 bits of the threshold for detection of synchronization. + 0 + 31 + read-write + + + + + LCIVRU + Local Time Counter Initial Value Registers + 0x0B0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRU + These bits hold the setting for the higher-order 16 bits of the integer portion of the initial value for the local timer counter. + 0 + 15 + read-write + + + + + LCIVRM + Local Time Counter Initial Value Registers + 0x0B4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRM + These bits hold the setting for the lower-order 32 bits of the integer portion of the initial value for the local timer counter. + 0 + 31 + read-write + + + + + LCIVRL + Local Time Counter Initial Value Registers + 0x0B8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRL + These bits hold the setting for the fractional portion of the initial value of the local timer counter in nanoseconds. + 0 + 31 + read-write + + + + + GETW10R + Worst 10 Acquisition Directive Register + 0x124 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GW10 + Worst 10 Acquisition Directive + 0 + 0 + read-write + + + 0 + The worst-10 values are not acquired. + #0 + + + 1 + Starts acquisition of the worst-10 values. + #1 + + + + + + + PLIMITRU + Positive Gradient Limit Registers + 0x128 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLIMITRU + These bits hold the setting for the higher-order 31 bits of the limit for the positive gradient. + 0 + 30 + read-write + + + + + PLIMITRM + Positive Gradient Limit Registers + 0x12C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLIMITRM + These bits hold the setting for the middle-order 32 bits of the limit for the positive gradient. + 0 + 31 + read-write + + + + + PLIMITRL + Positive Gradient Limit Registers + 0x130 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLIMITRL + These bits hold the setting for the lower-order 32 bits of the limit for the positive gradient. + 0 + 31 + read-write + + + + + MLIMITRU + Negative Gradient Limit Registers + 0x134 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MLIMITRU + These bits hold the setting for the higher-order 31 bits of the limit for the negative gradient. + 0 + 30 + read-write + + + + + MLIMITRM + Negative Gradient Limit Registers + 0x138 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MLIMITRM + These bits hold the setting for the middle-order 32 bits of the limit for the negative gradient. + 0 + 31 + read-write + + + + + MLIMITRL + Negative Gradient Limit Registers + 0x13C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MLIMITRL + These bits hold the setting for the lower-order 32 bits of the limit for the negative gradient. + 0 + 31 + read-write + + + + + GETINFOR + Statistical Information Retention Control Register + 0x140 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INFO + Information Retention ControlNOTE: Once information fetching is directed, values of various statistical information read before completion of information fetching are not guaranteed. + 0 + 0 + read-write + + + 0 + Has no effects.(write) / Information retention is completed.(read) + #0 + + + 1 + Information is retained.(write) / Processing for information retention is in progress.(read) + #1 + + + + + + + LCCVRU + Local Time Counters + 0x170 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + LCCVRU + These bits are for reading the higher-order 16 bits of the integer portion of the local timer counter's value. + 0 + 15 + read-only + + + + + LCCVRM + Local Time Counters + 0x174 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + LCCVRM + These bits are for reading the lower-order 32 bits of the integer portion of the local timer counter's value. + 0 + 31 + read-only + + + + + LCCVRL + Local Time Counters + 0x178 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + LCCVRL + These bits are for reading the fractional portion of the local timer counter's value (in nanoseconds). + 0 + 31 + read-only + + + + + PW10VRU + Positive Gradient Worst 10 Value Registers + 0x210 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRU + These bits are for reading the higher-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + PW10VRM + Positive Gradient Worst 10 Value Registers + 0x214 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRM + These bits are for reading the middle-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + PW10VRL + Positive Gradient Worst 10 Value Registers + 0x218 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRL + These bits are for reading the lower-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + MW10RU + Negative Gradient Worst 10 Value Registers + 0x2D0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RU + These bits are for reading the higher-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + MW10RM + Negative Gradient Worst 10 Value Registers + 0x2D4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RM + These bits are for reading the middle-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + MW10RL + Negative Gradient Worst 10 Value Registers + 0x2D8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RL + These bits are for reading the lower-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + TMSTARTR + Timer Start Register + 0x37C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN5 + Pulse Output Timer 5 Start + 5 + 5 + read-write + + + 0 + Stops pulse output timer 5. + #0 + + + 1 + Starts pulse output timer 5. + #1 + + + + + EN4 + Pulse Output Timer 4 Start + 4 + 4 + read-write + + + 0 + Stops pulse output timer 4. + #0 + + + 1 + Starts pulse output timer 4. + #1 + + + + + EN3 + Pulse Output Timer 3 Start + 3 + 3 + read-write + + + 0 + Stops pulse output timer 3. + #0 + + + 1 + Starts pulse output timer 3. + #1 + + + + + EN2 + Pulse Output Timer 2 Start + 2 + 2 + read-write + + + 0 + Stops pulse output timer 2. + #0 + + + 1 + Starts pulse output timer 2. + #1 + + + + + EN1 + Pulse Output Timer 1 Start + 1 + 1 + read-write + + + 0 + Stops pulse output timer 1. + #0 + + + 1 + Starts pulse output timer 1. + #1 + + + + + EN0 + Pulse Output Timer 0 Start + 0 + 0 + read-write + + + 0 + Stops pulse output timer 0. + #0 + + + 1 + Starts pulse output timer 0. + #1 + + + + + + + PRSR + PRC-TC Status Register + 0x400 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + URE1 + Relay Packet Underflow Detection Flag 1 + 29 + 29 + read-write + oneToClear + + + 0 + No underflow in transfer of data from SYNFP0 to SYNFP1. + #0 + + + 1 + An underflow has been detected in transfer of data from SYNFP0 to SYNFP1. + #1 + + + + + URE0 + Relay Packet Underflow Detection Flag 0 + 28 + 28 + read-write + oneToClear + + + 0 + No underflow in transfer of data from SYNFP1 to SYNFP0. + #0 + + + 1 + An underflow has been detected in transfer of data from SYNFP1 to SYNFP0. + #1 + + + + + MACE + Originating MAC Address Mismatch Detection Flag + 8 + 8 + read-write + oneToClear + modify + + + 0 + A MAC address mismatch has not been detected. + #0 + + + 1 + A MAC address mismatch has been detected. + #1 + + + + + OVRE3 + Relay Packet Overflow Detection Flag 3 + 3 + 3 + read-write + oneToClear + modify + + + 0 + No overflow in transfer of data from SYNFP0 to SYNFP1. + #0 + + + 1 + An overflow has been detected in transfer of data from SYNFP0 to SYNFP1. + #1 + + + + + OVRE2 + Relay Packet Overflow Detection Flag 2 + 2 + 2 + read-write + oneToClear + modify + + + 0 + No overflow in transfer of data from SYNFP1 to SYNFP0. + #0 + + + 1 + An overflow has been detected in transfer of data from SYNFP1 to SYNFP0. + #1 + + + + + OVRE1 + Relay Packet Overflow Detection Flag 1 + 1 + 1 + read-write + oneToClear + modify + + + 0 + No overflow in transfer of data from SYNFP0 to PTPEDMAC. + #0 + + + 1 + An overflow has been detected in transfer of data from SYNFP0 to PTPEDMAC. + #1 + + + + + OVRE0 + Relay Packet Overflow Detection Flag 0 + 0 + 0 + read-write + oneToClear + modify + + + 0 + No overflow in transfer of data from SYNFP1 to PTPEDMAC. + #0 + + + 1 + An overflow has been detected in transfer of data from SYNFP1 to PTPEDMAC. + #1 + + + + + + + PRIPR + PRC-TC Status Notification Permission Register + 0x404 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + URE1 + PRSR.URE1 Status Notification Permission + 29 + 29 + read-write + + + 0 + Prohibits notification of the state of PRSR.URE1. + #0 + + + 1 + Permits notification of the state of PRSR.URE1. + #1 + + + + + URE0 + PRSR.URE0 Status Notification Permission + 28 + 28 + read-write + + + 0 + Prohibits notification of the state of PRSR.URE0. + #0 + + + 1 + Permits notification of the state of PRSR.URE0. + #1 + + + + + MACE + PRSR.MACE Status Notification Permission + 8 + 8 + read-write + + + 0 + Prohibits notification of the state of PRSR.MACE + #0 + + + 1 + Permits notification of the state of PRSR.MACE + #1 + + + + + OVRE3 + PRSR.OVRE3 Status Notification Permission + 3 + 3 + read-write + + + 0 + Prohibits notification of the state of PRSR.OVRE3. + #0 + + + 1 + Permits notification of the state of PRSR.OVRE3. + #1 + + + + + OVRE2 + PRSR.OVRE2 Status Notification Permission + 2 + 2 + read-write + + + 0 + Prohibits notification of the state of PRSR.OVRE2. + #0 + + + 1 + Permits notification of the state of PRSR.OVRE2. + #1 + + + + + OVRE1 + PRSR.OVRE1 Status Notification Permission + 1 + 1 + read-write + + + 0 + Prohibits notification of the state of PRSR.OVRE1. + #0 + + + 1 + Permits notification of the state of PRSR.OVRE1. + #1 + + + + + OVRE0 + PRSR.OVRE0 Status Notification Permission + 0 + 0 + read-write + + + 0 + Prohibits notification of the state of PRSR.OVRE0. + #0 + + + 1 + Permits notification of the state of PRSR.OVRE0. + #1 + + + + + + + TRNDISR + Packet Transmission Control Register + 0x420 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDIS + Packet Transmission Control + 0 + 1 + read-write + + + 00 + PTP packets are transmitted through both Ethernet port 0 and Ethernet port 1. + #00 + + + 01 + PTP packets are only transmitted through Ethernet port 0. + #01 + + + 10 + PTP packets are only transmitted through Ethernet port 1. + #10 + + + 11 + Setting prohibited + #11 + + + + + + + TRNMR + Relay Mode Register + 0x430 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FWD1 + Channel 1 Relay Enable + 9 + 9 + read-write + + + 0 + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 1 to port 0. + #0 + + + 1 + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 1 to port 0. + #1 + + + + + FWD0 + Channel 0 Relay Enable + 8 + 8 + read-write + + + 0 + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 0 to port 1. + #0 + + + 1 + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 0 to port 1. + #1 + + + + + MOD + Cut-Through Mode + 0 + 0 + read-write + + + 0 + Store-and-forward + #0 + + + 1 + Cut-through + #1 + + + + + + + TRNCTTDR + Cut-Through Transfer Start Threshold Register + 0x434 + 32 + read-write + 0x00000060 + 0xFFFFFFFF + + + THVAL + FIFO Read Start ThresholdThreshold for starting to read data from the relay FIFO in cut-through mode (specified as the number of bytes)NOTE1: A value cannot be set in the lower-order 2 bits. These bits are fixed to 0.NOTE2: A value of less than 96 bytes cannot be set. + 0 + 10 + read-write + + + + + + + R_FACI_HP_CMD + Flash Application Command Interface Command-Issuing Area + 0x407E0000 + + 0x00000000 + 4 + registers + + + + FACI_CMD16 + FACI Command Issuing Area (halfword access) + 0 + 16 + read-write + 0x0000 + 0xFFFF + + + FACI_CMD8 + FACI Command Issuing Area (halfword access) + FACI_CMD16 + 0 + 8 + read-write + 0x00 + 0xFF + + + + + R_FACI_HP + Flash Application Command Interface + 0x407FE000 + + 0x00000000 + 0x100 + registers + + + + FASTAT + Flash Access Status + 0x0010 + 8 + read-write + 0x00 + 0xFF + + + CFAE + Code Flash Access Error + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No code flash access error has occurred. + #0 + + + 1 + Code flash access error has occurred. + #1 + + + + + CMDLK + Command Lock + 4 + 4 + read-only + + + DFAE + Data Flash Access Error + 3 + 3 + read-write + zeroToClear + modify + + + ECRCT + 0 + 0 + read-only + + + + + FAEINT + Flash Access Error Interrupt Enable + 0x0014 + 8 + read-write + 0x99 + 0xFF + + + CFAEIE + Code Flash Access Error Interrupt Enable + 7 + 7 + read-write + + + 0 + Does not generate "intflerr" interrupt request when CFAE = "1". + #0 + + + 1 + Generates "intflerr" interrupt request when CFAE = "1". + #1 + + + + + CMDLKIE + Command Lock Interrupt Enable + 4 + 4 + read-write + + + 0 + Does not generate "intflerr" interrupt request when CMDLK = "1". + #0 + + + 1 + Generates "intflerr" interrupt request when CMDLK = "1". + #1 + + + + + DFAEIE + Data Flash Access Error Interrupt Enable + 3 + 3 + read-write + + + 0 + Does not generate "intflerr" interrupt request when DFAE = "1". + #0 + + + 1 + Generates "intflerr" interrupt request when DFAE = "1". + #1 + + + + + ECRCTIE + Error Correct Interrupt Enable + 0 + 0 + read-write + + + 0 + Does not generate "intflerr" interrupt request when ECRCT = "1". + #0 + + + 1 + Generates "intflerr" interrupt request when ECRCT = "1". + #1 + + + + + + + FRDYIE + Flash Ready Interrupt Enable + 0x0018 + 8 + read-write + 0x00 + 0xFF + + + FRDYIE + FRDY Interrupt Enable + 0 + 0 + read-write + + + 0 + Does not generate "intflend" interrupt request when FRDY is changed from "0" to "1". + #0 + + + 1 + Generates "intflend" interrupt request when FRDY is changed from "0" to "1". + #1 + + + + + + + FSADDR + Flash Start Address + 0x0030 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FSA + Start Address of Flash Sequencer Command Target Area + These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. + 0 + 31 + read-write + + + others + Specifies start address for each command processing. + true + + + + + + + FEADDR + Flash End Address + 0x0034 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FEA + End Address of Flash Sequencer Command Target Area + Specifies end address of target area in "Blank Check" command. + These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. + 0 + 31 + read-write + + + + + FSTATR + Flash Status + 0x0080 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + EBFULL + FDMYECC Buffer Full + 18 + 18 + read-only + + + 0 + ECC Buffer is not full + #0 + + + 1 + ECC Buffer is full + #1 + + + + + OTPDTCT + OTP Bit ECC 2-Bit Error Detection Monitoring Bit + 17 + 17 + read-only + + + 0 + No error has been detected. + #0 + + + 1 + An error has been detected. + #1 + + + + + OTPCRCT + OTP Bit ECC 1-Bit Error Correction Monitoring Bit + 16 + 16 + read-only + + + 0 + No error has been corrected. + #0 + + + 1 + An error has been corrected. + #1 + + + + + FRDY + Flash Ready + 15 + 15 + read-only + + + 0 + "Program", "DMA Program", "Erase", "Program" or "Erase" command suspension, "Forced Stop", "Blank Check", "Config Program", "Config Clear", "Lock Bit Program", "Lock Bit Read", or "OTP Program" is processing. + #0 + + + 1 + None of the above is in progress. + #1 + + + + + ILGLERR + Illegal Command Error + 14 + 14 + read-only + + + 0 + Flash sequencer has not detected any illegal command or illegal flash memory access. + #0 + + + 1 + Flash sequencer has detected an illegal command or illegal flash memory access + #1 + + + + + ERSERR + Erasure Error + 13 + 13 + read-only + + + 0 + Erasure processing has been completed successfully + #0 + + + 1 + An error has occurred during erasure + #1 + + + + + PRGERR + Programming Error + 12 + 12 + read-only + + + 0 + Programming has been completed successfully + #0 + + + 1 + An error has occurred during programming + #1 + + + + + SUSRDY + Suspend Ready + 11 + 11 + read-only + + + 0 + Flash sequencer cannot accept "Program/Erase Suspend" command. + #0 + + + 1 + Flash sequencer can accept "Program/Erase Suspend" command. + #1 + + + + + DBFULL + Data Buffer Full + 10 + 10 + read-only + + + 0 + Data Buffer is not full + #0 + + + + + ERSSPD + Erasure-Suspended Status + 9 + 9 + read-only + + + 0 + Flash sequencer is in status other than the below mentioned. + #0 + + + 1 + Flash sequencer is in erasure suspension process or erasure-suspended status. + #1 + + + + + PRGSPD + Programming-Suspended Status + 8 + 8 + read-only + + + 0 + Flash sequencer is in status other than the below mentioned. + #0 + + + 1 + Flash sequencer is in programming suspension process or programming-suspended status. + #1 + + + + + FCUERR + FCU Error + 7 + 7 + read-only + + + 0 + No error has occurred during FPCC processing. + #0 + + + 1 + An error has occurred during FPCC processing. + #1 + + + + + FHVEERR + "fhve" Error + 6 + 6 + read-only + + + 0 + No error has been detected. + #0 + + + 1 + An error has been detected. + #1 + + + + + CFGDTCT + Config Area ECC 2-Bit Error Detection Monitoring Bit + 5 + 5 + read-only + + + 0 + No error has been detected. + #0 + + + 1 + An error has been detected. + #1 + + + + + CFGCRCT + Config Area ECC 1-Bit Error Correction Monitoring Bit + 4 + 4 + read-only + + + 0 + No error has been corrected. + #0 + + + 1 + An error has been corrected. + #1 + + + + + TBLDTCT + Table Area ECC 2-Bit Error Detection Monitoring Bit + 3 + 3 + read-only + + + 0 + No error has been detected. + #0 + + + 1 + An error has been detected. + #1 + + + + + TBLCRCT + Table Area ECC 1-Bit Error Correction Monitoring Bit + 2 + 2 + read-only + + + 0 + No error has been corrected. + #0 + + + 1 + An error has been corrected. + #1 + + + + + + + FENTRYR + Program/Erase Mode Entry + 0x0084 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + KEY Code + 8 + 15 + write-only + + + 0xAA + Writing to the other bits in this register is enabled. + 0xAA + + + others + Writing to the other bits in this register is disabled. + true + + + + + FENTRYD + Data Flash P/E Mode Entry + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits. + 7 + 7 + read-write + + + 0 + Data flash is in "Read Mode" + #0 + + + 1 + Data flash is in "P/E Mode" + #1 + + + + + FENTRYC + Code Flash P/E Mode Entry + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits + 0 + 0 + read-write + + + 0 + Code flash is in "Read Mode" + #0 + + + 1 + Code flash is in "P/E Mode" + #1 + + + + + + + FSUINITR + Flash Sequencer Set-up Initialize + 0x008C + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + KEY Code + 8 + 15 + write-only + + + 0x2D + Writing to the other bits in this register is enabled. + 0x2D + + + others + Writing to the other bits in this register is disabled. + true + + + + + SUINIT + Set-up Initialization + This bit can be written when FRDY bit of FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'2D is written to KEY bits. + 0 + 0 + read-write + + + 0 + Set-up registers keep its' value. + #0 + + + 1 + Set-up registers are initialized. + #1 + + + + + + + FCMDR + Flash Sequencer Command + 0x00A0 + 16 + read-only + 0x0000 + 0xFFFF + + + CMDR + Command Register + 8 + 15 + read-only + + + others + These bits store the latest command accepted by FACI. + true + + + + + PCMDR + Previous Command Register + 0 + 7 + read-only + + + others + These bits store previous command accepted by FACI. + true + + + + + + + FPESTAT + Program/Erase Error Status + 0x00C0 + 16 + read-only + 0x0000 + 0xFFFF + + + PEERRST + P/E Error Status + 0 + 7 + read-only + + + 0x01 + A write attempt made to an area protected by the lock bits + 0x01 + + + 0x02 + A write error caused by other source than the above + 0x02 + + + 0x11 + An erase attempt made to an area protected by the lock bits + 0x11 + + + 0x12 + An erase error caused by other source than the above + 0x12 + + + others + Reserved + true + + + + + + + FBCCNT + Blank Check Control + 0x00D0 + 8 + read-write + 0x00 + 0xFF + + + BCDIR + Blank Check Direction + 0 + 0 + read-write + + + 0 + Blank check is executed from smaller address to larger address. (Incremental mode) + #0 + + + 1 + Blank check is executed from larger address to smaller address. (Decremental mode) + #1 + + + + + + + FBCSTAT + Blank Check Status + 0x00D4 + 8 + read-only + 0x00 + 0xFF + + + BCST + Blank Check Status Bit + 0 + 0 + read-only + + + 0 + The target area is erased (blank). + #0 + + + 1 + The target area is filled with 0s and/or 1s. + #1 + + + + + + + FPSADDR + Programmed Area Start Address + 0x00D8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PSADR + Programmed Area Start Address + NOTE: Indicates address of the first programmed data which is found in "Blank Check" command execution. + 0 + 18 + read-only + + + + + FAWMON + Flash Access Window Monitor + 0x0DC + 32 + read-only + 0x00000000 + 0x00000000 + + + BTFLG + Flag of Start-Up area select for Boot Swap + 31 + 31 + read-only + + + 0 + The start-up area is the alternate area (sector 1) + #0 + + + 1 + The start-up area is the default area (sector 0) + #1 + + + + + FAWE + End Sector Address for Access Window + NOTE: These bits indicate the end sector address for setting the access window that is located in the configuration area. + 16 + 26 + read-only + + + FSPR + Protection Flag of programming the Access Window, Boot Flag and Temporary Boot Swap Control and "Config Clear" command execution + 15 + 15 + read-only + + + 0 + Protected state + #0 + + + 1 + Non-protected state + #1 + + + + + FAWS + Start Sector Address for Access Window + NOTE: These bits indicate the start sector address for setting the access window that is located in the configuration area. + 0 + 10 + read-only + + + + + FCPSR + FCU Process Switch + 0x00E0 + 16 + read-write + 0x0000 + 0xFFFF + + + ESUSPMD + Erasure-Suspended Mode + 0 + 0 + read-write + + + 0 + Suspension-priority mode + #0 + + + 1 + Erasure-priority mode + #1 + + + + + + + FPCKAR + Flash Sequencer Processing Clock Frequency Notification + 0x00E4 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + KEY Code + 8 + 15 + write-only + + + 0x1E + Writing to the other bits in this register is enabled. + 0x1E + + + others + Writing to the other bits in this register is disabled. + true + + + + + PCKA + Flash Sequencer Processing Clock Frequency + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'1E is written to KEY bits. + 0 + 7 + read-write + + + others + Notifies operating frequency of clkf. + true + + + + + + + FSUACR + Flash Start-Up Area Control Register + 0x00E8 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + KEY Code + 8 + 15 + write-only + + + 0x66 + Writing to the other bits in this register is enabled. + 0x66 + + + others + Writing to the other bits in this register is disabled. + true + + + + + SAS + Start Up Area Select + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'66 is written to KEY bits. + 0 + 1 + read-write + + + 10 + The start-up area is temporarily switched to the default area (sector 0) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. + #10 + + + 11 + The start-up area is temporarily switched to the alternate area (sector 1) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. + #11 + + + others + The start-up area is selected according to the start-up area setting of the configuration area (BTFLG bit). + true + + + + + + + + + R_FACI_LP + Flash Application Command Interface + 0x407EC000 + + 0x00000000 + 0x400 + registers + + + + DFLCTL + Flash P/E Mode Control Register + 0x090 + 8 + read-write + 0x00 + 0xFF + + + FPMCR + Flash P/E Mode Control Register + 0x100 + 8 + read-write + 0x08 + 0xFF + + + FMS2 + Flash Operating Mode Select 2. +Refer to the description of the FMS0 bit. + 7 + 7 + read-write + + + VLPE + Low-Voltage P/E Mode Enable + 6 + 6 + read-write + + + 0 + Low-voltage programming is disabled + #0 + + + 1 + Low-voltage programming is enabled + #1 + + + + + FMS1 + The bit to make data flash a programming mode +Refer to the description of the FMS0 bit. + 4 + 4 + read-write + + + RPDIS + Code Flash P/E Disable + 3 + 3 + read-write + + + 0 + The programming of the code flash is enabled + #0 + + + 1 + The programming of the code flash is disabled + #1 + + + + + FMS0 + Flash Operating Mode Select 0 +FMS2,1,0: + 000: Read mode + 011: Discharge mode 1 + 111: Discharge mode 2 + 101: Code Flash P/E mode + 010: Data flash P/E mode + Others: Setting prohibited. + 1 + 1 + read-write + + + + + FASR + Flash Area Select Register + 0x104 + 8 + read-write + 0x00 + 0xFF + + + EXS + Extra area select + 0 + 0 + read-write + + + 0 + User area or data area + #0 + + + 1 + Extra area + #1 + + + + + + + FSARL + Flash Processing Start Address Register L + 0x108 + 16 + read-write + 0x0000 + 0xFFFF + + + FSAR15_0 + Start address + 0 + 15 + read-write + + + + + FSARH + Flash Processing Start Address Register H + 0x110 + 16 + read-write + 0x0000 + 0xFFFF + + + FSAR31_25 + Start address + 9 + 15 + read-write + + + FSAR20_16 + Start address + 0 + 4 + read-write + + + + + FCR + Flash Control Register + 0x114 + 8 + read-write + 0x00 + 0xFF + + + OPST + Processing Start + 7 + 7 + read-write + + + 0 + Processing stops. + #0 + + + 1 + Processing starts. + #1 + + + + + STOP + Forced Processing Stop + 6 + 6 + read-write + + + DRC + Data Read Completion + 4 + 4 + read-write + + + 0 + Data is not read or next data is requested. + #0 + + + 1 + Data reading is completed. + #1 + + + + + CMD + Software Command Setting + 0 + 3 + read-write + + + 0001 + Program + #0001 + + + 0011 + Blank check + #0011 + + + 0100 + Block erase + #0100 + + + 0101 + Consecutive read + #0101 + + + 0111 + Chip erase + #0111 + + + others + Setting prohibited + true + + + + + + + FEARL + Flash Processing End Address Register L + 0x118 + 16 + read-write + 0x0000 + 0xFFFF + + + FEAR15_0 + End address + 0 + 15 + read-write + + + + + FEARH + Flash Processing End Address Register H + 0x120 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FEAR31_25 + End address + 9 + 15 + read-write + + + FEAR20_16 + End address + 0 + 4 + read-write + + + + + FRESETR + Flash Reset Register + 0x124 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRESET + Software Reset of the registers + 0 + 0 + read-write + + + 0 + No effect + #0 + + + 1 + The registers relates to the flash programming are reset. + #1 + + + + + + + FSTATR00 + Flash Status Register00 + 0x128 + 32 + read-only + 0x00000000 + 0xFFFFFFEF + + + EILGLERR + Extra Area Illegal Command Error Flag + 5 + 5 + read-only + + + 0 + No illegal command or illegal access to the extra area is detected. + #0 + + + 1 + An illegal command or illegal access to the extra area is detected. + #1 + + + + + ILGLERR + Illegal Command Error Flag + 4 + 4 + read-only + + + 0 + No illegal software command or illegal access is detected. + #0 + + + 1 + An illegal command or illegal access is detected. + #1 + + + + + BCERR0 + Blank Check Error Flag0 + 3 + 3 + read-only + + + 0 + Blank checking terminates normally. + #0 + + + 1 + An error occurs during blank checking. + #1 + + + + + PRGERR01 + Program Error Flag 01 + 2 + 2 + read-only + + + 0 + Programming by the FEXCR register terminates normally. + #0 + + + 1 + An error occurs during programming. + #1 + + + + + PRGERR0 + Program Error Flag0 + 1 + 1 + read-only + + + 0 + Programming terminates normally. + #0 + + + 1 + An error occurs during programming. + #1 + + + + + ERERR0 + Erase Error Flag0 + 0 + 0 + read-only + + + 0 + Erasure terminates normally. + #0 + + + 1 + An error occurs during erasure. + #1 + + + + + + + FSTATR1 + Flash Status Register1 + 0x12C + 32 + read-only + 0x00000000 + 0xFFFFFFFB + + + EXRDY + End status signal of a Extra programming sequencer + 7 + 7 + read-only + + + 0 + Other than below + #0 + + + 1 + The software command of the FEXCR register is terminated. + #1 + + + + + FRDY + End status signal of a sequencer + 6 + 6 + read-only + + + 0 + Other than below + #0 + + + 1 + The software command of the FCR register is terminated. + #1 + + + + + DRRDY + Data read request + 1 + 1 + read-only + + + 0 + Other than below + #0 + + + 1 + The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers. + #1 + + + + + + + FWBL0 + Flash Write Buffer Register L0 + 0x130 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDATA + Program data of the program command + 0 + 15 + read-write + + + + + FWBH0 + Flash Write Buffer Register H0 + 0x138 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDATA + Program data of the program command + 0 + 15 + + + + + FSTATR01 + Flash Status Register01 + 0x13C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + BCERR1 + Blank Check Error Flag1 + 3 + 3 + + + 0 + Blank checking terminates normally. + #0 + + + 1 + An error occurs during blank checking. + #1 + + + + + PRGERR1 + Program Error Flag1 + 1 + 1 + + + 0 + Programming terminates normally. + #0 + + + 1 + An error occurs during programming. + #1 + + + + + ERERR1 + Erase Error Flag1 + 0 + 0 + + + 0 + Erasure terminates normally. + #0 + + + 1 + An error occurs during erasure. + #1 + + + + + + + FWBL1 + Flash Write Buffer Register L1 + 0x140 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDATA47_32 + Program data of the program command + 0 + 15 + read-write + + + + + FWBH1 + Flash Write Buffer Register H1 + 0x144 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + WDATA63_48 + Program data of the program command + 0 + 15 + + + + + FRBL1 + Flash Read Buffer Register L1 + 0x148 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA47_32 + Read data of the consecutive read command + 0 + 15 + read-only + + + + + FRBH1 + Flash Read Buffer Register H1 + 0x14C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA63_48 + Read data of the consecutive read command + 0 + 15 + read-only + + + + + FPR + Protection Unlock Register + 0x180 + 32 + write-only + 0x00000000 + 0xFFFFFF00 + + + FPR + Protection Unlock Register + 0 + 7 + write-only + + + + + FPSR + Protection Unlock Status Register + 0x184 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PERR + Protect Error Flag + 0 + 0 + read-only + + + 0 + No error + #0 + + + 1 + An error occurs. + #1 + + + + + + + FRBL0 + Flash Read Buffer Register L0 + 0x188 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA + Read data of the consecutive read command + 0 + 15 + + + + + FRBH0 + Flash Read Buffer Register H0 + 0x190 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA + Read data of the consecutive read command + 0 + 15 + + + + + FSCMR + Flash Start-Up Setting Monitor Register + 0x1C0 + 32 + read-only + 0x00000000 + 0xFFFFBEFF + + + FSPR + Access Window Protection Flag + 14 + 14 + read-only + + + SASMF + Start-up Area Setting Monitor Flag + 8 + 8 + read-only + + + + + FAWSMR + Flash Access Window Start Address Monitor Register + 0x1C8 + 32 + read-only + 0x00000000 + 0xFFFFF000 + + + FAWS + Flash Access Window Start Address + 0 + 11 + read-only + + + + + FAWEMR + Flash Access Window End Address Monitor Register + 0x1D0 + 32 + read-only + 0x00000000 + 0xFFFFF000 + + + FAWE + Flash Access Window End Address + 0 + 11 + read-only + + + + + FISR + Flash Initial Setting Register + 0x1D8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAS + Temporary boot swap mode + 6 + 7 + + + 10 + The start-up area is switched to the default area temporarily. + #10 + + + 11 + The start-up area is switched to the alternate area temporarily. + #11 + + + others + The start-up area is selected according to the start-up area settings of the extra area. + true + + + + + PCKA + Peripheral Clock Notification + 0 + 5 + + + + + FEXCR + Flash Extra Area Control Register + 0x1DC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + OPST + Software Command Setting + 7 + 7 + read-write + + + 0 + Processing stops. + #0 + + + 1 + Processing starts. + #1 + + + + + CMD + Processing Start) + 0 + 2 + read-write + + + 001 + Start-up area selection and security setting + #001 + + + 010 + Access window information program + #010 + + + 011 + OCDID1 program + #011 + + + 100 + OCDID2 program + #100 + + + 101 + OCDID3 program + #101 + + + 110 + OCDID4 program + #110 + + + 111 + Extra area clear + #111 + + + others + Setting prohibited + true + + + + + + + FEAML + Flash Error Address Monitor Register L + 0x1E0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + FEAM + Flash Error Address Monitor Register + 0 + 15 + + + + + FEAMH + Flash Error Address Monitor Register H + 0x1E8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + FEAM + Flash Error Address Monitor Register + 0 + 15 + + + + + FSTATR2 + Flash Status Register2 + 0x1F0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + EILGLERR + Extra Area Illegal Command Error Flag + 5 + 5 + read-only + + + ILGLERR + Illegal Command Error Flag + 4 + 4 + read-only + + + BCERR + Blank Check Error Flag + 3 + 3 + read-only + + + PRGERR01 + Program Error Flag 01 + 2 + 2 + read-write + + + PRGERR1 + Program Error Flag + 1 + 1 + read-only + + + ERERR + Erase Error Flag + 0 + 0 + read-only + + + + + FENTRYR_MF4 + Flash P/E Mode Entry Register for MF4 + 0x3FB0 + 16 + read-write + 0x0000 + 0xFFFF + + + FENTRYR + Flash P/E Mode Entry Register + 0x3FB2 + 16 + read-write + 0x0000 + 0xFFFF + + + FLWAITR + Flash Wait Cycle Register + 0x3FC0 + 8 + read-write + 0x00 + 0xFF + + + PFBER + Prefetch Buffer Enable Register + 0x3FC8 + 8 + read-write + 0x00 + 0xFF + + + + + R_FCACHE + Flash Memory Cache + 0x4001C000 + + 0x00000100 + 0x02 + registers + + + 0x00000104 + 0x02 + registers + + + 0x0000011C + 0x01 + registers + + + + FCACHEE + Flash Cache Enable Register + 0x100 + 16 + read-write + 0x0000 + 0xFFFF + + + FCACHEEN + FCACHE Enable + 0 + 0 + read-write + + + 0 + Disable FCACHE + #0 + + + 1 + Enable FCACHE + #1 + + + + + + + FCACHEIV + Flash Cache Invalidate Register + 0x104 + 16 + read-write + 0x0000 + 0xFFFF + + + FCACHEIV + Flash Cache Invalidate Register + 0 + 0 + read-write + + + 0 + Do not invalidate reads, setting ignored on writes + #0 + + + 1 + Invalidate on reads and writes. + #1 + + + + + + + FLWT + Flash Wait Cycle Register + 0x11C + 8 + read-write + + + FLWT + Flash Wait Cycle + 0 + 2 + read-write + + + 000 + 0 waits (ICLK <= 80 MHz) + #000 + + + 001 + 1 wait (80 MHz < ICLK <= 160 MHz) + #001 + + + 010 + 2 waits (160 MHz < ICLK <= 240 MHz). + #010 + + + + + + + + + R_GLCDC + Graphics LCD Controller + 0x400E0000 + + 0x00000000 + 0x101C + registers + + + 0x00001100 + 0x014 + registers + + + 0x00001118 + 0x02C + registers + + + 0x0000114C + 0x00C + registers + + + 0x00001200 + 0x014 + registers + + + 0x00001218 + 0x02C + registers + + + 0x0000124C + 0x00C + registers + + + 0x00001300 + 0x03C + registers + + + 0x00001340 + 0x03C + registers + + + 0x00001380 + 0x03C + registers + + + 0x000013C0 + 0x018 + registers + + + 0x000013E4 + 0x04 + registers + + + 0x00001404 + 0x028 + registers + + + 0x00001440 + 0x014 + registers + + + + BG + Background Registers + 0x1000 + + EN + Background Plane Setting Operation Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWRST + Entire module SW reset control + 16 + 16 + read-write + + + 1 + Releases the entire module from the SW reset state. + #1 + + + 0 + Places the entire module in the SW reset state. + #0 + + + + + VEN + Control of LCDC internal register value reflection to internal operations + 8 + 8 + read-write + oneToSet + modify + + + 1 + Enables + #1 + + + 0 + Disables(Cleared to 0 by an internal source) + #0 + + + + + EN + Background plane generation module operation enable + 0 + 0 + read-write + + + 1 + Enables operation. + #1 + + + 0 + Disables operation. + #0 + + + + + + + PERI + Background Plane Setting Free-Running Period Register + 0x04 + 32 + read-write + 0x00170017 + 0xFFFFFFFF + + + FV + Background plane vertical synchronization signal period on the basis of line. + 16 + 26 + read-write + + + 0x013 + 0x3FF + + + + + FV + FV lines.The valid range is 0x013 to 0x3FF. + true + + + + + FH + Background plane horizontal synchronization signal period on the basis of pixel clock (PXCLK). + 0 + 10 + read-write + + + 0x017 + 0x3FF + + + + + FH + FH lines. The valid range is 0x017 to 0x3FF. + true + + + + + + + SYNC + Background Plane Setting Synchronization Position Register + 0x08 + 32 + read-write + 0x00010001 + 0xFFFFFFFF + + + VP + Background plane vertical synchronization signal assertion position on the basis of line. + 16 + 19 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + (VP)th line + true + + + + + HP + Background plane horizontal synchronization signal assertion position on the basis of pixel clock (PXCLK). + 0 + 3 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + (HP)th line (pixels) + true + + + + + + + VSIZE + Background Plane Setting Full Image Vertical Size Register + 0x0C + 32 + read-write + 0x00070010 + 0xFFFFFFFF + + + VP + Background plane vertical valid pixel start position on the basis of line + 16 + 26 + read-write + + + 0x0003 + 0x3EF + + + + + VP + VP lines. The valid range is 0x003 to 0x3EF. + true + + + + + VW + Background plane vertical valid pixel width on the basis of line + 0 + 10 + read-write + + + 0x0010 + 0x03FC + + + + + VW + VW lines. The valid range is 0x010 to 0x3F0. + true + + + + + + + HSIZE + Background Plane Setting Full Image Horizontal Size Register + 0x10 + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + HP + Background plane horizontal valid pixel start position on the basis of pixel clock (PXCLK). + 16 + 26 + read-write + + + 0x006 + 0x3EE + + + + + HP + HP cycle(pixel). The valid range is 0x006 to 0x3EE. + true + + + + + HW + + Background plane horizontall valid pixel width on the basis of pixel clock (PXCLK) + Note: When serial RGB is selected as the output format for the output control block, add two to the horizontal enable signal width and set the resulting value to this field. + + 0 + 10 + read-write + + + 0x010 + 0x3F8 + + + + + HW + HW cycles. The valid range is 0x010 to 0x3F8. + true + + + + + + + BGC + Background Plane Setting Background Color Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + R + + R value for background plane valid pixel area. + Unsigned; 8-bit integer. + + 16 + 23 + read-write + + + G + + G value for background plane valid pixel area + Unsigned; 8-bit integer + + 8 + 15 + read-write + + + B + + B value for background plane valid pixel area + Unsigned; 8-bit integer + + 0 + 7 + read-write + + + + + MON + Background Plane Setting Status Monitor Register + 0x18 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SWRST + Entire module SW reset state monitor. + 16 + 16 + read-only + + + 1 + The entire module is released from the SW reset state. + #1 + + + 0 + The entire module is in the SW reset state. + #0 + + + + + VEN + + Entire module internal operation reflection control signal monitor. + The signal state for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal. + + 8 + 8 + read-only + + + 1 + The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is asserted. + #1 + + + 0 + The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is negated. + #0 + + + + + EN + Background plane generation module operation state monitor. + 0 + 0 + read-only + + + 1 + Operation is in progress. + #1 + + + 0 + Operation is stopped. + #0 + + + + + + + + 2 + 0x100 + GR[%s] + Layer Registers + 0x1100 + + VEN + Graphics Register Update Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PVEN + + Control of graphics n module register value reflection to internal operations. + Reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + FLMRD + Graphics Frame Buffer Read Control Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RENB + Graphics data (frame buffer data) read enable. + 0 + 0 + read-write + + + 1 + Enables reading. + #1 + + + 0 + Disables reading. + #0 + + + + + + + FLM1 + Graphics Frame Buffer Control Register 1 + 0x08 + 32 + read-only + 0x00000003 + 0xFFFFFFFF + + + BSTMD + + Burst transfer control for graphics data (frame buffer data) + access + + 0 + 1 + read-only + + + 11 + 16-beat increment burst transfer (64-byte boundary) + #11 + + + others + Setting prohibited. + true + + + + + + + FLM2 + Graphics Frame Buffer Control Register 2 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BASE + + Base address for accessing graphics data (frame buffer data) + Set the head address in the frame buffer where graphics data is to be stored. GRn_FLM2.BASE[5:0] should be fixed to 0 during 64-byte burst transfer. + + 0 + 31 + read-write + + + + + FLM3 + Graphics Frame Buffer Control Register 3 + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LNOFF + + Macro line offset address for accessing graphics data + (frame buffer data) + Signed; 16-bit integer + + 16 + 31 + read-write + + + + + FLM5 + Graphics Frame Buffer Control Register 5 + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LNNUM + Number of lines per frame for accessing graphics data (frame buffer data). + 16 + 26 + read-write + + + 0x00F + 0x3FF + + + + + LNNUM + LNNUM lines. The valid range is 0x00F to 0x3FF. + true + + + + + DATANUM + Number of data transfer times per line for accessing graphics data (frame buffer data), where one transfer is defined as 16-beat burst access (64-byte boundary) + 0 + 15 + read-write + + + DATAUM + DATAUM+1 times. + true + + + + + + + FLM6 + Graphics Frame Buffer Control Register 6 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FORMAT + Data format for accessing graphics data (frame buffer data). + 28 + 30 + read-write + + + 111 + CLUT11bit/pix) + #111 + + + 110 + CLUT4 (4 bits/pix) + #110 + + + 101 + CLUT8 (8 bits/pix) + #101 + + + 100 + ARGB8888 (32 bits/pix) + #100 + + + 011 + ARGB4444 (16 bits/pix) + #011 + + + 010 + ARGB1555 (16 bits/pix, 1 bit of A is LUT data) + #010 + + + 001 + RGB888 (32 bits/pix, 8 bits on the MSB side are invalid) + #001 + + + 000 + RGB565 (16 bits/pix) + #000 + + + others + Setting prohibited. + true + + + + + + + AB1 + Graphics Alpha Blending Control Register 1 + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCON + Rectangular area alpha blending control. + 12 + 12 + read-write + + + 1 + On + #1 + + + 0 + Off + #0 + + + + + ARCDISPON + Image area border display control for rectangular area alpha blending. + 8 + 8 + read-write + + + 1 + Display on + #1 + + + 0 + Display off + #0 + + + + + GRCDISPON + Graphics image area border display control. + 4 + 4 + read-write + + + 1 + Display on + #1 + + + 0 + Display off + #0 + + + + + DISPSEL + Graphics display plane control. + 0 + 1 + read-write + + + 11 + Blended display of lower-layer graphics (input image from the previous stage) and current graphics (graphics data read from the AHB bus) + #11 + + + 10 + Current graphics display + #10 + + + 01 + Lower-layer graphics display + #01 + + + 00 + Background color display (value set by the GRn_BASE register). + #00 + + + + + + + AB2 + Graphics Alpha Blending Control Register 2 + 0x24 + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + GRCVS + Vertical start position of graphics image area. + 16 + 26 + read-write + + + 0x002 + 0x3EE + + + + + GRCVS + GRCVS lines. The valid range is 0x002 to 0x3EE. + true + + + + + GRCVW + Vertical width of graphics image area. + 0 + 10 + read-write + + + 0x010 + 0x3FC + + + + + GRCVW + GRCVW lines. The valid range is 0x010 to 0x3F0. + true + + + + + + + AB3 + Graphics Alpha Blending Control Register 3 + 0x28 + 32 + read-write + 0x00050010 + 0xFFFFFFFF + + + GRCHS + Horizontal start position of graphics image area. + 16 + 26 + read-write + + + 0x005 + 0x3ED + + + + + GRCHS + GRCHS lines. The valid range is 0x005 to 0x3ED. + true + + + + + GRCHW + Horizontal width of graphics image area. + 0 + 10 + read-write + + + 0x010 + 0x3F0 + + + + + GRCHW + GRCHW pixels. The valid range is 0x010 to 0x3F0. + true + + + + + + + AB4 + Graphics Alpha Blending Control Register 4 + 0x2C + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + ARCVS + Vertical start position of rectangular area alpha blending image area + 16 + 26 + read-write + + + 0x002 + 0x3EE + + + + + ARCVS + ARCVS linels. The valid range is 0x002 to 0x3EE. + true + + + + + ARCVW + Vertical width of rectangular area alpha blending image area. + 0 + 10 + read-write + + + 0x001 + 0x3FC + + + + + ARCVW + ARCVW linels. The valid range is 0x001 to 0x3F0. + true + + + + + + + AB5 + Graphics Alpha Blending Control Register 5 + 0x30 + 32 + read-write + 0x00050010 + 0xFFFFFFFF + + + ARCHS + Horizontal start position of rectangular area alpha blending image area. + 16 + 26 + read-write + + + 0x005 + 0x3ED + + + + + ARCHS + ARCHS pixel. The valid range is 0x005 to 0x3ED. + true + + + + + ARCHW + Horizontal width of rectangular area alpha blending image area. + 0 + 10 + read-write + + + 0x001 + 0x3F8 + + + + + ARCHW + ARCHW pixels. The valid range is 0x001 to 0x3F0. + true + + + + + + + AB6 + Graphics Alpha Blending Control Register 6 + 0x34 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCCOEF + + Alpha coefficient for alpha blending in rectangular area (-255 to 255). + [8]: Sign (0: addition, 1: subtraction) + [7:0]: Variation (absolute value) + + 16 + 24 + read-write + + + ARCRATE + Frame rate for alpha blending in rectangular area. + 0 + 7 + read-write + + + ARCRATE + ARCRATE+1 frames + true + + + + + + + AB7 + Graphics Alpha Blending Control Register 7 + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCDEF + Initial alpha value for alpha blending in rectangular area. + 16 + 23 + read-write + + + CKON + RGB-index chroma-key processing control. + 0 + 0 + read-write + + + 1 + Enables chroma-key processing + #1 + + + 0 + Disables chroma-key processing + #0 + + + + + + + AB8 + Graphics Alpha Blending Control Register 8 + 0x3C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKKG + + G signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 16 + 23 + read-write + + + CKKB + + B signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 8 + 15 + read-write + + + CKKR + + R signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 0 + 7 + read-write + + + + + AB9 + Graphics Alpha Blending Control Register 9 + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKA + A value after RGB-index chroma-key processing replacement. + 24 + 31 + read-write + + + CKG + + G value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 16 + 23 + read-write + + + CKB + + B value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 8 + 15 + read-write + + + CKR + + R value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 0 + 7 + read-write + + + + + BASE + Graphics Background Color Control Register + 0x4C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + G + + Background color G value + Unsigned; 8 bits + + 16 + 23 + read-write + + + B + + Background color B value + Unsigned; 8 bits + + 8 + 15 + read-write + + + R + + Background color R value + Unsigned; 8 bits + + 0 + 7 + read-write + + + + + CLUTINT + Graphics CLUT Table Interrupt Control Register + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + CLUT table control + 16 + 16 + read-write + + + 1 + Uses CLUT1 plane for internal operations. + #1 + + + 0 + Uses CLUT0 plane for internal operations. + #0 + + + others + Setting prohibited + true + + + + + LINE + Number of detection lines + 0 + 10 + read-write + + + 0x000 + 0x400 + + + + + LINE + LINE+1 lines. The valid range is 0x000 to 0x400. + true + + + + + + + MON + Graphics Status Monitor Register + 0x54 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + UNDFLST + Status monitor for underflow + 16 + 16 + read-only + + + 1 + An underflow occurs in internal operations. + #1 + + + 0 + No underflow occurs in internal operations. + #0 + + + + + ARCST + Status monitor for alpha blending in rectangular area + 0 + 0 + read-only + + + 1 + Fade-in/fade-out is in progress. + #1 + + + 0 + Fade-in/fade-out is not in progress. + #0 + + + + + + + + 3 + 0x40 + GAM[%s] + Gamma Settings + 0x1300 + + LATCH + Gamma Register Update Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VEN + + Control of gamma correction x module register value reflection to internal operations. + The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + GAM_SW + Gamma Correction Block Function Switch Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GAMON + Gamma correction on/off control + 0 + 0 + read-write + + + 1 + Turns on gamma correction. + #1 + + + 0 + Turns off gamma correction. + #0 + + + + + + + 8 + 0x04 + LUT[%s] + Gamma Correction Block Table Setting Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 2 + 16 + HIGH,LOW + _%s + + Gain value of area 0. + Unsigned 11-bit fixed point. + + 0 + 10 + read-write + + + GAIN00 + GAIN00/1024 + true + + + + + + + 5 + 0x04 + AREA[%s] + Gamma Correction Block Area Setting Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 3 + 10 + HIGH,MID,LOW + _%s + + Start threshold of area 1 + Unsigned 10-bit integer + + 0 + 9 + read-write + + + + + + OUT + Output Control Registers + 0x13C0 + + VLATCH + Output Control Block Register Update Control Register + 0x0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VEN + + Control of output control module register value reflection to internal operations. + The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + SET + Output Control Block Output Interface Register + 0x4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENDIANON + Bit endian change control + 28 + 28 + read-write + + + 1 + Ascending order (big endian) + #1 + + + 0 + Descending order (little endian) + #0 + + + + + SWAPON + Pixel order control + 24 + 24 + read-write + + + 1 + In the order of BGR + #1 + + + 0 + In the order of RGB + #0 + + + + + FORMAT + Output format select + 12 + 13 + read-write + + + 11 + Serial RGB; select RGB888 as dither output format. + #11 + + + 10 + RGB565; select RGB565 as dither output format. + #10 + + + 01 + RGB666; select RGB666 as dither output format. + #01 + + + 00 + RGB888; select RGB888 as dither output format. + #00 + + + + + FRQSEL + Clock frequency division control + 8 + 9 + read-write + + + 11 + Setting prohibited + #11 + + + 10 + Quarter frequency (serial RGB) + #10 + + + 01 + Setting prohibited + #01 + + + 00 + No frequency division, parallel RGB + #00 + + + + + DIRSEL + Invalid data position control in serial RGB format + 4 + 4 + read-write + + + 1 + Invalid data is output prior to valid (RGB) data. + #1 + + + 0 + Invalid data is output following valid (RGB) data. + #0 + + + + + PHASE + Data delay in serial RGB format (based on OUTCLK) + 0 + 1 + read-write + + + 11 + 3 cycles + #11 + + + 10 + 2 cycles + #10 + + + 01 + 1 cycle + #01 + + + 00 + 0 cycle + #00 + + + + + + + BRIGHT1 + Output Control Block Brightness Correction Register 1 + 0x8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRTG + + Brightness (DC) adjustment of G signal + Unsigned; 10 bits; +512 with offset; integer + + 0 + 9 + read-write + + + + + BRIGHT2 + Output Control Block Brightness Correction Register 2 + 0xC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRTB + + Brightness (DC) adjustment of B signal + Unsigned; 10 bits; +512 with offset; integer + + 16 + 25 + read-write + + + BRTR + + Brightness (DC) adjustment of R signal + Unsigned; 10 bits; +512 with offset; integer + + 0 + 9 + read-write + + + + + CONTRAST + Output Control Block Contrast Correction Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CONTG + + Contrast (GAIN) adjustment of G signal + Unsigned; 8 bits fixed point. + + 16 + 23 + read-write + + + CONTG + CONTG/128 + true + + + + + CONTB + + Contrast (GAIN) adjustment of B signal + Unsigned; 8 bits fixed point + + 8 + 15 + read-write + + + CONTB + CONTB/128 + true + + + + + CONTR + + Contrast (GAIN) adjustment of R signal + Unsigned; 8 bits fixed point + + 0 + 7 + read-write + + + CONTR + CONTR/128 + true + + + + + + + PDTHA + Output Control Block Panel Dither Correction Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + Operation mode + 20 + 21 + read-write + + + 11 + Setting prohibited + #11 + + + 10 + 2x2 pattern dither + #10 + + + 01 + Round-off + #01 + + + 00 + Truncate + #00 + + + + + FORM + Output format select + 16 + 17 + read-write + + + 11 + Setting prohibited + #11 + + + 10 + RGB565; select RGB565 as output interface format. + #10 + + + 01 + RGB666; select RGB666 as output interface format. + #01 + + + 00 + RGB888; select RGB888 or serial RGB as output interface format. + #00 + + + + + PA + + Pattern value (A) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 12 + 13 + read-write + + + PB + + Pattern value (B) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 8 + 9 + read-write + + + PC + + Pattern value (C) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 4 + 5 + read-write + + + PD + + Pattern value (D) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 0 + 1 + read-write + + + + + CLKPHASE + Output Control Block Output Phase Control Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRONTGAM + Correction control + 12 + 12 + read-write + + + 1 + Gamma correction is followed by brightness/contrast correction. + #1 + + + 0 + Brightness/contrast correction is followed by gamma correction. + #0 + + + + + LCDEDGE + LCD_DATA Output Phase Control + 8 + 8 + read-write + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + 1 + In synchronization with the falling edge of LCD_CLK + #1 + + + + + TCON0EDGE + LCD_TCON0 Output Phase Control + 6 + 6 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON1EDGE + LCD_TCON1 Output Phase Control + 5 + 5 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON2EDGE + LCD_TCON2 Output Phase Control + 4 + 4 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON3EDGE + LCD_TCON3 Output Phase Control + 3 + 3 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + + + + TCON + Timing Control Registers + 0x1400 + + TIM + TCON Reference Timing Setting Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HALF + + Vertical synchronization signal generation change timing + Sets the delay from the assertion of the internal horizontal synchronization signal in terms of pixels. + + 16 + 26 + read-write + + + 0x000 + 0x3FF + + + + + HALF + HALF pixels. The valid range is 0x000 to 0x3FF. + true + + + + + OFFSET + + Horizontal synchronization signal generation reference timing + Sets the offset from the assertion of the internal horizontal synchronization signal in terms of pixels. + + 0 + 10 + read-write + + + 0x000 + 0x3FF + + + + + OFFSET + OFFSET+1 pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STV%s1 + TCON Vertical Timing Setting Register %s1 + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VS + STVx1 first change timing + 16 + 26 + read-write + + + 0x000 + 0x7FF + + + + + VS + VS pixels. The valid range is 0x000 to 0x3FF. + true + + + + + VW + + STVx1 second change timing + Sets the signal assertion width. + + 0 + 10 + read-write + + + 0x000 + 0x7FF + + + + + VW + VW pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STV%s2 + TCON Vertical Timing Setting Register %s2 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INV + STVx signal polarity inversion control + 4 + 4 + read-write + + + 1 + Inverted + #1 + + + 0 + Not inverted + #0 + + + + + SEL + Output signal select control for VSOUT (controlled by TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 register) pin + 0 + 2 + read-write + + + 111 + DE + #111 + + + 110 + Setting prohibited + #110 + + + 101 + Setting prohibited + #101 + + + 100 + Setting prohibited + #100 + + + 011 + STHB + #011 + + + 010 + STHA + #010 + + + 001 + STVB + #001 + + + 000 + STVA + #000 + + + + + + + 2 + 0x8 + A,B + STH%s1 + TCON Horizontal Timing Setting Register STH%s1 + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HS + STHx1 first change timing + 16 + 26 + read-write + + + 0x000 + 0x3FF + + + + + HS + HS lines. The valid range is 0x000 to 0x3FF. + true + + + + + HW + + STHx1 second change timing. + Sets the signal assertion width. + + 0 + 10 + read-write + + + 0x000 + 0x3FF + + + + + HW + HW pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STH%s2 + TCON Horizontal Timing Setting Register STH%s2 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSSEL + STHx signal generation reference timing control. + 8 + 8 + read-write + + + 1 + Reference timing is the offset set with the TCON_TIM.OFFSET[10:0] (horizontal synchronization generation reference timing) field + #1 + + + 0 + Reference timing is the input horizontal synchronization signal (HSIN) + #0 + + + + + INV + STVx signal polarity inversion control. + 4 + 4 + read-write + + + 1 + Inverted + #1 + + + 0 + Not inverted + #0 + + + + + SEL + Output signal select control for LCD_TCON2 (controlled by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 register) pin. + 0 + 2 + read-write + + + 111 + DE + #111 + + + 110 + Setting prohibited + #110 + + + 101 + Setting prohibited + #101 + + + 100 + Setting prohibited + #100 + + + 011 + STHB + #011 + + + 010 + STHA + #010 + + + 001 + STVB + #001 + + + 000 + STVA + #000 + + + + + + + DE + TCON Data Enable Polarity Setting Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INV + DE signal polarity inversion control. + 0 + 0 + read-write + + + 1 + Inverted + #1 + + + 0 + Not inverted + #0 + + + + + + + + SYSCNT + GLCDC System Control Registers + 0x1440 + + DTCTEN + System control block State Detection Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + L2UNDFDTC + Graphics 2 underflow detection control + 2 + 2 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + + + + L1UNDFDTC + Graphics 1 underflow detection control + 1 + 1 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + + + + VPOSDTC + Specified line detection control + 0 + 0 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + + + + + + INTEN + System control block Interrupt Request Enable Control Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + L2UNDFINTEN + Interrupt request signal GLCDC_L2UNDF enable control. + 2 + 2 + read-write + + + 1 + Enables GLCDC_L2UNDF output + #1 + + + 0 + Disables GLCDC_L2UNDF output + #0 + + + + + L1UNDFINTEN + Interrupt request signal GLCDC_L1UNDF enable control. + 1 + 1 + read-write + + + 1 + Enables GLCDC_L1UNDF output + #1 + + + 0 + Disables GLCDC_L1UNDF output + #0 + + + + + VPOSINTEN + Interrupt request signal GLCDC_VPOS enable control. + 0 + 0 + read-write + + + 1 + Enables GLCDC_VPOS output + #1 + + + 0 + Disables GLCDC_VPOS output + #0 + + + + + + + STCLR + System control block Status Clear Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + L2UNDFCLR + Graphics 2 underflow detection flag clear field + 2 + 2 + read-write + + + 1 + Clears the graphics 2 underflow detection flag. + #1 + + + 0 + No operation + #0 + + + + + L1UNDFCLR + Graphics 1 underflow detection flag clear field + 1 + 1 + read-write + + + 1 + Clears the graphics 1 underflow detection flag. + #1 + + + 0 + No operation + #0 + + + + + VPOSCLR + Graphics 2 specified line detection flag clear field + 0 + 0 + read-write + + + 1 + Clears the specified line detection flag. + #1 + + + 0 + No operation + #0 + + + + + + + STMON + System control block Status Monitor Register + 0x0c + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + L2UNDF + Graphics 2 underflow detection flag + 2 + 2 + read-only + + + 1 + An underflow has been detected in graphics 2. + #1 + + + 0 + No underflow has been detected in graphics 2. + #0 + + + + + L1UNDF + Graphics 1 underflow detection flag + 1 + 1 + read-only + + + 1 + An underflow has been detected in graphics 1. + #1 + + + 0 + No underflow has been detected in graphics 1. + #0 + + + + + VPOS + Graphics 2 specified line detection flag + 0 + 0 + read-only + + + 1 + A specified line notification has been detected in graphics 2. + #1 + + + 0 + No specified line notification has been detected in graphics 2. + #0 + + + + + + + PANEL_CLK + System control block Version and Panel Clock Control Register + 0x10 + 32 + read-write + 0x01000000 + 0xFFFFFFFF + + + VER + + Version information + Version information of the GLCDC + + 16 + 31 + read-only + + + PIXSEL + + Pixel clock select control. + Must be set to the same value as OUT_SET.FRQSEL[1]. + + 12 + 12 + read-write + + + 0 + No frequency division, parallel RGB + #0 + + + 1 + Quarter frequency,serial RGB + #1 + + + + + CLKSEL + Panel clock supply source select + 8 + 8 + read-write + + + 0 + External clock select + #0 + + + 1 + PLL output select + #1 + + + + + CLKEN + + Panel clock output enable control + Note: Before changing the PIXSEL,CLKSEL or DCDR bit, this bit must be set to 0. + + 6 + 6 + read-write + + + 0 + Disable panel clock output + #0 + + + 1 + Enable panel clock output + #1 + + + + + DCDR + + Clock division ratio setting control + Refer toTable 2.7.1 for details about setting value. + Note: Settings that are not listed in table 2.7.1 are prohibited. + + 0 + 5 + read-write + + + + + + 256 + 0x4 + GR1_CLUT0[%s] + Color Palette 0 Plane for Graphics 1 Plane + 0x0000 + 32 + read-write + 0x00000000 + 0x00000000 + + + A + Alpha Blending Value of Color Palette n Plane for Graphics m Plane + 24 + 31 + read-write + + + R + R Value of Color Palette n Plane for Graphics m Plane + 16 + 23 + read-write + + + G + G Value of Color Palette n Plane for Graphics m Plane + 8 + 15 + read-write + + + B + B Value of Color Palette n Plane for Graphics m Plane + 0 + 7 + read-write + + + + + GR1_CLUT1[%s] + Color Palette 1 Plane for Graphics 1 Plane + 0x0400 + + + + GR2_CLUT0[%s] + Color Palette 0 Plane for Graphics 2 Plane + 0x0800 + + + + GR2_CLUT1[%s] + Color Palette 1 Plane for Graphics 2 Plane + 0x0C00 + + + + + + R_GPT0 + General PWM Timer + 0x40078000 + + 0x00000000 + 0x0A4 + registers + + + + GTWP + General PWM Timer Write-Protection Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRKEY + GTWP Key Code + 8 + 15 + write-only + + + 0xA5 + Written to these bits, the WP bits write is permitted. + 0xA5 + + + others + The WP bits write is not permitted. + true + + + + + WP + Register Write Disable + 0 + 0 + read-write + + + 0 + Write to the register is enabled + #0 + + + 1 + Write to the register is disabled + #1 + + + + + + + GTSTR + General PWM Timer Software Start Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CSTRT%s + Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. + 0 + 0 + read-write + + + 0 + No effect (write) / counter stop (read) + #0 + + + 1 + GTCNT counter starts (write) / Counter running (read) + #1 + + + + + + + GTSTP + General PWM Timer Software Stop Register + 0x08 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + 14 + 1 + CSTOP%s + Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. + 0 + 0 + read-write + + + 0 + No effect (write) / counter running (read) + #0 + + + 1 + GPT GTCNT counter stops (write) / Counter stop (read) + #1 + + + + + + + GTCLR + General PWM Timer Software Clear Register + 0x0C + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CCLR%s + Channel GTCNT Count Clear + 0 + 0 + write-only + + + 0 + No effect + #0 + + + 1 + GPT GTCNT counter clears + #1 + + + + + + + GTSSR + General PWM Timer Start Source Select Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTRT + Software Source Counter Start Enable + 31 + 31 + read-write + + + 0 + Counter start is disable by the GTSTR register + #0 + + + 1 + Counter start is enable by the GTSTR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + SSELC%s + ELC_GPT Event Source Counter Start Enable + 16 + 16 + read-write + + + 0 + Counter start is disable at the ELC_GPT input + #0 + + + 1 + Counter start is enable at the ELC_GPT input + #1 + + + + + SSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable + 15 + 15 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable + 14 + 14 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable + 13 + 13 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable + 12 + 12 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable + 11 + 11 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable + 10 + 10 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + SSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable + 9 + 9 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable + 8 + 8 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sF + GTETRG Pin Falling Input Source Counter Start Enable + 1 + 1 + read-write + + + 0 + Counter start is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter start is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sR + GTETRG Pin Rising Input Source Counter Start Enable + 0 + 0 + read-write + + + 0 + Counter start is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter start is enable at the rising edge of GTETRG input + #1 + + + + + + + GTPSR + General PWM Timer Stop Source Select Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTOP + Software Source Counter Stop Enable + 31 + 31 + read-write + + + 0 + Counter stop is disable by the GTSTP register + #0 + + + 1 + Counter stop is enable by the GTSTP register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + PSELC%s + ELC_GPTA Event Source Counter Stop Enable + 16 + 16 + read-write + + + 0 + Counter stop is disable at the ELC_GPTA input + #0 + + + 1 + Counter stop is enable at the ELC_GPTA input + #1 + + + + + PSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable + 15 + 15 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable + 14 + 14 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable + 13 + 13 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable + 12 + 12 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable + 11 + 11 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable + 10 + 10 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + PSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable + 9 + 9 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable + 8 + 8 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sF + GTETRG Pin Falling Input Source Counter Stop Enable + 1 + 1 + read-write + + + 0 + Counter stop is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sR + GTETRG Pin Rising Input Source Counter Stop Enable + 0 + 0 + read-write + + + 0 + Counter stop is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the rising edge of GTETRG input + #1 + + + + + + + GTCSR + General PWM Timer Clear Source Select Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCLR + Software Source Counter Clear Enable + 31 + 31 + read-write + + + 0 + Counter clear is disable by the GTCLR register + #0 + + + 1 + Counter clear is enable by the GTCLR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + CSELC%s + ELC_GPTA Event Source Counter Clear Enable + 16 + 16 + read-write + + + 0 + Counter clear is disable at the ELC_GPTA input + #0 + + + 1 + Counter clear is enable at the ELC_GPTA input + #1 + + + + + CSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable + 15 + 15 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable + 14 + 14 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable + 13 + 13 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable + 12 + 12 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable + 11 + 11 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable + 10 + 10 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + CSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable + 9 + 9 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable + 8 + 8 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sF + GTETRG Pin Falling Input Source Counter Clear Enable + 1 + 1 + read-write + + + 0 + Counter clear is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sR + GTETRG Pin Rising Input Source Counter Clear Enable + 0 + 0 + read-write + + + 0 + Counter clear is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the rising edge of GTETRG input + #1 + + + + + + + GTUPSR + General PWM Timer Up Count Source Select Register + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + USELC%s + ELC_GPT Event Source Counter Count Up Enable + 16 + 16 + read-write + + + 0 + Counter count up is disable at the ELC_GPT input + #0 + + + 1 + Counter count up is enable at the ELC_GPT input + #1 + + + + + USCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable + 15 + 15 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable + 14 + 14 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable + 13 + 13 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable + 12 + 12 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable + 11 + 11 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable + 10 + 10 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + USCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable + 9 + 9 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable + 8 + 8 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sF + GTETRG Pin Falling Input Source Counter Count Up Enable + 1 + 1 + read-write + + + 0 + Counter count up is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sR + GTETRG Pin Rising Input Source Counter Count Up Enable + 0 + 0 + read-write + + + 0 + Counter count up is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the rising edge of GTETRG input + #1 + + + + + + + GTDNSR + General PWM Timer Down Count Source Select Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + DSELC%s + ELC_GPT Event Source Counter Count Down Enable + 16 + 16 + read-write + + + 0 + Counter count down is disable at the ELC_GPT input + #0 + + + 1 + Counter count down is enable at the ELC_GPT input + #1 + + + + + DSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable + 15 + 15 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable + 14 + 14 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable + 13 + 13 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable + 12 + 12 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable + 11 + 11 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable + 10 + 10 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + DSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable + 9 + 9 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable + 8 + 8 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sF + GTETRG Pin Falling Input Source Counter Count Down Enable + 1 + 1 + read-write + + + 0 + Counter count down is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sR + GTETRG Pin Rising Input Source Counter Count Down Enable + 0 + 0 + read-write + + + 0 + Counter count down is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the rising edge of GTETRG input + #1 + + + + + + + GTICASR + General PWM Timer Input Capture Source Select Register A + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + ASELC%s + ELC_GPT Event Source GTCCRA Input Capture Enable + 16 + 16 + read-write + + + 0 + GTCCRA input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRA input capture is enable at the ELC_GPT input + #1 + + + + + ASCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 15 + 15 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + ASCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 14 + 14 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + ASCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 13 + 13 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + ASCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 12 + 12 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + ASCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 11 + 11 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 10 + 10 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + ASCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 8 + 8 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + ASGTRG%sF + GTETRG Pin Falling Input Source GTCCRA Input Capture Enable + 1 + 1 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + ASGTRG%sR + GTETRG Pin Rising Input Source GTCCRA Input Capture Enable + 0 + 0 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTETRG input + #1 + + + + + + + GTICBSR + General PWM Timer Input Capture Source Select Register B + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + BSELC%s + ELC_GPT Event Source GTCCRB Input Capture Enable + 16 + 16 + read-write + + + 0 + GTCCRB input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRB input capture is enable at the ELC_GPT input + #1 + + + + + BSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 15 + 15 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + BSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 14 + 14 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + BSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 13 + 13 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + BSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 12 + 12 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + BSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 11 + 11 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + BSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 10 + 10 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + BSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + BSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 8 + 8 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + BSGTRG%sF + GTETRG Pin Falling Input Source GTCCRB Input Capture Enable + 1 + 1 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + BSGTRG%sR + GTETRG Pin Rising Input Source GTCCRB Input Capture Enable + 0 + 0 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTETRG input + #1 + + + + + + + GTCR + General PWM Timer Control Register + 0x2C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPCS + Timer Prescaler Select + 24 + 26 + read-write + + + 0000 + PCLK/1 + #0000 + + + 0001 + PCLK/2 + #0001 + + + 0010 + PCLK/4 + #0010 + + + 0011 + PCLK/8 + #0011 + + + 0100 + PCLK/16 + #0100 + + + 0101 + PCLK/32 + #0101 + + + 0110 + PCLK/64 + #0110 + + + 1000 + PCLK/256 + #1000 + + + 1010 + PCLK/1024 + #1010 + + + 1100 + GTETRGA + #1100 + + + 1101 + GTETRGB + #1101 + + + 1110 + GTETRGC + #1110 + + + 1111 + GTETRGD + #1111 + + + others + Setting prohibied + true + + + + + MD + Mode Select + 16 + 18 + read-write + + + 000 + Saw-wave PWM mode (single buffer or double buffer possible) + #000 + + + 001 + Saw-wave one-shot pulse mode (fixed buffer operation) + #001 + + + 010 + Setting prohibited + #010 + + + 011 + Setting prohibited + #011 + + + 100 + Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) + #100 + + + 101 + Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) + #101 + + + 110 + Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) + #110 + + + 111 + Setting prohibited + #111 + + + + + CST + Count Start + 0 + 0 + read-write + + + 0 + Count operation is stopped + #0 + + + 1 + Count operation is performed + #1 + + + + + + + GTUDDTYC + General PWM Timer Count Direction and Duty Setting Register + 0x30 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + OBDTYR + GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 27 + 27 + read-write + + + 0 + Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + #0 + + + 1 + Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + #1 + + + + + OBDTYF + Forcible GTIOCB Output Duty Setting + 26 + 26 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + OBDTY + GTIOCB Output Duty Setting + 24 + 25 + read-write + + + 00 + GTIOCB pin duty is depend on compare match + #00 + + + 01 + GTIOCB pin duty is depend on compare match + #01 + + + 10 + GTIOCB pin duty 0 percent + #10 + + + 11 + GTIOCB pin duty 100 percent + #11 + + + + + OADTYR + GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 19 + 19 + read-write + + + 0 + Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + #0 + + + 1 + Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + #1 + + + + + OADTYF + Forcible GTIOCA Output Duty Setting + 18 + 18 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + OADTY + GTIOCA Output Duty Setting + 16 + 17 + read-write + + + 00 + GTIOCA pin duty is depend on compare match + #00 + + + 01 + GTIOCA pin duty is depend on compare match + #01 + + + 10 + GTIOCA pin duty 0 percent + #10 + + + 11 + GTIOCA pin duty 100 percent + #11 + + + + + UDF + Forcible Count Direction Setting + 1 + 1 + read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + + + + UD + Count Direction Setting + 0 + 0 + read-write + + + 0 + GTCNT counts down. + #0 + + + 1 + GTCNT counts up. + #1 + + + + + + + GTIOR + General PWM Timer I/O Control Register + 0x34 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NFCSB + Noise Filter B Sampling Clock Select + 30 + 31 + read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFBEN + Noise Filter B Enable + 29 + 29 + read-write + + + 0 + The noise filter for the GTIOCB pin is disabled. + #0 + + + 1 + The noise filter for the GTIOCB pin is enabled. + #1 + + + + + OBDF + GTIOCB Pin Disable Value Setting + 25 + 26 + read-write + + + 00 + Output disable is prohibited. + #00 + + + 01 + GTIOCB pin is set to Hi-Z when output disable is performed. + #01 + + + 10 + GTIOCB pin is set to 0 when output disable is performed. + #10 + + + 11 + GTIOCB pin is set to 1 when output disable is performed. + #11 + + + + + OBE + GTIOCB Pin Output Enable + 24 + 24 + read-write + + + 0 + Output is disabled + #0 + + + 1 + Output is enabled + #1 + + + + + OBHLD + GTIOCB Pin Output Setting at the Start/Stop Count + 23 + 23 + read-write + + + 0 + The GTIOCB pin output level at start/stop of counting depends on the register setting. + #0 + + + 1 + The GTIOCB pin output level is retained at start/stop of counting. + #1 + + + + + OBDFLT + GTIOCB Pin Output Value Setting at the Count Stop + 22 + 22 + read-write + + + 0 + The GTIOCB pin outputs low when counting is stopped. + #0 + + + 1 + The GTIOCB pin outputs high when counting is stopped. + #1 + + + + + GTIOB + GTIOCB Pin Function Select + 16 + 20 + read-write + + + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. + #00000 + + + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. + #00001 + + + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. + #00010 + + + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. + #00011 + + + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. + #00100 + + + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. + #00101 + + + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. + #00110 + + + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. + #00111 + + + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. + #01000 + + + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. + #01001 + + + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRB compare match. + #01010 + + + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. + #01011 + + + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. + #01100 + + + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. + #01101 + + + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. + #01110 + + + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #01111 + + + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. + #10000 + + + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. + #10001 + + + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. + #10010 + + + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRB compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRB compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRB compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #11111 + + + + + NFCSA + Noise Filter A Sampling Clock Select + 14 + 15 + read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFAEN + Noise Filter A Enable + 13 + 13 + read-write + + + 0 + The noise filter for the GTIOCA pin is disabled. + #0 + + + 1 + The noise filter for the GTIOCA pin is enabled. + #1 + + + + + OADF + GTIOCA Pin Disable Value Setting + 9 + 10 + read-write + + + 00 + Output disable is prohibited. + #00 + + + 01 + GTIOCA pin is set to Hi-Z when output disable is performed. + #01 + + + 10 + GTIOCA pin is set to 0 when output disable is performed. + #10 + + + 11 + GTIOCA pin is set to 1 when output disable is performed. + #11 + + + + + OAE + GTIOCA Pin Output Enable + 8 + 8 + read-write + + + 0 + Output is disabled + #0 + + + 1 + Output is enabled + #1 + + + + + OAHLD + GTIOCA Pin Output Setting at the Start/Stop Count + 7 + 7 + read-write + + + 0 + The GTIOCA pin output level at start/stop of counting depends on the register setting. + #0 + + + 1 + The GTIOCA pin output level is retained at start/stop of counting. + #1 + + + + + OADFLT + GTIOCA Pin Output Value Setting at the Count Stop + 6 + 6 + read-write + + + 0 + The GTIOCA pin outputs low when counting is stopped. + #0 + + + 1 + The GTIOCA pin outputs high when counting is stopped. + #1 + + + + + GTIOA + GTIOCA Pin Function Select + 0 + 4 + read-write + + + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. + #00000 + + + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. + #00001 + + + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. + #00010 + + + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. + #00011 + + + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. + #00100 + + + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. + #00101 + + + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. + #00110 + + + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. + #00111 + + + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. + #01000 + + + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. + #01001 + + + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRA compare match. + #01010 + + + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. + #01011 + + + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. + #01100 + + + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. + #01101 + + + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. + #01110 + + + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #01111 + + + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. + #10000 + + + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. + #10001 + + + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. + #10010 + + + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRA compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRA compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRA compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #11111 + + + + + + + GTINTAD + General PWM Timer Interrupt Output Setting Register + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GRPABL + Same Time Output Level Low Disable Request Enable + 30 + 30 + read-write + + + 0 + Same time output level low disable request is disabled. + #0 + + + 1 + Same time output level low disable request is enabled. + #1 + + + + + GRPABH + Same Time Output Level High Disable Request Enable + 29 + 29 + read-write + + + 0 + Same time output level high disable request is disabled. + #0 + + + 1 + Same time output level high disable request is enabled. + #1 + + + + + GRPDTE + Dead Time Error Output Disable Request Enable + 28 + 28 + read-write + + + 0 + Disable dead time error output disable request + #0 + + + 1 + Enable dead time error output disable request + #1 + + + + + GRP + Output Disable Source Select + 24 + 25 + read-write + + + 00 + Group A output disable request + #00 + + + 01 + Group B output disable request + #01 + + + 10 + Group C output disable request + #10 + + + 11 + Group D output disable request + #11 + + + others + Setting prohibited + true + + + + + + + GTST + General PWM Timer Status Register + 0x3C + 32 + read-write + 0x00008000 + 0xFFFFFFFF + + + OABLF + Same Time Output Level Low Disable Request Enable + 30 + 30 + read-only + + + 0 + GTIOCA pin and GTIOCB pin don't output 0 at the same time. + #0 + + + 1 + GTIOCA pin and GTIOCB pin output 0 at the same time. + #1 + + + + + OABHF + Same Time Output Level High Disable Request Enable + 29 + 29 + read-only + + + 0 + GTIOCA pin and GTIOCB pin don't output 1 at the same time. + #0 + + + 1 + GTIOCA pin and GTIOCB pin output 1 at the same time. + #1 + + + + + DTEF + Dead Time Error Flag + 28 + 28 + read-only + + + 0 + No dead time error has occurred. + #0 + + + 1 + A dead time error has occurred. + #1 + + + + + ODF + Output Disable Flag + 24 + 24 + read-only + + + 0 + No output disable request is generated. + #0 + + + 1 + An output disable request is generated. + #1 + + + + + ADTRBDF + GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag + 19 + 19 + read-write + + + 0 + No compare match of GTADTRB at down-counting is generated. + #0 + + + 1 + A compare match of GTADTRB at down-counting is generated. + #1 + + + + + ADTRBUF + GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag + 18 + 18 + read-write + + + 0 + No compare match of GTADTRB at up-counting is generated. + #0 + + + 1 + A compare match of GTADTRB at up-counting is generated. + #1 + + + + + ADTRADF + GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag + 17 + 17 + read-write + + + 0 + No compare match of GTADTRA at down-counting is generated. + #0 + + + 1 + A compare match of GTADTRA at down-counting is generated. + #1 + + + + + ADTRAUF + GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable + 16 + 16 + read-write + + + 0 + No compare match of GTADTRA at up-counting is generated. + #0 + + + 1 + A compare match of GTADTRA at up-counting is generated. + #1 + + + + + TUCF + Count Direction Flag + 15 + 15 + read-only + + + 0 + The GTCNT counter counts downward. + #0 + + + 1 + The GTCNT counter counts upward. + #1 + + + + + ITCNT + GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) + 8 + 10 + read-only + + + TCFPU + Underflow Flag + 7 + 7 + read-write + + + 0 + No underflow (trough) has occurred. + #0 + + + 1 + An underflow (trough) has occurred. + #1 + + + + + TCFPO + Overflow Flag + 6 + 6 + read-write + + + 0 + No overflow (crest) has occurred. + #0 + + + 1 + An overflow (crest) has occurred. + #1 + + + + + TCFF + Input Compare Match Flag F + 5 + 5 + read-write + + + 0 + No compare match of GTCCRF is generated. + #0 + + + 1 + A compare match of GTCCRF is generated. + #1 + + + + + TCFE + Input Compare Match Flag E + 4 + 4 + read-write + + + 0 + No compare match of GTCCRE is generated. + #0 + + + 1 + A compare match of GTCCRE is generated. + #1 + + + + + TCFD + Input Compare Match Flag D + 3 + 3 + read-write + + + 0 + No compare match of GTCCRD is generated. + #0 + + + 1 + A compare match of GTCCRD is generated. + #1 + + + + + TCFC + Input Compare Match Flag C + 2 + 2 + read-write + + + 0 + No compare match of GTCCRC is generated. + #0 + + + 1 + A compare match of GTCCRC is generated. + #1 + + + + + TCFB + Input Capture/Compare Match Flag B + 1 + 1 + read-write + + + 0 + No input capture/compare match of GTCCRB is generated. + #0 + + + 1 + An input capture/compare match of GTCCRB is generated. + #1 + + + + + TCFA + Input Capture/Compare Match Flag A + 0 + 0 + read-write + + + 0 + No input capture/compare match of GTCCRA is generated. + #0 + + + 1 + An input capture/compare match of GTCCRA is generated. + #1 + + + + + + + GTBER + General PWM Timer Buffer Enable Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADTDB + GTADTRB Double Buffer Operation + 30 + 30 + read-write + + + 0 + Single buffer operation (GTADTBRB --> GTADTRB) + #0 + + + 1 + Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) + #1 + + + + + ADTTB + GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 28 + 29 + read-write + + + 00 + No transfer + #00 + + + 01 + Transfer at crest + #01 + + + 10 + Transfer at trough + #10 + + + 11 + Transfer at both crest and trough + #11 + + + + + ADTDA + GTADTRA Double Buffer Operation + 26 + 26 + read-write + + + 0 + Single buffer operation (GTADTBRA --> GTADTRA) + #0 + + + 1 + Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) + #1 + + + + + ADTTA + GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 24 + 25 + read-write + + + 00 + No transfer + #00 + + + 01 + Transfer at crest + #01 + + + 10 + Transfer at trough + #10 + + + 11 + Transfer at both crest and trough + #11 + + + + + CCRSWT + GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. + 22 + 22 + write-only + + + 0 + no effect + #0 + + + 1 + Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. + #1 + + + + + PR + GTPR Buffer Operation + 20 + 21 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTPBR --> GTPR) + #01 + + + others + Setting prohibited + true + + + + + CCRB + GTCCRB Buffer Operation + 18 + 19 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTCCRB <--> GTCCRE) + #01 + + + 10 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #10 + + + 11 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #11 + + + + + CCRA + GTCCRA Buffer Operation + 16 + 17 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTCCRA <--> GTCCRC) + #01 + + + 10 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #10 + + + 11 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #11 + + + + + BD3 + BD[3]: GTDV Buffer Operation DisableBD[2] + 3 + 3 + read-write + + + 0 + Enable buffer operation + #0 + + + 1 + Disable buffer operation + #1 + + + + + BD2 + BD[2]: GTADTR Buffer Operation DisableBD + 2 + 2 + read-write + + + 0 + Enable buffer operation + #0 + + + 1 + Disable buffer operation + #1 + + + + + BD1 + BD[1]: GTPR Buffer Operation Disable + 1 + 1 + read-write + + + 0 + Buffer operation is enabled + #0 + + + 1 + Buffer operation is disabled + #1 + + + + + BD0 + BD[0]: GTCCR Buffer Operation Disable + 0 + 0 + read-write + + + 0 + Buffer operation is enabled + #0 + + + 1 + Buffer operation is disabled + #1 + + + + + + + GTITC + General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register + 0x44 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADTBL + GTADTRB A/D Converter Start Request Link + 14 + 14 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ADTAL + GTADTRA A/D Converter Start Request Link + 12 + 12 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function + #1 + + + + + IVTT + GPT_OVF/GPT_UDF Interrupt Skipping Count Select + 8 + 10 + read-write + + + 000 + No skipping + #000 + + + 001 + Skipping count of 1 + #001 + + + 010 + Skipping count of 2 + #010 + + + 011 + Skipping count of 3 + #011 + + + 100 + Skipping count of 4 + #100 + + + 101 + Skipping count of 5 + #101 + + + 110 + Skipping count of 6 + #110 + + + 111 + Skipping count of 7. + #111 + + + + + IVTC + GPT_OVF/GPT_UDF Interrupt Skipping Function Select + 6 + 7 + read-write + + + 00 + Do not perform skipping + #00 + + + 01 + Count and skip both overflow and underflow for saw waves and crest for triangle waves + #01 + + + 10 + Count and skip both overflow and underflow for saw waves and trough for triangle waves + #10 + + + 11 + Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. + #11 + + + + + ITLF + GTCCRF Compare Match Interrupt Link + 5 + 5 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLE + GTCCRE Compare Match Interrupt Link + 4 + 4 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLD + GTCCRD Compare Match Interrupt Link + 3 + 3 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLC + GTCCRC Compare Match Interrupt Link + 2 + 2 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLB + GTCCRB Compare Match/Input Capture Interrupt Link + 1 + 1 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLA + GTCCRA Compare Match/Input Capture Interrupt Link + 0 + 0 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + + + GTCNT + General PWM Timer Counter + 0x48 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GTCNT + Counter + 0 + 31 + read-write + + + + + 6 + 4 + + + A + A + 0 + + + B + B + 1 + + + C + C + 2 + + + E + E + 3 + + + D + D + 4 + + + F + F + 5 + + + GTCCR[%s] + General PWM Timer Compare Capture Register + 0x4C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTCCR + Compare Capture Register A + 0 + 31 + read-write + + + + + GTPR + General PWM Timer Cycle Setting Register + 0x64 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPR + Cycle Setting Register + 0 + 31 + read-write + + + + + GTPBR + General PWM Timer Cycle Setting Buffer Register + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPBR + Cycle Setting Buffer Register + 0 + 31 + read-write + + + + + GTPDBR + General PWM Timer Cycle Setting Double-Buffer Register + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPDBR + Cycle Setting Double-Buffer Register + 0 + 31 + read-write + + + + + GTADTRA + A/D Converter Start Request Timing Register A + 0x70 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRA + A/D Converter Start Request Timing Register A + 0 + 31 + read-write + + + + + GTADTRB + A/D Converter Start Request Timing Register B + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRB + A/D Converter Start Request Timing Register B + 0 + 31 + read-write + + + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0 + 31 + read-write + + + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0 + 31 + read-write + + + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0 + 31 + read-write + + + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0 + 31 + read-write + + + + + GTDTCR + General PWM Timer Dead Time Control Register + 0x88 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDFER + GTDVD Setting + 8 + 8 + read-write + + + 0 + Set GTDVU and GTDVD separately + #0 + + + 1 + Automatically set the value written to GTDVU to GTDVD + #1 + + + + + TDBDE + GTDVD Buffer Operation Enable + 5 + 5 + read-write + + + 0 + Disable GTDVD buffer operation + #0 + + + 1 + Enable GTDVD buffer operation + #1 + + + + + TDBUE + GTDVU Buffer Operation Enable + 4 + 4 + read-write + + + 0 + Disable GTDVU buffer operation + #0 + + + 1 + Enable GTDVU buffer operation + #1 + + + + + TDE + Negative-Phase Waveform Setting + 0 + 0 + read-write + + + 0 + GTCCRB is set without using GTDVU and GTDVD. + #0 + + + 1 + GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. + #1 + + + + + + + GTDVU + General PWM Timer Dead Time Value Register U + 0x8C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVU + Dead Time Value Register U + 0 + 31 + read-write + + + + + GTDVD + General PWM Timer Dead Time Value Register D + 0x90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVD + Dead Time Value Register D + 0 + 31 + read-write + + + + + GTDBU + General PWM Timer Dead Time Buffer Register U + 0x94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDVU + Dead Time Buffer Register U + 0 + 31 + read-write + + + + + GTDBD + General PWM Timer Dead Time Buffer Register D + 0x98 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTDBD + Dead Time Buffer Register D + 0 + 31 + read-write + + + + + GTSOS + General PWM Timer Output Protection Function Status Register + 0x9C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SOS + Output Protection Function Status + 0 + 1 + read-only + + + 00 + Normal operation + #00 + + + 01 + Protected state (GTCCRA = 0 is set during transfer at trough or crest) + #01 + + + 10 + Protected state (GTCCRA >= GTPR is set during transfer at trough) + #10 + + + 11 + Protected state (GTCCRA >= GTPR is set during transfer at crest) + #11 + + + + + + + GTSOTR + General PWM Timer Output Protection Function Temporary Release Register + 0xA0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SOTR + Output Protection Function Temporary Release + 0 + 0 + read-write + + + 0 + Do not release protected state + #0 + + + 1 + Release protected state + #1 + + + + + + + + + R_GPT1 + 0x40078100 + + + R_GPT2 + 0x40078200 + + + R_GPT3 + 0x40078300 + + + R_GPT4 + 0x40078400 + + + R_GPT5 + 0x40078500 + + + R_GPT6 + 0x40078600 + + + R_GPT7 + 0x40078700 + + + R_GPT8 + 0x40078800 + + + R_GPT9 + 0x40078900 + + + R_GPT10 + 0x40078A00 + + + R_GPT11 + 0x40078B00 + + + R_GPT12 + 0x40078C00 + + + R_GPT13 + 0x40078D00 + + + R_GPT_ODC + PWM Delay Generation Circuit + 0x4007B000 + + 0x00000000 + 0x004 + registers + + + 0x00000018 + 0x020 + registers + + + + 4 + 4 + GTDLYR[%s] + PWM DELAY RISING + 0x18 + + A + GTIOCA Output Delay Register + 0 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + B + GTIOCB Output Delay Register + 2 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + + GTDLYF[%s] + PWM DELAY FALLING + 0x28 + + + GTDLYCR1 + PWM Output Delay Control Register1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + DLLMOD + DLL Mode Select + 8 + 8 + read-write + + + 0 + 5 bit-mode + #0 + + + 1 + 4 bit-mode + #1 + + + + + DLYRST + PWM Delay Generation Circuit Reset + 1 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Reset + #1 + + + + + DLLEN + DLL Operation Enable + 0 + 0 + read-write + + + 0 + DLL operation is disabled + #0 + + + 1 + DLL operation is enabled + #1 + + + + + + + GTDLYCR2 + PWM Output Delay Control Register2 + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + 1 + 1 + DLYDENB%s + PWM Delay Generation Circuit Disenable for GTIOCB + 12 + 12 + read-write + + + 0 + Delay generation circuit of GTIOCB is based on DLYEN1. + #0 + + + 1 + Delay generation circuit of GTIOCB is disabled. + #1 + + + + + 1 + 1 + DLYEN%s + PWM Delay Generation Circuit enable + 8 + 8 + read-write + + + 0 + Delay generation circuit of channel is enabled + #0 + + + 1 + Delay generation circuit of channel is disabled. + #1 + + + + + 4 + 1 + DLYBS%s + PWM Delay Generation Circuit bypass + 0 + 0 + read-write + + + 0 + Delay generation circuit of channel is bypassed. + #0 + + + 1 + Delay generation circuit of channel is not bypassed. + #1 + + + + + + + + + R_GPT_OPS + Output Phase Switching for GPT + 0x40078FF0 + + 0x00000000 + 0x04 + registers + + + + OPSCR + Output Phase Switching Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NFCS + External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. + 30 + 31 + read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + + + + NFEN + External Input Noise Filter Enable + 29 + 29 + read-write + + + 0 + Do not use a noise filter to the external input. + #0 + + + 1 + Use a noise filter to the external input. + #1 + + + + + GODF + Group output disable function + 26 + 26 + read-write + + + 0 + This bit function is ignored. + #0 + + + 1 + Group disable will clear OPSCR.EN Bit. + #1 + + + + + GRP + Output disabled source selection + 24 + 25 + read-write + + + 00 + Select Group A output disable source + #00 + + + 01 + Select Group B output disable source + #01 + + + 10 + Select Group C output disable source + #10 + + + 11 + Select Group D output disable source + #11 + + + + + ALIGN + Input phase alignment + 21 + 21 + read-write + + + 0 + Input phase is aligned to PCLK. + #0 + + + 1 + Input phase is aligned PWM. + #1 + + + + + RV + Output phase rotation direction reversal + 20 + 20 + read-write + + + 0 + U/V/W-Phase output + #0 + + + 1 + Output to reverse the V / W-phase + #1 + + + + + INV + Invert-Phase Output Control + 19 + 19 + read-write + + + 0 + Positive Logic (Active High)output + #0 + + + 1 + Negative Logic (Active Low)output + #1 + + + + + N + Negative-Phase Output (N) Control + 18 + 18 + read-write + + + 0 + Level signal output + #0 + + + 1 + PWM signal output (PWM of GPT0) + #1 + + + + + P + Positive-Phase Output (P) Control + 17 + 17 + read-write + + + 0 + Level signal output + #0 + + + 1 + PWM signal output (PWM of GPT0) + #1 + + + + + FB + External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. + 16 + 16 + read-write + + + 0 + Select the external input. + #0 + + + 1 + Select the soft setting(OPSCR.UF, VF, WF). + #1 + + + + + EN + Enable-Phase Output Control + 8 + 8 + read-write + + + 0 + Not Output(Hi-Z external terminals). + #0 + + + 1 + Output + #1 + + + + + W + Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 6 + 6 + read-only + + + V + Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 5 + 5 + read-only + + + U + Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 4 + 4 + read-only + + + WF + Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 2 + 2 + read-write + + + VF + Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 1 + 1 + read-write + + + UF + Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 0 + 0 + read-write + + + + + + + R_GPT_POEG0 + Port Output Enable for GPT + 0x40042000 + + 0x00000000 + 0x04 + registers + + + + POEGG + POEG Group Setting Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NFCS + Noise Filter Clock Select + 30 + 31 + read-write + + + 00 + Sampling GTETRG pin input level for three times in every PCLKB. + #00 + + + 01 + Sampling GTETRG pin input level for three times in every PCLKB /8. + #01 + + + 10 + Sampling GTETRG pin input level for three times in every PCLKB /32. + #10 + + + 11 + Sampling GTETRG pin input level for three times in every PCLKB /128. + #11 + + + + + NFEN + Noise Filter Enable + 29 + 29 + read-write + + + 0 + Filtering noise disabled + #0 + + + 1 + Filtering noise enabled + #1 + + + + + INV + GTETRG Input Reverse + 28 + 28 + read-write + + + 0 + GTETRG Input + #0 + + + 1 + GTETRG Input Reversed. + #1 + + + + + ST + GTETRG Input Status Flag + 16 + 16 + read-only + + + 0 + GTETRG input after filtering is 0. + #0 + + + 1 + GTETRG input after filtering is 1. + #1 + + + + + 6 + 1 + CDRE%s + Comparator Disable Request Enable. Note: Can be modified only once after a reset. + 8 + 8 + read-write + + + 0 + A disable request of comparator 0 disabled. + #0 + + + 1 + A disable request of comparator 0 enabled. + #1 + + + + + OSTPE + Oscillation Stop Detection EnableNote: Can be modified only once after a reset. + 6 + 6 + read-write + + + 0 + A output-disable request from the oscillation stop detection disabled. + #0 + + + 1 + A output-disable request from the oscillation stop detection enabled. + #1 + + + + + IOCE + Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. + 5 + 5 + read-write + + + 0 + Disable output-disable requests from GPT disable request + #0 + + + 1 + Enable output-disable requests from GPT disable request + #1 + + + + + PIDE + Port Input Detection EnableNote: Can be modified only once after a reset. + 4 + 4 + read-write + + + 0 + A output-disable request from the GTETRG pins disabled. + #0 + + + 1 + A output-disable request from the GTETRG pins enabled. + #1 + + + + + SSF + Software Stop Flag + 3 + 3 + read-write + + + 0 + A output-disable request from software has not been generated. + #0 + + + 1 + A output-disable request from software has been generated. + #1 + + + + + OSTPF + Oscillation Stop Detection Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + A output-disable request from the oscillation stop detection has not been generated. + #0 + + + 1 + A output-disable request from the oscillation stop detection has been generated. + #1 + + + + + IOCF + Real Time Overcurrent Detection Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + A output-disable request from GPT disable request or comparator interrupt has not been generated. + #0 + + + 1 + A output-disable request from GPT disable request or comparator interrupt has been generated. + #1 + + + + + PIDF + Port Input Detection Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + A output-disable request from the GTETRG pin has not been generated. + #0 + + + 1 + A output-disable request from the GTETRG pin has been generated. + #1 + + + + + + + + + R_GPT_POEG1 + 0x40042100 + + + R_GPT_POEG2 + 0x40042200 + + + R_GPT_POEG3 + 0x40042300 + + + R_ICU + Interrupt Controller Unit + 0x40006000 + + 0x00000000 + 0x010 + registers + + + 0x00000100 + 0x01 + registers + + + 0x00000120 + 0x02 + registers + + + 0x00000130 + 0x02 + registers + + + 0x00000140 + 0x02 + registers + + + 0x000001A0 + 0x04 + registers + + + 0x00000200 + 0x02 + registers + + + 0x00000280 + 0x020 + registers + + + 0x00000300 + 0x180 + registers + + + + 16 + 0x1 + IRQCR[%s] + IRQ Control Register %s + 0x000 + 8 + read-write + 0x00 + 0xFF + + + FLTEN + IRQ Digital Filter Enable + 7 + 7 + read-write + + + 0 + Digital filter disabled. + #0 + + + 1 + Digital filter enabled. + #1 + + + + + FCLKSEL + IRQ Digital Filter Sampling Clock Select + 4 + 5 + read-write + + + 00 + PCLKB + #00 + + + 01 + PCLKB/8 + #01 + + + 10 + PCLKB/32 + #10 + + + 11 + PCLKB/64 + #11 + + + + + IRQMD + IRQ Detection Sense Select + 0 + 1 + read-write + + + 00 + Falling edge + #00 + + + 01 + Rising edge + #01 + + + 10 + Rising and falling edges + #10 + + + 11 + Low level + #11 + + + + + + + NMISR + Non-Maskable Interrupt Status Register + 0x140 + 16 + read-only + 0x0000 + 0xFFFF + + + SPEST + CPU Stack pointer monitor Interrupt Status Flag + 12 + 12 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + BUSMST + MPU Bus Master Error Interrupt Status Flag + 11 + 11 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + BUSSST + MPU Bus Slave Error Interrupt Status Flag + 10 + 10 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + RECCST + RAM ECC Error Interrupt Status Flag + 9 + 9 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + RPEST + RAM Parity Error Interrupt Status Flag + 8 + 8 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + NMIST + NMI Status Flag + 7 + 7 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + OSTST + Oscillation Stop Detection Interrupt Status Flag + 6 + 6 + read-only + + + 0 + Interrupt not requested for main oscillation stop + #0 + + + 1 + Interrupt requested for main oscillation stop. + #1 + + + + + VBATTST + VBATT monitor Interrupt Status Flag + 4 + 4 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + LVD2ST + Voltage-Monitoring 2 Interrupt Status Flag + 3 + 3 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + LVD1ST + Voltage-Monitoring 1 Interrupt Status Flag + 2 + 2 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + WDTST + WDT Underflow/Refresh Error Status Flag + 1 + 1 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + IWDTST + IWDT Underflow/Refresh Error Status Flag + 0 + 0 + read-only + + + 0 + Interrupt not requested + #0 + + + 1 + Interrupt requested. + #1 + + + + + + + NMIER + Non-Maskable Interrupt Enable Register + 0x120 + 16 + read-write + 0x0000 + 0xFFFF + + + SPEEN + CPU Stack pointer monitor Interrupt Enable + 12 + 12 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + BUSMEN + MPU Bus Master Error Interrupt Enable + 11 + 11 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + BUSSEN + MPU Bus Slave Error Interrupt Enable + 10 + 10 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + RECCEN + RAM ECC Error Interrupt Enable + 9 + 9 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + RPEEN + RAM Parity Error Interrupt Enable + 8 + 8 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + NMIEN + NMI Pin Interrupt Enable + 7 + 7 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + OSTEN + Oscillation Stop Detection Interrupt Enable + 6 + 6 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + VBATTEN + VBATT monitor Interrupt Enable + 4 + 4 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + LVD2EN + Voltage-Monitoring 2 Interrupt Enable + 3 + 3 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + LVD1EN + Voltage-Monitoring 1 Interrupt Enable + 2 + 2 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + WDTEN + WDT Underflow/Refresh Error Interrupt Enable + 1 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + IWDTEN + IWDT Underflow/Refresh Error Interrupt Enable + 0 + 0 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + + + NMICLR + Non-Maskable Interrupt Status Clear Register + 0x130 + 16 + read-write + 0x0000 + 0xFFFF + + + SPECLR + CPU Stack Pointer Monitor Interrupt Clear + 12 + 12 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.SPEST flag. + #1 + + + + + BUSMCLR + Bus Master Error Clear + 11 + 11 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.BUSMST flag. + #1 + + + + + BUSSCLR + Bus Slave Error Clear + 10 + 10 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.BUSSST flag. + #1 + + + + + RECCCLR + SRAM ECC Error Clear + 9 + 9 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.RECCST flag. + #1 + + + + + RPECLR + SRAM Parity Error Clear + 8 + 8 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.RPEST flag. + #1 + + + + + NMICLR + NMI Clear + 7 + 7 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.NMIST flag. + #1 + + + + + OSTCLR + OST Clear + 6 + 6 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.OSTST flag. + #1 + + + + + VBATTCLR + VBATT Clear + 4 + 4 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.VBATTST flag. + #1 + + + + + LVD2CLR + LVD2 Clear + 3 + 3 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.LVD2ST flag. + #1 + + + + + LVD1CLR + LVD1 Clear + 2 + 2 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.LVD1ST flag. + #1 + + + + + WDTCLR + WDT Clear + 1 + 1 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.WDTST flag. + #1 + + + + + IWDTCLR + IWDT Clear + 0 + 0 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the NMISR.IWDTST flag. + #1 + + + + + + + NMICR + NMI Pin Interrupt Control Register + 0x100 + 8 + read-write + 0x00 + 0xFF + + + NFLTEN + NMI Digital Filter Enable + 7 + 7 + read-write + + + 0 + Digital filter is disabled. + #0 + + + 1 + Digital filter is enabled. + #1 + + + + + NFCLKSEL + NMI Digital Filter Sampling Clock Select + 4 + 5 + read-write + + + 00 + PCLKB + #00 + + + 01 + PCLKB/8 + #01 + + + 10 + PCLKB/32 + #10 + + + 11 + PCLKB/64 + #11 + + + + + NMIMD + NMI Detection Set + 0 + 0 + read-write + + + 0 + Falling edge + #0 + + + 1 + Rising edge + #1 + + + + + + + 96 + 0x4 + IELSR[%s] + ICU Event Link Setting Register %s + 0x300 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DTCE + DTC Activation Enable + 24 + 24 + read-write + + + 0 + DTC activation is disabled + #0 + + + 1 + DTC activation is enabled + #1 + + + + + IR + Interrupt Status Flag + 16 + 16 + read-write + + + 0 + No interrupt request is generated + #0 + + + 1 + An interrupt request is generated ( 1 write to the IR bit is prohibited. ) + #1 + + + + + IELS + ICU Event selection to NVICSet the number for the event signal to be linked . + 0 + 8 + read-write + + + 0x000 + Nothing is selected + 0x000 + + + others + See Event Table + true + + + + + + + 8 + 0x4 + DELSR[%s] + DMAC Event Link Setting Register + 0x280 + 32 + read-write + 0x0000 + 0xFFFF + + + IR + Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited. + 16 + 16 + read-write + + + 0x0 + No interrupt request is generated. + #0 + + + 0x1 + An interrupt request is generated. + #1 + + + + + DELS + Event selection to DMAC Start request + 0 + 8 + read-write + + + 0x000 + Nothing is selected. + 0x000 + + + others + See Event Table + true + + + + + + + SELSR0 + Snooze Event Link Setting Register + 0x200 + 16 + read-write + 0x0000 + 0xFFFF + + + SELS + SYS Event Link Select + 0 + 8 + read-write + + + 0x000 + Nothing is selected + 0x000 + + + + + + + WUPEN + Wake Up Interrupt Enable Register + 0x1A0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + IIC0WUPEN + IIC0 address match interrupt S/W standby returns enable + 31 + 31 + read-write + + + 0 + S/W standby returns by IIC0 address match interrupt is disabled + #0 + + + 1 + S/W standby returns by IIC0 address match interrupt is enabled + #1 + + + + + AGT1CBWUPEN + AGT1 compare match B interrupt S/W standby returns enable + 30 + 30 + read-write + + + 0 + S/W standby returns by AGT1 compare match B interrupt is disabled + #0 + + + 1 + S/W standby returns by AGT1 compare match B interrupt is enabled + #1 + + + + + AGT1CAWUPEN + AGT1 compare match A interrupt S/W standby returns enable + 29 + 29 + read-write + + + 0 + S/W standby returns by AGT1 compare match A interrupt is disabled + #0 + + + 1 + S/W standby returns by AGT1 compare match A interrupt is enabled + #1 + + + + + AGT1UDWUPEN + AGT1 underflow interrupt S/W standby returns enable + 28 + 28 + read-write + + + 0 + S/W standby returns by AGT1 underflow interrupt is disabled + #0 + + + 1 + S/W standby returns by AGT1 underflow interrupt is enabled + #1 + + + + + USBFSWUPEN + USBFS interrupt S/W standby returns enable + 27 + 27 + read-write + + + 0 + S/W standby returns by USBFS interrupt is disabled + #0 + + + 1 + S/W standby returns by USBFS interrupt is enabled + #1 + + + + + USBHSWUPEN + USBHS interrupt S/W standby returns enable bit + 26 + 26 + read-write + + + 0 + S/W standby returns by USBHS interrupt is disabled + #0 + + + 1 + S/W standby returns by USBHS interrupt is enabled + #1 + + + + + RTCPRDWUPEN + RCT period interrupt S/W standby returns enable + 25 + 25 + read-write + + + 0 + S/W standby returns by RTC period interrupt is disabled + #0 + + + 1 + S/W standby returns by RTC period interrupt is enabled + #1 + + + + + RTCALMWUPEN + RTC alarm interrupt S/W standby returns enable + 24 + 24 + read-write + + + 0 + S/W standby returns by RTC alarm interrupt is disabled + #0 + + + 1 + S/W standby returns by RTC alarm interrupt is enabled + #1 + + + + + ACMPLP0WUPEN + ACMPLP0 interrupt S/W standby returns enable + 23 + 23 + read-write + + + 0 + S/W standby returns by ACMPLP0 interrupt is disabled + #0 + + + 1 + S/W standby returns by ACMPLP0 interrupt is enabled + #1 + + + + + ACMPHS0WUPEN + ACMPHS0 interrupt S/W standby returns enable bit + 22 + 22 + read-write + + + 0 + S/W standby returns by ACMPHS0 interrupt is disabled + #0 + + + 1 + S/W standby returns by ACMPHS0 interrupt is enabled + #1 + + + + + VBATTWUPEN + VBATT monitor interrupt S/W standby returns enable + 20 + 20 + read-write + + + 0 + S/W standby returns by VBATT monitor interrupt is disabled + #0 + + + 1 + S/W standby returns by VBATT monitor interrupt is enabled + #1 + + + + + LVD2WUPEN + LVD2 interrupt S/W standby returns enable + 19 + 19 + read-write + + + 0 + S/W standby returns by LVD2 interrupt is disabled + #0 + + + 1 + S/W standby returns by LVD2 interrupt is enabled + #1 + + + + + LVD1WUPEN + LVD1 interrupt S/W standby returns enable + 18 + 18 + read-write + + + 0 + S/W standby returns by LVD1 interrupt is disabled + #0 + + + 1 + S/W standby returns by LVD1 interrupt is enabled + #1 + + + + + KEYWUPEN + Key interrupt S/W standby returns enable + 17 + 17 + read-write + + + 0 + S/W standby returns by KEY interrupt is disabled + #0 + + + 1 + S/W standby returns by KEY interrupt is enabled + #1 + + + + + IWDTWUPEN + IWDT interrupt S/W standby returns enable + 16 + 16 + read-write + + + 0 + S/W standby returns by IWDT interrupt is disabled + #0 + + + 1 + S/W standby returns by IWDT interrupt is enabled + #1 + + + + + 16 + 0x01 + IRQWUPEN%s + IRQ interrupt S/W standby returns enable + 0 + 0 + read-write + + + 0 + S/W standby returns by IRQ interrupt is disabled + #0 + + + 1 + S/W standby returns by IRQ interrupt is enabled + #1 + + + + + + + + + R_IIC0 + I2C Bus Interface + 0x40053000 + + 0x00000000 + 0x014 + registers + + + 0x00000016 + 0x002 + registers + + + + 3 + 0x2 + SAR[%s] + Slave Address Registers + 0x0A + 16 + + L + Slave Address Register L + 0x0 + 8 + read-write + 0x00 + 0xFF + + + SVA + A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } + 0 + 7 + read-write + + + + + U + Slave Address Register U + 0x01 + 8 + read-write + 0x00 + 0xFF + + + SVA9 + 10-Bit Address(bit9) + 2 + 2 + read-write + + + SVA8 + 10-Bit Address(bit8) + 1 + 1 + read-write + + + FS + 7-Bit/10-Bit Address Format Selection + 0 + 0 + read-write + + + 0 + The 7-bit address format is selected. + #0 + + + 1 + The 10-bit address format is selected. + #1 + + + + + + + + ICCR1 + I2C Bus Control Register 1 + 0x00 + 8 + read-write + 0x1F + 0xFF + + + ICE + I2C Bus Interface Enable + 7 + 7 + read-write + + + 0 + Disable (SCLn and SDAn pins in inactive state) + #0 + + + 1 + Enable (SCLn and SDAn pins in active state) + #1 + + + + + IICRST + I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). + 6 + 6 + read-write + + + 0 + Releases the RIIC reset or internal reset. + #0 + + + 1 + Initiates the RIIC reset or internal reset. + #1 + + + + + CLO + Extra SCL Clock Cycle Output + 5 + 5 + read-write + + + 0 + Does not output an extra SCL clock cycle. + #0 + + + 1 + Outputs an extra SCL clock cycle. + #1 + + + + + SOWP + SCLO/SDAO Write Protect + 4 + 4 + read-write + + + 0 + Bits SCLO and SDAO can be written + #0 + + + 1 + Bits SCLO and SDAO are protected. + #1 + + + + + SCLO + SCL Output Control/Monitor + 3 + 3 + read-write + + + 0 + (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. + #0 + + + 1 + (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. + #1 + + + + + SDAO + SDA Output Control/Monitor + 2 + 2 + read-write + + + 0 + (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. + #0 + + + 1 + (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. + #1 + + + + + SCLI + SCL Line Monitor + 1 + 1 + read-only + + + 0 + SCLn line is low. + #0 + + + 1 + SCLn line is high. + #1 + + + + + SDAI + SDA Line Monitor + 0 + 0 + read-only + + + 0 + SDAn line is low. + #0 + + + 1 + SDAn line is high. + #1 + + + + + + + ICCR2 + I2C Bus Control Register 2 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + BBSY + Bus Busy Detection Flag + 7 + 7 + read-only + + + 0 + The I2C bus is released (bus free state). + #0 + + + 1 + The I2C bus is occupied (bus busy state). + #1 + + + + + MST + Master/Slave Mode + 6 + 6 + read-write + + + 0 + Slave mode + #0 + + + 1 + Master mode + #1 + + + + + TRS + Transmit/Receive Mode + 5 + 5 + read-write + + + 0 + Receive mode + #0 + + + 1 + Transmit mode + #1 + + + + + SP + Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. + 3 + 3 + read-write + + + 0 + Does not request to issue a stop condition. + #0 + + + 1 + Requests to issue a stop condition. + #1 + + + + + RS + Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. + 2 + 2 + read-write + + + 0 + Does not request to issue a restart condition. + #0 + + + 1 + Requests to issue a restart condition. + #1 + + + + + ST + Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). + 1 + 1 + read-write + + + 0 + Does not request to issue a start condition. + #0 + + + 1 + Requests to issue a start condition. + #1 + + + + + + + ICMR1 + I2C Bus Mode Register 1 + 0x02 + 8 + read-write + 0x08 + 0xFF + + + MTWP + MST/TRS Write Protect + 7 + 7 + read-write + + + 0 + Disables writing to the MST and TRS bits in ICCR2. + #0 + + + 1 + Enables writing to the MST and TRS bits in ICCR2. + #1 + + + + + CKS + Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) + 4 + 6 + read-write + + + 000 + PCLKB/1 clock + #000 + + + 001 + PCLKB/2 clock + #001 + + + 010 + PCLKB/4 clock + #010 + + + 011 + PCLKB/8 clock + #011 + + + 100 + PCLKB/16 clock + #100 + + + 101 + PCLKB/32 clock + #101 + + + 110 + PCLKB/64 clock + #110 + + + 111 + PCLKB/128 clock + #111 + + + + + BCWP + BC Write Protect(This bit is read as 1.) + 3 + 3 + write-only + + + 0 + Enables a value to be written in the BC[2:0] bits. + #0 + + + 1 + Disables a value to be written in the BC[2:0] bits. + #1 + + + + + BC + Bit Counter + 0 + 2 + read-write + + + 000 + 9 bits + #000 + + + 001 + 2 bits + #001 + + + 010 + 3 bits + #010 + + + 011 + 4 bits + #011 + + + 100 + 5 bits + #100 + + + 101 + 6 bits + #101 + + + 110 + 7 bits + #110 + + + 111 + 8 bits + #111 + + + + + + + ICMR2 + I2C Bus Mode Register 2 + 0x03 + 8 + read-write + 0x06 + 0xFF + + + DLCS + SDA Output Delay Clock Source Select + 7 + 7 + read-write + + + 0 + The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. + #0 + + + 1 + The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. + #1 + + + + + SDDL + SDA Output Delay Counter + 4 + 6 + read-write + + + 000 + No output delay + #000 + + + 001 + 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) + #001 + + + 010 + 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) + #010 + + + 011 + 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) + #011 + + + 100 + 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) + #100 + + + 101 + 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) + #101 + + + 110 + 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) + #110 + + + 111 + 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) + #111 + + + + + TMOH + Timeout H Count Control + 2 + 2 + read-write + + + 0 + Count is disabled while the SCLn line is at a high level. + #0 + + + 1 + Count is enabled while the SCLn line is at a high level. + #1 + + + + + TMOL + Timeout L Count Control + 1 + 1 + read-write + + + 0 + Count is disabled while the SCLn line is at a low level. + #0 + + + 1 + Count is enabled while the SCLn line is at a low level. + #1 + + + + + TMOS + Timeout Detection Time Select + 0 + 0 + read-write + + + 0 + Long mode is selected. + #0 + + + 1 + Short mode is selected. + #1 + + + + + + + ICMR3 + I2C Bus Mode Register 3 + 0x04 + 8 + read-write + 0x00 + 0xFF + + + SMBS + SMBus/I2C Bus Selection + 7 + 7 + read-write + + + 0 + The I2C bus is selected. + #0 + + + 1 + The SMBus is selected. + #1 + + + + + WAIT + WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. + 6 + 6 + read-write + + + 0 + No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) + #0 + + + 1 + WAIT (The period between ninth clock cycle and first clock cycle is held low.) + #1 + + + + + RDRFS + RDRF Flag Set Timing Selection + 5 + 5 + read-write + + + 0 + The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) + #0 + + + 1 + The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) + #1 + + + + + ACKWP + ACKBT Write Protect + 4 + 4 + read-write + + + 0 + Modification of the ACKBT bit is disabled. + #0 + + + 1 + Modification of the ACKBT bit is enabled. + #1 + + + + + ACKBT + Transmit Acknowledge + 3 + 3 + read-write + + + 0 + A 0 is sent as the acknowledge bit (ACK transmission). + #0 + + + 1 + A 1 is sent as the acknowledge bit (NACK transmission). + #1 + + + + + ACKBR + Receive Acknowledge + 2 + 2 + read-only + + + 0 + A 0 is received as the acknowledge bit (ACK reception). + #0 + + + 1 + A 1 is received as the acknowledge bit (NACK reception). + #1 + + + + + NF + Noise Filter Stage Selection + 0 + 1 + read-write + + + 00 + Noise of up to one fIIC cycle is filtered out (single-stage filter). + #00 + + + 01 + Noise of up to two fIIC cycles is filtered out (2-stage filter). + #01 + + + 10 + Noise of up to three fIIC cycles is filtered out (3-stage filter). + #10 + + + 11 + Noise of up to four fIIC cycles is filtered out (4-stage filter) + #11 + + + + + + + ICFER + I2C Bus Function Enable Register + 0x05 + 8 + read-write + 0x72 + 0xFF + + + FMPE + Fast-mode Plus Enable + 7 + 7 + read-write + + + 0 + No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. + #0 + + + 1 + An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. + #1 + + + + + SCLE + SCL Synchronous Circuit Enable + 6 + 6 + read-write + + + 0 + No SCL synchronous circuit is used. + #0 + + + 1 + An SCL synchronous circuit is used. + #1 + + + + + NFE + Digital Noise Filter Circuit Enable + 5 + 5 + read-write + + + 0 + No digital noise filter circuit is used. + #0 + + + 1 + A digital noise filter circuit is used. + #1 + + + + + NACKE + NACK Reception Transfer Suspension Enable + 4 + 4 + read-write + + + 0 + Transfer operation is not suspended during NACK reception (transfer suspension disabled). + #0 + + + 1 + Transfer operation is suspended during NACK reception (transfer suspension enabled). + #1 + + + + + SALE + Slave Arbitration-Lost Detection Enable + 3 + 3 + read-write + + + 0 + Slave arbitration-lost detection is disabled. + #0 + + + 1 + Slave arbitration-lost detection is enabled. + #1 + + + + + NALE + NACK Transmission Arbitration-Lost Detection Enable + 2 + 2 + read-write + + + 0 + NACK transmission arbitration-lost detection is disabled. + #0 + + + 1 + NACK transmission arbitration-lost detection is enabled. + #1 + + + + + MALE + Master Arbitration-Lost Detection Enable + 1 + 1 + read-write + + + 0 + Master arbitration-lost detection is disabled. + #0 + + + 1 + Master arbitration-lost detection is enabled. + #1 + + + + + TMOE + Timeout Function Enable + 0 + 0 + read-write + + + 0 + The timeout function is disabled. + #0 + + + 1 + The timeout function is enabled. + #1 + + + + + + + ICSER + I2C Bus Status Enable Register + 0x06 + 8 + read-write + 0x09 + 0xFF + + + HOAE + Host Address Enable + 7 + 7 + read-write + + + 0 + Host address detection is disabled. + #0 + + + 1 + Host address detection is enabled. + #1 + + + + + DIDE + Device-ID Address Detection Enable + 5 + 5 + read-write + + + 0 + Device-ID address detection is disabled. + #0 + + + 1 + Device-ID address detection is enabled. + #1 + + + + + GCAE + General Call Address Enable + 3 + 3 + read-write + + + 0 + General call address detection is disabled. + #0 + + + 1 + General call address detection is enabled. + #1 + + + + + SAR2E + Slave Address Register 2 Enable + 2 + 2 + read-write + + + 0 + Slave address in SARL2 and SARU2 is disabled. + #0 + + + 1 + Slave address in SARL2 and SARU2 is enabled + #1 + + + + + SAR1E + Slave Address Register 1 Enable + 1 + 1 + read-write + + + 0 + Slave address in SARL1 and SARU1 is disabled. + #0 + + + 1 + Slave address in SARL1 and SARU1 is enabled. + #1 + + + + + SAR0E + Slave Address Register 0 Enable + 0 + 0 + read-write + + + 0 + Slave address in SARL0 and SARU0 is disabled. + #0 + + + 1 + Slave address in SARL0 and SARU0 is enabled. + #1 + + + + + + + ICIER + I2C Bus Interrupt Enable Register + 0x07 + 8 + read-write + 0x00 + 0xFF + + + TIE + Transmit Data Empty Interrupt Request Enable + 7 + 7 + read-write + + + 0 + Transmit data empty interrupt request (IIC_TXI) is disabled. + #0 + + + 1 + Transmit data empty interrupt request (IIC_TXI) is enabled. + #1 + + + + + TEIE + Transmit End Interrupt Request Enable + 6 + 6 + read-write + + + 0 + Transmit end interrupt request (IIC_TEI) is disabled. + #0 + + + 1 + Transmit end interrupt request (IIC_TEI) is enabled. + #1 + + + + + RIE + Receive Data Full Interrupt Request Enable + 5 + 5 + read-write + + + 0 + Receive data full interrupt request (IIC_RXI) is disabled. + #0 + + + 1 + Receive data full interrupt request (IIC_RXI) is enabled. + #1 + + + + + NAKIE + NACK Reception Interrupt Request Enable + 4 + 4 + read-write + + + 0 + NACK reception interrupt request (NAKI) is disabled. + #0 + + + 1 + NACK reception interrupt request (NAKI) is enabled. + #1 + + + + + SPIE + Stop Condition Detection Interrupt Request Enable + 3 + 3 + read-write + + + 0 + Stop condition detection interrupt request (SPI) is disabled. + #0 + + + 1 + Stop condition detection interrupt request (SPI) is enabled. + #1 + + + + + STIE + Start Condition Detection Interrupt Request Enable + 2 + 2 + read-write + + + 0 + Start condition detection interrupt request (STI) is disabled. + #0 + + + 1 + Start condition detection interrupt request (STI) is enabled. + #1 + + + + + ALIE + Arbitration-Lost Interrupt Request Enable + 1 + 1 + read-write + + + 0 + Arbitration-lost interrupt request (ALI) is disabled. + #0 + + + 1 + Arbitration-lost interrupt request (ALI) is enabled. + #1 + + + + + TMOIE + Timeout Interrupt Request Enable + 0 + 0 + read-write + + + 0 + Timeout interrupt request (TMOI) is disabled. + #0 + + + 1 + Timeout interrupt request (TMOI) is enabled. + #1 + + + + + + + ICSR1 + I2C Bus Status Register 1 + 0x08 + 8 + read-write + 0x00 + 0xFF + + + HOA + Host Address Detection Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Host address is not detected. + #0 + + + 1 + Host address is detected. + #1 + + + + + DID + Device-ID Address Detection Flag + 5 + 5 + read-write + + + 0 + Device-ID command is not detected. + #0 + + + 1 + Device-ID command is detected. + #1 + + + + + GCA + General Call Address Detection Flag + 3 + 3 + read-write + + + 0 + General call address is not detected. + #0 + + + 1 + General call address is detected. + #1 + + + + + AAS2 + Slave Address 2 Detection Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Slave address 2 is not detected. + #0 + + + 1 + Slave address 2 is detected + #1 + + + + + AAS1 + Slave Address 1 Detection Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Slave address 1 is not detected. + #0 + + + 1 + Slave address 1 is detected. + #1 + + + + + AAS0 + Slave Address 0 Detection Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Slave address 0 is not detected. + #0 + + + 1 + Slave address 0 is detected. + #1 + + + + + + + ICSR2 + I2C Bus Status Register 2 + 0x09 + 8 + read-write + 0x00 + 0xFF + + + TDRE + Transmit Data Empty Flag + 7 + 7 + read-only + + + 0 + ICDRT contains transmit data. + #0 + + + 1 + ICDRT contains no transmit data. + #1 + + + + + TEND + Transmit End Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + Data is being transmitted. + #0 + + + 1 + Data has been transmitted. + #1 + + + + + RDRF + Receive Data Full Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + ICDRR contains no receive data. + #0 + + + 1 + ICDRR contains receive data. + #1 + + + + + NACKF + NACK Detection Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + NACK is not detected. + #0 + + + 1 + NACK is detected. + #1 + + + + + STOP + Stop Condition Detection Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Stop condition is not detected. + #0 + + + 1 + Stop condition is detected. + #1 + + + + + START + Start Condition Detection Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Start condition is not detected. + #0 + + + 1 + Start condition is detected. + #1 + + + + + AL + Arbitration-Lost Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Arbitration is not lost. + #0 + + + 1 + Arbitration is lost. + #1 + + + + + TMOF + Timeout Detection Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Timeout is not detected. + #0 + + + 1 + Timeout is detected. + #1 + + + + + + + ICBRL + I2C Bus Bit Rate Low-Level Register + 0x10 + 8 + read-write + 0xFF + 0xFF + + + BRL + Bit Rate Low-Level Period(Low-level period of SCL clock) + 0 + 4 + read-write + + + + + ICBRH + I2C Bus Bit Rate High-Level Register + 0x11 + 8 + read-write + 0xFF + 0xFF + + + BRH + Bit Rate High-Level Period(High-level period of SCL clock) + 0 + 4 + read-write + + + + + ICDRT + I2C Bus Transmit Data Register + 0x12 + 8 + read-write + 0xFF + 0xFF + + + ICDRT + 8-bit read-write register that stores transmit data. + 0 + 7 + read-write + + + + + ICDRR + I2C Bus Receive Data Register + 0x13 + 8 + read-only + 0x00 + 0xFF + + + ICDRR + 8-bit register that stores the received data + 0 + 7 + read-only + + + + + ICWUR + I2C Bus Wake Up Unit Register + 0x16 + 8 + read-write + 0x10 + 0xFF + + + WUE + Wakeup Function Enable + 7 + 7 + read-write + + + 0 + Wakeup function disabled + #0 + + + 1 + Wakeup function enabled. + #1 + + + + + WUIE + Wakeup Interrupt Request Enable + 6 + 6 + read-write + + + 0 + Wakeup Interrupt Request (IIC0_WUI) disabled + #0 + + + 1 + Wakeup Interrupt Request (IIC0_WUI) enabled. + #1 + + + + + WUF + Wakeup Event Occurrence Flag + 5 + 5 + read-write + + + 0 + Slave address does not match during wakeup function + #0 + + + 1 + Slave address matches during wakeup function. + #1 + + + + + WUACK + ACK bit for Wakeup Mode + 4 + 4 + read-write + + + 0 + State of synchronous operation + #0 + + + 1 + State of asynchronous operation + #1 + + + + + WUAFA + Wakeup Analog Filter Additional Selection + 0 + 0 + read-write + + + 0 + Do not add the wakeup analog filter + #0 + + + 1 + Add the wakeup analog filter. + #1 + + + + + + + ICWUR2 + I2C Bus Wake up Unit Register 2 + 0x17 + 8 + read-write + 0xFD + 0xFF + + + WUSYF + Wake-up Function Synchronous Operation Status Flag + 2 + 2 + read-only + + + 0 + IIC asynchronous circuit enable condition + #0 + + + 1 + IIC synchronous circuit enable condition. + #1 + + + + + WUASYF + Wake-up Function Asynchronous Operation Status Flag + 1 + 1 + read-only + + + 0 + IIC synchronous circuit enable condition + #0 + + + 1 + IIC asynchronous circuit enable condition. + #1 + + + + + WUSEN + Wake-up Function Synchronous Enable + 0 + 0 + read-only + + + 0 + IIC asynchronous circuit enable + #0 + + + 1 + IIC synchronous circuit enable + #1 + + + + + + + + + R_IIC1 + 0x40053100 + + + R_IIC2 + 0x40053200 + + + R_IRDA + IrDA Interface + 0x40070F00 + + 0x00000000 + 0x01 + registers + + + + IRCR + IrDA Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + IRE + IrDA Enable + 7 + 7 + read-write + + + 0 + Serial I/O pins are used for normal serial communication. + #0 + + + 1 + Serial I/O pins are used for IrDA data communication. + #1 + + + + + IRTXINV + IRTXD Polarity Switching + 3 + 3 + read-write + + + 0 + Data to be transmitted is output to IRTXD as is. + #0 + + + 1 + Data to be transmitted is output to IRTXD after the polarity is inverted. + #1 + + + + + IRRXINV + IRRXD Polarity Switching + 2 + 2 + read-write + + + 0 + IRRXD input is used as received data as is. + #0 + + + 1 + IRRXD input is used as received data after the polarity is inverted. + #1 + + + + + + + + + R_IWDT + Independent Watchdog Timer + 0x40044400 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x02 + registers + + + + IWDTRR + IWDT Refresh Register + 0x00 + 8 + read-write + 0xFF + 0xFF + + + IWDTRR + The counter is refreshed by writing 0x00 and then writing 0xFF to this register. + 0 + 7 + read-write + + + + + IWDTSR + IWDT Status Register + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + REFEF + Refresh Error Flag + 15 + 15 + read-write + zeroToClear + modify + + + 0 + Refresh error not occurred + #0 + + + 1 + Refresh error occurred + #1 + + + + + UNDFF + Underflow Flag + 14 + 14 + read-write + zeroToClear + modify + + + 0 + Underflow not occurred + #0 + + + 1 + Underflow occurred + #1 + + + + + CNTVAL + Counter ValueValue counted by the counter + 0 + 13 + read-only + + + + + + + R_JPEG + JPEG Codec + 0x400E6000 + + 0x00000000 + 0x002 + registers + + + 0x00000003 + 0x00F + registers + + + 0x00000040 + 0x014 + registers + + + 0x00000058 + 0x01C + registers + + + 0x0000008C + 0x008 + registers + + + 0x00000100 + 0x11C + registers + + + 0x00000220 + 0x0B2 + registers + + + 0x00000300 + 0x01C + registers + + + 0x00000320 + 0x0B2 + registers + + + + JCMOD + JPEG Code Mode Register + 0x000 + 8 + read-write + 0x00 + 0xFF + + + DSP + Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes. + 3 + 3 + read-write + + + 0 + Compression process + #0 + + + 1 + Decompression process + #1 + + + + + REDU + Pixel FormatNOTE: Read-only in Decompression. + 0 + 2 + read-write + + + 001 + YCbCr422(Compression) / YCbCr422(Decompression) + #001 + + + 000 + Setting prohibited(Compression) / YCbCr444(Decompression) + #000 + + + 110 + Setting prohibited(Compression) / YCbCr411/[Decompression] + #110 + + + 010 + Setting prohibited(Compression) / YCbCr420/[Decompression] + #010 + + + others + Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression]) + true + + + + + + + JCCMD + JPEG Code Command Register + 0x001 + 8 + write-only + 0x00 + 0x00 + + + BRST + Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued. + 7 + 7 + write-only + + + 0 + No effect. + #0 + + + 1 + Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers. + #1 + + + + + JEND + Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1 + 2 + 2 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear all bits in JINTE0. + #1 + + + + + JRST + JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. + 1 + 1 + write-only + + + 0 + No effect. + #0 + + + 1 + Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0). + #1 + + + + + JSRT + JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. + 0 + 0 + write-only + + + 0 + No effect. + #0 + + + 1 + Start JPEG core processing + #1 + + + + + + + JCQTN + JPEG Code Quantization Table Number Register + 0x003 + 8 + read-write + 0x00 + 0xFF + + + QT3 + Quantization table number for the third color component NOTE: Read-only in Decompression. + 4 + 5 + read-write + + + 00 + Use quantization table No.0 (JCQTBL0) as the third color component. + #00 + + + 01 + Use quantization table No.1 (JCQTBL1) as the third color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the third color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the third color component. + #11 + + + + + QT2 + Quantization table number for the second color component NOTE: Read-only in Decompression. + 2 + 3 + read-write + + + 00 + Use quantization table No.0 (JCQTBL0) as the second color component. + #00 + + + 01 + Use quantization table No.1 (JCQTBL1) as the second color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the second color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the second color component. + #11 + + + + + QT1 + Quantization table number for the first color componentNOTE: Read-only in Decompression. + 0 + 1 + read-write + + + 00 + Use quantization table No.0 (JCQTBL0) as the first color component. + #00 + + + 01 + Use quantization table No.1 (JCQTBL1) as the first color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the first color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the first color component. + #11 + + + + + + + JCHTN + JPEG Code Huffman Table Number Register + 0x004 + 8 + read-write + 0x00 + 0xFF + + + HTA3 + Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression. + 5 + 5 + read-write + + + 0 + AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1) + #0 + + + 1 + AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0) + #1 + + + + + HTD3 + Huffman table number (DC) for the third color component NOTE: Read-only in Decompression. + 4 + 4 + read-write + + + 0 + DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1) + #0 + + + 1 + DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0) + #1 + + + + + HTA2 + Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression. + 3 + 3 + read-write + + + 0 + AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1) + #0 + + + 1 + AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0) + #1 + + + + + HTD2 + Huffman table number (DC) for the second color component NOTE: Read-only in Decompression. + 2 + 2 + read-write + + + 0 + DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1) + #0 + + + 1 + DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0) + #1 + + + + + HTA1 + Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression. + 1 + 1 + read-write + + + 0 + AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1) + #0 + + + 1 + AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0) + #1 + + + + + HTD1 + Huffman table number (DC) for the first color component NOTE: Read-only in Decompression. + 0 + 0 + read-write + + + 0 + DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1) + #0 + + + 1 + DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0) + #1 + + + + + + + JCDRIU + JPEG Code DRI Upper Register + 0x005 + 8 + read-write + 0x00 + 0xFF + + + DRIU + Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCDRID + JPEG Code DRI Lower Register + 0x006 + 8 + read-write + 0x00 + 0xFF + + + DRID + Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCVSZU + JPEG Code Vertical Size Upper Register + 0x007 + 8 + read-write + 0x00 + 0xFF + + + VSZU + Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCVSZD + JPEG Code Vertical Size Lower Register + 0x008 + 8 + read-write + 0x00 + 0xFF + + + VSZD + Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCHSZU + JPEG Code Horizontal Size Upper Register + 0x009 + 8 + read-write + 0x00 + 0xFF + + + HSZU + Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCHSZD + JPEG Coded Horizontal Size Lower Register + 0x00A + 8 + read-write + 0x00 + 0xFF + + + HSZD + Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCDTCU + JPEG Code Data Count Upper Register + 0x00B + 8 + read-only + 0x00 + 0xFF + + + DCU + Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCM + JPEG Code Data Count Middle Register + 0x00C + 8 + read-only + 0x00 + 0xFF + + + DCM + Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCD + JPEG Code Data Count Lower Register + 0x00D + 8 + read-only + 0x00 + 0xFF + + + DCD + Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JINTE0 + JPEG Interrupt Enable Register 0 + 0x00E + 8 + read-write + 0x00 + 0xFF + + + INT7 + This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned. + 7 + 7 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + INT6 + This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 6 + 6 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + INT5 + This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 5 + 5 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + INT3 + This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. + 3 + 3 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + JINTS0 + JPEG Interrupt Status Register 0 + 0x00F + 8 + read-write + 0x00 + 0xFF + + + INS6 + This bit is set to 1 when this module completes compression process normally. + 6 + 6 + read-write + zeroToClear + modify + + + INS5 + This bit is set to 1 when a compressed data error occurs. + 5 + 5 + read-write + zeroToClear + modify + + + INS3 + This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. + 3 + 3 + read-write + zeroToClear + modify + + + + + JCDERR + JPEG Code Decode Error Register + 0x010 + 8 + read-write + 0x0A + 0xFF + + + ERR + Error Code (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression. + 0 + 3 + read-write + + + 0000 + Normal(Decompression error codes)/Normal(Segment error codes) + #0000 + + + 0001 + SOI not detected(Decompression error codes) + #0001 + + + 0010 + SOF1 to SOFF detected(Decompression error codes) + #0010 + + + 0011 + Unprovided pixel format detected(Decompression error codes) + #0011 + + + 0100 + SOF accuracy error(Decompression error codes) + #0100 + + + 0101 + DQT accuracy error(Decompression error codes) + #0101 + + + 0110 + Component error 1(Decompression error codes) + #0110 + + + 0111 + Component error 2(Decompression error codes) + #0111 + + + 1000 + SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes) + #1000 + + + 1001 + SOS not detected(Decompression error codes) + #1001 + + + 1010 + EOI not detected (default)(Decompression error codes) + #1010 + + + 1011 + Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes) + #1011 + + + 1100 + Image size error detected(Decompression error codes)/Image size error(Segment error codes) + #1100 + + + 1101 + Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes) + #1101 + + + 1110 + Block data number error detected(Decompression error codes)/Block data number error(Segment error codes) + #1110 + + + others + Setting prohibited + true + + + + + + + JCRST + JPEG Code Reset Register + 0x011 + 8 + read-only + 0x00 + 0xFF + + + RST + Operating State + 0 + 0 + read-only + + + 0 + State other than below + #0 + + + 1 + Suspended state caused by interrupt sources of JINTE0 + #1 + + + + + + + JIFECNT + JPEG Interface Compression Control Register + 0x040 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + JOUTSWAP + Byte/Halfword/Word Swap Output coded data in compression is swapped. + 8 + 10 + read-write + + + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 + + + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] + #111 + + + + + DINRINI + Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + 6 + 6 + read-write + + + 0 + The transfer address is not initialized when the input of image data lines is restarted + #0 + + + 1 + The transfer address is initialized when the input of image data lines is restarted + #1 + + + + + DINRCMD + Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. + 5 + 5 + write-only + + + DINLC + Count Mode Setting for Stopping Input Image Data Lines + 4 + 4 + read-write + + + 0 + Count mode for stopping the input of image data lines is off + #0 + + + 1 + Count mode for stopping the input of image data lines is on + #1 + + + + + DINSWAP + Byte/Halfword Swap + 0 + 2 + read-write + + + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 + + + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 + + + + + + + JIFESA + JPEG Interface Compression Source Address Register + 0x044 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ESA + Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFESOFST + JPEG Interface Compression Line Offset Register + 0x048 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ESMW + Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0. + 0 + 14 + read-write + + + + + JIFEDA + JPEG Interface Compression Destination Address Register + 0x04C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EDA + Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFESLC + JPEG Interface Compression Source Line Count Register + 0x050 + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + + + LINES + Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. + 0 + 15 + read-write + + + + + JIFDCNT + JPEG Interface Decompression Control Register + 0x058 + 32 + read-write + 0x01000000 + 0xFFFFFFFF + + + VINTER + Vertical SubsamplingSubsamples vertical output image data. + 28 + 29 + read-write + + + 00 + No subsampling + #00 + + + 01 + Subsamples output data into 1/2. + #01 + + + 10 + Subsamples output data into 1/4. + #10 + + + 11 + Subsamples output data into 1/8. + #11 + + + + + HINTER + Horizontal Subsampling Subsamples horizontal output image data. + 26 + 27 + read-write + + + 00 + No subsampling + #00 + + + 01 + Subsamples output data into 1/2. + #01 + + + 10 + Subsamples output data into 1/4. + #10 + + + 11 + Subsamples output data into 1/8. + #11 + + + + + OPF + Specifies output image data pixel format. + 24 + 25 + read-write + + + 01 + ARGB8888 + #01 + + + 10 + RGB565 + #10 + + + others + Setting prohibited + true + + + + + JINRINI + Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. + 14 + 14 + read-write + + + 0 + The transfer address is not initialized when the input of coded data is restarted. + #0 + + + 1 + The transfer address is initialized when the input of coded data is restarted. + #1 + + + + + JINRCMD + Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. + 13 + 13 + write-only + + + JINC + Count Mode Setting for Stopping Input Coded Data + 12 + 12 + read-write + + + 0 + Count mode for stopping the input of coded data is off. + #0 + + + 1 + Count mode for stopping the input of coded data is on + #1 + + + + + JINSWAP + Byte/Word/Longword Swap Input coded data in decompression is swapped. + 8 + 10 + read-write + + + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 + + + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 + + + + + DOUTRINI + Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + 6 + 6 + read-write + + + 0 + The transfer address is not initialized when the output of lines of image data is restarted. + #0 + + + 1 + The transfer address is initialized when the output of lines of image data is restarted + #1 + + + + + DOUTRCMD + Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. + 5 + 5 + write-only + + + DOUTLC + Count Mode for Stopping Output Image Data Lines + 4 + 4 + read-write + + + 0 + Count mode for stopping the output of image data lines is off. + #0 + + + 1 + Count mode for stopping the output of image data lines is on + #1 + + + + + DOUTSWAP + Byte/Word Swap Output image data in decompression is swapped. + 0 + 2 + read-write + + + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 + + + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 + + + + + + + JIFDSA + JPEG Interface Decompression Source Address Register + 0x05C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DSA + Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFDDOFST + JPEG Interface Decompression Line Offset Register + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DDMW + Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + 0 + 14 + read-write + + + + + JIFDDA + JPEG Interface Decompression Destination Address Register + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DDA + Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 + read-write + + + + + JIFDSDC + JPEG Interface Decompression Source Data Count Register + 0x068 + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + + + JDATAS + Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. + 0 + 15 + read-write + + + + + JIFDDLC + JPEG Interface Decompression Destination Line Count Register + 0x06C + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + + + LINES + Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units. + 0 + 15 + read-write + + + + + JIFDADT + JPEG Interface Decompression alpha Set Register + 0x070 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALPHA + Setting of the alpha value for output in ARGB8888 format. + 0 + 7 + read-write + + + + + JINTE1 + JPEG Interrupt Enable Register 1 + 0x08C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. + 6 + 6 + read-write + + + 0 + Disables an interrupt request. + #0 + + + 1 + Enables an interrupt request. + #1 + + + + + DINLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. + 5 + 5 + read-write + + + 0 + Disables an interrupt request. + #0 + + + 1 + Enables an interrupt request. + #1 + + + + + DBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. + 2 + 2 + read-write + + + 0 + Disables an interrupt request. + #0 + + + 1 + Enables an interrupt request. + #1 + + + + + JINEN + Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. + 1 + 1 + read-write + + + 0 + Disables an interrupt request. + #0 + + + 1 + Enables an interrupt request. + #1 + + + + + DOUTLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1 + 0 + 0 + read-write + + + 0 + Disables an interrupt request. + #0 + + + 1 + Enables an interrupt request. + #1 + + + + + + + JINTS1 + JPEG Interrupt Status Register 1 + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CBTF + This bit is set to 1 when the last output coded data is written in compression. + 6 + 6 + read-write + modify + + + DINLF + This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. + 5 + 5 + read-write + modify + + + DBTF + This bit is set to 1 when the last output image data is written in decompression. + 2 + 2 + read-write + modify + + + JINF + This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. This bit is valid only when the JINC bit in JIFDCNT is set to 1. + 1 + 1 + read-write + modify + + + DOUTLF + In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. + 0 + 0 + read-write + modify + + + + + 64 + 0x1 + JCQTBL0[%s] + Quantization Table 0 + 0x0100 + 8 + write-only + 0x00 + 0x00 + + + JCQTBL1[%s] + Quantization Table 1 + 0x0140 + + + JCQTBL2[%s] + Quantization Table 2 + 0x0180 + + + JCQTBL3[%s] + Quantization Table 3 + 0x01C0 + + + 28 + 0x1 + JCHTBD0[%s] + DC Huffman Table 0 + 0x0200 + 8 + read-write + 0x00 + 0x00 + + + JCHTBD1[%s] + DC Huffman Table 1 + 0x0300 + + + 178 + 0x1 + JCHTBA0[%s] + AC Huffman Table 0 + 0x0220 + 8 + read-write + 0x00 + 0x00 + + + JCHTBA1[%s] + DC Huffman Table 1 + 0x0320 + + + + + R_KINT + Key Interrupt Function + 0x40080000 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + + KRCTL + KEY Return Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + KRMD + Usage of Key Interrupt Flags(KR0 to KR7) + 7 + 7 + read-write + + + 0 + Do not use key interrupt flags + #0 + + + 1 + Use key interrupt flags. + #1 + + + + + KREG + Detection Edge Selection (KRF0 to KRF7) + 0 + 0 + read-write + + + 0 + Falling edge + #0 + + + 1 + Rising edge + #1 + + + + + + + KRF + KEY Return Flag Register + 0x04 + 8 + read-write + 0x00 + 0xFF + zeroToClear + modify + + + KRF7 + Key interrupt flag 7 + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF6 + Key interrupt flag 6 + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF5 + Key interrupt flag 5 + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF4 + Key interrupt flag 4 + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF3 + Key interrupt flag 3 + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF2 + Key interrupt flag 2 + 2 + 2 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF1 + Key interrupt flag 1 + 1 + 1 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + KRF0 + Key interrupt flag 0 + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No interrupt detected + #0 + + + 1 + Interrupt detected. + #1 + + + + + + + KRM + KEY Return Mode Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + KRM7 + Key interrupt mode control 7 + 7 + 7 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM6 + Key interrupt mode control 6 + 6 + 6 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM5 + Key interrupt mode control 5 + 5 + 5 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM4 + Key interrupt mode control 4 + 4 + 4 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM3 + Key interrupt mode control 3 + 3 + 3 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM2 + Key interrupt mode control 2 + 2 + 2 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM1 + Key interrupt mode control 1 + 1 + 1 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + KRM0 + Key interrupt mode control 0 + 0 + 0 + read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + + + + + + + + R_MMF + Memory Mirror Function + 0x40001000 + + 0x00000000 + 0x008 + registers + + + + MMSFR + MemMirror Special Function Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + KEY + MMSFR Key Code + 24 + 31 + write-only + + + 0xDB + Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB. + 0xDB + + + others + Writing to the MEMMIRADDR bits are invalid. + true + + + + + MEMMIRADDR + Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0. + 7 + 22 + read-write + + + + + MMEN + MemMirror Enable Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + KEY + MMEN Key Code + 24 + 31 + write-only + + + 0xDB + Writing to the EN bit is valid, when the KEY bits are written 0xDB. + 0xDB + + + others + Writing to the EN bit is invalid. + true + + + + + EN + Memory Mirror Function Enable + 0 + 0 + read-write + + + 1 + Memory Mirror Function is enabled. + #1 + + + 0 + Memory Mirror Function is disabled. + #0 + + + + + + + + + R_MPU_MMPU + Bus Master MPU + 0x40000000 + + 0x00000000 + 0x02 + registers + + + 0x00000102 + 0x02 + registers + + + 0x00000200 + 0x02 + registers + + + 0x00000204 + 0x008 + registers + + + 0x00000210 + 0x02 + registers + + + 0x00000214 + 0x008 + registers + + + 0x00000220 + 0x02 + registers + + + 0x00000224 + 0x008 + registers + + + 0x00000230 + 0x02 + registers + + + 0x00000234 + 0x008 + registers + + + 0x00000240 + 0x02 + registers + + + 0x00000244 + 0x008 + registers + + + 0x00000250 + 0x02 + registers + + + 0x00000254 + 0x008 + registers + + + 0x00000260 + 0x02 + registers + + + 0x00000264 + 0x008 + registers + + + 0x00000270 + 0x02 + registers + + + 0x00000274 + 0x008 + registers + + + 0x00000280 + 0x02 + registers + + + 0x00000284 + 0x008 + registers + + + 0x00000290 + 0x02 + registers + + + 0x00000294 + 0x008 + registers + + + 0x000002A0 + 0x02 + registers + + + 0x000002A4 + 0x008 + registers + + + 0x000002B0 + 0x02 + registers + + + 0x000002B4 + 0x008 + registers + + + 0x000002C0 + 0x02 + registers + + + 0x000002C4 + 0x008 + registers + + + 0x000002D0 + 0x02 + registers + + + 0x000002D4 + 0x008 + registers + + + 0x000002E0 + 0x02 + registers + + + 0x000002E4 + 0x008 + registers + + + 0x000002F0 + 0x02 + registers + + + 0x000002F4 + 0x008 + registers + + + 0x00000300 + 0x02 + registers + + + 0x00000304 + 0x008 + registers + + + 0x00000310 + 0x02 + registers + + + 0x00000314 + 0x008 + registers + + + 0x00000320 + 0x02 + registers + + + 0x00000324 + 0x008 + registers + + + 0x00000330 + 0x02 + registers + + + 0x00000334 + 0x008 + registers + + + 0x00000340 + 0x02 + registers + + + 0x00000344 + 0x008 + registers + + + 0x00000350 + 0x02 + registers + + + 0x00000354 + 0x008 + registers + + + 0x00000360 + 0x02 + registers + + + 0x00000364 + 0x008 + registers + + + 0x00000370 + 0x02 + registers + + + 0x00000374 + 0x008 + registers + + + 0x00000380 + 0x02 + registers + + + 0x00000384 + 0x008 + registers + + + 0x00000390 + 0x02 + registers + + + 0x00000394 + 0x008 + registers + + + 0x000003A0 + 0x02 + registers + + + 0x000003A4 + 0x008 + registers + + + 0x000003B0 + 0x02 + registers + + + 0x000003B4 + 0x008 + registers + + + 0x000003C0 + 0x02 + registers + + + 0x000003C4 + 0x008 + registers + + + 0x000003D0 + 0x02 + registers + + + 0x000003D4 + 0x008 + registers + + + 0x000003E0 + 0x02 + registers + + + 0x000003E4 + 0x008 + registers + + + 0x000003F0 + 0x02 + registers + + + 0x000003F4 + 0x008 + registers + + + 0x00000400 + 0x02 + registers + + + 0x00000502 + 0x02 + registers + + + 0x00000600 + 0x02 + registers + + + 0x00000604 + 0x008 + registers + + + 0x00000610 + 0x02 + registers + + + 0x00000614 + 0x008 + registers + + + 0x00000620 + 0x02 + registers + + + 0x00000624 + 0x008 + registers + + + 0x00000630 + 0x02 + registers + + + 0x00000634 + 0x008 + registers + + + 0x00000640 + 0x02 + registers + + + 0x00000644 + 0x008 + registers + + + 0x00000650 + 0x02 + registers + + + 0x00000654 + 0x008 + registers + + + 0x00000660 + 0x02 + registers + + + 0x00000664 + 0x008 + registers + + + 0x00000670 + 0x02 + registers + + + 0x00000674 + 0x008 + registers + + + 0x00000680 + 0x02 + registers + + + 0x00000684 + 0x008 + registers + + + 0x00000690 + 0x02 + registers + + + 0x00000694 + 0x008 + registers + + + 0x000006A0 + 0x02 + registers + + + 0x000006A4 + 0x008 + registers + + + 0x000006B0 + 0x02 + registers + + + 0x000006B4 + 0x008 + registers + + + 0x000006C0 + 0x02 + registers + + + 0x000006C4 + 0x008 + registers + + + 0x000006D0 + 0x02 + registers + + + 0x000006D4 + 0x008 + registers + + + 0x000006E0 + 0x02 + registers + + + 0x000006E4 + 0x008 + registers + + + 0x000006F0 + 0x02 + registers + + + 0x000006F4 + 0x008 + registers + + + 0x00000700 + 0x02 + registers + + + 0x00000704 + 0x008 + registers + + + 0x00000710 + 0x02 + registers + + + 0x00000714 + 0x008 + registers + + + 0x00000720 + 0x02 + registers + + + 0x00000724 + 0x008 + registers + + + 0x00000730 + 0x02 + registers + + + 0x00000734 + 0x008 + registers + + + 0x00000740 + 0x02 + registers + + + 0x00000744 + 0x008 + registers + + + 0x00000750 + 0x02 + registers + + + 0x00000754 + 0x008 + registers + + + 0x00000760 + 0x02 + registers + + + 0x00000764 + 0x008 + registers + + + 0x00000770 + 0x02 + registers + + + 0x00000774 + 0x008 + registers + + + 0x00000780 + 0x02 + registers + + + 0x00000784 + 0x008 + registers + + + 0x00000790 + 0x02 + registers + + + 0x00000794 + 0x008 + registers + + + 0x000007A0 + 0x02 + registers + + + 0x000007A4 + 0x008 + registers + + + 0x000007B0 + 0x02 + registers + + + 0x000007B4 + 0x008 + registers + + + 0x000007C0 + 0x02 + registers + + + 0x000007C4 + 0x008 + registers + + + 0x000007D0 + 0x02 + registers + + + 0x000007D4 + 0x008 + registers + + + 0x000007E0 + 0x02 + registers + + + 0x000007E4 + 0x008 + registers + + + 0x000007F0 + 0x02 + registers + + + 0x000007F4 + 0x008 + registers + + + 0x00000800 + 0x02 + registers + + + 0x00000902 + 0x02 + registers + + + 0x00000A00 + 0x02 + registers + + + 0x00000A04 + 0x008 + registers + + + 0x00000A10 + 0x02 + registers + + + 0x00000A14 + 0x008 + registers + + + 0x00000A20 + 0x02 + registers + + + 0x00000A24 + 0x008 + registers + + + 0x00000A30 + 0x02 + registers + + + 0x00000A34 + 0x008 + registers + + + 0x00000A40 + 0x02 + registers + + + 0x00000A44 + 0x008 + registers + + + 0x00000A50 + 0x02 + registers + + + 0x00000A54 + 0x008 + registers + + + 0x00000A60 + 0x02 + registers + + + 0x00000A64 + 0x008 + registers + + + 0x00000A70 + 0x02 + registers + + + 0x00000A74 + 0x008 + registers + + + 0x00000A80 + 0x02 + registers + + + 0x00000A84 + 0x008 + registers + + + 0x00000A90 + 0x02 + registers + + + 0x00000A94 + 0x008 + registers + + + 0x00000AA0 + 0x02 + registers + + + 0x00000AA4 + 0x008 + registers + + + 0x00000AB0 + 0x02 + registers + + + 0x00000AB4 + 0x008 + registers + + + 0x00000AC0 + 0x02 + registers + + + 0x00000AC4 + 0x008 + registers + + + 0x00000AD0 + 0x02 + registers + + + 0x00000AD4 + 0x008 + registers + + + 0x00000AE0 + 0x02 + registers + + + 0x00000AE4 + 0x008 + registers + + + 0x00000AF0 + 0x02 + registers + + + 0x00000AF4 + 0x008 + registers + + + 0x00000B00 + 0x02 + registers + + + 0x00000B04 + 0x008 + registers + + + 0x00000B10 + 0x02 + registers + + + 0x00000B14 + 0x008 + registers + + + 0x00000B20 + 0x02 + registers + + + 0x00000B24 + 0x008 + registers + + + 0x00000B30 + 0x02 + registers + + + 0x00000B34 + 0x008 + registers + + + 0x00000B40 + 0x02 + registers + + + 0x00000B44 + 0x008 + registers + + + 0x00000B50 + 0x02 + registers + + + 0x00000B54 + 0x008 + registers + + + 0x00000B60 + 0x02 + registers + + + 0x00000B64 + 0x008 + registers + + + 0x00000B70 + 0x02 + registers + + + 0x00000B74 + 0x008 + registers + + + 0x00000B80 + 0x02 + registers + + + 0x00000B84 + 0x008 + registers + + + 0x00000B90 + 0x02 + registers + + + 0x00000B94 + 0x008 + registers + + + 0x00000BA0 + 0x02 + registers + + + 0x00000BA4 + 0x008 + registers + + + 0x00000BB0 + 0x02 + registers + + + 0x00000BB4 + 0x008 + registers + + + 0x00000BC0 + 0x02 + registers + + + 0x00000BC4 + 0x008 + registers + + + 0x00000BD0 + 0x02 + registers + + + 0x00000BD4 + 0x008 + registers + + + 0x00000BE0 + 0x02 + registers + + + 0x00000BE4 + 0x008 + registers + + + 0x00000BF0 + 0x02 + registers + + + 0x00000BF4 + 0x008 + registers + + + + 3 + 0x400 + + + A + A + 0 + + + B + B + 1 + + + C + C + 2 + + + MMPU[%s] + Bus Master MPU Registers + 0x0000 + + CTL + Bus Master MPU Control Register + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the OAD and ENABLE bit is invalid. + true + + + + + OAD + Operation after detection + 1 + 1 + read-write + + + 0 + Non-maskable interrupt. + #0 + + + 1 + Internal reset. + #1 + + + + + ENABLE + Master Group enable + 0 + 0 + read-write + + + 0 + Master Group is disabled. Permission of all regions. + #0 + + + 1 + Master Group is enabled. Protection of all regions. + #1 + + + + + + + PT + Protection of Register + 0x102 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT bit is invalid. + true + + + + + PROTECT + Protection of region register + 0 + 0 + read-write + + + 0 + All Bus Master MPU register writing is possible. + #0 + + + 1 + All Bus Master MPU register writing is protected. Read is possible. + #1 + + + + + + + 32 + 0x10 + REGION[%s] + Address Region registers + 0x0200 + + C + Access Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + WP + Write protection + 2 + 2 + read-write + + + 0 + Write permission + #0 + + + 1 + Write protection + #1 + + + + + RP + Read protection + 1 + 1 + read-write + + + 0 + Read permission + #0 + + + 1 + Read protection + #1 + + + + + ENABLE + Region enable + 0 + 0 + read-write + + + 0 + Group m Region n unit is disabled + #0 + + + 1 + Group m Region n unit is enabled + #1 + + + + + + + S + Start Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MMPUSmn + Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. + 0 + 31 + read-write + + + + + E + End Address Register + 0x08 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + + + MMPUEmn + Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. + 0 + 31 + read-write + + + + + + + + + R_MPU_SMPU + Bus Slave MPU + 0x40000C00 + + 0x00000000 + 0x02 + registers + + + 0x00000010 + 0x02 + registers + + + 0x00000014 + 0x02 + registers + + + 0x00000018 + 0x02 + registers + + + 0x0000001C + 0x02 + registers + + + 0x00000020 + 0x02 + registers + + + 0x00000024 + 0x02 + registers + + + 0x00000028 + 0x02 + registers + + + 0x0000002C + 0x02 + registers + + + 0x00000030 + 0x02 + registers + + + 0x00000034 + 0x02 + registers + + + + 10 + 0x4 + + + MBIU + MBIU + 0 + + + FBIU + FBIU + 1 + + + R_SRAM + R_SRAM + 2 + + + SRAM1 + SRAM1 + 3 + + + P0BIU + P0BIU + 4 + + + P2BIU + P2BIU + 5 + + + P6BIU + P6BIU + 6 + + + B7BIU + B7BIU + 7 + + + EXBIU + EXBIU + 8 + + + EXBIU2 + EXBIU2 + 9 + + + SMPU[%s] + Access Control Structure for MBIU + 0x10 + + R + Access Control Register for MBIU + 0x00 + 16 + read-write + 0x2000 + 0xFFFF + + + WPSRAMHS + SRAMHS Write Protection + 15 + 15 + read-write + + + 0 + Memory protection for SRAMHS writes from master group A, B, and C disabled + #0 + + + 1 + Memory protection for SRAMHS writes from master group A, B, and C enabled. + #1 + + + + + RPSRAMHS + SRAMHS Read Protection + 14 + 14 + read-write + + + 0 + Memory protection for SRAMHS reads from master group A, B, and C disabled + #0 + + + 1 + Memory protection for SRAMHS reads from master group A, B, and C enabled. + #1 + + + + + WPFLI + Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.) + 13 + 13 + read-write + + + 0 + Setting prohibited + #0 + + + 1 + Memory protection for code flash memory writes from master group A, B, and C enabled. + #1 + + + + + RPFLI + Code Flash Memory Read Protection + 12 + 12 + read-write + + + 0 + Memory protection for code flash memory reads from master group A, B, and C disabled + #0 + + + 1 + Memory protection for code flash memory reads from master group A, B, and C enabled. + #1 + + + + + WPGRPC + Master Group C Write protection + 7 + 7 + read-write + + + 0 + Memory protection for master group C writes disabled + #0 + + + 1 + Memory protection for master group C writes enabled. + #1 + + + + + RPGRPC + Master Group C Read protection + 6 + 6 + read-write + + + 0 + Memory protection for master group C reads disabled + #0 + + + 1 + Memory protection for master group C reads enabled. + #1 + + + + + WPGRPB + Master Group B Write protection + 5 + 5 + read-write + + + 0 + Memory protection for master group B writes disabled + #0 + + + 1 + Memory protection for master group B writes enabled. + #1 + + + + + RPGRPB + Master Group B Read protection + 4 + 4 + read-write + + + 0 + Memory protection for master group B reads disabled + #0 + + + 1 + Memory protection for master group B reads enabled. + #1 + + + + + WPGRPA + Master Group A Write protection + 3 + 3 + read-write + + + 0 + Memory protection for master group A writes disabled + #0 + + + 1 + Memory protection for master group A writes enabled. + #1 + + + + + RPGRPA + Master Group A Read protection + 2 + 2 + read-write + + + 0 + Memory protection for master group A reads disabled + #0 + + + 1 + Memory protection for master group A reads enabled. + #1 + + + + + + + + SMPUCTL + Slave MPU Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT and OAD bit is invalid. + true + + + + + PROTECT + Protection of register + 1 + 1 + read-write + + + 0 + All Bus Slave register writing is possible. + #0 + + + 1 + All Bus Slave register writing is protected. Read is possible. + #1 + + + + + OAD + Master Group enable + 0 + 0 + read-write + + + 0 + Non-maskable interrupt. + #0 + + + 1 + Internal reset. + #1 + + + + + + + + + R_MPU_SPMON + CPU Stack Pointer Monitor + 0x40000D00 + + 0x00000000 + 0x02 + registers + + + 0x00000004 + 0x00E + registers + + + 0x00000014 + 0x00C + registers + + + + 2 + 0x10 + + + M + M + 0 + + + P + P + 1 + + + SP[%s] + Stack Pointer Monitor + 0x0000 + + OAD + Stack Pointer Monitor Operation After Detection Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the OAD bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the OAD bit is invalid. + true + + + + + OAD + Operation after detection + 0 + 0 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Reset. + #1 + + + + + + + CTL + Stack Pointer Monitor Access Control Register + 0x04 + 16 + read-write + 0x0000 + 0xFEFF + + + ERROR + Stack Pointer Monitor Error Flag + 8 + 8 + read-write + + + 0 + Stack pointer has not overflowed or underflowed + #0 + + + 1 + Stack pointer has overflowed or underflowed + #1 + + + + + ENABLE + Stack Pointer Monitor Enable + 0 + 0 + read-write + + + 0 + Stack pointer monitor is disabled + #0 + + + 1 + Stack pointer monitor is enabled. + #1 + + + + + + + PT + Stack Pointer Monitor Protection Register + 0x06 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT bit is invalid. + true + + + + + PROTECT + Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) + 0 + 0 + read-write + + + 0 + Stack Pointer Monitor register writing is possible. + #0 + + + 1 + Stack Pointer Monitor register writing is protected. + #1 + + + + + + + SA + Stack Pointer Monitor Start Address Register + 0x08 + 32 + read-write + 0x00000000 + 0x00000003 + + + MSPMPUSA + Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. + 0 + 31 + read-write + + + 0x1FF00000 + 0x200FFFFC + + + + + + + EA + Stack Pointer Monitor End Address Register + 0x0C + 32 + read-write + 0x00000003 + 0x00000003 + + + MSPMPUEA + Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. + 0 + 31 + read-write + + + 0x1FF00003 + 0x200FFFFF + + + + + + + + + + R_MSTP + System-Module Stop + 0x40047000 + + 0x00000000 + 0x00C + registers + + + + MSTPCRB + Module Stop Control Register B + 0x00 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPB31 + Serial Communication Interface 0 Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB30 + Serial Communication Interface 1 Module Stop + 30 + 30 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB29 + Serial Communication Interface 2 Module Stop + 29 + 29 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB28 + Serial Communication Interface 3 Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB27 + Serial Communication Interface 4 Module Stop + 27 + 27 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB26 + Serial Communication Interface 5 Module Stop + 26 + 26 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB25 + Serial Communication Interface 6 Module Stop + 25 + 25 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB24 + Serial Communication Interface 7 Module Stop + 24 + 24 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB23 + Serial Communication Interface 8 Module Stop + 23 + 23 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB22 + Serial Communication Interface 9 Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 20 + 21 + read-write + + + MSTPB19 + Serial Peripheral Interface 0 Module Stop + 19 + 19 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB18 + Serial Peripheral Interface Module Stop + 18 + 18 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 16 + 17 + read-write + + + MSTPB15 + ETHERC0 and EDMAC0 Module Stop + 15 + 15 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB14 + ETHERC1 and EDMAC1 Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB13 + EPTPC and PTPEDMAC Module Stop + 13 + 13 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB12 + Universal Serial Bus 2.0 HS Interface Module Stop + 12 + 12 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB11 + Universal Serial Bus 2.0 FS Interface Module Stop + 11 + 11 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + This bit is read as 1. The write value should be 1. + 10 + 10 + read-write + + + MSTPB9 + I2C Bus Interface 0 Module Stop + 9 + 9 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB8 + I2C Bus Interface 1 Module Stop + 8 + 8 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB7 + I2C Bus Interface 2 Module Stop + 7 + 7 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB6 + Queued Serial Peripheral Interface Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB5 + IrDA Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 3 + 4 + read-write + + + MSTPB2 + RCAN0 Module Stop + 2 + 2 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB1 + RCAN1 Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + This bit is read as 1. The write value should be 1. + 0 + 0 + read-write + + + + + MSTPCRC + Module Stop Control Register C + 0x04 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPC31 + AES Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC28 + Random Number Generator Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state. + #1 + + + + + MSTPC14 + Event Link Controller Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC13 + Data Operation Circuit Module Stop + 13 + 13 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC4 + Segment LCD Controller Module Stop + 4 + 4 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC3 + Capacitive Touch Sensing Unit Module Stop + 3 + 3 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC1 + CRC Calculator Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC0 + CAC Module Stop + 0 + 0 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + MSTPCRD + Module Stop Control Register D + 0x08 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPD31 + Operational Amplifier Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD29 + Comparator-LP Module Stop + 29 + 29 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD28 + ACMPHS0 Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD20 + 12-bit D/A Converter Module Stop + 20 + 20 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD19 + 8-Bit D/A Converter Module Stop + 19 + 19 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD17 + 24-bit Sigma-Delta A/DConverter Module Stop + 17 + 17 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD16 + 16-Bit A/D Converter Module Stop + 16 + 16 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD14 + POEG Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD6 + GPT ch6 - ch1 Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD5 + GPT ch0 Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD3 + AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0. + 3 + 3 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD2 + AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1. + 2 + 2 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + + + R_OPAMP + Operational Amplifier + 0x40086000 + + 0x00000008 + 0x005 + registers + + + 0x0000000E + 0x00C + registers + + + 0x0000001F + 0x007 + registers + + + + 4 + 0x3 + AMP[%s] + Input and Output Selectors for Operational Amplifier %s + 0x0E + read-write + + OS + Output Select Register + 0 + 8 + read-write + 0x00 + 0xFF + + + + PS + Plus Input Select Register + 2 + 8 + read-write + 0x00 + 0xFF + + + + MS + Minus Input Select Register + 1 + 8 + read-write + 0x00 + 0xFF + + + + + 3 + 2 + AMPOT[%s] + Operational Amplifier n Offset Trimming Registers + 0x20 + read-write + + P + Operational Amplifier n Offset Trimming Pch Register + 0 + 8 + read-write + 0 + 0xD0 + + + TRMP + AMPn input offset trimming Pch side + 0 + 4 + read-write + + + + + N + Operational Amplifier n Offset Trimming Nch Register + 1 + 8 + + + TRMN + AMPn input offset trimming Nch side + 0 + 4 + + + + + + AMPMC + Operational amplifier mode control register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + AMPSP + Operation mode selection + 7 + 7 + read-write + + + 0 + Low-power mode (low-speed). + #0 + + + 1 + High-speed mode. + #1 + + + + + 3 + 1 + AMPPC%s + Operational amplifier precharge control status + 0 + 0 + read-write + + + 0 + Precharging is stopped. + #0 + + + 1 + Precharging is enabled. + #1 + + + + + + + AMPTRM + Operational amplifier trigger mode control register + 0x09 + 8 + read-write + 0x00 + 0xFF + + + 4 + 2 + AMPTRM%s + Operational amplifier function activation/stop trigger control + 0 + 1 + read-write + + + 00 + Software trigger mode. + #00 + + + 01 + An activation and A/D trigger mode. + #01 + + + 10 + Setting prohibited. + #10 + + + 11 + An activation and A/D trigger mode. + #11 + + + + + + + AMPTRS + Operational Amplifier Activation Trigger Select Register + 0x0A + 8 + read-write + 0x00 + 0xFF + + + AMPTRS + ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. + 0 + 1 + read-write + + + 00 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3 + #00 + + + 01 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1 + #01 + + + 10 + Setting prohibited + #10 + + + 11 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0 + #11 + + + + + + + AMPC + Operational amplifier control register + 0x0B + 8 + read-write + 0x00 + 0xFF + + + IREFE + Operation control of operational amplifier reference current circuit + 7 + 7 + read-write + + + 0 + Operational amplifier reference current circuit is stopped. + #0 + + + 1 + Operation of operational amplifier reference current circuit is enabled. + #1 + + + + + 4 + 1 + AMPE%s + Operation control of operational amplifier + 0 + 0 + read-write + + + 0 + Operation amplifier is stopped. + #0 + + + 1 + Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. + #1 + + + + + + + AMPMON + Operational amplifier monitor register + 0x0C + 8 + read-only + 0x00 + 0xFF + + + 4 + 1 + AMPMON%s + Operational amplifier status + 0 + 0 + read-only + + + 0 + Operational amplifier is stopped. + #0 + + + 1 + Operational amplifier is operating. + #1 + + + + + + + AMPCPC + Operational amplifier switch charge pump control register + 0x1A + 8 + read-write + 0x00 + 0xFF + + + 3 + 1 + PUMP%sEN + charge pump for AMP%s enable/disable + 0 + 0 + read-write + + + 0 + charge pump for AMP is disabled. + #0 + + + 1 + charge pump for AMP is enabled. + #1 + + + + + + + AMPUOTE + Operational Amplifier User Offset Trimming Enable Register + 0x1F + 8 + read-write + 0x00 + 0xFF + + + 3 + 1 + AMP%sTE + AMP%sOT write enable + 0 + 0 + read-write + + + 0 + Not possible to write the AMPnOTP and AMPnOTN registers + #0 + + + 1 + Possible to write the AMPnOTP and AMPnOTN registers + #1 + + + + + + + + + R_PDC + Parallel Data Capture Unit + 0x40094000 + + 0x00000000 + 0x01C + registers + + + + PCCR0 + PDC Control Register 0 + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EDS + Endian Select + 14 + 14 + read-write + + + 0 + Little endian + #0 + + + 1 + Big endian + #1 + + + + + PCKDIV + PCKO Frequency Division Ratio Select + 11 + 13 + read-write + + + 000 + PCKO/2 + #000 + + + 001 + PCKO/4 + #001 + + + 010 + PCKO/6 + #010 + + + 011 + PCKO/8 + #011 + + + 100 + PCKO/10 + #100 + + + 101 + PCKO/12 + #101 + + + 110 + PCKO/14 + #110 + + + 111 + PCKO/16 + #111 + + + + + PCKOE + PCKO Output Enable + 10 + 10 + read-write + + + 0 + PCKO output is disabled (fixed to the high level) + #0 + + + 1 + PCKO output is enabled. + #1 + + + + + HERIE + Horizontal Byte Number Setting Error Interrupt Enable + 9 + 9 + read-write + + + 0 + Generation of horizontal byte number setting error interrupt requests is disabled. + #0 + + + 1 + Generation of horizontal byte number setting error interrupt requests is enabled. + #1 + + + + + VERIE + Vertical Line Number Setting Error Interrupt Enable + 8 + 8 + read-write + + + 0 + Generation of vertical line number setting error interrupt requests is disabled. + #0 + + + 1 + Generation of vertical line number setting error interrupt requests is enabled. + #1 + + + + + UDRIE + Underrun Interrupt Enable + 7 + 7 + read-write + + + 0 + Generation of underrun interrupt requests is disabled. + #0 + + + 1 + Generation of underrun interrupt requests is enabled. + #1 + + + + + OVIE + Overrun Interrupt Enable + 6 + 6 + read-write + + + 0 + Generation of overrun interrupt requests is disabled. + #0 + + + 1 + Generation of overrun interrupt requests is enabled. + #1 + + + + + FEIE + Frame End Interrupt Enable + 5 + 5 + read-write + + + 0 + Generation of frame end interrupt requests is disabled. + #0 + + + 1 + Generation of frame end interrupt requests is enabled. + #1 + + + + + DFIE + Receive Data Ready Interrupt Enable + 4 + 4 + read-write + + + 0 + Generation of receive data ready interrupt requests is disabled. + #0 + + + 1 + Generation of receive data ready interrupt requests is enabled. + #1 + + + + + PRST + PDC Reset + 3 + 3 + write-only + + + 0 + PDC reset is not applied. + #0 + + + 1 + PDC is reset. + #1 + + + + + HPS + HSYNC Signal Polarity Select + 2 + 2 + read-write + + + 0 + HSYNC signal is active high. + #0 + + + 1 + HSYNC signal is active low. + #1 + + + + + VPS + VSYNC Signal Polarity Select + 1 + 1 + read-write + + + 0 + VSYNC signal is active high. + #0 + + + 1 + VSYNC signal is active low. + #1 + + + + + PCKE + Channel 0 GTCNT Count Clear + 0 + 0 + read-write + + + 0 + Operations for reception are stopped. + #0 + + + 1 + Operations for reception are ongoing. + #1 + + + + + + + PCCR1 + PDC Control Register 1 + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PCE + PDC Operation Enable + 0 + 0 + read-write + + + 0 + Operations for reception are disabled. + #0 + + + 1 + Operations for reception are enabled. + #1 + + + + + + + PCSR + PDC Status Register + 0x008 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + HERF + Horizontal Byte Number Setting Error Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + Horizontal byte number setting error has not been generated. + #0 + + + 1 + Horizontal byte number setting error has been generated. + #1 + + + + + VERF + Vertical Line Number Setting Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Vertical line number setting error has not been generated. + #0 + + + 1 + Vertical line number setting error has been generated. + #1 + + + + + UDRF + Underrun Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Underrun has not been generated. + #0 + + + 1 + Underrun has been generated. + #1 + + + + + OVRF + Overrun Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + FIFO overrun has not been generated. + #0 + + + 1 + FIFO overrun has been generated. + #1 + + + + + FEF + Frame End Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Frame end has not been generated. + #0 + + + 1 + Frame end has been generated. + #1 + + + + + FEMPF + FIFO Empty Flag + 1 + 1 + read-only + + + 0 + FIFO is not empty. + #0 + + + 1 + FIFO is empty. + #1 + + + + + FBSY + Frame Busy Flag + 0 + 0 + read-only + + + 0 + Operations for reception are stopped. + #0 + + + 1 + Operations for reception are ongoing. + #1 + + + + + + + PCMONR + PDC Pin Monitor Register + 0x00C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + HSYNC + HSYNC Signal Status Flag + 1 + 1 + read-only + + + 0 + HSYNC signal is at the low level. + #0 + + + 1 + HSYNC signal is at the high level. + #1 + + + + + VSYNC + VSYNC Signal Status Flag + 0 + 0 + read-only + + + 0 + VSYNC signal is at the low level. + #0 + + + 1 + VSYNC signal is at the high level. + #1 + + + + + + + PCDR + PDC Receive Data Register + 0x010 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PCDR + The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time. + 0 + 31 + read-only + + + + + VCR + Vertical Capture Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VSZ + Vertical Capture Size Number of lines to be captured. + 16 + 27 + read-write + + + VST + Vertical Capture Start Line PositionNumber of the line where capture is to start. + 0 + 11 + read-write + + + + + HCR + Horizontal Capture Register + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSZ + Horizontal Capture Size Number of bytes to capture horizontally. + 16 + 27 + read-write + + + HST + Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start. + 0 + 11 + read-write + + + + + + + R_PORT0 + I/O Ports + 0x40040000 + + 0x00000000 + 0x010 + registers + + + + PCNTR1 + Port Control Register 1 + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PODR + Pmn Output Data + 16 + 31 + read-write + + + 0 + Low output + #0 + + + 1 + High output. + #1 + + + + + PDR + Pmn Direction + 0 + 15 + read-write + + + 0 + Input (functions as an input pin) + #0 + + + 1 + Output (functions as an output pin). + #1 + + + + + + + PODR + Output data register + PCNTR1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + PODR%s + Pmn Output Data + 0 + 0 + read-write + + + 0 + Low output + #0 + + + 1 + High output. + #1 + + + + + + + PDR + Data direction register + PCNTR1 + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + PDR%s + Pmn Direction + 0 + 0 + read-write + + + 0 + Input (functions as an input pin) + #0 + + + 1 + Output (functions as an output pin). + #1 + + + + + + + PCNTR2 + Port Control Register 2 + 0x04 + 32 + read-only + 0x00000000 + 0xFFFF0000 + + + EIDR + Pmn Event Input Data + 16 + 31 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + PIDR + Pmn Input Data + 0 + 15 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + EIDR + Event input data register + PCNTR2 + 0x04 + 16 + read-only + 0x0000 + 0xFFFF + + + 16 + 1 + EIDR%s + Pmn Event Input Data + 0 + 0 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + PIDR + Input data register + PCNTR2 + 0x06 + 16 + read-only + 0x0000 + 0x0000 + + + 16 + 1 + PIDR%s + Pmn Input Data + 0 + 0 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + PCNTR3 + Port Control Register 3 + 0x08 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + PORR + Pmn Output Reset + 16 + 31 + write-only + + + 0 + No affect to output + #0 + + + 1 + Low output. + #1 + + + + + POSR + Pmn Output Set + 0 + 15 + write-only + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + PORR + Output set register + PCNTR3 + 0x08 + 16 + write-only + 0x0000 + 0xFFFF + + + 16 + 1 + PORR%s + Pmn Output Reset + 0 + 0 + write-only + + + 0 + No affect to output + #0 + + + 1 + Low output. + #1 + + + + + + + POSR + Output reset register + PCNTR3 + 0x0A + 16 + write-only + 0x0000 + 0xFFFF + + + 16 + 1 + POSR%s + Pmn Output Set + 0 + 0 + write-only + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + PCNTR4 + Port Control Register 4 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EORR + Pmn Event Output Reset + 16 + 31 + read-write + + + 0 + No affect to output + #0 + + + 1 + Low output + #1 + + + + + EOSR + Pmn Event Output Set + 0 + 15 + read-write + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + EORR + Event output set register + PCNTR4 + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + EORR%s + Pmn Event Output Reset + 0 + 0 + read-write + + + 0 + No affect to output + #0 + + + 1 + Low output + #1 + + + + + + + EOSR + Event output reset register + PCNTR4 + 0x0E + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + EOSR%s + Pmn Event Output Set + 0 + 0 + read-write + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + + + R_PORT1 + 0x40040020 + + + R_PORT2 + 0x40040040 + + + R_PORT3 + 0x40040060 + + + R_PORT4 + 0x40040080 + + + R_PORT5 + 0x400400A0 + + + R_PORT6 + 0x400400C0 + + + R_PORT7 + 0x400400E0 + + + R_PORT8 + 0x40040100 + + + R_PORT9 + 0x40040120 + + + R_PORT10 + 0x40040140 + + + R_PORT11 + 0x40040160 + + + R_PFS + I/O Ports-PFS + 0x40040800 + + 0x00000000 + 0x040 + registers + + + + 12 + 0x40 + PORT[%s] + Port %s + + 16 + 4 + PIN[%s] + Pin Function Selects + 0 + + PmnPFS_BY + Pin Function Control Register + 0x003 + 8 + read-write + 0x00 + 0xFD + + + NCODR + N-Channel Open Drain Control + 6 + 6 + read-write + + + 0 + CMOS output + #0 + + + 1 + NMOS open-drain output + #1 + + + + + PIM + Port Input Mode Control + 5 + 5 + read-write + + + 0 + CMOS input + #0 + + + 1 + TTL input + #1 + + + + + PCR + Pull-up Control + 4 + 4 + read-write + + + 0 + Disables an input pull-up. + #0 + + + 1 + Enables an input pull-up. + #1 + + + + + PDR + Port Direction + 2 + 2 + read-write + + + 0 + Input (Functions as an input pin.) + #0 + + + 1 + Output (Functions as an output pin.) + #1 + + + + + PIDR + Port Input Data + 1 + 1 + read-only + + + 0 + Low input + #0 + + + 1 + High input + #1 + + + + + PODR + Port Output Data + 0 + 0 + read-write + + + 0 + Low output + #0 + + + 1 + High output + #1 + + + + + + + PmnPFS_HA + Pin Function Control Register + 0x002 + 16 + read-write + 0x0000 + 0xFFFD + + + ASEL + Analog Input enable + 15 + 15 + read-write + + + 0 + Used other than as analog pin + #0 + + + 1 + Used as analog pin + #1 + + + + + ISEL + IRQ input enable + 14 + 14 + read-write + + + 0 + Not used as IRQn input pin + #0 + + + 1 + Used as IRQn input pin + #1 + + + + + EOFR + Event on Falling/Rising + 12 + 13 + read-write + + + 00 + Do not care + #00 + + + 01 + Detect rising edge + #01 + + + 10 + Detect falling edge + #10 + + + 11 + Detect rising and falling edge + #11 + + + + + DSCR + Drive Strength Control Register + 10 + 11 + read-write + + + 00 + Normal drive output + #00 + + + 01 + Middle drive output + #01 + + + 10 + Middle drive with IIC + #10 + + + 11 + High-drive output + #11 + + + + + + + PmnPFS + Pin Function Control Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFD + + + PSEL + Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table + 24 + 28 + read-write + + + PMR + Port Mode Control + 16 + 16 + read-write + + + 0 + Uses the pin as a general I/O pin. + #0 + + + 1 + Uses the pin as an I/O port for peripheral functions. + #1 + + + + + + + + + + + R_PMISC + I/O Ports-MISC + 0x40040D00 + + 0x00000003 + 0x01 + registers + + + + PFENET + Ethernet Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + Reserved + These bits are read as 00. The write value should be 00. + 6 + 7 + read-write + + + PHYMODE1 + Ethernet Mode Setting ch1 + 5 + 5 + read-write + + + 0 + RMII mode (ETHERC channel 1) + #0 + + + 1 + MII mode (ETHERC channel 1) + #1 + + + + + PHYMODE0 + Ethernet Mode Setting ch0 + 4 + 4 + read-write + + + 0 + RMII mode (ETHERC channel 0) + #0 + + + 1 + MII mode (ETHERC channel 0) + #1 + + + + + Reserved + These bits are read as 0000. The write value should be 0000. + 0 + 3 + read-write + + + + + PWPR + Write-Protect Register + 3 + 8 + read-write + + + PFSWE + PmnPFS Register Write + 6 + 6 + read-write + + + 0 + Writing to the PmnPFS register is disabled + #0 + + + 1 + Writing to the PmnPFS register is enabled. + #1 + + + + + B0WI + PFSWE Bit Write Disable + 7 + 7 + + + 0 + Writing to the PFSWE bit is enabled + #0 + + + 1 + Writing to the PFSWE bit is disabled. + true + + + + + + + + + R_QSPI + Quad Serial Peripheral Interface + 0x64000000 + + 0x00000000 + 0x01C + registers + + + 0x00000020 + 0x00C + registers + + + 0x00000030 + 0x008 + registers + + + 0x00000804 + 0x04 + registers + + + + SFMSMD + Transfer Mode Control Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMCCE + Read instruction code selection. + 15 + 15 + read-write + + + 0 + Default instruction code set for each instruction + #0 + + + 1 + Instruction code written in the SFMSIC register + #1 + + + + + SFMOSW + Setup time adjustment for serial transmission + 11 + 11 + read-write + + + 0 + Does not extend the low-level width of SCK at transmission time + #0 + + + 1 + Extends the low-level width of SCK by 1*PCLKA at transmission time + #1 + + + + + SFMOHW + Hold time adjustment for serial transmission + 10 + 10 + read-write + + + 0 + Does not extend the high-level width of SCK at transmission time + #0 + + + 1 + Extends the high-level width of SCK by 1*PCLKA at transmission time + #1 + + + + + SFMOEX + Extension of the I/O buffer output enable signal for the serial interface + 9 + 9 + read-write + + + 0 + Does not extend the output enable signal + #0 + + + 1 + Extends the output enable signal by 1*QSPCLK + #1 + + + + + SFMMD3 + SPI mode selection. An initial value is determined by input to CFGMD3. + 8 + 8 + read-write + + + 0 + SPI mode 0 + #0 + + + 1 + SPI mode 3 + #1 + + + + + SFMPAE + Selection of the function for stopping prefetch at locations other than on byte boundaries + 7 + 7 + read-write + + + 0 + Disables prefetch stopping at locations other than on byte boundaries + #0 + + + 1 + Enables prefetch stopping at locations other than on byte boundaries + #1 + + + + + SFMPFE + Selection of the prefetch function + 6 + 6 + read-write + + + 0 + Disables prefetch + #0 + + + 1 + Enables prefetch + #1 + + + + + SFMSE + Selection of the prefetch function + 4 + 5 + read-write + + + 00 + Does not extend QSSL + #00 + + + 01 + Extends QSSL by 33*QSPCLK + #01 + + + 10 + Extends QSSL by 129*QSPCLK + #10 + + + 11 + Extends QSSL infinitely + #11 + + + + + SFMRM + Serial interface read mode selection + 0 + 2 + read-write + + + 000 + Standard Read + #000 + + + 001 + Fast Read + #001 + + + 010 + Fast Read Dual Output + #010 + + + 011 + Fast Read Dual I/O + #011 + + + 100 + Fast Read Quad Output + #100 + + + 101 + Fast Read Quad I/O + #101 + + + 110 + Setting prohibited + #110 + + + 111 + Setting prohibited + #111 + + + + + + + SFMSSC + Chip Selection Control Register + 0x004 + 32 + read-write + 0x00000037 + 0xFFFFFFFF + + + SFMSLD + QSSL signal output timing selection + 5 + 5 + read-write + + + 0 + Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK + #0 + + + 1 + Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK + #1 + + + + + SFMSHD + QSSL signal release timing selection + 4 + 4 + read-write + + + 0 + Releases QSSL 0.5*SCK after the last rising edge of QSPCLK + #0 + + + 1 + Releases QSSL 1.5*SCK after the last rising edge of QSPCLK + #1 + + + + + SFMSW + Selection of a minimum high-level width of the QSSL signal + 0 + 3 + read-write + + + 0000 + 1 x QSPCLK + #0000 + + + 0001 + 2 x QSPCLK + #0001 + + + 0010 + 3 x QSPCLK + #0010 + + + 0011 + 4 x QSPCLK + #0011 + + + 0100 + 5 x QSPCLK + #0100 + + + 0101 + 6 x QSPCLK + #0101 + + + 0110 + 7 x QSPCLK + #0110 + + + 0111 + 8 x QSPCLK + #0111 + + + 1000 + 9 x QSPCLK + #1000 + + + 1001 + 10 x QSPCLK + #1001 + + + 1010 + 11 x QSPCLK + #1010 + + + 1011 + 12 x QSPCLK + #1011 + + + 1100 + 13 x QSPCLK + #1100 + + + 1101 + 14 x QSPCLK + #1101 + + + 1110 + 15 x QSPCLK + #1110 + + + 1111 + 16 x QSPCLK + #1111 + + + + + + + SFMSKC + Clock Control Register + 0x008 + 32 + read-write + 0x00000008 + 0xFFFFFFFF + + + SFMDTY + Selection of a duty ratio correction function for the SCK signal + 5 + 5 + read-write + + + 0 + Serial interface reference cycle selection (* Pay attention to the irregularity.) + #0 + + + 1 + Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number) + #1 + + + + + SFMDV + Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. + 0 + 4 + read-write + + + 10000 + 18 x PCLKA + #10000 + + + 10001 + 20 x PCLKA + #10001 + + + 10010 + 22 x PCLKA + #10010 + + + 10011 + 24 x PCLKA + #10011 + + + 10100 + 26 x PCLKA + #10100 + + + 10101 + 28 x PCLKA + #10101 + + + 10110 + 30 x PCLKA + #10110 + + + 10111 + 32 x PCLKA + #10111 + + + 11000 + 34 x PCLKA + #11000 + + + 11001 + 36 x PCLKA + #11001 + + + 11010 + 38 x PCLKA + #11010 + + + 11011 + 40 x PCLKA + #11011 + + + 11100 + 42 x PCLKA + #11100 + + + 11101 + 44 x PCLKA + #11101 + + + 11110 + 46 x PCLKA + #11110 + + + 11111 + 48 x PCLKA + #11111 + + + others + ( SFMDV + 2 ) x PCLKA + true + + + + + + + SFMSST + Status Register + 0x00C + 32 + read-only + 0x00000080 + 0xFFFFFFFF + + + PFOFF + Prefetch function operation state + 7 + 7 + read-only + + + 0 + The prefetch function is operating. + #0 + + + 1 + The prefetch function is not enabled or is not operating. + #1 + + + + + PFFUL + Prefetch buffer state + 6 + 6 + read-only + + + 0 + The prefetch buffer has a free space. + #0 + + + 1 + The prefetch buffer is full. + #1 + + + + + PFCNT + Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.) + 0 + 4 + read-only + + + 00000 + Nodata has been prefetched. + #00000 + + + others + Data of (PFCNT) bytes hs been prefetched. + true + + + + + + + SFMCOM + Communication Port Register + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFF00 + + + SFMD + Port for direct communication with the SPI bus.Input/output to and from this port is converted to a SPIbus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode. + 0 + 7 + read-write + + + + + SFMCMD + Communication Mode Control Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCOM + Selection of a mode of communication with the SPI bus + 0 + 0 + read-write + + + 0 + ROM access mode + #0 + + + 1 + Direct communication mode + #1 + + + + + + + SFMCST + Communication Status Register + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EROMR + Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored. + 7 + 7 + read-only + + + 0 + ROM access is not detected in direct communication mode + #0 + + + 1 + ROM access is detected in direct communication mode + #1 + + + + + COMBSY + SPI bus cycle completion state in direct communication + 0 + 0 + read-only + + + 0 + There is no serial transfer being processed. + #0 + + + 1 + There is a serial transfer being processed. + #1 + + + + + + + SFMSIC + Instruction Code Register + 0x020 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMCIC + Serial ROM instruction code to substitute + 0 + 7 + read-write + + + + + SFMSAC + Address Mode Control Register + 0x024 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + SFM4BC + Selection of a default instruction code, when Serial Interface address width is selected 4 bytes. + 4 + 4 + read-write + + + 0 + Does not use 4 Byte address read Instruction code + #0 + + + 1 + Use 4 Byte address read Instruction code + #1 + + + + + SFMAS + Selection the number of address bits of the serial interface + 0 + 1 + read-write + + + 00 + 1byte + #00 + + + 01 + 2bytes + #01 + + + 10 + 3bytes + #10 + + + 11 + 4 bytes + #11 + + + + + + + SFMSDC + Dummy Cycle Control Register + 0x028 + 32 + read-write + 0x0000FF00 + 0xFFFFFFFF + + + SFMXD + Mode data for serial ROM. (Control XIP mode) + 8 + 15 + read-write + + + 0 + XIP mode is prohibited + #0 + + + 1 + XIP mode is permitted + #1 + + + + + SFMXEN + XIP mode permission + 7 + 7 + read-write + + + 0 + XIP mode is prohibited + #0 + + + 1 + XIP mode is permitted + #1 + + + + + SFMXST + XIP mode status + 6 + 6 + read-only + + + 0 + Normal (non-XIP) mode is operating + #0 + + + 1 + XIP mode is operating + #1 + + + + + SFMDN + Selection of the number of dummy cycles of Fast Read instructions + 0 + 3 + read-write + + + 0000 + Default dummy cycles of each instruction. + #0000 + + + others + ( SFMDN + 2 ) x SCK + true + + + + + + + SFMSPC + SPI Protocol Control Register + 0x030 + 32 + read-write + 0x00000010 + 0xFFFFFFFF + + + SFMSDE + Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected. + 4 + 4 + read-write + + + 0 + Does not allocate minimum switch time + #0 + + + 1 + Allocate the minimum switch time equivalent to 1*QSPXLK + #1 + + + + + SFMSPI + Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately. + 0 + 1 + read-write + + + 00 + Extended SPI protocol + #00 + + + 01 + Dual SPI protocol + #01 + + + 10 + Quad SPI protocol + #10 + + + 11 + Setting prohibited. + #11 + + + + + + + SFMPMD + Port Control Register + 0x034 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMWPL + Specify level of WP pin + 2 + 2 + read-write + + + 0 + Low level + #0 + + + 1 + High level + #1 + + + + + + + SFMCNT1 + External QSPI Address Register 1 + 0x804 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + QSPI_EXT + BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. + 26 + 31 + read-write + + + + + + + R_RTC + Realtime Clock + 0x40044000 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000006 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + 0x0000000A + 0x01 + registers + + + 0x0000000C + 0x01 + registers + + + 0x0000000E + 0x003 + registers + + + 0x00000012 + 0x01 + registers + + + 0x00000014 + 0x01 + registers + + + 0x00000016 + 0x01 + registers + + + 0x00000018 + 0x01 + registers + + + 0x0000001A + 0x01 + registers + + + 0x0000001C + 0x003 + registers + + + 0x00000022 + 0x01 + registers + + + 0x00000024 + 0x01 + registers + + + 0x00000028 + 0x01 + registers + + + 0x0000002A + 0x005 + registers + + + 0x00000040 + 0x01 + registers + + + 0x00000042 + 0x01 + registers + + + 0x00000044 + 0x01 + registers + + + 0x00000052 + 0x01 + registers + + + 0x00000054 + 0x01 + registers + + + 0x00000056 + 0x01 + registers + + + 0x0000005A + 0x01 + registers + + + 0x0000005C + 0x01 + registers + + + 0x00000062 + 0x01 + registers + + + 0x00000064 + 0x01 + registers + + + 0x00000066 + 0x01 + registers + + + 0x0000006A + 0x01 + registers + + + 0x0000006C + 0x01 + registers + + + 0x00000072 + 0x01 + registers + + + 0x00000074 + 0x01 + registers + + + 0x00000076 + 0x01 + registers + + + 0x0000007A + 0x01 + registers + + + 0x0000007C + 0x01 + registers + + + + 3 + 0x2 + RTCCR[%s] + Time Capture Control Register + 0x40 + + RTCCR + Time Capture Control Register + 0 + 8 + read-write + 0x00 + 0x00 + + + TCNF + Time Capture Noise Filter Control + 4 + 5 + read-write + + + 00 + The noise filter is off. + #00 + + + 01 + Setting prohibited + #01 + + + 10 + The noise filter is on (count source). + #10 + + + 11 + The noise filter is on (count source by divided by 32). + #11 + + + + + TCST + Time Capture Status + 2 + 2 + read-only + + + 0 + No event is detected. + #0 + + + 1 + An event is detected. + #1 + + + + + TCCT + Time Capture Control + 0 + 1 + read-write + + + 00 + No event is detected. + #00 + + + 01 + Rising edge is detected. + #01 + + + 10 + Falling edge is detected. + #10 + + + 11 + Both edges are detected. + #11 + + + + + + + + 3 + 0x10 + CP[%s] + Capture registers + 0x50 + + RSEC + Second Capture Register + 0x02 + 8 + read-only + 0x00 + 0x00 + + + SEC10 + 10-Second Capture Capture value for the tens place of seconds + 4 + 6 + read-only + + + SEC1 + 1-Second Capture Capture value for the ones place of seconds + 0 + 3 + read-only + + + + + BCNT0 + BCNT0 Capture Register + RSEC + 0x02 + 8 + read-only + 0x00 + 0x00 + + + BCNT0CP + BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RMIN + Minute Capture Register + 0x04 + 8 + read-only + 0x00 + 0x00 + + + MIN10 + 10-Minute Capture Capture value for the tens place of minutes + 4 + 6 + read-only + + + MIN1 + 1-Minute Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT1 + BCNT1 Capture Register + RMIN + 0x04 + 8 + read-only + 0x00 + 0x00 + + + BCNT1CP + BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RHR + Hour Capture Register + 0x06 + 8 + read-only + 0x00 + 0x00 + + + PM + A.m./p.m. select for time counter setting. + 6 + 6 + read-only + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Minute Capture Capture value for the tens place of minutes + 4 + 5 + read-only + + + HR1 + 1-Minute Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT2 + BCNT2 Capture Register + RHR + 0x06 + 8 + read-only + 0x00 + 0x00 + + + BCNT2CP + BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RDAY + Date Capture Register + 0x0A + 8 + read-only + 0x00 + 0x00 + + + DATE10 + 10-Day Capture Capture value for the tens place of minutes + 4 + 5 + read-only + + + DATE1 + 1-Day Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT3 + BCNT3 Capture Register + RDAY + 0x0A + 8 + read-only + 0x00 + 0x00 + + + BCNT3CP + BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RMON + Month Capture Register + 0x0C + 8 + read-only + 0x00 + 0x00 + + + MON10 + 10-Month Capture Capture value for the tens place of months + 4 + 4 + read-only + + + MON1 + 1-Month Capture Capture value for the ones place of months + 0 + 3 + read-only + + + + + + R64CNT + 64-Hz Counter + 0x00 + 8 + read-only + 0x00 + 0x80 + + + F1HZ + 1Hz + 6 + 6 + read-only + + + F2HZ + 2Hz + 5 + 5 + read-only + + + F4HZ + 4Hz + 4 + 4 + read-only + + + F8HZ + 8Hz + 3 + 3 + read-only + + + F16HZ + 16Hz + 2 + 2 + read-only + + + F32HZ + 32Hz + 1 + 1 + read-only + + + F64HZ + 64Hz + 0 + 0 + read-only + + + + + RSECCNT + Second Counter + 0x02 + 8 + read-write + 0x00 + 0x00 + + + SEC10 + 10-Second Count Counts from 0 to 5 for 60-second counting. + 4 + 6 + read-write + + + SEC1 + 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT0 + Binary Counter 0 + RSECCNT + 0x02 + 8 + read-write + 0x00 + 0x00 + + + BCNT0 + The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMINCNT + Minute Counter + 0x04 + 8 + read-write + 0x00 + 0x00 + + + MIN10 + 10-Minute Count Counts from 0 to 5 for 60-minute counting. + 4 + 6 + read-write + + + MIN1 + 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT1 + Binary Counter 1 + RMINCNT + 0x04 + 8 + read-write + 0x00 + 0x00 + + + BCNT1 + The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RHRCNT + Hour Counter + 0x06 + 8 + read-write + 0x00 + 0x00 + + + PM + Time Counter Setting for a.m./p.m. + 6 + 6 + read-write + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Hour Count Counts from 0 to 2 once per carry from the ones place. + 4 + 5 + read-write + + + HR1 + 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT2 + Binary Counter 2 + RHRCNT + 0x06 + 8 + read-write + 0x00 + 0x00 + + + BCNT2 + The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RWKCNT + Day-of-Week Counter + 0x08 + 8 + read-write + 0x00 + 0x00 + + + DAYW + Day-of-Week Counting + 0 + 2 + read-write + + + 000 + Sunday + #000 + + + 001 + Monday + #001 + + + 010 + Tuesday + #010 + + + 011 + Wednesday + #011 + + + 100 + Thursday + #100 + + + 101 + Friday + #101 + + + 110 + Saturday + #110 + + + 111 + Setting Prohibited + #111 + + + + + + + BCNT3 + Binary Counter 3 + RWKCNT + 0x08 + 8 + read-write + 0x00 + 0x00 + + + BCNT3 + The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RDAYCNT + Day Counter + 0x0A + 8 + read-write + 0x00 + 0xC0 + + + DATE10 + 10-Day Count Counts from 0 to 3 once per carry from the ones place. + 4 + 5 + read-write + + + DATE1 + 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RMONCNT + Month Counter + 0x0C + 8 + read-write + 0x00 + 0xE0 + + + MON10 + 10-Month Count Counts from 0 to 1 once per carry from the ones place. + 4 + 4 + read-write + + + MON1 + 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RYRCNT + Year Counter + 0x0E + 16 + read-write + 0x0000 + 0xFF00 + + + YR10 + 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. + 4 + 7 + read-write + + + YR1 + 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RSECAR + Second Alarm Register + 0x10 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RSECCNT counter value. + #0 + + + 1 + The register value is compared with the RSECCNT counter value. + #1 + + + + + SEC10 + 10-Seconds Value for the tens place of seconds + 4 + 6 + read-write + + + SEC1 + 1-Second Value for the ones place of seconds + 0 + 3 + write-only + + + + + BCNT0AR + Binary Counter 0 Alarm Register + RSECAR + 0x10 + 8 + read-write + 0x00 + 0x00 + + + BCNT0AR + he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMINAR + Minute Alarm Register + 0x12 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RMINCNT counter value. + #0 + + + 1 + The register value is compared with the RMINCNT counter value. + #1 + + + + + MIN10 + 10-Minute Count Value for the tens place of minutes + 4 + 6 + read-write + + + MIN1 + 1-Minute Count Value for the ones place of minutes + 0 + 3 + read-write + + + + + BCNT1AR + Binary Counter 1 Alarm Register + RMINAR + 0x12 + 8 + read-write + 0x00 + 0x00 + + + BCNT1AR + he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RHRAR + Hour Alarm Register + 0x14 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RHRCNT counter value. + #0 + + + 1 + The register value is compared with the RHRCNT counter value. + #1 + + + + + PM + Time Counter Setting for a.m./p.m. + 6 + 6 + read-write + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Hour Count Value for the tens place of hours + 4 + 5 + read-write + + + HR1 + 1-Hour Count Value for the ones place of hours + 0 + 3 + read-write + + + + + BCNT2AR + Binary Counter 2 Alarm Register + RHRAR + 0x14 + 8 + read-write + 0x00 + 0x00 + + + BCNT2AR + The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RWKAR + Day-of-Week Alarm Register + 0x16 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RWKCNT counter value. + #0 + + + 1 + The register value is compared with the RWKCNT counter value. + #1 + + + + + DAYW + Day-of-Week Counting + 0 + 2 + read-write + + + 000 + Sunday + #000 + + + 001 + Monday + #001 + + + 010 + Tuesday + #010 + + + 011 + Wednesday + #011 + + + 100 + Thursday + #100 + + + 101 + Friday + #101 + + + 110 + Saturday + #110 + + + 111 + Setting Prohibited + #111 + + + + + + + BCNT3AR + Binary Counter 3 Alarm Register + RWKAR + 0x16 + 8 + read-write + 0x00 + 0x00 + + + BCNT3AR + The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RDAYAR + Date Alarm Register + 0x18 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RDAYCNT counter value. + #0 + + + 1 + The register value is compared with the RDAYCNT counter value. + #1 + + + + + DATE10 + 10 Days Value for the tens place of days + 4 + 5 + read-write + + + DATE1 + 1 Day Value for the ones place of days + 0 + 3 + read-write + + + + + BCNT0AER + Binary Counter 0 Alarm Enable Register + RDAYAR + 0x18 + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMONAR + Month Alarm Register + 0x1A + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RMONCNT counter value. + #0 + + + 1 + The register value is compared with the RMONCNT counter value. + #1 + + + + + MON10 + 10 Months Value for the tens place of months + 4 + 4 + read-write + + + MON1 + 1 Month Value for the ones place of months + 0 + 3 + read-write + + + + + BCNT1AER + Binary Counter 1 Alarm Enable Register + RMONAR + 0x1A + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RYRAR + Year Alarm Register + 0x1C + 16 + read-write + 0x0000 + 0xFF00 + + + YR10 + 10 Years Value for the tens place of years + 4 + 7 + read-write + + + YR1 + 1 Year Value for the ones place of years + 0 + 3 + read-write + + + + + BCNT2AER + Binary Counter 2 Alarm Enable Register + RYRAR + 0x1C + 16 + read-write + 0x0000 + 0xFF00 + + + ENB + The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RYRAREN + Year Alarm Enable Register + 0x1E + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RYRCNT counter value. + #0 + + + 1 + The register value is compared with the RYRCNT counter value. + #1 + + + + + + + BCNT3AER + Binary Counter 3 Alarm Enable Register + RYRAREN + 0x1E + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RCR1 + RTC Control Register 1 + 0x22 + 8 + read-write + 0x00 + 0x0A + + + PES + Periodic Interrupt Select + 4 + 7 + read-write + + + 0110 + A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). + #0110 + + + 0111 + A periodic interrupt is generated every 1/128 second. + #0111 + + + 1000 + A periodic interrupt is generated every 1/64 second. + #1000 + + + 1001 + A periodic interrupt is generated every 1/32 second. + #1001 + + + 1010 + A periodic interrupt is generated every 1/16 second. + #1010 + + + 1011 + A periodic interrupt is generated every 1/8 second. + #1011 + + + 1100 + A periodic interrupt is generated every 1/4 second. + #1100 + + + 1101 + A periodic interrupt is generated every 1/2 second. + #1101 + + + 1110 + A periodic interrupt is generated every 1 second. + #1110 + + + 1111 + A periodic interrupt is generated every 2 seconds. + #1111 + + + others + No periodic interrupts are generated. + true + + + + + RTCOS + RTCOUT Output Select + 3 + 3 + read-write + + + 0 + RTCOUT outputs 1 Hz. + #0 + + + 1 + RTCOUT outputs 64 Hz. + #1 + + + + + PIE + Periodic Interrupt Enable + 2 + 2 + read-write + + + 0 + A periodic interrupt request is disabled. + #0 + + + 1 + A periodic interrupt request is enabled. + #1 + + + + + CIE + Carry Interrupt Enable + 1 + 1 + read-write + + + 0 + A carry interrupt request is disabled. + #0 + + + 1 + A carry interrupt request is enabled. + #1 + + + + + AIE + Alarm Interrupt Enable + 0 + 0 + read-write + + + 0 + An alarm interrupt request is disabled. + #0 + + + 1 + An alarm interrupt request is enabled. + #1 + + + + + + + RCR2 + RTC Control Register 2 + 0x24 + 8 + read-write + 0x00 + 0x0E + + + CNTMD + Count Mode Select + 7 + 7 + read-write + + + 0 + The calendar count mode. + #0 + + + 1 + The binary count mode. + #1 + + + + + HR24 + Hours Mode + 6 + 6 + read-write + + + 0 + The RTC operates in 12-hour mode. + #0 + + + 1 + The RTC operates in 24-hour mode. + #1 + + + + + AADJP + Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) + 5 + 5 + read-write + + + 0 + The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. + #0 + + + 1 + The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. + #1 + + + + + AADJE + Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) + 4 + 4 + read-write + + + 0 + Automatic adjustment is disabled. + #0 + + + 1 + Automatic adjustment is enabled. + #1 + + + + + RTCOE + RTCOUT Output Enable + 3 + 3 + read-write + + + 0 + RTCOUT output disabled. + #0 + + + 1 + RTCOUT output enabled. + #1 + + + + + ADJ30 + 30-Second Adjustment + 2 + 2 + read-write + + + 0 + Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) + #0 + + + 1 + 30-second adjustment is executed.(write) / During 30-second adjustment.(read) + #1 + + + + + RESET + RTC Software Reset + 1 + 1 + read-write + + + 0 + Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) + #0 + + + 1 + The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) + #1 + + + + + START + Start + 0 + 0 + read-write + + + 0 + Prescaler and time counter are stopped. + #0 + + + 1 + Prescaler and time counter operate normally. + #1 + + + + + + + RCR4 + RTC Control Register 4 + 0x28 + 8 + read-write + 0x00 + 0xFE + + + RCKSEL + Count Source Select + 0 + 0 + read-write + + + 0 + Sub-clock oscillator is selected. + #0 + + + 1 + LOCO clock oscillator is selected. + #1 + + + + + ROPSEL + RTC Operation Mode Select + 7 + 7 + read-write + + + 0 + Normal operation mode is selected. + #0 + + + 1 + Low-consumption clock mode is selected. + #1 + + + + + + + RFRH + Frequency Register H + 0x2A + 16 + read-write + 0x0000 + 0xFFFE + + + RFC16 + Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. + 0 + 0 + read-write + + + + + RFRL + Frequency Register L + 0x2C + 16 + read-write + 0x0000 + 0x0000 + + + RFC + Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. + 0 + 15 + read-write + + + + + RADJ + Time Error Adjustment Register + 0x2E + 8 + read-write + 0x00 + 0x00 + + + PMADJ + Plus-Minus + 6 + 7 + read-write + + + 00 + Adjustment is not performed. + #00 + + + 01 + Adjustment is performed by the addition to the prescaler. + #01 + + + 10 + Adjustment is performed by the subtraction from the prescaler. + #10 + + + 11 + Setting prohibited + #11 + + + + + ADJ + Adjustment Value These bits specify the adjustment value from the prescaler. + 0 + 5 + read-write + + + + + + + R_SCI0 + Serial Communications Interface + 0x40070000 + + 0x00000000 + 0x01D + registers + + + + SMR + Serial Mode Register (SCMR.SMIF = 0) + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CM + Communication Mode + 7 + 7 + read-write + + + 0 + Asynchronous mode or simple I2C mode + #0 + + + 1 + Clock synchronous mode + #1 + + + + + CHR + Character Length(Valid only in asynchronous mode) + 6 + 6 + read-write + + + 0 + Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) + #0 + + + 1 + Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) + #1 + + + + + PE + Parity Enable(Valid only in asynchronous mode) + 5 + 5 + read-write + + + 0 + Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) + #0 + + + 1 + The parity bit is added (transmitting) / The parity bit is checked (receiving) + #1 + + + + + PM + Parity Mode (Valid only when the PE bit is 1) + 4 + 4 + read-write + + + 0 + Selects even parity + #0 + + + 1 + Selects odd parity + #1 + + + + + STOP + Stop Bit Length(Valid only in asynchronous mode) + 3 + 3 + read-write + + + 0 + 1 stop bit + #0 + + + 1 + 2 stop bits + #1 + + + + + MP + Multi-Processor Mode(Valid only in asynchronous mode) + 2 + 2 + read-write + + + 0 + Multi-processor communications function is disabled + #0 + + + 1 + Multi-processor communications function is enabled + #1 + + + + + CKS + Clock Select + 0 + 1 + read-write + + + 00 + PCLK clock + #00 + + + 01 + PCLK/4 clock + #01 + + + 10 + PCLK/16 clock + #10 + + + 11 + PCLK/64 clock + #11 + + + + + + + SMR_SMCI + Serial mode register (SCMR.SMIF = 1) + SMR + 0x00 + 8 + read-write + 0x00 + 0xFF + + + GM + GSM Mode + 7 + 7 + read-write + + + 0 + Normal mode operation + #0 + + + 1 + GSM mode operation + #1 + + + + + BLK + Block Transfer Mode + 6 + 6 + read-write + + + 0 + Normal mode operation + #0 + + + 1 + Block transfer mode operation + #1 + + + + + PE + Parity Enable(Valid only in asynchronous mode) + 5 + 5 + read-write + + + 0 + Setting Prohibited + #0 + + + 1 + Set this bit to 1 in smart card interface mode. + #1 + + + + + PM + Parity Mode (Valid only when the PE bit is 1) + 4 + 4 + read-write + + + 0 + Selects even parity + #0 + + + 1 + Selects odd parity + #1 + + + + + BCP + Base Clock Pulse(Valid only in asynchronous mode) + 2 + 3 + read-write + + + 00 + 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) + #00 + + + 01 + 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) + #01 + + + 10 + 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) + #10 + + + 11 + 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) + #11 + + + + + CKS + Clock Select + 0 + 1 + read-write + + + 00 + PCLK clock + #00 + + + 01 + PCLK/4 clock + #01 + + + 10 + PCLK/16 clock + #10 + + + 11 + PCLK/64 clock + #11 + + + + + + + BRR + Bit Rate Register + 0x01 + 8 + read-write + 0xFF + 0xFF + + + BRR + BRR is an 8-bit register that adjusts the bit rate. + 0 + 7 + read-write + + + + + SCR + Serial Control Register (SCMR.SMIF = 0) + 0x02 + 8 + read-write + 0x00 + 0xFF + + + TIE + Transmit Interrupt Enable + 7 + 7 + read-write + + + 0 + SCI_TXI interrupt request is disabled + #0 + + + 1 + SCI_TXI interrupt request is enabled + #1 + + + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + 0 + SCI_RXI and SCI_ERI interrupt requests are disabled + #0 + + + 1 + SCI_RXI and SCI_ERI interrupt requests are enabled + #1 + + + + + TE + Transmit Enable + 5 + 5 + read-write + + + 0 + Serial transmission is disabled + #0 + + + 1 + Serial transmission is enabled + #1 + + + + + RE + Receive Enable + 4 + 4 + read-write + + + 0 + Serial reception is disabled + #0 + + + 1 + Serial reception is enabled + #1 + + + + + MPIE + Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) + 3 + 3 + read-write + + + 0 + Normal reception + #0 + + + 1 + When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. + #1 + + + + + TEIE + Transmit End Interrupt Enable + 2 + 2 + read-write + + + 0 + SCI_TEI interrupt request is disabled + #0 + + + 1 + SCI_TEI interrupt request is enabled + #1 + + + + + CKE + Clock Enable + 0 + 1 + read-write + + + 00 + The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) + #00 + + + 01 + The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) + #01 + + + others + The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) + true + + + + + + + SCR_SMCI + Serial Control Register (SCMR.SMIF =1) + SCR + 0x02 + 8 + read-write + 0x00 + 0xFF + + + TIE + Transmit Interrupt Enable + 7 + 7 + read-write + + + 0 + A SCI_TXI interrupt request is disabled + #0 + + + 1 + A SCI_TXI interrupt request is enabled + #1 + + + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + 0 + SCI_RXI and SCI_ERI interrupt requests are disabled + #0 + + + 1 + SCI_RXI and SCI_ERI interrupt requests are enabled + #1 + + + + + TE + Transmit Enable + 5 + 5 + read-write + + + 0 + Serial transmission is disabled + #0 + + + 1 + Serial transmission is enabled + #1 + + + + + RE + Receive Enable + 4 + 4 + read-write + + + 0 + Serial reception is disabled + #0 + + + 1 + Serial reception is enabled + #1 + + + + + MPIE + Multi-Processor Interrupt Enable + 3 + 3 + read-write + + + TEIE + Transmit End Interrupt Enable + 2 + 2 + read-write + + + CKE + Clock Enable + 0 + 1 + read-write + + + 00 + Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) + #00 + + + 01 + Clock Output + #01 + + + 10 + Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) + #10 + + + 11 + Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) + #11 + + + + + + + TDR + Transmit Data Register + 0x03 + 8 + read-write + 0xFF + 0xFF + + + TDR + TDR is an 8-bit register that stores transmit data. + 0 + 7 + read-write + + + + + SSR + Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) + 0x04 + 8 + read-write + 0x84 + 0xFF + + + TDRE + Transmit Data Empty Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Transmit data is in TDR register + #0 + + + 1 + No transmit data is in TDR register + #1 + + + + + RDRF + Receive Data Full Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No received data is in RDR register + #0 + + + 1 + Received data is in RDR register + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred + #0 + + + 1 + A framing error has occurred + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-only + + + 0 + A character is being transmitted. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + MPB + Multi-Processor + 1 + 1 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + MPBT + Multi-Processor Bit Transfer + 0 + 0 + read-write + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + + + SSR_FIFO + Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) + SSR + 0x04 + 8 + read-write + 0x80 + 0xFD + + + TDFE + Transmit FIFO data empty flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. + #0 + + + 1 + The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number + #1 + + + + + RDF + Receive FIFO data full flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + The quantity of receive data written in FRDR falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred. + #0 + + + 1 + A framing error has occurred. + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred. + #0 + + + 1 + A parity error has occurred. + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + A character is being transmitted or standing by for transmission. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + DR + Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. + #1 + + + + + + + SSR_SMCI + Serial Status Register(SCMR.SMIF = 1) + SSR + 0x04 + 8 + read-write + 0x84 + 0xFF + + + TDRE + Transmit Data Empty Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Transmit data is in TDR register + #0 + + + 1 + No transmit data is in TDR register + #1 + + + + + RDRF + Receive Data Full Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No received data is in RDR register + #0 + + + 1 + Received data is in RDR register + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + ERS + Error Signal Status Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Low error signal not responded + #0 + + + 1 + Low error signal responded + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-only + + + 0 + A character is being transmitted. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + MPB + Multi-ProcessorThis bit should be 0 in smart card interface mode. + 1 + 1 + read-only + + + MPBT + Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. + 0 + 0 + read-write + + + + + RDR + Receive Data Register + 0x05 + 8 + read-only + 0x00 + 0xFF + + + RDR + RDR is an 8-bit register that stores receive data. + 0 + 7 + read-only + + + + + SCMR + Smart Card Mode Register + 0x06 + 8 + read-write + 0xF2 + 0xFF + + + BCP2 + Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits + 7 + 7 + read-write + + + 0 + S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) + #0 + + + 1 + S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) + #1 + + + + + CHR1 + Character Length 1(Only valid in asynchronous mode) + 4 + 4 + read-write + + + 0 + Transmit/receive in 9-bit data length + #0 + + + 1 + Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) + #1 + + + + + SDIR + Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. + 3 + 3 + read-write + + + 0 + Transfer with LSB first + #0 + + + 1 + Transfer with MSB first + #1 + + + + + SINV + Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. + 2 + 2 + read-write + + + 0 + TDR contents are transmitted as they are. Receive data is stored as it is in RDR. + #0 + + + 1 + TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. + #1 + + + + + SMIF + Smart Card Interface Mode Select + 0 + 0 + read-write + + + 0 + Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) + #0 + + + 1 + Smart card interface mode + #1 + + + + + + + SEMR + Serial Extended Mode Register + 0x07 + 8 + read-write + 0x00 + 0xFF + + + RXDESEL + Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) + 7 + 7 + read-write + + + 0 + The low level on the RXDn pin is detected as the start bit. + #0 + + + 1 + A falling edge on the RXDn pin is detected as the start bit. + #1 + + + + + BGDM + Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). + 6 + 6 + read-write + + + 0 + Baud rate generator outputs the clock with normal frequency. + #0 + + + 1 + Baud rate generator outputs the clock with doubled frequency. + #1 + + + + + NFEN + Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. + 5 + 5 + read-write + + + 0 + Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. + #0 + + + 1 + Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. + #1 + + + + + ABCS + Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) + 4 + 4 + read-write + + + 0 + Selects 16 base clock cycles for 1-bit period. + #0 + + + 1 + Selects 8 base clock cycles for 1-bit period. + #1 + + + + + ABCSE + Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) + 3 + 3 + read-write + + + 0 + Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. + #0 + + + 1 + Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. + #1 + + + + + BRME + Bit Rate Modulation Enable + 2 + 2 + read-write + + + 0 + Bit rate modulation function is disabled. + #0 + + + 1 + Bit rate modulation function is enabled. + #1 + + + + + + + SNFR + Noise Filter Setting Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + NFCS + Noise Filter Clock Select + 0 + 2 + read-write + + + 000 + The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) + #000 + + + 001 + The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) + #001 + + + 010 + The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) + #010 + + + 011 + The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) + #011 + + + 100 + The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) + #100 + + + others + Settings prohibited. + true + + + + + + + SIMR1 + I2C Mode Register 1 + 0x09 + 8 + read-write + 0x00 + 0xFF + + + IICDL + SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. + 3 + 7 + read-write + + + 00000 + No output delay + #00000 + + + others + (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. + true + + + + + IICM + Simple I2C Mode Select + 0 + 0 + read-write + + + 0 + Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) + #0 + + + 1 + Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) + #1 + + + + + + + SIMR2 + I2C Mode Register 2 + 0x0A + 8 + read-write + 0x00 + 0xFF + + + IICACKT + ACK Transmission Data + 5 + 5 + read-write + + + 0 + ACK transmission + #0 + + + 1 + NACK transmission and reception of ACK/NACK + #1 + + + + + IICCSC + Clock Synchronization + 1 + 1 + read-write + + + 0 + No synchronization with the clock signal + #0 + + + 1 + Synchronization with the clock signal + #1 + + + + + IICINTM + I2C Interrupt Mode Select + 0 + 0 + read-write + + + 0 + Use ACK/NACK interrupts. + #0 + + + 1 + Use reception and transmission interrupts + #1 + + + + + + + SIMR3 + I2C Mode Register 3 + 0x0B + 8 + read-write + 0x00 + 0xFF + + + IICSCLS + SCL Output Select + 6 + 7 + read-write + + + 00 + Serial clock output + #00 + + + 01 + Generate a start, restart, or stop condition. + #01 + + + 10 + Output the low level on the SSCLn pin. + #10 + + + 11 + Place the SSCLn pin in the high-impedance state. + #11 + + + + + IICSDAS + SDA Output Select + 4 + 5 + read-write + + + 00 + Serial data output + #00 + + + 01 + Generate a start, restart, or stop condition. + #01 + + + 10 + Output the low level on the SSDAn pin. + #10 + + + 11 + Place the SSDAn pin in the high-impedance state. + #11 + + + + + IICSTIF + Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) + 3 + 3 + read-write + zeroToClear + modify + + + 0 + There are no requests for generating conditions or a condition is being generated. + #0 + + + 1 + A start, restart, or stop condition is completely generated. + #1 + + + + + IICSTPREQ + Stop Condition Generation + 2 + 2 + read-write + + + 0 + A stop condition is not generated. + #0 + + + 1 + A stop condition is generated. + #1 + + + + + IICRSTAREQ + Restart Condition Generation + 1 + 1 + read-write + + + 0 + A restart condition is not generated. + #0 + + + 1 + A restart condition is generated. + #1 + + + + + IICSTAREQ + Start Condition Generation + 0 + 0 + read-write + + + 0 + A start condition is not generated. + #0 + + + 1 + A start condition is generated. + #1 + + + + + + + SISR + I2C Status Register + 0x0C + 8 + read-only + 0x00 + 0xCB + + + IICACKR + ACK Reception Data Flag + 0 + 0 + read-only + + + 0 + ACK received + #0 + + + 1 + NACK received + #1 + + + + + + + SPMR + SPI Mode Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + CKPH + Clock Phase Select + 7 + 7 + read-write + + + 0 + Clock is not delayed. + #0 + + + 1 + Clock is delayed. + #1 + + + + + CKPOL + Clock Polarity Select + 6 + 6 + read-write + + + 0 + Clock polarity is not inverted. + #0 + + + 1 + Clock polarity is inverted + #1 + + + + + MFF + Mode Fault Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No mode fault error + #0 + + + 1 + Mode fault error + #1 + + + + + MSS + Master Slave Select + 2 + 2 + read-write + + + 0 + Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). + #0 + + + 1 + Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). + #1 + + + + + CTSE + CTS Enable + 1 + 1 + read-write + + + 0 + CTS function is disabled (RTS output function is enabled). + #0 + + + 1 + CTS function is enabled. + #1 + + + + + SSE + SSn Pin Function Enable + 0 + 0 + read-write + + + 0 + SSn pin function is disabled. + #0 + + + 1 + SSn pin function is enabled. + #1 + + + + + + + TDRHL + Transmit 9-bit Data Register + 0x0E + 16 + read-write + 0xFFFF + 0xFFFF + + + TDRHL + TDRHL is a 16-bit register that stores transmit data. + 0 + 15 + write-only + + + + + FTDRHL + Transmit FIFO Data Register HL + TDRHL + 0x0E + 16 + write-only + 0xFFFF + 0xFFFF + + + MPBT + Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) + 9 + 9 + write-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + TDAT + Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 8 + write-only + + + + + FTDRH + Transmit FIFO Data Register H + TDRHL + 0x0E + 8 + write-only + 0xFF + 0xFF + + + MPBT + Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) + 1 + 1 + write-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + TDATH + Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + write-only + + + + + FTDRL + Transmit FIFO Data Register L + TDRHL + 0x0F + 8 + write-only + 0xFF + 0xFF + + + TDATL + Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 7 + write-only + + + + + RDRHL + Receive 9-bit Data Register + 0x10 + 16 + read-only + 0x0000 + 0xFFFF + + + RDRHL + RDRHL is an 16-bit register that stores receive data. + 0 + 15 + read-only + + + + + FRDRHL + Receive FIFO Data Register HL + RDRHL + 0x10 + 16 + read-only + 0x0000 + 0xFFFF + + + RDF + Receive FIFO data full flag(It is same as SSR.RDF) + 14 + 14 + read-only + + + 0 + The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun error flag(It is same as SSR.ORER) + 13 + 13 + read-only + + + 0 + No overrun error occurred. + #0 + + + 1 + An overrun error has occurred. + #1 + + + + + FER + Framing error flag + 12 + 12 + read-only + + + 0 + No framing error occurred at the first data of FRDRH and FRDRL. + #0 + + + 1 + A framing error has occurred at the first data of FRDRH and FRDRL. + #1 + + + + + PER + Parity error flag + 11 + 11 + read-only + + + 0 + No parity error occurred at the first data of FRDRH and FRDRL. + #0 + + + 1 + A parity error has occurred at the first data of FRDRH and FRDRL. + #1 + + + + + DR + Receive data ready flag(It is same as SSR.DR) + 10 + 10 + read-only + + + 0 + Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving. + #1 + + + + + MPB + Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) + 9 + 9 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + RDAT + Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 8 + read-only + + + + + FRDRH + Receive FIFO Data Register H + RDRHL + 0x10 + 8 + read-only + 0x00 + 0xFF + + + RDF + Receive FIFO data full flag(It is same as SSR.RDF) + 6 + 6 + read-only + + + 0 + The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun error flag(It is same as SSR.ORER) + 5 + 5 + read-only + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing error flag + 4 + 4 + read-only + + + 0 + No framing error occurred at the first data of FRDRH and FRDRL + #0 + + + 1 + A framing error has occurred at the first data of FRDRH and FRDRL + #1 + + + + + PER + Parity error flag + 3 + 3 + read-only + + + 0 + No parity error occurred at the first data of FRDRH and FRDRL + #0 + + + 1 + A parity error has occurred at the first data of FRDRH and FRDRL + #1 + + + + + DR + Receive data ready flag(It is same as SSR.DR) + 2 + 2 + read-only + + + 0 + Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving. + #1 + + + + + MPB + Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) + 1 + 1 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + RDATH + Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + read-only + + + + + FRDRL + Receive FIFO Data Register L + RDRHL + 0x11 + 8 + read-only + 0x00 + 0xFF + + + RDATL + Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. + 0 + 7 + read-only + + + + + MDDR + Modulation Duty Register + 0x12 + 8 + read-write + 0xFF + 0xFF + + + MDDR + MDDR corrects the bit rate adjusted by the BRR register. + 0 + 7 + read-write + + + + + DCCR + Data Compare Match Control Register + 0x13 + 8 + read-write + 0x40 + 0xFF + + + DCME + Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) + 7 + 7 + read-write + + + 0 + Address match function is disabled. + #0 + + + 1 + Address match function is enabled + #1 + + + + + IDSEL + ID frame select(Valid only in asynchronous mode(including multi-processor) + 6 + 6 + read-write + + + 0 + Always compare data regardless of the value of the MPB bit. + #0 + + + 1 + Compare data when the MPB bit is 1 (ID frame) only. + #1 + + + + + DFER + Data Compare Match Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred + #0 + + + 1 + A framing error has occurred + #1 + + + + + DPER + Data Compare Match Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + DCMF + Data Compare Match Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No matched + #0 + + + 1 + Matched + #1 + + + + + + + FCR + FIFO Control Register + 0x14 + 16 + read-write + 0xF800 + 0xFFFF + + + RSTRG + RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 12 + 15 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + RTRG + Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 8 + 11 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + TTRG + Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 4 + 7 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + DRES + Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) + 3 + 3 + read-write + + + 0 + reception data full interrupt (RXI) + #0 + + + 1 + receive error interrupt (ERI) + #1 + + + + + TFRST + Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) + 2 + 2 + read-write + + + 0 + The number of data stored in FTDRH and FTDRL register are NOT made 0 + #0 + + + 1 + The number of data stored in FTDRH and FTDRL register are made 0 + #1 + + + + + RFRST + Receive FIFO Data Register Reset(Valid only in FCR.FM=1) + 1 + 1 + read-write + + + 0 + The number of data stored in FRDRH and FRDRL register are NOT made 0 + #0 + + + 1 + The number of data stored in FRDRH and FRDRL register are made 0 + #1 + + + + + FM + FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 0 + 0 + read-write + + + 0 + Non-FIFO mode(Selects o TDR/RDR for communication) + #0 + + + 1 + FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) + #1 + + + + + + + FDR + FIFO Data Count Register + 0x16 + 16 + read-only + 0x0000 + 0xFFFF + + + T + Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) + 8 + 12 + read-only + + + R + Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) + 0 + 4 + read-only + + + + + LSR + Line Status Register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + PNUM + Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). + 8 + 12 + read-only + + + FNUM + Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). + 2 + 6 + read-only + + + ORER + Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + read-only + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + + + CDR + Compare Match Data Register + 0x1A + 16 + read-write + 0x0000 + 0xFFFF + + + CMPD + Compare Match DataCompare data pattern for address match wake-up function + 0 + 8 + read-write + + + + + SPTR + Serial Port Register + 0x1C + 8 + read-write + 0x03 + 0xFF + + + SPB2IO + Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) + 2 + 2 + read-write + + + 0 + The value of SPB2DT bit is not output in TXD pin. + #0 + + + 1 + The value of SPB2DT bit is output in TXD pin. + #1 + + + + + SPB2DT + Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) + 1 + 1 + read-write + + + 0 + Low level is output on TXD pin + #0 + + + 1 + High level is output on TXD pin + #1 + + + + + RXDMON + Serial input data monitor bit(The state of the RXD terminal is shown.) + 0 + 0 + read-only + + + 0 + RXD pin is low. + #0 + + + 1 + RXD pin is high. + #1 + + + + + + + + + R_SCI1 + 0x40070020 + + + R_SCI2 + 0x40070040 + + + R_SCI3 + 0x40070060 + + + R_SCI4 + 0x40070080 + + + R_SCI5 + 0x400700A0 + + + R_SCI6 + 0x400700C0 + + + R_SCI7 + 0x400700E0 + + + R_SCI8 + 0x40070100 + + + R_SCI9 + 0x40070120 + + + R_SDADC0 + + 0x4009C000 + + 0x00000000 + 0x02 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x019 + registers + + + 0x00000024 + 0x008 + registers + + + 0x00000030 + 0x01 + registers + + + 0x00000034 + 0x01 + registers + + + 0x0000003C + 0x01 + registers + + + + STC1 + Startup Control Register 1 + 0x0 + 16 + read-write + 0XFFFF + + + VSBIAS + Reference voltage select + 8 + 11 + read-write + + + 0000 + 0.8V + #0000 + + + 0001 + 1.0V + #0001 + + + 0010 + 1.2V + #0010 + + + 0011 + 1.4V + #0011 + + + 0100 + 1.6V + #0100 + + + 0101 + 1.8V + #0101 + + + 0110 + 2.0V + #0110 + + + 0111 + 2.2V + #0111 + + + 1111 + 2.4V(only available when VREFSEL=0) + #1111 + + + + + CLKDIV + SDADC24 Reference Clock Division + 0 + 3 + read-write + + + 0000 + No Division + #0000 + + + 0001 + SDADCCLK/2 + #0001 + + + 0010 + SDADCCLK/3 + #0010 + + + 0011 + SDADCCLK/4 + #0011 + + + 0100 + SDADCCLK/5 + #0100 + + + 0101 + SDADCCLK/6 + #0101 + + + 0110 + SDADCCLK/8 + #0110 + + + 0111 + SDADCCLK/12 + #0111 + + + 1000 + SDADCCLK/16 + #1000 + + + + + SDADLPM + A/D conversion operation model select + 7 + 7 + read-write + + + 0 + Normal A/D conversion mode, SDADC Reference Clock: 4 MHz, Oversampingly clock: 1MHz + #0 + + + + + VREFSEL + VREF mode select + 15 + 15 + read-write + + + 0 + Internal VREF Mode + #0 + + + + + + + STC2 + Startup Control Register 2 + 0x04 + 8 + read-write + 0x00 + 0xFF + + + BGRPON + BGR part power control + 0 + 0 + + + 0 + Turn off power to ADBGR, SBIAS, VREFI, and ADREG + #0 + + + 1 + Turn onpower to ADBGR, SBIAS, VREFI, and ADREG + #1 + + + + + ADFPWDS + ADC reference supply part + 2 + 2 + + + 0 + Power of ADREG controlled by BGRPON register + #0 + + + 1 + Power of ADREG is off regardless of BGRPON setting + #1 + + + + + ADCPON + ADREG forced power-down + 1 + 1 + + + 0 + Turn off power to VBIAS, PGA and sigma-delta A/D converter + #0 + + + 1 + Turn on power to VBIAS, PGA and sigma-delta A/D converter + #1 + + + + + + + 5 + 4 + PGAC[%s] + Input Multiplexer %s Setting Register + 0x08 + 32 + read-write + 0x00010040 + 0xFFFFFFFF + + + PGAASN + Selection of the mode for specifying the number of A/D conversions in ADSCAN + 31 + 31 + read-write + + + 0 + Specify 1 to 8,032 times by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + #0 + + + 1 + Specify 1 to 255 times linearly by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + #1 + + + + + PGACVE + Calibration enable + 30 + 30 + read-write + + + 0 + Do not calculate the calibration correction factor + #0 + + + 1 + Calculate the calibration correction factor + #1 + + + + + PGAREV + Single-End Input A/D Converted Data Inversion Select + 28 + 28 + read-write + + + 0 + Do not invert the conversion result data + #0 + + + 1 + Invert the conversion result data + #1 + + + + + PGAAVE + Selection of averaging processing + 26 + 27 + read-write + + + 00 + Do not average the A/D conversion results + #00 + + + 01 + Do not average the A/D conversion results + #01 + + + 10 + Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs + #10 + + + 11 + Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times). + #11 + + + + + PGAAVN + Selection of the number of data to be averaged + 24 + 25 + read-write + + + 00 + 8 + #00 + + + 01 + 16 + #01 + + + 10 + 32 + #10 + + + 11 + 64 + #11 + + + + + PGACTN + Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN + 21 + 23 + read-write + + + 000 + 0 + #000 + + + 001 + 1 + #001 + + + 010 + 2 + #010 + + + 011 + 3 + #011 + + + 100 + 4 + #100 + + + 101 + 5 + #101 + + + 110 + 6 + #110 + + + 111 + 7 + #111 + + + + + PGACTM + Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN + 16 + 20 + read-write + + + PGASEL + Analog Channel Input Mode Select + 15 + 15 + read-write + + + 0 + Differential input mode + #0 + + + 1 + Single-end input mode + #1 + + + + + PGAPOL + Polarity select + 14 + 14 + read-write + + + 0 + Positive-side single-end input + #0 + + + 1 + Negative-side single-end input + #1 + + + + + PGAOFS + Offset voltage select + 8 + 12 + read-write + + + PGAOSR + Oversampling ratio select + 5 + 7 + read-write + + + 000 + 64 + #000 + + + 001 + 128 + #001 + + + 010 + 256 + #010 + + + 011 + 512 + #011 + + + 100 + 1024 + #100 + + + 101 + 2048 + #101 + + + others + Settings are prohibited. + true + + + + + PGAGC + Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal ) + 0 + 4 + read-write + + + 00000 + (1, 1, 1) + #00000 + + + 00100 + (2, 1, 2) + #00100 + + + 01000 + (3, 1, 3) + #01000 + + + 01100 + (4, 1, 4) + #01100 + + + 10000 + (8, 1, 8) + #10000 + + + 00001 + (1, 2, 2) + #00001 + + + 00101 + (2, 2, 4) + #00101 + + + 01001 + (3, 2, 6) + #01001 + + + 01101 + (4, 2, 8) + #01101 + + + 10001 + (8, 2, 16) + #10001 + + + 00010 + (1, 4, 4) + #00010 + + + 00110 + (2, 4, 8) + #00110 + + + 01010 + (3, 4, 12) + #01010 + + + 01110 + (4, 4, 16) + #01110 + + + 10010 + (8, 4, 32) + #10010 + + + 00011 + (1, 8, 8) + #00011 + + + 00111 + (2, 8, 16) + #00111 + + + 01011 + (3, 8, 24) + #01011 + + + 01111 + (4, 8, 32). + #01111 + + + others + Settings are prohibited. + true + + + + + + + ADC1 + Sigma-Delta A/D Converter Control Register 1 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PGASLFT + PGA offset self-diagnosis enable + 20 + 20 + read-write + + + 0 + Disable PGA offset self-diagnosis + #0 + + + 1 + Enable PGA offset self-diagnosis + #1 + + + + + PGADISC + Disconnection Detection Assist Setting + 17 + 17 + read-write + + + 0 + Discharge + #0 + + + 1 + Pre-charge + #1 + + + + + PGADISA + Control of disconnection detection + 16 + 16 + read-write + + + 0 + Normal operation + #0 + + + 1 + State of disconnection detection + #1 + + + + + SDADBMP + A/D conversion control of the signal from input multiplexer + 8 + 12 + read-write + + + SDADTMD + Selection of A/D conversion trigger signal + 4 + 4 + read-write + + + 0 + Software trigger (conversion is started by a write to SFR) + #0 + + + 1 + Hardware trigger (conversion is started in synchronization with the event signal selected by ELC_SDADC24). + #1 + + + + + SDADSCM + Selection of autoscan mode + 0 + 0 + read-write + + + 0 + Continuous scan mode + #0 + + + 1 + Single scan mode + #1 + + + + + + + ADC2 + Sigma-Delta A/D Converter Control Register 2 + 0x20 + 8 + read-write + 0x00 + 0xFF + + + SDADST + Control of A/D conversion + 0 + 0 + read-write + + + 0 + Stop A/D conversion + #0 + + + 1 + Start A/D conversion + #1 + + + + + + + ADCR + Sigma-delta A/D Converter Conversion Result Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDADCRC + Channel number for an A/D conversion result + 25 + 27 + read-only + + + 000 + Reset value (Conversion result is invalid) + #000 + + + 001 + Input multiplexer 0 (ANSD0P / ANSD0N) + #001 + + + 010 + Input multiplexer 1 (ANSD1P / ANSD1N) + #010 + + + 011 + Input multiplexer 2 (ANSD2P / ANSD2N) + #011 + + + 100 + Input multiplexer 3 (ANSD3P / ANSD3N) + #100 + + + 101 + Input multiplexer 4 (AMP0O / AMP1O) + #101 + + + + + SDADCRS + Status of an A/D conversion result + 24 + 24 + read-only + + + 0 + Normal status (within the range) + #0 + + + 1 + Overflow occurred + #1 + + + + + SDADCRD + The 24-bit A/D conversion result + 0 + 23 + read-only + + + + + ADAR + Sigma-delta A/D Converter Average Value Register + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SDADMVC + Channel number for an A/D conversion result + 25 + 27 + read-only + + + 000 + Reset value (Conversion result is invalid) + #000 + + + 001 + Input multiplexer 0 (ANSD0P / ANSD0N) + #001 + + + 010 + Input multiplexer 1 (ANSD1P / ANSD1N) + #010 + + + 011 + Input multiplexer 2 (ANSD2P / ANSD2N) + #011 + + + 100 + Input multiplexer 3 (ANSD3P / ANSD3N) + #100 + + + 101 + Input multiplexer 4 (AMP0O / AMP1O). + #101 + + + + + SDADMVS + Status of an A/D conversion result + 24 + 24 + read-only + + + 0 + Normal status (within the range) + #0 + + + 1 + Overflow occurred + #1 + + + + + SDADMVD + The 24-bit A/D average value + 0 + 23 + read-only + + + + + CLBC + Calibration Control Register + 0x30 + 8 + 0x00 + 0xFF + + + CLBMD + These bits are read as 0. The write value should be 0. + 0 + 1 + read-write + + + 00 + Internal calibration mode + #00 + + + 01 + External offset calibration mode + #01 + + + 10 + External gain calibration mode + #10 + + + 11 + Settings are prohibited + #11 + + + + + + + CLBSTR + Calibration Start Control Register + 0x34 + 8 + read-write + 0x00 + 0xFF + + + CLBST + Calibration start control + 0 + 0 + read-write + + + 0 + Disable writing + #0 + + + 1 + Start calibration + #1 + + + + + + + CLBSSR + Calibration Status Register + 0x3C + 8 + read-only + 0x00 + + + CLBSS + Calibration status + 0 + 0 + read-only + + + 0 + Calibration is not running + #0 + + + 1 + Calibration is running + #1 + + + + + + + + + R_SDHI0 + SD/MMC Host Interface + 0x40062000 + + 0x00000000 + 0x04 + registers + + + 0x00000008 + 0x04C + registers + + + 0x00000058 + 0x00C + registers + + + 0x00000068 + 0x00C + registers + + + 0x000001B0 + 0x04 + registers + + + 0x000001C0 + 0x04 + registers + + + 0x000001CC + 0x04 + registers + + + 0x000001E0 + 0x04 + registers + + + + SD_CMD + Command Type Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMD12AT + Multiple Block Transfer Mode (enabled at multiple block transfer) + 14 + 15 + read-write + + + 00 + CMD12 is automatically issued at multiple block transfer. + #00 + + + 01 + CMD12 is not automatically issued at multiple block transfer. + #01 + + + 10 + Setting prohibited + #10 + + + 11 + Setting prohibited + #11 + + + + + TRSTP + Single/Multiple Block Transfer (enabled when the command with data is handled) + 13 + 13 + read-write + + + 0 + Single block transfer + #0 + + + 1 + Multiple block transfer + #1 + + + + + CMDRW + Write/Read Mode (enabled when the command with data is handled) + 12 + 12 + read-write + + + 0 + Write (SD/MMC host interface -> SD card/MMC) + #0 + + + 1 + Read (SD/MMC host interface <- SD card/MMC) + #1 + + + + + CMDTP + Data Mode (Command Type) + 11 + 11 + read-write + + + 0 + Command does not include data transfer (bc, bcr, or ac) + #0 + + + 1 + Command includes data transfer (adtc) + #1 + + + + + RSPTP + Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type. + 8 + 10 + read-write + + + 000 + Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. + #000 + + + 011 + Expansion mode and no response + #011 + + + 100 + Expansion mode and R1, R5, R6, or R7 response + #100 + + + 101 + Expansion mode and R1b response + #101 + + + 110 + Expansion mode and R2 response + #110 + + + 111 + Expansion mode and R3 or R4 response + #111 + + + others + Settings prohibited. + true + + + + + ACMD + Command Type Select + 6 + 7 + read-write + + + 00 + CMD + #00 + + + 01 + ACMD + #01 + + + others + Setting prohibited + true + + + + + CMDIDX + Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 + 0 + 5 + read-write + + + + + SD_ARG + SD Command Argument Register + 0x008 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_ARG + Argument RegisterSet command format[39:8] (argument) + 0 + 31 + read-write + + + + + SD_ARG1 + SD Command Argument Register 1 + 0x00C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_ARG1 + Argument Register 1Set command format[39:24] (argument) + 0 + 15 + read-write + + + + + SD_STOP + Data Stop Register + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC + Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. + 8 + 8 + read-write + + + 0 + Disables SD_SECCNT setting value. + #0 + + + 1 + Enables SD_SECCNT setting value. + #1 + + + + + STP + Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set. + 0 + 0 + read-write + + + + + SD_SECCNT + Block Count Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_SECCNT + Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. + 0 + 31 + read-write + + + + + SD_RSP10 + SD Card Response Register 10 + 0x018 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP10 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP1 + SD Card Response Register 1 + 0x01C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP1 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP32 + SD Card Response Register 32 + 0x020 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP32 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP3 + SD Card Response Register 3 + 0x024 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP3 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP54 + SD Card Response Register 54 + 0x028 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP54 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP5 + SD Card Response Register 5 + 0x02C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP5 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP76 + SD Card Response Register 76 + 0x030 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP76 + Store the response from the SD card/MMC + 0 + 23 + read-only + + + + + SD_RSP7 + SD Card Response Register 7 + 0x034 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP7 + Store the response from the SD card/MMC + 0 + 7 + read-only + + + + + SD_INFO1 + SD Card Interrupt Flag Register 1 + 0x038 + 32 + read-write + 0x00000000 + 0xFFFFFB5F + + + SDD3MON + Inticates the SDnDAT3 State + 10 + 10 + read-only + + + 0 + SDnDAT3 is set to 0. + #0 + + + 1 + SDnDAT3 is set to 1. + #1 + + + + + SDD3IN + SDnDAT3 Card Insertion + 9 + 9 + read-write + zeroToClear + modify + + + 0 + SD card insertion not detected + #0 + + + 1 + SD card insertion detected + #1 + + + + + SDD3RM + SDnDAT3 Card Removal + 8 + 8 + read-write + zeroToClear + modify + + + 0 + SD card removal not detected + #0 + + + 1 + SD card removal detected + #1 + + + + + SDWPMON + Indicates the SDnWP state + 7 + 7 + read-only + + + 0 + SDnWP is set to 1. + #0 + + + 1 + SDnWP is set to 0. + #1 + + + + + SDCDMON + Indicates the SDnCD state + 5 + 5 + read-only + + + 0 + Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.) + #0 + + + 1 + Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.) + #1 + + + + + SDCDIN + SDnCD Card Insertion + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Card insertion not detected + #0 + + + 1 + Card insertion detected + #1 + + + + + SDCDRM + SDnCD Card Removal + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Card removal not detected + #0 + + + 1 + Card removal detected + #1 + + + + + ACEND + Access End + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Access end is not detected + #0 + + + 1 + Access end is detected + #1 + + + + + RSPEND + Response End Detection + 0 + 0 + read-write + + + 0 + Response end is not detected + #0 + + + 1 + Response end is detected + #1 + + + + + + + SD_INFO2 + SD Card Interrupt Flag Register 2 + 0x03C + 32 + read-write + 0x00002000 + 0xFFFFFF7F + + + ILA + Illegal Access Error + 15 + 15 + read-write + zeroToClear + modify + + + 0 + Illegal access error not detected + #0 + + + 1 + Illegal access error detected + #1 + + + + + CBSY + Command Type Register Busy + 14 + 14 + read-only + + + 0 + A command sequence is being executed. + #0 + + + 1 + A command sequence has been completed. + #1 + + + + + SD_CLK_CTRLEN + When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. + 13 + 13 + read-only + + + 0 + The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. + #0 + + + 1 + The SD/MMC bus (CMD, DAT) is not busy. + #1 + + + + + BWE + SD_BUF Write Enable + 9 + 9 + read-write + zeroToClear + modify + + + 1 + Data can be written in SD_BUF0. + #1 + + + 0 + Data cannot be written in SD_BUF0. + #0 + + + + + BRE + SD_BUF Read Enable + 8 + 8 + read-write + zeroToClear + modify + + + 1 + Data can be read from SD_BUF0. + #1 + + + 0 + Data cannot be read from SD_BUF0. + #0 + + + + + SDD0MON + SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. + 7 + 7 + read-only + + + 1 + SDDAT0 is set to 1. + #1 + + + 0 + SDDAT0 is set to 0. + #0 + + + + + RSPTO + Response Timeout + 6 + 6 + read-write + zeroToClear + modify + + + 0 + Response timeout not detected + #0 + + + 1 + Response timeout detected + #1 + + + + + ILR + SD_BUF Illegal Read Access + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Illegal read access to the SD_BUF register not detected + #0 + + + 1 + Illegal read access to the SD_BUF register detected + #1 + + + + + ILW + SD_BUF Illegal Write Access + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Illegal write access to the SD_BUF register not detected + #0 + + + 1 + Illegal write access to the SD_BUF register detected + #1 + + + + + DTO + Data Timeout + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Data timeout not detected + #0 + + + 1 + Data timeout detected + #1 + + + + + ENDE + END Error + 2 + 2 + read-write + zeroToClear + modify + + + 0 + End bit error not detected + #0 + + + 1 + End bit error detected + #1 + + + + + CRCE + CRC Error + 1 + 1 + read-write + zeroToClear + modify + + + 0 + CRC error not detected + #0 + + + 1 + CRC error detected + #1 + + + + + CMDE + Command Error + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Command error not detected + #0 + + + 1 + Command error detected + #1 + + + + + + + SD_INFO1_MASK + SD_INFO1 Interrupt Mask Register + 0x040 + 32 + read-write + 0x0000031D + 0xFFFFFFFF + + + SDD3INM + SDnDAT3 Card Insertion Interrupt Request Mask + 9 + 9 + read-write + + + 0 + SD card insertion interrupt request by the SDnDAT3 is not masked + #0 + + + 1 + SD card insertion interrupt request by the SDnDAT3 is masked + #1 + + + + + SDD3RMM + SDnDAT3 Card Removal Interrupt Request Mask + 8 + 8 + read-write + + + 0 + SD card removal interrupt request by the SDnDAT3 is not masked + #0 + + + 1 + SD card removal interrupt request by the SDnDAT3 is masked + #1 + + + + + SDCDINM + SDnCD card Insertion Interrupt Request Mask + 4 + 4 + read-write + + + 0 + Card insertion interrupt request by the SDnCD is not masked + #0 + + + 1 + Card insertion interrupt request by the SDnCD is masked + #1 + + + + + SDCDRMM + SDnCD card Removal Interrupt Request Mask + 3 + 3 + read-write + + + 0 + Card removal interrupt request by the by the SDnCD is not masked + #0 + + + 1 + Card removal interrupt request by the by the SDnCD is masked + #1 + + + + + ACENDM + Access End Interrupt Request Mask + 2 + 2 + read-write + + + 0 + Access end interrupt request is not masked + #0 + + + 1 + Access end interrupt request is masked + #1 + + + + + RSPENDM + Response End Interrupt Request Mask + 0 + 0 + read-write + + + 0 + Response end interrupt request is not masked + #0 + + + 1 + Response end interrupt request is masked + #1 + + + + + + + SD_INFO2_MASK + SD_INFO2 Interrupt Mask Register + 0x044 + 32 + read-write + 0x00008B7F + 0xFFFFFFFF + + + ILAM + Illegal Access Error Interrupt Request Mask + 15 + 15 + read-write + + + 0 + Illegal access error interrupt request not masked + #0 + + + 1 + Illegal access error interrupt request masked + #1 + + + + + BWEM + BWE Interrupt Request Mask + 9 + 9 + read-write + + + 0 + Write enable interrupt request for the SD_BUF register not masked + #0 + + + 1 + Write enable interrupt request for the SD_BUF register masked + #1 + + + + + BREM + BRE Interrupt Request Mask + 8 + 8 + read-write + + + 0 + Read enable interrupt request for the SD buffer not masked + #0 + + + 1 + Read enable interrupt request for the SD buffer masked + #1 + + + + + RSPTOM + Response Timeout Interrupt Request Mask + 6 + 6 + read-write + + + 0 + Response timeout interrupt request not masked + #0 + + + 1 + Response timeout interrupt request masked + #1 + + + + + ILRM + SD_BUF Register Illegal Read Interrupt Request Mask + 5 + 5 + read-write + + + 0 + Illegal read detection interrupt request for the SD_BUF register not masked + #0 + + + 1 + Illegal read detection interrupt request for the SD_BUF register masked + #1 + + + + + ILWM + SD_BUF Register Illegal Write Interrupt Request Mask + 4 + 4 + read-write + + + 0 + Illegal write detection interrupt request for the SD_BUF register not masked + #0 + + + 1 + Illegal write detection interrupt request for the SD_BUF register masked + #1 + + + + + DTOM + Data Timeout Interrupt Request Mask + 3 + 3 + read-write + + + 0 + Data timeout interrupt request not masked + #0 + + + 1 + Data timeout interrupt request masked + #1 + + + + + ENDEM + End Bit Error Interrupt Request Mask + 2 + 2 + read-write + + + 0 + End bit detection error interrupt request not masked + #0 + + + 1 + End bit detection error interrupt request masked + #1 + + + + + CRCEM + CRC Error Interrupt Request Mask + 1 + 1 + read-write + + + 0 + CRC error interrupt request not masked + #0 + + + 1 + CRC error interrupt request masked + #1 + + + + + CMDEM + Command Error Interrupt Request Mask + 0 + 0 + read-write + + + 0 + Command error interrupt request not masked + #0 + + + 1 + Command error interrupt request masked + #1 + + + + + + + SD_CLK_CTRL + SD Clock Control Register + 0x048 + 32 + read-write + 0x00000020 + 0xFFFFFFFF + + + CLKCTRLEN + SD/MMC Clock Output Automatic Control Enable + 9 + 9 + read-write + + + 0 + Automatic control for SD/MMC Clock output is disabled. + #0 + + + 1 + Automatic control for SD/MMC Clock output is enabled. + #1 + + + + + CLKEN + SD/MMC Clock Output Control Enable + 8 + 8 + read-write + + + 0 + SD/MMC Clock output is disabled. The SDCLK signal is fixed 0. + #0 + + + 1 + SD/MMC Clock output is enabled. + #1 + + + + + CLKSEL + SDHI Clock Frequency Select + 0 + 7 + read-write + + + 0x00 + PCLKA divided by 2 + 0x00 + + + 0x01 + PCLKA divided by 4 + 0x01 + + + 0x02 + PCLKA divided by 8 + 0x02 + + + 0x04 + PCLKA divided by 16 + 0x04 + + + 0x08 + PCLKA divided by 32 + 0x08 + + + 0x10 + PCLKA divided by 64 + 0x10 + + + 0x20 + PCLKA divided by 128 + 0x20 + + + 0x40 + PCLKA divided by 256 + 0x40 + + + 0x80 + PCLKA divided by 512 + 0x80 + + + others + Settings prohibited. + true + + + + + + + SD_SIZE + Transfer Data Length Register + 0x04C + 32 + read-write + 0x00000200 + 0xFFFFFFFF + + + LEN + Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0. + 0 + 9 + read-write + + + + + SD_OPTION + SD Card Access Control Option Register + 0x050 + 32 + read-write + 0x000040EE + 0xFFFFFFFF + + + WIDTH + Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0. + 15 + 15 + read-write + + + 0 + 4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) + #0 + + + 1 + 1-bit width (WIDTH8=0 or 1 ) + #1 + + + + + WIDTH8 + Bus Widthsee b15, WIDTH bit + 13 + 13 + read-write + + + TOUTMASK + Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence. + 8 + 8 + read-write + + + 0 + Activate Timeout + #0 + + + 1 + Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set) + #1 + + + + + TOP + Timeout Counter + 4 + 7 + read-write + + + 1111 + Setting prohibited + #1111 + + + others + SDHI clock x 2^(TOP+13) + true + + + + + CTOP + Card Detect Time Counter + 0 + 3 + read-write + + + 1111 + Setting prohibited + #1111 + + + others + IMCLK x 2^(CTOP+10) + true + + + + + + + SD_ERR_STS1 + SD Error Status Register 1 + 0x058 + 32 + read-only + 0x00002000 + 0xFFFFFFFF + + + CRCTK + CRC Status TokenStore the CRC status token value (normal value is 010b) + 12 + 14 + read-only + + + CRCTKE + CRC Status Token Error + 11 + 11 + read-only + + + 0 + An error has not occured in the CRC status. + #0 + + + 1 + An error has occured in the CRC status. + #1 + + + + + RDCRCE + Read Data CRC Error + 10 + 10 + read-only + + + 0 + CRC error has detected in read data + #0 + + + 1 + CRC error has not detected in read data + #1 + + + + + RSPCRCE1 + Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0. + 9 + 9 + read-only + + + 0 + CRC error has not occured. + #0 + + + 1 + CRC error has occured in the response to a command issued within a command sequence. + #1 + + + + + RSPCRCE0 + Response CRC Error 0NOTE: other than a response to a command issued within a command sequence + 8 + 8 + read-only + + + 0 + A CRC error has not occur in a response + #0 + + + 1 + A CRC error has occured in a response + #1 + + + + + CRCLENE + CRC Status Token Length Error + 5 + 5 + read-only + + + 0 + An error has not occured in the CRC status length. + #0 + + + 1 + An error has occured in the CRC status length (and the end bit has not been detected) + #1 + + + + + RDLENE + Read Data Length Error + 4 + 4 + read-only + + + 0 + An error has occurred not in the read data length. + #0 + + + 1 + An error has occured in the read data length (and the end bit has not been detected among the valid bits). + #1 + + + + + RSPLENE1 + Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0. + 3 + 3 + read-only + + + 0 + An error has not occurred in the response length to a command issued within a command sequence. + #0 + + + 1 + An error has occured in the response length to a command issued within a command sequence. + #1 + + + + + RSPLENE0 + Response Length Error 0NOTE: other than a response to a command issued within a command sequence + 2 + 2 + read-only + + + 0 + An error has not occured in the response length + #0 + + + 1 + An error has occured in the response length + #1 + + + + + CMDE1 + Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0. + 1 + 1 + read-only + + + 0 + An error has not occurs in the command index of the response to a command issued within a command sequence. + #0 + + + 1 + An error has occured in the command index of the response to a command issued within a command sequence. + #1 + + + + + CMDE0 + Command Error 0NOTE: other than a response to a command issued within a command sequence + 0 + 0 + read-only + + + 0 + An error has not occured in the command index of a response. + #0 + + + 1 + An error has occured in the command index of a response. + #1 + + + + + + + SD_ERR_STS2 + SD Error Status Register 2 + 0x05C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + CRCBSYTO + CRC Status Token Busy Timeout + 6 + 6 + read-only + + + 0 + Not timeout + #0 + + + 1 + The busy state continues for longer than N-cycle after the CRC status + #1 + + + + + CRCTO + CRC Status Token Timeout + 5 + 5 + read-only + + + 0 + Not timeout + #0 + + + 1 + The CRC status is not received though a longer time than N-cycle has elapsed after data writing. + #1 + + + + + RDTO + Read Data Timeout + 4 + 4 + read-only + + + 0 + Not timeout + #0 + + + 1 + The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state. + #1 + + + + + BSYTO1 + Busy Timeout 1 + 3 + 3 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0. + #1 + + + + + BSYTO0 + Busy Timeout 0 + 2 + 2 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The busy state for longer than N-cycle continues after R1b response. + #1 + + + + + RSPTO1 + Response Timeout 1 + 1 + 1 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0. + #1 + + + + + RSPTO0 + Response Timeout 0 + 0 + 0 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. + #1 + + + + + + + SD_BUF0 + SD Buffer Register + 0x060 + 32 + read-write + 0x00000000 + 0x00000000 + + + SD_BUF + SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. + 0 + 31 + read-write + + + + + SDIO_MODE + SDIO Mode Control Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + C52PUB + SDIO None AbortNOTE: See manual + 9 + 9 + read-write + + + IOABT + SDIO AbortNOTE: See manual + 8 + 8 + read-write + + + RWREQ + Read Wait Request + 2 + 2 + read-write + + + 0 + Allow SD/MMC to exit read wait state + #0 + + + 1 + Request for SD/MMC to enter read wait state. + #1 + + + + + INTEN + SDIO Mode + 0 + 0 + read-write + + + 1 + Enables the SD host interface to receive SDIO interrupt from the SDIO card + #1 + + + 0 + Disables the SD host interface to receive SDIO interrupt from the SDIO card + #0 + + + + + + + SDIO_INFO1 + SDIO Interrupt Flag Register 1 + 0x06C + 32 + read-write + 0x00000000 + 0xFFFFFFF9 + + + EXWT + EXWT Status FlagNOTE: See manual + 15 + 15 + read-write + zeroToClear + modify + + + EXPUB52 + EXPUB52 Status FlagNOTE: See manual + 14 + 14 + read-write + zeroToClear + modify + + + IOIRQ + SDIO Interrupt Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + SDIO interrupt not accepted + #0 + + + 1 + SDIO interrupt accepted + #1 + + + + + + + SDIO_INFO1_MASK + SDIO_INFO1 Interrupt Mask Register + 0x070 + 32 + read-write + 0x0000C007 + 0xFFFFFFFF + + + EXWTM + EXWT Interrupt Request Mask Control + 15 + 15 + read-write + + + 0 + EXWT interrupt request not masked + #0 + + + 1 + EXWT interrupt request masked + #1 + + + + + EXPUB52M + EXPUB52 Interrupt Request Mask Control + 14 + 14 + read-write + + + 0 + EXPUB52 interrupt request not masked + #0 + + + 1 + EXPUB52 interrupt request masked + #1 + + + + + IOIRQM + IOIRQ Interrupt Mask Control + 0 + 0 + read-write + + + 0 + IOIRQ interrupt not masked + #0 + + + 1 + IOIRQ interrupt masked + #1 + + + + + + + SD_DMAEN + DMA Mode Enable Register + 0x1B0 + 32 + read-write + 0x00001010 + 0xFFFFFFFF + + + DMAEN + SD_BUF Read/Write DMA Transfer + 1 + 1 + read-write + + + 0 + The SD_BUF read/write DMA transfer is disabled. + #0 + + + 1 + The SD_BUF read/write DMA transfer is enabled. + #1 + + + + + + + SOFT_RST + Software Reset Register + 0x1C0 + 32 + read-write + 0x00000007 + 0xFFFFFFFF + + + SDRST + Software Reset of SD I/F Unit + 0 + 0 + read-write + + + 0 + Reset + #0 + + + 1 + Reset released + #1 + + + + + + + SDIF_MODE + SD Interface Mode Setting Register + 0x1CC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NOCHKCR + CRC Check Mask (for MMC test commands) + 8 + 8 + read-write + + + 0 + CRC check is valid + #0 + + + 1 + CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write) + #1 + + + + + + + EXT_SWAP + Swap Control Register + 0x1E0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSWP + SD_BUF0 Swap Read + 7 + 7 + read-write + + + 0 + The current data are read without swapping. + #0 + + + 1 + Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds. + #1 + + + + + BWSWP + SD_BUF0 Swap Write + 6 + 6 + read-write + + + 0 + The current data are written without swapping. + #0 + + + 1 + Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds. + #1 + + + + + + + + + R_SDHI1 + 0x40062400 + + + R_SLCDC + Segment LCD Controller/Driver + 0x40082000 + + 0x00 + 4 + registers + + + 0x100 + 38 + registers + + + + LCDM0 + LCD Mode Register 0 + 0x000 + 8 + read-write + 0x00 + 0xFF + + + MDSET + LCD drive voltage generator selection + 6 + 7 + read-write + + + 00 + External resistance division method + #00 + + + 01 + Internal voltage boosting method + #01 + + + 10 + Capacitor split method + #10 + + + 11 + Setting prohibited + #11 + + + + + LWAVE + LCD display waveform selection + 5 + 5 + read-write + + + 0 + Waveform A + #0 + + + 1 + Waveform B + #1 + + + + + LDTY + Time Slice of LCD Display Select + 2 + 4 + read-write + + + 000 + Static + #000 + + + 001 + 2-time slice + #001 + + + 010 + 3-time slice + #010 + + + 011 + 4-time slice + #011 + + + 101 + 8-time slice + #101 + + + others + Setting prohibited + true + + + + + LBAS + LCD Display Bias Method Select + 0 + 1 + read-write + + + 00 + 1/2 bias method + #00 + + + 01 + 1/3 bias method + #01 + + + 10 + 1/4 bias method + #10 + + + 11 + Setting prohibited + #11 + + + + + + + LCDM1 + LCD Mode Register 1 + 0x001 + 8 + read-write + 0x00 + 0xFF + + + LCDON + LCD Display Enable/Disable + 7 + 7 + read-write + + + 0 + Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1) + #0 + + + 1 + Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1) + #1 + + + + + SCOC + LCD Display Enable/Disable + 6 + 6 + read-write + + + 0 + Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1) + #0 + + + 1 + Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1) + #1 + + + + + VLCON + Voltage boost circuit or capacitor split circuit operation enable/disable + 5 + 5 + read-write + + + 0 + Stops voltage boost circuit or capacitor split circuit operation + #0 + + + 1 + Enables voltage boost circuit or capacitor split circuit operation + #1 + + + + + BLON + Display data area control + 4 + 4 + read-write + + + 0 + Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1) + #0 + + + 1 + Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC)) + #1 + + + + + LCDSEL + Display data area control + 3 + 3 + read-write + + + 0 + Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + #0 + + + 1 + Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + #1 + + + + + Reserved + These bits are read as 00. The write value should be 00. + 1 + 2 + read-write + + + LCDVLM + Voltage Boosting Pin Initial Value Switching Control + 0 + 0 + read-write + + + 0 + Set when VDD >= 2.7 V + #0 + + + 1 + Set when VDD <= 4.2 V + #1 + + + + + + + LCDC0 + LCD Clock Control Register 0 + 0x002 + 8 + read-write + 0x00 + 0xFF + + + LCDC + LCD clock (LCDCL) + 0 + 5 + read-write + + + 000001 + (Sub clock)/22 or (LOCO clock)/22 + #000001 + + + 000010 + (Sub clock)/23 or (LOCO clock)/23 + #000010 + + + 000011 + (Sub clock)/24 or (LOCO clock)/24 + #000011 + + + 000100 + (Sub clock)/25 or (LOCO clock)/25 + #000100 + + + 000101 + (Sub clock)/26 or (LOCO clock)/26 + #000101 + + + 000110 + (Sub clock)/27 or (LOCO clock)/27 + #000110 + + + 000111 + (Sub clock)/28 or (LOCO clock)/28 + #000111 + + + 001000 + (Sub clock)/29 or (LOCO clock)/29 + #001000 + + + 001001 + (Sub clock)/210 or (LOCO clock)/210 + #001001 + + + 010001 + (Main clock)/28 or (HOCO clock)/28 + #010001 + + + 010010 + (Main clock)/29 or (HOCO clock)/29 + #010010 + + + 010011 + (Main clock)/210 or (HOCO clock)/210 + #010011 + + + 010100 + (Main clock)/211 or (HOCO clock)/211 + #010100 + + + 010101 + (Main clock)/212 or (HOCO clock)/212 + #010101 + + + 010110 + (Main clock)/213 or (HOCO clock)/213 + #010110 + + + 010111 + (Main clock)/214 or (HOCO clock)/214 + #010111 + + + 011000 + (Main clock)/215 or (HOCO clock)/215 + #011000 + + + 011001 + (Main clock)/216 or (HOCO clock)/216 + #011001 + + + 011010 + (Main clock)/217 or (HOCO clock)/217 + #011010 + + + 011011 + (Main clock)/218 or (HOCO clock)/218 + #011011 + + + 101011 + (Main clock)/219 or (HOCO clock)/219 + #101011 + + + others + Other than above Setting prohibited + true + + + + + + + VLCD + LCD Boost Level Control Register + 0x003 + 8 + read-write + 0x04 + 0xFF + + + VLCD + Reference Voltage(Contrast Adjustment) Select + 0 + 4 + read-write + + + 00100 + Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method) + #00100 + + + 00101 + Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method) + #00101 + + + 00110 + Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method) + #00110 + + + 00111 + Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method) + #00111 + + + 01000 + Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method) + #01000 + + + 01001 + Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method) + #01001 + + + 01010 + Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method) + #01010 + + + 01011 + Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01011 + + + 01100 + Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01100 + + + 01101 + Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01101 + + + 01110 + Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01110 + + + 01111 + Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01111 + + + 10000 + Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10000 + + + 10001 + Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10001 + + + 10010 + Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10010 + + + 10011 + Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10011 + + + others + Setting prohibited + true + + + + + + + 38 + 0x1 + SEG[%s] + LCD Display Data Array + 0x100 + 8 + read-write + 0x00 + 0xFF + + + A + A-Pattern Area + 0 + 3 + read-write + + + B + B-Pattern Area + 4 + 7 + read-write + + + + + + + R_SPI0 + Serial Peripheral Interface + 0x40072000 + + 0x00000000 + 0x008 + registers + + + 0x0000000A + 0x008 + registers + + + + SPCR + SPI Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + SPRIE + SPI Receive Buffer Full Interrupt Enable + 7 + 7 + read-write + + + 0 + Disables the generation of SPI receive buffer full interrupt requests + #0 + + + 1 + Enables the generation of SPI receive buffer full interrupt requests + #1 + + + + + SPE + SPI Function Enable + 6 + 6 + read-write + + + 0 + Disables the SPI function + #0 + + + 1 + Enables the SPI function + #1 + + + + + SPTIE + Transmit Buffer Empty Interrupt Enable + 5 + 5 + read-write + + + 0 + Disables the generation of transmit buffer empty interrupt requests + #0 + + + 1 + Enables the generation of transmit buffer empty interrupt requests + #1 + + + + + SPEIE + SPI Error Interrupt Enable + 4 + 4 + read-write + + + 0 + Disables the generation of SPI error interrupt requests + #0 + + + 1 + Enables the generation of SPI error interrupt requests + #1 + + + + + MSTR + SPI Master/Slave Mode Select + 3 + 3 + read-write + + + 0 + Slave mode + #0 + + + 1 + Master mode + #1 + + + + + MODFEN + Mode Fault Error Detection Enable + 2 + 2 + read-write + + + 0 + Disables the detection of mode fault error + #0 + + + 1 + Enables the detection of mode fault error + #1 + + + + + TXMD + Communications Operating Mode Select + 1 + 1 + read-write + + + 0 + Full-duplex synchronous serial communications + #0 + + + 1 + Serial communications consisting of only transmit operations + #1 + + + + + SPMS + SPI Mode Select + 0 + 0 + read-write + + + 0 + SPI operation (4-wire method) + #0 + + + 1 + Clock synchronous operation (3-wire method) + #1 + + + + + + + SSLP + SPI Slave Select Polarity Register + 0x01 + 8 + read-write + 0x00 + 0xFF + + + SSL3P + SSL3 Signal Polarity Setting + 3 + 3 + read-write + + + 0 + SSL3 signal is active low + #0 + + + 1 + SSL3 signal is active high + #1 + + + + + SSL2P + SSL2 Signal Polarity Setting + 2 + 2 + read-write + + + 0 + SSL2 signal is active low + #0 + + + 1 + SSL2 signal is active high + #1 + + + + + SSL1P + SSL1 Signal Polarity Setting + 1 + 1 + read-write + + + 0 + SSL1 signal is active low + #0 + + + 1 + SSL1 signal is active high + #1 + + + + + SSL0P + SSL0 Signal Polarity Setting + 0 + 0 + read-write + + + 0 + SSL0 signal is active low + #0 + + + 1 + SSL0 signal is active high + #1 + + + + + + + SPPCR + SPI Pin Control Register + 0x02 + 8 + read-write + 0x00 + 0xFF + + + MOIFE + MOSI Idle Value Fixing Enable + 5 + 5 + read-write + + + 0 + MOSI output value equals final data from previous transfer + #0 + + + 1 + MOSI output value equals the value set in the MOIFV bit + #1 + + + + + MOIFV + MOSI Idle Fixed Value + 4 + 4 + read-write + + + 0 + The level output on the MOSIn pin during MOSI idling corresponds to low. + #0 + + + 1 + The level output on the MOSIn pin during MOSI idling corresponds to high. + #1 + + + + + SPLP2 + SPI Loopback 2 + 1 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Loopback mode (data is not inverted for transmission) + #1 + + + + + SPLP + SPI Loopback + 0 + 0 + read-write + + + 0 + Normal mode + #0 + + + 1 + Loopback mode (data is inverted for transmission) + #1 + + + + + + + SPSR + SPI Status Register + 0x03 + 8 + read-write + 0x20 + 0xFF + + + SPRF + SPI Receive Buffer Full Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No valid data in SPDR + #0 + + + 1 + Valid data found in SPDR + #1 + + + + + SPTEF + SPI Transmit Buffer Empty Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Data found in the transmit buffer + #0 + + + 1 + No data in the transmit buffer + #1 + + + + + UDRF + Underrun Error Flag(When MODF is 0, This bit is invalid.) + 4 + 4 + read-write + zeroToClear + modify + + + 0 + A mode fault error occurs (MODF=1) + #0 + + + 1 + An underrun error occurs (MODF=1) + #1 + + + + + PERF + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurs + #0 + + + 1 + A parity error occurs + #1 + + + + + MODF + Mode Fault Error Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Neither mode fault error nor underrun error occurs + #0 + + + 1 + A mode fault error or an underrun error occurs. + #1 + + + + + IDLNF + SPI Idle Flag + 1 + 1 + read-only + + + 0 + SPI is in the idle state + #0 + + + 1 + SPI is in the transfer state + #1 + + + + + OVRF + Overrun Error Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No overrun error occurs + #0 + + + 1 + An overrun error occurs + #1 + + + + + + + SPDR + SPI Data Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPDR_HA + SPI Data Register ( halfword access ) + SPDR + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + SPDR_BY + SPI Data Register ( byte access ) + SPDR + 0x04 + 8 + read-write + 0x00 + 0xFF + + + SPSCR + SPI Sequence Control Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + Reserved + These bits are read as 00000. The write value should be 00000. + 3 + 7 + read-write + + + SPSLN + RSPI Sequence Length Specification +The order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. + 0 + 2 + read-write + + + 000 + Length 1 SPDMDx x = 0->0->... + #000 + + + 001 + Length 2 SPDMDx x = 0->1->0->... + #001 + + + 010 + Length 3 SPDMDx x = 0->1->2->0->... + #010 + + + 011 + Length 4 SPDMDx x = 0->1->2->3->0->... + #011 + + + 100 + Length 5 SPDMDx x = 0->1->2->3->4->0->... + #100 + + + 101 + Length 6 SPDMDx x = 0->1->2->3->4->5->0->... + #101 + + + 110 + Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... + #110 + + + 111 + Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... + #111 + + + + + + + SPBR + SPI Bit Rate Register + 0x0A + 8 + read-write + 0xFF + 0xFF + + + SPR + SPBR sets the bit rate in master mode. + 0 + 7 + read-write + + + + + SPDCR + SPI Data Control Register + 0x0B + 8 + read-write + 0x00 + 0xFF + + + SPBYT + SPI Byte Access Specification + 6 + 6 + read-write + + + 0 + SPDR is accessed in halfword or word (SPLW is valid) + #0 + + + 1 + SPDR is accessed in byte (SPLW is invalid). + #1 + + + + + SPLW + SPI Word Access/Halfword Access Specification + 5 + 5 + read-write + + + 0 + Set SPDR_HA to valid for halfword access + #0 + + + 1 + Set SPDR to valid for word access. + #1 + + + + + SPRDTD + SPI Receive/Transmit Data Selection + 4 + 4 + read-write + + + 0 + SPDR values are read from the receive buffer + #0 + + + 1 + SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) + #1 + + + + + SPFC + Number of Frames Specification + 0 + 1 + read-write + + + 00 + 1 frame + #00 + + + 01 + 2 frames + #01 + + + 10 + 3 frames + #10 + + + 11 + 4 frames. + #11 + + + + + + + SPCKD + SPI Clock Delay Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + SCKDL + RSPCK Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + #000 + + + 001 + 2 RSPCK + #001 + + + 010 + 3 RSPCK + #010 + + + 011 + 4 RSPCK + #011 + + + 100 + 5 RSPCK + #100 + + + 101 + 6 RSPCK + #101 + + + 110 + 7 RSPCK + #110 + + + 111 + 8 RSPCK + #111 + + + + + + + SSLND + SPI Slave Select Negation Delay Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + SLNDL + SSL Negation Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + #000 + + + 001 + 2 RSPCK + #001 + + + 010 + 3 RSPCK + #010 + + + 011 + 4 RSPCK + #011 + + + 100 + 5 RSPCK + #100 + + + 101 + 6 RSPCK + #101 + + + 110 + 7 RSPCK + #110 + + + 111 + 8 RSPCK + #111 + + + + + + + SPND + SPI Next-Access Delay Register + 0x0E + 8 + read-write + 0x00 + 0xFF + + + SPNDL + SPI Next-Access Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + 2 PCLK + #000 + + + 001 + 2 RSPCK + 2 PCLK + #001 + + + 010 + 3 RSPCK + 2 PCLK + #010 + + + 011 + 4 RSPCK + 2 PCLK + #011 + + + 100 + 5 RSPCK + 2 PCLK + #100 + + + 101 + 6 RSPCK + 2 PCLK + #101 + + + 110 + 7 RSPCK + 2 PCLK + #110 + + + 111 + 8 RSPCK + 2 PCLK + #111 + + + + + + + SPCR2 + SPI Control Register 2 + 0x0F + 8 + read-write + 0x00 + 0xFF + + + SCKASE + RSPCK Auto-Stop Function Enable + 4 + 4 + read-write + + + 0 + Disables the RSPCK auto-stop function + #0 + + + 1 + Enables the RSPCK auto-stop function + #1 + + + + + PTE + Parity Self-Testing + 3 + 3 + read-write + + + 0 + Disables the self-diagnosis function of the parity circuit + #0 + + + 1 + Enables the self-diagnosis function of the parity circuit + #1 + + + + + SPIIE + SPI Idle Interrupt Enable + 2 + 2 + read-write + + + 0 + Disables the generation of idle interrupt requests + #0 + + + 1 + Enables the generation of idle interrupt requests + #1 + + + + + SPOE + Parity Mode + 1 + 1 + read-write + + + 0 + Selects even parity for use in transmission and reception + #0 + + + 1 + Selects odd parity for use in transmission and reception + #1 + + + + + SPPE + Parity Enable + 0 + 0 + read-write + + + 0 + Does not add the parity bit to transmit data and does not check the parity bit of receive data + #0 + + + 1 + Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) + #1 + + + + + + + 8 + 0x02 + SPCMD[%s] + SPI Command Register %s + 0x10 + 16 + read-write + 0x070D + 0xFFFF + + + SCKDEN + RSPCK Delay Setting Enable + 15 + 15 + read-write + + + 0 + An RSPCK delay of 1 RSPCK + #0 + + + 1 + An RSPCK delay is equal to the setting of the SPI clock delay register (SPCKD) + #1 + + + + + SLNDEN + SSL Negation Delay Setting Enable + 14 + 14 + read-write + + + 0 + An SSL negation delay of 1 RSPCK + #0 + + + 1 + An SSL negation delay is equal to the setting of the SPI slave select negation delay register (SSLND) + #1 + + + + + SPNDEN + SPI Next-Access Delay Enable + 13 + 13 + read-write + + + 0 + A next-access delay of 1 RSPCK + 2 PCLK + #0 + + + 1 + A next-access delay is equal to the setting of the SPI next-access delay register (SPND) + #1 + + + + + LSBF + SPI LSB First + 12 + 12 + read-write + + + 0 + MSB first + #0 + + + 1 + LSB first + #1 + + + + + SPB + SPI Data Length Setting + 8 + 11 + read-write + + + 0100 + 8 bits + #0100 + + + 0101 + 8 bits + #0101 + + + 0110 + 8 bits + #0110 + + + 0111 + 8 bits + #0111 + + + 1000 + 9 bits + #1000 + + + 1001 + 10 bits + #1001 + + + 1010 + 11 bits + #1010 + + + 1011 + 12 bits + #1011 + + + 1100 + 13 bits + #1100 + + + 1101 + 14 bits + #1101 + + + 1110 + 15 bits + #1110 + + + 1111 + 16 bits + #1111 + + + others + Setting prohibited + true + + + + + SSLKP + SSL Signal Level Keeping + 7 + 7 + read-write + + + 0 + Negates all SSL signals upon completion of transfer + #0 + + + 1 + Keeps the SSL signal level from the end of transfer until the beginning of the next access + #1 + + + + + SSLA + SSL Signal Assertion Setting + 4 + 6 + read-write + + + 000 + SSL0 + #000 + + + 001 + SSL1 + #001 + + + 010 + SSL2 + #010 + + + 011 + SSL3 + #011 + + + others + Setting prohibited + true + + + + + BRDV + Bit Rate Division Setting + 2 + 3 + read-write + + + 00 + These bits select the base bit rate + #00 + + + 01 + These bits select the base bit rate divided by 2 + #01 + + + 10 + These bits select the base bit rate divided by 4 + #10 + + + 11 + These bits select the base bit rate divided by 8 + #11 + + + + + CPOL + RSPCK Polarity Setting + 1 + 1 + read-write + + + 0 + RSPCK is low when idle + #0 + + + 1 + RSPCK is high when idle + #1 + + + + + CPHA + RSPCK Phase Setting + 0 + 0 + read-write + + + 0 + Data sampling on odd edge, data variation on even edge + #0 + + + 1 + Data variation on odd edge, data sampling on even edge + #1 + + + + + + + SPDCR2 + SPI Data Control Register 2 + 0x20 + 8 + read-write + 0x00 + 0xFF + + + BYSW + Byte Swap Operating Mode Select + 0 + 0 + read-write + + + 0 + Byte Swap Operating Mode disabled + #0 + + + 1 + Byte Swap Operating Mode enabled + #1 + + + + + + + + + R_SPI1 + 0x40072100 + + + R_SRAM + SRAM + 0x40002000 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + 0x000000C0 + 0x005 + registers + + + 0x000000D0 + 0x01 + registers + + + 0x000000D4 + 0x01 + registers + + + 0x000000D8 + 0x01 + registers + + + + PARIOAD + SRAM Parity Error Operation After Detection Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + OAD + Operation after Detection + 0 + 0 + read-write + + + 1 + Reset + #1 + + + 0 + Non maskable interrupt. + #0 + + + + + + + SRAMPRCR + SRAM Protection Register + 0x04 + 8 + read-write + 0x00 + 0xFF + + + KW + Write Key Code + 1 + 7 + write-only + + + 1111000 + Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. + #1111000 + + + others + Writing to the RAMPRCR bit is invalid. + true + + + + + SRAMPRCR + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to protected registers + #0 + + + 1 + Enable writes to protected registers. + #1 + + + + + + + SRAMWTSC + RAM Wait State Control Register + 0x08 + 8 + read-write + 0x0E + 0xFF + + + SRAMHSWTEN + SRAMHS Wait Enable + 4 + 4 + read-write + + + 0 + Not add wait state in read access cycle to SRAMHS + #0 + + + 1 + Add wait state in read access cycle to SRAMHS + #1 + + + + + SRAM1WTEN + SRAM1 Wait Enable + 3 + 3 + read-write + + + 0 + Not add wait state in read access cycle to SRAM1 + #0 + + + 1 + Add wait state in read access cycle to SRAM1 + #1 + + + + + SRAM0WTEN + SRAM0 Wait Enable + 2 + 2 + read-write + + + 0 + Not add wait state in read access cycle to SRAM0 + #0 + + + 1 + Add wait state in read access cycle to SRAM0 + #1 + + + + + ECCRAMRDWTEN + ECCRAM Read wait enable + 1 + 1 + read-write + + + 0 + Not add wait state in read access cycle to SRAM0 (ECC area) + #0 + + + 1 + Add wait state in read access cycle to SRAM0 (ECC area) + #1 + + + + + ECCRAMWRWTEN + ECCRAM Write Wait Enable + 0 + 0 + read-write + + + 0 + Not add wait state in write access cycle to SRAM0 (ECC area) + #0 + + + 1 + Add wait state in write access cycle to SRAM0 (ECC area) + #1 + + + + + + + ECCMODE + ECC Operating Mode Control Register + 0xC0 + 8 + read-write + 0x00 + 0xFF + + + ECCMOD + ECC Operating Mode Select + 0 + 1 + read-write + + + 00 + Disable ECC function + #00 + + + 01 + Setting prohibited + #01 + + + 10 + Enable ECC function without error checking + #10 + + + 11 + Enable ECC function with error checking + #11 + + + + + + + ECC2STS + ECC 2-Bit Error Status Register + 0xC1 + 8 + read-write + 0x00 + 0xFF + + + ECC2ERR + ECC 2-Bit Error Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No 2-bit ECC error occurred + #0 + + + 1 + 2-bit ECC error occurred. + #1 + + + + + + + ECC1STSEN + ECC 1-Bit Error Information Update Enable Register + 0xC2 + 8 + read-write + 0x00 + 0xFF + + + E1STSEN + ECC 1-Bit Error Information Update Enable + 0 + 0 + read-write + + + 0 + Disables updating of the 1-bit ECC error information. + #0 + + + 1 + Enables updating of the 1-bit ECC error information. + #1 + + + + + + + ECC1STS + ECC 1-Bit Error Status Register + 0xC3 + 8 + read-write + 0x00 + 0xFF + + + ECC1ERR + ECC 1-Bit Error Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No 1-bit ECC error occurred + #0 + + + 1 + 1-bit ECC error occurred + #1 + + + + + + + ECCPRCR + ECC Protection Register + 0xC4 + 8 + read-write + 0x00 + 0xFF + + + KW + Write Key Code + 1 + 7 + write-only + + + 1111000 + Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. + #1111000 + + + others + Writing to the ECCRAMPRCR bit is invalid. + true + + + + + ECCPRCR + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to the protected registers + #0 + + + 1 + Enable writes to the protected registers + #1 + + + + + + + ECCPRCR2 + ECC Protection Register 2 + 0xD0 + 8 + read-write + 0x00 + 0xFF + + + KW2 + Write Key Code + 1 + 7 + write-only + + + 1111000 + These bits enable or disable writes to the ECCPRCR2 bit.. + #1111000 + + + others + Writing to the ECCRAMPRCR2 bit is invalid. + true + + + + + ECCPRCR2 + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to the protected registers + #0 + + + 1 + Enable writes to the protected registers. + #1 + + + + + + + ECCETST + ECC Test Control Register + 0xD4 + 8 + read-write + 0x00 + 0xFF + + + TSTBYP + ECC Bypass Select + 0 + 0 + read-write + + + 0 + ECC bypass disabled. + #0 + + + 1 + ECC bypass enabled. + #1 + + + + + + + ECCOAD + SRAM ECC Error Operation After Detection Register + 0xD8 + 8 + read-write + 0x00 + 0xFF + + + OAD + Operation after Detection + 0 + 0 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Reset + #1 + + + + + + + + + R_SRC + Sampling Rate Converter + 0x40048000 + + 0x00000000 + 0x56C0 + registers + + + 0x00005FF0 + 0x010 + registers + + + + 5552 + 0x4 + SRCFCTR[%s] + Filter Coefficient Table [%s] + 0x00 + 32 + read-write + 0x00000000 + 0xFFC00000 + + + SRCFCOE + Stores a filter coefficient value. + 0 + 21 + read-write + + + + + SRCID + Input Data Register + 0x5FF0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SRCID + SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0. + 0 + 31 + write-only + + + + + SRCOD + Output Data Register + 0x5FF4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SRCOD + SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again. + 0 + 31 + read-only + + + + + SRCIDCTRL + Input Data Control Register + 0x5FF8 + 16 + read-write + 0x0000 + 0xFFFF + + + IED + Input Data Endian + 9 + 9 + read-write + + + 0 + Endian formats 1 are the same between the CPU and input data. + #0 + + + 1 + Endian formats 1 are different between the CPU and input data. + #1 + + + + + IEN + Input FIFO Empty Interrupt Enable + 8 + 8 + read-write + + + 0 + Input FIFO empty interrupt is disabled. + #0 + + + 1 + Input FIFO empty interrupt is enabled. + #1 + + + + + IFTRG + Input FIFO Data Triggering Number + 0 + 1 + read-write + + + 00 + 0 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + 6 + #11 + + + + + + + SRCCTRL + Control Register + 0x5FFC + 16 + read-write + 0x0000 + 0xFFFF + + + FICRAE + Filter Coefficient Table Access Enable + 15 + 15 + read-write + + + 0 + Reading/writing to filter coefficient table RAM is disabled. + #0 + + + 1 + Reading/writing to filter coefficient table RAM is enabled. + #1 + + + + + CEEN + Conversion End Interrupt Enable + 13 + 13 + read-write + + + 0 + Disables conversion end interrupt requests. + #0 + + + 1 + Enables conversion end interrupt requests. + #1 + + + + + SRCEN + Module Enable + 12 + 12 + read-write + + + 0 + Disables this module operation. + #0 + + + 1 + Enables this module operation. + #1 + + + + + UDEN + Output Data FIFO Underflow Interrupt Enable + 11 + 11 + read-write + + + 0 + Disables output data FIFO underflow interrupt requests. + #0 + + + 1 + Enables output data FIFO underflow interrupt requests. + #1 + + + + + OVEN + Output Data FIFO Overwrite Interrupt Enable + 10 + 10 + read-write + + + 0 + Output data FIFO overwrite interrupt is disabled. + #0 + + + 1 + Output data FIFO overwrite interrupt is enabled. + #1 + + + + + FL + Internal Work Memory Flush + 9 + 9 + read-write + + + 0 + no effect + #0 + + + 1 + starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing). + #1 + + + + + CL + Internal Work Memory Clear + 8 + 8 + read-write + + + 0 + no effect + #0 + + + 1 + Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator. + #1 + + + + + IFS + Input Sampling Rate + 4 + 7 + read-write + + + 0000 + 8.0 kHz + #0000 + + + 0001 + 11.025 kHz + #0001 + + + 0010 + 12.0 kHz + #0010 + + + 0011 + Setting prohibited + #0011 + + + 0100 + 16.0 kHz + #0100 + + + 0101 + 22.05 kHz + #0101 + + + 0110 + 24.0 kHz + #0110 + + + 0111 + Setting prohibited + #0111 + + + 1000 + 32.0 kHz + #1000 + + + 1001 + 44.1 kHz + #1001 + + + 1010 + 48.0 kHz + #1010 + + + others + Settings prohibited. + true + + + + + OFS + Output Sampling Rate + 0 + 2 + read-write + + + 000 + 44.1 kHz + #000 + + + 001 + 48.0 kHz + #001 + + + 010 + 32.0 kHz + #010 + + + 011 + Setting prohibited + #011 + + + 100 + 8.0 kHz ( Valid only when IFS[3:0] =1001b ) + #100 + + + 101 + 16.0 kHz ( Valid only when IFS[3:0] =1001b ) + #101 + + + others + Settings other than above are prohibited. + true + + + + + + + SRCODCTRL + Output Data Control Register + 0x5FFA + 16 + read-write + 0x0000 + 0xFFFF + + + OCH + Output Data Channel Exchange + 10 + 10 + read-write + + + 0 + Does not exchange the channels (the same order as data input) + #0 + + + 1 + Exchanges the channels (the opposite order from data input) + #1 + + + + + OED + Output Data Endian + 9 + 9 + read-write + + + 0 + Endian formats are the same between the chip and input data. + #0 + + + 1 + Endian formats are different between the chip and input data. + #1 + + + + + OEN + Output Data FIFO Full Interrupt Enable + 8 + 8 + read-write + + + 0 + Output data FIFO full interrupt is disabled. + #0 + + + 1 + Output data FIFO full interrupt is enabled. + #1 + + + + + OFTRG + Output FIFO Data Trigger Number + 0 + 1 + read-write + + + 00 + 1 + #00 + + + 01 + 4 + #01 + + + 10 + 8 + #10 + + + 11 + 12 + #11 + + + + + + + SRCSTAT + Status Register + 0x5FFE + 16 + read-write + 0x0002 + 0xFFFF + + + OFDN + Output FIFO Data CountIndicates the number of data units in the output FIFO. + 11 + 15 + read-write + + + IFDN + Input FIFO Data CountIndicates the number of data units in the input FIFO. + 7 + 10 + read-write + + + CEF + Conversion End Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + All of the output data has not been read out. + #0 + + + 1 + All of the output data has been read out. + #1 + + + + + FLF + Flush Processing Status Flag + 4 + 4 + read-only + + + 0 + Flash processing is completed. + #0 + + + 1 + Flash processing is in progress. + #1 + + + + + UDF + Output FIFO Underflow Interrupt Request Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Output data FIFO has not been read out. + #0 + + + 1 + Output data FIFO has been read out. + #1 + + + + + OVF + Output Data FIFO Overwrite Interrupt Request Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Next data conversion processing is not completed. + #0 + + + 1 + Next data conversion processing is completed. + #1 + + + + + IINT + Input Data FIFO Empty Interrupt Request Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number. + #0 + + + 1 + Number of data units in the input FIFO has become equal to or smaller than the specified triggering number. + #1 + + + + + OINT + Output Data FIFO Full Interrupt Request Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Number of data units in the output FIFO has not become equal to or greater than the specified triggering number. + #0 + + + 1 + Number of data units in the output FIFO has become equal to or greater than the specified triggering number. + #1 + + + + + + + + + R_SSI0 + Serial Sound Interface Enhanced (SSIE) + 0x4004E000 + + 0x00 + 8 + registers + + + 0x10 + 24 + registers + + + + SSICR + Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKS + Oversampling Clock Select + 30 + 30 + read-write + + + 0 + AUDIO_CLK input + #0 + + + 1 + Setting prohibited + #1 + + + + + TUIEN + Transmit Underflow Interrupt Enable + 29 + 29 + read-write + + + 0 + Disables an underflow interrupt. + #0 + + + 1 + Enables an underflow interrupt. + #1 + + + + + TOIEN + Transmit Overflow Interrupt Enable + 28 + 28 + read-write + + + 0 + Disables an overflow interrupt. + #0 + + + 1 + Enables an overflow interrupt. + #1 + + + + + RUIEN + Receive Underflow Interrupt Enable + 27 + 27 + read-write + + + 0 + Disables an underflow interrupt. + #0 + + + 1 + Enables an underflow interrupt. + #1 + + + + + ROIEN + Receive Overflow Interrupt Enable + 26 + 26 + read-write + + + 0 + Disables an overflow interrupt. + #0 + + + 1 + Enables an overflow interrupt. + #1 + + + + + IIEN + Idle Mode Interrupt Enable + 25 + 25 + read-write + + + 0 + Disables an idle mode interrupt. + #0 + + + 1 + Enables an idle mode interrupt. + #1 + + + + + FRM + Channels + 22 + 23 + read-write + + + 00 + One channel + #00 + + + others + Settings other than above are prohibited. + true + + + + + DWL + Data Word Length + 19 + 21 + read-write + + + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 18 bits + #010 + + + 011 + 20 bits + #011 + + + 100 + 22 bits + #100 + + + 101 + 24 bits + #101 + + + others + Settings other than above are prohibited. + true + + + + + SWL + System Word LengthSet the system word length to the bit clock frequency/2 fs. + 16 + 18 + read-write + + + 000 + 8 bits (serial bit clock frequency = 16fs ) + #000 + + + 001 + 16 bits (serial bit clock frequency = 32fs ) + #001 + + + 010 + 24 bits (serial bit clock frequency = 48fs ) + #010 + + + 011 + 32 bits (serial bit clock frequency = 64fs ) + #011 + + + others + Settings other than above are prohibited. + true + + + + + MST + Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited. + 14 + 14 + read-write + + + 0 + Serial word select is input, slave mode. + #0 + + + 1 + Serial word select is output, master mode. + #1 + + + + + BCKP + Serial Bit Clock Polarity + 13 + 13 + read-write + + + 0 + SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). + #0 + + + 1 + SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge). + #1 + + + + + LRCKP + Serial WS Polarity + 12 + 12 + read-write + + + 0 + SSIWS is low for 1st channel, high for 2nd channel. + #0 + + + 1 + SSIWS is high for 1st channel, low for 2nd channel. + #1 + + + + + SPDP + Serial Padding Polarity + 11 + 11 + read-write + + + 0 + Padding bits are low. + #0 + + + 1 + Padding bits are high. + #1 + + + + + SDTA + Serial Data Alignment + 10 + 10 + read-write + + + 0 + Transmitting and receiving in the order of serial data and padding bits + #0 + + + 1 + Transmitting and receiving in the order of padding bits and serial data + #1 + + + + + PDTA + Parallel Data Alignment + 9 + 9 + read-write + + + 0 + The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits) + #0 + + + 1 + The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits) + #1 + + + + + DEL + Serial Data Delay + 8 + 8 + read-write + + + 0 + 1 clock cycle delay between SSIWS and SSIDATA + #0 + + + 1 + No delay between SSIWS and SSIDATA + #1 + + + + + CKDV + Serial Oversampling Clock Division Ratio + 4 + 7 + read-write + + + 0x0 + CLK + 0x0 + + + 0x1 + CLK/2 + 0x1 + + + 0x2 + CLK/4 + 0x2 + + + 0x3 + CLK/8 + 0x3 + + + 0x4 + CLK/16 + 0x4 + + + 0x5 + CLK/32 + 0x5 + + + 0x6 + CLK/64 + 0x6 + + + 0x7 + CLK/128 + 0x7 + + + 0x8 + CLK/6 + 0x8 + + + 0x9 + CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0x9 + + + 0xA + CLK/24 + 0xA + + + 0xB + CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0xB + + + 0xC + CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0xC + + + others + Settings other than above are prohibited. + true + + + + + MUEN + Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing. + 3 + 3 + read-write + + + 0 + This module is not muted. + #0 + + + 1 + This module is muted. + #1 + + + + + TEN + Transmit Enable + 1 + 1 + read-write + + + 0 + Disables the transmit operation. + #0 + + + 1 + Enables the transmit operation. + #1 + + + + + REN + Receive Enable + 0 + 0 + read-write + + + 0 + Disables the receive operation. + #0 + + + 1 + Enables the receive operation. + #1 + + + + + + + SSISR + Status Register + 0x04 + 32 + read-write + 0x02000013 + 0x3E00007F + + + TUIRQ + Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 29 + 29 + read-write + zeroToClear + modify + + + 0 + No transmit underflow has occurred. + #0 + + + 1 + A transmit underflow has occurred. + #1 + + + + + TOIRQ + Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 28 + 28 + read-write + zeroToClear + modify + + + 0 + No transmit overflow has occurred. + #0 + + + 1 + A transmit overflow has occurred. + #1 + + + + + RUIRQ + Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 27 + 27 + read-write + zeroToClear + modify + + + 0 + No receive underflow has occurred. + #0 + + + 1 + A receive underflow has occurred. + #1 + + + + + ROIRQ + Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 26 + 26 + read-write + zeroToClear + modify + + + 0 + No receive overflow has occurred. + #0 + + + 1 + A receive overflow has occurred. + #1 + + + + + IIRQ + Idle Mode Interrupt Status Flag + 25 + 25 + read-only + + + 0 + This module is not in idle state. + #0 + + + 1 + This module is in idle state. + #1 + + + + + TCHNO + Transmit Channel Number + 5 + 6 + read-only + + + TSWNO + Transmit Serial Word Number + 4 + 4 + read-only + + + RCHNO + Receive Channel Number.These bits are read as 00b. + 2 + 3 + read-only + + + RSWNO + Receive Serial Word Number + 1 + 1 + read-only + + + IDST + Idle Mode Status Flag + 0 + 0 + read-only + + + 0 + Serial bus is operating. + #0 + + + 1 + The current communication is stopped. + #1 + + + + + + + SSIFCR + FIFO Control Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AUCKE + Oversampling Clock Enable + 31 + 31 + read-write + + + 0 + The oversampling clock is disabled. + #0 + + + 1 + The oversampling clock is enabled. + #1 + + + + + SSIRST + SSI soft ware reset + 16 + 16 + read-write + + + 0 + Clears the SSI software reset. + #0 + + + 1 + initiates the SSI software reset. + #1 + + + + + TTRG + Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. + 6 + 7 + read-write + + + 00 + 7 (1) + #00 + + + 01 + 6 (2) + #01 + + + 10 + 4 (4) + #10 + + + 11 + 2 (6) + #11 + + + + + RTRG + Receive Data Trigger Number + 4 + 5 + read-write + + + 00 + 1 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + 6 + #11 + + + + + TIE + Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. + 3 + 3 + read-write + + + 0 + Transmit data empty interrupt (TXI) request is disabled + #0 + + + 1 + Transmit data empty interrupt (TXI) request is enabled + #1 + + + + + RIE + Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. + 2 + 2 + read-write + + + 0 + Receive data full interrupt (RXI) request is disabled + #0 + + + 1 + Receive data full interrupt (RXI) request is enabled + #1 + + + + + TFRST + Transmit FIFO Data Register Reset + 1 + 1 + read-write + + + 0 + Clears the transmit data FIFO reset. + #0 + + + 1 + Initiates the transmit data FIFO reset. + #1 + + + + + RFRST + Receive FIFO Data Register Reset + 0 + 0 + read-write + + + 0 + Clears the receive data FIFO reset. + #0 + + + 1 + Initiates the receive data FIFO reset. + #1 + + + + + + + SSIFSR + FIFO Status Register + 0x14 + 32 + read-write + 0x00010000 + 0xFFFFFFFF + + + TDC + Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR) + 24 + 29 + read-only + + + TDE + Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs. + 16 + 16 + read-write + zeroToClear + modify + + + 0 + Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number. + #0 + + + 1 + Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number. + #1 + + + + + RDC + Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR) + 8 + 13 + read-only + + + RDF + Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Number of received data bytes in SSIFRDR is less than the set receive trigger number. + #0 + + + 1 + Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number. + #1 + + + + + + + SSIFTDR + Transmit FIFO Data Register + 0x18 + 32 + write-only + 0x00000000 + 0x00000000 + + + SSIFTDR + SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs. + 0 + 31 + write-only + + + + + SSIFTDR16 + Transmit FIFO Data Register + SSIFTDR + 0x18 + 16 + write-only + 0x00000000 + 0x00000000 + + + SSIFTDR8 + Transmit FIFO Data Register + SSIFTDR + 0x18 + 8 + write-only + 0x00000000 + 0x00000000 + + + SSIFRDR + Receive FIFO Data Register + 0x1C + 32 + read-only + 0x00000000 + 0x00000000 + + + SSIFRDR + SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data. + 0 + 31 + read-only + + + + + SSIFRDR16 + Receive FIFO Data Register + SSIFRDR + 0x1C + 16 + read-only + 0x00000000 + 0x00000000 + + + SSIFRDR8 + Receive FIFO Data Register + SSIFRDR + 0x1C + 8 + read-only + 0x00000000 + 0x00000000 + + + SSIOFR + Audio Format Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCKASTP + Whether to Enable Stopping BCK Output When SSIE is in Idle Status + 9 + 9 + read-write + + + 0 + Always outputs BCK to the SSIBCK pin. + #0 + + + 1 + Automatically controls output of BCK to the SSIBCK pin. + #1 + + + + + LRCONT + Whether to Enable LRCK/FS Continuation + 8 + 8 + read-write + + + 0 + Disables LRCK/FS continuation. + #0 + + + 1 + Enables LRCK/FS continuation. + #1 + + + + + OMOD + Audio Format Select + 0 + 1 + read-write + + + 00 + I2S format + #00 + + + 01 + TDM format + #01 + + + 10 + Monaural format + #10 + + + 11 + Setting prohibited. + #11 + + + + + + + SSISCR + Status Control Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDES + TDE Setting Condition Select + 8 + 12 + read-write + + + 00000 + SSIFTDR has one stage or more free space + #00000 + + + 00001 + SSIFTDR has two stages or more free space (snip) + #00001 + + + 11110 + SSIFTDR has thirty-one stages or more free space + #11110 + + + 11111 + SSIFTDR has thirty-two stages or more free space. + #11111 + + + + + RDFS + RDF Setting Condition Select + 0 + 4 + read-write + + + 00000 + SSIFRDR has one stage or more data size + #00000 + + + 00001 + SSIFRDR has two stages or more data size (snip) + #00001 + + + 11110 + SSIFRDR has thirty-one stages or more data size + #11110 + + + 11111 + SSIFRDR has thirty-two stages or more data size. + #11111 + + + + + + + + + R_SSI1 + Serial Sound Interface Enhanced (SSIE) + 0x4004E100 + + + R_SYSTEM + System Pins + 0x4001E000 + + 0x0000000C + 0x02 + registers + + + 0x0000001C + 0x009 + registers + + + 0x00000026 + 0x01 + registers + + + 0x00000028 + 0x004 + registers + + + 0x00000030 + 0x003 + registers + + + 0x00000036 + 0x01 + registers + + + 0x00000038 + 0x005 + registers + + + 0x0000003E + 0x004 + registers + + + 0x00000050 + 0x01 + registers + + + 0x00000052 + 0x002 + registers + + + 0x00000061 + 0x002 + registers + + + 0x00000092 + 0x01 + registers + + + 0x00000094 + 0x01 + registers + + + 0x00000098 + 0x04 + registers + + + 0x0000009E + 0x003 + registers + + + 0x000000A2 + 0x01 + registers + + + 0x000000A5 + 0x01 + registers + + + 0x000000AA + 0x01 + registers + + + 0x000000C0 + 0x02 + registers + + + 0x000000D1 + 0x01 + registers + + + 0x000000E0 + 0x004 + registers + + + 0x000003FE + 0x02 + registers + + + 0x00000402 + 0x00B + registers + + + 0x0000040E + 0x01 + registers + + + 0x00000410 + 0x002 + registers + + + 0x00000413 + 0x01 + registers + + + 0x00000417 + 0x002 + registers + + + 0x0000041A + 0x002 + registers + + + 0x0000041F + 0x01 + registers + + + 0x00000480 + 0x002 + registers + + + 0x00000490 + 0x01 + registers + + + 0x00000492 + 0x01 + registers + + + 0x000004B0 + 0x003 + registers + + + 0x000004B4 + 0x01 + registers + + + 0x000004B6 + 0x01 + registers + + + 0x000004B8 + 0x008 + registers + + + 0x00000500 + 0x200 + registers + + + + SBYCR + Standby Control Register + 0x00C + 16 + read-write + 0x4000 + 0xFFFF + + + SSBY + Software Standby + 15 + 15 + read-write + + + 0 + Sleep mode + #0 + + + 1 + Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1) + #1 + + + + + OPE + Output Port Enable + 14 + 14 + read-write + + + 0 + In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state. + #0 + + + 1 + In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state.. + #1 + + + + + + + MSTPCRA + Module Stop Control Register A + 0x01C + 32 + read-write + 0xFFBFFF1C + 0xFFFFFFFF + + + MSTPA22 + DMA Controller/Data Transfer Controller Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA7 + Standby RAM Module Stop + 7 + 7 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA6 + ECCRAM Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA5 + High-Speed RAM Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA1 + RAM1 Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA0 + RAM0 Module Stop + 0 + 0 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + SCKDIVCR + System Clock Division Control Register + 0x020 + 32 + read-write + 0x22022222 + 0xFFFFFFFF + + + FCK + Flash IF Clock (FCLK) Select + 28 + 30 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + ICK + System Clock (ICLK) Select + 24 + 26 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + BCK + External Bus Clock (BCLK) Select + 16 + 18 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKA + Peripheral Module Clock A (PCLKA) Select + 12 + 14 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKB + Peripheral Module Clock B (PCLKB) Select + 8 + 10 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKC + Peripheral Module Clock C (PCLKC) Select + 4 + 6 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKD + Peripheral Module Clock D (PCLKD) Select + 0 + 2 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + + + SCKDIVCR2 + System Clock Division Control Register 2 + 0x024 + 8 + read-write + 0x40 + 0xFF + + + UCK + USB Clock (UCLK) Select + 4 + 6 + read-write + + + 010 + /3 + #010 + + + 011 + /4 + #011 + + + 100 + /5 + #100 + + + others + Setting prohibited + true + + + + + + + SCKSCR + System Clock Source Control Register + 0x026 + 8 + read-write + 0x01 + 0xFF + + + CKSEL + Clock Source Select + 0 + 2 + read-write + + + 000 + HOCO + #000 + + + 001 + MOCO + #001 + + + 010 + LOCO + #010 + + + 011 + Main clock oscillator + #011 + + + 100 + Sub-clock oscillator + #100 + + + 101 + PLL + #101 + + + others + Setting prohibited + true + + + + + + + PLLCCR + PLL Clock Control Register + 0x028 + 16 + read-write + 0x1300 + 0xFFFF + + + PLLMUL + PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0 + 8 + 13 + read-write + + + #010011 + #111011 + + + + + others + Setting prohibited + true + + + + + PLSRCSEL + PLL Clock Source Select + 4 + 4 + read-write + + + 0 + Main clock oscillator + #0 + + + 1 + HOCO + #1 + + + + + PLIDIV + PLL Input Frequency Division Ratio Select + 0 + 1 + read-write + + + 00 + /1 + #00 + + + 01 + /2 + #01 + + + 10 + /3 + #10 + + + 11 + Setting prohibited + #11 + + + + + + + PLLCR + PLL Control Register + 0x02A + 8 + read-write + 0x01 + 0xFF + + + PLLSTP + PLL Stop Control + 0 + 0 + read-write + + + 0 + Operate the PLL + #0 + + + 1 + Stop the PLL. + #1 + + + + + + + PLLCCR2 + PLL Clock Control Register2 + 0x02B + 8 + read-write + 0x07 + 0xFF + + + PLODIV + PLL Output Frequency Division Ratio Select + 6 + 7 + read-write + + + 00 + /1. + #00 + + + 01 + /2. + #01 + + + 10 + /4. + #10 + + + 11 + Setting prohibited. + #11 + + + + + PLLMUL + PLL Frequency Multiplication Factor Select + 0 + 4 + read-write + + + 1111 + Settings prohibited. + #1111 + + + others + x PLLMUL[4:0] +1 + true + + + + + + + BCKCR + External Bus Clock Control Register + 0x030 + 8 + read-write + 0x00 + 0xFF + + + BCLKDIV + BCLK Pin Output Select + 0 + 0 + read-write + + + 0 + BCLK + #0 + + + 1 + BCLK/2 + #1 + + + + + + + MEMWAIT + Memory Wait Cycle Control Register + 0x031 + 8 + read-write + 0x00 + 0xFF + + + MEMWAIT + Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz). + 0 + 0 + read-write + + + 0 + no wait + #0 + + + 1 + wait + #1 + + + + + + + MOSCCR + Main Clock Oscillator Control Register + 0x032 + 8 + read-write + 0x01 + 0xFF + + + MOSTP + Main Clock Oscillator Stop + 0 + 0 + read-write + + + 0 + Main clock oscillator is operating. + #0 + + + 1 + Main clock oscillator is stopped. + #1 + + + + + + + HOCOCR + High-Speed On-Chip Oscillator Control Register + 0x036 + 8 + read-write + 0x00 + 0xFE + + + HCSTP + HOCO Stop + 0 + 0 + read-write + + + 0 + Operate the HOCO clock + #0 + + + 1 + Stop the HOCO clock + #1 + + + + + + + MOCOCR + Middle-Speed On-Chip Oscillator Control Register + 0x038 + 8 + read-write + 0x00 + 0xFF + + + MCSTP + MOCO Stop + 0 + 0 + read-write + + + 0 + Operate the MOCO clock + #0 + + + 1 + Stop the MOCO clock + #1 + + + + + + + FLLCR1 + FLL Control Register 1 + 0x039 + 8 + read-write + 0x00 + 0xFF + + + FLLEN + FLL Enable + 0 + 0 + read-write + + + 0 + FLL function is disabled. + #0 + + + 1 + FLL function is enabled. + #1 + + + + + + + FLLCR2 + FLL Control Register 2 + 0x03A + 16 + read-write + 0x0000 + 0xFFFF + + + FLLCNTL + FLL Multiplication ControlMultiplication ratio of the FLL reference clock select + 0 + 10 + read-write + + + + + OSCSF + Oscillation Stabilization Flag Register + 0x03C + 8 + read-only + 0x00 + 0xFE + + + PLLSF + PLL Clock Oscillation Stabilization Flag + 5 + 5 + read-only + + + 0 + PLL clock is stopped or is not yet stable + #0 + + + 1 + PLL clock is stable, so is available for use as the system clock + #1 + + + + + MOSCSF + Main Clock Oscillation Stabilization Flag + 3 + 3 + read-only + + + 0 + Main clock oscillator is stopped (MOSTP = 1) or is not yet stable + #0 + + + 1 + Main clock oscillator is stable, so is available for use as the system clock + #1 + + + + + HOCOSF + HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. + 0 + 0 + read-only + + + 0 + HOCO clock is stopped or is not yet stable + #0 + + + 1 + HOCO clock is stable, so is available for use as the system clock + #1 + + + + + + + CKOCR + Clock Out Control Register + 0x03E + 8 + read-write + 0x00 + 0xFF + + + CKOEN + Clock out enable + 7 + 7 + read-write + + + 0 + Disable clock out + #0 + + + 1 + Enable clock out + #1 + + + + + CKODIV + Clock out input frequency Division Select + 4 + 6 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + 111 + /128 + #111 + + + + + CKOSEL + Clock out source select + 0 + 2 + read-write + + + 000 + HOCO + #000 + + + 001 + MOCO + #001 + + + 010 + LOCO + #010 + + + 011 + MOSC + #011 + + + 100 + SOSC + #100 + + + others + Setting prohibited + true + + + + + + + TRCKCR + Trace Clock Control Register + 0x03F + 8 + read-write + 0x01 + 0xFF + + + TRCKEN + Trace Clock operating Enable + 7 + 7 + read-write + + + 0 + Disable operation + #0 + + + 1 + Enable operation + #1 + + + + + TRCK + Trace Clock operating frequency select + 0 + 3 + read-write + + + 0000 + /1 + #0000 + + + 0001 + /2 + #0001 + + + 0010 + /4 + #0010 + + + others + Setting prohibited + true + + + + + + + OSTDCR + Oscillation Stop Detection Control Register + 0x040 + 8 + read-write + 0x00 + 0xFF + + + OSTDE + Oscillation Stop Detection Function Enable + 7 + 7 + read-write + + + 0 + Disable oscillation stop detection function + #0 + + + 1 + Enable oscillation stop detection function + #1 + + + + + OSTDIE + Oscillation Stop Detection Interrupt Enable + 0 + 0 + read-write + + + 0 + Disable oscillation stop detection interrupt (do not notify the POEG) + #0 + + + 1 + Enable oscillation stop detection interrupt (notify the POEG) + #1 + + + + + + + OSTDSR + Oscillation Stop Detection Status Register + 0x041 + 8 + read-write + 0x00 + 0xFF + + + OSTDF + Oscillation Stop Detection Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Main clock oscillation stop not detected + #0 + + + 1 + Main clock oscillation stop detected + #1 + + + + + + + SLCDSCKCR + Segment LCD Source Clock Control Register + 0x050 + 8 + read-write + 0x00 + 0xFF + + + LCDSCKEN + LCD Source Clock Out Enable + 7 + 7 + read-write + + + 0 + LCD source clock out disabled + #0 + + + 1 + LCD source clock out enabled. + #1 + + + + + LCDSCKSEL + LCD Source Clock (LCDSRCCLK) Select + 0 + 2 + read-write + + + 000 + LOCO + #000 + + + 001 + SOSC + #001 + + + 010 + MOSC + #010 + + + 100 + HOCO + #100 + + + others + Settings other than above are prohibited. + true + + + + + + + EBCKOCR + External Bus Clock Output Control Register + 0x052 + 8 + read-write + 0x00 + 0xFF + + + EBCKOEN + BCLK Pin Output Control + 0 + 0 + read-write + + + 0 + Disable EBCLK pin output (fixed high) + #0 + + + 1 + Enable EBCLK pin output + #1 + + + + + + + SDCKOCR + SDRAM Clock Output Control Register + 0x053 + 8 + read-write + 0x00 + 0xFF + + + SDCKOEN + SDCLK Pin Output Control + 0 + 0 + read-write + + + 0 + Disable SDCLK pin output (fixed high) + #0 + + + 1 + Enable SDCLK pin output + #1 + + + + + + + MOCOUTCR + MOCO User Trimming Control Register + 0x061 + 8 + read-write + 0x00 + 0xFF + + + MOCOUTRM + MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits + 0 + 7 + read-write + + + + + HOCOUTCR + HOCO User Trimming Control Register + 0x062 + 8 + read-write + 0x00 + 0xFF + + + HOCOUTRM + HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits + 0 + 7 + read-write + + + + + SNZCR + Snooze Control Register + 0x092 + 8 + read-write + 0x00 + 0xFF + + + SNZE + Snooze Mode Enable + 7 + 7 + read-write + + + 0 + Disable Snooze Mode + #0 + + + 1 + Enable Snooze Mode + #1 + + + + + SNZDTCEN + DTC Enable in Snooze Mode + 1 + 1 + read-write + + + 0 + Disable DTC operation + #0 + + + 1 + Enable DTC operation + #1 + + + + + RXDREQEN + RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. + 0 + 0 + read-write + + + 0 + Ignore RXD0 falling edge in Standby mode. + #0 + + + 1 + Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. + #1 + + + + + + + SNZEDCR + Snooze End Control Register + 0x094 + 8 + read-write + 0x00 + 0xFF + + + SCI0UMTED + SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode. + 7 + 7 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD1UMTED + AD compare mismatch 1 Snooze End Enable + 6 + 6 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD1MATED + AD compare match 1 Snooze End Enable + 5 + 5 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD0UMTED + AD compare mismatch 0 Snooze End Enable + 4 + 4 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD0MATED + AD compare match 0 Snooze End Enable + 3 + 3 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + DTCNZRED + Not Last DTC transmission completion Snooze End Enable + 2 + 2 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + DTCZRED + Last DTC transmission completion Snooze End Enable + 1 + 1 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AGT1UNFED + AGT1 underflow Snooze End Enable + 0 + 0 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + + + SNZREQCR + Snooze Request Control Register + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SNZREQEN30 + Snooze Request Enable 30Enable AGT1 compare match B snooze request + 30 + 30 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN29 + Snooze Request Enable 29Enable AGT1 compare match A snooze request + 29 + 29 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN28 + Snooze Request Enable 28Enable AGT1 underflow snooze request + 28 + 28 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN25 + Snooze Request Enable 25Enable RTC period snooze request + 25 + 25 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN24 + Snooze Request Enable 24Enable RTC alarm snooze request + 24 + 24 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN23 + Snooze Request Enable 23Enable Comparator-LP0 snooze request + 23 + 23 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN22 + Snooze Request Enable 22Enable Comparator-HS0 snooze request + 22 + 22 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN17 + Snooze Request Enable 17Enable KR snooze request + 17 + 17 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + 16 + 1 + SNZREQEN%s + Snooze Request Enable 0Enable IRQ %s pin snooze request + 0 + 0 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + + + FLSTOP + Flash Operation Control Register + 0x09E + 8 + read-write + 0x00 + 0xFF + + + FLSTPF + Flash Memory Operation Status Flag + 4 + 4 + read-write + + + 0 + Transition completed + #0 + + + 1 + During transition (from the flash-stop-status to flash-operating-status or vice versa) + #1 + + + + + FLSTOP + Selecting ON/OFF of the Flash Memory Operation + 0 + 0 + read-write + + + 0 + Code flash and data flash memory operates + #0 + + + 1 + Code flash and data flash memory stops. + #1 + + + + + + + PSMCR + Power Save Memory Control Register + 0x09F + 8 + read-write + 0x00 + 0xFF + + + PSMC + Power save memory control. + 0 + 1 + read-write + + + 00 + All RAM is on Software Standby mode. + #00 + + + 01 + 48KB RAM is on in Software Standby mode. + #01 + + + others + Setting prohibited. + true + + + + + + + OPCCR + Operating Power Control Register + 0x0A0 + 8 + read-write + 0x00 + 0xFF + + + OPCMTSF + Operating Power Control Mode Transition Status Flag + 4 + 4 + read-only + + + 0 + Transition completed + #0 + + + 1 + During transition + #1 + + + + + OPCM + Operating Power Control Mode Select + 0 + 1 + read-write + + + 00 + High-speed mode + #00 + + + 01 + Prohibited + #01 + + + 10 + Prohibited + #10 + + + 11 + Low-speed mode + #11 + + + others + Setting prohibited + true + + + + + + + SOPCCR + Sub Operating Power Control Register + 0x0AA + 8 + read-write + 0x00 + 0xFF + + + SOPCMTSF + Sub Operating Power Control Mode Transition Status Flag + 4 + 4 + read-only + + + 0 + Transition completed + #0 + + + 1 + During transition + #1 + + + + + SOPCM + Sub Operating Power Control Mode Select + 0 + 0 + read-write + + + 0 + Other than Subosc-speed mode + #0 + + + 1 + Subosc-speed mode + #1 + + + + + + + MOSCWTCR + Main Clock Oscillator Wait Control Register + 0x0A2 + 8 + read-write + 0x05 + 0xFF + + + MSTS + Main clock oscillator wait time setting + 0 + 3 + read-write + + + 0001 + Wait time = 35 cycles (133.5 us) + #0001 + + + 0010 + Wait time = 67 cycles (255.6 us) + #0010 + + + 0011 + Wait time = 131 cycles (499.7 us) + #0011 + + + 0100 + Wait time = 259 cycles (988.0 us) + #0100 + + + 0101 + Wait time = 547 cycles (2086.6 us) (value after reset) + #0101 + + + 0110 + Wait time = 1059 cycles (4039.8 us) + #0110 + + + 0111 + Wait time = 2147 cycles (8190.2 us) + #0111 + + + 1000 + Wait time = 4291 cycles (16368.9 us) + #1000 + + + 1001 + Wait time = 8163 cycles (31139.4 us). + #1001 + + + others + settings prohibited. + true + + + + + + + HOCOWTCR + High-speed on-chip oscillator wait control register + 0x0A5 + 8 + read-write + 0x02 + 0xFF + + + HSTS + HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) + 0 + 2 + read-write + + + + + RSTSR1 + Reset Status Register 1 + 0x0C0 + 16 + read-write + 0x0000 + 0xE0F8 + + + SPERF + SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 12 + 12 + read-write + zeroToClear + modify + + + 0 + SP error reset not detected. + #0 + + + 1 + SP error reset detected. + #1 + + + + + BUSMRF + Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 11 + 11 + read-write + zeroToClear + modify + + + 0 + Bus Master MPU reset not detected. + #0 + + + 1 + Bus Master MPU reset detected. + #1 + + + + + BUSSRF + Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 10 + 10 + read-write + zeroToClear + modify + + + 0 + Bus Slave MPU reset not detected. + #0 + + + 1 + Bus Slave MPU reset detected. + #1 + + + + + REERF + RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 9 + 9 + read-write + zeroToClear + modify + + + 0 + RAM ECC error reset not detected. + #0 + + + 1 + RAM ECC error reset detected. + #1 + + + + + RPERF + RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 8 + 8 + read-write + zeroToClear + modify + + + 0 + RAM parity error reset not detected. + #0 + + + 1 + RAM parity error reset detected. + #1 + + + + + SWRF + Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Software reset not detected. + #0 + + + 1 + Software reset detected. + #1 + + + + + WDTRF + Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Watchdog timer reset not detected. + #0 + + + 1 + Watchdog timer reset detected. + #1 + + + + + IWDTRF + Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Independent watchdog timer reset not detected. + #0 + + + 1 + Independent watchdog timer reset detected. + #1 + + + + + + + STCONR + Standby Condition Register + 0x40F + 8 + read-write + 0xC3 + 0xFF + + + STCON + SSTBY condition bit + 0 + 1 + read-write + + + 00 + set this value in case of transferring to Software Standby Mode in using HOCO. + #00 + + + 11 + set this value in case of transferring to Software Standby Mode in using expect for HOCO. + #11 + + + + + + + 2 + 0x2 + 1,2 + LVD%sCR1 + Voltage Monitor %s Circuit Control Register 1 + 0x0E0 + 8 + read-write + 0x01 + 0xFF + + + IRQSEL + Voltage Monitor Interrupt Type Select + 2 + 2 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Maskable interrupt + #1 + + + + + IDTSEL + Voltage Monitor Interrupt Generation Condition Select + 0 + 1 + read-write + + + 00 + Generate when VCC>=Vdet (rise) is detected + #00 + + + 01 + Generate when VCC<Vdet (drop) is detected + #01 + + + 10 + Generate when drop and rise are detected + #10 + + + 11 + Settings prohibited + #11 + + + + + + + USBCKCR + USB Clock Control Register + 0xD0 + 8 + read-write + 0x00 + 0xFF + + + USBCLKSEL + The USBCLKSEL bit selects the source of the USB clock (UCLK). + 0 + 0 + read-write + + + 0 + PLL + #0 + + + 1 + HOCO + #1 + + + + + + + SDADCCKCR + 24-bit Sigma-Delta A/D Converter Clock Control Register + 0xD1 + 8 + read-write + 0x00 + 0xFF + + + SDADCCKSEL + 24-bit Sigma-Delta A/D Converter Clock Select + 0 + 0 + read-write + + + 0 + MOSC is chosen by a source clock of 24-bit Sigma-Delta A/D Converter Clock. + #0 + + + 1 + HOCO is chosen by a source clock of 24-bit Sigma-Delta AA/D Converter Clock. + #1 + + + + + SDADCCKEN + 24-bit Sigma-Delta A/D Converter Clock Enable + 7 + 7 + read-write + + + 0 + 24-bit Sigma-Delta A/D Converter Clock is disabled + #0 + + + 1 + 24-bit Sigma-Delta A/D Converter Clock is enabled. + #1 + + + + + + + 2 + 0x2 + 1,2 + LVD%sSR + Voltage Monitor %s Circuit Status Register + 0x0E1 + 8 + read-write + 0x02 + 0xFF + + + MON + Voltage Monitor 1 Signal Monitor Flag + 1 + 1 + read-only + + + 0 + VCC < Vdet + #0 + + + 1 + VCC >= Vdet or MON bit is disabled + #1 + + + + + DET + Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Not detected + #0 + + + 1 + Vdet1 passage detection + #1 + + + + + + + PRCR + Protect Register + 0x3FE + 16 + read-write + 0x0000 + 0xFFFF + + + PRKEY + PRKEY Key Code + 8 + 15 + write-only + + + 0x5A + Enables writing to the PRCR register. + 0x5A + + + others + Disables writing to the PRCR register. + true + + + + + PRC3 + Enables writing to the registers related to the LVD. + 3 + 3 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + PRC1 + Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function. + 1 + 1 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + PRC0 + Enables writing to the registers related to the clock generation circuit. + 0 + 0 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + + + DPSIER0 + Deep Standby Interrupt Enable Register 0 + 0x402 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sE + IRQ-DS Pin Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER1 + Deep Standby Interrupt Enable Register 1 + 0x403 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + 8-15 + DIRQ%sE + IRQ-DS Pin Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER2 + Deep Standby Interrupt Enable Register 2 + 0x404 + 8 + read-write + 0x00 + 0xFF + + + DNMIE + NMI Pin Enable + 4 + 4 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DRTCAIE + RTC Alarm interrupt Deep Standby Cancel Signal Enable + 3 + 3 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DTRTCIIE + RTC Interval interrupt Deep Standby Cancel Signal Enable + 2 + 2 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DLVD2IE + LVD2 Deep Standby Cancel Signal Enable + 1 + 1 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DLVD1IE + LVD1 Deep Standby Cancel Signal Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER3 + Deep Standby Interrupt Enable Register 3 + 0x405 + 8 + read-write + 0x00 + 0xFF + + + DAGT1IE + AGT1 Underflow Deep Standby Cancel Signal Enable + 2 + 2 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DUSBHSIE + USBHS Suspend/Resume Deep Standby Cancel Signal Enable + 1 + 1 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DUSBFSIE + USBFS Suspend/Resume Deep Standby Cancel Signal Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIFR0 + Deep Standby Interrupt Flag Register 0 + 0x406 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sF + IRQ-DS Pin Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR1 + Deep Standby Interrupt Flag Register 1 + 0x407 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + 8-15 + DIRQ%sF + IRQ-DS Pin Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR2 + Deep Standby Interrupt Flag Register 2 + 0x408 + 8 + read-write + 0x00 + 0xFF + + + DNMIF + NMI Pin Deep Standby Cancel Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DRTCAIF + RTC Alarm interrupt Deep Standby Cancel Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DTRTCIIF + RTC Interval interrupt Deep Standby Cancel Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DLVD2IF + LVD2 Deep Standby Cancel Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DLVD1IF + LVD1 Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR3 + Deep Standby Interrupt Flag Register 3 + 0x409 + 8 + read-write + 0x00 + 0xFF + + + DAGT1IF + AGT1 Underflow Deep Standby Cancel Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DUSBHSIF + USBHS Suspend/Resume Deep Standby Cancel Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DUSBFSIF + USBFS Suspend/Resume Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + 2 + 1 + DPSIEGR%s + Deep Standby Interrupt Edge Register %s + 0x40A + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sEG + IRQ-DS Pin Edge Select + 0 + 0 + read-write + + + 0 + A cancel request is generated at a falling edge + #0 + + + 1 + A cancel request is generated at a rising edge + #1 + + + + + + + DPSIEGR2 + Deep Standby Interrupt Edge Register 2 + 0x40C + 8 + read-write + 0x00 + 0xFF + + + DNMIEG + NMI Pin Edge Select + 4 + 4 + read-write + + + 0 + A cancel request is generated at a falling edge + #0 + + + 1 + A cancel request is generated at a rising edge + #1 + + + + + DLVD2IEG + LVD2 Edge Select + 1 + 1 + read-write + + + 0 + A cancel request is generated when VCC<Vdet2 (fall) is detected + #0 + + + 1 + A cancel request is generated when VCC>=Vdet2 (rise) is detected + #1 + + + + + DLVD1IEG + LVD1 Edge Select + 0 + 0 + read-write + + + 0 + A cancel request is generated when VCC<Vdet1 (fall) is detected + #0 + + + 1 + A cancel request is generated when VCC>=Vdet1 (rise) is detected + #1 + + + + + + + DPSBYCR + Deep Standby Control Register + 0x400 + 8 + read-write + 0x01 + 0xFF + + + DPSBY + Deep Software Standby + 7 + 7 + read-write + + + 0 + Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) + #0 + + + 1 + Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) + #1 + + + + + IOKEEP + I/O Port Retention + 6 + 6 + read-write + + + 0 + When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. + #0 + + + 1 + When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. + #1 + + + + + DEEPCUT + Power-Supply Control + 0 + 1 + read-write + + + 00 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. + #00 + + + 01 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode. + #01 + + + 10 + Setting prohibited. + #10 + + + 11 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. + #11 + + + + + + + SYOCDCR + System Control OCD Control Register + 0x40E + 8 + read-write + 0x00 + 0xFE + + + DBGEN + Debugger Enable bit + 7 + 7 + read-write + + + 0 + On-chip debugger is disabled + #0 + + + 1 + On-chip debugger is enabled + #1 + + + + + DOCDF + Deep Standby OCD flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + On-chip debugger is disabled + #0 + + + 1 + On-chip debugger is enabled + #1 + + + + + + + MOMCR + Main Clock Oscillator Mode Oscillation Control Register + 0x413 + 8 + read-write + 0x00 + 0xFF + + + AUTODRVEN + Main Clock Oscillator Drive Capability Auto Switching Enable + 7 + 7 + read-write + + + 0 + Disable + #0 + + + 1 + Enable. + #1 + + + + + MOSEL + Main Clock Oscillator Switching + 6 + 6 + read-write + + + 0 + Resonator + #0 + + + 1 + External clock input + #1 + + + + + MODRV0 + Main Clock Oscillator Drive Capability 0 Switching + 4 + 5 + read-write + + + 00 + 20MHz to 24MHz + #00 + + + 01 + 16MHz to 20MHz + #01 + + + 10 + 8MHz to 16MHz + #10 + + + 11 + 8MHz + #11 + + + + + MODRV1 + Main Clock Oscillator Drive Capability 1 Switching + 3 + 3 + read-write + + + 0 + 10 MHz to 20 MHz + #0 + + + 1 + 1 MHz to 10 MHz. + #1 + + + + + + + RSTSR0 + Reset Status Register 0 + 0x410 + 8 + read-write + 0x00 + 0x70 + + + DPSRSTF + Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Deep software standby mode cancelation not requested by an interrupt. + #0 + + + 1 + Deep software standby mode cancelation requested by an interrupt. + #1 + + + + + LVD2RF + Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 2 reset not detected. + #0 + + + 1 + Voltage Monitor 2 reset detected. + #1 + + + + + LVD1RF + Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 1 reset not detected. + #0 + + + 1 + Voltage Monitor 1 reset detected. + #1 + + + + + LVD0RF + Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 0 reset not detected. + #0 + + + 1 + Voltage Monitor 0 reset detected. + #1 + + + + + PORF + Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Power-on reset not detected. + #0 + + + 1 + Power-on reset detected. + #1 + + + + + + + RSTSR2 + Reset Status Register 2 + 0x411 + 8 + read-write + 0x00 + 0xFE + + + CWSF + Cold/Warm Start Determination Flag + 0 + 0 + read-write + oneToSet + modify + + + 0 + Cold start + #0 + + + 1 + Warm start + #1 + + + + + + + LVCMPCR + Voltage Monitor Circuit Control Register + 0x417 + 8 + read-write + 0x00 + 0xFF + + + LVD2E + Voltage Detection 2 Enable + 6 + 6 + read-write + + + 0 + Voltage detection 2 circuit disabled + #0 + + + 1 + Voltage detection 2 circuit enabled + #1 + + + + + LVD1E + Voltage Detection 1 Enable + 5 + 5 + read-write + + + 0 + Voltage detection 1 circuit disabled + #0 + + + 1 + Voltage detection 1 circuit enabled + #1 + + + + + + + LVDLVLR + Voltage Detection Level Select Register + 0x418 + 8 + read-write + 0xF3 + 0xFF + + + LVD2LVL + Voltage Detection 2 Level Select (Standard voltage during fall in voltage) + 5 + 7 + read-write + + + 101 + 2.99V (Vdet2_1) + #101 + + + 110 + 2.92V (Vdet2_2) + #110 + + + 111 + 2.85V (Vdet2_3) + #111 + + + others + Settings other than above are prohibited. + true + + + + + LVD1LVL + Voltage Detection 1 Level Select (Standard voltage during fall in voltage) + 0 + 4 + read-write + + + 10001 + 2.99V (Vdet1_1) + #10001 + + + 10010 + 2.92V (Vdet1_2) + #10010 + + + 10011 + 2.85V (Vdet1_3) + #10011 + + + others + Settings other than above are prohibited. + true + + + + + + + 2 + 0x1 + 1,2 + LVD%sCR0 + Voltage Monitor %s Circuit Control Register 0 + 0x41A + 8 + read-write + 0x8A + 0xF7 + + + RN + Voltage Monitor Reset Negate Select + 7 + 7 + read-write + + + 0 + Negation follows a stabilization time (tLVD) after VCC > Vdet is detected. + #0 + + + 1 + Negation follows a stabilization time (tLVD) after assertion of the LVD reset. + #1 + + + + + RI + Voltage Monitor Circuit Mode Select + 6 + 6 + read-write + + + 0 + Voltage Monitor interrupt during Vdet1 passage + #0 + + + 1 + Voltage Monitor reset enabled when the voltage falls to and below Vdet1 + #1 + + + + + FSAMP + Sampling Clock Select + 4 + 5 + read-write + + + 00 + 1/2 LOCO frequency + #00 + + + 01 + 1/4 LOCO frequency + #01 + + + 10 + 1/8 LOCO frequency + #10 + + + 11 + 1/16 LOCO frequency + #11 + + + + + CMPE + Voltage Monitor Circuit Comparison Result Output Enable + 2 + 2 + read-write + + + 0 + Disable voltage monitor 1 circuit comparison result output + #0 + + + 1 + Enable voltage monitor 1 circuit comparison result output. + #1 + + + + + DFDIS + Voltage Monitor Digital Filter Disable Mode Select + 1 + 1 + read-write + + + 0 + Enable digital filter + #0 + + + 1 + Disable digital filter + #1 + + + + + RIE + Voltage Monitor Interrupt/Reset Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + VBTCR1 + VBATT Control Register1 + 0x41F + 8 + read-write + 0x00 + 0xFF + + + BPWSWSTP + Battery Power supply Switch Stop + 0 + 0 + read-write + + + 0 + Battery Power supply Switch Enable + #0 + + + 1 + Battery Power supply Switch stop + #1 + + + + + + + SOSCCR + Sub-Clock Oscillator Control Register + 0x480 + 8 + read-write + 0x01 + 0xFF + + + SOSTP + Sub-Clock Oscillator Stop + 0 + 0 + read-write + + + 0 + Sub-clock oscillator is operating. + #0 + + + 1 + Sub-clock oscillator is stopped. + #1 + + + + + + + SOMCR + Sub Clock Oscillator Mode Control Register + 0x481 + 8 + read-write + 0x00 + 0xFF + + + SODRV + Sub-Clock Oscillator Drive Capability Switching + 0 + 1 + read-write + + + 00 + Normal mode + #00 + + + 01 + Low power mode 1 + #01 + + + 10 + Low power mode 2 + #10 + + + 11 + Low power mode 3. + #11 + + + + + + + LOCOCR + Low-Speed On-Chip Oscillator Control Register + 0x490 + 8 + read-write + 0x00 + 0xFF + + + LCSTP + LOCO Stop + 0 + 0 + read-write + + + 0 + LOCO is operating. + #0 + + + 1 + LOCO is stopped. + #1 + + + + + + + LOCOUTCR + LOCO User Trimming Control Register + 0x492 + 8 + read-write + 0x00 + 0xFF + + + LOCOUTRM + LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits + 0 + 7 + read-write + + + + + VBTCR2 + VBATT Control Register2 + 0x4B0 + 8 + read-write + 0x00 + 0xFF + + + VBTLVDLVL + VBATT Pin Voltage Low Voltage Detect Level Select Bit + 6 + 7 + read-write + + + 00 + 2.7V + #00 + + + 01 + Setting prohibited + #01 + + + 10 + 2.3V + #10 + + + 11 + 2.1V + #11 + + + + + VBTLVDEN + VBATT Pin Low Voltage Detect Enable Bit + 4 + 4 + read-write + + + 0 + VBATT pin low voltage detect disable + #0 + + + 1 + VBATT pin low voltage detect enable + #1 + + + + + + + VBTSR + VBATT Status Register + 0x4B1 + 8 + read-write + 0x01 + 0xEC + + + VBTRVLD + VBATT_R Valid + 4 + 4 + read-only + + + 0 + VBATT_R area not valid + #0 + + + 1 + VBATT_R area valid + #1 + + + + + VBTBLDF + VBATT Battery Low voltage Detect Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + VBATT pin low voltage not detected + #0 + + + 1 + VBATT pin low voltage detected. + #1 + + + + + VBTRDF + VBAT_R Reset Detect Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + VBATT_R voltage power-on reset not detected + #0 + + + 1 + VBATT_R selected voltage power-on reset detected. + #1 + + + + + + + VBTCMPCR + VBATT Comparator Control Register + 0x4B2 + 8 + read-write + 0x00 + 0xFF + + + VBTCMPE + VBATT pin low voltage detect circuit output enable + 0 + 0 + read-write + + + 0 + VBATT pin low voltage detect circuit output disabled + #0 + + + 1 + VBATT pin low voltage detect circuit output enabled + #1 + + + + + + + VBTLVDICR + VBATT Pin Low Voltage Detect Interrupt Control Register + 0x4B4 + 8 + read-write + 0x00 + 0xFF + + + VBTLVDISEL + Pin Low Voltage Detect Interrupt Select bit + 1 + 1 + read-write + + + 0 + Non Maskable Interrupt + #0 + + + 1 + Maskable Interrupt + #1 + + + + + VBTLVDIE + VBATT Pin Low Voltage Detect Interrupt Enable bit + 0 + 0 + read-write + + + 0 + VBATT Pin Low Voltage Detect Interrupt Disable + #0 + + + 1 + VBATT Pin Low Voltage Detect Interrupt Enable + #1 + + + + + + + VBTWCTLR + VBATT Wakeup function Control Register + 0x4B6 + 8 + read-write + 0x00 + 0xFF + + + VWEN + VBATT wakeup enable + 0 + 0 + read-write + + + 0 + Disable Wakeup function + #0 + + + 1 + Enable Wakeup function + #1 + + + + + + + VBTWCH0OTSR + VBATT Wakeup I/O 0 Output Trigger Select Register + 0x4B8 + 8 + read-write + 0x00 + 0xFF + + + CH0VAGTUTE + CH0 Output AGT(ch1) underflow Signal Enable + 5 + 5 + read-write + + + 0 + VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is disabled + #0 + + + 1 + VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is enabled + #1 + + + + + CH0VRTCATE + VBATWIO0 Output RTC Alarm Signal Enable + 4 + 4 + read-write + + + 0 + VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled + #0 + + + 1 + VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled. + #1 + + + + + CH0VRTCTE + VBATWIO0 Output RTC Periodic Signal Enable + 3 + 3 + read-write + + + 0 + VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled + #0 + + + 1 + VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled. + #1 + + + + + CH0VCH2TE + VBATWIO0 Output VBATWIO2 Trigger Enable + 2 + 2 + read-write + + + 0 + VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled. + #1 + + + + + CH0VCH1TE + VBATWIO0 Output VBATWIO1 Trigger Enable + 1 + 1 + read-write + + + 0 + VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled. + #1 + + + + + + + VBTWCH1OTSR + VBATT Wakeup I/O 1 Output Trigger Select Register + 0x4B9 + 8 + read-write + 0x00 + 0xFF + + + CH1VAGTUTE + CH1 Output AGT(ch1) underflow Signal Enable + 5 + 5 + read-write + + + 0 + VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is disabled + #0 + + + 1 + VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is enabled + #1 + + + + + CH1VRTCATE + VBATWIO1 Output RTC Alarm Signal Enable + 4 + 4 + read-write + + + 0 + VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled + #0 + + + 1 + VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled. + #1 + + + + + CH1VRTCTE + VBATWIO1 Output RTC Periodic Signal Enable + 3 + 3 + read-write + + + 0 + VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled + #0 + + + 1 + VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled + #1 + + + + + CH1VCH2TE + VBATWIO1 Output VBATWIO2 Trigger Enable + 2 + 2 + read-write + + + 0 + VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled. + #1 + + + + + CH1VCH0TE + VBATWIO1 Output VBATWIO0 Trigger Enable + 0 + 0 + read-write + + + 0 + VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. + #1 + + + + + + + VBTWCH2OTSR + VBATT Wakeup I/O 2 Output Trigger Select Register + 0x4BA + 8 + read-write + 0x00 + 0xFF + + + CH2VAGTUTE + CH2 Output AGT(CH2) underflow Signal Enable + 5 + 5 + read-write + + + 0 + VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is disabled + #0 + + + 1 + VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is enabled + #1 + + + + + CH2VRTCATE + VBATWIO2 Output RTC Alarm Signal Enable + 4 + 4 + read-write + + + 0 + VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled + #0 + + + 1 + VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled. + #1 + + + + + CH2VRTCTE + VBATWIO2 Output RTC Periodic Signal Enable + 3 + 3 + read-write + + + 0 + VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled + #0 + + + 1 + VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled. + #1 + + + + + CH2VCH1TE + VBATWIO2 Output VBATWIO1 Trigger Enable + 1 + 1 + read-write + + + 0 + VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled. + #1 + + + + + CH2VCH0TE + VBATWIO2 Output VBATWIO0 Trigger Enable + 0 + 0 + read-write + + + 0 + VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled + #0 + + + 1 + VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled. + #1 + + + + + + + VBTICTLR + VBATT Input Control Register + 0x4BB + 8 + read-write + 0x00 + 0xF8 + + + VCH2INEN + RTCIC2 Input Enable + 2 + 2 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + VCH1INEN + RTCIC1 Input Enable + 1 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + VCH0INEN + RTCIC0 Input Enable + 0 + 0 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + VBTOCTLR + VBATT Output Control Register + 0x4BC + 8 + read-write + 0x00 + 0xFF + + + VOUT2LSEL + VBATT Wakeup I/O 2 Output Level Selection + 5 + 5 + read-write + + + 0 + Output L before VBATT wake up trigger + #0 + + + 1 + Output H before VBATT wake up trigger + #1 + + + + + VCOU1LSEL + VBATT Wakeup I/O 1 Output Level Selection + 4 + 4 + read-write + + + 0 + Output L before VBATT wake up trigger + #0 + + + 1 + Output H before VBATT wake up trigger + #1 + + + + + VOUT0LSEL + VBATT Wakeup I/O 0 Output Level Selection + 3 + 3 + read-write + + + 0 + Output L before VBATT wakeup trigger + #0 + + + 1 + Output H before VBATT wakeup trigger + #1 + + + + + VCH2OEN + VBATT Wakeup I/O 2 Output Enable + 2 + 2 + read-write + + + 0 + VBATWIO2 output disabled + #0 + + + 1 + VBATWIO2 output enabled + #1 + + + + + VCH1OEN + VBATT Wakeup I/O 1 Output Enable + 1 + 1 + read-write + + + 0 + VBATWIO1 output disabled + #0 + + + 1 + VBATWIO1 output enabled + #1 + + + + + VCH0OEN + VBATT Wakeup I/O 0 Output Enable + 0 + 0 + read-write + + + 0 + VBATWIO0 output disabled + #0 + + + 1 + VBATWIO0 output enabled + #1 + + + + + + + VBTWTER + VBATT Wakeup Trigger source Enable Register + 0x4BD + 8 + read-write + 0x00 + 0xFF + + + VAGTUE + AGT(ch1) underflow Signal Enable + 5 + 5 + read-write + + + 0 + VBATT wakeup triggered by the AGT(ch1) underflow signal is disabled + #0 + + + 1 + VBATT wakeup triggered by the AGT(ch1) underflow signal is enabled + #1 + + + + + VRTCAE + RTC Alarm Signal Enable + 4 + 4 + read-write + + + 0 + VBATT wakeup triggered by RTC alarm signal is disabled + #0 + + + 1 + VBATT wakeup triggered by RTC alarm signal is enabled. + #1 + + + + + VRTCIE + RTC Periodic Signal Enable + 3 + 3 + read-write + + + 0 + VBATT wakeup triggered by RTC periodic signal is disabled + #0 + + + 1 + VBATT wakeup triggered by RTC periodic signal is enabled. + #1 + + + + + VCH2E + VBATWIO2 Pin Enable + 2 + 2 + read-write + + + 0 + VBATT wakeup triggered by the VBATWIO2 pin is disabled + #0 + + + 1 + VBATT wakeup triggered by the VBATWIO2 pin is enabled. + #1 + + + + + VCH1E + VBATWIO1 Pin Enable + 1 + 1 + read-write + + + 0 + VBATT wakeup triggered by the VBATWIO1 pin is disabled + #0 + + + 1 + VBATT wakeup triggered by the VBATWIO1 pin is enabled. + #1 + + + + + VCH0E + VBATWIO0 Pin Enable + 0 + 0 + read-write + + + 0 + VBATT wakeup triggered by the VBATWIO0 pin is disabled + #0 + + + 1 + VBATT wakeup triggered by the VBATWIO0 pin is enabled. + #1 + + + + + + + VBTWEGR + VBATT Wakeup Trigger source Edge Register + 0x4BE + 8 + read-write + 0x00 + 0xFF + + + VCH2EG + VBATWIO2 Wakeup Trigger Source Edge Select + 2 + 2 + read-write + + + 0 + Wakeup trigger is generated at a falling edge + #0 + + + 1 + Wakeup trigger is generated at a rising edge. + #1 + + + + + VCH1EG + VBATWIO1 Wakeup Trigger Source Edge Select + 1 + 1 + read-write + + + 0 + Wakeup trigger is generated at a falling edge + #0 + + + 1 + Wakeup trigger is generated at a rising edge. + #1 + + + + + VCH0EG + VBATWIO0 Wakeup Trigger Source Edge Select + 0 + 0 + read-write + + + 0 + Wakeup trigger is generated at a falling edge + #0 + + + 1 + Wakeup trigger is generated at a rising edge. + #1 + + + + + + + VBTWFR + VBATT Wakeup trigger source Flag Register + 0x4BF + 8 + read-write + 0x00 + 0xFF + + + VAGTUF + AGT(ch1) underflow VBATT Wakeup Trigger Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the AGT(ch1) underflow is generated + #0 + + + 1 + A wakeup trigger by the AGT(ch1) underflow is generated + #1 + + + + + VRTCAF + VBATT RTC-Alarm Wakeup Trigger Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the RTC alarm is generated + #0 + + + 1 + A wakeup trigger by the RTC alarm is generated + #1 + + + + + VRTCIF + VBATT RTC-Interval Wakeup Trigger Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the RTC interval is generated + #0 + + + 1 + A wakeup trigger by the RTC interval is generated + #1 + + + + + VCH2F + VBATWIO2 Wakeup Trigger Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the VBATWIO2 pin is generated + #0 + + + 1 + A wakeup trigger by the VBATWIO2 pin is generated + #1 + + + + + VCH1F + VBATWIO1 Wakeup Trigger Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the VBATWIO1 pin is generated + #0 + + + 1 + A wakeup trigger by the VBATWIO1 pin is generated + #1 + + + + + VCH0F + VBATWIO0 Wakeup Trigger Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No wakeup trigger by the VBATWIO0 pin is generated + #0 + + + 1 + A wakeup trigger by the VBATWIO0 pin is generated + #1 + + + + + + + 512 + 0x1 + VBTBKR[%s] + VBATT Backup Register [%s] + 0x500 + 8 + read-write + 0x00 + 0x00 + + + VBTBKR + VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. + 0 + 7 + read-write + + + + + FWEPROR + Flash P/E Protect Register + 0x416 + 8 + read-write + 0x02 + 0xFF + + + FLWE + Flash Programming and Erasure + 0 + 1 + read-write + + + 00 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #00 + + + 01 + Permits programming and erasure of the code flash, data flash or blank checking. + #01 + + + 10 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #10 + + + 11 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #11 + + + + + + + + + R_TSN + Temperature Sensor + 0x407EC000 + + 0x00000228 + 0x002 + registers + + + + TSCDRH + Temperature Sensor Calibration Data Register H + 0x229 + 8 + read-only + 0x00 + 0x00 + + + TSCDRH + The calibration data stores the higher 8 bits of the convertedvalue. + 0 + 7 + read-only + + + + + TSCDRL + Temperature Sensor Calibration Data Register L + 0x228 + 8 + read-only + 0x00 + 0x00 + + + TSCDRL + The calibration data stores the lower 8 bits of the convertedvalue. + 0 + 7 + read-only + + + + + + + R_TSN_CTRL + Temperature Sensor + 0x4005D000 + + 0x00 + 1 + registers + + + + TSCR + Temperature Sensor Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + TSEN + Temperature Sensor Output Enable + 7 + 7 + read-write + + + 0 + Stops the temperature sensor. + #0 + + + 1 + Starts the temperature sensor. + #1 + + + + + TSOE + Temperature Sensor Enable + 4 + 4 + read-write + + + 0 + Disables output from the temperature sensor to the 12-bit A/D converter. + #0 + + + 1 + Enables output from the temperature sensor to the 12-bit A/D converter. + #1 + + + + + + + + + R_USB_FS0 + USB 2.0 Module + 0x40090000 + + 0x00000000 + 0x00A + registers + + + 0x0000000C + 0x02 + registers + + + 0x00000014 + 0x010 + registers + + + 0x00000028 + 0x00C + registers + + + 0x00000036 + 0x00E + registers + + + 0x00000046 + 0x00C + registers + + + 0x00000054 + 0x00E + registers + + + 0x00000064 + 0x02 + registers + + + 0x00000068 + 0x02 + registers + + + 0x0000006C + 0x016 + registers + + + 0x00000090 + 0x014 + registers + + + 0x000000B0 + 0x02 + registers + + + 0x000000C4 + 0x02 + registers + + + 0x000000CC + 0x02 + registers + + + 0x000000D0 + 0x014 + registers + + + 0x000000F0 + 0x04 + registers + + + 0x00000100 + 0x004 + registers + + + 0x00000140 + 0x02 + registers + + + 0x00000144 + 0x008 + registers + + + 0x00000160 + 0x00C + registers + + + 0x00000400 + 0x008 + registers + + + + 5 + 0x004 + PIPE_TR[%s] + Pipe Transaction Counter Registers + 0x090 + + E + Pipe Transaction Counter Enable Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + TRENB + Transaction Counter Enable + 9 + 9 + read-write + + + 0 + Transaction counter is disabled. + #0 + + + 1 + Transaction counter is enabled. + #1 + + + + + TRCLR + Transaction Counter Clear + 8 + 8 + read-write + + + 0 + Invalid + #0 + + + 1 + The current counter value is cleared. + #1 + + + + + + + N + Pipe Transaction Counter Register + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + TRNCNT + Transaction Counter + 0 + 15 + read-write + + + + + + SYSCFG + System Configuration Control Register + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + SCKE + USB Clock Enable + 10 + 10 + read-write + + + 0 + Clock supply to the USBFS stopped + #0 + + + 1 + Clock supply to the USBFS enabled. + #1 + + + + + CNEN + CNEN Single End Receiver Enable + 8 + 8 + read-write + + + 0 + Single end receiver disabled + #0 + + + 1 + Single end receiver enabled + #1 + + + + + DCFM + Controller Function Select + 6 + 6 + read-write + + + 0 + Device controller selected + #0 + + + 1 + Host controller selected. + #1 + + + + + DRPD + D+/D- Line Resistor Control + 5 + 5 + read-write + + + 0 + Line pull-down disabled + #0 + + + 1 + Line pull-down enabled. + #1 + + + + + DPRPU + D+ Line Resistor Control + 4 + 4 + read-write + + + 0 + Line pull-down disabled + #0 + + + 1 + Line pull-down enabled. + #1 + + + + + DMRPU + D- Line Resistor Control + 3 + 3 + read-write + + + 0 + Line pull-up disabled + #0 + + + 1 + Line pull-up enabled. + #1 + + + + + USBE + USB Operation Enable + 0 + 0 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled. + #1 + + + + + + + BUSWAIT + CPU Bus Wait Register + 0x002 + 16 + read-write + 0x000F + 0x3F3F + + + BWAIT + CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) + 0 + 3 + read-write + + + BWAIT + BWAIT wait(s) ( BWAIT + 2 access cycles ) + true + + + + + + + SYSSTS0 + System Configuration Status Register 0 + 0x004 + 16 + read-only + 0x0000 + 0x0000 + + + OVCMON + External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. + 14 + 15 + read-only + + + HTACT + USB Host Sequencer Status Monitor + 6 + 6 + read-only + + + 0 + Host sequencer completely stopped + #0 + + + 1 + Host sequencer not completely stopped. + #1 + + + + + SOFEA + SOF Active Monitor While Host Controller Function is Selected. + 5 + 5 + read-only + + + 0 + SOF output is stopped. + #0 + + + 1 + SOF output is operating. + #1 + + + + + IDMON + External ID0 Input Pin Monitor + 2 + 2 + read-only + + + 0 + USB0_ID pin is low + #0 + + + 1 + USB0_ID pin is high + #1 + + + + + LNST + USB Data Line Status Monitor + 0 + 1 + read-only + + + 00 + SE0 + #00 + + + 01 + K-State (FS) / J-State(LS) + #01 + + + 10 + J-State(FS) / K-State(LS) + #10 + + + 11 + SE1 + #11 + + + + + + + PLLSTA + PLL Status Register + 0x006 + 16 + read-only + 0x0000 + 0x0001 + + + PLLLOCK + PLL Lock Flag + 0 + 0 + read-only + + + 0 + PLL is not locked. + #0 + + + 1 + PLL is locked. + #1 + + + + + + + DVSTCTR0 + Device State Control Register 0 + 0x008 + 16 + read-write + 0x0000 + 0xFFFF + + + HNPBTOA + Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. + 11 + 11 + read-write + + + 0 + Normal Operation + #0 + + + 1 + Switching from device B to device A is enabled + #1 + + + + + EXICEN + USB_EXICEN Output Pin Control + 10 + 10 + read-write + + + 0 + External USB_EXICEN pin outputs low + #0 + + + 1 + External USB_EXICEN pin outputs high + #1 + + + + + VBUSEN + USB_VBUSEN Output Pin Control + 9 + 9 + read-write + + + 0 + External USB_VBUSEN pin outputs low + #0 + + + 1 + External USB_VBUSEN pin outputs high + #1 + + + + + WKUP + Wakeup Output + 8 + 8 + read-write + + + 0 + Remote wakeup signal is not output. + #0 + + + 1 + Remote wakeup signal is output. + #1 + + + + + RWUPE + Wakeup Detection Enable + 7 + 7 + read-write + + + 0 + Downstream port wakeup is disabled. + #0 + + + 1 + Downstream port wakeup is enabled. + #1 + + + + + USBRST + USB Bus Reset Output + 6 + 6 + read-write + + + 0 + USB bus reset signal is not output. + #0 + + + 1 + USB bus reset signal is output. + #1 + + + + + RESUME + Resume Output + 5 + 5 + read-write + + + 0 + Resume signal is not output. + #0 + + + 1 + Resume signal is output. + #1 + + + + + UACT + USB Bus Enable + 4 + 4 + read-write + + + 0 + Downstream port is disabled (SOF transmission is disabled). + #0 + + + 1 + Downstream port is enabled (SOF transmission is enabled). + #1 + + + + + RHST + USB Bus Reset Status + 0 + 2 + read-only + + + 000 + Communication speed not determined + #000 + + + 001 + Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) + #001 + + + 010 + Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) + #010 + + + 011 + Setting prohibited + #011 + + + others + USB bus reset in progress(When the host controller function is selected) + true + + + + + + + TESTMODE + USB Test Mode Register + 0x00C + 16 + read-write + 0x0000 + 0x000F + + + UTST + Test Mode + 0 + 3 + read-write + + + 0000 + Normal operation + #0000 + + + 0001 + Test_J TestMode(When the Function Controller Function is Selected) + #0001 + + + 0010 + Test_K TestMode(When the Function Controller Function is Selected) + #0010 + + + 0011 + Test_SE0_NAK TestMode(When the Function Controller Function is Selected) + #0011 + + + 0100 + Test_Packet TestMode(When the Function Controller Function is Selected) + #0100 + + + 0101 + Reserved TestMode(When the Function Controller Function is Selected) + #0101 + + + 0110 + Reserved TestMode(When the Function Controller Function is Selected) + #0110 + + + 0111 + Reserved TestMode(When the Function Controller Function is Selected) + #0111 + + + 1001 + Test_J TestMode(When the Host Controller Function is Selected) + #1001 + + + 1010 + Test_K TestMode(When the Host Controller Function is Selected) + #1010 + + + 1011 + Test_SE0_NAK TestMode(When the Host Controller Function is Selected) + #1011 + + + 1100 + Test_Packet TestMode(When the Host Controller Function is Selected) + #1100 + + + 1101 + Test_Force_EnableTestMode(When the Host Controller Function is Selected) + #1101 + + + 1110 + Reserved TestMode(When the Host Controller Function is Selected) + #1110 + + + 1111 + Reserved TestMode(When the Host Controller Function is Selected) + #1111 + + + + + + + CFIFOL + CFIFO Port Register L + 0x014 + 16 + read-write + 0x0000 + 0xFFFF + + + + CFIFOLL + CFIFO Port Register LL + CFIFOL + 0x014 + 8 + read-write + 0x00 + 0xFF + + + + CFIFO + CFIFO Port Register + CFIFOL + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + CFIFOH + CFIFO Port Register H + CFIFO + 0x016 + 16 + read-write + 0x0000 + 0xFFFF + + + + CFIFOHH + CFIFO Port Register HH + CFIFOH + 0x017 + 8 + read-write + 0x00 + 0xFF + + + + D0FIFOL + D0FIFO Port Register L + 0x018 + 16 + read-write + 0x0000 + 0xFFFF + + + + D0FIFOLL + D0FIFO Port Register LL + D0FIFOL + 0x018 + 8 + read-write + 0x00 + 0xFF + + + + D0FIFO + D0FIFO Port Register + D0FIFOL + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + D0FIFOH + D0FIFO Port Register H + D0FIFO + 0x01A + 16 + read-write + 0x0000 + 0xFFFF + + + + D0FIFOHH + D0FIFO Port Register HH + D0FIFOH + 0x01B + 8 + read-write + 0x00 + 0xFF + + + + D1FIFOL + D1FIFO Port Register L + 0x01C + 16 + read-write + 0x0000 + 0xFFFF + + + + D1FIFOLL + D1FIFO Port Register LL + D1FIFOL + 0x01C + 8 + read-write + 0x00 + 0xFF + + + + D1FIFO + D1FIFO Port Register + D1FIFOL + 0x01C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + D1FIFOH + D1FIFO Port Register H + D1FIFO + 0x01E + 16 + read-write + 0x0000 + 0xFFFF + + + + D1FIFOHH + D1FIFO Port Register HH + D1FIFOH + 0x01F + 8 + read-write + 0x00 + 0xFF + + + + CFIFOSEL + CFIFO Port Select Register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + RCNT + Read Count Mode + 15 + 15 + read-write + + + 0 + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) + #0 + + + 1 + The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. + #1 + + + + + REW + Buffer Pointer Rewind + 14 + 14 + read-write + + + 0 + The buffer pointer is not rewound. + #0 + + + 1 + The buffer pointer is rewound. + #1 + + + + + MBW + CFIFO Port Access Bit Width + 10 + 11 + read-write + + + 0 + 8-bit width + 0 + + + 1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 + + + + + BIGEND + CFIFO Port Endian Control + 8 + 8 + read-write + + + 0 + Little endian + #0 + + + 1 + Big endian + #1 + + + + + ISEL + CFIFO Port Access Direction When DCP is Selected + 5 + 5 + read-write + + + 0 + Reading from the buffer memory is selected + #0 + + + 1 + Writing to the buffer memory is selected + #1 + + + + + CURPIPE + CFIFO Port Access Pipe Specification + 0 + 3 + read-write + + + 0000 + DCP (Default control pipe) + #0000 + + + 0001 + Pipe 1 + #0001 + + + 0010 + Pipe 2 + #0010 + + + 0011 + Pipe 3 + #0011 + + + 0100 + Pipe 4 + #0100 + + + 0101 + Pipe 5 + #0101 + + + 0110 + Pipe 6 + #0110 + + + 0111 + Pipe 7 + #0111 + + + 1000 + Pipe 8 + #1000 + + + 1001 + Pipe 9 + #1001 + + + others + Setting prohibited + true + + + + + + + CFIFOCTR + CFIFO Port Control Register + 0x022 + 16 + read-write + 0x0000 + 0xFFFF + + + BVAL + Buffer Memory Valid Flag + 15 + 15 + read-write + + + 0 + Invalid + #0 + + + 1 + Writing ended + #1 + + + + + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 + read-write + + + 0 + Does not operate + #0 + + + 1 + FIFO buffer cleared on the CPU side. + #1 + + + + + FRDY + FIFO Port Ready + 13 + 13 + read-only + + + 0 + FIFO port access is disabled. + #0 + + + 1 + FIFO port access is enabled. + #1 + + + + + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + + + + + D0FIFOSEL + D0FIFO Port Select Register + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + + + RCNT + Read Count Mode + 15 + 15 + read-write + + + 0 + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) + #0 + + + 1 + The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) + #1 + + + + + REW + Buffer Pointer RewindNote: Only 0 can be read. + 14 + 14 + read-write + + + 0 + The buffer pointer is not rewound. + #0 + + + 1 + The buffer pointer is rewound. + #1 + + + + + DCLRM + Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read + 13 + 13 + read-write + + + 0 + Auto buffer clear mode is disabled. + #0 + + + 1 + Auto buffer clear mode is enabled. + #1 + + + + + DREQE + DMA/DTC Transfer Request Enable + 12 + 12 + read-write + + + 0 + DMA/DTC transfer request is disabled. + #0 + + + 1 + DMA/DTC transfer request is enabled. + #1 + + + + + MBW + FIFO Port Access Bit Width + 10 + 11 + read-write + + + 0 + 8-bit width + 0 + + + 1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 + + + + + BIGEND + FIFO Port Endian Control + 8 + 8 + read-write + + + 0 + Little endian + #0 + + + 1 + Big endian + #1 + + + + + CURPIPE + FIFO Port Access Pipe Specification + 0 + 3 + read-write + + + 0000 + DCP (Default control pipe) + #0000 + + + 0001 + Pipe 1 + #0001 + + + 0010 + Pipe 2 + #0010 + + + 0011 + Pipe 3 + #0011 + + + 0100 + Pipe 4 + #0100 + + + 0101 + Pipe 5 + #0101 + + + 0110 + Pipe 6 + #0110 + + + 0111 + Pipe 7 + #0111 + + + 1000 + Pipe 8 + #1000 + + + 1001 + Pipe 9 + #1001 + + + others + Setting prohibited + true + + + + + + + D0FIFOCTR + D0FIFO Port Control Register + 0x02A + 16 + read-write + 0x0000 + 0xFFFF + + + BVAL + Buffer Memory Valid Flag + 15 + 15 + read-write + + + 0 + Invalid + #0 + + + 1 + Writing ended + #1 + + + + + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 + read-write + + + 0 + Does not operate + #0 + + + 1 + FIFO buffer cleared on the CPU side. + #1 + + + + + FRDY + FIFO Port Ready + 13 + 13 + read-only + + + 0 + FIFO port access is disabled. + #0 + + + 1 + FIFO port access is enabled. + #1 + + + + + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + + + + + D1FIFOSEL + D1FIFO Port Select Register + 0x02C + 16 + read-write + 0x0000 + 0xFFFF + + + RCNT + Read Count Mode + 15 + 15 + read-write + + + 0 + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) + #0 + + + 1 + The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) + #1 + + + + + REW + Buffer Pointer Rewind + 14 + 14 + read-write + + + 0 + The buffer pointer is not rewound. + #0 + + + 1 + The buffer pointer is rewound. + #1 + + + + + DCLRM + Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read + 13 + 13 + read-write + + + 0 + Auto buffer clear mode is disabled. + #0 + + + 1 + Auto buffer clear mode is enabled. + #1 + + + + + DREQE + DMA/DTC Transfer Request Enable + 12 + 12 + read-write + + + 0 + DMA/DTC transfer request is disabled. + #0 + + + 1 + DMA/DTC transfer request is enabled. + #1 + + + + + MBW + FIFO Port Access Bit Width + 10 + 11 + read-write + + + 0 + 8-bit width + 0 + + + 1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 + + + + + BIGEND + FIFO Port Endian Control + 8 + 8 + read-write + + + 0 + Little endian + #0 + + + 1 + Big endian + #1 + + + + + CURPIPE + FIFO Port Access Pipe Specification + 0 + 3 + read-write + + + 0000 + DCP (Default control pipe) + #0000 + + + 0001 + Pipe 1 + #0001 + + + 0010 + Pipe 2 + #0010 + + + 0011 + Pipe 3 + #0011 + + + 0100 + Pipe 4 + #0100 + + + 0101 + Pipe 5 + #0101 + + + 0110 + Pipe 6 + #0110 + + + 0111 + Pipe 7 + #0111 + + + 1000 + Pipe 8 + #1000 + + + 1001 + Pipe 9 + #1001 + + + others + Setting prohibited + true + + + + + + + D1FIFOCTR + D1FIFO Port Control Register + 0x02E + 16 + read-write + 0x0000 + 0xFFFF + + + BVAL + Buffer Memory Valid Flag + 15 + 15 + read-write + + + 0 + Invalid + #0 + + + 1 + Writing ended + #1 + + + + + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 + read-write + + + 0 + Does not operate + #0 + + + 1 + FIFO buffer cleared on the CPU side. + #1 + + + + + FRDY + FIFO Port Ready + 13 + 13 + read-only + + + 0 + FIFO port access is disabled. + #0 + + + 1 + FIFO port access is enabled. + #1 + + + + + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + + + + + INTENB0 + Interrupt Enable Register 0 + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + + + VBSE + VBUS Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + RSME + Resume Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + SOFE + Frame Number Update Interrupt Enable + 13 + 13 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + DVSE + Device State Transition Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + CTRE + Control Transfer Stage Transition Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + BEMPE + Buffer Empty Interrupt Enable + 10 + 10 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + NRDYE + Buffer Not Ready Response Interrupt Enable + 9 + 9 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + BRDYE + Buffer Ready Interrupt Enable + 8 + 8 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + + + INTENB1 + Interrupt Enable Register 1 + 0x032 + 16 + read-write + 0x0000 + 0xFFFF + + + OVRCRE + Overcurrent Input Change Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + BCHGE + USB Bus Change Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + DTCHE + Disconnection Detection Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + ATTCHE + Connection Detection Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + EOFERRE + EOF Error Detection Interrupt Enable + 6 + 6 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + SIGNE + Setup Transaction Error Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + SACKE + Setup Transaction Normal Response Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + PDDETINTE0 + PDDETINT0 Detection Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + + + BRDYENB + BRDY Interrupt Enable Register + 0x036 + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sBRDYE + BRDY Interrupt Enable for PIPE + 0 + 0 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + + + NRDYENB + NRDY Interrupt Enable Register + 0x038 + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sNRDYE + NRDY Interrupt Enable for PIPE + 0 + 0 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + + + BEMPENB + BEMP Interrupt Enable Register + 0x03A + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sBEMPE + BEMP Interrupt Enable for PIPE + 0 + 0 + read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + + + + + + SOFCFG + SOF Output Configuration Register + 0x03C + 16 + read-write + 0x0000 + 0xFFFF + + + TRNENSEL + Transaction-Enabled Time Select + 8 + 8 + read-write + + + 0 + Not low-speed communication + #0 + + + 1 + Low-speed communication. + #1 + + + + + BRDYM + BRDY Interrupt Status Clear Timing + 6 + 6 + read-write + + + 0 + BRDY flag cleared by software + #0 + + + 1 + BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer. + #1 + + + + + INTL + Interrupt Output Sense Select + 5 + 5 + read-write + + + 0 + Edge sense + #0 + + + 1 + Level sense + #1 + + + + + EDGESTS + Edge Interrupt Output Status Monitor + 4 + 4 + read-only + + + 0 + before stopping the clock supply to the USB module + #0 + + + 1 + the edge interrupt output signal is in the middle of the edge processing + #1 + + + + + + + PHYSET + PHY Setting Register + 0x03E + 16 + read-write + 0x0033 + 0x0B3B + + + HSEB + CL-Only Mode + 15 + 15 + read-write + + + 0 + CL-only mode is not activated. + #0 + + + 1 + CL-only mode is activated. + #1 + + + + + REPSTART + Forcibly Start Terminating Resistance Adjustment + 11 + 11 + read-write + + + 0 + Terminating resistance adjustment is forcibly started + #0 + + + 1 + Terminating resistance adjustment is not forcibly started + #1 + + + + + REPSEL + Terminating Resistance Adjustment Cycle + 8 + 9 + read-write + + + 00 + No cycle is set. + #00 + + + 01 + Adjust terminating resistance at 16-second intervals. + #01 + + + 10 + Adjust terminating resistance at 64-second intervals. + #10 + + + 11 + Adjust terminating resistance at 128-second intervals. + #11 + + + + + CLKSEL + Input System Clock Frequency + 4 + 5 + read-write + + + 00 + Setting Prohibited + #00 + + + 01 + 12 MHz + #01 + + + 10 + 20 MHz + #10 + + + 11 + 24 MHz + #11 + + + + + CDPEN + Charging Downstream Port Enable + 3 + 3 + read-write + + + 0 + Disable charging downstream port + #0 + + + 1 + Enable charging downstream port + #1 + + + + + PLLRESET + PLL Reset Control + 1 + 1 + read-write + + + 0 + Disable PLL reset control for UTMI_PHY + #0 + + + 1 + Enable PLL reset control for UTMI_PHY + #1 + + + + + DIRPD + Power-Down Control + 0 + 0 + read-write + + + 0 + Does not enter low-power consumption mode + #0 + + + 1 + Enter low-power consumption mode + #1 + + + + + + + INTSTS0 + Interrupt Status Register 0 + 0x040 + 16 + read-write + 0x0000 + 0xFF7F + + + VBINT + VBUS Interrupt Status + 15 + 15 + read-write + zeroToClear + modify + + + 0 + VBUS interrupts are not generated. + #0 + + + 1 + VBUS interrupts are generated. + #1 + + + + + RESM + Resume Interrupt Status + 14 + 14 + read-write + zeroToClear + modify + + + 0 + Resume interrupts are not generated. + #0 + + + 1 + Resume interrupts are generated. + #1 + + + + + SOFR + Frame Number Refresh Interrupt Status + 13 + 13 + read-write + zeroToClear + modify + + + 0 + SOF interrupts are not generated. + #0 + + + 1 + SOF interrupts are generated. + #1 + + + + + DVST + Device State Transition Interrupt Status + 12 + 12 + read-write + zeroToClear + modify + + + 0 + Device state transition interrupts are not generated. + #0 + + + 1 + Device state transition interrupts are generated. + #1 + + + + + CTRT + Control Transfer Stage Transition Interrupt Status + 11 + 11 + read-write + zeroToClear + modify + + + 0 + Control transfer stage transition interrupts are not generated. + #0 + + + 1 + Control transfer stage transition interrupts are generated. + #1 + + + + + BEMP + Buffer Empty Interrupt Status + 10 + 10 + read-only + + + 0 + BEMP interrupts are not generated. + #0 + + + 1 + BEMP interrupts are generated. + #1 + + + + + NRDY + Buffer Not Ready Interrupt Status + 9 + 9 + read-only + + + 0 + NRDY interrupts are not generated. + #0 + + + 1 + NRDY interrupts are generated. + #1 + + + + + BRDY + Buffer Ready Interrupt Status + 8 + 8 + read-only + + + 0 + BRDY interrupts are not generated. + #0 + + + 1 + BRDY interrupts are generated. + #1 + + + + + VBSTS + VBUS Input Status + 7 + 7 + read-only + + + 0 + USB_VBUS pin is low. + #0 + + + 1 + USB_VBUS pin is high. + #1 + + + + + DVSQ + Device State + 4 + 6 + read-only + + + 000 + Powered state + #000 + + + 001 + Default state + #001 + + + 010 + Address state + #010 + + + 011 + Configured state + #011 + + + others + Suspended state + true + + + + + VALID + USB Request Reception + 3 + 3 + read-write + + + 0 + Setup packet is not received + #0 + + + 1 + Setup packet is received + #1 + + + + + CTSQ + Control Transfer Stage + 0 + 2 + read-only + + + 000 + Idle or setup stage + #000 + + + 001 + Control read data stage + #001 + + + 010 + Control read status stage + #010 + + + 011 + Control write data stage + #011 + + + 100 + Control write status stage + #100 + + + 101 + Control write (no data) status stage + #101 + + + 110 + Control transfer sequence error + #110 + + + others + Setting prohibited + true + + + + + + + INTSTS1 + Interrupt Status Register 1 + 0x042 + 16 + read-write + 0x0000 + 0xFFFF + + + OVRCR + Overcurrent Input Change Interrupt Status + 15 + 15 + read-write + zeroToClear + modify + + + 0 + OVRCR interrupts are not generated. + #0 + + + 1 + OVRCR interrupts are generated. + #1 + + + + + BCHG + USB Bus Change Interrupt Status + 14 + 14 + read-write + zeroToClear + modify + + + 0 + BCHG interrupts are not generated. + #0 + + + 1 + BCHG interrupts are generated. + #1 + + + + + DTCH + USB Disconnection Detection Interrupt Status + 12 + 12 + read-write + zeroToClear + modify + + + 0 + DTCH interrupts are not generated. + #0 + + + 1 + DTCH interrupts are generated. + #1 + + + + + ATTCH + ATTCH Interrupt Status + 11 + 11 + read-write + zeroToClear + modify + + + 0 + ATTCH interrupts are not generated. + #0 + + + 1 + ATTCH interrupts are generated. + #1 + + + + + L1RSMEND + L1 Resume End Interrupt Status + 9 + 9 + read-write + zeroToClear + modify + + + 0 + L1RSMEND interrupts are not generated + #0 + + + 1 + L1RSMEND interrupts are generated + #1 + + + + + LPMEND + LPM Transaction End Interrupt Status + 8 + 8 + read-write + zeroToClear + modify + + + 0 + LPMEND interrupts are not generated + #0 + + + 1 + LPMEND interrupts are generated + #1 + + + + + EOFERR + EOF Error Detection Interrupt Status + 6 + 6 + read-write + zeroToClear + modify + + + 0 + EOFERR interrupts are not generated. + #0 + + + 1 + EOFERR interrupts are generated. + #1 + + + + + SIGN + Setup Transaction Error Interrupt Status + 5 + 5 + read-write + zeroToClear + modify + + + 0 + SIGN interrupts are not generated. + #0 + + + 1 + SIGN interrupts are generated. + #1 + + + + + SACK + Setup Transaction Normal Response Interrupt Status + 4 + 4 + read-write + zeroToClear + modify + + + 0 + SACK interrupts are not generated. + #0 + + + 1 + SACK interrupts are generated. + #1 + + + + + PDDETINT0 + PDDET0 Detection Interrupt Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + PDDET0 detection interrupts are not generated. + #0 + + + 1 + PDDET0 detection interrupts are generated. + #1 + + + + + + + BRDYSTS + BRDY Interrupt Status Register + 0x046 + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sBRDY + BRDY Interrupt Status for PIPE + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Interrupts are not generated. + #0 + + + 1 + Interrupts are generated. + #1 + + + + + + + NRDYSTS + NRDY Interrupt Status Register + 0x048 + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sNRDY + NRDY Interrupt Status for PIPE + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Interrupts are not generated. + #0 + + + 1 + Interrupts are generated. + #1 + + + + + + + BEMPSTS + BEMP Interrupt Status Register + 0x04A + 16 + read-write + 0x0000 + 0xFFFF + + + 10 + 1 + PIPE%sBEMP + BEMP Interrupt Status for PIPE + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Interrupts are not generated. + #0 + + + 1 + Interrupts are generated. + #1 + + + + + + + FRMNUM + Frame Number Register + 0x04C + 16 + read-write + 0x0000 + 0xFFFF + + + OVRN + Overrun/Underrun Detection Status + 15 + 15 + read-write + + + 0 + No error + #0 + + + 1 + An error occurred + #1 + + + + + CRCE + Receive Data Error + 14 + 14 + read-write + + + 0 + No error + #0 + + + 1 + An error occurred + #1 + + + + + FRNM + Frame NumberLatest frame number + 0 + 10 + read-only + + + + + UFRMNUM + uFrame Number Register + 0x04E + 16 + read-write + 0x0000 + 0x8007 + + + DVCHG + Device State Change + 15 + 15 + read-write + + + 0 + Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. + #0 + + + 1 + Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. + #1 + + + + + UFRNM + MicroframeIndicate the microframe number. + 0 + 2 + read-only + + + + + USBADDR + USB Address Register + 0x050 + 16 + read-write + 0x0000 + 0x077F + + + STSRECOV0 + Status Recovery + 8 + 10 + read-write + + + 001 + Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) + #001 + + + 010 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected) + #010 + + + 011 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) + #011 + + + 100 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected) + #100 + + + 101 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) + #101 + + + 110 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected) + #110 + + + 111 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) + #111 + + + others + Setting prohibited. + true + + + + + USBADDR + USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully. + 0 + 6 + read-only + + + + + USBREQ + USB Request Type Register + 0x054 + 16 + read-write + 0x0000 + 0xFFFF + + + BREQUEST + RequestThese bits store the USB request bRequest value. + 8 + 15 + read-write + + + BMREQUESTTYPE + Request TypeThese bits store the USB request bmRequestType value. + 0 + 7 + read-write + + + + + USBVAL + USB Request Value Register + 0x056 + 16 + read-write + 0x0000 + 0xFFFF + + + WVALUE + ValueThese bits store the USB request Value value. + 0 + 15 + read-write + + + + + USBINDX + USB Request Index Register + 0x058 + 16 + read-write + 0x0000 + 0xFFFF + + + WINDEX + IndexThese bits store the USB request wIndex value. + 0 + 15 + read-write + + + + + USBLENG + USB Request Length Register + 0x05A + 16 + read-write + 0x0000 + 0xFFFF + + + WLENGTH + LengthThese bits store the USB request wLength value. + 0 + 15 + read-write + + + + + DCPCFG + DCP Configuration Register + 0x05C + 16 + read-write + 0x0000 + 0xFFFF + + + CNTMD + Continuous Transfer Mode + 8 + 8 + read-write + + + 0 + Non-continuous transfer mode + #0 + + + 1 + Continuous transfer mode + #1 + + + + + SHTNAK + Pipe Disabled at End of Transfer + 7 + 7 + read-write + + + 0 + Pipe continued at the end of transfer + #0 + + + 1 + Pipe disabled at the end of transfer + #1 + + + + + DIR + Transfer Direction + 4 + 4 + read-write + + + 0 + Data receiving direction + #0 + + + 1 + Data transmitting direction + #1 + + + + + + + DCPMAXP + DCP Maximum Packet Size Register + 0x05E + 16 + read-write + 0x0040 + 0xFFFF + + + DEVSEL + Device Select + 12 + 15 + read-write + + + 0000 + Address 0000 + #0000 + + + 0001 + Address 0001 + #0001 + + + 0010 + Address 0010 + #0010 + + + 0011 + Address 0011 + #0011 + + + 0100 + Address 0100 + #0100 + + + 0101 + Address 0101 + #0101 + + + others + Settings prohibited. + true + + + + + MXPS + Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP. + 0 + 6 + read-write + + + 0x08 + 8 bytes + 0x08 + + + 0x10 + 16 bytes + 0x10 + + + 0x18 + 24 bytes + 0x18 + + + 0x20 + 32 bytes + 0x20 + + + 0x28 + 40 bytes + 0x28 + + + 0x30 + 48 bytes + 0x30 + + + 0x38 + 56 bytes + 0x38 + + + 0x40 + 64 bytes + 0x40 + + + 0x48 + 72 bytes + 0x48 + + + 0x50 + 80 bytes + 0x50 + + + 0x58 + 88 bytes + 0x58 + + + 0x60 + 96 bytes + 0x60 + + + 0x68 + 104 bytes + 0x68 + + + 0x70 + 112 bytes + 0x70 + + + 0x78 + 120 bytes + 0x78 + + + others + Setting prohibited + true + + + + + + + DCPCTR + DCP Control Register + 0x060 + 16 + read-write + 0x0040 + 0xFFFF + + + BSTS + Buffer Status + 15 + 15 + read-only + + + 0 + Buffer access is disabled. + #0 + + + 1 + Buffer access is enabled. + #1 + + + + + SUREQ + Setup Token Transmission + 14 + 14 + read-write + + + 0 + Invalid + #0 + + + 1 + Transmits the setup packet. + #1 + + + + + SUREQCLR + SUREQ Bit Clear + 11 + 11 + read-write + + + 0 + Invalid + #0 + + + 1 + Clears the SUREQ bit to 0. + #1 + + + + + SQCLR + Sequence Toggle Bit Clear + 8 + 8 + read-write + + + 0 + Invalid + #0 + + + 1 + Specifies DATA0. + #1 + + + + + SQSET + Sequence Toggle Bit Set + 7 + 7 + read-write + + + 0 + Invalid + #0 + + + 1 + Specifies DATA1. + #1 + + + + + SQMON + Sequence Toggle Bit Monitor + 6 + 6 + read-only + + + 0 + DATA0 + #0 + + + 1 + DATA1 + #1 + + + + + PBUSY + Pipe Busy + 5 + 5 + read-only + + + 0 + DCP is not used for the transaction. + #0 + + + 1 + DCP is used for the transaction. + #1 + + + + + CCPL + Control Transfer End Enable + 2 + 2 + read-write + + + 0 + Invalid + #0 + + + 1 + Completion of control transfer is enabled. + #1 + + + + + PID + Response PID + 0 + 1 + read-write + + + 00 + NAK response + #00 + + + 01 + BUF response (depending on the buffer state) + #01 + + + 10 + STALL response + #10 + + + 11 + STALL response + #11 + + + + + + + PIPESEL + Pipe Window Select Register + 0x064 + 16 + read-write + 0x0000 + 0xFFFF + + + PIPESEL + Pipe Window Select + 0 + 3 + read-write + + + 0000 + No pipe selected + #0000 + + + 0001 + PIPE1 + #0001 + + + 0010 + PIPE2 + #0010 + + + 0011 + PIPE3 + #0011 + + + 0100 + PIPE4 + #0100 + + + 0101 + PIPE5 + #0101 + + + 0110 + PIPE6 + #0110 + + + 0111 + PIPE7 + #0111 + + + 1000 + PIPE8 + #1000 + + + 1001 + PIPE9 + #1001 + + + others + Settings prohibited. + true + + + + + + + PIPECFG + Pipe Configuration Register + 0x068 + 16 + read-write + 0x0000 + 0xFFFF + + + TYPE + Transfer Type + 14 + 15 + read-write + + + 00 + Pipe not used + #00 + + + 01 + Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) + #01 + + + 10 + Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) + #10 + + + 11 + Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) + #11 + + + + + BFRE + BRDY Interrupt Operation Specification + 10 + 10 + read-write + + + 0 + BRDY interrupt upon transmitting or receiving data + #0 + + + 1 + BRDY interrupt upon completion of reading data + #1 + + + + + DBLB + Double Buffer Mode + 9 + 9 + read-write + + + 0 + Single buffer + #0 + + + 1 + Double buffer + #1 + + + + + SHTNAK + Pipe Disabled at End of Transfer + 7 + 7 + read-write + + + 0 + Continue pipe operation after transfer ends + #0 + + + 1 + Disable pipe operation after transfer ends. + #1 + + + + + DIR + Transfer Direction + 4 + 4 + read-write + + + 0 + Receiving direction + #0 + + + 1 + Transmitting direction + #1 + + + + + EPNUM + Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. + 0 + 3 + read-write + + + + + PIPEMAXP + Pipe Maximum Packet Size Register + 0x06C + 16 + read-write + 0x0000 + 0xFFBF + + + DEVSEL + Device Select + 12 + 15 + read-write + + + 0000 + Address 0000 + #0000 + + + 0001 + Address 0001 + #0001 + + + 0010 + Address 0010 + #0010 + + + 0011 + Address 0011 + #0011 + + + 0100 + Address 0100 + #0100 + + + 0101 + Address 0101 + #0101 + + + others + Settings prohibited. + true + + + + + MXPS + Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) + 0 + 8 + read-write + + + + + PIPEPERI + Pipe Cycle Control Register + 0x06E + 16 + read-write + 0x0000 + 0xFFFF + + + IFIS + Isochronous IN Buffer Flush + 12 + 12 + read-write + + + 0 + The buffer is not flushed. + #0 + + + 1 + The buffer is flushed. + #1 + + + + + IITV + Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. + 0 + 2 + read-write + + + + + 9 + 0x002 + PIPE_CTR[%s] + Pipe %s Control Register + 0x070 + 16 + read-write + 0x0000 + 0xFFFF + + + BSTS + Buffer Status + 15 + 15 + read-only + + + 0 + Buffer access by the CPU is disabled. + #0 + + + 1 + Buffer access by the CPU is enabled. + #1 + + + + + INBUFM + Transmit Buffer Monitor + 14 + 14 + read-only + + + 0 + No data to be transmitted is in the FIFO buffer + #0 + + + 1 + Data to be transmitted is in the FIFO buffer + #1 + + + + + CSCLR + CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe + 13 + 13 + read-write + + + 0 + Writing is disabled. + #0 + + + 1 + The CSSTS bit is cleared. + #1 + + + + + CSSTS + CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe + 12 + 12 + read-only + + + 0 + SSplit Transaction processing is in progress or transfer without Split Transaction is in progress. + #0 + + + 1 + CSplit Transaction processing is in progress. + #1 + + + + + ATREPM + Auto Response Mode + 10 + 10 + read-write + + + 0 + Auto response disabled. + #0 + + + 1 + Auto response enabled. + #1 + + + + + ACLRM + Auto Buffer Clear Mode + 9 + 9 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled (all buffers are initialized) + #1 + + + + + SQCLR + Sequence Toggle Bit Clear + 8 + 8 + read-write + + + 0 + Write disabled + #0 + + + 1 + Specifies DATA0. + #1 + + + + + SQSET + Sequence Toggle Bit Set + 7 + 7 + read-write + + + 0 + Write disabled + #0 + + + 1 + Specifies DATA1. + #1 + + + + + SQMON + Sequence Toggle Bit Confirmation + 6 + 6 + read-only + + + 0 + DATA0 + #0 + + + 1 + DATA1 + #1 + + + + + PBUSY + Pipe Busy + 5 + 5 + read-only + + + 0 + Pipe n not in use for the transaction + #0 + + + 1 + Pipe n in use for the transaction. + #1 + + + + + PID + Response PID + 0 + 1 + read-write + + + 00 + NAK response + #00 + + + 01 + BUF response (depending on the buffer state) + #01 + + + 10 + STALL response + #10 + + + 11 + STALL response + #11 + + + + + + + 10 + 0x002 + DEVADD[%s] + Device Address Configuration Register + 0x0D0 + 16 + read-write + 0x0000 + 0xFFFF + + + UPPHUB + Communication Target Connecting Hub Register + 11 + 14 + read-write + + + 0x0000 + 0x1010 + + + + + 0000 + Directly connected to the port of the USBHS. + #0000 + + + UPPHUB + USB address of the hub + true + + + + + HUBPORT + Communication Target Connecting Hub Port + 8 + 10 + read-write + + + 000 + Directly connected to the port of the USBHS. + #000 + + + others + Port number of the hub + true + + + + + USBSPD + Transfer Speed of Communication Target Device + 6 + 7 + read-write + + + 00 + DEVADDn is not used + #00 + + + 01 + Low speed + #01 + + + 10 + Full speed + #10 + + + 11 + Setting prohibited + #11 + + + + + + + USBBCCTRL0 + BC Control Register 0 + 0x0B0 + 16 + read-write + 0x0000 + 0xFFFF + + + PDDETSTS0 + D+ Pin 0.6 V Input Detection Status + 9 + 9 + read-only + + + 0 + Not detected + #0 + + + 1 + Detected + #1 + + + + + CHGDETSTS0 + D- Pin 0.6 V Input Detection Status + 8 + 8 + read-only + + + 0 + Not detected + #0 + + + 1 + Detected + #1 + + + + + BATCHGE0 + BC (Battery Charger) Function Ch0 General Enable Control + 7 + 7 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + VDMSRCE0 + D- Pin VDMSRC (0.6 V) Output Control + 5 + 5 + read-write + + + 0 + Stop + #0 + + + 1 + 0.6V output + #1 + + + + + IDPSINKE0 + D+ Pin 0.6 V Input Detection (Comparator and Sink) Control + 4 + 4 + read-write + + + 0 + Detection off + #0 + + + 1 + Detection on ( Comparator and sink current on ) + #1 + + + + + VDPSRCE0 + D+ Pin VDPSRC (0.6 V) Output Control + 3 + 3 + read-write + + + 0 + Stop + #0 + + + 1 + 0.6V output + #1 + + + + + IDMSINKE0 + D- Pin 0.6 V Input Detection (Comparator and Sink) Control + 2 + 2 + read-write + + + 0 + Detection off + #0 + + + 1 + Detection on ( Comparator and sink current on ) + #1 + + + + + IDPSRCE0 + D+ Pin IDPSRC Output Control + 1 + 1 + read-write + + + 0 + Stop + #0 + + + 1 + 10uA output + #1 + + + + + RPDME0 + D- Pin Pull-Down Control + 0 + 0 + read-write + + + 0 + Pull-down off + #0 + + + 1 + Pull-down on + #1 + + + + + + + UCKSEL + USB Clock Selection Register + 0x0C4 + 16 + read-write + 0x0000 + 0xFFFF + + + UCKSELC + USB Clock Selection + 0 + 0 + read-write + + + 0 + High-speed on-chip oscillator clock (HOCO) is not selected as USB clock + #0 + + + 1 + High-speed on-chip oscillator clock (HOCO) is selected as USB clock + #1 + + + + + + + USBMC + USB Module Control Register + 0x0CC + 16 + read-write + 0x0002 + 0xFFFF + + + VDCEN + USB Regulator On/Off Control + 7 + 7 + read-write + + + 0 + USB regulator off + #0 + + + 1 + USB regulator on + #1 + + + + + VDDUSBE + USB Reference Power Supply Circuit On/Off Control + 0 + 0 + read-write + + + 0 + USB reference power supply circuit off + #0 + + + 1 + USB reference power supply circuit on + #1 + + + + + + + PHYSLEW + PHY Cross Point Adjustment Register + 0x0F0 + 32 + read-write + 0x0000000E + 0xFF4CFFFF + + + SLEWF01 + Receiver Cross Point Adjustment 01 + 3 + 3 + read-write + + + 1 + Host or device controller mode. + #1 + + + + + SLEWF00 + Receiver Cross Point Adjustment 00 + 2 + 2 + read-write + + + 1 + Host or device controller mode. + #1 + + + + + SLEWR01 + Receiver Cross Point Adjustment 01 + 1 + 1 + read-write + + + 1 + Host or device controller mode. + #1 + + + + + SLEWR00 + Receiver Cross Point Adjustment 00 + 0 + 0 + read-write + + + 1 + Host or device controller mode. + #1 + + + + + + + LPCTRL + Low Power Control Register + 0x100 + 16 + read-write + 0x0000 + 0x0181 + + + HWUPM + Resume Return Mode Setting + 7 + 7 + read-write + + + 0 + Hardware does not recover while CPU clock inactive + #0 + + + 1 + Hardware recovers while CPU clock inactive. + #1 + + + + + + + LPSTS + Low Power Status Register + 0x102 + 16 + read-write + 0x0000 + 0x510B + + + SUSPENDM + UTMI SuspendM Control + 14 + 14 + read-write + + + 0 + UTMI suspension mode + #0 + + + 1 + UTMI normal mode + #1 + + + + + + + BCCTRL + Battery Charging Control Register + 0x140 + 16 + read-write + 0x0000 + 0x033F + + + PDDETSTS + PDDET Status + 9 + 9 + read-only + + + 0 + The PDDET pin is at low level. + #0 + + + 1 + The PDDET pin is at high level. + #1 + + + + + CHGDETSTS + CHGDET Status + 8 + 8 + read-only + + + 0 + The CHGDET pin is at low level. + #0 + + + 1 + The CHGDET pin is at high level. + #1 + + + + + DCPMODE + DCP Mode Control + 5 + 5 + read-write + + + 0 + The RDCP_DAT resistor is disabled + #0 + + + 1 + The RDCP_DAT resistor is enabled. + #1 + + + + + VDMSRCE + VDMSRC Control + 4 + 4 + read-write + + + 0 + The VDM_SRC circuit is disabled. (Initial value) + #0 + + + 1 + The VDM_SRC circuit is enabled. + #1 + + + + + IDPSINKE + IDPSINK Control + 3 + 3 + read-write + + + 0 + The IDP_SINK circuit is disabled. (Initial value) + #0 + + + 1 + The IDP_SINK circuit is enabled. + #1 + + + + + VDPSRCE + VDPSRC Control + 2 + 2 + read-write + + + 0 + The VDP_SRC circuit is disabled. (Initial value) + #0 + + + 1 + The VDP_SRC circuit is enabled. + #1 + + + + + IDMSINKE + IDMSINK Control + 1 + 1 + read-write + + + 0 + The IDM_SINK circuit is disabled. (Initial value) + #0 + + + 1 + The IDM_SINK circuit is enabled. + #1 + + + + + IDPSRCE + IDPSRC Control + 0 + 0 + read-write + + + 0 + The IDP_SRC circuit is disabled. (Initial value) + #0 + + + 1 + The IDP_SRC circuit is enabled. + #1 + + + + + + + PL1CTRL1 + Function L1 Control Register 1 + 0x144 + 16 + read-write + 0x0000 + 0x4FFF + + + L1EXTMD + PHY Control Mode at L1 Return + 14 + 14 + read-write + + + 0 + SUSPENDM is not set by hardware when Host K is received. + #0 + + + 1 + SUSPENDM is set by hardware when Host K is received. + #1 + + + + + HIRDTHR + L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL. + 8 + 11 + read-write + + + DVSQ + DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0]. + 4 + 7 + read-only + + + 0000 + Powered state + #0000 + + + 0001 + Default state + #0001 + + + 0010 + Address state + #0010 + + + 0011 + Configured state + #0011 + + + 0100 + Suspended state + #0100 + + + 0101 + Suspended state + #0101 + + + 0110 + Suspended state + #0110 + + + 0111 + Suspended state + #0111 + + + 1000 + L1 state + #1000 + + + 1001 + L1 state + #1001 + + + 1010 + L1 state + #1010 + + + 1011 + L1 state + #1011 + + + others + setting prohibited + true + + + + + L1NEGOMD + L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11. + 3 + 3 + read-write + + + 0 + When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. + #0 + + + 1 + When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. + #1 + + + + + L1RESPMD + L1 Response Mode + 1 + 2 + read-write + + + 00 + NYET + #00 + + + 01 + ACK + #01 + + + 10 + STALL + #10 + + + 11 + According to the L1NEGOMD bit + #11 + + + + + L1RESPEN + L1 Response Enable + 0 + 0 + read-write + + + 0 + LPM is not supported. + #0 + + + 1 + LPM is supported. + #1 + + + + + + + PL1CTRL2 + Function L1 Control Register 2 + 0x146 + 16 + read-write + 0x0000 + 0x1F00 + + + RWEMON + RWE Value Monitor + 12 + 12 + read-write + + + 0 + The RWE bit value of the LPM token received last is reflected. + #0 + + + 1 + The RWE bit value of the LPM token received last is reflected. + #1 + + + + + HIRDMON + HIRD Value Monitor + 8 + 11 + read-write + + + 0 + The HIRD field value of the LPM token received last is reflected. + #0 + + + 1 + The HIRD field value of the LPM token received last is reflected. + #1 + + + + + + + HL1CTRL1 + Host L1 Control Register 1 + 0x148 + 16 + read-write + 0x0000 + 0x0007 + + + L1STATUS + L1 Request Completion Status + 1 + 2 + read-only + + + 00 + ACK received + #00 + + + 01 + NYET received + #01 + + + 10 + STALL received + #10 + + + 11 + Transaction error + #11 + + + + + L1REQ + L1 Transition Request + 0 + 0 + read-write + + + 0 + This bit is cleared to 0 by hardware when the LPM transaction is completed. + #0 + + + 1 + Set this bit to 1 when requesting a transition to the L1 state. + #1 + + + + + + + HL1CTRL2 + Host L1 Control Register 2 + 0x14A + 16 + read-write + 0x0000 + 0x9F0F + + + BESL + BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume. + 15 + 15 + read-write + + + L1RWE + LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token. + 12 + 12 + read-write + + + HIRD + LPM Token HIRD + 8 + 11 + read-write + + + 0000 + 50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1) + #0000 + + + 0001 + 125 us(BESL = 0) / 100 us(BESL = 1) + #0001 + + + 0010 + 200 us(BESL = 0) / 150 us(BESL = 1) + #0010 + + + 0011 + 275 us(BESL = 0) / 250 us(BESL = 1) + #0011 + + + 0100 + 350 us(BESL = 0) / 350 us(BESL = 1) + #0100 + + + 0101 + 425 us(BESL = 0) / 450 us(BESL = 1) + #0101 + + + 0110 + 500 us(BESL = 0) / 950 us(BESL = 1) + #0110 + + + 0111 + 575 us(BESL = 0) / 1950 us(BESL = 1) + #0111 + + + 1000 + 650 us(BESL = 0) / 2950 us(BESL = 1) + #1000 + + + 1001 + 725 us(BESL = 0) / 3950 us(BESL = 1) + #1001 + + + 1010 + 800 us(BESL = 0) / 4950 us(BESL = 1) + #1010 + + + 1011 + 875 us(BESL = 0) / 5950 us(BESL = 1) + #1011 + + + 1100 + 950 us(BESL = 0) / 6950 us(BESL = 1) + #1100 + + + 1101 + 1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1) + #1101 + + + 1110 + 1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1) + #1110 + + + 1111 + 1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1) + #1111 + + + + + L1ADDR + LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token. + 0 + 3 + read-write + + + + + DPUSR0R + Deep Standby USB Transceiver Control/Pin Monitor Register + 0x160 + 32 + read-only + 0x00000000 + 0xFF4FFFFF + + + DVBSTSHM + VBUS InputIndicates VBUS input signal on the HS side of USB port. + 23 + 23 + read-only + + + DOVCBHM + OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. + 21 + 21 + read-only + + + DOVCAHM + OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. + 20 + 20 + read-only + + + + + DPUSR1R + Deep Standby USB Suspend/Resume Interrupt Register + 0x164 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DVBSTSH + Indication of Return from VBUS Interrupt Source + 23 + 23 + read-only + + + 0 + Indicates deep software standby mode + #0 + + + 1 + Indicates return from deep software standby mode + #1 + + + + + DOVCBH + Indication of Return from OVRCURB Interrupt Source + 21 + 21 + read-only + + + 0 + Indicates deep software standby mode + #0 + + + 1 + Indicates return from deep software standby mode + #1 + + + + + DOVCAH + Indication of Return from OVRCURA Interrupt Source + 20 + 20 + read-only + + + 0 + Indicates deep software standby mode + #0 + + + 1 + Indicates return from deep software standby mode + #1 + + + + + DVBSTSHE + VBUS Interrupt Enable/Clear + 7 + 7 + read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + + + + DOVCBHE + OVRCURB Interrupt Enable Clear + 5 + 5 + read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + + + + DOVCAHE + OVRCURA Interrupt Enable Clear + 4 + 4 + read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + + + + + + DPUSR2R + Deep Standby USB Suspend/Resume Interrupt Register + 0x168 + 16 + read-write + 0x0000 + 0xFFFF + + + DMINTE + DM Interrupt Enable Clear + 9 + 9 + read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + + + + DPINTE + DP Interrupt Enable Clear + 8 + 8 + read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + + + + DMVAL + DM InputIndicates DM input signal on the HS side of USB port. + 5 + 5 + read-only + + + DPVAL + DP InputIndicates DP input signal on the HS side of USB port. + 4 + 4 + read-only + + + DMINT + Indication of Return from DM Interrupt Source + 1 + 1 + read-only + + + 0 + Indicates deep software standby mode + #0 + + + 1 + Indicates return from deep software standby mode + #1 + + + + + DPINT + Indication of Return from DP Interrupt Source + 0 + 0 + read-only + + + 0 + Indicates deep software standby mode + #0 + + + 1 + Indicates return from deep software standby mode + #1 + + + + + + + DPUSRCR + Deep Standby USB Suspend/Resume Command Register + 0x16A + 16 + read-write + 0x0000 + 0xFFFF + + + FIXPHYPD + USB Transceiver Control Fix for PLL + 1 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Go to/Return from deep software standby mode + #1 + + + + + FIXPHY + USB Transceiver Control Fix + 0 + 0 + read-write + + + 0 + Normal mode + #0 + + + 1 + Go to/Return from deep software standby mode + #1 + + + + + + + DPUSR0R_FS + Deep Software Standby USB Transceiver Control/Pin Monitor Register + 0x400 + 32 + read-write + 0x00000000 + 0xFF4CFFFF + + + DVBSTS0 + USB VBUS InputIndicates the VBUS input signal of the USB. + 23 + 23 + read-only + + + DOVCB0 + USB OVRCURB InputIndicates the OVRCURB input signal of the USB. + 21 + 21 + read-only + + + DOVCA0 + USB OVRCURA InputIndicates the OVRCURA input signal of the USB. + 20 + 20 + read-only + + + DM0 + USB D-InputIndicates the D- input signal of the USB. + 17 + 17 + read-only + + + DP0 + USB0 D+ InputIndicates the D+ input signal of the USB. + 16 + 16 + read-only + + + FIXPHY0 + USB Transceiver Output Fix + 4 + 4 + read-write + + + 0 + The outputs are fixed in normal mode and on return from deep software standby mode. + #0 + + + 1 + The outputs are fixed on transitions to deep software standby mode. + #1 + + + + + DRPD0 + D+/D- Pull-Down Resistor Control + 3 + 3 + read-write + + + 0 + Disables DP/DM pull-down resistor. + #0 + + + 1 + Enables DP/DM pull-down resistor. + #1 + + + + + RPUE0 + DP Pull-Up Resistor Control + 1 + 1 + read-write + + + 0 + Disables DP pull-up resistor. + #0 + + + 1 + Enables DP pull-up resistor. + #1 + + + + + SRPC0 + USB Single End Receiver Control + 0 + 0 + read-write + + + 0 + Input through the DP and DM inputs is disabled. + #0 + + + 1 + Input through the DP and DM inputs is enabled. + #1 + + + + + + + DPUSR1R_FS + Deep Software Standby USB Suspend/Resume Interrupt Register + 0x404 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DVBINT0 + USB VBUS Interrupt Source Recovery + 23 + 23 + read-only + + + 0 + The system has not returned from deep software standby mode. + #0 + + + 1 + The system has returned from deep software standby mode. + #1 + + + + + DOVRCRB0 + USB OVRCURB Interrupt Source Recovery + 21 + 21 + read-only + + + 0 + The system has not returned from deep software standby mode. + #0 + + + 1 + The system has returned from deep software standby mode. + #1 + + + + + DOVRCRA0 + USB OVRCURA Interrupt Source Recovery + 20 + 20 + read-only + + + 0 + The system has not returned from deep software standby mode. + #0 + + + 1 + The system has returned from deep software standby mode. + #1 + + + + + DMINT0 + USB DM Interrupt Source Recovery + 17 + 17 + read-only + + + 0 + The system has not returned from deep software standby mode. + #0 + + + 1 + The system has returned from deep software standby mode. + #1 + + + + + DPINT0 + USB DP Interrupt Source Recovery + 16 + 16 + read-only + + + 0 + The system has not returned from deep software standby mode. + #0 + + + 1 + The system has returned from deep software standby mode. + #1 + + + + + DVBSE0 + USB VBUS Interrupt Enable/Clear + 7 + 7 + read-write + + + 0 + Recovery from deep software standby mode is disabled. + #0 + + + 1 + Recovery from deep software standby mode is enabled. + #1 + + + + + DOVRCRBE0 + USB OVRCURB Interrupt Enable/Clear + 5 + 5 + read-write + + + 0 + Recovery from deep software standby mode is disabled. + #0 + + + 1 + Recovery from deep software standby mode is enabled. + #1 + + + + + DOVRCRAE0 + USB OVRCURA Interrupt Enable/Clear + 4 + 4 + read-write + + + 0 + Recovery from deep software standby mode is disabled. + #0 + + + 1 + Recovery from deep software standby mode is enabled. + #1 + + + + + DMINTE0 + USB DM Interrupt Enable/Clear + 1 + 1 + read-write + + + 0 + Recovery from deep software standby mode is disabled. + #0 + + + 1 + Recovery from deep software standby mode is enabled. + #1 + + + + + DPINTE0 + USB DP Interrupt Enable/Clear + 0 + 0 + read-write + + + 0 + Recovery from deep software standby mode is disabled. + #0 + + + 1 + Recovery from deep software standby mode is enabled. + #1 + + + + + + + + + R_USB_HS0 + 0x40060000 + + + R_WDT + Watchdog Timer + 0x40044200 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x005 + registers + + + 0x00000008 + 0x01 + registers + + + + WDTRR + WDT Refresh Register + 0x00 + 8 + read-write + 0xFF + 0xFF + + + WDTRR + WDTRR is an 8-bit register that refreshes the down-counter of the WDT. + 0 + 7 + read-write + + + + + WDTCR + WDT Control Register + 0x02 + 16 + read-write + 0x33F3 + 0xFFFF + + + RPSS + Window Start Position Selection + 12 + 13 + read-write + + + 00 + 25% + #00 + + + 01 + 50% + #01 + + + 10 + 75% + #10 + + + 11 + 100% (window start position is not specified) + #11 + + + + + RPES + Window End Position Selection + 8 + 9 + read-write + + + 00 + 75% + #00 + + + 01 + 50% + #01 + + + 10 + 25% + #10 + + + 11 + 0% (window end position is not specified) + #11 + + + + + CKS + Clock Division Ratio Selection + 4 + 7 + read-write + + + 0001 + PCLK/4 + #0001 + + + 0100 + PCLK/64 + #0100 + + + 1111 + PCLK/128 + #1111 + + + 0110 + PCLK/512 + #0110 + + + 0111 + PCLK/2048 + #0111 + + + 1000 + PCLK/8192 + #1000 + + + others + setting prohibited + true + + + + + TOPS + Timeout Period Selection + 0 + 1 + read-write + + + 00 + 1,024 cycles (03FFh) + #00 + + + 01 + 4,096 cycles (0FFFh) + #01 + + + 10 + 8,192 cycles (1FFFh) + #10 + + + 11 + 16,384 cycles (3FFFh) + #11 + + + + + + + WDTSR + WDT Status Register + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + REFEF + Refresh Error Flag + 15 + 15 + read-write + zeroToClear + modify + + + 0 + No refresh error occurred + #0 + + + 1 + Refresh error occurred + #1 + + + + + UNDFF + Underflow Flag + 14 + 14 + read-write + zeroToClear + modify + + + 0 + No underflow occurred + #0 + + + 1 + Underflow occurred + #1 + + + + + CNTVAL + Down-Counter Value + 0 + 13 + read-only + + + + + WDTRCR + WDT Reset Control Register + 0x06 + 8 + read-write + 0x80 + 0xFF + + + RSTIRQS + Reset Interrupt Request Selection + 7 + 7 + read-write + + + 0 + Non-maskable interrupt request or interrupt request output is enabled + #0 + + + 1 + Reset output is enabled. + #1 + + + + + + + WDTCSTPR + WDT Count Stop Control Register + 0x08 + 8 + read-write + 0x80 + 0xFF + + + SLCSTP + Sleep-Mode Count Stop Control + 7 + 7 + read-write + + + 0 + Count stop is disabled. + #0 + + + 1 + Count is stopped at a transition to sleep mode. + #1 + + + + + + + + + \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 0000000000..dfb1c8b7e2 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Defines function pointers to be used with vector table. */ +typedef void (* exc_ptr_t)(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Reset_Handler(void); +void Default_Handler(void); +int32_t main(void); + +/*******************************************************************************************************************//** + * MCU starts executing here out of reset. Main stack pointer is set up already. + **********************************************************************************************************************/ +void Reset_Handler (void) +{ + /* Initialize system using BSP. */ + SystemInit(); + + /* Call user application. */ + main(); + + while (1) + { + /* Infinite Loop. */ + } +} + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption + * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status + * registers for more information. + */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); +} + +/* Main stack */ +static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) BSP_PLACE_IN_SECTION( + BSP_SECTION_STACK); + +/* Heap */ +#if (BSP_CFG_HEAP_BYTES > 0) + +BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ + BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); +#endif + +/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle + * these exceptions in their code they should define their own function with the same name. + */ +#if defined(__ICCARM__) + #define WEAK_REF_ATTRIBUTE + + #pragma weak HardFault_Handler = Default_Handler + #pragma weak MemManage_Handler = Default_Handler + #pragma weak BusFault_Handler = Default_Handler + #pragma weak UsageFault_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak DebugMon_Handler = Default_Handler + #pragma weak PendSV_Handler = Default_Handler + #pragma weak SysTick_Handler = Default_Handler +#elif defined(__GNUC__) + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void NMI_Handler(void); // NMI has many sources and is handled by BSP +void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; +void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; +void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; +void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; +void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; +void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; + +/* Vector table. */ +BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION( + BSP_SECTION_FIXED_VECTORS) = +{ + (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ +}; + +/** @} (end addtogroup BSP_MCU) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 0000000000..5122e34cfb --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,354 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "../../../../mcu/all/bsp_clocks.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Mask to select CP bits( 0xF00000 ) */ +#define CP_MASK (0x0000000FU << 20) + +/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */ +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 0U; + +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$BSS$$ZI$$Base; +extern uint32_t Image$$BSS$$ZI$$Length; +extern uint32_t Load$$DATA$$Base; +extern uint32_t Image$$DATA$$Base; +extern uint32_t Image$$DATA$$Length; +extern uint32_t Image$$STACK$$RW$$Base; +extern uint32_t Image$$STACK$$RW$$Length; +#elif defined(__GNUC__) + +/* Generated by linker. */ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackLimit; +extern uint32_t __StackTop; +#elif defined(__ICCARM__) + #pragma section=".bss" + #pragma section=".data" + #pragma section=".data_init" + #pragma section=".stack" +#endif + +/* Initialize static constructors */ +#if defined(__ARMCC_VERSION) +extern void (* Image$$INIT_ARRAY$$Base[])(void); +extern void (* Image$$INIT_ARRAY$$Limit[])(void); +#elif defined(__GNUC__) + +extern void (* __init_array_start[])(void); + +extern void (* __init_array_end[])(void); +#elif defined(__ICCARM__) +extern void __call_ctors(void const *, void const *); + + #pragma section = "SHT$$PREINIT_ARRAY" const + #pragma section = "SHT$$INIT_ARRAY" const +#endif + +extern void * __Vectors[]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit(void); + +#endif + +#if defined(__ICCARM__) + #pragma weak R_BSP_WarmStart +void R_BSP_WarmStart(bsp_warm_start_event_t event); + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ +#if __FPU_USED + + /* Enable the Cortex-M4 FPU only when -mfloat-abi=hard. + * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ + + /* Set bits 20-23 to enable CP10 and CP11 coprocessor */ + /* SCB is a CMSIS defined element over which we have no control. */ + SCB->CPACR |= (uint32_t) CP_MASK; +#endif + +#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP + + /* Unlock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + + /* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1 + * "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual + * R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot + * be accessed until VBTSR.VBTRVLD is set. */ + R_SYSTEM->VBTCR1 = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U); + + /* Lock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#endif + + /* Call pre clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + + /* Configure system clocks. */ + bsp_clock_init(); + +#if BSP_FEATURE_BSP_RESET_TRNG + + /* To prevent an undesired current draw, this MCU requires a reset + * of the TRNG circuit after the clocks are initialized */ + bsp_reset_trng_circuit(); +#endif + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + + /* Initialize C runtime environment. */ + /* Zero out BSS */ +#if defined(__ARMCC_VERSION) + memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length); +#elif defined(__GNUC__) + memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__)); +#elif defined(__ICCARM__) + memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss")); +#endif + + /* Copy initialized RAM data from ROM to RAM. */ +#if defined(__ARMCC_VERSION) + memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length); +#elif defined(__GNUC__) + memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__)); +#elif defined(__ICCARM__) + memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"), + (uint32_t) __section_size(".data")); + + /* Copy functions to be executed from RAM. */ + #pragma section=".code_in_ram" + #pragma section=".code_in_ram_init" + memcpy((uint32_t *) __section_begin(".code_in_ram"), + (uint32_t *) __section_begin(".code_in_ram_init"), + (uint32_t) __section_size(".code_in_ram")); + + /* Copy main thread TLS to RAM. */ + #pragma section="__DLIB_PERTHREAD_init" + #pragma section="__DLIB_PERTHREAD" + memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"), + (uint32_t) __section_size("__DLIB_PERTHREAD_init")); +#endif + + /* Disable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 0; + + /* Setup NMI interrupt */ + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; +#if defined(__ICCARM__) + + /* Setup start address */ + R_MPU_SPMON->SP[0].SA = (uint32_t) __section_begin(".stack"); + + /* Setup end address */ + R_MPU_SPMON->SP[0].EA = (uint32_t) __section_end(".stack"); +#elif defined(__ARMCC_VERSION) + + /* Setup start address */ + R_MPU_SPMON->SP[0].SA = (uint32_t) &Image$$STACK$$RW$$Base; + + /* Setup end address */ + R_MPU_SPMON->SP[0].EA = (uint32_t) &Image$$STACK$$RW$$Base + (uint32_t) &Image$$STACK$$RW$$Length; +#elif defined(__GNUC__) + + /* Setup start address */ + R_MPU_SPMON->SP[0].SA = (uint32_t) &__StackLimit; + + /* Setup end address */ + R_MPU_SPMON->SP[0].EA = (uint32_t) &__StackTop; +#endif + + /* Disable stack monitoring for FreeRTOS. Not yet supported. */ +#if (BSP_CFG_RTOS == 0) + + /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + /* Enable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 1U; +#endif + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + +#if !BSP_CFG_PFS_PROTECT + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + + /* Initialize static constructors */ +#if defined(__ARMCC_VERSION) + int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base; + for (int32_t i = 0; i < count; i++) + { + void (* p_init_func)(void) = + (void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]); + p_init_func(); + } + +#elif defined(__GNUC__) + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + +#elif defined(__ICCARM__) + void const * pibase = __section_begin("SHT$$PREINIT_ARRAY"); + void const * ilimit = __section_end("SHT$$INIT_ARRAY"); + __call_ctors(pibase, ilimit); +#endif + + /* Initialize ELC events that will be used to trigger NVIC interrupts. */ + bsp_irq_cfg(); + + /* Call any BSP specific code. No arguments are needed so NULL is sent. */ + bsp_init(NULL); +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module + * is not in use. + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit (void) +{ + volatile uint8_t read_port = 0U; + FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning + + /* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example + * of initial setting flow for an unused circuit") */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Enable TRNG function (disable stop function) */ + #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2 + R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_BSP_HAS_SCE5 + R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Wait for at least 3 PCLKB cycles */ + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + + /* Disable TRNG function */ + #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2 + R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_BSP_HAS_SCE5 + R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example + * of initial setting flow for an unused circuit") */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 0000000000..f3e97ceeaa --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,945 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +#define BSP_PRV_MAXIMUM_HOCOWTR_HSTS ((uint8_t) 0x6U) + +/* Wait state definitions for MEMWAIT. */ +#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U) + +/* Wait state definitions for FLDWAITR. */ +#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U) +#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U) + +/* Temporary solution until R_FACI is added to renesas.h. */ +#define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U))) + +/* Wait state definitions for MCUS with SRAMWTSC and FLWT. */ +#define BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) +#define BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) +#define BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS (80000000U) +#define BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES (0xEU) +#define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_SRAM_PRCR_KEY (0x78U) +#define BSP_PRV_SRAM_UNLOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U) +#define BSP_PRV_SRAM_LOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U) + +/* Calculate value to write to MOMCR (MODRV controls main clock drive strength and MOSEL determines the source of the + * main oscillator). */ +#define BSP_PRV_MOMCR_MOSEL_BIT (6) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) +#define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << BSP_PRV_MOMCR_MOSEL_BIT) +#define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL) + +/* Locations of bitfields used to configure CLKOUT. */ +#define BSP_PRV_CKOCR_CKODIV_BIT (4U) +#define BSP_PRV_CKOCR_CKOEN_BIT (7U) + +/* Location of bitfield used to configure USB clock divider. */ +#define BSP_PRV_SCKDIVCR2_UCK_BIT (4U) + +/* Calculate the value to write to SCKDIVCR. */ +#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 7U) << 24U) +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0x7U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0x7U) << 4U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0x7U) << 16U) +#elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + +/* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */ + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0x7U) << 28U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) + +/* The number of clocks is used to size the g_clock_freq array. */ +#if BSP_PRV_PLL_SUPPORTED + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U) +#else + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U) +#endif + +/* Frequencies of clocks with fixed freqencies. */ +#define BSP_PRV_LOCO_FREQ (32768U) // LOCO frequency is fixed at 32768 Hz +#define BSP_PRV_SUBCLOCK_FREQ (32768U) // Subclock frequency is 32768 Hz +#define BSP_PRV_MOCO_FREQ (8000000U) // MOCO frequency is fixed at 8 MHz + +/* Calculate PLLCCR value. */ +#if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #endif + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL_DIV) + #endif + #if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide + #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6 + + #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1) + #define BSP_PRV_PLLCCR (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ + (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT) + #endif +#endif + +/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock + * frequency. */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \ + BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED) +#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) +#else + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz); +static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state); + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE +static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode); + +#endif + +#if !BSP_CFG_SOFT_RESET_SUPPORTED +static void bsp_prv_clock_set_hard_reset(void); + +#endif + +/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C + * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime + * environment is initialized. */ +static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(".noinit"); + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/* List of MSTP bits that must be set before entering low power modes or changing SCKDIVCR. */ +static const uint8_t g_bsp_prv_power_change_mstp_data[][2] = BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY; + +static const uint8_t g_bsp_prv_power_change_mstp_length = sizeof(g_bsp_prv_power_change_mstp_data) / + sizeof(g_bsp_prv_power_change_mstp_data[0]); + +static volatile uint32_t * const gp_bsp_prv_mstp = &R_MSTP->MSTPCRB; +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed in OPCCR. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be + * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED + **********************************************************************************************************************/ +static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode) +{ + #if BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR + + /* If the desired operating mode is already set, return. */ + if (operating_mode == R_SYSTEM->OPCCR) + { + return; + } + + /* On some MCUs, the HOCO must be stable before updating OPCCR.OPCM. */ + if (0U == R_SYSTEM->HOCOCR) + { + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + } + #endif + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); + + /* Apply requested operating speed mode. */ + R_SYSTEM->OPCCR = operating_mode; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); +} + +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed mode. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros + **********************************************************************************************************************/ +void bsp_prv_operating_mode_set (uint8_t operating_mode) +{ + if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) + { + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Set subosc speed mode. */ + R_SYSTEM->SOPCCR = 0x1U; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + } + else + { + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Exit subosc speed mode first. */ + R_SYSTEM->SOPCCR = 0U; + + /* Wait for transition to complete. Check the entire register here since it should be set to 0 at this point. + * Checking the entire register is slightly more efficient. This will also hang the program if the LPM + * registers are not unlocked, which can help catch programming errors. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U); + + bsp_prv_operating_mode_opccr_set(operating_mode); + } +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*********************************************************************************************************************** + * Updates the operating frequency of the PLL. + * + * @param[in] pll_freq_hz New frequency of the PLL after the PLL is configured + **********************************************************************************************************************/ +void bsp_prv_prepare_pll (uint32_t pll_freq_hz) +{ + /* Store the PLL frequency, which is required to update SystemCoreClock after switching to PLL. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = pll_freq_hz; +} + +#endif + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t clock_index = R_SYSTEM->SCKSCR; + SystemCoreClock = g_clock_freq[clock_index] >> R_SYSTEM->SCKDIVCR_b.ICK; +} + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Sets MSTP bits as required by the hardware manual for the MCU (reference Figure 9.2 "Example flow for changing the + * value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100). + * + * This function must be called before entering standby or changing SCKDIVCR. + * + * @return bitmask of bits set, where each bit corresponds to an index in g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +uint32_t bsp_prv_power_change_mstp_set (void) +{ + uint32_t mstp_set_bitmask = 0U; + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + /* Only set the bit if it's currently cleared. */ + if (!(gp_bsp_prv_mstp[mstp_index] & mstp_bit)) + { + gp_bsp_prv_mstp[mstp_index] |= mstp_bit; + mstp_set_bitmask |= 1U << i; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being set. It was measured + * at 58 cycles for default IAR build configurations and 59 cycles for default GCC build configurations. */ + } + + /* The time between setting last MSTP bit and setting SCKDIVCR takes over 750 ns (90 cycles at 120 MHz). It was + * measured at 96 cycles for default IAR build configurations and 102 cycles for default GCC build + * configurations. */ + + return mstp_set_bitmask; +} + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Clears MSTP bits set by bsp_prv_power_change_mstp_set as required by the hardware manual for the MCU (reference + * Figure 9.2 "Example flow for changing the value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100). + * + * This function must be called after exiting standby or changing SCKDIVCR. + * + * @param[in] mstp_clear_bitmask bitmask of bits to clear, where each bit corresponds to an index in + * g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask) +{ + /* The time between setting SCKDIVCR and clearing the first MSTP bit takes over 250 ns (30 cycles at 120 MHz). It + * was measured at 38 cycles for default IAR build configurations and 68 cycles for default GCC build + * configurations. */ + + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Only clear the bit if it was set in bsp_prv_power_change_mstp_set. */ + if ((1U << i) & mstp_clear_bitmask) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + gp_bsp_prv_mstp[mstp_index] &= ~mstp_bit; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being cleared. It was measured + * at 44 cycles for default IAR build configurations and 53 cycles for default GCC build configurations. */ + } +} + +#endif + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] clock Desired system clock + * @param[in] sckdivcr Value to set in SCKDIVCR register + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr) +{ +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Set MSTP bits as required by the hardware manual. This is done first to ensure the 750 ns delay required after + * increasing any division ratio in SCKDIVCR is met. */ + uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set(); +#endif + + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK; + + /* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be + * set is higher than before. */ + uint32_t clock_freq_hz_post_change = g_clock_freq[clock] >> iclk_div; + uint8_t new_rom_wait_state = bsp_clock_set_prechange(clock_freq_hz_post_change); + + /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and + * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */ + + /* If the current ICLK divider is less (higher frequency) than the requested ICLK divider, set the divider + * first. */ + sckdivcr = sckdivcr & BSP_PRV_SCKDIVCR_MASK; + if (R_SYSTEM->SCKDIVCR_b.ICK < iclk_div) + { + /* Set the system dividers */ + R_SYSTEM->SCKDIVCR = sckdivcr; + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + } + + /* If the current ICLK divider is greater (lower frequency) than the requested ICLK divider, set the clock + * source first. If the ICLK divider is the same, order does not matter. */ + else + { + /* Set the system source clock */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + + /* Set the system dividers */ + R_SYSTEM->SCKDIVCR = sckdivcr; + } + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + bsp_clock_set_postchange(SystemCoreClock, new_rom_wait_state); + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Clear MSTP bits as required by the hardware manual. This is done last to ensure the 250 ns delay required after + * decreasing any division ratio in SCKDIVCR is met. */ + bsp_prv_power_change_mstp_clear(mstp_set_bitmask); +#endif +} + +#if !BSP_CFG_SOFT_RESET_SUPPORTED + +static void bsp_prv_clock_set_hard_reset (void) +{ + /* Wait states in SRAMWTSC are set after hard reset. No change required here. */ + + /* Calculate the wait states for ROM */ + #if BSP_FEATURE_CGC_HAS_FLWT + #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS + + /* Do nothing. Default setting in FLWT is correct. */ + #elif BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS + R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES; + #else + R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + #endif + #endif + + /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and + * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */ + + /* ICLK divider at reset is lowest possible, so set dividers first. */ + + /* Set the system dividers first if ICLK divisor is larger than reset value. */ + #if BSP_CFG_ICLK_DIV >= BSP_FEATURE_CGC_ICLK_DIV_RESET + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + /* Set the system dividers after setting the system clock source if ICLK divisor is smaller than reset value. */ + #if BSP_CFG_ICLK_DIV < BSP_FEATURE_CGC_ICLK_DIV_RESET + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + + /* ROM wait states are 0 by default. No change required here. */ +} + +#endif + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + /* Unlock CGC and LPM protection registers. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE + + /* Disable ROM cache. */ + R_FCACHE->FCACHEE = 0U; +#endif +#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER + + /* Disable the flash prefetch buffer. */ + R_FACI_LP->PFBER = 0; +#endif + + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] = BSP_HOCO_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] = BSP_PRV_MOCO_FREQ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] = BSP_PRV_LOCO_FREQ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_PRV_SUBCLOCK_FREQ; +#if BSP_PRV_PLL_SUPPORTED + + /* The PLL value will be calculated at initialization. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ; +#endif + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); + +#if BSP_CFG_SOFT_RESET_SUPPORTED + + /* Update the main oscillator drive, source, and wait states if the main oscillator is stopped. If the main + * oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */ + if (R_SYSTEM->MOSCCR) + { + /* Don't write to MOSCWTCR unless MOSTP is 1 and MOSCSF = 0. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 0U); + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the main oscillator wait time. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; + } +#else + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the main oscillator wait time. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; +#endif + +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* If the board has a subclock, set the subclock drive and start the subclock if the subclock is stopped. If the + * subclock is running, the subclock drive is assumed to be set appropriately. */ + if (R_SYSTEM->SOSCCR) + { + /* Configure the subclock drive if the subclock is not already running. */ + R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); + R_SYSTEM->SOSCCR = 0U; + #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + + /* If the subclock is the system clock source, wait for it to stabilize. */ + R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS); + #endif + } +#else + R_SYSTEM->SOSCCR = 1U; +#endif + +#if BSP_FEATURE_CGC_HAS_HOCOWTCR + #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY + + /* These MCUs only require writes to HOCOWTCR if HOCO is set to 64 MHz. */ + #if 64000000 == BSP_HOCO_HZ + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Wait for HOCO to stabilize before writing to HOCOWTCR. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #else + + /* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating + * power control mode. */ + #endif + R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS; + #endif + #else + + /* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode. There is no restriction to + * writing this register. */ + R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS; + #endif +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_CFG_SOFT_RESET_SUPPORTED + + /* Switch to high-speed to prevent any issues with the subsequent clock configurations. */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #elif BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ > 0U + + /* MCUs that support low voltage mode start up in low voltage mode. */ + bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_CLOCK_SOURCE && BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE + + /* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low + * voltage mode. */ + R_SYSTEM->HOCOCR = 1U; + #endif + #endif +#endif + + /* If the PLL is the desired source clock, ensure the source clock is running and stable and the power mode + * allows PLL operation. */ +#if BSP_PRV_PLL_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + + /* Start PLL source clock. */ + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + R_SYSTEM->HOCOCR = 0U; + #else + R_SYSTEM->MOSCCR = 0U; + #endif + + /* Store PLL frequency. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; + + /* Configure the PLL registers. */ + #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; + #endif + + #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0 + + /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some + * MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100). + * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of + * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running + * while setting PLLCCR. */ + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); + #endif + + /* Verify PLL source is stable before starting PLL. */ + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #else + + /* Wait for main oscillator to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); + #endif + #endif +#endif + + /* Start source clock. */ +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE + R_SYSTEM->HOCOCR = 0U; + + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE + #if BSP_CFG_SOFT_RESET_SUPPORTED + + /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->MOCOCR) + { + R_SYSTEM->MOCOCR = 0U; + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif +#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE + #if BSP_CFG_SOFT_RESET_SUPPORTED + + /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->LOCOCR) + { + R_SYSTEM->LOCOCR = 0U; + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #else + R_SYSTEM->LOCOCR = 0U; + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE + R_SYSTEM->MOSCCR = 0U; + + /* Wait for main oscillator to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + R_SYSTEM->PLLCR = 0U; + + /* Wait for PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U); +#else + + /* Do nothing. Subclock is already started and stabilized if it is populated and selected as system clock. */ +#endif + + /* Set source clock and dividers. */ +#if BSP_CFG_SOFT_RESET_SUPPORTED + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR); +#else + bsp_prv_clock_set_hard_reset(); +#endif + + /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */ +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED + #if BSP_PRV_PLL_SUPPORTED + #if BSP_CFG_SOFT_RESET_SUPPORTED + if (BSP_PRV_OPERATING_MODE_LOW_SPEED == BSP_PRV_STARTUP_OPERATING_MODE) + { + /* If the MCU has a PLL, ensure PLL is stopped and stable before entering low speed mode. */ + R_SYSTEM->PLLCR = 1U; + + /* Wait for PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0U); + } + #endif + #endif + bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE); + #endif +#endif + + /* Set USB clock divisor if it exists on the MCU. */ +#ifdef BSP_CFG_UCK_DIV + R_SYSTEM->SCKDIVCR2 = BSP_CFG_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; +#endif + +#if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL + + /* Some MCUs have an alternate register for selecting the USB clock source. */ + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCK_SOURCE + + /* Write to USBCKCR to select the PLL. */ + R_SYSTEM->USBCKCR = 0; + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCK_SOURCE + + /* Write to USBCKCR to select the HOCO. */ + R_SYSTEM->USBCKCR = 1; + #endif + #endif +#endif + + /* Configure BCLK if it exists on the MCU. */ +#ifdef BSP_CFG_BCLK_OUTPUT + #if BSP_CFG_BCLK_OUTPUT > 0U + R_SYSTEM->BCKCR = BSP_CFG_BCLK_OUTPUT - 1U; + R_SYSTEM->EBCKOCR = 1U; + #else + #if BSP_CFG_SOFT_RESET_SUPPORTED + R_SYSTEM->EBCKOCR = 0U; + #endif + #endif +#endif + + /* Configure SDRAM clock if it exists on the MCU. */ +#ifdef BSP_CFG_SDCLK_OUTPUT + R_SYSTEM->SDCKOCR = BSP_CFG_SDCLK_OUTPUT; +#endif + + /* Configure CLKOUT. */ +#if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLKOUT_DISABLED + #if BSP_CFG_SOFT_RESET_SUPPORTED + R_SYSTEM->CKOCR = 0U; + #endif +#else + uint8_t ckocr = BSP_CFG_CLKOUT_SOURCE | (BSP_CFG_CLKOUT_DIV << BSP_PRV_CKOCR_CKODIV_BIT); + R_SYSTEM->CKOCR = ckocr; + ckocr |= (1U << BSP_PRV_CKOCR_CKOEN_BIT); + R_SYSTEM->CKOCR = ckocr; +#endif + + /* Lock CGC and LPM protection registers. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + +#if BSP_FEATURE_BSP_FLASH_CACHE + + /* Invalidate flash cache. */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; +#endif + +#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 1; +#endif +} + +/*******************************************************************************************************************//** + * Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change. + * + * @param[in] requested_freq_hz New core clock frequency after the clock change. + * + * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist). + **********************************************************************************************************************/ +static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) +{ + uint8_t new_rom_wait_state = 0U; + +#if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (requested_freq_hz > BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS) + { + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES; + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + } +#endif + +#if BSP_FEATURE_CGC_HAS_FLWT + + /* Calculate the wait states for ROM */ + if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + + /* If more wait states are required after the change, then set the wait states before changing the clock. */ + if (new_rom_wait_state > R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } +#endif + +#if BSP_FEATURE_CGC_HAS_MEMWAIT + if (requested_freq_hz > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + } +#endif + +#if BSP_FEATURE_CGC_HAS_FLDWAITR + if (requested_freq_hz > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + } +#endif + + return new_rom_wait_state; +} + +/*******************************************************************************************************************//** + * Decreases the ROM and RAM wait state settings to the minimum supported based on the applied clock change. + * + * @param[in] updated_freq_hz New clock frequency after clock change + * @param[in] new_rom_wait_state Optimal value for FLWT if it exists, 0 if FLWT does not exist on the MCU + **********************************************************************************************************************/ +static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_wait_state) +{ + /* These variables are unused for some MCUs. */ + FSP_PARAMETER_NOT_USED(new_rom_wait_state); + FSP_PARAMETER_NOT_USED(updated_freq_hz); + +#if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (updated_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS) + { + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + } +#endif + +#if BSP_FEATURE_CGC_HAS_FLWT + if (new_rom_wait_state != R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } +#endif + +#if BSP_FEATURE_CGC_HAS_MEMWAIT + if (updated_freq_hz <= BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ) + { + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES; + } +#endif + +#if BSP_FEATURE_CGC_HAS_FLDWAITR + if (updated_freq_hz <= BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES; + } +#endif +} + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 0000000000..e2fd781def --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,262 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match SCKCR.CKSEL values. */ +#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. + +/* PLL is not supported in the following scenarios: + * - When using low voltage mode + * - When using an MCU that does not have a PLL + * - When the PLL only accepts the main oscillator as a source and XTAL is not used + */ +#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ + !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) + #define BSP_PRV_PLL_SUPPORTED (1) +#else + #define BSP_PRV_PLL_SUPPORTED (0) +#endif + +/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency + * calculated here is also used to initialize the g_clock_freq array. */ +#if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif + +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_PRV_MOCO_FREQ) +#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_PRV_LOCO_FREQ) +#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_PRV_SUBCLOCK_FREQ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #endif + #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ + (BSP_CFG_PLL_DIV + 1U)) + #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ + (BSP_CFG_PLL_DIV)) + #endif +#endif + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ +#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV) +#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV) +#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV) +#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV) +#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV) +#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV) +#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV) + +/* System clock divider options. */ +#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. +#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. +#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. +#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. +#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. +#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. +#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. +#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). + +/* USB clock divider options. */ +#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 +#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 +#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 + +/* PLL divider options. */ +#define BSP_CLOCKS_PLL_DIV_1 (0) +#define BSP_CLOCKS_PLL_DIV_2 (1) +#define BSP_CLOCKS_PLL_DIV_3 (2) +#define BSP_CLOCKS_PLL_DIV_4 (2) + +/* PLL multiplier options. */ +#define BSP_CLOCKS_PLL_MUL_8_0 (0xF) +#define BSP_CLOCKS_PLL_MUL_9_0 (0x11) +#define BSP_CLOCKS_PLL_MUL_10_0 (0x13) +#define BSP_CLOCKS_PLL_MUL_10_5 (0x14) +#define BSP_CLOCKS_PLL_MUL_11_0 (0x15) +#define BSP_CLOCKS_PLL_MUL_11_5 (0x16) +#define BSP_CLOCKS_PLL_MUL_12_0 (0x17) +#define BSP_CLOCKS_PLL_MUL_12_5 (0x18) +#define BSP_CLOCKS_PLL_MUL_13_0 (0x19) +#define BSP_CLOCKS_PLL_MUL_13_5 (0x1A) +#define BSP_CLOCKS_PLL_MUL_14_0 (0x1B) +#define BSP_CLOCKS_PLL_MUL_14_5 (0x1c) +#define BSP_CLOCKS_PLL_MUL_15_0 (0x1d) +#define BSP_CLOCKS_PLL_MUL_15_5 (0x1e) +#define BSP_CLOCKS_PLL_MUL_16_0 (0x1f) +#define BSP_CLOCKS_PLL_MUL_16_5 (0x20) +#define BSP_CLOCKS_PLL_MUL_17_0 (0x21) +#define BSP_CLOCKS_PLL_MUL_17_5 (0x22) +#define BSP_CLOCKS_PLL_MUL_18_0 (0x23) +#define BSP_CLOCKS_PLL_MUL_18_5 (0x24) +#define BSP_CLOCKS_PLL_MUL_19_0 (0x25) +#define BSP_CLOCKS_PLL_MUL_19_5 (0x26) +#define BSP_CLOCKS_PLL_MUL_20_0 (0x27) +#define BSP_CLOCKS_PLL_MUL_20_5 (0x28) +#define BSP_CLOCKS_PLL_MUL_21_0 (0x29) +#define BSP_CLOCKS_PLL_MUL_21_5 (0x2A) +#define BSP_CLOCKS_PLL_MUL_22_0 (0x2B) +#define BSP_CLOCKS_PLL_MUL_22_5 (0x2c) +#define BSP_CLOCKS_PLL_MUL_23_0 (0x2d) +#define BSP_CLOCKS_PLL_MUL_23_5 (0x2e) +#define BSP_CLOCKS_PLL_MUL_24_0 (0x2f) +#define BSP_CLOCKS_PLL_MUL_24_5 (0x30) +#define BSP_CLOCKS_PLL_MUL_25_0 (0x31) +#define BSP_CLOCKS_PLL_MUL_25_5 (0x32) +#define BSP_CLOCKS_PLL_MUL_26_0 (0x33) +#define BSP_CLOCKS_PLL_MUL_26_5 (0x34) +#define BSP_CLOCKS_PLL_MUL_27_0 (0x35) +#define BSP_CLOCKS_PLL_MUL_27_5 (0x36) +#define BSP_CLOCKS_PLL_MUL_28_0 (0x37) +#define BSP_CLOCKS_PLL_MUL_28_5 (0x38) +#define BSP_CLOCKS_PLL_MUL_29_0 (0x39) +#define BSP_CLOCKS_PLL_MUL_29_5 (0x3A) +#define BSP_CLOCKS_PLL_MUL_30_0 (0x3B) +#define BSP_CLOCKS_PLL_MUL_31_0 (0x3D) + +/* Configuration option used to disable CLKOUT output. */ +#define BSP_CLOCKS_CLKOUT_DISABLED (0xFFU) + +/* HOCO cycles per microsecond. */ +#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) + +/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ +#if BSP_HOCO_HZ < 48000000U + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) +#else + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) +#endif + +/* Create a mask of valid bits in SCKDIVCR. */ +#define BSP_PRV_SCKDIVCR_ICLK_MASK (7U << 24) +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (7U << 0) +#else + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (7U << 4) +#else + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (7U << 8) +#else + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (7U << 12) +#else + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + #define BSP_PRV_SCKDIVCR_BCLK_MASK (7U << 16) +#else + #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_SCKDIVCR_FCLK_MASK (7U << 28) +#else + #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) +#endif +#define BSP_PRV_SCKDIVCR_MASK ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) | \ + BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \ + BSP_PRV_SCKDIVCR_PCLKA_MASK) | \ + BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK) + +/* Operating power control modes. */ +#define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed +#define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed +#define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage +#define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed +#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +/* Used internally by CGC */ + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE +void bsp_prv_operating_mode_set(uint8_t operating_mode); + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED +uint32_t bsp_prv_power_change_mstp_set(void); +void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); + +#endif + +void bsp_prv_prepare_pll(uint32_t pll_freq_hz); +void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c new file mode 100644 index 0000000000..e8e73f6338 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* BSP version structure. */ +const fsp_version_t g_bsp_version = +{ + .api_version_minor = BSP_API_VERSION_MINOR, + .api_version_major = BSP_API_VERSION_MAJOR, + .code_version_major = BSP_CODE_VERSION_MAJOR, + .code_version_minor = BSP_CODE_VERSION_MINOR +}; + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the BSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_BSP_VersionGet (fsp_version_t * p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + p_version->api_version_major = BSP_API_VERSION_MAJOR; + p_version->api_version_minor = BSP_API_VERSION_MINOR; + p_version->code_version_major = BSP_CODE_VERSION_MAJOR; + p_version->code_version_minor = BSP_CODE_VERSION_MINOR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) { + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 0000000000..7d4d63a2a5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,286 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Version of this module's code and API. */ +#define BSP_CODE_VERSION_MAJOR (1U) +#define BSP_CODE_VERSION_MINOR (1U) +#define BSP_API_VERSION_MAJOR (1U) +#define BSP_API_VERSION_MINOR (0U) + +#define FSP_CONTEXT_SAVE +#define FSP_CONTEXT_RESTORE + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +/** Version data structure used by error logger macro. */ +extern const fsp_version_t g_bsp_version; + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so + * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \ + defined(__ARM_ARCH_7EM__) // CM4 + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else // CM23 + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */ +#define FSP_PRIV_SCKDIVCR_DIV_MASK (7) + +#define BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_UNIQUE_ID_OFFSET (0x14) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/** @} (end addtogroup BSP_MCU) */ + +/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_PCLKD = 0, + FSP_PRIV_CLOCK_PCLKC = 4, + FSP_PRIV_CLOCK_PCLKB = 8, + FSP_PRIV_CLOCK_PCLKA = 12, + FSP_PRIV_CLOCK_BCLK = 16, + FSP_PRIV_CLOCK_ICLK = 24, + FSP_PRIV_CLOCK_FCLK = 28, +} fsp_priv_clock_t; + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + uint32_t sckdivcr = R_SYSTEM->SCKDIVCR; + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK; + uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK; + + return (SystemCoreClock << iclk_div) >> clock_div; +} + +/*******************************************************************************************************************//** + * Get unique ID for this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet () +{ + return (bsp_unique_id_t *) ((*(uint32_t *) BSP_MCU_INFO_POINTER_LOCATION) + BSP_UNIQUE_ID_OFFSET); +} + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 0000000000..e0dfd42d06 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H +#define BSP_COMPILER_SUPPORT_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) /* AC6 compiler */ + #define BSP_SECTION_HEAP ".bss.heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) +#elif defined(__GNUC__) /* GCC compiler */ + #define BSP_SECTION_HEAP ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) +#elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_SECTION_HEAP "HEAP" + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") +#endif + +#define BSP_SECTION_STACK ".stack" +#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" +#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" +#define BSP_SECTION_ID_CODE ".id_code" + +/* Compiler neutral macros. */ +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + +#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + +#define BSP_PACKED __attribute__((aligned(1))) + +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ +#define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c new file mode 100644 index 0000000000..b8349c10fa --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,166 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_NS_PER_US (1000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n + * At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n + * Therefore one run through bsp_prv_software_delay_loop() takes: + * ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. + * A delay of 2 us therefore requires 2000ns/332ns or 6 loops. + * + * The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. + * @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. + * @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds + * + * Note that requests for very large delays will be affected by rounding in the calculations and the actual delay + * achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds. + * + * Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called + * at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the + * overhead associated with executing the code to just get to this point has certainly satisfied the requested delay. + * + * + * @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires + * that the BSP has already initialized the CGC (which it does as part of the Sysinit). + * Care should be taken to ensure this remains the case if in the future this function were to be called as part + * of the BSP initialization. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t iclk_hz; + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + uint64_t ns_64bits; + + iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + + /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution + * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting + * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single + * pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request + * will generate a minimum delay of ~200 us.*/ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. */ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt) +{ + __asm volatile ("sw_delay_loop: \n" + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs r0, #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle +#endif + + " cmp r0, #0 \n" ///< 1 cycle + +/* CM0 and CM23 have a different instruction set */ +#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne sw_delay_loop \n" ///< 2 cycles +#else + " bne.n sw_delay_loop \n" ///< 2 cycles +#endif + " bx lr \n"); ///< 2 cycles +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 0000000000..e4bbe015a3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #define BSP_DELAY_LOOP_CYCLES (4) +#endif + +/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c new file mode 100644 index 0000000000..5098697f37 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -0,0 +1,121 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_GRP_IRQ_TOTAL_ITEMS (13U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** This array holds callback functions. */ +static bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] = {0}; + +void NMI_Handler(void); +static void bsp_group_irq_call(bsp_grp_irq_t irq); + +/*******************************************************************************************************************//** + * Calls the callback function for an interrupt if a callback has been registered. + * + * @param[in] irq Which interrupt to check and possibly call. + * + * @retval FSP_SUCCESS Callback was called. + * @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source. + * + * @warning This function is called from within an interrupt + **********************************************************************************************************************/ +static void bsp_group_irq_call (bsp_grp_irq_t irq) +{ + /** Check for valid callback */ + if (NULL != g_bsp_group_irq_sources[irq]) + { + /** Callback has been found. Call it. */ + g_bsp_group_irq_sources[irq](irq); + } +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] irq Interrupt for which to register a callback. + * @param[in] p_callback Pointer to function to call when interrupt occurs. + * + * @retval FSP_SUCCESS Callback registered + * @retval FSP_ERR_ASSERTION Callback pointer is NULL + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value. */ + FSP_ASSERT(p_callback); +#endif + + /* Register callback. */ + g_bsp_group_irq_sources[irq] = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because + * there are many sources that map to the NMI exception. + **********************************************************************************************************************/ +void NMI_Handler (void) +{ + uint16_t nmisr = R_ICU->NMISR; + + /* Loop over all NMI status flags */ + for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_MPU_STACK; irq++) + { + /* If the current irq status register is set call the irq callback. */ + if (0U != (nmisr & (1U << irq))) + { + (void) bsp_group_irq_call(irq); + } + } + + /* Clear status flags that have been handled. */ + R_ICU->NMICLR = nmisr; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h new file mode 100644 index 0000000000..a51e154e5f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error + BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error + BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error + BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error + BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error +} bsp_grp_irq_t; + +/* Callback type. */ +typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_group_interrupt_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c new file mode 100644 index 0000000000..66c88ca851 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c @@ -0,0 +1,41 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 0000000000..4eec4289d6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,387 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PWPR_B0WI_OFFSET (7U) +#define BSP_IO_PWPR_PFSWE_OFFSET (6U) +#define BSP_IO_PFS_PDR_OUTPUT (4U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 +} bsp_io_port_pin_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + /* Read pin level. */ + return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + /* Set output level and pin direction to output. */ + uint32_t lvl = (uint32_t) level; + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = BSP_IO_PFS_PDR_OUTPUT | lvl; +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_pfswe_counter) + { + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + } + + /** Increment the protect counter */ + g_protect_pfswe_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_pfswe_counter) + { + /* Decrement the protect counter */ + g_protect_pfswe_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_pfswe_counter) + { + R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c new file mode 100644 index 0000000000..edd9e64fec --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 0000000000..768a84fe50 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,217 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ +#if (4U == __CORTEX_M) + NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); +#else + NVIC_SetPriority(irq, priority); +#endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 0000000000..f0c07c6fd1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +fsp_err_t R_BSP_VersionGet(fsp_version_t * p_version); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 0000000000..a70c3bd00e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,140 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ + +#define BSP_MSTP_REG_FSP_IP_GPT R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + +#define BSP_MSTP_REG_FSP_IP_DMAC R_SYSTEM->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_DTC R_SYSTEM->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_CAN R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_IRDA R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_QSPI R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIC R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBFS R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBHS R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_EPTPC R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ETHER R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_FSP_IP_SPI R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCI R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CTSU R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_FSP_IP_SLCDC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_GLCDC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_JPEG R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_DRW R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_SSI R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_FSP_IP_SRC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDHIMMC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_DOC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ELC R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_FSP_IP_TRNG R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCE R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_AES R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_AGT R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_FSP_IP_POEG R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); +#define BSP_MSTP_REG_FSP_IP_ADC R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDADC R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_FSP_IP_DAC8 R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_FSP_IP_DAC R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); +#define BSP_MSTP_REG_FSP_IP_TSN R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPHS R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPLP R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_FSP_IP_OPAMP R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c new file mode 100644 index 0000000000..e19c87250a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Used for holding reference counters for protection bits. */ +static volatile uint16_t g_protect_counters[] = +{ + 0U, 0U, 0U +}; + +/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t g_prcr_masks[] = +{ + 0x0001U, /* PRC0. */ + 0x0002U, /* PRC1. */ + 0x0008U, /* PRC3. */ +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable register protection. Registers that are protected cannot be written to. Register protection is + * enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_protect Registers which have write protection enabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Is it safe to disable write access? */ + if (0U != g_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + g_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0U == g_protect_counters[regs_to_protect]) + { + /** Enable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Disable register protection. Registers that are protected cannot be written to. Register protection is + * disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_unprotect Registers which have write protection disabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* If this is first entry then disable protection. */ + if (0U == g_protect_counters[regs_to_unprotect]) + { + /** Disable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); + } + + /** Increment the protect counter */ + g_protect_counters[regs_to_unprotect]++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 0000000000..7bd186c003 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to operating modes, low power consumption, and battery backup + * function. */ + BSP_REG_PROTECT_OM_LPC_BATT, + + /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + * LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c new file mode 100644 index 0000000000..1d1f63f93d --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** OR in the HOCO frequency setting from bsp_clock_cfg.h with the OFS1 setting from bsp_cfg.h. */ +#define BSP_ROM_REG_OFS1_SETTING \ + (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \ + ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) + +/** Build up SECMPUAC register based on MPU settings. */ +#define BSP_ROM_REG_MPU_CONTROL_SETTING \ + ((0xFFFFFCF0U) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \ + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3)) + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */ +BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) = +{ + (uint32_t) BSP_CFG_ROM_REG_OFS0, + (uint32_t) BSP_ROM_REG_OFS1_SETTING, + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU), + ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U), + (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U), + (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING +}; + +/** ID code definitions defined here. */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, +#if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, +#endif + BSP_CFG_ID_CODE_LONG_2, +#if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, +#endif + BSP_CFG_ID_CODE_LONG_3, +#if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, +#endif + BSP_CFG_ID_CODE_LONG_4 +}; + +/** @} (end addtogroup BSP_MCU) */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c new file mode 100644 index 0000000000..3425c72b70 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c @@ -0,0 +1,106 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include "bsp_api.h" +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +caddr_t _sbrk(int incr); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ + +caddr_t _sbrk (int incr) +{ + extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker. + + extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker. + + uint32_t bytes = (uint32_t) incr; + static char * current_heap_end = 0; + char * current_block_address; + + if (current_heap_end == 0) + { + current_heap_end = &_Heap_Begin; + } + + current_block_address = current_heap_end; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if (current_heap_end + bytes > &_Heap_Limit) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_heap_end += bytes; + + return (caddr_t) current_block_address; +} + +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h new file mode 100644 index 0000000000..833a1991e5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h @@ -0,0 +1,237 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA4W1 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU1 + * @note This list may change based on device. This list is for RA4W1. + * */ +typedef enum e_elc_event +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (1), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (2), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (3), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (4), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (5), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ6 = (7), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (8), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (9), // Interrupt for BLE middleware use only + ELC_EVENT_ICU_IRQ9 = (10), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ11 = (12), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ14 = (15), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (16), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (17), // DMAC transfer end 0 + ELC_EVENT_DMAC1_INT = (18), // DMAC transfer end 1 + ELC_EVENT_DMAC2_INT = (19), // DMAC transfer end 2 + ELC_EVENT_DMAC3_INT = (20), // DMAC transfer end 3 + ELC_EVENT_DTC_COMPLETE = (21), // DTC last transfer + ELC_EVENT_DTC_END = (22), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (23), // Canceling from Snooze mode + ELC_EVENT_FCU_FRDYI = (24), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (25), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_VBATT = (27), // VBATT low voltage detect + ELC_EVENT_CGC_MOSC_STOP = (28), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (29), // Snooze entry + ELC_EVENT_AGT0_INT = (30), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (31), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (32), // Compare match B + ELC_EVENT_AGT1_INT = (33), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (34), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (35), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (36), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (37), // WDT underflow + ELC_EVENT_RTC_ALARM = (38), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (39), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (40), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (41), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (42), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (43), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (44), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (45), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (46), // Compare mismatch + ELC_EVENT_ACMPLP0_INT = (47), // Analog Comparator Channel 0 interrupt + ELC_EVENT_ACMPLP1_INT = (48), // Analog Comparator Channel 1 interrupt + ELC_EVENT_USBFS_FIFO_0 = (49), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (50), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (51), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (52), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (53), // Receive data full + ELC_EVENT_IIC0_TXI = (54), // Transmit data empty + ELC_EVENT_IIC0_TEI = (55), // Transmit end + ELC_EVENT_IIC0_ERI = (56), // Transfer error + ELC_EVENT_IIC0_WUI = (57), // Slave address match + ELC_EVENT_IIC1_RXI = (58), // Receive data full + ELC_EVENT_IIC1_TXI = (59), // Transmit data empty + ELC_EVENT_IIC1_TEI = (60), // Transmit end + ELC_EVENT_IIC1_ERI = (61), // Transfer error + ELC_EVENT_SSI0_TXI = (66), // Transmit data empty + ELC_EVENT_SSI0_RXI = (67), // Receive data full + ELC_EVENT_SSI0_INT = (69), // Error interrupt + ELC_EVENT_CTSU_WRITE = (70), // Write request interrupt + ELC_EVENT_CTSU_READ = (71), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (72), // Measurement end interrupt + ELC_EVENT_KEY_INT = (73), // Key interrupt + ELC_EVENT_DOC_INT = (74), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (75), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (76), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (77), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (78), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (79), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (80), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (81), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (82), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (83), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (84), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (85), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (86), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (87), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (88), // Software event 1 + ELC_EVENT_POEG0_EVENT = (89), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (90), // Port Output disable interrupt B + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (91), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (92), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (93), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (94), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (95), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (96), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (97), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (98), // Underflow + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (99), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (100), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (101), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (102), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (103), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (104), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (105), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (106), // Underflow + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (107), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (108), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (109), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (110), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (111), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (112), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (113), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (114), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (115), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (116), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (117), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (118), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (119), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (120), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (121), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (122), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (123), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (124), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (125), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (126), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (127), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (128), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (129), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (130), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (131), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (132), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (133), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (134), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (135), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (136), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (137), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (138), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (155), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (156), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (157), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (158), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (159), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (160), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (161), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (162), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (171), // UVW edge event + ELC_EVENT_SCI0_RXI = (172), // Receive data full + ELC_EVENT_SCI0_TXI = (173), // Transmit data empty + ELC_EVENT_SCI0_TEI = (174), // Transmit end + ELC_EVENT_SCI0_ERI = (175), // Receive error + ELC_EVENT_SCI0_AM = (176), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (177), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (178), // Received data full + ELC_EVENT_SCI1_TXI = (179), // Transmit data empty + ELC_EVENT_SCI1_TEI = (180), // Transmit end + ELC_EVENT_SCI1_ERI = (181), // Receive error + ELC_EVENT_SCI1_AM = (182), // Address match event + ELC_EVENT_SCI4_RXI = (193), // Received data full + ELC_EVENT_SCI4_TXI = (194), // Transmit data empty + ELC_EVENT_SCI4_TEI = (195), // Transmit end + ELC_EVENT_SCI4_ERI = (196), // Receive error + ELC_EVENT_SCI4_AM = (197), // Address match event + ELC_EVENT_SCI9_RXI = (198), // Received data full + ELC_EVENT_SCI9_TXI = (199), // Transmit data empty + ELC_EVENT_SCI9_TEI = (200), // Transmit end + ELC_EVENT_SCI9_ERI = (201), // Receive error + ELC_EVENT_SCI9_AM = (202), // Address match event + ELC_EVENT_SPI0_RXI = (203), // Receive buffer full + ELC_EVENT_SPI0_TXI = (204), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (205), // Idle + ELC_EVENT_SPI0_ERI = (206), // Error + ELC_EVENT_SPI0_TEI = (207), // Transmission complete event + ELC_EVENT_SPI1_RXI = (208), // Receive buffer full + ELC_EVENT_SPI1_TXI = (209), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (210), // Idle + ELC_EVENT_SPI1_ERI = (211), // Error + ELC_EVENT_SPI1_TEI = (212), // Transmission complete event + ELC_EVENT_QSPI_INT = (213), // Error + ELC_EVENT_SDHIMMC0_ACCS = (214), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (215), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (216), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (217), // DMA transfer request + ELC_EVENT_SCE_PROC_BUSY = (218), + ELC_EVENT_SCE_ROMOK = (219), + ELC_EVENT_SCE_LONG_PLG = (220), + ELC_EVENT_SCE_TEST_BUSY = (221), + ELC_EVENT_SCE_WRRDY_0 = (222), + ELC_EVENT_SCE_WRRDY_4 = (223), + ELC_EVENT_SCE_RDRDY_0 = (224), + ELC_EVENT_SCE_INTEGRATE_WRRDY = (225), + ELC_EVENT_SCE_INTEGRATE_RDRDY = (226), +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA4W1) */ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h new file mode 100644 index 0000000000..47c72c8e0b --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -0,0 +1,234 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (9999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#else + #define CGC_MAINCLOCK_DRIVE (0x01U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1A0670) // 4 to 6, 9, 10, 17, 19, 20 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_SCE5 (1) +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) +#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4W1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_VERSION (3) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x13F) + +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SCI_CHANNELS (0x213U) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h new file mode 100644 index 0000000000..b6af370b91 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA4W1 RA4W1 + * @includedoc config_bsp_ra4w1_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA4W1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "../../src/bsp/mcu/ra4w1/bsp_elc.h" +#include "../../src/bsp/mcu/ra4w1/bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c new file mode 100644 index 0000000000..353bd0247e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c @@ -0,0 +1,915 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_agt.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "AGT" in ASCII, used to determine if channel is open. */ +#define AGT_OPEN (0x00414754ULL) + +#define AGT_PRV_VALID_CHANNEL_MASK (0x3U) + +#define AGT_COMPARE_MATCH_A_OUTPUT (0x03U) ///< Enabling AGTOAn pin +#define AGT_COMPARE_MATCH_B_OUTPUT (0x30U) ///< Enabling AGTOBn pin + +#define AGT_SOURCE_CLOCK_PCLKB_BITS (0x3U) + +#define FSUB_FREQUENCY_HZ (32768U) + +#define AGT_PRV_CLOCK_PCLKB_DIV_8 (1U) +#define AGT_PRV_CLOCK_PCLKB_DIV_2 (3U) + +#define AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER (2U) +#define AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH (3U) + +#define AGT_PRV_AGTCR_FORCE_STOP (0xF4U) +#define AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS (0x4U) +#define AGT_PRV_AGTCR_STATUS_FLAGS (0xF0U) +#define AGT_PRV_AGTCR_STOP_TIMER (0xF0U) +#define AGT_PRV_AGTCR_START_TIMER (0xF1U) + +#define AGT_PRV_AGTCMSR_PIN_B_OFFSET (4U) +#define AGT_PRV_AGTCMSR_VALID_BITS (0x77U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_agt_period_register_set(agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts); + +static void r_agt_hardware_cfg(agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static uint32_t r_agt_clock_frequency_get(R_AGT0_Type * p_agt_regs); + +static fsp_err_t r_agt_common_preamble(agt_instance_ctrl_t * p_instance_ctrl); + +#if AGT_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_agt_open_param_checking(agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg); + +#endif + +/* ISRs. */ +void agt_int_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Version data structure. */ +static const fsp_version_t s_agt_version = +{ + .api_version_minor = TIMER_API_VERSION_MINOR, + .api_version_major = TIMER_API_VERSION_MAJOR, + .code_version_minor = AGT_CODE_VERSION_MINOR, + .code_version_major = AGT_CODE_VERSION_MAJOR, +}; + +/* The period for channel 0 must be known to calculate the frequency of channel 1 if the count source is AGT0 + * underflow. */ +static uint32_t gp_prv_agt_periods[2]; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** AGT Implementation of General Timer Driver */ +const timer_api_t g_timer_on_agt = +{ + .open = R_AGT_Open, + .stop = R_AGT_Stop, + .start = R_AGT_Start, + .reset = R_AGT_Reset, + .enable = R_AGT_Enable, + .disable = R_AGT_Disable, + .periodSet = R_AGT_PeriodSet, + .dutyCycleSet = R_AGT_DutyCycleSet, + .infoGet = R_AGT_InfoGet, + .statusGet = R_AGT_StatusGet, + .close = R_AGT_Close, + .versionGet = R_AGT_VersionGet +}; + +/*******************************************************************************************************************//** + * @addtogroup AGT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the AGT module instance. Implements @ref timer_api_t::open. + * + * The AGT hardware does not support one-shot functionality natively. The one-shot feature is therefore implemented in + * the AGT HAL layer. For a timer configured as a one-shot timer, the timer is stopped upon the first timer expiration. + * + * The AGT implementation of the general timer can accept an optional agt_extended_cfg_t extension parameter. For + * AGT, the extension specifies the clock to be used as timer source and the output pin configurations. If the + * extension parameter is not specified (NULL), the default clock PCLKB is used and the output pins are disabled. + * + * Example: + * @snippet r_agt_example.c R_AGT_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_ALREADY_OPEN R_AGT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on AGT. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_agt_open_param_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint32_t base_address = (uint32_t) R_AGT0 + (p_cfg->channel * ((uint32_t) R_AGT1 - (uint32_t) R_AGT0)); + p_instance_ctrl->p_reg = (R_AGT0_Type *) base_address; + p_instance_ctrl->p_cfg = p_cfg; + + /* Power on the AGT channel. */ + R_BSP_MODULE_START(FSP_IP_AGT, p_cfg->channel); + + /* Forcibly stop timer and clear flags. */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS; + + /* Clear AGTMR2 before AGTMR1 is set. Reference Note 3 in section 25.2.6 "AGT Mode Register 2 (AGTMR2)" + * of the RA6M3 manual R01UH0886EJ0100. */ + p_instance_ctrl->p_reg->AGTMR2 = 0U; + + /* Set count source and divider and configure pins. */ + r_agt_hardware_cfg(p_instance_ctrl, p_cfg); + + /* Set period register and update duty cycle if output mode is used for one-shot or periodic mode. */ + r_agt_period_register_set(p_instance_ctrl, p_cfg->period_counts); + + if (p_cfg->cycle_end_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + } + + p_instance_ctrl->open = AGT_OPEN; + + /* All done. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_agt_example.c R_AGT_Start + * + * @retval FSP_SUCCESS Timer started. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start timer */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER; + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* If using output compare in one-shot mode, update the compare match registers after starting the timer. This + * ensures the output pin will not toggle again right after the period ends. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Verify the timer is started before modifying any other AGT registers. Reference section 25.4.1 "Count + * Operation Start and Stop Control" in the RA6M3 manual R01UH0886EJ0100. */ + FSP_HARDWARE_REGISTER_WAIT(1U, p_instance_ctrl->p_reg->AGTCR_b.TCSTF); + p_instance_ctrl->p_reg->AGTCMA = UINT16_MAX; + p_instance_ctrl->p_reg->AGTCMB = UINT16_MAX; + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_agt_example.c R_AGT_Stop + * + * @retval FSP_SUCCESS Timer stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Stop (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Stop timer */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to the period minus one. Implements @ref timer_api_t::reset. + * + * @retval FSP_SUCCESS Counter reset. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Reset (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Reset counter to period minus one. */ + p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_agt_example.c R_AGT_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Enable (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Reset counter to period minus one. */ + p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U); + + /* Enable captures. */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable. + * + * Example: + * @snippet r_agt_example.c R_AGT_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Disable (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable captures. */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates period. The new period is updated immediately and the counter is reset to the maximum value. Implements + * @ref timer_api_t::periodSet. + * + * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. + * If this function is called while the timer is running and an AGT underflow occurs during processing, the duty cycle + * will not be the desired 50% duty cycle until the counter underflow after processing completes. + * + * @warning Stop the timer before calling this function if one-shot output is used. + * + * Example: + * @snippet r_agt_example.c R_AGT_PeriodSet + * + * @retval FSP_SUCCESS Period value updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the period was not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + + /* Validate period parameter. */ + FSP_ASSERT(0U != period_counts); + FSP_ASSERT(period_counts <= AGT_MAX_PERIOD); +#endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set period. */ + r_agt_period_register_set(p_instance_ctrl, period_counts); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates duty cycle. If the timer is counting, the new duty cycle is reflected after the next counter underflow. + * Implements @ref timer_api_t::dutyCycleSet. + * + * Example: + * @snippet r_agt_example.c R_AGT_DutyCycleSet + * + * @retval FSP_SUCCESS Duty cycle updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the pin was not AGT_AGTO_AGTOA or AGT_AGTO_AGTOB. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle was not in the valid range of 0 to period (counts) - 1 + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + * @retval FSP_ERR_UNSUPPORTED AGT_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_AGT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + #if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT((pin == AGT_OUTPUT_PIN_AGTOA) || (pin == AGT_OUTPUT_PIN_AGTOB)); + #endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(duty_cycle_counts < (p_instance_ctrl->period), FSP_ERR_INVALID_ARGUMENT); + #endif + + uint32_t temp_duty_cycle_counts = duty_cycle_counts; + uint32_t agtcmsr_agtoab_start_level_bit = 1U << 2 << (4 * pin); + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (p_extend->agtoab_settings & agtcmsr_agtoab_start_level_bit) + { + /* Invert duty cycle if this pin starts high since the high portion is at the beginning of the cycle. */ + temp_duty_cycle_counts = p_instance_ctrl->period - temp_duty_cycle_counts; + } + + /* Set duty cycle. */ + volatile uint16_t * const p_agtcm = &p_instance_ctrl->p_reg->AGTCMA; + p_agtcm[pin] = (uint16_t) temp_duty_cycle_counts; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Gets timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_agt_example.c R_AGT_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, and frequency stored in p_info. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_info); +#endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get and store period */ + p_info->period_counts = p_instance_ctrl->period; + + /* Get and store clock frequency */ + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source) + { + /* Clock frequency is the AGT0 clock frequency divided by the period of AGT0. */ + p_info->clock_frequency = r_agt_clock_frequency_get(R_AGT0) / gp_prv_agt_periods[0]; + } + else + { + p_info->clock_frequency = r_agt_clock_frequency_get(p_instance_ctrl->p_reg); + } + + /* AGT supports only counting down direction */ + p_info->count_direction = TIMER_DIRECTION_DOWN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Retrieves the current state and counter value stores them in p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_agt_example.c R_AGT_StatusGet + * + * @retval FSP_SUCCESS Current status and counter value provided in p_status. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_status); +#endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Read the state. */ + p_status->state = (timer_state_t) p_instance_ctrl->p_reg->AGTCR_b.TCSTF; + + /* Read counter value */ + p_status->counter = p_instance_ctrl->p_reg->AGT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables interrupts, disables output pins, and clears internal driver data. Implements + * @ref timer_api_t::close. + * + * + * + * @retval FSP_SUCCESS Timer closed. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Close (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */ + + /* Stop timer */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP; + + /* Clear AGT output. */ + p_instance_ctrl->p_reg->AGTIOC = 0U; + + if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq) + { + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->cycle_end_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl); + } + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets driver version based on compile time macros. Implements @ref timer_api_t::versionGet. + * + * @retval FSP_SUCCESS Version in p_version. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_AGT_VersionGet (fsp_version_t * const p_version) +{ +#if AGT_CFG_PARAM_CHECKING_ENABLE + + /* Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + p_version->version_id = s_agt_version.version_id; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup AGT) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if AGT_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_AGT_Open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * @param[in] p_cfg Configuration structure for this instance + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_ALREADY_OPEN R_AGT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on AGT. + **********************************************************************************************************************/ +static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(AGT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Enable IRQ if user supplied a callback function, + * or if the timer is a one-shot timer (so the driver is able to + * turn off the timer after one period. */ + if ((NULL != p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) + { + /* Return error if IRQ is required and not in the vector table. */ + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + FSP_ASSERT(0U != p_cfg->period_counts); + + /* Validate period parameter. */ + FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD); + + /* Validate channel number. */ + FSP_ERROR_RETURN(((1U << p_cfg->channel) & AGT_PRV_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* AGT_CLOCK_AGT0_UNDERFLOW is not allowed on AGT channel 0. */ + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; + FSP_ASSERT((AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source) || (1U == p_cfg->channel)); + + /* Validate divider. */ + if (AGT_CLOCK_PCLKB == p_extend->count_source) + { + /* Allowed dividers for PCLKB are 1, 2, and 8. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_8); + FSP_ASSERT(p_cfg->source_div != TIMER_SOURCE_DIV_4); + } + else if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source) + { + /* Divider not used if AGT0 underflow is selected as count source. */ + FSP_ASSERT(p_cfg->source_div == TIMER_SOURCE_DIV_1); + } + else + { + /* Allowed dividers for LOCO and SUBCLOCK are 1, 2, 4, 8, 16, 32, 64, and 128. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Common code at the beginning of all AGT functions except open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * + * @retval FSP_SUCCESS No invalid conditions detected, timer state matches expected state. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +static fsp_err_t r_agt_common_preamble (agt_instance_ctrl_t * p_instance_ctrl) +{ +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Ensure timer state reflects expected status. Reference section 25.4.1 "Count Operation Start and Stop Control" + * in the RA6M3 manual R01UH0886EJ0100. */ + uint32_t agtcr_tstart = p_instance_ctrl->p_reg->AGTCR_b.TSTART; + FSP_HARDWARE_REGISTER_WAIT(agtcr_tstart, p_instance_ctrl->p_reg->AGTCR_b.TCSTF); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets count source and divider. + * + * @note Counter must be stopped before entering this function. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] p_cfg Configuration structure for this instance + **********************************************************************************************************************/ +static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Update the divider for PCLKB. */ + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; + uint32_t count_source_int = (uint32_t) p_extend->count_source; + uint32_t agtmr2 = 0U; + uint32_t agtcmsr = 0U; + uint32_t tedgsel = 0U; + uint32_t agtioc = p_extend->agtio_filter; + uint32_t mode = p_extend->measurement_mode & R_AGT0_AGTMR1_TMOD_Msk; + uint32_t edge = 0U; + if (AGT_CLOCK_PCLKB == p_extend->count_source) + { + if (TIMER_SOURCE_DIV_1 != p_cfg->source_div) + { + /* Toggle the second bit if the count_source_int is not 0 to map PCLKB / 8 to 1 and PCLKB / 2 to 3. */ + count_source_int = p_cfg->source_div ^ 2U; + count_source_int <<= R_AGT0_AGTMR1_TCK_Pos; + } + } + +#if AGT_CFG_INPUT_SUPPORT_ENABLE + else if (AGT_CLOCK_AGTIO & p_extend->count_source) + { + /* If the count source is external, configure the AGT for event counter mode. */ + mode = AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER; + count_source_int = 0U; + edge |= (p_extend->trigger_edge & R_AGT0_AGTMR1_TEDGPL_Msk); + agtioc |= (p_extend->enable_pin & R_AGT0_AGTIOC_TIOGT_Msk); + p_instance_ctrl->p_reg->AGTISR = (p_extend->enable_pin & R_AGT0_AGTISR_EEPS_Msk); + p_instance_ctrl->p_reg->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO); + } +#endif + else if (AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source) + { + /* Update the divider for LOCO/subclock. */ + agtmr2 = p_cfg->source_div; + } + else + { + /* No divider can be used when count source is AGT_CLOCK_AGT0_UNDERFLOW. */ + } + + uint32_t agtmr1 = (count_source_int | edge) | mode; + + /* Configure output settings. */ + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Set output if requested */ + agtcmsr = p_extend->agtoab_settings & AGT_PRV_AGTCMSR_VALID_BITS; + + /* Set initial duty cycle for PWM mode in open. Duty cycle is set for other modes in r_agt_period_register_set. */ + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + uint32_t inverted_duty_cycle = p_instance_ctrl->p_cfg->period_counts - + p_instance_ctrl->p_cfg->duty_cycle_counts; + uint32_t agtcma = p_instance_ctrl->p_cfg->duty_cycle_counts; + uint32_t agtcmb = p_instance_ctrl->p_cfg->duty_cycle_counts; + if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtoa) + { + agtcma = inverted_duty_cycle; + } + + if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtob) + { + agtcmb = inverted_duty_cycle; + } + + p_instance_ctrl->p_reg->AGTCMA = (uint16_t) agtcma; + p_instance_ctrl->p_reg->AGTCMB = (uint16_t) agtcmb; + } + + /* Configure TEDGSEL bit based on user input. */ + if (AGT_PIN_CFG_DISABLED != p_extend->agto) + { + /* Set the TOE bit if AGTO is enabled. AGTO can be enabled in any mode. */ + agtioc |= (1U << R_AGT0_AGTIOC_TOE_Pos); + + if (AGT_PIN_CFG_START_LEVEL_LOW == p_extend->agto) + { + /* Configure the start level of AGTO. */ + tedgsel |= (1U << R_AGT0_AGTIOC_TEDGSEL_Pos); + } + } +#endif +#if AGT_CFG_INPUT_SUPPORT_ENABLE && AGT_CFG_OUTPUT_SUPPORT_ENABLE + else +#endif +#if AGT_CFG_INPUT_SUPPORT_ENABLE + { + /* This if statement applies when p_extend->measurement_mode is AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL or + * AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL because the high level bit is in bit 4 and was masked off of mode. */ + if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == mode) + { + /* Level is stored with measurement mode for pulse width mode. */ + tedgsel = p_extend->measurement_mode >> 4U; + } + else + { + /* Use the trigger edge for pulse period or event counting modes. */ + tedgsel = (p_extend->trigger_edge & R_AGT0_AGTIOC_TEDGSEL_Msk); + } + } +#endif + + agtioc |= tedgsel; + + p_instance_ctrl->p_reg->AGTIOC = (uint8_t) agtioc; + p_instance_ctrl->p_reg->AGTCMSR = (uint8_t) agtcmsr; + p_instance_ctrl->p_reg->AGTMR1 = (uint8_t) agtmr1; + p_instance_ctrl->p_reg->AGTMR2 = (uint8_t) agtmr2; +} + +/*******************************************************************************************************************//** + * Sets period register and updates compare match registers in one-shot and periodic mode. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] period_counts AGT period in counts + **********************************************************************************************************************/ +static void r_agt_period_register_set (agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts) +{ + /* Store the period value so it can be retrieved later. */ + p_instance_ctrl->period = period_counts; + gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel] = period_counts; + + uint16_t period_reg = (uint16_t) (period_counts - 1U); + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + uint16_t duty_cycle_counts = 0U; + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = (uint16_t) (period_counts >> 1); + } + else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = period_reg; + } + else + { + /* Do nothing, duty cycle should not be updated in R_AGT_PeriodSet. */ + } + + if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->AGTCMA = duty_cycle_counts; + p_instance_ctrl->p_reg->AGTCMB = duty_cycle_counts; + } +#endif + + /* Set counter to period minus one. */ + p_instance_ctrl->p_reg->AGT = period_reg; +} + +/*******************************************************************************************************************//** + * Obtains the clock frequency of AGT for all clock sources except AGT0 underflow, with divisor applied. + * + * @param[in] p_agt_regs Registers of AGT channel used + * + * @return Source clock frequency of AGT in Hz, divider applied. + **********************************************************************************************************************/ +static uint32_t r_agt_clock_frequency_get (R_AGT0_Type * p_agt_regs) +{ + uint32_t clock_freq_hz = 0U; + uint8_t count_source_int = p_agt_regs->AGTMR1_b.TCK; + timer_source_div_t divider = TIMER_SOURCE_DIV_1; + if (0U == (count_source_int & (~AGT_SOURCE_CLOCK_PCLKB_BITS))) + { + /* Call CGC function to obtain current PCLKB clock frequency. */ + clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + + /* If Clock source is PCLKB or derived from PCLKB */ + divider = (timer_source_div_t) count_source_int; + if (0U != divider) + { + /* Set divider to 3 to divide by 8 when AGTMR1.TCK is 1 (PCLKB / 8). Set divider to 1 to divide by 2 when + * AGTMR1.TCK is 3 (PCLKB / 2). XOR with 2 to convert 1 to 3 and 3 to 1. */ + divider ^= 2U; + } + } + else + { + /* Else either fSUB clock or LOCO clock is used. The frequency is set to 32Khz (32768). This function does not + * support AGT0 underflow as count source. */ + clock_freq_hz = FSUB_FREQUENCY_HZ; + + divider = (timer_source_div_t) p_agt_regs->AGTMR2_b.CKS; + } + + clock_freq_hz >>= divider; + + return clock_freq_hz; +} + +/********************************************************************************************************************* + * AGT counter underflow interrupt. + **********************************************************************************************************************/ +void agt_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Save AGTCR to determine the source of the interrupt. */ + uint32_t agtcr = p_instance_ctrl->p_reg->AGTCR; + + /* If the channel is configured to be one-shot mode, stop the timer. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Forcibly stopping the timer resets AGTCMSR, AGTCMA, and AGTCMB. AGTCMA and AGTCMB are based on the + * timer period, but AGTCMSR must be saved so it can be restored. */ + uint8_t agtcmsr = p_instance_ctrl->p_reg->AGTCMSR; +#endif + + /* Stop timer */ + p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP; + agtcr &= AGT_PRV_AGTCR_STATUS_FLAGS; + + /* Set counter to period minus one. */ + r_agt_period_register_set(p_instance_ctrl, p_instance_ctrl->period); + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Restore AGTCMSR. */ + p_instance_ctrl->p_reg->AGTCMSR = agtcmsr; +#endif + } + + /* Invoke the callback function if it is set. */ + if (NULL != p_instance_ctrl->p_cfg->p_callback) + { + /* Setup parameters for the user-supplied callback function. */ + timer_callback_args_t callback_args; + if (agtcr & R_AGT0_AGTCR_TUNDF_Msk) + { + callback_args.event = TIMER_EVENT_CYCLE_END; + } + +#if AGT_CFG_INPUT_SUPPORT_ENABLE + else + { + callback_args.event = TIMER_EVENT_CAPTURE_A; + uint32_t reload_value = p_instance_ctrl->period - 1U; + callback_args.capture = reload_value - p_instance_ctrl->p_reg->AGT; + + /* The AGT counter is not reset in pulse width measurement mode. Reset it by software. Note that this + * will restart the counter if a new capture has already started. Application writers must ensure that + * this interrupt processing completes before the next capture begins. */ + if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == p_instance_ctrl->p_reg->AGTMR1_b.TMOD) + { + p_instance_ctrl->p_reg->AGT = (uint16_t) reload_value; + } + else + { + /* Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1 + * Reference section 25.4.5 of the RA6M3 manual R01UH0886EJ0100. */ + callback_args.capture++; + } + } +#endif + + callback_args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&callback_args); + } + + /* Clear flags in AGTCR. */ + p_instance_ctrl->p_reg->AGTCR = (uint8_t) (agtcr & ~AGT_PRV_AGTCR_STATUS_FLAGS); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c new file mode 100644 index 0000000000..2f027e1c60 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c @@ -0,0 +1,2636 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include + +#include "r_flash_lp.h" + +/* Configuration for this package. */ +#include "r_flash_lp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "OPEN" in ASCII, used to avoid multiple open. */ +#define FLASH_HP_OPEN (0x4f50454eULL) + +#define FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ 4000000U /// Minimum FCLK for Flash Operations in Hz + +/* The number of CPU cycles per each timeout loop. */ +#ifndef FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP + #if defined(__GNUC__) + #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #elif defined(__ICCARM__) + #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #endif +#endif + +#define FLASH_LP_HZ_IN_MHZ (1000000U) + +#if defined(__ICCARM__) + #define BSP_ATTRIBUTE_STACKLESS __stackless +#elif defined(__GNUC__) + + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) +#endif + +/* Roughly 4 cycles per loop */ +#define FLASH_LP_DELAY_LOOP_CYCLES 4U + +/* flash mode definition (FENTRYR Register setting)*/ +#define FLASH_LP_FENTRYR_DATAFLASH_PE_MODE (0xAA80U) +#define FLASH_LP_FENTRYR_CODEFLASH_PE_MODE (0xAA01U) +#define FLASH_LP_FENTRYR_READ_MODE (0xAA00U) + +/* flash mode definition (FPMCR Register setting)*/ +#define FLASH_LP_DATAFLASH_PE_MODE (0x10U) +#define FLASH_LP_READ_MODE (0x08U) +#define FLASH_LP_LVPE_MODE (0x40U) +#define FLASH_LP_DISCHARGE_1 (0x12U) +#define FLASH_LP_DISCHARGE_2 (0x92U) +#define FLASH_LP_CODEFLASH_PE_MODE (0x82U) + +/* operation definition (FCR Register setting)*/ +#define FLASH_LP_FCR_WRITE (0x81U) +#define FLASH_LP_FCR_ERASE (0x84U) +#define FLASH_LP_FCR_BLANKCHECK (0x83U) +#define FLASH_LP_FCR_CLEAR (0x00U) + +/* operation definition (FEXCR Register setting)*/ +#define FLASH_LP_FEXCR_STARTUP (0x81U) +#define FLASH_LP_FEXCR_AW (0x82U) +#define FLASH_LP_FEXCR_OCDID1 (0x83U) +#define FLASH_LP_FEXCR_OCDID2 (0x84U) +#define FLASH_LP_FEXCR_OCDID3 (0x85U) +#define FLASH_LP_FEXCR_OCDID4 (0x86U) +#define FLASH_LP_FEXCR_CLEAR (0x00U) +#define FLASH_LP_FEXCR_MF4_AW_STARTUP (0x82U) + +/* Wait Process definition */ +#define FLASH_LP_WAIT_TDIS (3U) +#define FLASH_LP_WAIT_TMS_MID (4U) +#define FLASH_LP_WAIT_TMS_HIGH (6U) +#define FLASH_LP_WAIT_TDSTOP (6U) + +/* Flash information */ +/* Used for DataFlash */ +#define FLASH_LP_DATAFLASH_READ_BASE_ADDR (0x40100000U) +#define FLASH_LP_DATAFLASH_WRITE_BASE_ADDR (0xFE000000U) +#define FLASH_LP_DATAFLASH_ADDR_OFFSET (FLASH_LP_DATAFLASH_WRITE_BASE_ADDR - \ + FLASH_LP_DATAFLASH_READ_BASE_ADDR) + +#define FLASH_LP_FENTRYR_DF_PE_MODE (0x0080U) +#define FLASH_LP_FENTRYR_CF_PE_MODE (0x0001U) +#define FLASH_LP_FENTRYR_PE_MODE_BITS (FLASH_LP_FENTRYR_DF_PE_MODE | FLASH_LP_FENTRYR_CF_PE_MODE) + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + #define FLASH_LP_PRV_FENTRYR R_FACI_LP->FENTRYR_MF4 +#else + #define FLASH_LP_PRV_FENTRYR R_FACI_LP->FENTRYR +#endif + +#define FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS (0xFEFFU) + +#define FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK (0x8000U) + +#define FLASH_LP_FCR_PROCESSING_MASK (0x80U) +#define FLASH_LP_FEXCR_PROCESSING_MASK (0x80U) + +#define FLASH_LP_MAX_WRITE_CF_TIME_US (1411) +#define FLASH_LP_MAX_WRITE_DF_TIME_US (886) +#define FLASH_LP_MAX_BLANK_CHECK_TIME_US (88) +#define FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US (289000) +#define FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US (299000) +#define FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US (592000) + +#define FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS (0x10) +#define FLASH_LP_FSTATR2_ERASE_ERROR_BITS (0x11) +#define FLASH_LP_FSTATR2_WRITE_ERROR_BITS 0x12 + +#define FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ (32) + +#define FLASH_LP_6BIT_MASK (0x3FU) +#define FLASH_LP_5BIT_MASK (0x1FU) + +#define FLASH_LP_DF_START_ADDRESS (0x40100000) + +#define FLASH_LP_FPR_UNLOCK 0xA5U + +/** The maximum timeout for commands is 100usec when FCLK is 16 MHz i.e. 1600 FCLK cycles. + * Assuming worst case of ICLK at 240 MHz and FCLK at 4 MHz, and optimization set to max such that + * each count decrement loop takes only 5 cycles, then ((240/4)*1600)/5 = 19200 */ +#define FLASH_LP_FRDY_CMD_TIMEOUT (19200) + +#define FLASH_LP_REGISTER_WAIT_TIMEOUT(val, reg, timeout, err) \ + while (val != reg) \ + { \ + if (0 == timeout) \ + { \ + return err; \ + } \ + timeout--; \ + } + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** + * @struct r_dataflash_data_t + * DATAFLASH information values + */ +typedef struct r_dataflash_data_t +{ + uint32_t start_addr; /* start address (Erase) or Ram Source for Write, Dest for read */ + uint32_t end_addr; /* end address (Erase), or Flash Start address which will be read/written */ + uint32_t write_cnt; /* bytes remaining to do */ +} r_dataflash_data_t; + +typedef struct r_dataflash_erase_t +{ + uint32_t start_addr; /* start address (Erase) or Ram Source for Write, Dest for read */ + uint32_t end_addr; /* end address (Erase), or Flash Start address which will be read/written */ + uint32_t write_cnt; /* bytes remaining to do */ +} r_dataflash_erase_t; + +/** FLASH operation command values */ +typedef enum e_flash_command +{ + FLASH_COMMAND_ACCESSWINDOW, /**< Flash access window command */ + FLASH_COMMAND_STARTUPAREA /**< Flash change startup area command */ +} r_flash_command_t; + +/****************************************************************************** + * Exported global variables + ******************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_flash_lp_init(flash_lp_instance_ctrl_t * p_ctrl); + +static void r_flash_lp_df_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl); + +static inline bool r_flash_lp_frdyi_df_bgo_blankcheck(flash_lp_instance_ctrl_t * p_ctrl, + flash_callback_args_t * p_cb_data); + +static inline bool r_flash_lp_frdyi_df_bgo_erase(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); + +static inline bool r_flash_lp_frdyi_df_bgo_write(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data); + +static fsp_err_t r_flash_lp_set_fisr(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_df_write_monitor(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_pe_mode_exit(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_setup(flash_lp_instance_ctrl_t * p_ctrl); + +static void r_flash_lp_df_write_operation(const uint32_t psrc_addr, uint32_t dest_addr); + +static void r_flash_lp_process_command(const uint32_t start_addr, uint32_t num_bytes, + uint32_t command) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_command_finish(uint32_t timeout) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_delay_us(uint32_t us, uint32_t mhz) PLACE_IN_RAM_SECTION __attribute__((noinline)); + +static void r_flash_lp_reset(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_write_fpmcr(uint8_t value) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_wait_for_ready(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t timeout, + uint32_t error_bits, + fsp_err_t return_code) PLACE_IN_RAM_SECTION; + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +static fsp_err_t r_flash_lp_df_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result); + +static fsp_err_t r_flash_lp_df_erase(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size); + +static fsp_err_t r_flash_lp_df_write(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const src_start_address, + uint32_t dest_start_address, + uint32_t num_bytes); + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +static void r_flash_lp_memcpy(uint8_t * const dest, uint8_t * const src, uint32_t len) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_cf_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_extra_check(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_extra_command_finish(uint32_t timeout) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_set_startup_area_boot(flash_lp_instance_ctrl_t * const p_ctrl, + flash_startup_area_swap_t swap_type, + bool temporary) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_cf_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_cf_erase(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_cf_write(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const src_start_address, + uint32_t dest_start_address, + uint32_t num_bytes) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_access_window_set(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_set_id_code(flash_lp_instance_ctrl_t * const p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_cf_write_operation(const uint32_t psrc_addr, const uint32_t dest_addr) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_extra_operation(const uint32_t start_addr_startup_value, + const uint32_t end_addr, + r_flash_command_t command) PLACE_IN_RAM_SECTION; + +#endif + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +static fsp_err_t r_flash_lp_common_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_write_read_bc_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write); + +#endif + +/** FRDY ISR is only used for DataFlash operations. For Code flash operations are blocking. Therefore ISR does + * not need to be located in RAM. + */ +void fcu_frdyi_isr(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +const flash_api_t g_flash_on_flash_lp = +{ + .open = R_FLASH_LP_Open, + .close = R_FLASH_LP_Close, + .write = R_FLASH_LP_Write, + .erase = R_FLASH_LP_Erase, + .blankCheck = R_FLASH_LP_BlankCheck, + .statusGet = R_FLASH_LP_StatusGet, + .infoGet = R_FLASH_LP_InfoGet, + .accessWindowSet = R_FLASH_LP_AccessWindowSet, + .accessWindowClear = R_FLASH_LP_AccessWindowClear, + .idCodeSet = R_FLASH_LP_IdCodeSet, + .reset = R_FLASH_LP_Reset, + .startupAreaSelect = R_FLASH_LP_StartUpAreaSelect, + .updateFlashClockFreq = R_FLASH_LP_UpdateFlashClockFreq, + .versionGet = R_FLASH_LP_VersionGet +}; + +/** Version data structure used by error logger macro. */ +static const fsp_version_t g_flash_lp_version = +{ + .api_version_minor = FLASH_API_VERSION_MINOR, + .api_version_major = FLASH_API_VERSION_MAJOR, + .code_version_major = FLASH_LP_CODE_VERSION_MAJOR, + .code_version_minor = FLASH_LP_CODE_VERSION_MINOR +}; + +/** Name of module used by error logger macro */ +#if BSP_CFG_ERROR_LOG != 0 +static const char g_module_name[] = "r_flash_lp"; +#endif + +const flash_block_info_t g_code_flash_macro_info = +{ + .block_section_st_addr = 0, + .block_section_end_addr = BSP_ROM_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE +}; + +static flash_regions_t g_flash_code_region = +{ + .num_regions = 1, + .p_block_array = &g_code_flash_macro_info +}; + +const flash_block_info_t g_data_flash_macro_info = +{ + .block_section_st_addr = FLASH_LP_DF_START_ADDRESS, + .block_section_end_addr = FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE +}; + +static flash_regions_t g_flash_data_region = +{ + .num_regions = 1, + .p_block_array = &g_data_flash_macro_info +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup FLASH_LP + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the Low Power flash peripheral. Implements @ref flash_api_t::open. + * + * The Open function initializes the Flash. + * + * This function must be called once prior to calling any other FLASH API functions. If a user supplied callback + * function is supplied, then the Flash Ready interrupt will be configured to call the users callback routine with an + * Event type describing the source of the interrupt for Data Flash operations. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Open + * + * @note Providing a callback function in the supplied p_cfg->callback field automatically configures the Flash + * for Data Flash to operate in non-blocking background operation (BGO) mode. + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl, p_cfg or p_callback if BGO is enabled. + * @retval FSP_ERR_IRQ_BSP_DISABLED Caller is requesting BGO but the Flash interrupts are not enabled. + * @retval FSP_ERR_FCLK FCLK must be a minimum of 4 MHz for Flash operations. + * @retval FSP_ERR_ALREADY_OPEN Flash Open() has already been called. + * @retval FSP_ERR_TIMEOUT Failed to exit P/E mode after configuring flash. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + + /* If null pointers return error. */ +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_ctrl); + + /* If open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN != p_ctrl->opened), FSP_ERR_ALREADY_OPEN); + + /* Background operations for data flash are enabled but the flash interrupt is disabled. */ + if (p_cfg->data_flash_bgo) + { + FSP_ERROR_RETURN(p_cfg->irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ASSERT(p_cfg->p_callback); + } +#endif + + p_ctrl->p_cfg = p_cfg; + + if (p_cfg->data_flash_bgo) + { + R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl); + } + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* Check FCLK, calculate timeout values. */ + err = r_flash_lp_setup(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + /* Set the FlashIF peripheral clock frequency. */ + err = r_flash_lp_set_fisr(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + p_ctrl->opened = FLASH_HP_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Write to the specified Code or Data Flash memory area. Implements @ref flash_api_t::write. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Write + * + * @retval FSP_SUCCESS Operation successful. If BGO is enabled this means the operation was started + * successfully. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may + * be returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU operation to complete. + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Write (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Check parameters. If failure return error */ + err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + + /* Configure the current parameters for code flash or data flash depending on address. */ + if (flash_address < BSP_ROM_SIZE_BYTES) + { + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify the source address is not in code flash. It will not be available in P/E mode. */ + FSP_ASSERT(src_address > BSP_ROM_SIZE_BYTES); + #endif + + /* Write the data */ + err = + r_flash_lp_cf_write(p_ctrl, src_address, flash_address, num_bytes); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + + /* Write the data */ + err = + r_flash_lp_df_write(p_ctrl, src_address, flash_address, num_bytes); +#endif + } + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Erase the specified Code or Data Flash blocks. Implements @ref flash_api_t::erase. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Erase + * + * @retval FSP_SUCCESS Successful open. + * @retval FSP_ERR_INVALID_BLOCKS Invalid number of blocks specified + * @retval FSP_ERR_INVALID_ADDRESS Invalid address specified + * @retval FSP_ERR_IN_USE Other flash operation in progress, or API not initialized + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU to be ready. + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If invalid number of blocks return error. */ + FSP_ERROR_RETURN(num_blocks != 0U, FSP_ERR_INVALID_BLOCKS); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + + /* Configure the current parameters based on if the operation is for code flash or data flash. */ + if (address < BSP_ROM_SIZE_BYTES) + { + uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE - 1); + + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE; + + FSP_ERROR_RETURN(start_address + num_bytes <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_BLOCKS); + #endif + + err = r_flash_lp_cf_erase(p_ctrl, start_address, num_blocks, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE - 1); + + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE; + + FSP_ERROR_RETURN((start_address >= (FLASH_LP_DF_START_ADDRESS)) && + (start_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_ADDRESS); + + FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES), + FSP_ERR_INVALID_BLOCKS); + #endif + + /* If this is a request to erase Data Flash configure BGO mode if it is enabled. */ + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_ERASE; + } + + /* Initiate the flash erase. */ + err = r_flash_lp_df_erase(p_ctrl, start_address, num_blocks, BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE); +#else + + return FSP_ERR_INVALID_ADDRESS; +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Perform a blank check on the specified address area. Implements @ref flash_api_t::blankCheck. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_BlankCheck + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in p_blank_check_result, or + * blankcheck started and in-progess (BGO mode). + * @retval FSP_ERR_INVALID_ADDRESS Invalid data flash address was input + * @retval FSP_ERR_INVALID_SIZE 'num_bytes' was either too large or not aligned for the CF/DF boundary size. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_BlankCheck (flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Check parameters. If failure return error */ + err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, address, num_bytes, false); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* Initiate the Blank Check operation */ + /* Configure the current operation and wait count based on the number of bytes and if it's a data flash or code flash operation. */ + /* Is this a request to Blank check Code Flash? */ +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if (address < BSP_ROM_SIZE_BYTES) + { + /* This is a request to Blank check Code Flash */ + err = r_flash_lp_cf_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + + /* This is a request to Blank check Data Flash */ + /* No errors in parameters. Enter Data Flash PE mode*/ + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_BLANKCHECK; + } + err = r_flash_lp_df_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result); +#endif + } + + /* If failure reset the flash. */ + /* FSP_ERR_IN_USE would indicate that a BGO operation is underway, so don't reset in that case */ + if ((FSP_SUCCESS != err) && (FSP_ERR_IN_USE != err)) + { + /* This will clear error flags and exit the P/E mode*/ + r_flash_lp_reset(p_ctrl); + } + + return err; +} + +/*******************************************************************************************************************//** + * Query the FLASH for its status. Implements @ref flash_api_t::statusGet. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_StatusGet + * + * @retval FSP_SUCCESS Flash is ready and available to accept commands. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_StatusGet (flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status) +{ + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If null status pointer return error. */ + FSP_ASSERT(p_status); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Return flash status */ + if ((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U) + { + *p_status = FLASH_STATUS_IDLE; + } + else + { + *p_status = FLASH_STATUS_BUSY; + } + + return err; +} + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory. Implements @ref flash_api_t::accessWindowSet. + * + * An access window defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on + * block boundaries. The block containing start_addr is the first block. The block containing end_addr is the last + * block. The access window then becomes first block (inclusive) --> last block (exclusive). Anything outside this range + * of Code Flash is then write protected. As an example, if you wanted to place an accesswindow on Code Flash Blocks 0 + * and 1, such that only those two blocks were writable, you would need to specify (address in block 0, address in block + * 2) as the respective start and end address. + * @note If the start address and end address are set to the same value, then the access window is effectively + * removed. This accomplishes the same functionality as R_FLASH_LP_AccessWindowClear(). + * + * The invalid address and programming boundaries supported and enforced by this function are dependent on the MCU in + * use as well as the part package size. Please see the User manual and/or requirements document for additional + * information. + * + * @param p_api_ctrl The p api control + * @param[in] start_addr The start address + * @param[in] end_addr The end address + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_INVALID_ADDRESS Invalid settings for start_addr and/or end_addr. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AccessWindowSet (flash_ctrl_t * const p_api_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Note that the end_addr indicates the address up to, but not including the block that contains that address. */ + /* Therefore to allow the very last Block to be included in the access window we must allow for FLASH_CF_BLOCK_END+1 */ + /* If the start or end addresses are invalid return error. */ + FSP_ERROR_RETURN((start_addr <= end_addr) && (end_addr <= BSP_ROM_SIZE_BYTES), FSP_ERR_INVALID_ADDRESS); + #endif + + /* Set the access window. */ + err = r_flash_lp_access_window_set(p_ctrl, start_addr, end_addr); +#else + + /* Remove warnings generated when Code Flash code is DISABLED. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(start_addr); + FSP_PARAMETER_NOT_USED(end_addr); + + /* If not code flash return error. */ + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Remove any access window that is configured in the Code Flash. Implements @ref flash_api_t::accessWindowClear. On + * successful return from this call all Code Flash is writable. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AccessWindowClear (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* If successful clear the access window. When the start address and end address are set to the same value, + * then the access window is effectively removed. */ + err = r_flash_lp_access_window_set(p_ctrl, 0, 0); +#else + + /* Return error if Code Flash not enabled. */ + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Write the ID code provided to the id code registers. Implements @ref flash_api_t::idCodeSet. + * + * @retval FSP_SUCCESS ID code successfully configured. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_IdCodeSet (flash_ctrl_t * const p_api_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify the id bytes are not in code flash. They will not be available in P/E mode. */ + FSP_ASSERT(((uint32_t) p_id_code) > BSP_ROM_SIZE_BYTES); + #endif + + /* Set the id code. */ + err = r_flash_lp_set_id_code(p_ctrl, p_id_code, mode); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_id_code); + FSP_PARAMETER_NOT_USED(mode); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Reset the FLASH peripheral. Implements @ref flash_api_t::reset. + * + * No attempt is made to check if the flash is busy before executing the reset since the assumption is that a reset + * will terminate any existing operation. + * @retval FSP_SUCCESS Flash circuit successfully reset. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Reset (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); +#endif + + /* Reset the flash. */ + r_flash_lp_reset(p_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Select which block is used as the startup area block. Implements @ref flash_api_t::startupAreaSelect. + * + * Selects which block - Default (Block 0) or Alternate (Block 1) is used as the startup area block. The provided + * parameters determine which block will become the active startup block and whether that action will be immediate (but + * temporary), or permanent subsequent to the next reset. Doing a temporary switch might appear to have limited + * usefulness. If there is an access window in place such that Block 0 is write protected, then one could do a temporary + * switch, update the block and switch them back without having to touch the access window. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. Cannot set FLASH_STARTUP_AREA_BTFLG + * when the temporary flag is false. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_StartUpAreaSelect (flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* If the swap type is BTFLG and the operation is temporary there's nothing to do. */ + FSP_ASSERT(!((swap_type == FLASH_STARTUP_AREA_BTFLG) && (is_temporary == false))); + + err = r_flash_lp_set_startup_area_boot(p_ctrl, swap_type, is_temporary); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(swap_type); + FSP_PARAMETER_NOT_USED(is_temporary); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Indicate to the already open Flash API that the FCLK has changed. Implements flash_api_t::updateFlashClockFreq. + * + * This could be the case if the application has changed the system clock, and therefore the FCLK. Failure to call this + * function subsequent to changing the FCLK could result in damage to the flash macro. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_FCLK Invalid flash clock source frequency. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_UpdateFlashClockFreq (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Check FCLK, calculate timeout values. */ + err = r_flash_lp_setup(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + /* Set the FlashIF peripheral clock frequency. */ + err = r_flash_lp_set_fisr(p_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Returns the information about the flash regions. Implements @ref flash_api_t::infoGet. + * + * @retval FSP_SUCCESS Successful retrieved the request information. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_info. + * @retval FSP_ERR_NOT_OPEN The flash is not open. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_InfoGet (flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info) +{ +#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + // todo add back the NULL != + FSP_ASSERT(p_info); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Copy the region data to the info structure. */ + p_info->code_flash = g_flash_code_region; + p_info->data_flash = g_flash_data_region; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Release any resources that were allocated by the Flash API. Implements @ref flash_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Close (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + +#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE + + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Mark the control block as closed. */ + p_ctrl->opened = 0; + + /* Disable the flash interrupt. */ + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->irq) + { + /* Disable interrupt in ICU*/ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get Flash LP driver version. + * + * @retval FSP_SUCCESS Operation performed successfully + * @retval FSP_ERR_ASSERTION Null Pointer + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_VersionGet (fsp_version_t * const p_version) +{ +#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE + + /* If null pointer return error. */ + FSP_ASSERT(p_version); +#endif + + /* Return the version id of the flash lp module. */ + p_version->version_id = g_flash_lp_version.version_id; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup FLASH_LP) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function verifies that FCLK falls within the allowable range and calculates the timeout values based on the + * current FCLK frequency. + * @param p_ctrl The p control + * @retval FSP_SUCCESS Success + * @retval FSP_ERR_FCLK FCLK must be >= 4 MHz. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_setup (flash_lp_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Get the frequency of the clock driving the flash. */ + p_ctrl->flash_clock_frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC); + + /* FCLK must be a minimum of 4 MHz for Flash operations. If not return error. */ + FSP_ERROR_RETURN(p_ctrl->flash_clock_frequency >= FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ, FSP_ERR_FCLK); + + /* Get the frequency of the system clock. */ + p_ctrl->system_clock_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + + /* Initialize the flash timeout calculations and transfer global parameters to code and data flash layers. */ + r_flash_lp_init(p_ctrl); + + /* Enable the DataFlash if not already enabled */ + if (1U != R_FACI_LP->DFLCTL) + { + R_FACI_LP->DFLCTL = 1U; + + /* Wait for (tDSTOP) before reading from data flash. */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency); + } + + return err; +} + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by Write, Read and BlankCheck functions. + * + * @param p_ctrl Pointer to the control block + * @param[in] flash_address The flash address + * @param[in] num_bytes The number bytes + * @param[in] check_write Check paramters for writing. + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_write_read_bc_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write) +{ + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If invalid address or number of bytes return error. */ + #if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 0) + FSP_PARAMETER_NOT_USED(check_write); + #else + if (flash_address < BSP_ROM_SIZE_BYTES) + { + /* If the start address is in code flash verify the end address is in code flash. */ + FSP_ERROR_RETURN(flash_address + num_bytes <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_SIZE); + + if (check_write) + { + FSP_ERROR_RETURN(!(flash_address & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(!(num_bytes & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_SIZE); + } + } + else + #endif + { + #if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + FSP_ERROR_RETURN((flash_address >= (FLASH_LP_DF_START_ADDRESS)) && + (flash_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN((flash_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_SIZE); + #else + + return FSP_ERR_INVALID_ADDRESS; + #endif + } + + /* If invalid number of bytes return error. */ + FSP_ERROR_RETURN((0 != num_bytes), FSP_ERR_INVALID_SIZE); + + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by the R_FLASH_LP_Write() function. + * @param p_ctrl Pointer to the control block + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_NOT_OPEN The flash module is not open. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_common_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + /* If the API is not ready return error. */ + FSP_ERROR_RETURN((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U, FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * This function will calculate the timeout values for various operations. + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +void r_flash_lp_init (flash_lp_instance_ctrl_t * p_ctrl) +{ + /* Round up the frequency to a whole number. */ + p_ctrl->flash_clock_frequency = (p_ctrl->flash_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) / + FLASH_LP_HZ_IN_MHZ; + + /* If the frequency is over 32MHz round up to an even number. */ +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + if ((p_ctrl->flash_clock_frequency > FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) && + (1 == p_ctrl->flash_clock_frequency % 2)) + { + p_ctrl->flash_clock_frequency++; + } +#endif + + p_ctrl->system_clock_frequency = (p_ctrl->system_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) / + FLASH_LP_HZ_IN_MHZ; + + /* According to HW Manual the Max Programming Time for 4 bytes(RA2L1) or 8 bytes(RA2A1/RA4M1)(ROM) + * is 1411us. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_cf = + (uint32_t) (FLASH_LP_MAX_WRITE_CF_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Programming Time for 1 byte + * (Data Flash) is 886us. This is with a FCLK of 4MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_df = + (uint32_t) (FLASH_LP_MAX_WRITE_DF_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Blank Check time for 2 bytes (S12*) or 8 bytes (RA2A1/RA4M1) + * (Code Flash) is 87.7 usec. This is with a FCLK of 1MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_blank_check = + (uint32_t) (FLASH_LP_MAX_BLANK_CHECK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 1KB block (S12*) or 2KB bytes (RA2A1/RA4M1) is + * around 289ms. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_cf_block = + (uint32_t) (FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 1KB Data Flash block is + * around 299ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_df_block = + (uint32_t) (FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for writing to the extra area is + * around 585ms. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_extra_area = + (uint32_t) (FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* FLWAITR should be set to 0 when the FCLK/ICLK is within the acceptable range. */ + R_FACI_LP->FLWAITR = 0U; +} + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code or Data Flash blocks + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * @param[in] block_size The Flash block size. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Erase failed. Flash could be locked or address could be under access window + * control. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_erase (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + + /* Select user area. */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* Save the current operation parameters. */ + p_ctrl->source_start_address = block_address + FLASH_LP_DATAFLASH_ADDR_OFFSET; + p_ctrl->operations_remaining = num_blocks; + + /* Start the code flash erase operation. */ + r_flash_lp_process_command(p_ctrl->source_start_address, num_blocks * block_size, FLASH_LP_FCR_ERASE); + + /* If configured for Blocking mode then don't return until the entire operation is complete */ + if (!p_ctrl->p_cfg->data_flash_bgo) + { + /* Waits for the erase commands to be completed and verifies the result of the command execution. */ + err = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_erase_df_block * num_blocks, + FLASH_LP_FSTATR2_ERASE_ERROR_BITS, + FSP_ERR_ERASE_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Disable P/E mode for data flash. */ + r_flash_lp_pe_mode_exit(p_ctrl); + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code Flash blocks + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * @param[in] block_size The Flash block size. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_cf_erase (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size) +{ + fsp_err_t err = FSP_SUCCESS; + + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* Start the code flash erase operation. */ + r_flash_lp_process_command(block_address, num_blocks * block_size, FLASH_LP_FCR_ERASE); + + /* Wait for the operation to complete. */ + err = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_erase_cf_block * num_blocks, + FLASH_LP_FSTATR2_ERASE_ERROR_BITS, + FSP_ERR_ERASE_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return r_flash_lp_pe_mode_exit(p_ctrl); +} + +#endif + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function writes a specified number of bytes to Code or Data Flash. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] src_start_address The starting address of the first byte (from source) to write. + * @param[in] dest_start_address The starting address of the Flash (to destination) to write. + * @param[in] num_bytes The number of bytes to write. + * + * @retval FSP_SUCCESS Data successfully written (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_IN_USE Command still executing. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may be + * returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the Flash sequencer to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_write (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const src_start_address, + uint32_t dest_start_address, + uint32_t num_bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + p_ctrl->dest_end_address = dest_start_address; + p_ctrl->source_start_address = src_start_address; + p_ctrl->operations_remaining = num_bytes; + + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_WRITE; + } + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + + /* Select user area. */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* Initiate the data flash write operation. */ + r_flash_lp_df_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address); + + /* If configured for Blocking mode then don't return until the entire operation is complete */ + if (!p_ctrl->p_cfg->data_flash_bgo) + { + do + { + /* Wait for the write commands to be completed and verifies the result of the command execution. */ + err = r_flash_lp_df_write_monitor(p_ctrl); + } while (FSP_ERR_IN_USE == err); + + /* Disable P/E mode for data flash. */ + if (FSP_SUCCESS == err) + { + r_flash_lp_pe_mode_exit(p_ctrl); + } + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function writes a specified number of bytes to Code Flash. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] src_start_address The starting address of the first byte (from source) to write. + * @param[in] dest_start_address The starting address of the Flash (to destination) to write. + * @param[in] num_bytes The number of bytes to write. + * + * @retval FSP_SUCCESS Data successfully written (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may be + * returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the Flash sequencer to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_cf_write (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const src_start_address, + uint32_t dest_start_address, + uint32_t num_bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + p_ctrl->dest_end_address = dest_start_address; + p_ctrl->source_start_address = src_start_address; + + /* Calculate the number of writes needed. */ + + /* This is done with right shift instead of division to avoid using the division library, which would be in flash + * and cause a jump from RAM to flash. */ + p_ctrl->operations_remaining = num_bytes / BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + + while (p_ctrl->operations_remaining && (FSP_SUCCESS == err)) + { + /* Initiate the code flash write operation. */ + r_flash_lp_cf_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address); + + /* If there is more data to write then write the next data. */ + p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + p_ctrl->dest_end_address += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + p_ctrl->operations_remaining--; + err = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_write_cf, + FLASH_LP_FSTATR2_WRITE_ERROR_BITS, + FSP_ERR_WRITE_FAILED); + } + + /* If successful exit P/E mode. */ + if (FSP_SUCCESS == err) + { + r_flash_lp_pe_mode_exit(p_ctrl); + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Execute a single Write operation on the Low Power Data Flash data. + * MF3: See Figure 10.15 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.12 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] psrc_addr Source address for data to be written. + * @param[in] dest_addr End address (read form) for writing. + **********************************************************************************************************************/ +static void r_flash_lp_df_write_operation (const uint32_t psrc_addr, uint32_t dest_addr) +{ + uint32_t dest_addr_idx; + uint8_t * data8_ptr; + data8_ptr = (uint8_t *) psrc_addr; + + dest_addr_idx = dest_addr + FLASH_LP_DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */ + + /* Write flash address setting */ + R_FACI_LP->FSARH = (uint16_t) ((dest_addr_idx >> 16)); + R_FACI_LP->FSARL = (uint16_t) (dest_addr_idx); + + /* Write data address setting */ + R_FACI_LP->FWBL0 = *data8_ptr; // For data flash there are only 8 bits used of the 16 in the reg + + /* Execute Write command */ + R_FACI_LP->FCR = FLASH_LP_FCR_WRITE; +} + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Execute a single Write operation on the Low Power Code Flash data. + * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.11 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] psrc_addr Source address for data to be written. + * @param[in] dest_addr End address (read form) for writing. + **********************************************************************************************************************/ +static void r_flash_lp_cf_write_operation (const uint32_t psrc_addr, const uint32_t dest_addr) +{ + uint16_t data[BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE / 2]; + + /* Write flash address setting */ + R_FACI_LP->FSARH = (uint16_t) ((dest_addr >> 16)); + R_FACI_LP->FSARL = (uint16_t) (dest_addr); + + /* Copy the data and write them to the flash write buffers. CM23 parts to not support unaligned access so this + * must be done using byte access. */ + r_flash_lp_memcpy((uint8_t *) data, (uint8_t *) psrc_addr, BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE); + R_FACI_LP->FWBL0 = data[0]; + R_FACI_LP->FWBH0 = data[1]; + #if BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE == 8 + R_FACI_LP->FWBL1 = data[2]; + R_FACI_LP->FWBH1 = data[3]; + #endif + + /* Execute Write command */ + R_FACI_LP->FCR = FLASH_LP_FCR_WRITE; +} + +#endif + +/*******************************************************************************************************************//** + * Waits for the write command to be completed and verifies the result of the command execution. + * + * @param[in] p_ctrl Pointer to the Flash control block + * + * @retval FSP_SUCCESS Write command successfully completed. + * @retval FSP_ERR_IN_USE Write command still in progress. + * @retval FSP_ERR_TIMEOUT Timed out waiting for write command completion. + * @retval FSP_ERR_WRITE_FAILED Write failed. Flash could be locked, area has not been erased, or address could be + * under access window control. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_write_monitor (flash_lp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t status; + + /* Wait for the data to be written. */ + status = + r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_write_df, + FLASH_LP_FSTATR2_WRITE_ERROR_BITS, + FSP_ERR_WRITE_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* If there are more blocks to write initiate another write operation. If failure return error. */ + p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE; + p_ctrl->dest_end_address += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE; + p_ctrl->operations_remaining--; + + /* If there is more data to write start the write otherwise return success. */ + if (p_ctrl->operations_remaining) + { + r_flash_lp_df_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address); + status = FSP_ERR_IN_USE; + } + else + { + status = FSP_SUCCESS; + } + + /* Return status */ + return status; +} + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function checks if the specified Data Flash address range is blank. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * @param[out] result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in result, or blankcheck started + * and in-progess (BGO mode). + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + + /* Execute blank check command. */ + r_flash_lp_process_command(start_address + FLASH_LP_DATAFLASH_ADDR_OFFSET, num_bytes, FLASH_LP_FCR_BLANKCHECK); + + /* If in DF BGO mode, exit here; remaining processing if any will be done in ISR */ + if (p_ctrl->p_cfg->data_flash_bgo) + { + *result = FLASH_RESULT_BGO_ACTIVE; + + return err; + } + + /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check. This is the same as + * the wait time for a 1 byte Data Flash blankcheck.*/ + err = + r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_blank_check * num_bytes, + FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, + FSP_ERR_BLANK_CHECK_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check the result of the blank check. */ + if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank + { + *result = FLASH_RESULT_NOT_BLANK; + } + else + { + *result = FLASH_RESULT_BLANK; + } + + /* Return the data flash to P/E mode. */ + r_flash_lp_pe_mode_exit(p_ctrl); + + /* Return status. Blank status is in result. */ + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function checks if the specified Data Flash address range is blank. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * @param[out] result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in result, or blankcheck started + * and in-progess (BGO mode). + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_cf_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) +{ + fsp_err_t err = FSP_SUCCESS; + + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + /* Give the blank check command to the FACI. */ + r_flash_lp_process_command(start_address, num_bytes, FLASH_LP_FCR_BLANKCHECK); + + /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check. + * num_bytes is divided by 4 and then multiplied to calculate the wait time for the entire operation */ + uint32_t wait_count = p_ctrl->timeout_blank_check * ((num_bytes + 3) / 4); + + /* Wait for the blank check to complete and return result in control block. */ + err = + r_flash_lp_wait_for_ready(p_ctrl, wait_count, FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, FSP_ERR_BLANK_CHECK_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank + { + /* If the result is already NOT Blank there is no reason to continue with any subsequent checks, simply return */ + *result = FLASH_RESULT_NOT_BLANK; + } + else + { + *result = FLASH_RESULT_BLANK; + } + + /* Return the flash to P/E mode. */ + err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* Return status. Blank status is in result. */ + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Initiates a flash command. + * MF3: See Figures 10.18, 10.19, 10.22 and 10.23 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figures 10.15, 10.16, 10.19 and 10.20 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] start_addr Start address of the operation. + * @param[in] num_bytes Number of bytes beginning at start_addr. + * @param[in] command The flash command + **********************************************************************************************************************/ +static void r_flash_lp_process_command (const uint32_t start_addr, uint32_t num_bytes, uint32_t command) +{ + uint32_t end_addr_idx = start_addr + (num_bytes - 1U); + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* BlankCheck start address setting */ + R_FACI_LP->FSARH = (uint16_t) ((start_addr >> 16)); + R_FACI_LP->FSARL = (uint16_t) (start_addr); + + /* BlankCheck end address setting */ + R_FACI_LP->FEARH = ((end_addr_idx >> 16)); + R_FACI_LP->FEARL = (uint16_t) (end_addr_idx); + + /* Execute BlankCheck command */ + R_FACI_LP->FCR = (uint8_t) command; +} + +/*******************************************************************************************************************//** + * This function switches the peripheral from P/E mode for Code Flash or Data Flash to Read mode. + * MF3: See Figures 10.12 and 10.13 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figures 10.9 and 10.10 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] p_ctrl Pointer to the Flash control block + * @retval FSP_SUCCESS Successfully entered P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for confirmation of transition to read mode + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_pe_mode_exit (flash_lp_instance_ctrl_t * const p_ctrl) +{ +#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + uint32_t flash_pe_mode = FLASH_LP_PRV_FENTRYR; +#endif + + /* Timeout counter. */ + volatile uint32_t wait_cnt = FLASH_LP_FRDY_CMD_TIMEOUT; + +#if BSP_FEATURE_FLASH_LP_VERSION == 3 && FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) + { + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_2); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1); + } +#endif + r_flash_lp_write_fpmcr(FLASH_LP_READ_MODE); + + /* Wait for 5us over (tMS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TMS_HIGH, p_ctrl->system_clock_frequency); + + /* Clear the P/E mode register */ + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_READ_MODE; + + /* Loop until the Flash P/E mode entry register is cleared or a timeout occurs. If timeout occurs return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, FLASH_LP_PRV_FENTRYR, wait_cnt, FSP_ERR_TIMEOUT); + +#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) + { + #if BSP_FEATURE_BSP_FLASH_CACHE + + /* Invalidate flash cache. */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; + #endif + #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 1; + #endif + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function resets the Flash sequencer. + * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.14 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +static void r_flash_lp_reset (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* Cancel any in progress BGO operation. */ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* If not currently in PE mode then enter P/E mode. */ + if (FLASH_LP_PRV_FENTRYR == 0x0000UL) + { + /* Enter P/E mode so that we can execute some FACI commands. Either Code or Data Flash P/E mode would work + * but Code Flash P/E mode requires FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE ==1, which may not be true */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + } + + /* Reset the flash. */ + R_FACI_LP->FRESETR_b.FRESET = 1U; + R_FACI_LP->FRESETR_b.FRESET = 0U; + + /* Transition to Read mode */ + r_flash_lp_pe_mode_exit(p_ctrl); +} + +/*******************************************************************************************************************//** + * Handle the FACI frdyi interrupt when the operation is Data Flash BGO write. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] p_cb_data Pointer to the Flash callback event structure. + * + * @retval true When operation is completed or error has occurred. + **********************************************************************************************************************/ +static inline bool r_flash_lp_frdyi_df_bgo_write (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data) +{ + bool operation_complete = false; + fsp_err_t result = FSP_SUCCESS; + + /* We are handling the interrupt indicating the last write operation has completed. */ + /* Whether we are done or not we want to check the status */ + + result = r_flash_lp_df_write_monitor(p_ctrl); + if ((result != FSP_SUCCESS) && (result != FSP_ERR_IN_USE)) + { + r_flash_lp_reset(p_ctrl); + p_cb_data->event = FLASH_EVENT_ERR_FAILURE; ///< Pass result back to callback + operation_complete = true; + } + else + { + /* If the operation has completed return write complete. */ + if (p_ctrl->operations_remaining == (uint32_t) 0) + { + p_cb_data->event = FLASH_EVENT_WRITE_COMPLETE; + operation_complete = true; + } + } + + return operation_complete; +} + +/*******************************************************************************************************************//** + * Handle the FACI frdyi interrupt when the operation is Data Flash BGO erase. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] p_cb_data Pointer to the Flash callback event structure. + * + * @retval true When operation is completed or error has occurred. + **********************************************************************************************************************/ +static inline bool r_flash_lp_frdyi_df_bgo_erase (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data) +{ + fsp_err_t result = FSP_SUCCESS; + + /* We are handling the interrupt indicating the last erase operation has completed. Check the status. */ + result = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_erase_df_block, + FLASH_LP_FSTATR2_ERASE_ERROR_BITS, + FSP_ERR_ERASE_FAILED); + if (result != FSP_SUCCESS) + { + r_flash_lp_reset(p_ctrl); + + /* Pass result back to callback. */ + p_cb_data->event = FLASH_EVENT_ERR_FAILURE; + } + else + { + p_cb_data->event = FLASH_EVENT_ERASE_COMPLETE; + } + + return true; +} + +/*******************************************************************************************************************//** + * Handle the FACI frdyi interrupt when the operation is Data Flash BGO blankcheck. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] p_cb_data Pointer to the Flash callback event structure. + * + * @retval true When operation is completed or error has occurred. + **********************************************************************************************************************/ +static inline bool r_flash_lp_frdyi_df_bgo_blankcheck (flash_lp_instance_ctrl_t * p_ctrl, + flash_callback_args_t * p_cb_data) +{ + fsp_err_t result = FSP_SUCCESS; + + /* We are handling the interrupt indicating the last blank check operation has completed. */ + /* Whether we are done or not we want to check the status */ + result = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_blank_check, + FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, + FSP_ERR_BLANK_CHECK_FAILED); + + /* If failure reset the flash and return failure */ + if (result != FSP_SUCCESS) + { + r_flash_lp_reset(p_ctrl); + p_cb_data->event = FLASH_EVENT_ERR_FAILURE; + } + else + { + /* Check the result and return it */ + if (R_FACI_LP->FSTATR00_b.BCERR0 == 1U) + { + p_cb_data->event = FLASH_EVENT_NOT_BLANK; + } + else + { + p_cb_data->event = FLASH_EVENT_BLANK; + } + } + + return true; +} + +/*******************************************************************************************************************//** + * FLASH ready interrupt routine. + * + * This function implements the FLASH ready isr. The function clears the interrupt request source on entry populates the + * callback structure with the relevant event, and providing a callback routine has been provided, calls the callback + * function with the event. + **********************************************************************************************************************/ +void fcu_frdyi_isr (void) +{ + FSP_CONTEXT_SAVE + flash_callback_args_t cb_data; + bool operation_completed = false; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Continue the current operation. If unknown operation set callback event to failure. */ + if (FLASH_OPERATION_DF_BGO_WRITE == p_ctrl->current_operation) + { + operation_completed = r_flash_lp_frdyi_df_bgo_write(p_ctrl, &cb_data); + } + else if ((FLASH_OPERATION_DF_BGO_ERASE == p_ctrl->current_operation)) + { + operation_completed = r_flash_lp_frdyi_df_bgo_erase(p_ctrl, &cb_data); + } + else + { + operation_completed = r_flash_lp_frdyi_df_bgo_blankcheck(p_ctrl, &cb_data); + } + + /* If the operation completed exit read mode, release the flash, and call the callback if available. */ + if (operation_completed == true) + { + /* finished current operation. Exit P/E mode*/ + r_flash_lp_pe_mode_exit(p_ctrl); + + if (NULL != p_ctrl->p_cfg->p_callback) + { + /* Set data to identify callback to user, then call user callback. */ + p_ctrl->p_cfg->p_callback(&cb_data); + } + } + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Delay for the given number of micro seconds at the given frequency + * + * @note This is used instead of R_BSP_SoftwareDelay because that may be linked in code flash. + * + * @param[in] us Number of microseconds to delay + * @param[in] mhz The frequency of the system clock + **********************************************************************************************************************/ +static void r_flash_lp_delay_us (uint32_t us, uint32_t mhz) +{ + uint32_t loop_cnt; + + // @12 MHz, one loop is 332 ns. A delay of 5 us would require 15 loops. 15 * 332 = 4980 ns or ~ 5us + + /* Calculation of a loop count */ + loop_cnt = ((us * mhz) / FLASH_LP_DELAY_LOOP_CYCLES); + + if (loop_cnt > 0U) + { + __asm volatile ("delay_loop:\n" +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs %[loops_remaining], #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub %[loops_remaining], %[loops_remaining], #1 \n" ///< 1 cycle +#endif + "cmp %[loops_remaining], #0\n" // 1 cycle + +/* CM0 and CM23 have different instruction sets */ +#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne delay_loop \n" ///< 2 cycles +#else + " bne.n delay_loop \n" ///< 2 cycles +#endif + : // No outputs + :[loops_remaining] "r" (loop_cnt) + : // No clobbers + ); + } +} + +/*******************************************************************************************************************//** + * Transition to Data Flash P/E mode. + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +void r_flash_lp_df_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl) +{ + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_DATAFLASH_PE_MODE; + + r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency); + + /* See "Procedure for changing from the read mode to the data flash P/E mode": figure 10.11 in + * SC32_FlashMemory_supplement(MF3)_20170117 and figure 10.8 in Peaks_FlashMemory_supplement(MF4)_20181105 */ +#if BSP_FEATURE_FLASH_LP_VERSION == 3 + + /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */ + if (R_SYSTEM->OPCCR_b.OPCM == 0U) + { + r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE); + } + else + { + r_flash_lp_write_fpmcr((uint8_t) FLASH_LP_DATAFLASH_PE_MODE | (uint8_t) FLASH_LP_LVPE_MODE); + } + +#elif BSP_FEATURE_FLASH_LP_VERSION == 4 + r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE); + + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); +#endif + + /* If BGO mode is enabled and interrupts are being used then enable interrupts. */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + /* We are supporting Flash Rdy interrupts for Data Flash operations. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->irq); + } +} + +/*******************************************************************************************************************//** + * Sets the FPMCR register, used to place the Flash sequencer in Code Flash P/E mode. + * @param[in] value - 8 bit value to be written to the FPMCR register. + **********************************************************************************************************************/ +static void r_flash_lp_write_fpmcr (uint8_t value) +{ + /* The procedure for writing to FPMCR is documented in section 10.2.3 of SC32_FlashMemory_supplement(MF3)_20170117 + * and Peaks_FlashMemory_supplement(MF4)_20181105 */ + R_FACI_LP->FPR = FLASH_LP_FPR_UNLOCK; + + R_FACI_LP->FPMCR = value; + R_FACI_LP->FPMCR = (uint8_t) ~value; + R_FACI_LP->FPMCR = value; + + if (value == R_FACI_LP->FPMCR) + { + __NOP(); + } +} + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory using the provided start and end address. An access window + * defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on block boundaries. The + * block containing start_addr is the first block. The block containing end_addr is the last block. The access window + * then becomes first block - last block inclusive. Anything outside this range of Code Flash is then write protected. + * This command DOES modify the configuration via The Configuration Set command to update the FAWS and FAWE. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_access_window_set (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + /* Select The Extra Area */ + R_FACI_LP->FASR_b.EXS = 1U; + + /* Set the access window. */ + r_flash_lp_extra_operation(start_addr, end_addr, FLASH_COMMAND_ACCESSWINDOW); + + /* Wait for the operation to complete or error. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + /* Return status. */ + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Set the id code + * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param p_ctrl Pointer to the instance control block + * @param p_id_code Pointer to the code to be written + * @param[in] mode The id code mode + * + * @retval FSP_SUCCESS The id code have been written. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_set_id_code (flash_lp_instance_ctrl_t * const p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t fexcr_command = FLASH_LP_FEXCR_OCDID1; + + uint16_t mode_mask = (uint16_t) mode; + + /* Update Flash state and enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + /* For each ID byte register */ + for (uint32_t i = 0U; i < 16U; i += 4U) + { + /* Select Extra Area */ + R_FACI_LP->FASR_b.EXS = 1U; + + /* Write the ID Bytes. If mode is unlocked write all 0xFF. Write the mode mask to the MSB. */ + if (FLASH_ID_CODE_MODE_UNLOCKED == mode) + { + R_FACI_LP->FWBL0 = UINT16_MAX; + R_FACI_LP->FWBH0 = UINT16_MAX; + } + else + { + /* The id code array may be unaligned. Do not attempt to optimize this code to prevent unaligned access. */ + R_FACI_LP->FWBL0 = (uint16_t) (p_id_code[i] | (p_id_code[i + 1] << 8)); + if (12U == i) + { + R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8)) | mode_mask; + } + else + { + R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8)); + } + } + + /* Execute OCDID command */ + R_FACI_LP->FEXCR = fexcr_command; + + /* Increment the command to write to the next OCDID bytes */ + fexcr_command++; + + /* Wait until the operation is complete or an error. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + + /* If failure return error */ + if (FSP_SUCCESS != err) + { + break; + } + } + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Modifies the start-up program swap flag (BTFLG) based on the supplied parameters. These changes will take effect on + * the next reset. This command DOES modify the configuration via The Configuration Set command to update the BTFLG. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] swap_type Specifies the startup area swap being requested. + * @param[in] temporary Swap blocks temporarily. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_set_startup_area_boot (flash_lp_instance_ctrl_t * const p_ctrl, + flash_startup_area_swap_t swap_type, + bool temporary) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Update Flash state and enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl); + + if (temporary) + { + /* Set the Flash initial setting startup area select bit as requested. */ + R_FACI_LP->FISR_b.SAS = swap_type; + } + else + { + /* Sets the BTFLG flag where 1 selects block 0 and 0 selects block 1. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 8); // move selection to bit 8 + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 15); // move selection to bit 15 + #endif + + /* Select Extra Area */ + R_FACI_LP->FASR_b.EXS = 1U; + + /* Call extra operation to set the startup area. */ + r_flash_lp_extra_operation(startup_area_mask, 0, FLASH_COMMAND_STARTUPAREA); + + /* Wait until the operation is complete or an error occurs. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR_b.EXS = 0U; + } + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Command processing for the extra area. + * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] start_addr_startup_value Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + * @param[in] command Select from R_FLASH_ACCESSWINDOW or R_FLASH_STARTUPAREA. + **********************************************************************************************************************/ +static void r_flash_lp_extra_operation (const uint32_t start_addr_startup_value, + const uint32_t end_addr, + r_flash_command_t command) +{ + /* Per the spec: */ + /* Setting data to the FWBL0 register, this command is allowed to select the start-up area from the */ + /* default area (blocks 0-3) to the alternative area (blocks 4-7) and set the security. */ + /* Bit 8 of the FWBL0 register is 0: the alternative area (blocks 4-7) are selected as the start-up area. */ + /* Bit 8 of the FWBL0 register is 1: the default area (blocks 0-3) are selected as the start-up area. */ + /* Bit 14 of the FWBL0 register MUST be 1! Setting this bit to zero will clear the FSPR register and lock the */ + /* FLASH!!! It is not be possible to unlock it. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + if (FLASH_COMMAND_ACCESSWINDOW == command) + { + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + R_FACI_LP->FWBL0 = (uint16_t) ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT)); + R_FACI_LP->FWBH0 = (uint16_t) ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT)); + + /* Execute Access Window command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_AW; + } + else + { + /* Startup Area Flag value setting */ + R_FACI_LP->FWBH0 = UINT16_MAX; + + /* FSPR must be set. Unused bits write value should be 1. */ + R_FACI_LP->FWBL0 = (start_addr_startup_value | FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS); + + /* Execute Startup Area Flag command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_STARTUP; + } + + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + if (FLASH_COMMAND_ACCESSWINDOW == command) + { + uint32_t fawsmr = R_FACI_LP->FAWSMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK; + uint32_t fawemr = R_FACI_LP->FAWEMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK; + + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + R_FACI_LP->FWBL0 = ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawsmr); + R_FACI_LP->FWBH0 = ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawemr); + + /* Execute Access Window command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP; + } + else + { + uint32_t fawsmr = R_FACI_LP->FAWSMR; + uint32_t fawemr = R_FACI_LP->FAWEMR & ~FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK; + + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + + /* Set the access window start address to what was in FAWSMR. */ + R_FACI_LP->FWBL0 = fawsmr; + + /* Set the access window end address to what was in FAWEMR. Set BTFLG according to user input. */ + R_FACI_LP->FWBH0 = (start_addr_startup_value | fawemr); + + /* Execute Startup Area Flag command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP; + } + #endif +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing + * bit before clearing the rest of FCR. + * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] timeout The timeout + * @retval FSP_SUCCESS The command completed successfully. + * @retval FSP_ERR_TIMEOUT The command timed out. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_extra_command_finish (uint32_t timeout) +{ + /* Timeout counter. */ + volatile uint32_t wait_cnt = timeout; + + /* If the software command of the FEXCR register is not terminated return in use. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT); + + #if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* Stop Processing */ + R_FACI_LP->FEXCR = R_FACI_LP->FEXCR & ((uint8_t) ~FLASH_LP_FEXCR_PROCESSING_MASK); + #endif + + /* Clear the Flash Extra Area Control Register. */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_CLEAR; + + wait_cnt = timeout; + + /* Wait until the command has completed or a timeout occurs. If timeout return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Verifying the execution result for the extra area. + * @param[in] p_ctrl Pointer to the Flash control block + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_extra_check (flash_lp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = r_flash_lp_extra_command_finish(p_ctrl->timeout_write_extra_area); + + /* If a timeout occurs reset the flash and return error. */ + if (FSP_ERR_TIMEOUT == err) + { + r_flash_lp_reset(p_ctrl); + + return err; + } + + /* If Extra Area Illegal Command Error Flag or Error during programming reset the flash and return error. */ + if (0 != (FLASH_LP_FSTATR2_WRITE_ERROR_BITS & R_FACI_LP->FSTATR2)) + { + r_flash_lp_reset(p_ctrl); + + return FSP_ERR_WRITE_FAILED; + } + + /* Return success. */ + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Transition to Code Flash P/E mode. + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +void r_flash_lp_cf_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* While the Flash API is in use we will disable the Flash Cache. */ + #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 0; + #endif + #if BSP_FEATURE_BSP_FLASH_CACHE + R_FCACHE->FCACHEE = 0U; + #endif + + if (p_ctrl->p_cfg->data_flash_bgo) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); // We are not supporting Flash Rdy interrupts for Code Flash operations + } + + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_CODEFLASH_PE_MODE; + + /* See "Procedure for entering code flash P/E mode": figure 10.10 in SC32_FlashMemory_supplement(MF3)_20170117 + * and figure 10.7 in Peaks_FlashMemory_supplement(MF4)_20181105. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + + uint32_t fpmcr_command1; + uint32_t fpmcr_command2; + uint32_t fpmcr_mode_setup_time; + + /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */ + if (R_SYSTEM->OPCCR_b.OPCM == 0U) + { + fpmcr_command1 = FLASH_LP_DISCHARGE_2; + fpmcr_command2 = FLASH_LP_CODEFLASH_PE_MODE; + fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_HIGH; + } + else + { + fpmcr_command1 = FLASH_LP_DISCHARGE_2 | FLASH_LP_LVPE_MODE; + fpmcr_command2 = FLASH_LP_CODEFLASH_PE_MODE | FLASH_LP_LVPE_MODE; + fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_MID; + } + + r_flash_lp_write_fpmcr((uint8_t) fpmcr_command1); + r_flash_lp_write_fpmcr((uint8_t) fpmcr_command2); + + /* Wait for 5us or 3us depending on current operating mode. (tMS) */ + r_flash_lp_delay_us(fpmcr_mode_setup_time, p_ctrl->system_clock_frequency); + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + r_flash_lp_write_fpmcr(0x02); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing + * bit before clearing the rest of FCR. + * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117 + * MF4: See Figures 10.14 and 10.15 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105 + * + * @param[in] timeout The timeout + * @retval FSP_SUCCESS The command completed successfully. + * @retval FSP_ERR_TIMEOUT The command timed out. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_command_finish (uint32_t timeout) +{ + /* Worst case timeout */ + volatile uint32_t wait = timeout; + + /* Check the Flash Ready Flag bit*/ + FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT); + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* Stop Processing */ + R_FACI_LP->FCR = R_FACI_LP->FCR & ((uint8_t) ~FLASH_LP_FCR_PROCESSING_MASK); +#endif + + /* Clear FCR register */ + R_FACI_LP->FCR = FLASH_LP_FCR_CLEAR; + + /* Worst case timeout */ + wait = timeout; + + /* Wait for the Flash Ready Flag bit to indicate ready or a timeout to occur. If timeout return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and check for error. + * + * @param p_ctrl Pointer to the control block + * @param[in] timeout The timeout + * @param[in] error_bits The error bits related to the current command + * @param[in] return_code The operation specific error code + * + * @retval FSP_SUCCESS Erase command successfully completed. + * @retval FSP_ERR_TIMEOUT Timed out waiting for erase command completion. + * @return return_code The operation specific error code. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_wait_for_ready (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t timeout, + uint32_t error_bits, + fsp_err_t return_code) +{ + fsp_err_t err = r_flash_lp_command_finish(timeout); + + /* If a timeout occurs reset the flash and return error. */ + if (FSP_ERR_TIMEOUT == err) + { + r_flash_lp_reset(p_ctrl); + + return err; + } + + /* If an error occurs reset and return error. */ + if (0U != (R_FACI_LP->FSTATR2 & error_bits)) + { + r_flash_lp_reset(p_ctrl); + + return return_code; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the flash interface peripheral clock frequency + * @param p_ctrl Pointer to the interface control block + * @retval FSP_SUCCESS Flash interface clock frequency succesfully configured. + * @retval FSP_ERR_TIMEOUT Setting the flash interface clock frequency timed out. + **********************************************************************************************************************/ +fsp_err_t r_flash_lp_set_fisr (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* Enter data flash P/E mode to enable writing to FISR. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* If the flash clock is larger than 32 increment FISR_b.PCKA by 1 for every 2MHZ. (See Section 10.2.6 "Flash + * Internal Setting Register" of the MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105) */ + if (p_ctrl->flash_clock_frequency >= FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) + { + R_FACI_LP->FISR_b.PCKA = + (0x1F + ((p_ctrl->flash_clock_frequency - FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) >> 1)) & + FLASH_LP_6BIT_MASK; + } + else +#endif + { + R_FACI_LP->FISR_b.PCKA = (p_ctrl->flash_clock_frequency - 1U) & FLASH_LP_5BIT_MASK; + } + + return r_flash_lp_pe_mode_exit(p_ctrl); +} + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Local memcpy function to prevent from using memcpy linked in code flash + * + * @param dest The destination + * @param src The source + * @param[in] len The length + **********************************************************************************************************************/ +__STATIC_INLINE void r_flash_lp_memcpy (uint8_t * const dest, uint8_t * const src, uint32_t len) +{ + for (uint32_t i = 0; i < len; i++) + { + dest[i] = src[i]; + } +} + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c new file mode 100644 index 0000000000..39bc1d9eec --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c @@ -0,0 +1,1367 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_gpt.h" +#include "r_gpt_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "GPT" in ASCII, used to determine if channel is open. */ +#define GPT_OPEN (0x00475054ULL) + +#define GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK (BSP_FEATURE_GPTEH_CHANNEL_MASK | \ + BSP_FEATURE_GPTE_CHANNEL_MASK) + +#define GPT_PRV_GTWP_RESET_VALUE (0xA500U) +#define GPT_PRV_GTWP_WRITE_PROTECT (0xA501U) + +#define GPT_PRV_GTIOR_STOP_LEVEL_BIT (6) +#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT (4) + +#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END (0x6U) +#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END (0x9U) + +#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH (0x3U) + +#define GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER (0x550000U) + +#define GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE (0x80000000U) + +#define GPT_PRV_GTCCRA (0U) +#define GPT_PRV_GTCCRB (1U) +#define GPT_PRV_GTCCRC (2U) +#define GPT_PRV_GTCCRD (3U) + +/* GPT_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */ +#define GPT_PRV_EXTRA_FEATURES_ENABLED (2U) + +#define R_GPT0_GTINTAD_ADTRAUEN_Pos (16U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Duty cycle mode. */ +typedef enum e_gpt_duty_cycle_mode +{ + GPT_DUTY_CYCLE_MODE_REGISTER = 0, // Duty cycle depends on compare match + GPT_DUTY_CYCLE_MODE_0_PERCENT = 2, // Output low + GPT_DUTY_CYCLE_MODE_100_PERCENT = 3, // Output high +} gpt_duty_cycle_mode_t; + +/* Count direction */ +typedef enum e_gpt_dir +{ + GPT_DIR_COUNT_DOWN = 0, + GPT_DIR_COUNT_UP = 1 +} gpt_dir_t; + +typedef struct st_gpt_prv_duty_registers +{ + uint32_t gtccr_buffer; + uint32_t omdty; +} gpt_prv_duty_registers_t; + +typedef enum e_gpt_prv_capture_event +{ + GPT_PRV_CAPTURE_EVENT_A, + GPT_PRV_CAPTURE_EVENT_B, +} gpt_prv_capture_event_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void gpt_hardware_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static void gpt_common_open(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static uint32_t gpt_clock_frequency_get(gpt_instance_ctrl_t * const p_instance_ctrl); + +static void gpt_hardware_events_disable(gpt_instance_ctrl_t * p_instance_ctrl); + +static void r_gpt_disable_irq(IRQn_Type irq); + +static inline void r_gpt_write_protect_enable(gpt_instance_ctrl_t * const p_instance_ctrl); +static inline void r_gpt_write_protect_disable(gpt_instance_ctrl_t * const p_instance_ctrl); + +/* Noinline attribute added to reduce code size for CM23 GCC build. */ +static void r_gpt_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context) __attribute__((noinline)); + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +static void gpt_calculate_duty_cycle(gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t const duty_cycle_counts, + gpt_prv_duty_registers_t * p_duty_reg); + +static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void gpt_counter_overflow_isr(void); +void gpt_counter_underflow_isr(void); +void gpt_capture_a_isr(void); +void gpt_capture_b_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Version data structure used by error logger macro. */ +static const fsp_version_t g_gpt_version = +{ + .api_version_minor = TIMER_API_VERSION_MINOR, + .api_version_major = TIMER_API_VERSION_MAJOR, + .code_version_major = GPT_CODE_VERSION_MAJOR, + .code_version_minor = GPT_CODE_VERSION_MINOR +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* GPT implementation of timer interface */ +const timer_api_t g_timer_on_gpt = +{ + .open = R_GPT_Open, + .stop = R_GPT_Stop, + .start = R_GPT_Start, + .reset = R_GPT_Reset, + .enable = R_GPT_Enable, + .disable = R_GPT_Disable, + .periodSet = R_GPT_PeriodSet, + .dutyCycleSet = R_GPT_DutyCycleSet, + .infoGet = R_GPT_InfoGet, + .statusGet = R_GPT_StatusGet, + .close = R_GPT_Close, + .versionGet = R_GPT_VersionGet +}; + +/*******************************************************************************************************************//** + * @addtogroup GPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * GPT hardware does not support one-shot functionality natively. When using one-shot mode, the timer will be stopped + * in an ISR after the requested period has elapsed. + * + * The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not + * NULL, but ISR is not enabled. ISR must be enabled to use one-shot mode or + * callback. + * @retval FSP_ERR_INVALID_MODE Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(0U == (p_cfg->source_div % 2U)); + #if GPT_PRV_EXTRA_FEATURES_ENABLED != GPT_CFG_OUTPUT_SUPPORT_ENABLE + FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_PWM, FSP_ERR_INVALID_MODE); + #endif + FSP_ERROR_RETURN(GPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + p_instance_ctrl->channel_mask = 1U << p_cfg->channel; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_VALID_CHANNEL_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) + { + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Callback is required if underflow interrupt is enabled. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + if (NULL != p_pwm_cfg) + { + if (p_pwm_cfg->trough_irq >= 0) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + } + #endif +#endif + + /* Initialize control structure based on configurations. */ + gpt_common_open(p_instance_ctrl, p_cfg); + + gpt_hardware_initialize(p_instance_ctrl, p_cfg); + + p_instance_ctrl->open = GPT_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop timer */ + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Start timer */ + p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to 0. Implements @ref timer_api_t::reset. + * + * @note This function also updates to the new period if no counter overflow has occurred since the last call to + * R_GPT_PeriodSet(). + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear timer counter. */ + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Enable (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint32_t gtssr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + uint32_t gtpsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + uint32_t gtcsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + + /* OR with user settings. */ + gtssr |= p_extend->start_source; + gtpsr |= p_extend->stop_source; + gtcsr |= p_extend->clear_source; + + r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set the count sources. Ensure stop and clear sources are set before start source, and capture sources are set + * after start source. */ + p_instance_ctrl->p_reg->GTPSR = gtpsr; + p_instance_ctrl->p_reg->GTCSR = gtcsr; + p_instance_ctrl->p_reg->GTSSR = gtssr; + p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source; + p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable. + * + * @note The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop(). + * + * Example: + * @snippet r_gpt_example.c R_GPT_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Disable (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + gpt_hardware_events_disable(p_instance_ctrl); + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets period value provided. If the timer is running, the period will be updated after the next counter overflow. + * If the timer is stopped, this function resets the counter and updates the period. + * Implements @ref timer_api_t::periodSet. + * + * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. + * If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle + * will not be the desired 50% duty cycle until the counter overflow after processing completes. + * + * Example: + * @snippet r_gpt_example.c R_GPT_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + /* Update period buffer register. The actual period is one cycle longer than the register value for saw waves + * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting + * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for + * triangle waves. */ + uint32_t new_gtpr = period_counts - 1U; +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + new_gtpr = period_counts; + } +#endif + + p_instance_ctrl->p_reg->GTPBR = new_gtpr; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Set a 50% duty cycle so the period of the waveform on the output pin matches the requested period. */ + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference + * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle + * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */ + uint32_t duty_cycle_50_percent = (period_counts >> 1) - 1U; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD] = duty_cycle_50_percent; + } +#endif + + /* If the counter is not counting, update period register and reset counter. */ + if (0U == p_instance_ctrl->p_reg->GTCR_b.CST) + { + p_instance_ctrl->p_reg->GTPR = new_gtpr; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER; +#endif + + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + } + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet. + * + * Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter + * overflow). + * + * Example: + * @snippet r_gpt_example.c R_GPT_DutyCycleSet + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] duty_cycle_counts Duty cycle to set in counts. + * @param[in] pin Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA or GPT_IO_PIN_GTIOCB + * + * @retval FSP_SUCCESS Duty cycle updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL or the pin is not one of gpt_io_pin_t + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle is larger than period. + * @retval FSP_ERR_UNSUPPORTED GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + #if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(pin <= GPT_IO_PIN_GTIOCA_AND_GTIOCB); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(duty_cycle_counts <= (p_instance_ctrl->p_reg->GTPR + 1), FSP_ERR_INVALID_ARGUMENT); + #endif + + /* Set duty cycle. */ + gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0}; + gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs); + + r_gpt_write_protect_disable(p_instance_ctrl); + + p_instance_ctrl->p_reg->GTCCR[pin + 2] = duty_regs.gtccr_buffer; + + /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the + * other pin. */ + + uint32_t gtuddtyc = p_instance_ctrl->p_reg->GTUDDTYC; + if (GPT_IO_PIN_GTIOCB != pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtuddtyc &= ~R_GPT0_GTUDDTYC_OADTY_Msk; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos; + } + + if (GPT_IO_PIN_GTIOCA != pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtuddtyc &= ~R_GPT0_GTUDDTYC_OBDTY_Msk; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos; + } + + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_gpt_example.c R_GPT_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's + * structure successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get and store period */ + uint32_t gtpr = p_instance_ctrl->p_reg->GTPR; + uint32_t period_counts = gtpr + 1; +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + period_counts = gtpr; + } +#endif + p_info->period_counts = period_counts; + + /* Get and store clock frequency */ + p_info->clock_frequency = gpt_clock_frequency_get(p_instance_ctrl); + + /* Get and store clock counting direction. Read count direction setting */ + p_info->count_direction = TIMER_DIRECTION_UP; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_gpt_example.c R_GPT_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value set successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get counter state. */ + p_status->state = (timer_state_t) p_instance_ctrl->p_reg->GTCR_b.CST; + + /* Get counter value */ + p_status->counter = p_instance_ctrl->p_reg->GTCNT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set counter value. + * + * @note Do not call this API while the counter is counting. The counter value can only be updated while the counter + * is stopped. + * + * @retval FSP_SUCCESS Counter value updated. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IN_USE The timer is running. Stop the timer before calling this function. + **********************************************************************************************************************/ +fsp_err_t R_GPT_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->GTCR_b.CST, FSP_ERR_IN_USE); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set counter value */ + p_instance_ctrl->p_reg->GTCNT = counter; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable output for GTIOCA and/or GTIOCB. + * + * @retval FSP_SUCCESS Output is enabled. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_OutputEnable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + uint32_t gtior = p_instance_ctrl->p_reg->GTIOR; + if (GPT_IO_PIN_GTIOCB != pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtior |= R_GPT0_GTIOR_OAE_Msk; + } + + if (GPT_IO_PIN_GTIOCA != pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtior |= R_GPT0_GTIOR_OBE_Msk; + } + + p_instance_ctrl->p_reg->GTIOR = gtior; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable output for GTIOCA and/or GTIOCB. + * + * @retval FSP_SUCCESS Output is disabled. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_OutputDisable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + uint32_t gtior = p_instance_ctrl->p_reg->GTIOR; + if (GPT_IO_PIN_GTIOCB != pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtior &= ~R_GPT0_GTIOR_OAE_Msk; + } + + if (GPT_IO_PIN_GTIOCA != pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtior &= ~R_GPT0_GTIOR_OBE_Msk; + } + + p_instance_ctrl->p_reg->GTIOR = gtior; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set A/D converter start request compare match value. + * + * @retval FSP_SUCCESS Counter value updated. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const p_ctrl, + gpt_adc_compare_match_t which_compare_match, + uint32_t compare_match_value) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set A/D converter start request compare match value. */ + volatile uint32_t * p_gtadtr = &p_instance_ctrl->p_reg->GTADTRA; + p_gtadtr[which_compare_match] = compare_match_value; + + r_gpt_write_protect_enable(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; + + r_gpt_write_protect_disable(p_instance_ctrl); + + /* Stop counter. */ + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + /* Disable output. */ + p_instance_ctrl->p_reg->GTIOR = 0U; + + r_gpt_write_protect_enable(p_instance_ctrl); + + /* Disable interrupts. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + r_gpt_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); + r_gpt_disable_irq(p_extend->capture_a_irq); + r_gpt_disable_irq(p_extend->capture_b_irq); +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + if (NULL != p_pwm_cfg) + { + r_gpt_disable_irq(p_pwm_cfg->trough_irq); + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Sets driver version based on compile time macros. Implements @ref timer_api_t::versionGet. + * + * @retval FSP_SUCCESS Version stored in p_version. + * @retval FSP_ERR_ASSERTION p_version was NULL. + **********************************************************************************************************************/ +fsp_err_t R_GPT_VersionGet (fsp_version_t * const p_version) +{ +#if GPT_CFG_PARAM_CHECKING_ENABLE + + /* Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + p_version->version_id = g_gpt_version.version_id; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup GPT) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enables write protection. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_enable (gpt_instance_ctrl_t * const p_instance_ctrl) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_WRITE_PROTECT; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * Disables write protection. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_disable (gpt_instance_ctrl_t * const p_instance_ctrl) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * Initializes control structure based on configuration. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Initialize control structure. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* If callback is not null or timer mode is one shot, make sure the IRQ is enabled and store callback in the + * control block. + * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be + * stopped and cleared using software in the ISR. *//* Determine if this is a 32-bit or a 16-bit timer. */ + p_instance_ctrl->variant = TIMER_VARIANT_16_BIT; + if (0U != (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_32BIT_CHANNEL_MASK)) + { + p_instance_ctrl->variant = TIMER_VARIANT_32_BIT; + } + + /* Save register base address. */ + uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0)); + p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address; +} + +/*******************************************************************************************************************//** + * Performs hardware initialization of the GPT. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Save pointer to extended configuration structure. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; + + /* Power on GPT before setting any hardware registers. Make sure the counter is stopped before setting mode + * register, PCLK divisor register, and counter register. */ + R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel); + + /* Initialize all registers that may affect operation of this driver to reset values. Skip these since they + * affect all channels, and are initialized in GTCR and GTCNT: GTSTR, GTSTP, GTCLR. GTCR is set immediately after + * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */ + p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE; + p_instance_ctrl->p_reg->GTCR = 0U; + p_instance_ctrl->p_reg->GTST = 0U; + p_instance_ctrl->p_reg->GTCNT = 0U; + + /* GTPR, GTCCRn, GTIOR, GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTPBR, and GTUDDTYC are set by this driver. */ + + /* Initialization sets all register required for up counting as described in hardware manual (Figure 23.4 in the + * RA6M3 manual R01UH0886EJ0100) and other registers required by the driver. */ + + /* Dividers for GPT are half the enum value. */ + uint32_t gtcr_tpcs = p_cfg->source_div >> 1; + uint32_t gtcr = gtcr_tpcs << R_GPT0_GTCR_TPCS_Pos; + + /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves + * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting + * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for + * triangle waves. */ + uint32_t gtpr = p_cfg->period_counts - 1U; +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Saw-wave PWM mode is set in GTCR.MD for all modes except TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM and + * TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM. */ + if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + gtcr |= ((uint32_t) p_cfg->mode << R_GPT0_GTCR_MD_Pos); + gtpr = p_cfg->period_counts; + } +#endif + + /* Counter must be stopped to update TPCS. Reference section 23.2.12 "General PWM Timer Control Register (GTCR)" + * in the RA6M3 manual R01UH0886EJ0100. */ + p_instance_ctrl->p_reg->GTCR = gtcr; + + gpt_hardware_events_disable(p_instance_ctrl); + + /* Configure the up/down count sources. These are not affected by enable/disable. */ + p_instance_ctrl->p_reg->GTUPSR = p_extend->count_up_source; + p_instance_ctrl->p_reg->GTDNSR = p_extend->count_down_source; + + /* Set period. The actual period is one cycle longer than the register value. Reference section 23.2.21 + * "General PWM Timer Cycle Setting Register (GTPR)". */ + p_instance_ctrl->p_reg->GTPBR = gtpr; + p_instance_ctrl->p_reg->GTPR = gtpr; + + uint32_t gtuddtyc = 0U; + uint32_t gtior = 0U; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* For one shot mode, the compare match buffer register must be loaded with a value that exceeds the timer + * cycle end value so that second compare match event would never occur and hence there will be only a + * single pulse. Writing to the upper bits is ignored for 16-bit timers. */ + gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0}; + + if (TIMER_MODE_PERIODIC == p_cfg->mode) + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference + * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle + * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */ + uint32_t duty_cycle_50_percent = (p_cfg->period_counts >> 1) - 1U; + duty_regs.gtccr_buffer = duty_cycle_50_percent; + } + + if (p_cfg->mode >= TIMER_MODE_PWM) + { + gpt_calculate_duty_cycle(p_instance_ctrl, p_cfg->duty_cycle_counts, &duty_regs); + } + + /* Set the compare match and compare match buffer registers based on previously calculated values. */ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_regs.gtccr_buffer; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD] = duty_regs.gtccr_buffer; + + /* If the requested duty cycle is 0% or 100%, set this in the registers. */ + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos; + + /* Calculate GTIOR. */ + if (p_extend->gtioca.output_enabled) + { + uint32_t gtioca_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtioca.stop_level); + gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos; + } + + if (p_extend->gtiocb.output_enabled) + { + uint32_t gtiocb_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtiocb.stop_level); + gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos; + } +#endif + +#if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK + if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK) + { + /* This register is available on GPTE and GPTEH only. It must be cleared before setting. When modifying the + * IVTT[2:0] bits, first set the IVTC[1:0] bits to 00b. Reference section 23.2.18 "General PWM Timer Interrupt + * and A/D Converter Start Request Skipping Setting Register (GTITC)"" of the RA6M3 manual R01UH0886EJ0100. */ + p_instance_ctrl->p_reg->GTITC = 0U; + } +#endif + +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + if (NULL != p_pwm_cfg) + { + p_instance_ctrl->p_reg->GTINTAD = ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) | + ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos) | + ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos); + p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up; + + /* Set GTDTCR.TDE only if one of the dead time values is non-zero. */ + uint32_t gtdtcr = ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0)); + + #if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK + if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK) + { + /* These registers are only available on GPTE and GPTEH. */ + p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT0_GTITC_IVTC_Pos) | + ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT0_GTITC_IVTT_Pos) | + ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT0_GTITC_ADTAL_Pos); + p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down; + p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match; + p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match; + } + #endif + + gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT0_GTIOR_OADF_Pos); + gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT0_GTIOR_OBDF_Pos); + + p_instance_ctrl->p_reg->GTDTCR = gtdtcr; + } + else +#endif + { + /* GTADTR* registers are unused if GTINTAD is cleared. */ + p_instance_ctrl->p_reg->GTINTAD = 0U; + p_instance_ctrl->p_reg->GTDTCR = 0U; + + /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */ + } + + /* Configure the noise filter for the GTIOC pins. */ + gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos); + gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos); + + /* Enable the compare match buffer. */ + p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + /* In one shot mode, the output pin toggles when counting starts, then again when the period expires. + * The buffer is enabled to set the compare match to UINT32_MAX after the one shot pulse is output + * so that the pin level will not change if the period expires again before the timer is stopped in + * the interrupt.*/ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0U; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0U; + } +#endif + + /* Reset counter to 0. */ + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + + /* Set the I/O control register. */ + p_instance_ctrl->p_reg->GTIOR = gtior; + + /* Configure duty cycle and force timer to count up. GTUDDTYC must be set, then cleared to force the count + * direction to be reflected when counting starts. Reference section 23.2.13 "General PWM Timer Count Direction + * and Duty Setting Register (GTUDDTYC)" in the RA6M3 manual R01UH0886EJ0100. */ + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U; + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U; + + r_gpt_write_protect_enable(p_instance_ctrl); + + /* Enable CPU interrupts if callback is not null. Also enable interrupts for one shot mode. + * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be + * stopped and cleared using software in the ISR. */ + r_gpt_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl); +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (NULL != p_pwm_cfg) + { + r_gpt_enable_irq(p_pwm_cfg->trough_irq, p_pwm_cfg->trough_ipl, p_instance_ctrl); + } +#endif +} + +/*******************************************************************************************************************//** + * Disables hardware events that would cause the timer to start, stop, clear, or capture. + * + * @param[in] p_instance_ctrl Instance control structure + **********************************************************************************************************************/ +static void gpt_hardware_events_disable (gpt_instance_ctrl_t * p_instance_ctrl) +{ + /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */ + p_instance_ctrl->p_reg->GTSSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTPSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTCSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTICASR = GPT_SOURCE_NONE; + p_instance_ctrl->p_reg->GTICBSR = GPT_SOURCE_NONE; +} + +/*******************************************************************************************************************//** + * Disables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +static void r_gpt_disable_irq (IRQn_Type irq) +{ + /* Disable interrupts. */ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Configures and enables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +static void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, priority, p_context); + } +} + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Calculates duty cycle register values. GTPR must be set before entering this function. + * + * @param[in] p_instance_ctrl Instance control structure + * @param[in] duty_cycle_counts Duty cycle to set + * @param[out] p_duty_reg Duty cycle register values + **********************************************************************************************************************/ +static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t const duty_cycle_counts, + gpt_prv_duty_registers_t * p_duty_reg) +{ + /* 0% and 100% duty cycle are supported in OADTY/OBDTY. */ + uint32_t current_period = p_instance_ctrl->p_reg->GTPR; + if (0U == duty_cycle_counts) + { + p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT; + } + else if (duty_cycle_counts >= current_period) + { + p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_100_PERCENT; + } + else + { + uint32_t temp_duty_cycle = duty_cycle_counts; + + /* When the GPT_SHORTEST_LEVEL_ON is set, the high part of the PWM wave is at the end of the cycle. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal) + { + temp_duty_cycle = current_period - temp_duty_cycle; + } + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + p_duty_reg->gtccr_buffer = temp_duty_cycle; + } + else + #endif + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference + * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. */ + temp_duty_cycle--; + p_duty_reg->gtccr_buffer = temp_duty_cycle; + } + } +} + +#endif + +/*******************************************************************************************************************//** + * Calculates clock frequency of GPT counter. Divides GPT clock by GPT clock divisor. + * + * @param[in] p_instance_ctrl Instance control block + * + * @return Clock frequency of the GPT counter. + **********************************************************************************************************************/ +static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl) +{ + /* Look up PCLKD frequency and divide it by GPT PCLKD divider. */ + timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS << 1); + uint32_t pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD); + + return pclk_freq_hz >> pclk_divisor; +} + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Calculates GTIOR settings for given mode and stop level. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] p_cfg Timer configuration + * @param[in] level Output level after timer stops + **********************************************************************************************************************/ +static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level) +{ + /* The stop level is used as both the initial level and the stop level. */ + uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << GPT_PRV_GTIOR_STOP_LEVEL_BIT) | + ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT); + + uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END; + gpt_pin_level_t compare_match = GPT_PIN_LEVEL_LOW; + + if (TIMER_MODE_PWM == p_cfg->mode) + { + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; + if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal) + { + /* Output high after compare match when GPT_SHORTEST_LEVEL_ON is used to generate the shortest PWM duty cycle. */ + compare_match = GPT_PIN_LEVEL_HIGH; + } + } + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + else if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH; + } + #endif + else + { + /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts counting). */ + if (GPT_PIN_LEVEL_LOW == stop_level) + { + compare_match = GPT_PIN_LEVEL_HIGH; + } + } + + if (compare_match == GPT_PIN_LEVEL_HIGH) + { + gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END; + } + + gtior |= gtion; + + return gtior; +} + +#endif + +/*******************************************************************************************************************//** + * Common processing for input capture interrupt. + * + * @param[in] event Which input capture event occurred + **********************************************************************************************************************/ +static void r_gpt_capture_common_isr (gpt_prv_capture_event_t event) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Get captured value. */ + uint32_t counter = p_instance_ctrl->p_reg->GTCCR[event]; + + /* If we captured a one-shot pulse, then disable future captures. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Disable captures. */ + gpt_hardware_events_disable(p_instance_ctrl); + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + } + + /* If a callback is provided, then call it with the captured counter value. */ + if (NULL != p_instance_ctrl->p_cfg->p_callback) + { + timer_callback_args_t callback_args; + callback_args.event = (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event); + callback_args.capture = counter; + callback_args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&callback_args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_counter_overflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* If one-shot mode is selected, stop the timer since period has expired. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + r_gpt_write_protect_disable(p_instance_ctrl); + + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */ + p_instance_ctrl->p_reg->GTCNT = 0; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0; + + r_gpt_write_protect_enable(p_instance_ctrl); + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + } + + if (NULL != p_instance_ctrl->p_cfg->p_callback) + { + /* Set data to identify callback to user, then call user callback. */ + timer_callback_args_t callback_args; + callback_args.p_context = p_instance_ctrl->p_cfg->p_context; + callback_args.event = TIMER_EVENT_CYCLE_END; + p_instance_ctrl->p_cfg->p_callback(&callback_args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Only supported for asymmetric triangle-wave PWM. Notifies application of trough event. + **********************************************************************************************************************/ +void gpt_counter_underflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Set data to identify callback to user, then call user callback. */ + timer_callback_args_t callback_args; + callback_args.p_context = p_instance_ctrl->p_cfg->p_context; + callback_args.event = TIMER_EVENT_TROUGH; + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +/*******************************************************************************************************************//** + * Interrupt triggered by a capture A source. + * + * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_capture_a_isr (void) +{ + r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_A); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a capture B source. + * + * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_capture_b_isr (void) +{ + r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_B); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c new file mode 100644 index 0000000000..c23457f418 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c @@ -0,0 +1,301 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_icu.h" +#include "r_icu_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "ICU" in ASCII, used to determine if channel is open. */ +#define ICU_OPEN (0x00494355U) + +#define ICU_IRQMD_OFFSET (0) +#define ICU_FCLKSEL_OFFSET (4) +#define ICU_FLTEN_OFFSET (7) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void r_icu_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Version data structure used by error logger macro. */ +static const fsp_version_t g_icu_version = +{ + .api_version_minor = EXTERNAL_IRQ_API_VERSION_MINOR, + .api_version_major = EXTERNAL_IRQ_API_VERSION_MAJOR, + .code_version_major = ICU_CODE_VERSION_MAJOR, + .code_version_minor = ICU_CODE_VERSION_MINOR +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* ICU implementation of External IRQ API. */ +const external_irq_api_t g_external_irq_on_icu = +{ + .open = R_ICU_ExternalIrqOpen, + .enable = R_ICU_ExternalIrqEnable, + .disable = R_ICU_ExternalIrqDisable, + .close = R_ICU_ExternalIrqClose, + .versionGet = R_ICU_ExternalIrqVersionGet +}; + +/*******************************************************************************************************************//** + * @addtogroup ICU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure an IRQ input pin for use with the external interrupt interface. Implements @ref external_irq_api_t::open. + * + * The Open function is responsible for preparing an external IRQ pin for operation. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION One of the following is invalid: + * - p_ctrl or p_cfg is NULL + * @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. No configurations were changed. + * Call the associated Close function to reconfigure the channel. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in + * r_bsp_cfg.h. + * @retval FSP_ERR_INVALID_ARGUMENT p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to + * use callback function. + * + * @note This function is reentrant for different channels. It is not reentrant for the same channel. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Callback must be used with a valid interrupt priority otherwise it will never be called. */ + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + p_ctrl->irq = p_cfg->irq; + + /* IELSR Must be zero when modifying the IRQCR bits. + * (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */ + uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq]; + R_ICU->IELSR[p_ctrl->irq] = 0; + + /* Initialize control block. */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->channel = p_cfg->channel; + + /* Disable digital filter */ + R_ICU->IRQCR[p_ctrl->channel] = 0U; + + /* Set the digital filter divider. */ + uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET); + + /* Enable/Disable digital filter. */ + irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET); + + /* Set the IRQ trigger. */ + irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET); + + /* Write IRQCR */ + R_ICU->IRQCR[p_ctrl->channel] = irqcr; + + /* Restore IELSR. */ + R_ICU->IELSR[p_ctrl->irq] = ielsr; + + /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases + * where the external IRQ driver is used to generate ELC events only (without CPU interrupts). + * In such cases we will not set the IRQ priority but will continue with the processing. + */ + if (p_ctrl->irq >= 0) + { + R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl); + } + + /* Mark the control block as open */ + p_ctrl->open = ICU_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable. + * + * @retval FSP_SUCCESS Interrupt Enabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#endif + + /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */ + R_BSP_IrqEnable(p_ctrl->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable. + * + * @retval FSP_SUCCESS Interrupt disabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#endif + + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + R_BSP_IrqDisable(p_ctrl->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close the external interrupt channel. Implements @ref external_irq_api_t::close. + * + * @retval FSP_SUCCESS Successfully closed. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Cleanup. Disable interrupt */ + if (p_ctrl->irq >= 0) + { + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + R_BSP_IrqDisable(p_ctrl->irq); + R_FSP_IsrContextSet(p_ctrl->irq, NULL); + } + + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set driver version based on compile time macros. Implements @ref external_irq_api_t::versionGet. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqVersionGet (fsp_version_t * const p_version) +{ +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_version); +#endif + + p_version->version_id = g_icu_version.version_id; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ICU) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * ICU External Interrupt ISR. + **********************************************************************************************************************/ +void r_icu_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + bool level_irq = false; + if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD) + { + level_irq = true; + } + else + { + /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active + * it will not be missed. */ + R_BSP_IrqStatusClear(irq); + } + + if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback)) + { + /* Set data to identify callback to user, then call user callback. */ + external_irq_callback_args_t args; + args.channel = p_ctrl->channel; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + + if (level_irq) + { + /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not + * be called again. */ + R_BSP_IrqStatusClear(irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c new file mode 100644 index 0000000000..a80edb1b3f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c @@ -0,0 +1,909 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Mask to get PSEL bitfield from PFS register. */ +#define BSP_PRV_PFS_PSEL_MASK (0x1F000000UL) + +/* Shift to get pin 0 on a package in extended data. */ +#define IOPORT_PRV_EXISTS_B0_SHIFT (16UL) + +/* Mask to determine if any pins on port exist on this package. */ +#define IOPORT_PRV_PORT_EXISTS_MASK (0xFFFF0000U) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#ifndef BSP_MCU_VBATT_SUPPORT + #define BSP_MCU_VBATT_SUPPORT (0U) +#endif + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +#define IOPORT_PRV_PCNTR_OFFSET 0x00000020U + +#define IOPORT_PRV_PERIPHERAL_FUNCTION (1U << 16) +#define IOPORT_PRV_CLEAR_BITS_MASK (0x1F01FCD5U) ///< Zero bits in mask must be written as zero to PFS register + +#define IOPORT_PRV_8BIT_MASK (0xFFU) +#define IOPORT_PRV_16BIT_MASK (0xFFFFU) +#define IOPORT_PRV_UPPER_16BIT_MASK (0xFFFF0000U) +#define IOPORT_PRV_PFENET_MASK (0x30U) + +#define IOPORT_PRV_SET_PWPR_PFSWE (0x40U) +#define IOPORT_PRV_SET_PWPR_BOWI (0x80U) + +#define IOPORT_PRV_PORT_ADDRESS(port_number) ((uint32_t) (R_PORT1 - R_PORT0) * (port_number) + R_PORT0) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); + +static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port, + ioport_size_t set_value, + ioport_size_t reset_value, + bsp_io_level_t pin_level); + +static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value); + +#if BSP_MCU_VBATT_SUPPORT +static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Version data structure used by error logger macro. */ +static const fsp_version_t g_ioport_version = +{ + .api_version_minor = IOPORT_API_VERSION_MINOR, + .api_version_major = IOPORT_API_VERSION_MAJOR, + .code_version_major = IOPORT_CODE_VERSION_MAJOR, + .code_version_minor = IOPORT_CODE_VERSION_MINOR +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinEthernetModeCfg = R_IOPORT_EthernetModeCfg, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, + .versionGet = R_IOPORT_VersionGet, +}; + +#if BSP_MCU_VBATT_SUPPORT +static const bsp_io_port_pin_t g_vbatt_pins_input[] = +{ + BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN + BSP_IO_PORT_04_PIN_03, ///< Associated with VBTICTLR->VCH1INEN + BSP_IO_PORT_04_PIN_04 ///< Associated with VBTICTLR->VCH2INEN +}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into pin PFS registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of PmnPFS registers with the supplied values. This data can be generated + * by the Pins tab of the RA Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if BSP_MCU_VBATT_SUPPORT + + /* Create temporary structure for handling VBATT pins. */ + ioport_cfg_t temp_cfg; + ioport_pin_cfg_t temp_pin_cfg; + + temp_pin_cfg.pin = pin; + temp_pin_cfg.pin_cfg = cfg; + + temp_cfg.number_of_pins = 1U; + temp_cfg.p_pin_cfg_data = &temp_pin_cfg; + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(&temp_cfg); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pfs_write(pin, cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of PCNTR2 register for the specified port */ + *p_port_value = p_ioport_regs->PCNTR2 & IOPORT_PRV_16BIT_MASK; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different ports. This function makes use of the PCNTR3 register to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits; + ioport_size_t clrbits; + + /* High bits */ + setbits = value & mask; + + /* Low bits */ + /* Cast to ensure size */ + clrbits = (ioport_size_t) ((~value) & mask); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opene + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different pins. This function makes use of the PCNTR3 register to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits = 0U; + ioport_size_t clrbits = 0U; + bsp_io_port_t port = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + + ioport_size_t shift = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin; + ioport_size_t pin_mask = (ioport_size_t) (1U << shift); + + if (BSP_IO_LEVEL_LOW == level) + { + clrbits = pin_mask; + } + else + { + setbits = pin_mask; + } + + /* PCNTR register is updated instead of using PFS as access is atomic and PFS requires seperate enable/disable + * using PWPR register */ + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + ioport_size_t orig_value; + ioport_size_t set_bits; + ioport_size_t clr_bits; + ioport_size_t write_value; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of PCNTR1 register for the specified port */ + orig_value = p_ioport_regs->PCNTR1 & IOPORT_PRV_16BIT_MASK; + + /* High bits */ + set_bits = direction_values & mask; + + /* Low bits */ + /* Cast to ensure size */ + clr_bits = (ioport_size_t) ((~direction_values) & mask); + + /* New value to write to port direction register */ + write_value = orig_value; + write_value |= set_bits; + + /* Cast to ensure size */ + write_value &= (ioport_size_t) (~clr_bits); + + p_ioport_regs->PCNTR1 = write_value & IOPORT_PRV_16BIT_MASK; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(port >> IOPORT_PRV_PORT_OFFSET & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + *p_event_data = p_ioport_regs->PCNTR2_b.EIDR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + * + * @note This function is re-entrant. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ + ioport_size_t portvalue; + ioport_size_t mask; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((pin >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + portvalue = p_ioport_regs->PCNTR2_b.EIDR; + mask = (ioport_size_t) (1U << (IOPORT_PRV_PIN_BITS & (bsp_io_port_t) pin)); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ + ioport_size_t set_bits; + ioport_size_t reset_bits; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + set_bits = event_data & mask_value; + + /* Cast to ensure size */ + reset_bits = (ioport_size_t) ((~event_data) & mask_value); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* PCNTR4 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR4 = (uint32_t) (((uint32_t) reset_bits << 16) | set_bits); + + return FSP_SUCCESS; +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t set_bits; + ioport_size_t reset_bits; + bsp_io_port_t port; + uint16_t pin_to_port; + + /* Cast to ensure correct conversion of parameter. */ + pin_to_port = (uint16_t) pin; + pin_to_port = pin_to_port & (uint16_t) IOPORT_PRV_PORT_BITS; + port = (bsp_io_port_t) pin_to_port; + set_bits = (ioport_size_t) 0; + reset_bits = (ioport_size_t) 0; + + if (BSP_IO_LEVEL_HIGH == pin_value) + { + /* Cast to ensure size */ + set_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS)); + } + else + { + /* Cast to ensure size */ + reset_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS)); + } + + r_ioport_hw_pin_event_output_data_write(port, set_bits, reset_bits, pin_value); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns IOPort HAL driver version. Implements @ref ioport_api_t::versionGet. + * + * @retval FSP_SUCCESS Version information read + * @retval FSP_ERR_ASSERTION The parameter p_data is NULL + * + * @note This function is reentrant. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_VersionGet (fsp_version_t * p_data) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + + /* Verify parameters are valid */ + FSP_ASSERT(NULL != p_data); +#endif + + *p_data = g_ioport_version; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg. + * + * @retval FSP_SUCCESS Ethernet PHY mode set + * @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid + * @retval FSP_ERR_UNSUPPORTED Ethernet configuration not supported on this device. + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is not re-entrant. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl, + ioport_ethernet_channel_t channel, + ioport_ethernet_mode_t mode) +{ + FSP_ERROR_RETURN(1U == BSP_FEATURE_IOPORT_HAS_ETHERNET, FSP_ERR_UNSUPPORTED); + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(channel < IOPORT_ETHERNET_CHANNEL_END, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(mode < IOPORT_ETHERNET_MODE_END, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(channel); +#endif + + R_PMISC->PFENET = (uint8_t) mode; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ +#if BSP_MCU_VBATT_SUPPORT + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(p_cfg); +#endif + + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Protect PWPR from re-entrancy + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); +} + +/*******************************************************************************************************************//** + * Writes the set and clear values on a pin of the port when an ELC event occurs. This allows accurate timing of + * pin output level. + * + * @param[in] port Port to read event data + * @param[in] set_value Bit in the port to set high (1 = that bit will be set high) + * @param[in] reset_value Bit in the port to clear low (1 = that bit will be cleared low) + * @param[in] pin_level Event data for pin + **********************************************************************************************************************/ +static void r_ioport_hw_pin_event_output_data_write (bsp_io_port_t port, + ioport_size_t set_value, + ioport_size_t reset_value, + bsp_io_level_t pin_level) +{ + uint32_t port_value = 0; + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of PCNTR4 register */ + port_value = p_ioport_regs->PCNTR4; + + if (BSP_IO_LEVEL_HIGH == pin_level) + { + /* set value contains the bit to be set high (bit mask) */ + port_value |= (uint32_t) (set_value); + + /* reset value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR + * bit of a particular pin should not be high at the same time */ + port_value &= (((uint32_t) reset_value << 16) | IOPORT_PRV_16BIT_MASK); + } + else + { + /* reset_value contains the bit to be cleared low */ + port_value |= (uint32_t) reset_value << 16; + + /* set value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR bit of a + * particular pin should not be high at the same time */ + port_value &= (uint32_t) ((set_value | IOPORT_PRV_UPPER_16BIT_MASK)); + } + + p_ioport_regs->PCNTR4 = port_value; +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's PFS register + * + * @param[in] pin Pin to write PFS data for + * @param[in] value Value to be written to the PFS register + * + **********************************************************************************************************************/ +static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value) +{ + /* PMR bits should be cleared before specifying PSEL. Reference section "20.7 Notes on the PmnPFS Register Setting" + * in the RA6M3 manual R01UH0886EJ0100. */ + if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0) + { + /* Clear PMR */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PMR = 0; + + /* New config with PMR = 0 */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & + BSP_IO_PRV_8BIT_MASK].PmnPFS = + (value & ~((uint32_t) IOPORT_PRV_PERIPHERAL_FUNCTION)); + } + + /* Write configuration */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value; +} + +#if BSP_MCU_VBATT_SUPPORT + +/*******************************************************************************************************************//** + * @brief Initializes VBTICTLR register based on pin configuration. + * + * The VBTICTLR register may need to be modified based on the project's pin configuration. There is a set of pins that + * needs to be checked. If one of these pins is found in the pin configuration table then it will be tested to see if + * the appropriate VBTICTLR bit needs to be set or cleared. If one of the pins that is being searched for is not found + * then the accompanying VBTICTLR bit is left as-is. + **********************************************************************************************************************/ +static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg) +{ + uint32_t pin_index; + uint32_t vbatt_index; + uint8_t local_vbtictlr_set; ///< Will hold bits to set in VBTICTLR + uint8_t local_vbtictlr_clear; ///< Will hold bits to clear in VBTICTLR + + /* Make no changes unless required. */ + local_vbtictlr_set = 0U; + local_vbtictlr_clear = 0U; + + /* Must loop over all pins as pin configuration table is unordered. */ + for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++) + { + /* Loop over VBATT input pins. */ + for (vbatt_index = 0U; + vbatt_index < (sizeof(g_vbatt_pins_input) / sizeof(g_vbatt_pins_input[0])); + vbatt_index++) + { + if (p_pin_cfg->p_pin_cfg_data[pin_index].pin == g_vbatt_pins_input[vbatt_index]) + { + /* Get PSEL value for pin. */ + uint32_t pfs_psel_value = p_pin_cfg->p_pin_cfg_data[pin_index].pin_cfg & BSP_PRV_PFS_PSEL_MASK; + + /* Check if pin is being used for RTC or AGT use. */ + if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value)) + { + /* Bit should be set to 1. */ + local_vbtictlr_set |= (uint8_t) (1U << vbatt_index); + } + else + { + /* Bit should be cleared to 0. */ + local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index); + } + } + } + } + + /* Disable write protection on VBTICTLR. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Read value, set and clear bits as needed and write back. */ + uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR; + local_vbtictlr |= local_vbtictlr_set; ///< Set appropriate bits + local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits + + R_SYSTEM->VBTICTLR = local_vbtictlr; + + /* Enable write protection on VBTICTLR. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +} + +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c new file mode 100644 index 0000000000..dca675aaf3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c @@ -0,0 +1,4186 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#include + +#include "rm_ble_abs_api.h" +#include "rm_ble_abs.h" + +#include "fsp_common_api.h" + +#if ((BSP_CFG_RTOS == 2)) + #include "FreeRTOS.h" + #include "task.h" + #include "event_groups.h" + #define BLE_EVENT_PATTERN (0x0A0A) +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "BLE_ABS" in ASCII, used to determine if module is open. */ +#define BLE_ABS_OPEN (0X00424C45ULL) + +/**********************************/ +/** Define for advertising handle */ +/**********************************/ +/** Advertising Handle for Legacy Advertising. */ +#define BLE_ABS_LEGACY_HDL (0x00) + +/** Advertising Handle for Extended Advertising. */ +#define BLE_ABS_EXT_HDL (0x01) + +/** Advertising Handle for Non-Connectable Advertising. */ +#define BLE_ABS_NON_CONN_HDL (0x02) + +/** Advertising Handle for Periodic Advertising. */ +#define BLE_ABS_PERD_HDL (0x03) + +/** Advertising Handle for Legacy Advertising */ +#define BLE_ABS_COMMON_HDL (0x00) + +/**********************************/ +/** Define for advertising status */ +/**********************************/ +/** set fast advertising parameters */ +#define BLE_ABS_ADV_STATUS_PARAM_FAST (0x00000001) + +/** set slow advertising parameters */ +#define BLE_ABS_ADV_STATUS_PARAM_SLOW (0x00000002) + +/** set advertising data */ +#define BLE_ABS_ADV_STATUS_ADV_DATA (0x00000010) + +/** set scan response data */ +#define BLE_ABS_ADV_STATUS_SRES_DATA (0x00000020) + +/** set periodic advertising data */ +#define BLE_ABS_ADV_STATUS_PERD_DATA (0x00000040) + +/** start fast advertising */ +#define BLE_ABS_ADV_STATUS_ADV_FAST_START (0x00000100) + +/** start slow advertising */ +#define BLE_ABS_ADV_STATUS_ADV_SLOW_START (0x00000200) + +/** set periodic advertising parameters */ +#define BLE_ABS_ADV_STATUS_PERD_PARAM (0x00001000) + +/** start periodic advertising */ +#define BLE_ABS_ADV_STATUS_PERD_START (0x00010000) + +/** set legacy adv for legacy advertising */ +#define BLE_ABS_ADV_COMM_LEG (0x00100000) + +/** set non-connectable adv for legacy advertising */ +#define BLE_ABS_ADV_COMM_NON (0x00200000) + +/** set non-connectable adv for legacy advertising */ +#define BLE_ABS_ADV_COMM_TO (0x01000000) + +/**********************************/ +/** Define for scan status */ +/**********************************/ +/** start fast scan */ +#define BLE_ABS_SCAN_STATUS_FAST_START (0x00000001) + +/** start slow scan */ +#define BLE_ABS_SCAN_STATUS_SLOW_START (0x00000002) + +/**********************************/ +/** Define for privacy status */ +/**********************************/ +/** create irk */ +#define BLE_ABS_PV_STATUS_CREATE_IRK (0x00000001) + +/** add irk to resolving list */ +#define BLE_ABS_PV_STATUS_ADD_RSLV (0x00000002) + +/** set privacy mode */ +#define BLE_ABS_PV_STATUS_SET_MODE (0x00000004) + +/** enable resolvable private address function */ +#define BLE_ABS_PV_STATUS_EN_RPA (0x00000008) + +/**********************************/ +/** Define for create connection */ +/**********************************/ +/** scan interval for connection request with 1M & 2M PHY */ +#define BLE_ABS_CONN_SC_INTV_FAST (0x0060) + +/** scan window for connection request with 1M & 2M PHY */ +#define BLE_ABS_CONN_SC_WINDOW_FAST (0x0030) + +/** scan interval for connection request with coded PHY */ +#define BLE_ABS_CONN_SC_INTV_SLOW (0x0180) + +/** scan window for connection request with coded PHY */ +#define BLE_ABS_CONN_SC_WINDOW_SLOW (0x0090) + +/** minimum advertising data length */ +#define BLE_ABS_LEGACY_ADV_DATA_LEN (31) +#define BLE_ABS_CONN_EXT_ADV_DATA_LEN (229) + +/** add magic number value set */ +#define BLE_ABS_GAP_CONNECTION_CE_LENGTH (0xFFFF) +#define BLE_ABS_SET_PAIRING_MAXIMUM_LTK_SIZE (0x10) +#define BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF (0xFF) +#define BLE_ABS_GAP_REMOTE_IRK_AA (0xAA) +#define BLE_ABS_REMOTE_DEVICE_ADDRESS_55 (0x55) +#define BLE_ABS_GAP_EVENT_CONNECTION_TIMEOUT_1000 (1000) + +/*** r_ble_sec_data functions added start ***/ +#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) + #define BLE_SECD_UPD_BN_ADD (0x00) + #define BLE_SECD_UPD_BN_ADD_OVERWR (0x01) + #define BLE_SECD_UPD_BN_DEL (0x02) + #define BLE_SECD_UPD_BN_ALL_DEL (0x03) + #define BLE_ABS_SECURE_DATA_DELETE_LOCAL_FF (0xFF) + #define BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF (0xFF) + #define BLE_ABS_SECURE_DATA_REMOTE_BOND_NUMBER_FF (0xFF) + #define BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF (0xFF) + #define BLE_ABS_SECURE_DATA_BOND_CHECK_FF (0xFF) +#endif + +#if (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE != 0) + #define BLE_DEV_DATA_DF_ADDR _BLE_DF_ADDR(BLE_CFG_DEV_DATA_DF_BLOCK) + #define BLE_ABS_SECURE_DATA_DF_ADDR _BLE_DF_ADDR(BLE_CFG_SECD_DATA_DF_BLOCK) +#elif (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE != 0) + #define BLE_DEV_DATA_DF_ADDR _BLE_DF_ADDR(BLE_CFG_DEV_DATA_DF_BLOCK) + #define BLE_ABS_SECURE_DATA_DF_ADDR _BLE_DF_ADDR(BLE_CFG_SECD_DATA_DF_BLOCK) +#endif + +/**** RF event notify function pointer ****/ +#define BLE_EVENT_TYPE_CONN (0x0000U) +#define BLE_EVENT_TYPE_ADV (0x0001U) +#define BLE_EVENT_TYPE_SCAN (0x0002U) +#define BLE_EVENT_TYPE_INITIATOR (0x0003U) + +#define BLE_EVENT_NOTIFY_CONN_START_POS (0) +#define BLE_EVENT_NOTIFY_ADV_START_POS (1) +#define BLE_EVENT_NOTIFY_SCAN_START_POS (2) +#define BLE_EVENT_NOTIFY_INIT_START_POS (3) +#define BLE_EVENT_NOTIFY_CONN_CLOSE_POS (4) +#define BLE_EVENT_NOTIFY_ADV_CLOSE_POS (5) +#define BLE_EVENT_NOTIFY_SCAN_CLOSE_POS (6) +#define BLE_EVENT_NOTIFY_INIT_CLOSE_POS (7) +#define BLE_EVENT_NOTIFY_DS_START_POS (8) +#define BLE_EVENT_NOTIFY_DS_CLOSE_POS (9) + +#define BLE_EVENT_TYPE_RF_DS_START (0x0U) +#define BLE_EVENT_TYPE_RF_DS_CLOSE (0x1U) + +#define BLE_EVENT_NOTIFY_CONN_START_BIT (0x1U << BLE_EVENT_NOTIFY_CONN_START_POS) +#define BLE_EVENT_NOTIFY_ADV_START_BIT (0x1U << BLE_EVENT_NOTIFY_ADV_START_POS) +#define BLE_EVENT_NOTIFY_SCAN_START_BIT (0x1U << BLE_EVENT_NOTIFY_SCAN_START_POS) +#define BLE_EVENT_NOTIFY_INIT_START_BIT (0x1U << BLE_EVENT_NOTIFY_INIT_START_POS) + +#define BLE_EVENT_NOTIFY_CONN_CLOSE_BIT (0x1U << BLE_EVENT_NOTIFY_CONN_CLOSE_POS) +#define BLE_EVENT_NOTIFY_ADV_CLOSE_BIT (0x1U << BLE_EVENT_NOTIFY_ADV_CLOSE_POS) +#define BLE_EVENT_NOTIFY_SCAN_CLOSE_BIT (0x1U << BLE_EVENT_NOTIFY_SCAN_CLOSE_POS) +#define BLE_EVENT_NOTIFY_INIT_CLOSE_BIT (0x1U << BLE_EVENT_NOTIFY_INIT_CLOSE_POS) + +#define BLE_EVENT_NOTIFY_DS_START_BIT (0x1U << BLE_EVENT_NOTIFY_DS_START_POS) +#define BLE_EVENT_NOTIFY_DS_CLOSE_BIT (0x1U << BLE_EVENT_NOTIFY_DS_CLOSE_POS) + +#define BLE_EVENT_NOTIFY_START_MASK ( \ + (BLE_EVENT_NOTIFY_CONN_START_BIT) | \ + (BLE_EVENT_NOTIFY_ADV_START_BIT) | \ + (BLE_EVENT_NOTIFY_SCAN_START_BIT) | \ + (BLE_EVENT_NOTIFY_INIT_START_BIT) | \ + (0x0U)) + +#define BLE_EVENT_NOTIFY_CLOSE_MASK ( \ + (BLE_EVENT_NOTIFY_CONN_CLOSE_BIT) | \ + (BLE_EVENT_NOTIFY_ADV_CLOSE_BIT) | \ + (BLE_EVENT_NOTIFY_SCAN_CLOSE_BIT) | \ + (BLE_EVENT_NOTIFY_INIT_CLOSE_BIT) | \ + (0x0U)) + +#define BLE_EVENT_NOTIFY_DS_MASK ( \ + (BLE_EVENT_NOTIFY_DS_START_BIT) | \ + (BLE_EVENT_NOTIFY_DS_CLOSE_BIT) | \ + (0x0U)) + +#define BLE_HOST_TBL_NUM 8 + +#define BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE (4) +#define BLE_ABS_SECURE_DATA_MAGIC_NUMBER (0x12345678) + +/** Internal data flash base address. */ +#define BLE_ABS_SECURE_DATA_BLOCK_BASE (0x40100000) + +#if (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE != 0) + #define BLE_ABS_SECURE_DATA_BLOCK_SIZE (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE) +#elif (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE != 0) + #define BLE_ABS_SECURE_DATA_BLOCK_SIZE (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE) +#endif + +#define BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE +#define BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET (5) +#define BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET (8) +#define BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET (12) +#define BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET (20) +#define BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET (48) + +#define BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE (88) +#define BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE (40) +#define BLE_ABS_SECURE_DATA_LOCAL_INFOMATION_SIZE (1) +#define BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE (7) +#define BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE (8) +#define BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE (6) +#define BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE (65) +#define BLE_ABS_SECURE_DATA_REMOTE_KEYS_INFOMATION_SIZE (4) + +#define BLE_ABS_SECURE_DATA_BASE_ADDR (BLE_ABS_SECURE_DATA_BLOCK_BASE + \ + (BLE_ABS_CFG_SECURE_DATA_DATAFLASH_BLOCK * \ + BLE_ABS_SECURE_DATA_BLOCK_SIZE)) +#define BLE_ABS_SECURE_DATA_ADDR_MGN_DATA (BLE_ABS_SECURE_DATA_BASE_ADDR) +#define BLE_ABS_SECURE_DATA_SEC_BOND_NUM (BLE_ABS_SECURE_DATA_ADDR_MGN_DATA + \ + BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE) +#define BLE_ABS_SECURE_DATA_ADDR_LOC_AREA (BLE_ABS_SECURE_DATA_BASE_ADDR + \ + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE) +#define BLE_ABS_SECURE_DATA_ADDR_LOC_IRK (BLE_ABS_SECURE_DATA_ADDR_LOC_AREA) +#define BLE_ABS_SECURE_DATA_ADDR_LOC_CSRK (BLE_ABS_SECURE_DATA_ADDR_LOC_IRK + BLE_GAP_IRK_SIZE) +#define BLE_ABS_SECURE_DATA_ADDR_LOC_IDADDR (BLE_ABS_SECURE_DATA_ADDR_LOC_CSRK + BLE_GAP_CSRK_SIZE) +#define BLE_ABS_SECURE_DATA_ADDR_LOC_INFO (BLE_ABS_SECURE_DATA_ADDR_LOC_IDADDR + \ + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE) +#define BLE_ABS_SECURE_DATA_ADDR_REM_START (BLE_ABS_SECURE_DATA_ADDR_LOC_INFO + \ + BLE_ABS_SECURE_DATA_LOCAL_INFOMATION_SIZE) +#define BLE_ABS_SECURE_DATA_MAX_SIZE (BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + \ + BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE * \ + BLE_ABS_CFG_NUMBER_BONDING) +#define BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK (BLE_ABS_SECURE_DATA_BLOCK_SIZE - 1UL) + +/** The invalid timer handle. */ +#define BLE_TIMER_INVALID_HDL (0xFF) + +/** add magic number value set */ +#define BLE_ABS_TIMER_REMAIN_TIMESHORTEST (0xFFFFFFFF) +#define BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS (1000) +#define BLE_ABS_TIMER_METRIC_PREFIX (1000) + +/*********************************************************************************************************************** + * Local Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static fsp_err_t ble_abs_set_pairing_parameter(ble_abs_pairing_parameter_t * p_pairing_parameter); +static fsp_err_t ble_abs_convert_legacy_advertising_parameter( + ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter); + +#if (BLE_CFG_LIBRARY_TYPE == 0) +static fsp_err_t ble_abs_convert_extend_advertising_parameter( + ble_abs_extend_advertising_parameter_t * advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter); + +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +static fsp_err_t ble_abs_convert_non_connectable_advertising_parameter( + ble_abs_non_connectable_advertising_parameter_t * p_non_connectable_advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter, + uint8_t advertising_handle); +static fsp_err_t ble_abs_advertising_report_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data); +static fsp_err_t ble_abs_check_scan_phy_parameter(ble_abs_scan_phy_parameter_t * p_scan_phy); +static fsp_err_t ble_abs_set_scan_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_abs_scan_parameter_t * p_scan_parameter); + +static void ble_abs_gap_callback(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data); +static void ble_abs_vendor_specific_callback(uint16_t event_type, + ble_status_t event_result, + st_ble_vs_evt_data_t * p_event_data); +static void ble_abs_set_abs_callback(ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_gap_application_callback_t gap_callback, + ble_vendor_specific_application_callback_t vendor_specific_callback); +static void ble_abs_set_advertising_status(ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint8_t advertising_handle, + uint32_t set, + uint32_t clear); +static void ble_abs_set_advertising_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl, + void * p_advertising_parameter, + uint8_t advertising_handle); +static void ble_abs_cancel_connection_function(void); + +#if (BLE_CFG_LIBRARY_TYPE != 0) +static void ble_abs_advertising_to_function(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_handle); + +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ +static void ble_abs_set_scan_status(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t set, uint32_t clear); +static void ble_abs_update_data_status(ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint32_t advertising_status, + uint8_t * p_advertising_data, + uint16_t advertising_data_len, + uint8_t advertising_handle); +static void ble_abs_connection_indication_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_scan_to_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_loc_ver_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, st_ble_evt_data_t * p_event_data); +static void ble_abs_advertising_parameter_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data); +static void ble_abs_advertising_data_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data); +static void ble_abs_periodic_parameter_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_advertising_off_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data); +static void ble_abs_conflict_resolving_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data); +static void ble_abs_random_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_vs_evt_data_t * p_event_data); +static void ble_abs_set_irk_to_resolving_list(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t * p_lc_irk); +static void ble_abs_advertising_start(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle); +static void ble_abs_advertising_set_data(ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint8_t advertising_handle, + uint8_t data_type); +static void ble_abs_set_legacy_scan_response_data(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_convert_scan_phy_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_abs_scan_phy_parameter_t * p_abs_phy, + ble_gap_scan_phy_parameter_t * p_gap_phy, + ble_gap_scan_on_t * p_scan_enable); +static void ble_abs_set_connection_parameter(ble_abs_connection_phy_parameter_t * p_abs_connection_parameter, + ble_gap_connection_phy_parameter_t * p_connection_phy_parameter, + ble_gap_connection_parameter_t * p_connection_parameter); +static void ble_abs_convert_scan_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_gap_scan_param_t * p_scan_parameter, + ble_gap_scan_on_t * p_scan_enable, + uint32_t status); +static void ble_abs_set_connection_advertising_interval(st_ble_gap_adv_param_t * p_advertising_parameter, + uint32_t fast_advertising_interval, + uint32_t slow_advertising_interval, + uint16_t fast_period); + +/*** ble secure data functions start ***/ + +static fsp_err_t ble_abs_secure_data_writelocinfo(flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk); +static fsp_err_t ble_abs_secure_data_readlocinfo(flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk); +static void ble_abs_secure_data_recvremkeys(ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys); +static fsp_err_t ble_abs_secure_data_writeremkeys(flash_instance_t const * p_instance, + ble_device_address_t * p_addr, + st_ble_gap_auth_info_t * p_keyinfo); +static fsp_err_t ble_abs_secure_data_init(flash_instance_t const * p_instance); + +#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) + +static st_ble_gap_key_ex_param_t gs_key_ex_param; +static st_ble_gap_key_dist_t gs_key_dist; + +static const ble_device_address_t invalid_rem_addr = +{ + .addr = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, + .type = 0xFF +}; + +static fsp_err_t ble_abs_secure_data_find_entry(ble_device_address_t * p_dev_addr, + int32_t * p_entry, + uint8_t * p_sec_data); +static void ble_abs_secure_data_find_oldest_entry(flash_instance_t const * p_instance, int32_t * p_entry); +static fsp_err_t ble_abs_secure_data_update_bond_num(flash_instance_t const * p_instance, + int32_t entry, + int32_t op_code, + uint8_t * p_alloc_bond_num, + uint8_t * p_sec_data); +static void ble_abs_secure_data_update_bond_order(flash_instance_t const * p_instance, + int32_t entry, + uint8_t * p_sec_data, + uint8_t bond_order); +static fsp_err_t ble_abs_secure_data_is_valid_entry(flash_instance_t const * p_instance, int32_t entry); +static fsp_err_t ble_abs_secure_data_read_bond_info(flash_instance_t const * p_instance, + uint8_t * p_out_bond_num, + uint8_t ** pp_sec_data, + st_ble_gap_bond_info_t * p_bond_info); +static void ble_abs_secure_data_release_bond_info_buf(uint8_t * p_sec_data); + +#endif +static fsp_err_t ble_abs_secure_data_flash_read(flash_instance_t const * p_instance, + uint32_t addr, + uint8_t * buff, + uint16_t len); +static fsp_err_t ble_abs_secure_data_flash_write(flash_instance_t const * p_instance, + uint32_t addr, + uint8_t * buff, + uint16_t len); + +uint8_t r_dflash_read(uint32_t addr, uint8_t * buff, uint16_t len); +uint8_t r_dflash_write(uint32_t addr, uint8_t * buff, uint16_t len); + +/*** ble secure data functions end ***/ + +/*** platform control functions added start ***/ + +void r_ble_rf_control_error(uint32_t err_no); +uint8_t r_ble_rf_power_save_mode(void); + +#if (BSP_CFG_RTOS == 2) +void r_ble_wake_up_task(void * EventGroupHandle); +void r_ble_wake_up_task_from_isr(void * EventGroupHandle); + +#endif + +/*** platform control functions end ***/ + +/*** ble timer functions start ***/ +static void ble_abs_timer_update_remaining_time_ms(ble_abs_instance_ctrl_t * const p_instance_ctrl, bool expired); +static uint32_t ble_abs_timer_alloc_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_timer_free_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl); +static void ble_abs_timer_start_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_timer_stop_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_timer_add_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl); +static void ble_abs_timer_remove_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl); +static void ble_abs_timer_event_cb(ble_abs_instance_ctrl_t * const p_instance_ctrl); +void ble_abs_timer_process_timer_expire(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_timer_init(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static void ble_abs_timer_terminate(ble_abs_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ble_abs_timer_create(ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint32_t * p_timer_hdl, + uint32_t timeout_ms, + uint8_t type, + ble_abs_timer_cb_t cb); +static fsp_err_t ble_abs_timer_delete(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t * p_timer_hdl); +static fsp_err_t ble_abs_timer_start(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl); +static fsp_err_t ble_abs_timer_stop(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl); +static void ble_abs_init_hw_timer(timer_instance_t const * p_instance); +static void ble_abs_terminate_hw_timer(timer_instance_t const * p_instance); +static void ble_abs_start_hw_timer(timer_instance_t const * p_instance, + uint32_t * current_timeout_ms, + uint32_t * elapsed_timeout_ms, + uint32_t timeout_ms); +static void ble_abs_stop_hw_timer(timer_instance_t const * p_instance, + uint32_t * current_timeout_ms, + uint32_t * elapsed_timeout_ms); +static uint32_t ble_abs_get_elapsed_time_ms(timer_instance_t const * p_instance, + bool expired, + const uint32_t current_timeout_ms, + uint32_t * elapsed_timeout_ms); +void ble_abs_hw_timer_callback(timer_callback_args_t * callback_args); + +/*** ble timer functions end ***/ + +/* Version data structure. */ +static const fsp_version_t g_ble_abs_version = +{ + .api_version_minor = BLE_ABS_API_VERSION_MINOR, + .api_version_major = BLE_ABS_API_VERSION_MAJOR, + .code_version_minor = BLE_ABS_CODE_VERSION_MINOR, + .code_version_major = BLE_ABS_CODE_VERSION_MAJOR +}; + +/** BLE ABS on BLE HAL API mapping for BLE ABS interface */ +const ble_abs_api_t g_ble_abs_on_ble = +{ + .open = RM_BLE_ABS_Open, + .close = RM_BLE_ABS_Close, + .reset = RM_BLE_ABS_Reset, + .versionGet = RM_BLE_ABS_VersionGet, + .startLegacyAdvertising = RM_BLE_ABS_StartLegacyAdvertising, + .startExtendedAdvertising = RM_BLE_ABS_StartExtendedAdvertising, + .startNonConnectableAdvertising = RM_BLE_ABS_StartNonConnectableAdvertising, + .startPeriodicAdvertising = RM_BLE_ABS_StartPeriodicAdvertising, + .startScanning = RM_BLE_ABS_StartScanning, + .createConnection = RM_BLE_ABS_CreateConnection, + .setLocalPrivacy = RM_BLE_ABS_SetLocalPrivacy, + .startAuthentication = RM_BLE_ABS_StartAuthentication, +}; + +static ble_abs_instance_ctrl_t * gp_instance_ctrl; + +/*********************************************************************************************************************** + * Exported global functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Host stack is initialized with this function. Before using All the R_BLE APIs, + * it's necessary to call this function. A callback functions are registered with this function. + * In order to receive the GAP, GATT, Vendor specific event, + * it's necessary to register a callback function. + * The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event. + * Implements @ref ble_abs_api_t::open. + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_Open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Null pointer presented. + * @retval FSP_ERR_INVALID_CHANNEL The channel number is invalid. + * @retval FSP_ERR_ALREADY_OPEN Requested channel is already open in a different configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_Open (ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg) +{ + int32_t i; + fsp_err_t err = FSP_SUCCESS; + ble_status_t ble_status = BLE_SUCCESS; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ASSERT(p_cfg->gap_callback); + FSP_ERROR_RETURN(0 == p_cfg->channel, FSP_ERR_INVALID_CHANNEL); +#endif + FSP_ERROR_RETURN(BLE_ABS_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + gp_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + (*p_instance_ctrl).abs_gap_callback = NULL; + (*p_instance_ctrl).abs_vendor_specific_callback = NULL; + (*p_instance_ctrl).privacy_mode = BLE_GAP_NET_PRIV_MODE; + (*p_instance_ctrl).set_privacy_status = 0; + (*p_instance_ctrl).p_cfg = p_cfg; + + R_BLE_Open(); + + /* check pairing parameter */ + err = ble_abs_set_pairing_parameter(p_cfg->p_pairing_parameter); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_INVALID_ARGUMENT); + + /* initialize GAP layer */ + ble_status = R_BLE_GAP_Init(ble_abs_gap_callback); + FSP_ERROR_RETURN(BLE_SUCCESS == ble_status, FSP_ERR_INVALID_ARGUMENT); + + for (i = 0; i < BLE_MAX_NO_OF_ADV_SETS_SUPPORTED; i++) + { + p_instance_ctrl->advertising_sets[i].advertising_status = 0; + } + + p_instance_ctrl->abs_scan.scan_status = 0; + (*p_instance_ctrl).connection_timer_handle = BLE_TIMER_INVALID_HDL; +#if (BLE_CFG_LIBRARY_TYPE != 0) + (*p_instance_ctrl).advertising_timer_handle = BLE_TIMER_INVALID_HDL; +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + (*p_instance_ctrl).set_privacy_status = 0; + + /* set pairing parameter */ + ble_abs_set_pairing_parameter(p_cfg->p_pairing_parameter); + ble_abs_set_abs_callback(p_instance_ctrl, p_cfg->gap_callback, p_cfg->vendor_specific_callback); + + if ((0 < p_cfg->gatt_server_callback_list_number) && (NULL != p_cfg->p_gatt_server_callback_list)) + { + FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTS_Init(p_cfg->gatt_server_callback_list_number), + FSP_ERR_INVALID_ARGUMENT); + + for (i = 0; i < p_cfg->gatt_server_callback_list_number; i++) + { + if (NULL != p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_function) + { + FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTS_RegisterCb( + p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_function, + p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_priority + ), + FSP_ERR_INVALID_ARGUMENT); + } + else + { + break; + } + } + } + +#if (BLE_CFG_LIBRARY_TYPE != 2) + if ((0 < p_cfg->gatt_client_callback_list_number) && (NULL != p_cfg->p_gatt_client_callback_list)) + { + FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTC_Init(p_cfg->gatt_client_callback_list_number), + FSP_ERR_INVALID_ARGUMENT); + + for (i = 0; i < p_cfg->gatt_client_callback_list_number; i++) + { + if (NULL != p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_function) + { + FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTC_RegisterCb( + p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_function, + p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_priority), + FSP_ERR_INVALID_ARGUMENT); + } + else + { + break; + } + } + } +#endif /* (BLE_CFG_LIBRARY_TYPE != 2) */ + + FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_VS_Init(ble_abs_vendor_specific_callback), FSP_ERR_INVALID_ARGUMENT); + + ble_abs_timer_init(p_instance_ctrl); + + p_instance_ctrl->open = BLE_ABS_OPEN; + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_Open() */ + +/*******************************************************************************************************************//** + * @brief Close the BLE channel. + * Implements @ref ble_abs_api_t::close. + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_Close + * + * @retval FSP_SUCCESS Channel closed successfully. + * @retval FSP_ERR_ASSERTION Null pointer presented. + * @retval FSP_ERR_NOT_OPEN Control block not open. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_Close (ble_abs_ctrl_t * const p_ctrl) +{ + ble_abs_instance_ctrl_t * p_ble_abs_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ble_abs_ctrl); +#endif + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_ble_abs_ctrl->open, FSP_ERR_NOT_OPEN); + + R_BLE_Close(); + + R_BLE_GAP_Terminate(); + + ble_abs_timer_terminate(p_ble_abs_ctrl); + + p_ble_abs_ctrl->open = 0; + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_Close() */ + +/*******************************************************************************************************************//** + * BLE is reset with this function. The process is carried out in the following order. + * R_BLE_Close() -> R_BLE_GAP_Terminate() -> R_BLE_Open() -> R_BLE_SetEvent(). + * The init_cb callback initializes the others (Host Stack, timer, etc...). + * Implements @ref ble_abs_api_t::reset. + * + * @retval FSP_SUCCESS Channel closed successfully. + * @retval FSP_ERR_ASSERTION Null pointer presented. + * @retval FSP_ERR_NOT_OPEN Control block not open. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_Reset (ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback) +{ + ble_abs_instance_ctrl_t * p_ble_abs_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ble_abs_ctrl); +#endif + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_ble_abs_ctrl->open, FSP_ERR_NOT_OPEN); + + R_BLE_Close(); + + R_BLE_GAP_Terminate(); + + R_BLE_Open(); + + if (NULL != init_callback) + { + R_BLE_SetEvent(init_callback); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get BLE module code and API versions. + * Implements @ref ble_abs_api_t::versionGet. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_VersionGet (fsp_version_t * const p_version) +{ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_version); +#endif + + p_version->version_id = g_ble_abs_version.version_id; + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_VersionGet() */ + +/*******************************************************************************************************************//** + * Start Legacy Advertising after setting advertising parameters, advertising data and scan response data. + * The legacy advertising uses the advertising set whose advertising handle is 0. + * The advertising type is connectable and scannable(ADV_IND). + * The address type of local device is Public Identity Address or + * RPA(If the resolving list contains no matching entry, use the public address.). + * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified. + * Implements @ref ble_abs_api_t::startLegacyAdvertising + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartLegacyAdvertising + * + * @retval FSP_SUCCESS Operation succeeded + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_STATE Host stack hasn't been initialized. + * @retval FSP_ERR_INVALID_POINTER p_advertising_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartLegacyAdvertising (ble_abs_ctrl_t * const p_ctrl, + ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter) +{ + st_ble_gap_adv_param_t advertising_parameter; + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + +#if (BLE_CFG_LIBRARY_TYPE == 0) + uint8_t advertising_handle = BLE_ABS_LEGACY_HDL; +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + uint8_t advertising_handle = BLE_ABS_COMMON_HDL; +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER); +#endif + + /** status check */ + FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & + (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)), + FSP_ERR_INVALID_STATE); + +#if (BLE_CFG_LIBRARY_TYPE == 0) + ble_abs_set_advertising_status(p_instance_ctrl, + advertising_handle, + 0, + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)); +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + ble_abs_set_advertising_status(p_instance_ctrl, + advertising_handle, + 0, + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW | + BLE_ABS_ADV_COMM_LEG | BLE_ABS_ADV_COMM_NON)); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_convert_legacy_advertising_parameter((ble_abs_legacy_advertising_parameter_t *) + p_advertising_parameter, + &advertising_parameter), + FSP_ERR_INVALID_ARGUMENT); + + /** check data length */ + FSP_ERROR_RETURN((BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->advertising_data_length) && + (BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->scan_response_data_length), + FSP_ERR_INVALID_ARGUMENT); + + ble_abs_set_connection_advertising_interval(&advertising_parameter, + p_advertising_parameter->fast_advertising_interval, + p_advertising_parameter->slow_advertising_interval, + p_advertising_parameter->fast_advertising_period); ///< check advertising interval + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_ADV_DATA, + p_advertising_parameter->p_advertising_data, + p_advertising_parameter->advertising_data_length, + advertising_handle); ///< advertising data update check + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_SRES_DATA, + p_advertising_parameter->p_scan_response_data, + p_advertising_parameter->scan_response_data_length, + advertising_handle); ///< scan response data update check + + ble_abs_set_advertising_parameter(p_instance_ctrl, + (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter, + BLE_ABS_LEGACY_HDL); + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT); + +#if (BLE_CFG_LIBRARY_TYPE == 0) + uint32_t status = + p_advertising_parameter->fast_advertising_period ? BLE_ABS_ADV_STATUS_PARAM_FAST : BLE_ABS_ADV_STATUS_PARAM_SLOW; +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + uint32_t status = + p_advertising_parameter->fast_advertising_period ? (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_COMM_LEG) : + (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_COMM_LEG); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0); + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_StartLegacyAdvertising() */ + +/*******************************************************************************************************************//** + * Start Extended Advertising after setting advertising parameters, advertising data. + * The extended advertising uses the advertising set whose advertising handle is 1. + * The advertising type is connectable and non-scannable. + * The address type of local device is Public Identity Address or + * RPA(If the resolving list contains no matching entry, use the public address.). + * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified. + * Implements @ref ble_abs_api_t::startExtendedAdvertising + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_POINTER p_advertising_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_STATE Host stack hasn't been initialized. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + * @retval FSP_ERR_UNSUPPORTED Subordinate modules do not support this feature. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartExtendedAdvertising (ble_abs_ctrl_t * const p_ctrl, + ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter) +{ +#if (BLE_CFG_LIBRARY_TYPE == 0) + st_ble_gap_adv_param_t advertising_parameter; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ + #if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + /** status check */ + FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)), + FSP_ERR_INVALID_STATE); + + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_EXT_HDL, + 0, + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)); + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_convert_extend_advertising_parameter((ble_abs_extend_advertising_parameter_t *) + p_advertising_parameter, + &advertising_parameter), + FSP_ERR_INVALID_ARGUMENT); + + FSP_ERROR_RETURN(BLE_ABS_CONN_EXT_ADV_DATA_LEN >= p_advertising_parameter->advertising_data_length, + FSP_ERR_INVALID_ARGUMENT); ///< check data length + + ble_abs_set_connection_advertising_interval(&advertising_parameter, + p_advertising_parameter->fast_advertising_interval, + p_advertising_parameter->slow_advertising_interval, + p_advertising_parameter->fast_advertising_period); ///< check advertising interval + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_ADV_DATA, + p_advertising_parameter->p_advertising_data, + p_advertising_parameter->advertising_data_length, + BLE_ABS_EXT_HDL); ///< data update check + + ble_abs_set_advertising_parameter(p_instance_ctrl, + (ble_abs_extend_advertising_parameter_t *) p_advertising_parameter, + BLE_ABS_EXT_HDL); + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT); + + uint32_t status = + p_advertising_parameter->fast_advertising_period ? BLE_ABS_ADV_STATUS_PARAM_FAST : BLE_ABS_ADV_STATUS_PARAM_SLOW; + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_EXT_HDL, status, 0); + + return FSP_SUCCESS; +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + return FSP_ERR_UNSUPPORTED; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function RM_BLE_ABS_StartExtendedAdvertising() */ + +/*******************************************************************************************************************//** + * Start Non-Connectable Advertising after setting advertising parameters, advertising data. + * The non-connectable advertising uses the advertising set whose advertising handle is 2. + * The advertising type is non-connectable and non-scannable. + * The address type of local device is Public Identity Address or + * RPA(If the resolving list contains no matching entry, use the public address.). + * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified. + * Secondary Advertising Max Skip is 0. + * Implements @ref ble_abs_api_t::startNonConnectableAdvertising. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_POINTER p_advertising_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_STATE Host stack hasn't been initialized. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartNonConnectableAdvertising ( + ble_abs_ctrl_t * const p_ctrl, + ble_abs_non_connectable_advertising_parameter_t const * const p_advertising_parameter) +{ + st_ble_gap_adv_param_t advertising_parameter; + +#if (BLE_CFG_LIBRARY_TYPE == 0) + uint8_t advertising_handle = BLE_ABS_NON_CONN_HDL; +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + uint8_t advertising_handle = BLE_ABS_COMMON_HDL; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /** status check */ + FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)), + FSP_ERR_INVALID_STATE); + +#if (BLE_CFG_LIBRARY_TYPE == 0) + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0, BLE_ABS_ADV_STATUS_PARAM_SLOW); +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + ble_abs_set_advertising_status(p_instance_ctrl, + advertising_handle, + 0, + (BLE_ABS_ADV_STATUS_PARAM_SLOW | + BLE_ABS_ADV_COMM_LEG | BLE_ABS_ADV_COMM_NON)); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_convert_non_connectable_advertising_parameter(( + ble_abs_non_connectable_advertising_parameter_t + *) + p_advertising_parameter, + &advertising_parameter, + advertising_handle), + FSP_ERR_INVALID_ARGUMENT); + + advertising_parameter.adv_intv_min = p_advertising_parameter->advertising_interval; + advertising_parameter.adv_intv_max = p_advertising_parameter->advertising_interval; + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_ADV_DATA, + p_advertising_parameter->p_advertising_data, + p_advertising_parameter->advertising_data_length, + advertising_handle); ///< data update check + + ble_abs_set_advertising_parameter(p_instance_ctrl, + (ble_abs_non_connectable_advertising_parameter_t *) p_advertising_parameter, + BLE_ABS_NON_CONN_HDL); + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT); + +#if (BLE_CFG_LIBRARY_TYPE == 0) + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0); +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + ble_abs_set_advertising_status(p_instance_ctrl, + advertising_handle, + (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_COMM_NON), + 0); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_StartNonConnectableAdvertising() */ + +/*******************************************************************************************************************//** + * Start Periodic Advertising after setting advertising parameters, periodic advertising parameters, + * advertising data and periodic advertising data. + * The periodic advertising uses the advertising set whose advertising handle is 3. + * The advertising type is non-connectable and non-scannable. + * The address type of local device is Public Identity Address or + * RPA(If the resolving list contains no matching entry, use the public address.). + * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified. + * Secondary Advertising Max Skip is 0. + * Implements @ref ble_abs_api_t::startPeriodicAdvertising + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_POINTER p_advertising_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + * @retval FSP_ERR_UNSUPPORTED Subordinate modules do not support this feature. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartPeriodicAdvertising (ble_abs_ctrl_t * const p_ctrl, + ble_abs_periodic_advertising_parameter_t const * const p_advertising_parameter) +{ +#if (BLE_CFG_LIBRARY_TYPE == 0) + st_ble_gap_adv_param_t advertising_parameter; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ + #if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + /** status check */ + FSP_ASSERT(!(p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_PERD_START))); + + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_PERD_HDL, + 0, + (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_STATUS_PERD_PARAM)); + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_convert_non_connectable_advertising_parameter(( + ble_abs_non_connectable_advertising_parameter_t + *) (& + p_advertising_parameter + -> + advertising_parameter), + &advertising_parameter, + BLE_ABS_PERD_HDL), + FSP_ERR_INVALID_ARGUMENT); + + advertising_parameter.adv_intv_min = p_advertising_parameter->advertising_parameter.advertising_interval; + advertising_parameter.adv_intv_max = p_advertising_parameter->advertising_parameter.advertising_interval; + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_ADV_DATA, + p_advertising_parameter->advertising_parameter.p_advertising_data, + p_advertising_parameter->advertising_parameter.advertising_data_length, + BLE_ABS_PERD_HDL); ///< advertising data update check + + ble_abs_update_data_status(p_instance_ctrl, + BLE_ABS_ADV_STATUS_PERD_DATA, + p_advertising_parameter->p_periodic_advertising_data, + p_advertising_parameter->periodic_advertising_data_length, + BLE_ABS_PERD_HDL); ///< periodic advertising data update check + + ble_abs_set_advertising_parameter(p_instance_ctrl, + (ble_abs_periodic_advertising_parameter_t *) p_advertising_parameter, + BLE_ABS_PERD_HDL); + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT); + + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0); + + return FSP_SUCCESS; +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + return FSP_ERR_UNSUPPORTED; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function RM_BLE_ABS_StartPeriodicAdvertising() */ + +/*******************************************************************************************************************//** + * Start scanning after setting scan parameters. + * The scanner address type is Public Identity Address. + * Fast scan is followed by slow scan. + * The end of fast scan or slow scan is notified with BLE_GAP_EVENT_SCAN_TO event. + * If fast_period is 0, only slow scan is carried out. + * If scan_period is 0, slow scan continues. + * Implements @ref ble_abs_api_t::startScanning. + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartScanning + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_POINTER p_scan_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_ARGUMENT The scan parameter is out of range. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartScanning (ble_abs_ctrl_t * const p_ctrl, + ble_abs_scan_parameter_t const * const p_scan_parameter) +{ + st_ble_gap_scan_param_t gap_scan_parameter; + st_ble_gap_scan_phy_param_t phy_parameter_1M; + st_ble_gap_scan_phy_param_t phy_parameter_coded; + ble_gap_scan_on_t gap_scan_enable; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_scan_parameter, FSP_ERR_INVALID_POINTER); +#endif + + gap_scan_parameter.p_phy_param_1M = p_scan_parameter->p_phy_parameter_1M ? &phy_parameter_1M : NULL; ///< set scan phy parameter for 1M + gap_scan_parameter.p_phy_param_coded = p_scan_parameter->p_phy_parameter_coded ? &phy_parameter_coded : NULL; ///< set scan phy parameter for coded + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_set_scan_parameter(p_instance_ctrl, (ble_abs_scan_parameter_t *) p_scan_parameter), + FSP_ERR_INVALID_ARGUMENT); ///< scan parameter check + + ble_abs_convert_scan_parameter(p_instance_ctrl, + &gap_scan_parameter, + &gap_scan_enable, + BLE_ABS_SCAN_STATUS_FAST_START); + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_StartScan(&gap_scan_parameter, + (st_ble_gap_scan_on_t *) (&gap_scan_enable)), + FSP_ERR_INVALID_ARGUMENT); + if (0 == p_scan_parameter->fast_scan_period) + { + ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_SLOW_START, 0); + } + else + { + ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_FAST_START, 0); + } + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_StartScanning() */ + +/*******************************************************************************************************************//** + * Generate a IRK, add it to the resolving list, set privacy mode and enable RPA function. + * Register vendor specific callback function, if IRK is generated by this function. + * After configuring local device privacy, + * BLE_GAP_ADDR_RPA_ID_PUBLIC is specified as own device address + * in theadvertising/scan/create connection API. + * Implements @ref ble_abs_api_t::setLocalPrivacy + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_SetLocalPrivacy + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_ARGUMENT The privacy_mode parameter is out of range. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Host stack hasn't been initialized. + * configuring the resolving list or privacy mode. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_SetLocalPrivacy (ble_abs_ctrl_t * const p_ctrl, + uint8_t const * const p_lc_irk, + uint8_t privacy_mode) +{ + ble_status_t ble_status = BLE_SUCCESS; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BLE_GAP_DEV_PRIV_MODE >= privacy_mode, FSP_ERR_INVALID_ARGUMENT); +#endif + + if (NULL == p_lc_irk) + { + ble_status = R_BLE_VS_GetRand(BLE_GAP_IRK_SIZE); + p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == ble_status) ? BLE_ABS_PV_STATUS_CREATE_IRK : 0; + } + else + { + ble_abs_set_irk_to_resolving_list(p_instance_ctrl, (uint8_t *) p_lc_irk); + FSP_ERROR_RETURN(0 != p_instance_ctrl->set_privacy_status, FSP_ERR_BLE_ABS_INVALID_OPERATION); + } + + p_instance_ctrl->privacy_mode = privacy_mode; + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_SetLocalPrivacy() */ + +/*******************************************************************************************************************//** + * Request create connection. + * The initiator address type is Public Identity Address. + * The scan interval is 60ms and the scan window is 30ms in case of 1M PHY or 2M PHY. + * The scan interval is 180ms and the scan window is 90ms in case of coded PHY. + * The Minimum CE Length and the Maximum CE Length are 0xFFFF. + * When the request for a connection has been received by the Controller, + * BLE_GAP_EVENT_CREATE_CONN_COMP event is notified. + * When a link has beens established, BLE_GAP_EVENT_CONN_IND event is notified. + * Implements @ref ble_abs_api_t::createConnection. + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_CreateConnection + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_POINTER p_connection_parameter is specified as NULL. + * @retval FSP_ERR_INVALID_ARGUMENT The create connection parameter is out of range. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Couldn't find a valid timer. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Invalid operation for the selected timer. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_CreateConnection (ble_abs_ctrl_t * const p_ctrl, + ble_abs_connection_parameter_t const * const p_connection_parameter) +{ + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_connection_parameter, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(10 >= p_connection_parameter->connection_timeout, FSP_ERR_INVALID_ARGUMENT); +#endif + + st_ble_gap_create_conn_param_t connection_parameter; + fsp_err_t ret = FSP_SUCCESS; + connection_parameter.init_filter_policy = p_connection_parameter->filter_parameter; + connection_parameter.own_addr_type = BLE_GAP_ADDR_PUBLIC; + + if (BLE_GAP_INIT_FILT_USE_ADDR == p_connection_parameter->filter_parameter) + { + memcpy(connection_parameter.remote_bd_addr, p_connection_parameter->p_device_address->addr, BLE_BD_ADDR_LEN); + connection_parameter.remote_bd_addr_type = p_connection_parameter->p_device_address->type; + } + else + { + connection_parameter.remote_bd_addr_type = BLE_GAP_ADDR_PUBLIC; + } + + /** set connection parameters for 1M */ + ble_gap_connection_parameter_t connection_parameter_1M; ///< connection parameter for 1M + ble_gap_connection_phy_parameter_t connection_phy_1M; ///< connection phy for 1M + ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_1M, + &connection_phy_1M, + &connection_parameter_1M); ///< select connection parameters for 1M + connection_parameter.p_conn_param_1M = + p_connection_parameter->p_connection_phy_parameter_1M ? (st_ble_gap_conn_phy_param_t *) (&connection_phy_1M) : + NULL; ///< set connection parameters for 1M + + /** set connection parameters for 2M */ + ble_gap_connection_parameter_t connection_parameter_2M; ///< connection parameter for 2M + ble_gap_connection_phy_parameter_t connection_phy_2M; ///< connection phy for 2M + ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_2M, + &connection_phy_2M, + &connection_parameter_2M); ///< select connection parameters for 2M + connection_parameter.p_conn_param_2M = + p_connection_parameter->p_connection_phy_parameter_2M ? (st_ble_gap_conn_phy_param_t *) (&connection_phy_2M) : + NULL; ///< set connection parameters for 2M + + /** set connection parameters for coded */ + ble_gap_connection_parameter_t connection_parameter_coded; ///< connection parameter for coded + ble_gap_connection_phy_parameter_t connection_phy_coded; ///< connection phy for coded + ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_coded, + &connection_phy_coded, + &connection_parameter_coded); ///< select connection parameters for coded + connection_parameter.p_conn_param_coded = + p_connection_parameter->p_connection_phy_parameter_coded ? (st_ble_gap_conn_phy_param_t *) (& + connection_phy_coded) + : + NULL; ///< set connection parameters for coded + if (NULL != p_connection_parameter->p_connection_phy_parameter_coded) + { + connection_phy_coded.scan_intv = BLE_ABS_CONN_SC_INTV_SLOW; + connection_phy_coded.scan_window = BLE_ABS_CONN_SC_WINDOW_SLOW; + } + + /** create timer for cancel */ + if (0 != p_connection_parameter->connection_timeout) + { + ble_abs_timer_create(p_instance_ctrl, + &p_instance_ctrl->connection_timer_handle, + (uint32_t) (p_connection_parameter->connection_timeout * + BLE_ABS_GAP_EVENT_CONNECTION_TIMEOUT_1000), + BLE_TIMER_ONE_SHOT, + (ble_abs_timer_cb_t) ble_abs_cancel_connection_function); + } + + ble_status_t retval = BLE_SUCCESS; + retval = R_BLE_GAP_CreateConn(&connection_parameter); ///< create connection + if (0 != p_connection_parameter->connection_timeout) + { + if (BLE_SUCCESS == retval) + { + ret = ble_abs_timer_start(p_instance_ctrl, p_instance_ctrl->connection_timer_handle); + } + else + { + ret = ble_abs_timer_delete(p_instance_ctrl, &p_instance_ctrl->connection_timer_handle); + } + } + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, ret); + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_CreateConnection() */ + +/*******************************************************************************************************************//** + * Start pairing or encryption. If pairing has been done, start encryption. + * The pairing parameters are configured by RM_BLE_ABS_Open() or R_BLE_GAP_SetPairingParams(). + * If the pairing parameters are configure by RM_BLE_ABS_Open(), + * - bonding policy is that bonding information is stored. + * - Key press notification is not supported. + * Implements @ref ble_abs_api_t::startAuthentication. + * + * Example: + * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartAuthentication + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or connection_handle are specified as NULL. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_ARGUMENT The connection handle parameter is out of range. + **********************************************************************************************************************/ +fsp_err_t RM_BLE_ABS_StartAuthentication (ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle) +{ + st_ble_gap_auth_info_t security_information; + ble_status_t retval; + + ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + retval = R_BLE_GAP_GetDevSecInfo(connection_handle, &security_information); ///< check security information + if (BLE_SUCCESS == retval) + { + retval = R_BLE_GAP_StartEnc(connection_handle); + } + else + { + retval = R_BLE_GAP_StartPairing(connection_handle); + } + + FSP_ERROR_RETURN(BLE_ERR_INVALID_HDL != retval, FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} /* End of function RM_BLE_ABS_StartAuthentication() */ + +/************************************************ + * static function definitions * + ***********************************************/ + +/*******************************************************************************************************************//** + * Set Abstraction API connection parameters to GAP connection parameters. + **********************************************************************************************************************/ +static void ble_abs_set_connection_parameter (ble_abs_connection_phy_parameter_t * p_abs_connection_parameter, + ble_gap_connection_phy_parameter_t * p_connection_phy_parameter, + ble_gap_connection_parameter_t * p_connection_parameter) +{ + if (NULL != p_abs_connection_parameter) + { + p_connection_parameter->conn_intv_min = p_abs_connection_parameter->connection_interval; + p_connection_parameter->conn_intv_max = p_abs_connection_parameter->connection_interval; + p_connection_parameter->conn_latency = p_abs_connection_parameter->connection_slave_latency; + p_connection_parameter->sup_to = p_abs_connection_parameter->supervision_timeout; + p_connection_parameter->min_ce_length = BLE_ABS_GAP_CONNECTION_CE_LENGTH; + p_connection_parameter->max_ce_length = BLE_ABS_GAP_CONNECTION_CE_LENGTH; + p_connection_phy_parameter->scan_intv = BLE_ABS_CONN_SC_INTV_FAST; + p_connection_phy_parameter->scan_window = BLE_ABS_CONN_SC_WINDOW_FAST; + p_connection_phy_parameter->p_conn_param = p_connection_parameter; + } +} /* End of function ble_abs_set_connection_parameter() */ + +/*******************************************************************************************************************//** + * Set pairing parameters. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_ASSERTION parameter is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT The pairing parameter is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_set_pairing_parameter (ble_abs_pairing_parameter_t * p_pairing_parameter) +{ + FSP_ASSERT(p_pairing_parameter); + + st_ble_gap_pairing_param_t pairing_parameter; + + pairing_parameter.iocap = p_pairing_parameter->io_capabilitie_local_device; + pairing_parameter.mitm = p_pairing_parameter->mitm_protection_policy; + pairing_parameter.bonding = BLE_GAP_BONDING; + pairing_parameter.max_key_size = BLE_ABS_SET_PAIRING_MAXIMUM_LTK_SIZE; + pairing_parameter.min_key_size = p_pairing_parameter->maximum_key_size; + pairing_parameter.loc_key_dist = p_pairing_parameter->local_key_distribute; + pairing_parameter.rem_key_dist = p_pairing_parameter->remote_key_distribute; + pairing_parameter.key_notf = BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT; + pairing_parameter.sec_conn_only = p_pairing_parameter->secure_connection_only; + + FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetPairingParams(&pairing_parameter), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} /* End of function ble_abs_set_pairing_parameter() */ + +#if (BLE_CFG_LIBRARY_TYPE != 0) + +/*******************************************************************************************************************//** + * Advertising timer handler for legacy advertising. + **********************************************************************************************************************/ +static void ble_abs_advertising_to_function (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_handle) +{ + R_BLE_GAP_StopAdv(BLE_ABS_COMMON_HDL); + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_ABS_ADV_COMM_TO, 0); +} /* End of function ble_abs_advertising_to_function() */ + +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + +/*******************************************************************************************************************//** + * Cancel a request for connection. + **********************************************************************************************************************/ +static void ble_abs_cancel_connection_function (void) +{ + R_BLE_GAP_CancelCreateConn(); +} /* End of function ble_abs_cancel_connection_function() */ + +/*******************************************************************************************************************//** + * Configure scan response data and start legacy advertising. + **********************************************************************************************************************/ +static void ble_abs_set_legacy_scan_response_data (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.legacy_advertising_parameter. + scan_response_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.legacy_advertising_parameter. + p_scan_response_data)) + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status & BLE_ABS_ADV_STATUS_SRES_DATA) + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL); + } + else + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_SCAN_RSP_DATA_MODE); + } + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL); + } +} /* End of function ble_abs_set_legacy_scan_response_data() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_ADV_PARAM_SET_COMP event. + **********************************************************************************************************************/ +void ble_abs_advertising_parameter_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data) +{ +#if (BLE_CFG_LIBRARY_TYPE == 0) + st_ble_gap_adv_set_evt_t * p_advertising_set_parameter; + p_advertising_set_parameter = (st_ble_gap_adv_set_evt_t *) p_event_data->p_param; + + switch (p_advertising_set_parameter->adv_hdl) + { + case BLE_ABS_LEGACY_HDL: + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW))) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.p_advertising_data)) + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status & + BLE_ABS_ADV_STATUS_ADV_DATA) + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + else + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_ADV_DATA_MODE); + } + } + else + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + } + + break; + } + + case BLE_ABS_EXT_HDL: + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW))) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter. + extend_advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter. + extend_advertising_parameter.p_advertising_data)) + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status & + BLE_ABS_ADV_STATUS_ADV_DATA) + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_EXT_HDL); + } + else + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_EXT_HDL, BLE_GAP_ADV_DATA_MODE); + } + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_EXT_HDL); + } + } + + break; + } + + case BLE_ABS_NON_CONN_HDL: + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_status & + BLE_ABS_ADV_STATUS_PARAM_SLOW) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter. + non_connectable_advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter. + non_connectable_advertising_parameter.p_advertising_data)) + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_NON_CONN_HDL, BLE_GAP_ADV_DATA_MODE); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_NON_CONN_HDL); + } + } + + break; + } + + default /* BLE_ABS_PERD_HDL */: + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW) + { + st_ble_gap_perd_adv_param_t periodic_parameter; + periodic_parameter.adv_hdl = BLE_ABS_PERD_HDL; + periodic_parameter.prop_type = 0x0000; + periodic_parameter.perd_intv_min = + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter + .periodic_advertising_interval; + periodic_parameter.perd_intv_max = periodic_parameter.perd_intv_min; + R_BLE_GAP_SetPerdAdvParam(&periodic_parameter); + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_ABS_ADV_STATUS_PERD_PARAM, 0); + } + + break; + } + } + +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & + (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW))) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter.p_advertising_data)) + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & + BLE_ABS_ADV_STATUS_ADV_DATA) + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + else + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_GAP_ADV_DATA_MODE); + } + } + else + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + } + } + else + { + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + non_connectable_advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + non_connectable_advertising_parameter.p_advertising_data)) + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_GAP_ADV_DATA_MODE); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_NON_CONN_HDL); + } + } + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function ble_abs_advertising_parameter_set_handler() */ + +/*******************************************************************************************************************//** + * Start advertising. + * + * @retval FSP_SUCCESS Operation succeeded. + **********************************************************************************************************************/ +static void ble_abs_advertising_start (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle) +{ + ble_status_t retval = BLE_SUCCESS; + + uint32_t status = 0; + +#if (BLE_CFG_LIBRARY_TYPE == 0) + uint16_t fast_period = (uint16_t) ((BLE_ABS_LEGACY_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.fast_advertising_period : + (BLE_ABS_EXT_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter. + extend_advertising_parameter.fast_advertising_period : + 0x0000); + uint16_t slow_period = (uint16_t) ((BLE_ABS_LEGACY_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.slow_advertising_period : + (BLE_ABS_EXT_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter. + extend_advertising_parameter.slow_advertising_period : + (BLE_ABS_NON_CONN_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter. + non_connectable_advertising_parameter.advertising_duration : + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter.advertising_parameter.advertising_duration); +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + uint16_t fast_period = + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.legacy_advertising_parameter. + fast_advertising_period; + uint16_t slow_period = + (uint16_t) ((0 != + (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & + BLE_ABS_ADV_COMM_LEG)) ? + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter.slow_advertising_period : + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + non_connectable_advertising_parameter.advertising_duration); + uint32_t to = slow_period; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + if (0x0000 == fast_period) + { +#if (BLE_CFG_LIBRARY_TYPE == 0) + if ((BLE_ABS_PERD_HDL == advertising_handle) && + (!(p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PERD_START))) + { + retval = R_BLE_GAP_StartPerdAdv(BLE_ABS_PERD_HDL); + status = BLE_ABS_ADV_STATUS_PERD_START; + } + else +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + { + retval = R_BLE_GAP_StartAdv(advertising_handle, slow_period, 0x0000); + status = BLE_ABS_ADV_STATUS_ADV_SLOW_START; + } + } + else + { + if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW) + { + retval = R_BLE_GAP_StartAdv(advertising_handle, slow_period, 0x0000); + status = BLE_ABS_ADV_STATUS_ADV_SLOW_START; + } + else + { +#if (BLE_CFG_LIBRARY_TYPE != 0) + to = fast_period; +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + retval = R_BLE_GAP_StartAdv(advertising_handle, fast_period, 0x0000); + status = BLE_ABS_ADV_STATUS_ADV_FAST_START; + } + } + + if (BLE_SUCCESS == retval) + { +#if (BLE_CFG_LIBRARY_TYPE != 0) + if (0 != to) + { + ble_abs_timer_create(p_instance_ctrl, + &p_instance_ctrl->advertising_timer_handle, + (to * 10), + BLE_TIMER_ONE_SHOT, + ble_abs_advertising_to_function); + ble_abs_timer_start(p_instance_ctrl, p_instance_ctrl->advertising_timer_handle); + } +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0); + } +} /* End of function ble_abs_advertising_start() */ + +/*******************************************************************************************************************//** + * Configure advertising data or scan response data or periodic advertising data. + * + * @retval FSP_SUCCESS Operation succeeded. + **********************************************************************************************************************/ +static void ble_abs_advertising_set_data (ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint8_t advertising_handle, + uint8_t data_type) +{ + st_ble_gap_adv_data_t advertising_data; + ble_status_t retval = BLE_SUCCESS; + uint32_t status = 0; + + advertising_data.adv_hdl = advertising_handle; + advertising_data.zero_length_flag = BLE_GAP_DATA_0_CLEAR; +#if (BLE_CFG_LIBRARY_TYPE == 0) + switch (advertising_handle) + { + case BLE_ABS_LEGACY_HDL: + { + status = (BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_ABS_ADV_STATUS_ADV_DATA : + BLE_ABS_ADV_STATUS_SRES_DATA; + advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_GAP_ADV_DATA_MODE : + BLE_GAP_SCAN_RSP_DATA_MODE); + advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL]. + advertising_parameter.legacy_advertising_parameter. + advertising_data_length : + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL]. + advertising_parameter.legacy_advertising_parameter. + scan_response_data_length); + advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.p_advertising_data : + p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter. + legacy_advertising_parameter.p_scan_response_data; + break; + } + + case BLE_ABS_EXT_HDL: + case BLE_ABS_NON_CONN_HDL: + { + status = BLE_ABS_ADV_STATUS_ADV_DATA; + advertising_data.data_type = BLE_GAP_ADV_DATA_MODE; + advertising_data.data_length = (uint16_t) ((BLE_ABS_EXT_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL]. + advertising_parameter.extend_advertising_parameter. + advertising_data_length : + p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL]. + advertising_parameter.non_connectable_advertising_parameter. + advertising_data_length); + advertising_data.p_data = (BLE_ABS_EXT_HDL == advertising_handle) ? + p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter. + extend_advertising_parameter.p_advertising_data : + p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter. + non_connectable_advertising_parameter.p_advertising_data; + break; + } + + default /* BLE_ABS_PERD_HDL */: + { + status = (BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_ABS_ADV_STATUS_ADV_DATA : + BLE_ABS_ADV_STATUS_PERD_DATA; + advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_GAP_ADV_DATA_MODE : + BLE_GAP_PERD_ADV_DATA_MODE); + advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL]. + advertising_parameter.periodic_advertising_parameter. + advertising_parameter.advertising_data_length : + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL]. + advertising_parameter.periodic_advertising_parameter. + periodic_advertising_data_length); + advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter.advertising_parameter.p_advertising_data : + p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter.p_periodic_advertising_data; + break; + } + } + +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG) + { + status = (BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_ABS_ADV_STATUS_ADV_DATA : + BLE_ABS_ADV_STATUS_SRES_DATA; + advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + BLE_GAP_ADV_DATA_MODE : + BLE_GAP_SCAN_RSP_DATA_MODE); + advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL]. + advertising_parameter.legacy_advertising_parameter. + advertising_data_length : + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL]. + advertising_parameter.legacy_advertising_parameter. + scan_response_data_length); + advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ? + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter.p_advertising_data : + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter.p_scan_response_data; + } + else + { + status = BLE_ABS_ADV_STATUS_ADV_DATA; + advertising_data.data_type = BLE_GAP_ADV_DATA_MODE; + advertising_data.data_length = + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + non_connectable_advertising_parameter + .advertising_data_length; + advertising_data.p_data = + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + non_connectable_advertising_parameter + .p_advertising_data; + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + retval = R_BLE_GAP_SetAdvSresData(&advertising_data); + if (BLE_SUCCESS == retval) + { + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0); + } +} /* End of function ble_abs_advertising_set_data() */ + +/*******************************************************************************************************************//** + * Configure advertising data or scan response data or periodic advertising data. + **********************************************************************************************************************/ +static void ble_abs_periodic_parameter_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ +#if (BLE_CFG_LIBRARY_TYPE == 0) + if (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PERD_PARAM) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.periodic_advertising_parameter. + advertising_parameter.advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.periodic_advertising_parameter. + advertising_parameter.p_advertising_data)) + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_ADV_DATA_MODE); + } + else + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter.periodic_advertising_data_length) && + (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter. + periodic_advertising_parameter.p_periodic_advertising_data)) + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_PERD_ADV_DATA_MODE); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL); + } + } + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function ble_abs_periodic_parameter_handler() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_ADV_DATA_UPD_COMP event. + **********************************************************************************************************************/ +static void ble_abs_advertising_data_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data) +{ + st_ble_gap_adv_data_evt_t * p_advertising_data_set_parameter; + + p_advertising_data_set_parameter = (st_ble_gap_adv_data_evt_t *) p_event_data->p_param; + +#if (BLE_CFG_LIBRARY_TYPE == 0) + switch (p_advertising_data_set_parameter->adv_hdl) + { + case BLE_ABS_LEGACY_HDL: + { + if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type) + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL); + } + + break; + } + + case BLE_ABS_EXT_HDL: + case BLE_ABS_NON_CONN_HDL: + { + ble_abs_advertising_start(p_instance_ctrl, p_advertising_data_set_parameter->adv_hdl); + break; + } + + default: /* BLE_ABS_PERD_HDL */ + { + if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type) + { + ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_PERD_ADV_DATA_MODE); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL); + } + + break; + } + } + +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG) + { + if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type) + { + ble_abs_set_legacy_scan_response_data(p_instance_ctrl); + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_COMMON_HDL); + } + } + else + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_COMMON_HDL); + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function ble_abs_advertising_data_set_handler() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_ADV_OFF event. + **********************************************************************************************************************/ +static void ble_abs_advertising_off_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data) +{ + st_ble_gap_adv_off_evt_t * p_advertising_off_parameter; + + p_advertising_off_parameter = (st_ble_gap_adv_off_evt_t *) p_event_data->p_param; + +#if (BLE_CFG_LIBRARY_TYPE == 0) + switch (p_advertising_off_parameter->adv_hdl) + { + case BLE_ABS_LEGACY_HDL: + case BLE_ABS_EXT_HDL: + { + if (0x02 == p_advertising_off_parameter->reason) + { + if ((p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].advertising_status & + BLE_ABS_ADV_STATUS_ADV_FAST_START)) + { + st_ble_gap_adv_param_t advertising_parameter; + + ble_abs_set_advertising_status(p_instance_ctrl, + p_advertising_off_parameter->adv_hdl, + 0, + BLE_ABS_ADV_STATUS_ADV_FAST_START); ///< fast -> slow + + if (BLE_ABS_LEGACY_HDL == p_advertising_off_parameter->adv_hdl) + { + ble_abs_convert_legacy_advertising_parameter(&p_instance_ctrl->advertising_sets[ + p_advertising_off_parameter->adv_hdl].advertising_parameter.legacy_advertising_parameter, + &advertising_parameter); + advertising_parameter.adv_intv_min = + p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl]. + advertising_parameter. + legacy_advertising_parameter.slow_advertising_interval; + advertising_parameter.adv_intv_max = + p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl]. + advertising_parameter. + legacy_advertising_parameter.slow_advertising_interval; + } + else + { + ble_abs_convert_extend_advertising_parameter(&p_instance_ctrl->advertising_sets[ + p_advertising_off_parameter->adv_hdl].advertising_parameter.extend_advertising_parameter, + &advertising_parameter); + advertising_parameter.adv_intv_min = + p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl]. + advertising_parameter. + extend_advertising_parameter.slow_advertising_interval; + advertising_parameter.adv_intv_max = + p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl]. + advertising_parameter. + extend_advertising_parameter.slow_advertising_interval; + } + + R_BLE_GAP_SetAdvParam(&advertising_parameter); + ble_abs_set_advertising_status(p_instance_ctrl, + p_advertising_off_parameter->adv_hdl, + BLE_ABS_ADV_STATUS_PARAM_SLOW, + 0); + } + else + { + if ((p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].advertising_status & + BLE_ABS_ADV_STATUS_ADV_SLOW_START)) + { + ble_abs_set_advertising_status(p_instance_ctrl, + p_advertising_off_parameter->adv_hdl, + 0, + BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off + } + } + } + else + { + ble_abs_set_advertising_status(p_instance_ctrl, + p_advertising_off_parameter->adv_hdl, + 0, + (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START)); + } + + break; + } + + case BLE_ABS_NON_CONN_HDL: + { + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_NON_CONN_HDL, 0, BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off + break; + } + + default: /* BLE_ABS_PERD_HDL */ + { + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, 0, BLE_ABS_ADV_STATUS_ADV_SLOW_START); + if (0 != + (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & + BLE_ABS_ADV_STATUS_PERD_START)) + { + R_BLE_GAP_StopPerdAdv(BLE_ABS_PERD_HDL); + } + + break; + } + } + +#else /* (BLE_CFG_LIBRARY_TYPE == 0) */ + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_TO) + { + p_advertising_off_parameter->reason = 0x02; + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, 0, BLE_ABS_ADV_COMM_TO); + } + + if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG) + { + if (0x02 == p_advertising_off_parameter->reason) + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & + BLE_ABS_ADV_STATUS_ADV_FAST_START)) + { + st_ble_gap_adv_param_t advertising_parameter; + + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_COMMON_HDL, + 0, + BLE_ABS_ADV_STATUS_ADV_FAST_START); ///< fast -> slow + + ble_abs_convert_legacy_advertising_parameter( + &p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.legacy_advertising_parameter, + &advertising_parameter); + advertising_parameter.adv_intv_min = + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter + .slow_advertising_interval; + advertising_parameter.adv_intv_max = + p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter. + legacy_advertising_parameter + .slow_advertising_interval; + + R_BLE_GAP_SetAdvParam(&advertising_parameter); + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0); + } + else + { + if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & + BLE_ABS_ADV_STATUS_ADV_SLOW_START)) + { + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_COMMON_HDL, + 0, + BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off + } + } + } + else + { + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_COMMON_HDL, + 0, + (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START | + BLE_ABS_ADV_COMM_LEG)); + } + } + else + { + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_COMMON_HDL, + 0, + (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_COMM_NON)); ///< slow -> off + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ +} /* End of function ble_abs_advertising_off_handler() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_ADV_REPT_IND event. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Filtering data is not included in the advertising data. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_advertising_report_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data) +{ + st_ble_gap_adv_rept_evt_t * p_advertising_report_parameter; + uint8_t * p_buf = NULL; + uint32_t len = 0; + fsp_err_t retval = FSP_ERR_BLE_ABS_NOT_FOUND; + + if ((NULL == p_instance_ctrl->abs_scan.scan_parameter.p_filter_data) || + (0 == p_instance_ctrl->abs_scan.scan_parameter.filter_data_length)) + { + retval = FSP_SUCCESS; + } + else + { + p_advertising_report_parameter = (st_ble_gap_adv_rept_evt_t *) p_event_data->p_param; + + switch (p_advertising_report_parameter->adv_rpt_type) + { + /*Legacy Advertising Report.*/ + case 0x00: + { + p_buf = p_advertising_report_parameter->param.p_adv_rpt->p_data; + len = p_advertising_report_parameter->param.p_adv_rpt->len; + + break; + } + + /*Extended Advertising Report.*/ + case 0x01: + { + p_buf = p_advertising_report_parameter->param.p_ext_adv_rpt->p_data; + len = p_advertising_report_parameter->param.p_ext_adv_rpt->len; + + break; + } + + /*Periodic Advertising Report.*/ + case 0x02: + { + p_buf = p_advertising_report_parameter->param.p_per_adv_rpt->p_data; + len = p_advertising_report_parameter->param.p_per_adv_rpt->len; + break; + } + + default: + { + break; + } + } + + uint32_t cnt = len - (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length + 1; + + if (1 <= cnt) + { + uint32_t i; + uint16_t pos = 0U; + + while (pos < len) + { + /* Each advertising structure have following constructs. + * - Lenght: 1 byte (The length of AD type + AD data) + * - AD type: 1 byte + * - AD data: variable + */ + uint8_t ad_len = (uint8_t) (p_buf[pos] - 1); + uint8_t type = p_buf[pos + 1]; + + if (type == p_instance_ctrl->abs_scan.scan_parameter.filter_ad_type) + { + for (i = 0; i < ad_len; i++) + { + if (0 == memcmp(&p_buf[pos + 2U + i], + p_instance_ctrl->abs_scan.scan_parameter.p_filter_data, + (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length)) + { + return FSP_SUCCESS; + } + } + } + + pos = (uint16_t) (pos + ad_len); + pos = (uint16_t) (pos + 2UL); + } + } + } + + return retval; +} /* End of function ble_abs_advertising_report_handler() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_LOC_VER_INFO event. + **********************************************************************************************************************/ +static void ble_abs_loc_ver_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, st_ble_evt_data_t * p_event_data) +{ + st_ble_gap_loc_dev_info_evt_t * event_parameter; + event_parameter = (st_ble_gap_loc_dev_info_evt_t *) p_event_data->p_param; + p_instance_ctrl->loc_bd_addr = event_parameter->l_dev_addr; +} /* End of function ble_abs_loc_ver_handler() */ + +/*******************************************************************************************************************//** + * Convert Abstraction API scan phy parameters to GAP scan phy parameters. + **********************************************************************************************************************/ +static void ble_abs_convert_scan_phy_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_abs_scan_phy_parameter_t * p_abs_phy, + ble_gap_scan_phy_parameter_t * p_gap_phy, + ble_gap_scan_on_t * p_scan_enable) +{ + if ((NULL != p_abs_phy) && (NULL != p_gap_phy)) + { + p_gap_phy->scan_type = p_abs_phy->scan_type; + + if (p_instance_ctrl->abs_scan.scan_parameter.fast_scan_period) + { + p_gap_phy->scan_intv = p_abs_phy->fast_scan_interval; + p_gap_phy->scan_window = p_abs_phy->fast_scan_window; + p_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.fast_scan_period; + } + else + { + p_gap_phy->scan_intv = p_abs_phy->slow_scan_interval; + p_gap_phy->scan_window = p_abs_phy->slow_scan_window; + p_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.slow_scan_period; + } + } +} /* End of function ble_abs_convert_scan_phy_parameter() */ + +/*******************************************************************************************************************//** + * Convert Abstraction API scan parameters to GAP scan parameters. + **********************************************************************************************************************/ +static void ble_abs_convert_scan_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_gap_scan_param_t * p_gap_scan_parameter, + ble_gap_scan_on_t * p_gap_scan_enable, + uint32_t status) +{ + p_gap_scan_parameter->o_addr_type = BLE_GAP_ADDR_PUBLIC; + p_gap_scan_parameter->filter_policy = p_instance_ctrl->abs_scan.scan_parameter.device_scan_filter_policy; + p_gap_scan_enable->proc_type = BLE_GAP_SC_PROC_OBS; + p_gap_scan_enable->period = 0; + p_gap_scan_enable->filter_dups = p_instance_ctrl->abs_scan.scan_parameter.filter_duplicate; + + if (BLE_ABS_SCAN_STATUS_FAST_START == status) + { + if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M) + { + ble_abs_convert_scan_phy_parameter(p_instance_ctrl, + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M, + (ble_gap_scan_phy_parameter_t *) p_gap_scan_parameter->p_phy_param_1M, + p_gap_scan_enable); + } + + if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded) + { + ble_abs_convert_scan_phy_parameter(p_instance_ctrl, + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded, + (ble_gap_scan_phy_parameter_t *) p_gap_scan_parameter->p_phy_param_coded, + p_gap_scan_enable); + } + } + else + { + if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M) + { + p_gap_scan_parameter->p_phy_param_1M->scan_type = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->scan_type; + p_gap_scan_parameter->p_phy_param_1M->scan_intv = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->slow_scan_interval; + p_gap_scan_parameter->p_phy_param_1M->scan_window = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->slow_scan_window; + } + + if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded) + { + p_gap_scan_parameter->p_phy_param_coded->scan_type = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->scan_type; + p_gap_scan_parameter->p_phy_param_coded->scan_intv = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->slow_scan_interval; + p_gap_scan_parameter->p_phy_param_coded->scan_window = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->slow_scan_window; + } + + p_gap_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.slow_scan_period; + } +} /* End of function ble_abs_convert_scan_parameter() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_SCAN_TO event. + **********************************************************************************************************************/ +static void ble_abs_scan_to_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + st_ble_gap_scan_param_t scan_parameter; + ble_gap_scan_phy_parameter_t phy_parameter_1M; + ble_gap_scan_phy_parameter_t phy_parameter_coded; + ble_gap_scan_on_t scan_enable; + + if (p_instance_ctrl->abs_scan.scan_status & BLE_ABS_SCAN_STATUS_FAST_START) + { + ble_abs_set_scan_status(p_instance_ctrl, 0, BLE_ABS_SCAN_STATUS_SLOW_START); ///< fast -> slow + scan_parameter.p_phy_param_1M = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M ? (st_ble_gap_scan_phy_param_t *) (& + phy_parameter_1M) + : + NULL; + scan_parameter.p_phy_param_coded = + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded ? (st_ble_gap_scan_phy_param_t *) (& + phy_parameter_coded) + : + NULL; + + ble_abs_convert_scan_parameter(p_instance_ctrl, &scan_parameter, &scan_enable, BLE_ABS_SCAN_STATUS_SLOW_START); + + R_BLE_GAP_StartScan(&scan_parameter, (st_ble_gap_scan_on_t *) &scan_enable); + ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_SLOW_START, BLE_ABS_SCAN_STATUS_FAST_START); + } + else + { + if (p_instance_ctrl->abs_scan.scan_status & BLE_ABS_SCAN_STATUS_SLOW_START) + { + ble_abs_set_scan_status(p_instance_ctrl, 0, BLE_ABS_SCAN_STATUS_SLOW_START); ///< slow -> off + } + } +} /* End of function ble_abs_scan_to_handler() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_CONN_IND event. + **********************************************************************************************************************/ +static void ble_abs_connection_indication_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + ble_abs_timer_stop(p_instance_ctrl, p_instance_ctrl->connection_timer_handle); + ble_abs_timer_delete(p_instance_ctrl, &p_instance_ctrl->connection_timer_handle); + +#if (BLE_CFG_LIBRARY_TYPE != 0) + ble_abs_timer_stop(p_instance_ctrl, p_instance_ctrl->advertising_timer_handle); + + ble_abs_set_advertising_status(p_instance_ctrl, + BLE_ABS_COMMON_HDL, + 0, + (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START | + BLE_ABS_ADV_COMM_LEG)); +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ +} /* End of function ble_abs_connection_indication_handler() */ + +/*******************************************************************************************************************//** + * Set gap callback and vendor specific callback function. + **********************************************************************************************************************/ +static void ble_abs_set_abs_callback (ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_gap_application_callback_t gap_callback, + ble_vendor_specific_application_callback_t vendor_specific_callback) +{ + p_instance_ctrl->abs_gap_callback = gap_callback; + p_instance_ctrl->abs_vendor_specific_callback = vendor_specific_callback; +} /* End of function ble_abs_set_abs_callback() */ + +/*******************************************************************************************************************//** + * Set advertising interval. + **********************************************************************************************************************/ +static void ble_abs_set_connection_advertising_interval (st_ble_gap_adv_param_t * p_advertising_parameter, + uint32_t fast_advertising_interval, + uint32_t slow_advertising_interval, + uint16_t fast_period) +{ + /** check advertising interval */ + if (fast_period) + { + p_advertising_parameter->adv_intv_min = fast_advertising_interval; + p_advertising_parameter->adv_intv_max = fast_advertising_interval; + } + else + { + p_advertising_parameter->adv_intv_min = slow_advertising_interval; + p_advertising_parameter->adv_intv_max = slow_advertising_interval; + } +} /* End of function ble_abs_set_connection_advertising_interval() */ + +/*******************************************************************************************************************//** + * Update advertising data status. + **********************************************************************************************************************/ +static void ble_abs_update_data_status (ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint32_t advertising_status, + uint8_t * p_advertising_data, + uint16_t advertising_data_len, + uint8_t advertising_handle) +{ + if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & advertising_status) + { + if ((0 != advertising_data_len) && (NULL != p_advertising_data)) + { + ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0, advertising_status); + } + } +} /* End of function ble_abs_update_data_status() */ + +/*******************************************************************************************************************//** + * Convert the legacy advertising parameters to GAP advertising parameters. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_convert_legacy_advertising_parameter ( + ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter) +{ + p_gap_advertising_parameter->adv_hdl = BLE_ABS_LEGACY_HDL; + p_gap_advertising_parameter->adv_prop_type = BLE_GAP_LEGACY_PROP_ADV_IND; + p_gap_advertising_parameter->adv_ch_map = p_legacy_advertising_parameter->advertising_channel_map; + + FSP_ERROR_RETURN((BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_legacy_advertising_parameter->own_bluetooth_address_type), + FSP_ERR_INVALID_ARGUMENT); + + memcpy(p_gap_advertising_parameter->o_addr, + (void *) p_legacy_advertising_parameter->own_bluetooth_address, + BLE_BD_ADDR_LEN); + + p_gap_advertising_parameter->o_addr_type = p_legacy_advertising_parameter->own_bluetooth_address_type; + + if (p_legacy_advertising_parameter->p_peer_address) + { + memcpy(p_gap_advertising_parameter->p_addr, + p_legacy_advertising_parameter->p_peer_address->addr, + BLE_BD_ADDR_LEN); + p_gap_advertising_parameter->p_addr_type = p_legacy_advertising_parameter->p_peer_address->type; + } + else + { + p_gap_advertising_parameter->p_addr_type = BLE_GAP_ADDR_PUBLIC; + } + + FSP_ERROR_RETURN( + BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST >= p_legacy_advertising_parameter->advertising_filter_policy, + FSP_ERR_INVALID_ARGUMENT); + + p_gap_advertising_parameter->filter_policy = p_legacy_advertising_parameter->advertising_filter_policy; + + p_gap_advertising_parameter->adv_phy = BLE_GAP_ADV_PHY_1M; + p_gap_advertising_parameter->sec_adv_max_skip = 0x00; + p_gap_advertising_parameter->sec_adv_phy = BLE_GAP_ADV_PHY_1M; + p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE; + + return FSP_SUCCESS; +} /* End of function ble_abs_convert_legacy_advertising_parameter() */ + +/*******************************************************************************************************************//** + * Convert the extended advertising parameters to GAP advertising parameters. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +#if (BLE_CFG_LIBRARY_TYPE == 0) +static fsp_err_t ble_abs_convert_extend_advertising_parameter ( + ble_abs_extend_advertising_parameter_t * p_extend_advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter) +{ + p_gap_advertising_parameter->adv_hdl = BLE_ABS_EXT_HDL; + p_gap_advertising_parameter->adv_ch_map = p_extend_advertising_parameter->advertising_channel_map; + + FSP_ERROR_RETURN((BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_extend_advertising_parameter->own_bluetooth_address_type), + FSP_ERR_INVALID_ARGUMENT); + + memcpy(p_gap_advertising_parameter->o_addr, + (void *) p_extend_advertising_parameter->own_bluetooth_address, + BLE_BD_ADDR_LEN); + + p_gap_advertising_parameter->o_addr_type = p_extend_advertising_parameter->own_bluetooth_address_type; + + if (p_extend_advertising_parameter->p_peer_address) + { + memcpy(p_gap_advertising_parameter->p_addr, + p_extend_advertising_parameter->p_peer_address->addr, + BLE_BD_ADDR_LEN); + p_gap_advertising_parameter->p_addr_type = p_extend_advertising_parameter->p_peer_address->type; + p_gap_advertising_parameter->adv_prop_type = BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT; + } + else + { + p_gap_advertising_parameter->p_addr_type = BLE_GAP_ADDR_PUBLIC; + p_gap_advertising_parameter->adv_prop_type = BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT; + } + + FSP_ERROR_RETURN( + BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST >= p_extend_advertising_parameter->advertising_filter_policy, + FSP_ERR_INVALID_ARGUMENT); + + p_gap_advertising_parameter->filter_policy = p_extend_advertising_parameter->advertising_filter_policy; + + FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M == p_extend_advertising_parameter->primary_advertising_phy) || + (BLE_GAP_ADV_PHY_CD == p_extend_advertising_parameter->primary_advertising_phy), + FSP_ERR_INVALID_ARGUMENT); + + p_gap_advertising_parameter->adv_phy = p_extend_advertising_parameter->primary_advertising_phy; + p_gap_advertising_parameter->sec_adv_max_skip = 0x00; + + FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M <= p_extend_advertising_parameter->secondary_advertising_phy) && + (BLE_GAP_ADV_PHY_CD >= p_extend_advertising_parameter->secondary_advertising_phy), + FSP_ERR_INVALID_ARGUMENT); + + p_gap_advertising_parameter->sec_adv_phy = p_extend_advertising_parameter->secondary_advertising_phy; + p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE; + + return FSP_SUCCESS; +} /* End of function ble_abs_convert_extend_advertising_parameter() */ + +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + +/*******************************************************************************************************************//** + * Convert the non-connectable advertising parameters to GAP advertising parameters. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_convert_non_connectable_advertising_parameter ( + ble_abs_non_connectable_advertising_parameter_t * p_non_connectable_advertising_parameter, + st_ble_gap_adv_param_t * p_gap_advertising_parameter, + uint8_t advertising_handle) +{ + p_gap_advertising_parameter->adv_hdl = advertising_handle; + p_gap_advertising_parameter->adv_ch_map = p_non_connectable_advertising_parameter->advertising_channel_map; + + FSP_ERROR_RETURN( + (BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_non_connectable_advertising_parameter->own_bluetooth_address_type), + FSP_ERR_INVALID_ARGUMENT); + + memcpy(p_gap_advertising_parameter->o_addr, + (void *) p_non_connectable_advertising_parameter->own_bluetooth_address, + BLE_BD_ADDR_LEN); + + p_gap_advertising_parameter->o_addr_type = p_non_connectable_advertising_parameter->own_bluetooth_address_type; +#if (BLE_CFG_LIBRARY_TYPE != 0) + p_non_connectable_advertising_parameter->primary_advertising_phy = BLE_ABS_ADVERTISING_PHY_LEGACY; +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M >= p_non_connectable_advertising_parameter->primary_advertising_phy) || + (BLE_GAP_ADV_PHY_CD == p_non_connectable_advertising_parameter->primary_advertising_phy), + FSP_ERR_INVALID_ARGUMENT); +#if (BLE_CFG_LIBRARY_TYPE == 0) + FSP_ERROR_RETURN((BLE_ABS_ADVERTISING_PHY_LEGACY != p_non_connectable_advertising_parameter->primary_advertising_phy) || + (BLE_ABS_PERD_HDL != advertising_handle), + FSP_ERR_INVALID_ARGUMENT); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + p_gap_advertising_parameter->adv_phy = + (uint8_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY == + p_non_connectable_advertising_parameter->primary_advertising_phy) ? + BLE_GAP_ADV_PHY_1M : + p_non_connectable_advertising_parameter->primary_advertising_phy); + + if (p_non_connectable_advertising_parameter->p_peer_address) + { + memcpy(p_gap_advertising_parameter->p_addr, + p_non_connectable_advertising_parameter->p_peer_address->addr, + BLE_BD_ADDR_LEN); + p_gap_advertising_parameter->p_addr_type = p_non_connectable_advertising_parameter->p_peer_address->type; + p_gap_advertising_parameter->adv_prop_type = + (uint16_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY != + p_non_connectable_advertising_parameter->primary_advertising_phy) ? + BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT : + BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND); + } + else + { + p_gap_advertising_parameter->p_addr_type = BLE_GAP_ADDR_PUBLIC; + p_gap_advertising_parameter->adv_prop_type = + (uint16_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY != + p_non_connectable_advertising_parameter->primary_advertising_phy) ? + BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT : + BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND); + } + + p_gap_advertising_parameter->filter_policy = BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY; + p_gap_advertising_parameter->sec_adv_max_skip = 0x00; + + FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M <= p_non_connectable_advertising_parameter->secondary_advertising_phy) && + (BLE_GAP_ADV_PHY_CD >= p_non_connectable_advertising_parameter->secondary_advertising_phy), + FSP_ERR_INVALID_ARGUMENT); + + p_gap_advertising_parameter->sec_adv_phy = p_non_connectable_advertising_parameter->secondary_advertising_phy; + p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE; + + return FSP_SUCCESS; +} /* End of function ble_abs_convert_non_connectable_advertising_parameter() */ + +/*******************************************************************************************************************//** + * Set advertising status. + **********************************************************************************************************************/ +static void ble_abs_set_advertising_status (ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint8_t advertising_handle, + uint32_t set, + uint32_t clear) +{ + p_instance_ctrl->advertising_sets[advertising_handle].advertising_status |= set; + p_instance_ctrl->advertising_sets[advertising_handle].advertising_status &= ~clear; +} /* End of function ble_abs_set_advertising_status() */ + +/*******************************************************************************************************************//** + * Store advertising configuration. + **********************************************************************************************************************/ +static void ble_abs_set_advertising_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl, + void * p_advertising_parameter, + uint8_t advertising_handle) +{ + switch (advertising_handle) + { + case BLE_ABS_LEGACY_HDL: + { + ble_abs_legacy_advertising_parameter_t * p_abs_legacy; + p_abs_legacy = (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter; +#if (BLE_CFG_LIBRARY_TYPE != 0) + advertising_handle = BLE_ABS_COMMON_HDL; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + memcpy( + &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter, + p_abs_legacy, + sizeof(ble_abs_legacy_advertising_parameter_t)); + if (NULL != p_abs_legacy->p_peer_address) + { + memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address, + p_abs_legacy->p_peer_address, + sizeof(ble_device_address_t)); + p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter + .p_peer_address = &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address; + } + + break; + } + +#if (BLE_CFG_LIBRARY_TYPE == 0) + case BLE_ABS_EXT_HDL: + { + ble_abs_extend_advertising_parameter_t * p_abs_ext; + p_abs_ext = (ble_abs_extend_advertising_parameter_t *) p_advertising_parameter; + memcpy( + &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.extend_advertising_parameter, + p_abs_ext, + sizeof(ble_abs_extend_advertising_parameter_t)); + if (NULL != p_abs_ext->p_peer_address) + { + memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address, + p_abs_ext->p_peer_address, + sizeof(ble_device_address_t)); + p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.extend_advertising_parameter + .p_peer_address = &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address; + } + + break; + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + + case BLE_ABS_NON_CONN_HDL: + { + ble_abs_non_connectable_advertising_parameter_t * p_abs_non_conn; + p_abs_non_conn = (ble_abs_non_connectable_advertising_parameter_t *) p_advertising_parameter; +#if (BLE_CFG_LIBRARY_TYPE != 0) + advertising_handle = BLE_ABS_COMMON_HDL; +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + memcpy( + &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.non_connectable_advertising_parameter, + p_abs_non_conn, + sizeof(ble_abs_non_connectable_advertising_parameter_t)); + if (NULL != p_abs_non_conn->p_peer_address) + { + memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address, + p_abs_non_conn->p_peer_address, + sizeof(ble_device_address_t)); + p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter. + non_connectable_advertising_parameter.p_peer_address = + &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address; + } + + break; + } + + default: /** BLE_ABS_PERD_HDL */ +#if (BLE_CFG_LIBRARY_TYPE == 0) + { + ble_abs_periodic_advertising_parameter_t * p_abs_perd; + p_abs_perd = (ble_abs_periodic_advertising_parameter_t *) p_advertising_parameter; + memcpy( + &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.periodic_advertising_parameter, + p_abs_perd, + sizeof(ble_abs_periodic_advertising_parameter_t)); + if (NULL != p_abs_perd->advertising_parameter.p_peer_address) + { + memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address, + p_abs_perd->advertising_parameter.p_peer_address, + sizeof(ble_device_address_t)); + p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter. + periodic_advertising_parameter.advertising_parameter.p_peer_address = + &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address; + } + } +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + break; + } +} /* End of function ble_abs_set_advertising_parameter() */ + +/*******************************************************************************************************************//** + * Check scan phy parameters. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT The advertising parameter is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_check_scan_phy_parameter (ble_abs_scan_phy_parameter_t * p_scan_phy) +{ + FSP_ERROR_RETURN((BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->fast_scan_interval) && + (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->slow_scan_interval) && + (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->fast_scan_window) && + (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->slow_scan_window) && + (BLE_GAP_SCAN_ACTIVE >= p_scan_phy->scan_type), + FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Store scan configuration. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT Scan phy parameter is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_set_scan_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl, + ble_abs_scan_parameter_t * p_scan_parameter) +{ + if (p_scan_parameter->p_phy_parameter_1M) + { + FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_check_scan_phy_parameter(p_scan_parameter->p_phy_parameter_1M), + FSP_ERR_INVALID_ARGUMENT); ///< check abs scan parameters 1M + } + + if (p_scan_parameter->p_phy_parameter_coded) + { + FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_check_scan_phy_parameter(p_scan_parameter->p_phy_parameter_coded), + FSP_ERR_INVALID_ARGUMENT); ///< check abs scan parameters coded + } + + FSP_ERROR_RETURN(BLE_ABS_CONN_EXT_ADV_DATA_LEN >= p_scan_parameter->filter_data_length, FSP_ERR_INVALID_ARGUMENT); + + memcpy(&p_instance_ctrl->abs_scan.scan_parameter, p_scan_parameter, sizeof(ble_abs_scan_parameter_t)); + if (p_scan_parameter->p_phy_parameter_1M) + { + memcpy(&p_instance_ctrl->abs_scan.scan_phy_parameter_1M, + p_scan_parameter->p_phy_parameter_1M, + sizeof(ble_abs_scan_phy_parameter_t)); + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M = &p_instance_ctrl->abs_scan.scan_phy_parameter_1M; + } + + if (p_scan_parameter->p_phy_parameter_coded) + { + memcpy(&p_instance_ctrl->abs_scan.scan_phy_parameter_coded, + p_scan_parameter->p_phy_parameter_coded, + sizeof(ble_abs_scan_phy_parameter_t)); + p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded = + &p_instance_ctrl->abs_scan.scan_phy_parameter_coded; + } + + return FSP_SUCCESS; +} /* End of function ble_abs_set_scan_parameter() */ + +/*******************************************************************************************************************//** + * Set scan status. + **********************************************************************************************************************/ +static void ble_abs_set_scan_status (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t set, uint32_t clear) +{ + p_instance_ctrl->abs_scan.scan_status |= set; + p_instance_ctrl->abs_scan.scan_status &= ~clear; +} /* End of function ble_abs_set_scan_status() */ + +/*******************************************************************************************************************//** + * Register IRK to the Resolving List. + * + * @retval FSP_SUCCESS Operation succeeded. + **********************************************************************************************************************/ +static void ble_abs_set_irk_to_resolving_list (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t * p_lc_irk) +{ + st_ble_gap_rslv_list_key_set_t peer_irk; + ble_device_address_t remote_device_address; + ble_status_t retval = BLE_SUCCESS; + + memset(peer_irk.remote_irk, BLE_ABS_GAP_REMOTE_IRK_AA, BLE_GAP_IRK_SIZE); + peer_irk.local_irk_type = BLE_GAP_RL_LOC_KEY_REGISTERED; + memset(remote_device_address.addr, BLE_ABS_REMOTE_DEVICE_ADDRESS_55, BLE_BD_ADDR_LEN); + remote_device_address.type = BLE_GAP_ADDR_PUBLIC; + + R_BLE_GAP_SetLocIdInfo(&p_instance_ctrl->loc_bd_addr, p_lc_irk); + + /** store local id info */ + ble_abs_secure_data_writelocinfo(p_instance_ctrl->p_cfg->p_flash_instance, + (ble_device_address_t *) (&p_instance_ctrl->loc_bd_addr), + p_lc_irk, + NULL); ///< store local id info + + retval = R_BLE_GAP_ConfRslvList(BLE_GAP_LIST_ADD_DEV, (st_ble_dev_addr_t *) (&remote_device_address), &peer_irk, 1); + p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ? BLE_ABS_PV_STATUS_ADD_RSLV : 0; +} /* End of function ble_abs_set_irk_to_resolving_list() */ + +/*******************************************************************************************************************//** + * Handler for GAP BLE_GAP_EVENT_RSLV_LIST_CONF_COMP event. + * + * @retval FSP_SUCCESS Operation succeeded. + **********************************************************************************************************************/ +static void ble_abs_conflict_resolving_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_evt_data_t * p_event_data) +{ + if (p_instance_ctrl->set_privacy_status) + { + st_ble_gap_rslv_list_conf_evt_t * p_resolving_list_config; + ble_status_t retval = BLE_SUCCESS; + + p_resolving_list_config = (st_ble_gap_rslv_list_conf_evt_t *) p_event_data->p_param; + if (BLE_GAP_LIST_ADD_DEV == p_resolving_list_config->op_code) + { + ble_device_address_t remote_device_address; + memset(remote_device_address.addr, BLE_ABS_REMOTE_DEVICE_ADDRESS_55, BLE_BD_ADDR_LEN); + remote_device_address.type = 0x00; + retval = R_BLE_GAP_SetPrivMode((st_ble_dev_addr_t *) (&remote_device_address), + &p_instance_ctrl->privacy_mode, + 1); + p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ? + BLE_ABS_PV_STATUS_SET_MODE : + 0; + } + } +} /* End of function ble_abs_conflict_resolving_handler() */ + +/*******************************************************************************************************************//** + * GAP Event handler. + * + * @retval FSP_SUCCESS Operation succeeded. + **********************************************************************************************************************/ +static void ble_abs_gap_callback (uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data) +{ + ble_abs_instance_ctrl_t * p_instance_ctrl = gp_instance_ctrl; + + switch (event_type) + { + case BLE_GAP_EVENT_STACK_ON: + { + R_BLE_GAP_GetVerInfo(); + uint8_t irk[BLE_GAP_IRK_SIZE]; + ble_device_address_t identity_address; + fsp_err_t retval; + + ble_abs_secure_data_init(p_instance_ctrl->p_cfg->p_flash_instance); + retval = ble_abs_secure_data_readlocinfo(p_instance_ctrl->p_cfg->p_flash_instance, + &identity_address, + irk, + NULL); + if (FSP_SUCCESS == retval) + { + R_BLE_GAP_SetLocIdInfo((st_ble_dev_addr_t *) (&identity_address), irk); + } + + break; + } + + case BLE_GAP_EVENT_LOC_VER_INFO: + { + ble_abs_loc_ver_handler(p_instance_ctrl, p_event_data); + break; + } + + case BLE_GAP_EVENT_ADV_REPT_IND: + { + if (FSP_SUCCESS != ble_abs_advertising_report_handler(p_instance_ctrl, p_event_data)) + { + return; + } + + break; + } + + case BLE_GAP_EVENT_ADV_PARAM_SET_COMP: + { + ble_abs_advertising_parameter_set_handler(p_instance_ctrl, p_event_data); + break; + } + + case BLE_GAP_EVENT_ADV_DATA_UPD_COMP: + { + ble_abs_advertising_data_set_handler(p_instance_ctrl, p_event_data); + break; + } + + case BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP: + { + ble_abs_periodic_parameter_handler(p_instance_ctrl); + break; + } + + case BLE_GAP_EVENT_PERD_ADV_ON: + { + ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL); + break; + } + + case BLE_GAP_EVENT_PERD_ADV_OFF: + { + ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, 0, BLE_ABS_ADV_STATUS_PERD_START); + break; + } + + case BLE_GAP_EVENT_ADV_OFF: + { + ble_abs_advertising_off_handler(p_instance_ctrl, p_event_data); + break; + } + + case BLE_GAP_EVENT_SCAN_TO: + { + ble_abs_scan_to_handler(p_instance_ctrl); + break; + } + + case BLE_GAP_EVENT_CONN_IND: + { + ble_abs_connection_indication_handler(p_instance_ctrl); + break; + } + + case BLE_GAP_EVENT_CONN_PARAM_UPD_REQ: + { + st_ble_gap_conn_upd_req_evt_t * p_conn_upd_req_evt_param = + (st_ble_gap_conn_upd_req_evt_t *) p_event_data->p_param; + + st_ble_gap_conn_param_t conn_updt_param = + { + .conn_intv_min = p_conn_upd_req_evt_param->conn_intv_min, + .conn_intv_max = p_conn_upd_req_evt_param->conn_intv_max, + .conn_latency = p_conn_upd_req_evt_param->conn_latency, + .sup_to = p_conn_upd_req_evt_param->sup_to, + }; + + R_BLE_GAP_UpdConn(p_conn_upd_req_evt_param->conn_hdl, + BLE_GAP_CONN_UPD_MODE_RSP, + BLE_GAP_CONN_UPD_ACCEPT, + &conn_updt_param); + break; + } + + case BLE_GAP_EVENT_RSLV_LIST_CONF_COMP: + { + ble_abs_conflict_resolving_handler(p_instance_ctrl, p_event_data); + break; + } + + case BLE_GAP_EVENT_RPA_EN_COMP: + { + p_instance_ctrl->set_privacy_status = 0; + break; + } + + case BLE_GAP_EVENT_PRIV_MODE_SET_COMP: + { + if (BLE_ABS_PV_STATUS_SET_MODE == p_instance_ctrl->set_privacy_status) + { + ble_status_t retval = BLE_SUCCESS; + retval = R_BLE_GAP_EnableRpa(BLE_GAP_RPA_ENABLED); + p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ? + BLE_ABS_PV_STATUS_EN_RPA : + 0; + } + + break; + } + + case BLE_GAP_EVENT_PAIRING_REQ: + { + st_ble_gap_pairing_info_evt_t * p_param; + p_param = (st_ble_gap_pairing_info_evt_t *) p_event_data->p_param; + R_BLE_GAP_ReplyPairing(p_param->conn_hdl, BLE_GAP_PAIRING_ACCEPT); + break; + } + + case BLE_GAP_EVENT_PAIRING_COMP: + { + if (FSP_SUCCESS == event_result) + { + st_ble_gap_pairing_info_evt_t * p_param; + p_param = (st_ble_gap_pairing_info_evt_t *) p_event_data->p_param; + ble_abs_secure_data_writeremkeys(p_instance_ctrl->p_cfg->p_flash_instance, + (ble_device_address_t *) (&p_param->bd_addr), + &p_param->auth_info); + } + + break; + } + + case BLE_GAP_EVENT_PEER_KEY_INFO: + { + st_ble_gap_peer_key_info_evt_t * p_param; + p_param = (st_ble_gap_peer_key_info_evt_t *) p_event_data->p_param; + ble_abs_secure_data_recvremkeys((ble_device_address_t *) (&p_param->bd_addr), &p_param->key_ex_param); + break; + } + + case BLE_GAP_EVENT_EX_KEY_REQ: + { + st_ble_gap_conn_hdl_evt_t * p_param; + p_param = (st_ble_gap_conn_hdl_evt_t *) p_event_data->p_param; + R_BLE_GAP_ReplyExKeyInfoReq(p_param->conn_hdl); + break; + } + + case BLE_GAP_EVENT_LTK_REQ: + { + st_ble_gap_ltk_req_evt_t * p_param; + p_param = (st_ble_gap_ltk_req_evt_t *) p_event_data->p_param; + R_BLE_GAP_ReplyLtkReq(p_param->conn_hdl, p_param->ediv, p_param->p_peer_rand, BLE_GAP_LTK_REQ_ACCEPT); + break; + } + + default: + { + break; + } + } + + (*p_instance_ctrl).abs_gap_callback(event_type, event_result, p_event_data); +} /* End of function ble_abs_gap_callback() */ + +/*******************************************************************************************************************//** + * Handler for Vendor Specific BLE_VS_EVENT_GET_RAND event. + **********************************************************************************************************************/ +static void ble_abs_random_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, + st_ble_vs_evt_data_t * p_event_data) +{ + if (p_instance_ctrl->set_privacy_status) + { + st_ble_vs_get_rand_comp_evt_t * p_random_parameter; + p_random_parameter = (st_ble_vs_get_rand_comp_evt_t *) p_event_data->p_param; + ble_abs_set_irk_to_resolving_list(p_instance_ctrl, p_random_parameter->p_rand); + } +} /* End of function ble_abs_random_handler() */ + +/*******************************************************************************************************************//** + * Vendor Specific Event handler. + **********************************************************************************************************************/ +static void ble_abs_vendor_specific_callback (uint16_t event_type, + ble_status_t event_result, + st_ble_vs_evt_data_t * p_event_data) +{ + ble_abs_instance_ctrl_t * p_instance_ctrl = gp_instance_ctrl; + + switch (event_type) + { + case BLE_VS_EVENT_GET_RAND: + { + ble_abs_random_handler(p_instance_ctrl, p_event_data); + break; + } + + default: + { + break; + } + } + + if (p_instance_ctrl->abs_vendor_specific_callback) + { + p_instance_ctrl->abs_vendor_specific_callback(event_type, event_result, p_event_data); + } +} /* End of function ble_abs_vendor_specific_callback() */ + +/*** platform control functions added start ***/ + +void r_ble_rf_control_error (uint32_t err_no) +{ + FSP_PARAMETER_NOT_USED(err_no); +} + +uint8_t r_ble_rf_power_save_mode (void) +{ + uint8_t ret = BLE_ABS_CFG_RF_DEEP_SLEEP_EN; + + return ret; +} + +#if (BSP_CFG_RTOS == 2) +void r_ble_wake_up_task (void * EventGroupHandle) +{ + EventGroupHandle_t event_group_handle = (EventGroupHandle_t) EventGroupHandle; + + if (event_group_handle != NULL) + { + xEventGroupSetBits(event_group_handle, (EventBits_t) BLE_EVENT_PATTERN); + portYIELD(); + } +} + +void r_ble_wake_up_task_from_isr (void * EventGroupHandle) +{ + BaseType_t xHigherPriorityTaskWoken; + xHigherPriorityTaskWoken = pdFALSE; + EventGroupHandle_t event_group_handle = (EventGroupHandle_t) EventGroupHandle; + + if (event_group_handle != NULL) + { + xEventGroupSetBitsFromISR(event_group_handle, + (EventBits_t) BLE_EVENT_PATTERN, + &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +#endif + +/*** platform control functions end ***/ + +/*** r_ble_sec_data functions added start ***/ +#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) + +/*******************************************************************************************************************//** + * Write Local device Identity Address, IRK and/or CSRK in DataFlash. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_POINTER IRK(p_lc_id_addr or p_lc_irk) or CSRK(p_lc_csrk) + * is specified and as NULL. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Write to DataFlash is failed. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_writelocinfo (flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk) +{ + uint32_t local_tmp_data[(BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + 3) / 4]; + + FSP_ASSERT(p_lc_id_addr); + FSP_ASSERT(p_lc_irk); + FSP_ASSERT(p_lc_csrk); + + FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_secure_data_flash_read(p_instance, + BLE_ABS_SECURE_DATA_BASE_ADDR, + (uint8_t *) local_tmp_data, + BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE + + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE), + FSP_ERR_BLE_ABS_INVALID_OPERATION); + + if (NULL != p_lc_irk) + { + memcpy((uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE, p_lc_irk, BLE_GAP_IRK_SIZE); + memcpy( + (uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE + BLE_GAP_CSRK_SIZE, + p_lc_id_addr, + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE); + } + + if (NULL != p_lc_csrk) + { + memcpy((uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE, + p_lc_csrk, + BLE_GAP_CSRK_SIZE); + } + + local_tmp_data[0] = BLE_ABS_SECURE_DATA_MAGIC_NUMBER; + + FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_secure_data_flash_write(p_instance, + BLE_ABS_SECURE_DATA_BASE_ADDR, + (uint8_t *) local_tmp_data, + BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE + + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE), + FSP_ERR_BLE_ABS_INVALID_OPERATION); + + return FSP_SUCCESS; +} /* End of function ble_abs_secure_data_writelocinfo() */ + +/*******************************************************************************************************************//** + * Read Local device Identity Address and IRK and/or CSRK in DataFlash. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_POINTER IRK(p_lc_id_addr or p_lc_irk) or CSRK(p_lc_csrk) + * is specified and as NULL. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Read to DataFlash is failed. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND IRK and Identity Address not found. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_readlocinfo (flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk) +{ + fsp_err_t retval; + uint8_t * p_loc_area; + uint32_t mgc_num; + + p_loc_area = malloc(BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE); + FSP_ERROR_RETURN(NULL != p_loc_area, FSP_ERR_BLE_ABS_NOT_FOUND); + + retval = ble_abs_secure_data_flash_read(p_instance, + BLE_ABS_SECURE_DATA_ADDR_MGN_DATA, + p_loc_area, + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + + BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE); + if (FSP_SUCCESS != retval) + { + free(p_loc_area); + p_loc_area = NULL; + } + + FSP_ERROR_RETURN(FSP_SUCCESS == retval, FSP_ERR_BLE_ABS_INVALID_OPERATION); + + memcpy(&mgc_num, p_loc_area, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE); + if ((BLE_ABS_SECURE_DATA_MAGIC_NUMBER != mgc_num) && (NULL == p_loc_area)) + { + free(p_loc_area); + p_loc_area = NULL; + } + + FSP_ERROR_RETURN(BLE_ABS_SECURE_DATA_MAGIC_NUMBER != mgc_num, FSP_ERR_BLE_ABS_NOT_FOUND); + + if ((NULL != p_lc_irk) && (NULL != p_lc_id_addr)) + { + memcpy(p_lc_irk, &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE], BLE_GAP_IRK_SIZE); + memcpy(p_lc_id_addr, + &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE + BLE_GAP_CSRK_SIZE], + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE); + } + + if (NULL != p_lc_csrk) + { + memcpy(p_lc_csrk, &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE], BLE_GAP_CSRK_SIZE); + } + + if (NULL == p_loc_area) + { + free(p_loc_area); + } + + return FSP_SUCCESS; +} /* End of function ble_abs_secure_data_readlocinfo() */ + +/*******************************************************************************************************************//** + * Receive remote keys for write in DataFlash. + **********************************************************************************************************************/ +static void ble_abs_secure_data_recvremkeys (ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys) +{ + if ((NULL == p_addr) || (NULL == p_keys)) + { + return; + } + + (void) p_addr; + + memcpy((uint8_t *) &gs_key_ex_param, (uint8_t *) p_keys, BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE); ///< key_ex_parma + + memcpy((uint8_t *) &gs_key_dist, (uint8_t *) p_keys->p_keys_info, BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE); ///< keys +} /* End of function ble_abs_secure_data_recvremkeys() */ + +/*******************************************************************************************************************//** + * Write Remote Keys in DataFlash. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_POINTER p_addr or p_keyinfo is specified as NULL. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Write to DataFlash is failed. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Memory allocation is failed. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_writeremkeys (flash_instance_t const * p_instance, + ble_device_address_t * p_addr, + st_ble_gap_auth_info_t * p_keyinfo) +{ + fsp_err_t retval = FSP_SUCCESS; + int32_t entry; + int32_t op_code = BLE_SECD_UPD_BN_ADD; + uint32_t start_addr; + uint8_t bond_num; + uint8_t * p_sec_data; + + FSP_ASSERT(p_addr); + FSP_ASSERT(p_keyinfo); + + p_sec_data = malloc(BLE_ABS_SECURE_DATA_MAX_SIZE); ///< memory allocation + FSP_ERROR_RETURN(NULL != p_sec_data, FSP_ERR_BLE_ABS_NOT_FOUND); + + retval = ble_abs_secure_data_flash_read(p_instance, + BLE_ABS_SECURE_DATA_BASE_ADDR, + p_sec_data, + BLE_ABS_SECURE_DATA_MAX_SIZE); ///< read remote area + if (FSP_SUCCESS != retval) + { + free(p_sec_data); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == retval, FSP_ERR_BLE_ABS_INVALID_OPERATION); + + retval = ble_abs_secure_data_find_entry(p_addr, &entry, p_sec_data); ///< find entry with p_addr + if (FSP_SUCCESS != retval) + { + retval = ble_abs_secure_data_find_entry(NULL, &entry, p_sec_data); ///< find empty entry + if (FSP_SUCCESS != retval) + { + ble_abs_secure_data_find_oldest_entry(p_instance, &entry); ///< find oldest entry + + op_code = BLE_SECD_UPD_BN_ADD_OVERWR; ///< found the entry for overwrite + } + } + + start_addr = BLE_ABS_SECURE_DATA_ADDR_REM_START + (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE; + + memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE], + (uint8_t *) p_addr, + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE); ///< addr + + gs_key_ex_param.p_keys_info = (st_ble_gap_key_dist_t *) (start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET); ///< ex_key_param + memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET], + (uint8_t *) &gs_key_ex_param, + BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE); + + memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET], + (uint8_t *) &gs_key_dist, + BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE); ///< keys + + memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET], + (uint8_t *) p_keyinfo, + BLE_ABS_SECURE_DATA_REMOTE_KEYS_INFOMATION_SIZE); ///< keyinfo + + ble_abs_secure_data_update_bond_num(p_instance, entry, op_code, &bond_num, p_sec_data); ///< update bond order and the number of bonds. + + p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE] = bond_num; + + retval = ble_abs_secure_data_flash_write(p_instance, + BLE_ABS_SECURE_DATA_BASE_ADDR, + p_sec_data, + BLE_ABS_SECURE_DATA_MAX_SIZE); ///< write to DataFlash + free(p_sec_data); + + return retval; +} /* End of function ble_abs_secure_data_writeremkeys() */ + +/*******************************************************************************************************************//** + * Set bonding information in DataFlash to Host Stack. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_POINTER p_addr or p_keys is specified as NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Number of bonding information is out of range. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_init (flash_instance_t const * p_instance) +{ + uint8_t in_bond_num = 0; + uint8_t out_bond_num; + fsp_err_t ret = FSP_SUCCESS; + uint8_t * p_sec_data; + st_ble_gap_bond_info_t bond_info[BLE_ABS_CFG_NUMBER_BONDING] = {0}; + + ret = ble_abs_secure_data_read_bond_info(p_instance, &in_bond_num, &p_sec_data, bond_info); + FSP_ERROR_RETURN((FSP_SUCCESS == ret) || (FSP_ERR_BLE_ABS_NOT_FOUND == ret), ret); ///< Read bonding information from DataFlash. + + FSP_ERROR_RETURN(0 != in_bond_num, FSP_SUCCESS); ///< No bonding information is written in DataFlash. + + R_BLE_GAP_SetBondInfo(bond_info, in_bond_num, &out_bond_num); ///< Set bonding information in DataFlash to Host Stack. + + /** bonding info buffer release */ + ble_abs_secure_data_release_bond_info_buf(p_sec_data); ///< bonding info buffer release + + return ret; +} /* End of function ble_abs_secure_data_init() */ + +/*******************************************************************************************************************//** + * Find entry. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Empty entry is not found. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_find_entry (ble_device_address_t * p_dev_addr, + int32_t * p_entry, + uint8_t * p_sec_data) +{ + ble_device_address_t * p_addr; + int32_t i; + uint32_t mgc_num = BLE_ABS_SECURE_DATA_MAGIC_NUMBER; + fsp_err_t retval = FSP_ERR_BLE_ABS_NOT_FOUND; + + FSP_ERROR_RETURN((NULL == p_dev_addr) || + (0 == memcmp(p_sec_data, (uint8_t *) &mgc_num, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE)), + FSP_ERR_BLE_ABS_NOT_FOUND); ///< check magic number + + p_addr = (NULL == p_dev_addr) ? (ble_device_address_t *) &invalid_rem_addr : p_dev_addr; + + for (i = 0; i < BLE_ABS_CFG_NUMBER_BONDING; i++) + { + if (0 == + memcmp(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i * + BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE], + p_addr, + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE)) + { + *p_entry = i; + retval = FSP_SUCCESS; + } + } + + return retval; +} /* End of function ble_abs_secure_data_find_entry() */ + +/*******************************************************************************************************************//** + * Find the oldest entry. + **********************************************************************************************************************/ +static void ble_abs_secure_data_find_oldest_entry (flash_instance_t const * p_instance, int32_t * p_entry) +{ + uint8_t bond_order; + int32_t out_bond; + + ble_abs_secure_data_flash_read(p_instance, + BLE_ABS_SECURE_DATA_ADDR_MGN_DATA + BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET, + &bond_order, + 1); + out_bond = (int32_t) bond_order; + *p_entry = out_bond; +} /* End of function ble_abs_secure_data_find_oldest_entry() */ + +/*******************************************************************************************************************//** + * Update Bond Number + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Magic Numver read or write failuire. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_update_bond_num (flash_instance_t const * p_instance, + int32_t entry, + int32_t op_code, + uint8_t * p_alloc_bond_num, + uint8_t * p_sec_data) +{ + fsp_err_t retval = FSP_ERR_BLE_ABS_INVALID_OPERATION; + uint8_t bond_num; + uint8_t bond_order; + + bond_num = p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE]; + + switch (op_code) + { + case BLE_SECD_UPD_BN_ADD: + case BLE_SECD_UPD_BN_ADD_OVERWR: + { + /* update bond_num */ + if (BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF == bond_num) + { + bond_num = 1; + p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = 0; + uint32_t mgc_num = BLE_ABS_SECURE_DATA_MAGIC_NUMBER; + memcpy(p_sec_data, (uint8_t *) &mgc_num, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE); + } + else if (BLE_ABS_CFG_NUMBER_BONDING <= bond_num) + { + bond_num = BLE_ABS_CFG_NUMBER_BONDING; + } + else + { + bond_num++; + } + + p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE] = bond_num; + + /* update bond order */ + if (BLE_SECD_UPD_BN_ADD_OVERWR == op_code) + { + ble_abs_secure_data_update_bond_order(p_instance, entry, p_sec_data, 1); + } + + *p_alloc_bond_num = bond_num; + retval = FSP_SUCCESS; + break; + } + + default: /* BLE_SECD_UPD_BN_DEL & BLE_SECD_UPD_BN_ALL_DEL */ + { + if (BLE_ABS_CFG_NUMBER_BONDING >= bond_num) + { + /* update bond_num */ + if ((BLE_SECD_UPD_BN_ALL_DEL == op_code) || (0 == bond_num - 1)) + { + bond_num = BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF; + p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF; + } + else + { + bond_num = (uint8_t) (bond_num - 1); + } + + p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE] = bond_num; + + if (BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF != bond_num) + { + bond_order = p_sec_data[BLE_ABS_SECURE_DATA_ADDR_REM_START + + (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE]; + ble_abs_secure_data_update_bond_order(p_instance, entry, p_sec_data, bond_order); + } + + retval = FSP_SUCCESS; + } + + break; + } + } + + return retval; +} /* End of function ble_abs_secure_data_update_bond_num() */ + +/*******************************************************************************************************************//** + * Check entry validation + **********************************************************************************************************************/ +static void ble_abs_secure_data_update_bond_order (flash_instance_t const * p_instance, + int32_t entry, + uint8_t * p_sec_data, + uint8_t bond_order) +{ + fsp_err_t retval = FSP_ERR_BLE_ABS_INVALID_OPERATION; + int32_t i; + + for (i = 0; i < BLE_ABS_CFG_NUMBER_BONDING; i++) + { + if (entry != i) + { + retval = ble_abs_secure_data_is_valid_entry(p_instance, i); + if (FSP_SUCCESS != retval) + { + continue; + } + + uint8_t tmp_order; + tmp_order = + p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE]; + + if (bond_order < tmp_order) + { + tmp_order = (uint8_t) (tmp_order - 1); + p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE + + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE] = tmp_order; + if (1 == tmp_order) + { + p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = (uint8_t) i; + } + } + } + } +} /* End of function ble_abs_secure_data_update_bond_order() */ + +/*******************************************************************************************************************//** + * Check entry validation + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Read BD_ADDR is failed. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND invalid entry + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_is_valid_entry (flash_instance_t const * p_instance, int32_t entry) +{ + uint8_t bd_addr[BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE]; + uint8_t invalid_bd_addr[BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE]; + uint32_t start_addr; + + start_addr = BLE_ABS_SECURE_DATA_ADDR_REM_START + (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE; + + FSP_ERROR_RETURN(FSP_SUCCESS == + ble_abs_secure_data_flash_read(p_instance, + start_addr, + bd_addr, + BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE), + FSP_ERR_BLE_ABS_INVALID_OPERATION); + + memset(invalid_bd_addr, BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF, BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE); + FSP_ERROR_RETURN(0 != memcmp(bd_addr, invalid_bd_addr, BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE), + FSP_ERR_BLE_ABS_NOT_FOUND); + + return FSP_SUCCESS; +} /* End of function ble_abs_secure_data_is_valid_entry() */ + +/*******************************************************************************************************************//** + * Read Remote bonding information in DataFlash. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Memory allocation is failed. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND No security data is stored in DataFlash. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_read_bond_info (flash_instance_t const * p_instance, + uint8_t * p_out_bond_num, + uint8_t ** pp_sec_data, + st_ble_gap_bond_info_t * p_bond_info) +{ + fsp_err_t retval = FSP_SUCCESS; + int32_t i; + uint32_t start_addr; + uint8_t * p_bonds; + uint32_t magic_num; + + *pp_sec_data = malloc(BLE_ABS_SECURE_DATA_MAX_SIZE); + p_bonds = *pp_sec_data; + FSP_ERROR_RETURN(NULL != p_bonds, FSP_ERR_BLE_ABS_NOT_FOUND); + + ble_abs_secure_data_flash_read(p_instance, + (uint32_t) BLE_ABS_SECURE_DATA_BASE_ADDR, + p_bonds, + BLE_ABS_SECURE_DATA_MAX_SIZE); + + /** check magic number and bond number */ + *p_out_bond_num = 0; + memcpy((uint8_t *) &magic_num, p_bonds, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE); + if ((BLE_ABS_SECURE_DATA_MAGIC_NUMBER != magic_num) || + (BLE_ABS_SECURE_DATA_BOND_CHECK_FF == p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]) || + (0x00 == p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET])) + { + free(p_bonds); + retval = FSP_ERR_BLE_ABS_NOT_FOUND; + } + + FSP_ERROR_RETURN((retval != FSP_ERR_BLE_ABS_NOT_FOUND), FSP_ERR_BLE_ABS_NOT_FOUND); + + if (BLE_ABS_CFG_NUMBER_BONDING < p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]) + { + free(p_bonds); + retval = FSP_ERR_BLE_ABS_NOT_FOUND; + } + + FSP_ERROR_RETURN((retval != FSP_ERR_BLE_ABS_NOT_FOUND), FSP_ERR_BLE_ABS_NOT_FOUND); + + for (i = 0; i < p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]; i++) + { + start_addr = BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + (uint32_t) i * + BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE; + p_bond_info[i].p_addr = (st_ble_dev_addr_t *) (p_bonds + start_addr); + p_bond_info[i].p_auth_info = + (st_ble_gap_auth_info_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET); + p_bond_info[i].p_keys = + (st_ble_gap_key_ex_param_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET); + p_bond_info[i].p_keys->p_keys_info = + (st_ble_gap_key_dist_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET); + (*p_out_bond_num)++; + } + + return retval; +} /* End of function ble_abs_secure_data_read_bond_info() */ + +/*******************************************************************************************************************//** + * Release bonding information buffer. + **********************************************************************************************************************/ +static void ble_abs_secure_data_release_bond_info_buf (uint8_t * p_sec_data) +{ + free(p_sec_data); +} /* End of function ble_abs_secure_data_release_bond_info_buf() */ + +#else /* (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) */ + +/*******************************************************************************************************************//** + * Write Local device Identity Address, IRK and/or CSRK in DataFlash. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported in this configuration. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_writelocinfo (flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk) +{ + (void) p_instance; + (void) p_lc_id_addr; + (void) p_lc_irk; + (void) p_lc_csrk; + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Read Local device Identity Address and IRK and/or CSRK in DataFlash. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported in this configuration. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_readlocinfo (flash_instance_t const * p_instance, + ble_device_address_t * p_lc_id_addr, + uint8_t * p_lc_irk, + uint8_t * p_lc_csrk) +{ + (void) p_instance; + (void) p_lc_id_addr; + (void) p_lc_irk; + (void) p_lc_csrk; + + return FSP_ERR_UNSUPPORTED; +} + +static void ble_abs_secure_data_recvremkeys (ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys) +{ + (void) p_addr; + (void) p_keys; +} + +/*******************************************************************************************************************//** + * Write Remote Keys in DataFlash. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported in this configuration. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_writeremkeys (flash_instance_t const * p_instance, + ble_device_address_t * p_addr, + st_ble_gap_auth_info_t * p_keyinfo) +{ + (void) p_instance; + (void) p_addr; + (void) p_keyinfo; + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Set bonding information in DataFlash to Host Stack. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported in this configuration. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_secure_data_init (flash_instance_t const * p_instance) +{ + (void) p_instance; + + return FSP_ERR_UNSUPPORTED; +} + +#endif /* (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) */ + +/**************************************************************************************//** + * Read the value of the specified data flash + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT parameter is invalid. + *****************************************************************************************/ +static fsp_err_t ble_abs_secure_data_flash_read (flash_instance_t const * p_instance, + uint32_t addr, + uint8_t * buff, + uint16_t len) +{ + fsp_err_t err = FSP_SUCCESS; + uint8_t * p_address = (uint8_t *) addr; + flash_info_t info; + + /* Open driver */ + err = p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg); + + /* Check for a valid address. */ + if (FSP_SUCCESS != err) + { + err = p_instance->p_api->infoGet(p_instance->p_ctrl, &info); + + if (((addr) < info.data_flash.p_block_array->block_section_st_addr) || + ((addr + len) >= info.data_flash.p_block_array->block_section_end_addr)) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + } + + /* Directly read data flush*/ + while ((len--) && (FSP_SUCCESS == err)) + { + *buff++ = *p_address++; + } + + /* Close driver */ + p_instance->p_api->close(p_instance->p_ctrl); + + return err; +} + +/**************************************************************************************//** + * Write data flash and Read data that has already been written and overwrite the value. + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_INVALID_ARGUMENT parameter is invalid. + *****************************************************************************************/ +static fsp_err_t ble_abs_secure_data_flash_write (flash_instance_t const * p_instance, + uint32_t addr, + uint8_t * buff, + uint16_t len) +{ + fsp_err_t err = FSP_SUCCESS; + uint8_t * block_addr = (uint8_t *) (addr & ~BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK); + uint16_t offset = (uint16_t) (addr & BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK); + uint32_t i; + flash_info_t info; + uint8_t temporary_buffer[BLE_ABS_SECURE_DATA_BLOCK_SIZE]; + + /* Open driver */ + if (FSP_SUCCESS != err) + { + err = p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg); + } + + /* Check for a valid address. */ + if (FSP_SUCCESS != err) + { + err = p_instance->p_api->infoGet(p_instance->p_ctrl, &info); + + if (((addr) < info.data_flash.p_block_array->block_section_st_addr) || + ((addr + len) >= info.data_flash.p_block_array->block_section_end_addr)) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + } + + while (FSP_SUCCESS != err) + { + /* set write data */ + for (i = 0; i < BLE_ABS_SECURE_DATA_BLOCK_SIZE; i++) + { + if ((i >= offset) && (i < (offset + len))) + { + temporary_buffer[i] = *buff++; + } + else + { + temporary_buffer[i] = block_addr[i]; + } + } + + /* Erase data block */ + err = p_instance->p_api->erase(p_instance->p_ctrl, (uint32_t) block_addr, 1); + + /* Write data flash */ + if (FSP_SUCCESS != err) + { + err = p_instance->p_api->write(p_instance->p_ctrl, + (uint32_t) temporary_buffer, + (uint32_t) block_addr, + BLE_ABS_SECURE_DATA_BLOCK_SIZE); + } + } + + /* Close driver */ + p_instance->p_api->close(p_instance->p_ctrl); + + return err; +} + +uint8_t r_dflash_read (uint32_t addr, uint8_t * buff, uint16_t len) { + ble_abs_secure_data_flash_read(gp_instance_ctrl->p_cfg->p_flash_instance, addr, buff, len); + + return FSP_SUCCESS; +} + +uint8_t r_dflash_write (uint32_t addr, uint8_t * buff, uint16_t len) { + ble_abs_secure_data_flash_write(gp_instance_ctrl->p_cfg->p_flash_instance, addr, buff, len); + + return FSP_SUCCESS; +} + +/*** r_ble_sec_data functions added end ***/ + +static void ble_abs_timer_update_remaining_time_ms (ble_abs_instance_ctrl_t * const p_instance_ctrl, bool expired) +{ + uint32_t elapsed_time_ms = ble_abs_get_elapsed_time_ms(p_instance_ctrl->p_cfg->p_timer_instance, + expired, + p_instance_ctrl->current_timeout_ms, + &p_instance_ctrl->elapsed_timeout_ms); + + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + if (BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status) + { + p_instance_ctrl->timer[i].remaining_time_ms -= elapsed_time_ms; + } + } +} + +static uint32_t ble_abs_timer_alloc_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + if (p_instance_ctrl->timer[i].status == BLE_TIMER_STATUS_FREE) + { + p_instance_ctrl->timer[i].status = BLE_TIMER_STATUS_IDLE; + + return i; + } + } + + return BLE_TIMER_INVALID_HDL; +} + +static void ble_abs_timer_free_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl) +{ + p_instance_ctrl->timer[timer_hdl].status = BLE_TIMER_STATUS_FREE; + p_instance_ctrl->timer[timer_hdl].timer_hdl = BLE_TIMER_INVALID_HDL; + p_instance_ctrl->timer[timer_hdl].timeout_ms = 0; + p_instance_ctrl->timer[timer_hdl].type = BLE_TIMER_ONE_SHOT; + p_instance_ctrl->timer[timer_hdl].cb = NULL; +} + +static void ble_abs_timer_start_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + uint32_t next_hdl = BLE_TIMER_INVALID_HDL; + uint32_t shortest = BLE_ABS_TIMER_REMAIN_TIMESHORTEST; + + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + if ((BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status) && + (shortest > p_instance_ctrl->timer[i].remaining_time_ms)) + { + shortest = p_instance_ctrl->timer[i].remaining_time_ms; + next_hdl = i; + } + } + + if (BLE_TIMER_INVALID_HDL != next_hdl) + { + ble_abs_start_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance, + &p_instance_ctrl->current_timeout_ms, + &p_instance_ctrl->elapsed_timeout_ms, + p_instance_ctrl->timer[next_hdl].remaining_time_ms); + } +} + +static void ble_abs_timer_stop_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + ble_abs_stop_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance, + &p_instance_ctrl->current_timeout_ms, + &p_instance_ctrl->elapsed_timeout_ms); +} + +static void ble_abs_timer_add_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl) +{ + p_instance_ctrl->timer[timer_hdl].status = BLE_TIMER_STATUS_STARTED; + p_instance_ctrl->timer[timer_hdl].remaining_time_ms = p_instance_ctrl->timer[timer_hdl].timeout_ms; +} + +static void ble_abs_timer_remove_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl) +{ + p_instance_ctrl->timer[timer_hdl].status = BLE_TIMER_STATUS_IDLE; +} + +static void ble_abs_timer_event_cb (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + if (BLE_TIMER_STATUS_EXPIRED == p_instance_ctrl->timer[i].status) + { + p_instance_ctrl->timer[i].cb(i); + + if (BLE_TIMER_PERIODIC == p_instance_ctrl->timer[i].type) + { + ble_abs_timer_add_timer(p_instance_ctrl, i); + } + else + { + ble_abs_timer_remove_timer(p_instance_ctrl, i); + } + } + } + + ble_abs_timer_stop_timer(p_instance_ctrl); + ble_abs_timer_start_timer(p_instance_ctrl); +} + +void ble_abs_timer_process_timer_expire (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, true); + + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + if ((BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status) && + (0 == p_instance_ctrl->timer[i].remaining_time_ms)) + { + p_instance_ctrl->timer[i].status = BLE_TIMER_STATUS_EXPIRED; + ble_abs_timer_event_cb(p_instance_ctrl); + } + } + + ble_abs_timer_start_timer(p_instance_ctrl); +} + +static void ble_abs_timer_init (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + ble_abs_timer_free_timer(p_instance_ctrl, i); + } + + ble_abs_init_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance); +} + +static void ble_abs_timer_terminate (ble_abs_instance_ctrl_t * const p_instance_ctrl) +{ + for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++) + { + ble_abs_timer_free_timer(p_instance_ctrl, i); + } + + ble_abs_terminate_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance); +} + +/*******************************************************************************************************************//** + * Create timer for communication. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_NOT_FOUND Couldn't find a valid timer. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid parameter is given. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_timer_create (ble_abs_instance_ctrl_t * const p_instance_ctrl, + uint32_t * p_timer_hdl, + uint32_t timeout_ms, + uint8_t type, + ble_abs_timer_cb_t cb) +{ + uint32_t timer_hdl; + + FSP_ERROR_RETURN((NULL != p_timer_hdl) && (timeout_ms != 0) && (NULL != cb) && + ((type == BLE_TIMER_ONE_SHOT) || (type == BLE_TIMER_PERIODIC)), + FSP_ERR_INVALID_ARGUMENT); + + timer_hdl = ble_abs_timer_alloc_timer(p_instance_ctrl); + + FSP_ERROR_RETURN((timer_hdl != BLE_TIMER_INVALID_HDL), FSP_ERR_BLE_ABS_NOT_FOUND); + + *p_timer_hdl = timer_hdl; + + p_instance_ctrl->timer[timer_hdl].timeout_ms = timeout_ms; + p_instance_ctrl->timer[timer_hdl].type = type; + p_instance_ctrl->timer[timer_hdl].cb = cb; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Delete timer for communication. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Invalid operation for the selected timer. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid timer handle. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_timer_delete (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t * p_timer_hdl) +{ + FSP_ERROR_RETURN((NULL != p_timer_hdl), FSP_ERR_INVALID_ARGUMENT); + + uint32_t timer_hdl = *p_timer_hdl; + FSP_ERROR_RETURN((BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT > timer_hdl), FSP_ERR_BLE_ABS_INVALID_OPERATION); + + *p_timer_hdl = BLE_TIMER_INVALID_HDL; + + if (BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[timer_hdl].status) + { + ble_abs_timer_stop(p_instance_ctrl, timer_hdl); + } + + ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false); + ble_abs_timer_stop_timer(p_instance_ctrl); + ble_abs_timer_remove_timer(p_instance_ctrl, timer_hdl); + ble_abs_timer_free_timer(p_instance_ctrl, timer_hdl); + ble_abs_timer_start_timer(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Start timer for communication. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Invalid operation for the selected timer. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_timer_start (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl) +{ + FSP_ERROR_RETURN((timer_hdl < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT), FSP_ERR_BLE_ABS_INVALID_OPERATION); + + FSP_ERROR_RETURN((BLE_TIMER_STATUS_FREE != p_instance_ctrl->timer[timer_hdl].status) && + (BLE_TIMER_STATUS_EXPIRED != p_instance_ctrl->timer[timer_hdl].status), + FSP_ERR_BLE_ABS_INVALID_OPERATION); + + ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false); + ble_abs_timer_stop_timer(p_instance_ctrl); + ble_abs_timer_add_timer(p_instance_ctrl, timer_hdl); + ble_abs_timer_start_timer(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stop timer for communication. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION Invalid operation for the selected timer. + **********************************************************************************************************************/ +static fsp_err_t ble_abs_timer_stop (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl) +{ + FSP_ERROR_RETURN((timer_hdl < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT), FSP_ERR_BLE_ABS_INVALID_OPERATION); + + ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false); + ble_abs_timer_stop_timer(p_instance_ctrl); + ble_abs_timer_remove_timer(p_instance_ctrl, timer_hdl); + ble_abs_timer_start_timer(p_instance_ctrl); + + return FSP_SUCCESS; +} + +static void ble_abs_init_hw_timer (timer_instance_t const * p_instance) +{ + p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg); +} + +static void ble_abs_terminate_hw_timer (timer_instance_t const * p_instance) +{ + p_instance->p_api->stop(p_instance->p_ctrl); + p_instance->p_api->close(p_instance->p_ctrl); +} + +static void ble_abs_start_hw_timer (timer_instance_t const * p_instance, + uint32_t * current_timeout_ms, + uint32_t * elapsed_timeout_ms, + uint32_t timeout_ms) +{ + uint32_t timer_count; + timer_info_t timer_info; + + if (timeout_ms > BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS) + { + *current_timeout_ms = BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS; + } + else + { + *current_timeout_ms = timeout_ms; + } + + *elapsed_timeout_ms = 0; + + p_instance->p_api->infoGet(p_instance->p_ctrl, &timer_info); + + timer_count = *current_timeout_ms * (timer_info.clock_frequency / BLE_ABS_TIMER_METRIC_PREFIX); + p_instance->p_api->periodSet(p_instance->p_ctrl, timer_count); + p_instance->p_api->start(p_instance->p_ctrl); +} + +static void ble_abs_stop_hw_timer (timer_instance_t const * p_instance, + uint32_t * current_timeout_ms, + uint32_t * elapsed_timeout_ms) +{ + *current_timeout_ms = 0; + *elapsed_timeout_ms = 0; + p_instance->p_api->stop(p_instance->p_ctrl); +} + +void ble_abs_hw_timer_callback (timer_callback_args_t * callback_args) +{ + ble_abs_instance_t * p_instance = (ble_abs_instance_t *) callback_args->p_context; + ble_abs_timer_process_timer_expire(p_instance->p_ctrl); +} + +static uint32_t ble_abs_get_elapsed_time_ms (timer_instance_t const * p_instance, + bool expired, + const uint32_t current_timeout_ms, + uint32_t * elapsed_timeout_ms) +{ + uint32_t elapsed_time_from_prev_update_ms = 0; + uint32_t total_elapsed_timeout_ms; + + timer_status_t status; + timer_info_t info; + + p_instance->p_api->statusGet(p_instance->p_ctrl, &status); + p_instance->p_api->infoGet(p_instance->p_ctrl, &info); + + if (expired) + { + elapsed_time_from_prev_update_ms = current_timeout_ms - *elapsed_timeout_ms; + *elapsed_timeout_ms = current_timeout_ms; + } + else if (status.state == TIMER_STATE_COUNTING) + { + total_elapsed_timeout_ms = (status.counter / info.clock_frequency) / BLE_ABS_TIMER_METRIC_PREFIX; + elapsed_time_from_prev_update_ms = total_elapsed_timeout_ms - *elapsed_timeout_ms; + *elapsed_timeout_ms = total_elapsed_timeout_ms; + } + else if (0 == current_timeout_ms) + { + elapsed_time_from_prev_update_ms = 0; + } + else + { + } + + return elapsed_time_from_prev_update_ms; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg.txt b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg.txt new file mode 100644 index 0000000000..f678053f04 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg.txt @@ -0,0 +1,320 @@ +RA Configuration + Board "EK-RA4W1" + R7FA4W1AD2CNG + part_number: R7FA4W1AD2CNG + rom_size_bytes: 524288 + ram_size_bytes: 98304 + data_flash_size_bytes: 8192 + package_style: QFN + package_pins: 56 + + RA4W1 + series: 4 + + RA4W1 Family + OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled + OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles + OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128 + OFS0 register settings: Independent WDT: Window End Position: 0% (no window end position) + OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position) + OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled + OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby + OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode) + OFS0 register settings: WDT: Timeout Period: 16384 cycles + OFS0 register settings: WDT: Clock Frequency Division Ratio: 128 + OFS0 register settings: WDT: Window End Position: 0% (no window end position) + OFS0 register settings: WDT: Window Start Position: 100% (no window start position) + OFS0 register settings: WDT: Reset Interrupt Request: Reset + OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode + OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset + OFS1 register settings: Voltage Detection 0 Level: 1.90 V + OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset + Use Low Voltage Mode: Disable + MPU: Enable or disable PC Region 0: Disabled + MPU: PC0 Start: 0x00FFFFFC + MPU: PC0 End: 0x00FFFFFF + MPU: Enable or disable PC Region 1: Disabled + MPU: PC1 Start: 0x00FFFFFC + MPU: PC1 End: 0x00FFFFFF + MPU: Enable or disable Memory Region 0: Disabled + MPU: Memory Region 0 Start: 0x00FFFFFC + MPU: Memory Region 0 End: 0x00FFFFFF + MPU: Enable or disable Memory Region 1: Disabled + MPU: Memory Region 1 Start: 0x200FFFFC + MPU: Memory Region 1 End: 0x200FFFFF + MPU: Enable or disable Memory Region 2: Disabled + MPU: Memory Region 2 Start: 0x407FFFFC + MPU: Memory Region 2 End: 0x407FFFFF + MPU: Enable or disable Memory Region 3: Disabled + MPU: Memory Region 3 Start: 0x400DFFFC + MPU: Memory Region 3 End: 0x400DFFFF + + RA Common + Main stack size (bytes): 0x2000 + Heap size (bytes): 0x2000 + MCU Vcc (mV): 3300 + Parameter checking: Disabled + Assert Failures: Return FSP_ERR_ASSERTION + Error Log: No Error Log + ID Code Mode: Unlocked (Ignore ID) + ID Code (32 Hex Characters): FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + Soft Reset: Disabled + Main Oscillator Populated: Populated + PFS Protect: Enabled + Main Oscillator Wait Time: 32768 us + Main Oscillator Clock Source: Crystal or Resonator + Subclock Populated: Populated + Subclock Drive: Standard + Subclock Stabilization Time (ms): 1000 + + Clocks + XTAL 8000000Hz + HOCO 32MHz + PLL Div /2 + PLL Mul x12 + Clock Src: HOCO + ICLK Div /1 + PCLKA Div /1 + PCLKB Div /1 + PCLKC Div /1 + PCLKD Div /1 + BCLK Div /2 + BCK/2 + FCLK Div /2 + CLKOUT Disabled + CLKOUT Div /1 + UCLK Src: PLL + + Pin Configurations + RA4W1-EK.pincfg -> g_bsp_pin_cfg + ANT 30 RADIO0_ANT - - - - - - + AVCC0 35 ANALOG0_AVCC0 - - - - - - + AVDDRF 39 RADIO0_AVDDRF - - - - - - + AVSS0 36 ANALOG0_AVSS0 - - - - - - + FBIN 45 RADIO0_FBIN - - - - - - + LX 41 RADIO0_LX - - - - - - + P004 40 - - - Disabled - - "ADC0: AN04; ICU0: IRQ03; OPAMP2: AMPO" + P010 38 - - - Disabled - - "ADC0: AN05; CTSU0: TS30; ICU0: IRQ14; OPAMP2: AMP-" + P011 37 - - - Disabled - - "ADC0: AN06; CTSU0: TS31; ICU0: IRQ15; OPAMP2: AMP+" + P014 32 - - - Disabled - - "ADC0: AN09; DAC0: DA" + P015 31 - - - Disabled - - "ADC0: AN10; CTSU0: TS28; ICU0: IRQ07" + P100 27 SPI0_MISO Low None "Peripheral mode" CMOS None "ACMPLP0: CMPIN; AGT0: AGTIO; BUS_ASYNCH0: D00; GPT_POEG0: GTETRG; GPT5: GTIOCB; ICU0: IRQ02; IIC1: SCL; KINT0: KRM0; SCI0: RXD; SCI0: SCL; SCI1: SCK; SLCDC0: VL1; SPI0: MISO" + P101 26 SPI0_MOSI Low None "Peripheral mode" CMOS None "ACMPLP0: CMPREF; AGT0: AGTEE; BUS_ASYNCH0: D01; GPT_POEG1: GTETRG; GPT5: GTIOCA; ICU0: IRQ01; IIC1: SDA; KINT0: KRM1; SCI0: SDA; SCI0: TXD; SCI1: CTS; SLCDC0: VL2; SPI0: MOSI" + P102 25 SPI0_RSPCK Low - "Peripheral mode" CMOS None "ACMPLP1: CMPIN; ADC0: ADTRG; ADC0: AN20; AGT0: AGTO; BUS_ASYNCH0: D02; CAN0: CRX; GPT_OPS0: GTOWLO; GPT2: GTIOCB; KINT0: KRM2; SCI0: SCK; SLCDC0: VL3; SPI0: RSPCK" + P103 24 SPI0_SSL0 Low - "Peripheral mode" CMOS None "ACMPLP1: CMPREF; ADC0: AN19; BUS_ASYNCH0: D03; CAN0: CTX; GPT_OPS0: GTOWUP; GPT2: GTIOCA; KINT0: KRM3; SCI0: CTS; SLCDC0: VL4; SPI0: SSL0" + P104 23 - - - Disabled - - "BUS_ASYNCH0: D04; CTSU0: TS13; GPT_POEG1: GTETRG; GPT1: GTIOCB; ICU0: IRQ01; KINT0: KRM4; SCI0: RXD; SCI0: SCL; SLCDC0: COM0; SPI0: SSL1" + P105 22 - - - Disabled - - "BUS_ASYNCH0: D05; CTSU0: TS34; GPT_POEG0: GTETRG; GPT1: GTIOCA; ICU0: IRQ00; KINT0: KRM5; SLCDC0: COM1; SPI0: SSL2" + P106 21 GPIO Low - "Output mode (Initial High)" CMOS - "BUS_ASYNCH0: D06; GPT8: GTIOCB; KINT0: KRM6; SLCDC0: COM2; SPI0: SSL3" + P107 20 - - - Disabled - - "BUS_ASYNCH0: D07; GPT8: GTIOCA; KINT0: KRM7; SLCDC0: COM3" + P108 14 DEBUG0_TMS Low - "Peripheral mode" CMOS None "DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOCB; SCI9: CTS; SPI1: SSL0" + P109 15 DEBUG0_TDO Low - "Peripheral mode" CMOS None "CAN0: CTX; CGC0: CLKOUT; CTSU0: TS10; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOCA; SCI1: SCK; SCI9: SDA; SCI9: TXD; SLCDC0: SEG52; SPI1: MOSI" + P110 16 DEBUG0_TDI Low None "Peripheral mode" CMOS None "ACMP(0-1): VCOUT; CAN0: CRX; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOCB; ICU0: IRQ03; SCI9: RXD; SCI9: SCL; SLCDC0: SEG53; SPI1: MISO" + P111 17 - - - Disabled - - "BUS_ASYNCH0: A05; CTSU0: TS12; GPT3: GTIOCA; ICU0: IRQ04; SCI9: SCK; SLCDC0: CAPH; SPI1: RSPCK" + P200 12 - - - Disabled - - "ICU0: NMI" + P201 11 - - - Disabled - - "SYSTEM0: MD; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC" + P204 9 IIC0_SCL Medium - "Peripheral mode" CMOS None "AGT1: AGTIO; BUS_ASYNCH0: A18; CAC0: CACREF; CTSU0: TS00; GPT_OPS0: GTIW; GPT4: GTIOCB; IIC0: SCL; SCI4: SCK; SCI9: SCK; SDHI0: DAT4; SLCDC0: SEG23; SPI1: RSPCK; USB_FS0: OVRCURB" + P205 8 SCI4_TXD Low None "Peripheral mode" CMOS None "AGT1: AGTO; BUS_ASYNCH0: A16; CGC0: CLKOUT; CTSU0: TSCAP; GPT_OPS0: GTIV; GPT4: GTIOCA; ICU0: IRQ01; IIC1: SCL; SCI4: SDA; SCI4: TXD; SCI9: CTS; SDHI0: DAT3; SLCDC0: SEG20; SPI1: SSL0; USB_FS0: OVRCURA" + P206 7 SCI4_RXD Low None "Peripheral mode" CMOS None "BUS_ASYNCH0: WAIT; CTSU0: TS01; GPT_OPS0: GTIU; ICU0: IRQ00; IIC1: SDA; SCI4: RXD; SCI4: SCL; SDHI0: DAT2; SLCDC0: SEG12; SPI1: SSL1; USB_FS0: VBUSEN" + P212 53 - - - Disabled - - "AGT1: AGTEE; CGC0: EXTAL; GPT_POEG1: GTETRG; GPT0: GTIOCB; ICU0: IRQ03; SCI1: RXD; SCI1: SCL" + P213 52 - - - Disabled - - "CGC0: XTAL; GPT_POEG0: GTETRG; GPT0: GTIOCA; ICU0: IRQ02; SCI1: SDA; SCI1: TXD" + P214 50 - - - Disabled - - "CGC0: XCOUT" + P215 49 - - - Disabled - - "CGC0: XCIN" + P300 13 DEBUG0_TCK Low - "Peripheral mode" CMOS None "DEBUG0: SWCLK; DEBUG0: TCK; GPT_OPS0: GTOUUP; GPT0: GTIOCA; SPI1: SSL1" + P305 - - - - Disabled - - - + P402 44 IRQ0_IRQ04 - IRQ04 "IRQ mode" - - "AGT0: AGTIO; AGT1: AGTIO; CAN0: CRX; CTSU0: TS18; ICU0: IRQ04; RTC0: RTCIC0; SCI1: RXD; SCI1: SCL; SLCDC0: SEG06" + P404 46 GPIO Low - "Output mode (Initial High)" CMOS - "GPT3: GTIOCB; RTC0: RTCIC2; SSI0: SSIWS" + P407 1 IIC0_SDA Medium - "Peripheral mode" CMOS None "ADC0: ADTRG; AGT0: AGTIO; CTSU0: TS03; IIC0: SDA; RTC0: RTCOUT; SCI4: CTS; SLCDC0: SEG11; SPI1: SSL3" + P409 56 - - - Disabled - - "GPT_OPS0: GTOWUP; GPT5: GTIOCA; ICU0: IRQ06; SLCDC0: SEG09; USB_FS0: EXICEN" + P414 55 - - - Disabled - - "GPT0: GTIOCB; ICU0: IRQ09; SDHI0: WP; SPI0: SSL1" + P501 29 - - - Disabled - - "ACMPLP1: CMPIN; ADC0: AN17; AGT0: AGTOB; GPT_OPS0: GTIV; GPT2: GTIOCB; ICU0: IRQ11; QSPI0: QSSL; SLCDC0: SEG49; USB_FS0: OVRCURA" + P914 4 - - - Disabled - - "USB_FS0: DP" + P915 3 - - - Disabled - - "USB_FS0: DM" + Q1 34 RADIO0_Q1 - - - - - - + Q2 33 RADIO0_Q2 - - - - - - + RES# 10 SYSTEM0_RES - - - - - - + TEST0 28 RADIO0_TEST0 - - - - - - + VBATT 47 SYSTEM0_VBATT - - - - - - + VCC 18 SYSTEM0_VCC - - - - - - + VCC 54 SYSTEM0_VCC - - - - - - + VCCUSB 5 USBFS0_VCC - - - - - - + VCCUSBLDO 6 USBFS0_VCCLDO - - - - - - + VCL 48 SYSTEM0_VCL - - - - - - + VDDDIG 43 RADIO0_VDDDIG - - - - - - + VDDRF 42 RADIO0_VDDRF - - - - - - + VSS 19 SYSTEM0_VSS - - - - - - + VSS 51 SYSTEM0_VSS - - - - - - + VSSUSB 2 USBFS0_VSS - - - - - - + + User Events + + User Event Links + + Module "I/O Port Driver on r_ioport" + Parameter Checking: Default (BSP) + + Module "BLE Abstraction Driver on rm_ble_abs" + Debug Public Address: {0xFF,0xFF,0xFF,0x50,0x90,0x74} + Debug Random Address: {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} + Maximum number of connections: 7 + Maximum connection data length: 251 + Maximum advertising data length: 1650 + Maximum advertising set number: 4 + Maximum periodic sync set number.: 2 + Store Security Data: Disable + Data Flash Block for Security Data: 0 + Remote Device Bonding Number: 7 + Connection Event Start Notify: Disable notify + Connection Event Close Notify: Disable notify + Advertising Event Start Notify: Disable notify + Advertising Event Close Notify: Disable notify + Scanning Event Start Notify: Disable notify + Scanning Event Close Notify: Disable notify + Initiating Event Start Notify: Disable notify + Initiating Event Close Notify: Disable notify + RF Deep Sleep Start Notify: Disable notify + RF Deep Sleep Wakeup Notify: Disable notify + Bluetooth dedicated clock: 6 + DC-DC Converter: Disable DC-DC Converter + Slow Clock Source: Use RF_LOCO + MCU CLKOUT Port: P109 + MCU CLKOUT Frequency Output: MCU CLKOUT frequency 32.768kHz + Sleep Clock Accuracy(SCA): 250 + Transmission Power Maximum Value: max +4dBm + Transmission Power Default Value: High 0dBm(Transmission Power Maximum Value = +0dBm) / +4dBm(Transmission Power Maximum Value = +4dBm) + CLKOUT_RF Output: No output + RF_DEEP_SLEEP Transition: Enable + MCU Main Clock Frequency: 8000 + Code Flash(ROM) Device Data Block: 255 + Device Specific Data Flash Block: -1 + MTU Size Configured: 247 + Timer Slot Maximum Number: 10 + Parameter Checking: Default (BSP) + + Module "Timer Driver on r_agt" + Parameter Checking: Default (BSP) + Pin Output Support: Disabled + Pin Input Support: Disabled + + Module "Network Driver on r_ble_all" + Module "Flash Driver on r_flash_lp" + Parameter Checking: Default (BSP) + Code Flash Programming: Disabled + Data Flash Programming: Enabled + + Module "External IRQ Driver on r_icu" + Parameter Checking: Default (BSP) + + Module "Timer Driver on r_gpt" + Parameter Checking: Default (BSP) + Pin Output Support: Disabled + Write Protect Enable: Disabled + + HAL + Instance "g_ioport I/O Port Driver on r_ioport" + Name: g_ioport + Port 1 ELC Trigger Source: Disabled + Port 2 ELC Trigger Source: Disabled + Port 3 ELC Trigger Source: Disabled + Port 4 ELC Trigger Source: Disabled + + Instance "BLE Abstraction Driver on rm_ble_abs" + Name: g_ble_abs0 + Gap callback: gap_cb + Vendor specific callback: vs_cb + Pairing parameters: gs_abs_pairing_param + GATT server callback parameter: gs_abs_gatts_cb_param + GATT server callback number: 2 + GATT client callback parameter: gs_abs_gattc_cb_param + GATT client callback number: 2 + Interrupts: Callback provided when an ISR occurs: NULL + IO capabilities of local device.: BLE_GAP_IOCAP_NOINPUT_NOOUTPUT + MITM protection policy.: BLE_GAP_SEC_MITM_BEST_EFFORT + Determine whether to accept only Secure Connections or not.: BLE_GAP_SC_BEST_EFFORT + Type of keys to be distributed from local device.: BLE_GAP_KEY_DIST_ENCKEY + Type of keys which local device requests a remote device to distribute.: 0 + Maximum LTK size.: 16 + + Instance "Network Driver on r_ble_all" + + Instance "g_flash0 Flash Driver on r_flash_lp" + Name: g_flash0 + Data Flash Background Operation: Disabled + Callback: NULL + Flash Ready Interrupt Priority: Disabled + + Instance "g_external_irq0 External IRQ Driver on r_icu" + Name: g_external_irq0 + Channel: 8 + Trigger: Falling + Digital Filtering: Disabled + Digital Filtering Sample Clock (Only valid when Digital Filtering is Enabled): PCLK / 64 + Callback: r_rf_ble_interrupt + Pin Interrupt Priority: Priority 1 + + Instance "g_timer1 Timer Driver on r_gpt" + General: Name: g_timer1 + General: Channel: 1 + General: Mode: Periodic + General: Period: 10 + General: Period Unit: Milliseconds + Output: Duty Cycle Percent (only applicable in PWM mode): 50 + Output: Duty Cycle Range (only applicable in PWM mode): Shortest: 2 PCLK, Longest: (Period - 1) PCLK + Output: GTIOCA Output Enabled: False + Output: GTIOCA Stop Level: Pin Level Low + Output: GTIOCB Output Enabled: False + Output: GTIOCB Stop Level: Pin Level Low + Input: Count Up Source: + Input: Count Down Source: + Input: Start Source: + Input: Stop Source: + Input: Clear Source: + Input: Capture A Source: + Input: Capture B Source: + Input: Noise Filter A Sampling Clock Select: No Filter + Input: Noise Filter B Sampling Clock Select: No Filter + Interrupts: Callback: r_rf_host_timer_interrupt + Interrupts: Overflow/Crest Interrupt Priority: Priority 2 + Interrupts: Capture A Interrupt Priority: Disabled + Interrupts: Capture B Interrupt Priority: Disabled + Interrupts: Trough Interrupt Priority: Disabled + Extra Features: Extra Features: Disabled + Extra Features: Output Disable: POEG Link: POEG Channel 0 + Extra Features: Output Disable: Output Disable POEG Trigger: + Extra Features: ADC Trigger: Start Event Trigger (GPTE/GPTEH only): + Extra Features: Dead Time: Dead Time Count Up (Raw Counts): 0 + Extra Features: Dead Time: Dead Time Count Down (Raw Counts) (GPTE/GPTEH only): 0 + Extra Features: ADC Trigger (GPTE/GPTEH only): ADC A Compare Match (Raw Counts): 0 + Extra Features: ADC Trigger (GPTE/GPTEH only): ADC B Compare Match (Raw Counts): 0 + Extra Features: Interrupt Skipping (GPTE/GPTEH only): Interrupt to Count: None + Extra Features: Interrupt Skipping (GPTE/GPTEH only): Interrupt Skip Count: 0 + Extra Features: Interrupt Skipping (GPTE/GPTEH only): Skip ADC Events: None + Extra Features: Output Disable: GTIOCA Disable Setting: Disable Prohibited + Extra Features: Output Disable: GTIOCB Disable Setting: Disable Prohibited + + Instance "g_timer0 Timer Driver on r_agt" + General: Name: g_timer0 + General: Channel: 0 + General: Mode: Periodic + General: Period: 0x10000 + General: Period Unit: Raw Counts + Output: Duty Cycle Percent (only applicable in PWM mode): 50 + General: Count Source: LOCO + Output: AGTOA Output: Disabled + Output: AGTOB Output: Disabled + Output: AGTO Output: Disabled + Input: Measurement Mode: Measure Disabled + Input: AGTIO Filter: No Filter + Input: Enable Pin: Enable Pin Not Used + Input: Trigger Edge: Trigger Edge Rising + Interrupts: Callback: ble_abs_hw_timer_callback + Interrupts: Underflow Interrupt Priority: Priority 3 + + Instance "g_ble_sw_irq External IRQ Driver on r_icu" + Name: g_ble_sw_irq + Channel: 4 + Trigger: Falling + Digital Filtering: Disabled + Digital Filtering Sample Clock (Only valid when Digital Filtering is Enabled): PCLK / 64 + Callback: Callback_ble_sw_irq + Pin Interrupt Priority: Priority 4 + diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 0000000000..fd7b0ccb8f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/ra4w1_ek/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 0000000000..a779e60c13 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,65 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x2000) +#define BSP_CFG_HEAP_BYTES (0x2000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..444d32e560 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..70984c8ef6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4W1AD2CNG +#define BSP_ROM_SIZE_BYTES (524288) +#define BSP_RAM_SIZE_BYTES (98304) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_QFN +#define BSP_PACKAGE_PINS (56) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..2a6d96b63d --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,56 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA4W1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 +#define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 +#define BSP_HOCO_HZ (64000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (1 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 0000000000..d3ab559238 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h new file mode 100644 index 0000000000..ae35f40541 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_BLE_CFG_H_ +#define R_BLE_CFG_H_ +#define BLE_CFG_LIBRARY_TYPE 0 +#endif /* R_BLE_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h new file mode 100644 index 0000000000..4aa033e167 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (0) +#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h new file mode 100644 index 0000000000..0c7c1bc78a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) +#endif /* R_GPT_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 0000000000..5e77b6980f --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 0000000000..6b4353d238 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h new file mode 100644 index 0000000000..b43a884c06 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h @@ -0,0 +1,40 @@ +/* generated configuration header file - do not edit */ +#ifndef RM_BLE_ABS_CFG_H_ +#define RM_BLE_ABS_CFG_H_ +#define BLE_ABS_CFG_RF_DEBUG_PUBLIC_ADDRESS {0xFF,0xFF,0xFF,0x50,0x90,0x74} +#define BLE_ABS_CFG_RF_DEBUG_RANDOM_ADDRESS {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} +#define BLE_ABS_CFG_RF_CONNECTION_MAXIMUM (7) +#define BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM (251) +#define BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM (1650) +#define BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM (4) +#define BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM (2) +#define BLE_ABS_CFG_ENABLE_SECURE_DATA (0) +#define BLE_ABS_CFG_SECURE_DATA_DATAFLASH_BLOCK (0) +#define BLE_ABS_CFG_NUMBER_BONDING (7) +#define BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_START (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_CLOSE (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_START (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_CLOSE (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_START (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_CLOSE (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_START (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_CLOSE (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_START (0) +#define BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP (0) +#define BLE_ABS_CFG_RF_CLVAL (6) +#define BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE (0) +#define BLE_ABS_CFG_RF_EXT32K_EN (0) +#define BLE_ABS_CFG_RF_MCU_CLKOUT_PORT (0) +#define BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ (0) +#define BLE_ABS_CFG_RF_SCA (250) +#define BLE_ABS_CFG_RF_MAX_TX_POW (1) +#define BLE_ABS_CFG_RF_DEF_TX_POW (0) +#define BLE_ABS_CFG_RF_CLKOUT_EN (0) +#define BLE_ABS_CFG_RF_DEEP_SLEEP_EN (1) +#define BLE_ABS_CFG_MCU_MAIN_CLK_KHZ (8000) +#define BLE_ABS_CFG_DEV_DATA_CF_BLOCK (255) +#define BLE_ABS_CFG_DEV_DATA_DF_BLOCK (-1) +#define BLE_ABS_CFG_GATT_MTU_SIZE (247) +#define BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT (10) +#define BLE_ABS_CFG_PARAMETER_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* RM_BLE_ABS_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/RA4W1-EK.csv b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/RA4W1-EK.csv new file mode 100644 index 0000000000..46a0534438 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/RA4W1-EK.csv @@ -0,0 +1,257 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"ANT","30","RADIO0_ANT","","","","","","" +"AVCC0","35","ANALOG0_AVCC0","","","","","","" +"AVDDRF","39","RADIO0_AVDDRF","","","","","","" +"AVSS0","36","ANALOG0_AVSS0","","","","","","" +"FBIN","45","RADIO0_FBIN","","","","","","" +"LX","41","RADIO0_LX","","","","","","" +"P004","40","","","","Disabled","","","ADC0: AN04 +ICU0: IRQ03 +OPAMP2: AMPO" +"P010","38","","","","Disabled","","","ADC0: AN05 +CTSU0: TS30 +ICU0: IRQ14 +OPAMP2: AMP-" +"P011","37","","","","Disabled","","","ADC0: AN06 +CTSU0: TS31 +ICU0: IRQ15 +OPAMP2: AMP+" +"P014","32","","","","Disabled","","","ADC0: AN09 +DAC0: DA" +"P015","31","","","","Disabled","","","ADC0: AN10 +CTSU0: TS28 +ICU0: IRQ07" +"P100","27","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPIN +AGT0: AGTIO +BUS_ASYNCH0: D00 +GPT_POEG0: GTETRG +GPT5: GTIOCB +ICU0: IRQ02 +IIC1: SCL +KINT0: KRM0 +SCI0: RXD +SCI0: SCL +SCI1: SCK +SLCDC0: VL1 +SPI0: MISO" +"P101","26","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPREF +AGT0: AGTEE +BUS_ASYNCH0: D01 +GPT_POEG1: GTETRG +GPT5: GTIOCA +ICU0: IRQ01 +IIC1: SDA +KINT0: KRM1 +SCI0: SDA +SCI0: TXD +SCI1: CTS +SLCDC0: VL2 +SPI0: MOSI" +"P102","25","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPIN +ADC0: ADTRG +ADC0: AN20 +AGT0: AGTO +BUS_ASYNCH0: D02 +CAN0: CRX +GPT_OPS0: GTOWLO +GPT2: GTIOCB +KINT0: KRM2 +SCI0: SCK +SLCDC0: VL3 +SPI0: RSPCK" +"P103","24","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPREF +ADC0: AN19 +BUS_ASYNCH0: D03 +CAN0: CTX +GPT_OPS0: GTOWUP +GPT2: GTIOCA +KINT0: KRM3 +SCI0: CTS +SLCDC0: VL4 +SPI0: SSL0" +"P104","23","","","","Disabled","","","BUS_ASYNCH0: D04 +CTSU0: TS13 +GPT_POEG1: GTETRG +GPT1: GTIOCB +ICU0: IRQ01 +KINT0: KRM4 +SCI0: RXD +SCI0: SCL +SLCDC0: COM0 +SPI0: SSL1" +"P105","22","","","","Disabled","","","BUS_ASYNCH0: D05 +CTSU0: TS34 +GPT_POEG0: GTETRG +GPT1: GTIOCA +ICU0: IRQ00 +KINT0: KRM5 +SLCDC0: COM1 +SPI0: SSL2" +"P106","21","","","","Disabled","","","BUS_ASYNCH0: D06 +GPT8: GTIOCB +KINT0: KRM6 +SLCDC0: COM2 +SPI0: SSL3" +"P107","20","","","","Disabled","","","BUS_ASYNCH0: D07 +GPT8: GTIOCA +KINT0: KRM7 +SLCDC0: COM3" +"P108","14","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO +DEBUG0: TMS +GPT_OPS0: GTOULO +GPT0: GTIOCB +SCI9: CTS +SPI1: SSL0" +"P109","15","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX +CGC0: CLKOUT +CTSU0: TS10 +DEBUG0: TDO +DEBUG0: TRACESWO +GPT_OPS0: GTOVUP +GPT1: GTIOCA +SCI1: SCK +SCI9: SDA +SCI9: TXD +SLCDC0: SEG52 +SPI1: MOSI" +"P110","16","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","ACMP(0-1): VCOUT +CAN0: CRX +DEBUG0: TDI +GPT_OPS0: GTOVLO +GPT1: GTIOCB +ICU0: IRQ03 +SCI9: RXD +SCI9: SCL +SLCDC0: SEG53 +SPI1: MISO" +"P111","17","","","","Disabled","","","BUS_ASYNCH0: A05 +CTSU0: TS12 +GPT3: GTIOCA +ICU0: IRQ04 +SCI9: SCK +SLCDC0: CAPH +SPI1: RSPCK" +"P200","12","","","","Disabled","","","ICU0: NMI" +"P201","11","","","","Disabled","","","SYSTEM0: MD +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC" +"P204","9","IIC0_SCL","Medium","","Peripheral mode","CMOS","None","AGT1: AGTIO +BUS_ASYNCH0: A18 +CAC0: CACREF +CTSU0: TS00 +GPT_OPS0: GTIW +GPT4: GTIOCB +IIC0: SCL +SCI4: SCK +SCI9: SCK +SDHI0: DAT4 +SLCDC0: SEG23 +SPI1: RSPCK +USB_FS0: OVRCURB" +"P205","8","SCI4_TXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO +BUS_ASYNCH0: A16 +CGC0: CLKOUT +CTSU0: TSCAP +GPT_OPS0: GTIV +GPT4: GTIOCA +ICU0: IRQ01 +IIC1: SCL +SCI4: SDA +SCI4: TXD +SCI9: CTS +SDHI0: DAT3 +SLCDC0: SEG20 +SPI1: SSL0 +USB_FS0: OVRCURA" +"P206","7","SCI4_RXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: WAIT +CTSU0: TS01 +GPT_OPS0: GTIU +ICU0: IRQ00 +IIC1: SDA +SCI4: RXD +SCI4: SCL +SDHI0: DAT2 +SLCDC0: SEG12 +SPI1: SSL1 +USB_FS0: VBUSEN" +"P212","53","","","","Disabled","","","AGT1: AGTEE +CGC0: EXTAL +GPT_POEG1: GTETRG +GPT0: GTIOCB +ICU0: IRQ03 +SCI1: RXD +SCI1: SCL" +"P213","52","","","","Disabled","","","CGC0: XTAL +GPT_POEG0: GTETRG +GPT0: GTIOCA +ICU0: IRQ02 +SCI1: SDA +SCI1: TXD" +"P214","50","","","","Disabled","","","CGC0: XCOUT" +"P215","49","","","","Disabled","","","CGC0: XCIN" +"P300","13","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK +DEBUG0: TCK +GPT_OPS0: GTOUUP +GPT0: GTIOCA +SPI1: SSL1" +"P305","","","","","Disabled","","","" +"P402","44","IRQ0_IRQ04","","IRQ04","IRQ mode","","","AGT0: AGTIO +AGT1: AGTIO +CAN0: CRX +CTSU0: TS18 +ICU0: IRQ04 +RTC0: RTCIC0 +SCI1: RXD +SCI1: SCL +SLCDC0: SEG06" +"P404","46","GPIO","Low","","Output mode (Initial High)","CMOS","","GPT3: GTIOCB +RTC0: RTCIC2 +SSI0: SSIWS" +"P407","1","IIC0_SDA","Medium","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +IIC0: SDA +RTC0: RTCOUT +SCI4: CTS +SLCDC0: SEG11 +SPI1: SSL3" +"P409","56","","","","Disabled","","","GPT_OPS0: GTOWUP +GPT5: GTIOCA +ICU0: IRQ06 +SLCDC0: SEG09 +USB_FS0: EXICEN" +"P414","55","","","","Disabled","","","GPT0: GTIOCB +ICU0: IRQ09 +SDHI0: WP +SPI0: SSL1" +"P501","29","","","","Disabled","","","ACMPLP1: CMPIN +ADC0: AN17 +AGT0: AGTOB +GPT_OPS0: GTIV +GPT2: GTIOCB +ICU0: IRQ11 +QSPI0: QSSL +SLCDC0: SEG49 +USB_FS0: OVRCURA" +"P914","4","","","","Disabled","","","USB_FS0: DP" +"P915","3","","","","Disabled","","","USB_FS0: DM" +"Q1","34","RADIO0_Q1","","","","","","" +"Q2","33","RADIO0_Q2","","","","","","" +"RES#","10","SYSTEM0_RES","","","","","","" +"TEST0","28","RADIO0_TEST0","","","","","","" +"VBATT","47","SYSTEM0_VBATT","","","","","","" +"VCC","18","SYSTEM0_VCC","","","","","","" +"VCC","54","SYSTEM0_VCC","","","","","","" +"VCCUSB","5","USBFS0_VCC","","","","","","" +"VCCUSBLDO","6","USBFS0_VCCLDO","","","","","","" +"VCL","48","SYSTEM0_VCL","","","","","","" +"VDDDIG","43","RADIO0_VDDDIG","","","","","","" +"VDDRF","42","RADIO0_VDDRF","","","","","","" +"VSS","19","SYSTEM0_VSS","","","","","","" +"VSS","51","SYSTEM0_VSS","","","","","","" +"VSSUSB","2","USBFS0_VSS","","","","","","" diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_clock_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_clock_cfg.h new file mode 100644 index 0000000000..870acfa350 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_XTAL_HZ (8000000) /* XTAL 8000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 32MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_12_0) /* PLL Mul x12 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKB Div /1 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLKOUT_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_pin_cfg.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_pin_cfg.h new file mode 100644 index 0000000000..497c92d06e --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4W1-EK.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.c new file mode 100644 index 0000000000..5a5bbae8b5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.c @@ -0,0 +1,8 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) +{ +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.h new file mode 100644 index 0000000000..e2eb70836b --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.c new file mode 100644 index 0000000000..b2cbd8c29d --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.c @@ -0,0 +1,493 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +icu_instance_ctrl_t g_ble_sw_irq_ctrl; +const external_irq_cfg_t g_ble_sw_irq_cfg = +{ .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_FALLING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = Callback_ble_sw_irq, + .p_context = NULL, + .p_extend = NULL, + .ipl = (4), +#if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, +#else + .irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const external_irq_instance_t g_ble_sw_irq = +{ .p_ctrl = &g_ble_sw_irq_ctrl, .p_cfg = &g_ble_sw_irq_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_LOCO, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 2 seconds. Actual duty: 50%. */.period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t) 0, .channel = 0, .p_callback = + ble_abs_hw_timer_callback, + /** If NULL then do not add & */ +#if defined(g_ble_abs0) + .p_context = g_ble_abs0, +#else + .p_context = &g_ble_abs0, +#endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (3), +#if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +gpt_instance_ctrl_t g_timer1_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer1_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = GPT_OUTPUT_DISABLE_NONE, + .adc_trigger = GPT_ADC_TRIGGER_NONE, + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer1_extend = + { .gtioca = + { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, + .gtiocb = + { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, + .shortest_pwm_signal = GPT_SHORTEST_LEVEL_OFF, .start_source = GPT_SOURCE_NONE, .stop_source = GPT_SOURCE_NONE, .clear_source = + GPT_SOURCE_NONE, + .count_up_source = GPT_SOURCE_NONE, .count_down_source = GPT_SOURCE_NONE, .capture_a_source = GPT_SOURCE_NONE, .capture_b_source = + GPT_SOURCE_NONE, + .capture_a_ipl = (BSP_IRQ_DISABLED), .capture_b_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer1_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif + }; +const timer_cfg_t g_timer1_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.01 seconds. Actual duty: 50%. */.period_counts = (uint32_t) 0x4e200, + .duty_cycle_counts = 0x27100, .source_div = (timer_source_div_t) 0, .channel = 1, .p_callback = + r_rf_host_timer_interrupt, + .p_context = NULL, .p_extend = &g_timer1_extend, .cycle_end_ipl = (2), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const timer_instance_t g_timer1 = +{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_gpt }; +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_FALLING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = r_rf_ble_interrupt, + .p_context = NULL, + .p_extend = NULL, + .ipl = (1), +#if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, +#else + .irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +flash_lp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, +#else + .irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; +external_irq_instance_t const *g_ble_external_irq = &g_external_irq0; +flash_instance_t const *g_ble_flash = &g_flash0; + +#ifndef ENABLE_HCI_MODE +timer_instance_t const *g_ble_pl_timer = &g_timer1; +#endif +static ble_abs_pairing_parameter_t gs_abs_pairing_param = +{ .io_capabilitie_local_device = BLE_GAP_IOCAP_NOINPUT_NOOUTPUT, + .mitm_protection_policy = BLE_GAP_SEC_MITM_BEST_EFFORT, + .secure_connection_only = BLE_GAP_SC_BEST_EFFORT, + .local_key_distribute = BLE_GAP_KEY_DIST_ENCKEY, + .remote_key_distribute = 0, + .maximum_key_size = 16, }; + +ble_abs_instance_ctrl_t g_ble_abs0_ctrl; + +const ble_abs_cfg_t g_ble_abs0_cfg = +{ .gap_callback = gap_cb, + .vendor_specific_callback = vs_cb, + .p_pairing_parameter = &gs_abs_pairing_param, + .p_gatt_server_callback_list = gs_abs_gatts_cb_param, + .gatt_server_callback_list_number = 2, + .p_gatt_client_callback_list = gs_abs_gattc_cb_param, + .gatt_client_callback_list_number = 2, + .p_flash_instance = &g_flash0, + .p_timer_instance = &g_timer0, + .p_callback = NULL, + .p_context = NULL, + .p_extend = NULL, }; + +/* Instance structure to use this module. */ +const ble_abs_instance_t g_ble_abs0 = +{ .p_ctrl = &g_ble_abs0_ctrl, .p_cfg = &g_ble_abs0_cfg, .p_api = &g_ble_abs_on_ble }; + +const st_ble_rf_notify_t g_ble_rf_notify = +{ .enable = BLE_EVENT_NOTIFY_ENABLE_VAL, + +#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_START_MASK) != 0) + .start_cb = r_ble_rf_notify_event_start, +#endif /* ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_START_MASK) != 0) */ +#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_CLOSE_MASK) != 0) + .close_cb = r_ble_rf_notify_event_close, +#endif +#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_DS_MASK) != 0) + .dsleep_cb = r_ble_rf_notify_deep_sleep, +#endif + }; + +const uint8_t g_ble_dbg_pub_addr[6] = BLE_ABS_CFG_RF_DEBUG_PUBLIC_ADDRESS; +const uint8_t g_ble_dbg_rand_addr[6] = BLE_ABS_CFG_RF_DEBUG_RANDOM_ADDRESS; + +void ble_host_conn_config(uint32_t **pp_host_conn_config_table); + +/****************************/ +/*** Memory customization ***/ +/****************************/ +#if (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM <= 7) +const uint16_t g_ble_conn_max = BLE_ABS_CFG_RF_CONNECTION_MAXIMUM; +#endif + +#if (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM >= 27) && (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM <= 251) +const uint16_t g_ble_conn_data_max = BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM; +#endif + +#if (BLE_CFG_LIBRARY_TYPE == 0) +#if (BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM >= 31) && (BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM <= 1650) +const uint16_t g_ble_adv_data_max = BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM; +#endif + +#if (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM <= 4) +const uint16_t g_ble_adv_set_max = BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM; +#endif + +#if (BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM <= 2) +const uint16_t g_ble_sync_set_max = BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM; +#endif +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + +/******************************************/ +/**** LL management data area (2bytes) ****/ +/******************************************/ +#if (BLE_CFG_LIBRARY_TYPE != 0) +#define BLE_CNTL_DATA_MIN (392) +#define BLE_CNTL_DATA_CONN (65) +#define BLE_CNTL_DATA_ADV (0) +#define BLE_CNTL_DATA_SYNC (0) +#else /* (BLE_CFG_LIBRARY_TYPE != 0) */ +#define BLE_CNTL_DATA_MIN (279) +#define BLE_CNTL_DATA_CONN (65) +#define BLE_CNTL_DATA_ADV (78) +#define BLE_CNTL_DATA_SYNC (33) +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ +#define BLE_CNTL_DATA_MAX \ +( \ + (BLE_CNTL_DATA_MIN) + \ + (BLE_CNTL_DATA_CONN * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) + \ + (BLE_CNTL_DATA_ADV * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) + \ + (BLE_CNTL_DATA_SYNC * BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM) +\ + (0) \ +) + +/******************************************/ +/**** BLE stack event heap area (1byte)****/ +/******************************************/ +#ifdef ENABLE_HCI_MODE +#define BLE_HOST_HEAP_MIN (0) +#else /* ENABLE_HCI_MODE */ +#define BLE_HOST_HEAP_MIN (3032) +#endif /* ENABLE_HCI_MODE */ +#if (BLE_CFG_LIBRARY_TYPE != 0) +#define BLE_CNTL_HEAP_MIN (88) +#define BLE_CNTL_HEAP_EVENT (720) +#else /* (BLE_CFG_LIBRARY_TYPE != 0) */ +#define BLE_CNTL_HEAP_MIN (280) +#define BLE_CNTL_HEAP_EVENT (3784) +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ +#define BLE_CNTL_HEAP_CONN (388) +#define _ALIGN_4BYTE(base) ((((base)+3)>>2)<<2) +#define BLE_CNTL_HEAP_TX_DATA (_ALIGN_4BYTE(BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+4)+20) +#define BLE_CNTL_HEAP_RX_DATA (_ALIGN_4BYTE(BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+8)+4) +#define BLE_CNTL_HEAP_TX2_DATA (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+8) +#define BLE_CNTL_TXRX_MAX (4) + +#if (BLE_CFG_LIBRARY_TYPE != 0) +#define BLE_CNTL_ADV_DATA_MAX (0) +#else /* (BLE_CFG_LIBRARY_TYPE != 0) */ +#define BLE_ADV_DATA_BLOCKS_LIMIT (36) +#define BLE_ADV_DATA_BLOCKS ((((BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM + 251)/252) * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) * 2) +#if (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT) +#define BLE_CNTL_ADV_DATA_MAX (BLE_ADV_DATA_BLOCKS_LIMIT * 256) +#else /* (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT) */ +#define BLE_CNTL_ADV_DATA_MAX (BLE_ADV_DATA_BLOCKS * 256) +#endif /* (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT) */ +#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */ + +#define BLE_CNTL_HEAP_MAX \ +( \ + (BLE_CNTL_HEAP_MIN) + \ + (BLE_HOST_HEAP_MIN) + \ + (BLE_CNTL_HEAP_EVENT) + \ + (BLE_CNTL_HEAP_CONN * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) + \ + (BLE_CNTL_HEAP_TX_DATA * BLE_CNTL_TXRX_MAX) + \ + (BLE_CNTL_HEAP_RX_DATA * BLE_CNTL_TXRX_MAX) + \ + (BLE_CNTL_ADV_DATA_MAX) + \ + (0) \ +) + +/******************************************/ +/**** LL connection entry area (1byte) ****/ +/******************************************/ +#if (BLE_CFG_LIBRARY_TYPE == 1) +#define BLE_CNTL_CONN_ENT (328) +#elif (BLE_CFG_LIBRARY_TYPE == 2) +#define BLE_CNTL_CONN_ENT (316) +#else /* (BLE_CFG_LIBRARY_TYPE == x) */ +#define BLE_CNTL_CONN_ENT (336) +#endif /* (BLE_CFG_LIBRARY_TYPE == x) */ +#define BLE_CNTL_CONN_ENT_MAX \ +( \ + (BLE_CNTL_CONN_ENT * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) + \ + (0) \ +) + +/******************************************/ +/**** LL Advertising set area (1byte) ****/ +/******************************************/ +#define BLE_CNTL_ADV_SET (152) +#define BLE_CNTL_ADV_SET_MAX \ +( \ + (BLE_CNTL_ADV_SET * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) + \ + (0) \ +) + +uint16_t g_ble_cntl_data[BLE_CNTL_DATA_MAX]; +uint32_t g_ble_cntl_heap[(BLE_CNTL_HEAP_MAX + 3) / 4]; +uint32_t g_ble_cntl_heap2[(BLE_CNTL_HEAP_TX2_DATA + 3) / 4]; +uint32_t g_ble_cntl_conn_ent[(BLE_CNTL_CONN_ENT_MAX + 3) / 4]; +#if (BLE_CFG_LIBRARY_TYPE == 0) +uint32_t g_ble_cntl_adv_set[(BLE_CNTL_ADV_SET_MAX + 3) / 4]; +const uint16_t g_ble_adv_block = (uint16_t) (BLE_CNTL_ADV_DATA_MAX / 256); +#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */ + +#ifdef NO_USE_BSP +const uint16_t g_ble_main_clk_khz = (uint16_t)BLE_ABS_CFG_MCU_MAIN_CLK_KHZ; +const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = NULL; +#else /* NO_USE_BSP */ + +#include "bsp_cfg.h" +#if (BSP_CFG_CLKOUT_RF_MAIN == 1) && (BSP_CFG_XTAL_HZ == 4000000) && (BLE_ABS_CFG_RF_CLKOUT_EN == 5) +extern void R_BSP_ConfigClockSetting(void); +const uint16_t g_ble_main_clk_khz = (uint16_t)(BSP_CFG_XTAL_HZ/1000); +const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = R_BSP_ConfigClockSetting; +#elif (BSP_CFG_CLKOUT_RF_MAIN == 0) +const uint16_t g_ble_main_clk_khz = (uint16_t) BLE_ABS_CFG_MCU_MAIN_CLK_KHZ; +const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = NULL; + +#endif /* (BSP_CFG_CLKOUT_RF_MAIN == 1) && (BSP_CFG_XTAL_HZ == 4000000) && (BLE_ABS_CFG_RF_CLKOUT_EN == 5) */ +#endif /* NO_USE_BSP */ + +#if (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255) +const uint32_t g_ble_dev_data_cf_addr = BLE_ABS_CFG_DEV_DATA_CF_BLOCK; +#else /* (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255) */ +const uint32_t g_ble_dev_data_cf_addr = 0U; +#endif /* (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255) */ + +#if (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7) +const uint32_t g_ble_dev_data_df_addr = BLE_ABS_CFG_DEV_DATA_DF_BLOCK; +#else /* (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7) */ +const uint32_t g_ble_dev_data_df_addr = 0U; +#endif /* (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7) */ + +const uint8_t g_ble_rf_config[] = +{ +/***************************************/ +/**** CLVAL setting ****/ +/***************************************/ +#if (BLE_ABS_CFG_RF_CLVAL >= 0) && (BLE_ABS_CFG_RF_CLVAL <= 15) + (BLE_ABS_CFG_RF_CLVAL << 0) | +#endif /* BLE_ABS_CFG_RF_CLVAL */ + 0x00, /* base value */ + + /***************************************/ + /**** RF Slow Clock setting ****/ + /***************************************/ +#if (BLE_ABS_CFG_RF_EXT32K_EN >= 0) && (BLE_ABS_CFG_RF_EXT32K_EN <= 1) + /**** External 32kHz setting ****/ + (BLE_ABS_CFG_RF_EXT32K_EN << 0) | +#endif /* BLE_ABS_CFG_RF_EXT32K_EN */ + +#if (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ >= 0) && (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ <= 1) + /**** MCU CLKOUT setting ****/ + (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ << 1) | +#endif /* BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ */ + +#if (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT >= 0) && (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT <= 1) + /**** RF_LOCO setting ****/ + (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT << 2) | +#endif /* BLE_RF_CONF_RF_LOCO */ + + /**** Sleep Clock Accuracy (SCA) setting ****/ +#if (BLE_ABS_CFG_RF_SCA>=251) && (BLE_ABS_CFG_RF_SCA<=500) + (0x00 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=151) && (BLE_ABS_CFG_RF_SCA<=250) + (0x01 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=101) && (BLE_ABS_CFG_RF_SCA<=150) + (0x02 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=76 ) && (BLE_ABS_CFG_RF_SCA<=100) + (0x03 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=51 ) && (BLE_ABS_CFG_RF_SCA<=75 ) + (0x04 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=31 ) && (BLE_ABS_CFG_RF_SCA<=50 ) + (0x05 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=21 ) && (BLE_ABS_CFG_RF_SCA<=30 ) + (0x06 << 4) | +#elif (BLE_ABS_CFG_RF_SCA>=0 ) && (BLE_ABS_CFG_RF_SCA<=20 ) + (0x07 << 4) | +#endif /* BLE_ABS_CFG_RF_SCA */ + 0x00, /* base value */ + + /***************************************/ + /**** Tx Power setting ****/ + /***************************************/ +#if (BLE_ABS_CFG_RF_MAX_TX_POW >= 0) && (BLE_ABS_CFG_RF_MAX_TX_POW <= 2) + /**** Defalut Tx Power Setting ****/ + (BLE_ABS_CFG_RF_MAX_TX_POW << 0) | +#endif /* BLE_ABS_CFG_RF_MAX_TX_POW */ + 0x00, /* base value */ + + /***************************************/ + /**** RF option setting ****/ + /***************************************/ +#if (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE >= 0) && (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE <= 1 ) + + /**** DC-DC converter setting ****/ + (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE << 0) | + +#endif /* BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE */ +#if (BLE_ABS_CFG_RF_DEF_TX_POW >= 0) && (BLE_ABS_CFG_RF_DEF_TX_POW <= 1) + /**** Max Tx Power Setting ****/ + (BLE_ABS_CFG_RF_DEF_TX_POW << 1) | +#endif /* BLE_ABS_CFG_RF_DEF_TX_POW */ +#if (BLE_ABS_CFG_RF_CLKOUT_EN >= 0) && (BLE_ABS_CFG_RF_CLKOUT_EN <= 7) + /**** RF clock output settng ****/ + (BLE_ABS_CFG_RF_CLKOUT_EN << 4) | +#endif /* BLE_ABS_CFG_RF_CLKOUT_EN */ + + 0x00 /* base value */ +}; + +/***************************************/ +/**** Host Stack settings ****/ +/***************************************/ +#ifndef ENABLE_HCI_MODE +#define BLE_HOST_L2_SIG_TBL_LEN 24 +#define BLE_HOST_L2_CH_PARAM_TBL_LEN 2 +#define BLE_HOST_HCI_REM_TBL_LEN 6 +#define BLE_HOST_SMP_CONFIG_LEN 108 +#define BLE_HOST_GAP_CONN_TBL_LEN 12 +#define BLE_HOST_DEV_Q_TBL_LEN 14 +#define BLE_HOST_ATT_CONN_TBL_LEN 16 +#define BLE_HOST_GATTS_CNF_TBL_LEN 2 + +uint32_t g_ble_host_dev_q_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_DEV_Q_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_hci_rem_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_HCI_REM_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_l2_sig_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_L2_SIG_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_l2_ch_param_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_L2_CH_PARAM_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_smp_config_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_SMP_CONFIG_LEN + 3) / 4]; +uint32_t g_ble_host_att_conn_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_ATT_CONN_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_gap_conn_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_GAP_CONN_TBL_LEN + 3) / 4]; +uint32_t g_ble_host_gatts_cnf_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_GATTS_CNF_TBL_LEN + 3) / 4]; + +const uint32_t g_p_ble_host_config_tbls[] = +{ (uint32_t) g_ble_host_dev_q_tbl, + (uint32_t) g_ble_host_hci_rem_tbl, + (uint32_t) g_ble_host_l2_sig_tbl, + (uint32_t) g_ble_host_l2_ch_param_tbl, + (uint32_t) g_ble_host_smp_config_tbl, + (uint32_t) g_ble_host_att_conn_tbl, + (uint32_t) g_ble_host_gap_conn_tbl, + (uint32_t) g_ble_host_gatts_cnf_tbl }; + +void ble_host_conn_config(uint32_t **pp_host_conn_config_table) +{ + *pp_host_conn_config_table = (uint32_t *) g_p_ble_host_config_tbls; +} +#endif /* !ENABLE_HCI_MODE */ + +/***************************************/ +/**** Data Flash Usage ****/ +/***************************************/ + +#if (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) || \ + ( (BLE_ABS_CFG_EN_SEC_DATA != 0) && (BLE_ABS_CFG_SECD_DATA_DF_BLOCK >= 0) ) +uint32_t g_ble_flash_enable = 1; +#else +uint32_t g_ble_flash_enable = 0; +#endif +void g_hal_init(void) +{ + g_common_init (); +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.h new file mode 100644 index 0000000000..f1f15e512a --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/hal_data.h @@ -0,0 +1,108 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_flash_lp.h" +#include "r_flash_api.h" + +#include "rm_ble_abs.h" +#include "rm_ble_abs_api.h" +FSP_HEADER +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_ble_sw_irq; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_ble_sw_irq_ctrl; +extern const external_irq_cfg_t g_ble_sw_irq_cfg; + +#ifndef Callback_ble_sw_irq +void Callback_ble_sw_irq(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef ble_abs_hw_timer_callback +void ble_abs_hw_timer_callback(timer_callback_args_t *p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer1; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef r_rf_host_timer_interrupt +void r_rf_host_timer_interrupt(timer_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef r_rf_ble_interrupt +void r_rf_ble_interrupt(external_irq_callback_args_t *p_args); +#endif +/* Flash on Flash LP Instance. */ +extern const flash_instance_t g_flash0; + +/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_lp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif + +void r_ble_rf_notify_event_start(uint32_t param); +void r_ble_rf_notify_event_close(uint32_t param); +void r_ble_rf_notify_deep_sleep(uint32_t param); + +/** BLE_ABS on BLE Instance. */ +extern const ble_abs_instance_t g_ble_abs0; + +/** Access the BLE_ABS instance using these structures when calling API functions directly (::p_api is not used). */ +extern ble_abs_instance_ctrl_t g_ble_abs0_ctrl; +extern const ble_abs_cfg_t g_ble_abs0_cfg; + +/** Callback used by ble_abs Instance. */ +#ifndef gap_cb +void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data); +#endif + +#ifndef vs_cb +void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data); +#endif + +#ifndef gs_abs_gatts_cb_param +extern ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[]; +#else +ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[]; +#endif + +#ifndef gs_abs_gattc_cb_param +extern ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[]; +#else +ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[]; +#endif + +#ifndef NULL +void NULL(ble_abs_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/main.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/main.c new file mode 100644 index 0000000000..6f1f9608fa --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/main.c @@ -0,0 +1,7 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) +{ + hal_entry (); + return 0; +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/pin_data.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/pin_data.c new file mode 100644 index 0000000000..3c0c8bcf72 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/pin_data.c @@ -0,0 +1,65 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC), + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH), + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.c new file mode 100644 index 0000000000..2c412c6b36 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.c @@ -0,0 +1,19 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = r_icu_isr, /* BLEIRQ (Only for BLE middleware use) */ + [1] = gpt_counter_overflow_isr, /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [3] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* BLEIRQ (Only for BLE middleware use) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_GPT1_COUNTER_OVERFLOW), /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ +}; +#endif diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.h b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.h new file mode 100644 index 0000000000..e0e4dec7d6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/ra_gen/vector_data.h @@ -0,0 +1,35 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (4) +#endif +/* ISR prototypes */ +void r_icu_isr(void); +void gpt_counter_overflow_isr(void); +void agt_int_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type) 0) /* BLEIRQ (Only for BLE middleware use) */ +#define VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type) 2) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type) 3) /* ICU IRQ4 (External pin interrupt 4) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + ICU_IRQ8_IRQn = 0, /* BLEIRQ (Only for BLE middleware use) */ + GPT1_COUNTER_OVERFLOW_IRQn = 1, /* GPT1 COUNTER OVERFLOW (Overflow) */ + AGT0_INT_IRQn = 2, /* AGT0 INT (AGT interrupt) */ + ICU_IRQ4_IRQn = 3, /* ICU IRQ4 (External pin interrupt 4) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/script/ra4w1.ld b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/script/ra4w1.ld new file mode 100644 index 0000000000..6b8e553975 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/script/ra4w1.ld @@ -0,0 +1,280 @@ +/* + Linker File for RA4W1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x0080000 /* 512K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0018000 /* 96K */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x0002000 /* 8K */ + + ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x20 /* 32 bytes */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} diff --git a/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/src/hal_entry.c b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/src/hal_entry.c new file mode 100644 index 0000000000..c84178fde3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_baremetal_ek_ra4w1/src/hal_entry.c @@ -0,0 +1,41 @@ +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +extern void app_main(void); +FSP_CPP_FOOTER + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + app_main(); +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { +#if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ +#endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.cproject b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.cproject new file mode 100644 index 0000000000..dedef0d196 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.cproject @@ -0,0 +1,326 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.project b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.project similarity index 96% rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.project rename to application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.project index 9cd9e4edfa..057d09cd49 100644 --- a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.project +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.project @@ -1,6 +1,6 @@ - reset_ek_ra6m3 + ble_freertos_ek_ra4w1 diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/CoverageSetting.xml b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/CoverageSetting.xml similarity index 100% rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/CoverageSetting.xml rename to application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/CoverageSetting.xml diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/DebugVirtualConsoleSetting.xml b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/DebugVirtualConsoleSetting.xml new file mode 100644 index 0000000000..098c55d872 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/DebugVirtualConsoleSetting.xml @@ -0,0 +1,12 @@ + + + + true + + false + + 0 + true + false + + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central new file mode 100644 index 0000000000..cfdcfba7d3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.central @@ -0,0 +1 @@ +{"Scan":{"Name":"Scan","CheckEnableFast":false,"CheckSetAdvertisePeriod":false,"FastWindow":30,"FastInterval":60,"FastPeriod":30000,"ReduceWindow":11.25,"ReduceInterval":1280,"ReducePeriod":0,"PassiveScanning":true,"ActiveScanning":false,"AllowAll":true,"AllowOnlyWhitelist":false,"FilterDisabled":false,"FilterEnabled":true,"CheckFilterReset":false},"ScanFilterData":[{"Name":"Flags","AdType":1,"Check":false,"LimitediscoverableMode":false,"GeneralDiscoverableMode":true,"NonDiscoverableMode":false,"NotSupported":true,"Controller":false,"Host":false},{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":false,"ShortName":false,"LocalName":""},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"Connection":{"Name":"Connection","Interval":50,"Latency":0,"SupervisionTiomeOut":5120,"connectionTiomeOut":5}} \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral new file mode 100644 index 0000000000..97f1179109 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.peripheral @@ -0,0 +1 @@ +{"AdvertisingData":[{"Name":"Flags","AdType":1,"Check":true,"LimitediscoverableMode":false,"GeneralDiscoverableMode":true,"NonDiscoverableMode":false,"NotSupported":false,"Controller":true,"Host":true},{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":true,"ShortName":true,"LocalName":"RBLE"},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"Scan":[{"Name":"ServiceClassUUIDs","AdType":2,"Check":false,"ServiceUUIDList":[]},{"Name":"Local Name","AdType":8,"Check":true,"ShortName":false,"LocalName":"TEST_RBLE"},{"Name":"Tx Power Level","AdType":10,"Check":false,"TxPowerLevel":0},{"Name":"Slave Connection Interval Range","AdType":18,"Check":false,"MinValue":65535,"MaxValue":65535},{"Name":"ServiceSolicitationUUIDs","AdType":20,"Check":false,"ServiceUUIDList":[]},{"Name":"Service Data","AdType":22,"Check":false,"ServiceData":[]},{"Name":"Public Target Address","AdType":23,"Check":false,"PublicTargetAddress":[]},{"Name":"Random Target Address","AdType":24,"Check":false,"RandomTargetAddress":[]},{"Name":"Appearance","AdType":25,"Check":false,"Appearance":0},{"Name":"Advertising Interval","AdType":26,"Check":false,"AdvertisingInterval":0},{"Name":"Manufacturer Specific Data","AdType":-1,"Check":false,"ManufacturerSpecificData":[]}],"AdvertisingEventsData":{"Name":"AdvertisingEventsData","CheckEnableFast":false,"CheckSetAdvertisePeriod":false,"FastInterval":30,"FastPeriod":30000,"ReduceInterval":60,"ReducePeriod":0,"CheckChannel37":true,"CheckChannel38":true,"CheckChannel39":true,"PublicAddress":false,"RandomAddress":true,"CheckImage":true}} \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile new file mode 100644 index 0000000000..c65f8aa8eb --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/.settings/com.renesas.apltool.blera/config_ble.profile @@ -0,0 +1 @@ +{"profileName":"Profile","qeIsCentralDevice":false,"services":[{"name":"GAP Service","uuid":["0x00","0x18"],"abbreviation":"gap","description":"The generic_access service contains generic information about the device.","aux_properties":["None"],"error_codes":[],"characteristics":[{"name":"Device Name","abbreviation":"dev name","uuid":["0x00","0x2A"],"description":"The Device Name characteristic shall contain the name of the device.","properties":["Read","Write"],"aux_properties":[],"value":"","db_size":128,"fields":[{"name":"Name","description":"Name","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Appearance","abbreviation":"appearance","uuid":["0x01","0x2A"],"description":"The Appearance characteristic defines the representation of the external appearance of the device.","properties":["Read"],"aux_properties":[],"value":"","db_size":2,"fields":[{"name":"Category","description":"Category","format":"uint16_t","length":"1","enumerations":[{"value":"Unknown","key":0,"description":"Unknown"},{"value":"Generic Phone","key":64,"description":"Generic Phone"},{"value":"Generic Computer","key":128,"description":"Generic Computer"},{"value":"Generic Watch","key":192,"description":"Generic Watch"},{"value":"Watch Sports Watch","key":193,"description":"Watch: Sports Watch"},{"value":"Generic Clock","key":256,"description":"Generic Clock"},{"value":"Generic Display","key":320,"description":"Generic Display"},{"value":"Generic Remote Control","key":384,"description":"Generic Remote Control"},{"value":"Generic Eye-glasses","key":448,"description":"Generic Eye-glasses"},{"value":"Generic Tag","key":512,"description":"Generic Tag"},{"value":"Generic Keyring","key":576,"description":"Generic Keyring"},{"value":"Generic Media Player","key":640,"description":"Generic Media Player"},{"value":"Generic Barcode Scanner","key":704,"description":"Generic Barcode Scanner"},{"value":"Generic Thermometer","key":768,"description":"Generic Thermometer"},{"value":"Thermometer Ear","key":769,"description":"Thermometer Ear"},{"value":"Generic Heart rate Sensor","key":832,"description":"Generic Heart rate Sensor"},{"value":"Heart Rate Sensor Heart Rate Belt","key":833,"description":"Heart Rate Sensor Heart Rate Belt"},{"value":"Generic Blood Pressure","key":896,"description":"Generic Blood Pressure"},{"value":"Blood Pressure Arm","key":897,"description":"Blood Pressure: Arm"},{"value":"Blood Pressure Wrist","key":898,"description":"Blood Pressure: Wrist"},{"value":"Human Interface Device","key":960,"description":"Human Interface Device (HID)"},{"value":"Keyboard","key":961,"description":"Keyboard"},{"value":"Mouse","key":962,"description":"Mouse"},{"value":"Joystick","key":963,"description":"Joystick"},{"value":"Gamepad","key":964,"description":"Gamepad"},{"value":"Digitizer Tablet","key":965,"description":"Digitizer Tablet"},{"value":"Card Reader","key":966,"description":"Card Reader"},{"value":"Digital Pen","key":967,"description":"Digital Pen"},{"value":"Barcode Scanner","key":968,"description":"Barcode Scanner"},{"value":"Generic Glucose Meter","key":1024,"description":"Generic Glucose Meter"},{"value":"Generic Running Walking Sensor","key":1088,"description":"Generic: Running Walking Sensor"},{"value":"Running Walking Sensor In Shoe","key":1089,"description":"Running Walking Sensor: In-Shoe"},{"value":"Running Walking Sensor On Shoe","key":1090,"description":"Running Walking Sensor: On-Shoe"},{"value":"Running Walking Sensor On Hip","key":1091,"description":"Running Walking Sensor: On-Hip"},{"value":"Generic: Cycling","key":1152,"description":"Generic Cycling"},{"value":"Cycling Cycling Computer","key":1153,"description":"Cycling Cycling Computer"},{"value":"Cycling Speed Sensor","key":1154,"description":"Cycling Speed Sensor"},{"value":"Cycling Cadence Sensor","key":1155,"description":"Cycling Cadence Sensor"},{"value":"Cycling Power Sensor","key":1156,"description":"Cycling: Power Sensor"},{"value":"Cycling Speed and Cadence Sensor","key":1157,"description":"Cycling Speed and Cadence Sensor"},{"value":"Generic Pulse Oximeter","key":3136,"description":"Generic Pulse Oximeter"},{"value":"Fingertip","key":3137,"description":"Fingertip"},{"value":"Wrist Worn","key":3138,"description":"Wrist Worn"},{"value":"Generic: Weight Scale","key":3200,"description":"Generic Weight Scale"},{"value":"Generic Outdoor Sports Activity","key":5184,"description":"Generic Outdoor Sports Activity"},{"value":"Location Display Device","key":5185,"description":"Location Display Device"},{"value":"Location and Navigation Display Device","key":5186,"description":"Location and Navigation Display Device"},{"value":"Location Pod","key":5187,"description":"Location Pod"},{"value":"Location and Navigation Pod","key":5188,"description":"Location and Navigation Pod"}],"fields":[]}],"descriptors":[]},{"name":"Peripheral Preferred Connection Parameters","abbreviation":"per pref conn param","uuid":["0x04","0x2A"],"description":"The Peripheral Preferred Connection Parameters (PPCP) characteristic contains the preferred connection parameters of the Peripheral","properties":["Read"],"aux_properties":[],"value":"","db_size":8,"fields":[{"name":"Minimum Connection Interval","description":"Minimum Connection Interval","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Maximum Connection Interval","description":"Maximum Connection Interval","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Slave Latency","description":"Slave Latency","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"Connection Supervision Timeout Multiplier","description":"Connection Supervision Timeout Multiplier","format":"uint16_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Central Address Resolution","abbreviation":"cent addr rslv","uuid":["0xA6","0x2A"],"description":"The Peripheral should check if the peer device supports address resolution by reading the Central Address Resolution characteristic.","properties":["Read"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"Central Address Resolution Support","description":"Central Address Resolution Support","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]},{"name":"Resolvable Private Address Only","abbreviation":"rslv priv addr only","uuid":["0xC9","0x2A"],"description":"The device should check if the peer will only use Resolvable Private Addresses (RPAs) after bonding by reading the Resolvable Private Address Only characteristic.","properties":["Read"],"aux_properties":[],"value":"","db_size":1,"fields":[{"name":"Resolvable Private Address Only","description":"Resolvable Private Address Only","format":"uint8_t","length":"1","bits":[],"fields":[]}],"descriptors":[]}],"qeServiceDataIsSigAdopted":true,"qeServiceDefinitionJsonFileName":"generic_access.service.json","qeServiceDataIsOutputServerRole":true,"qeServiceDataIsOutputClentRole":true},{"name":"GATT Service","uuid":["0x01","0x18"],"abbreviation":"gat","description":"The Generic Attribute Service contains generic information of the GATT attributes.","aux_properties":["None"],"error_codes":[],"characteristics":[{"name":"Service Changed","abbreviation":"serv chged","uuid":["0x05","0x2A"],"description":"The Service Changed characteristic is a control-point attribute that shall be used to indicate to connected devices that services have changed.","properties":["Indicate"],"aux_properties":[],"value":"","db_size":4,"fields":[{"name":"start_hdl","description":"Start of Affected Attribute Handle Range","format":"uint16_t","length":"1","bits":[],"fields":[]},{"name":"end_hdl","description":"End of Affected Attribute Handle Range","format":"uint16_t","length":"1","bits":[],"fields":[]}],"descriptors":[{"name":"Client Characteristic Configuration","abbreviation":"cli cnfg","uuid":["0x02","0x29"],"description":"Client Characteristic Configuration Descriptor","aux_properties":["Peer Specific"],"properties":["Read","Write"],"value":"","db_size":2,"fields":[{"name":"cli cnfg","description":"Client Characteristic Configuration","format":"uint16_t","length":"1","bits":[],"fields":[]}]}]}],"qeServiceDataIsSigAdopted":true,"qeServiceDefinitionJsonFileName":"generic_attribute.service.json","qeServiceDataIsOutputServerRole":true,"qeServiceDataIsOutputClentRole":false},{"name":"LED Switch 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a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/R7FA4W1AD2CNG.pincfg b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/R7FA4W1AD2CNG.pincfg new file mode 100644 index 0000000000..652a1e38ee --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/R7FA4W1AD2CNG.pincfg @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/RA4W1-EK.pincfg b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/RA4W1-EK.pincfg new file mode 100644 index 0000000000..417e7b87c8 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/RA4W1-EK.pincfg @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/secure_data_at_rest_ek_ra6m3.elf.jlink b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ble_freertos_ek_ra4w1 Debug.jlink similarity index 100% rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/secure_data_at_rest_ek_ra6m3.elf.jlink rename to application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ble_freertos_ek_ra4w1 Debug.jlink diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ble_freertos_ek_ra4w1 Debug.launch b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ble_freertos_ek_ra4w1 Debug.launch new file mode 100644 index 0000000000..67fe854038 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ble_freertos_ek_ra4w1 Debug.launch @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/configuration.xml b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/configuration.xml new file mode 100644 index 0000000000..f8e4f7ceb2 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/configuration.xml @@ -0,0 +1,448 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FreeRTOS + Amazon.AWS.1.1.1.pack + + + Arm CMSIS Version 5 - Core (M) + Arm.CMSIS5.5.6.0.pack + + + EK-RA4W1 Board Support Files + Renesas.RA_board_ra4w1_ek.1.1.1.pack + + + Board Support Package Common Files + Renesas.RA.1.1.1.pack + + + I/O Port + Renesas.RA.1.1.1.pack + + + Board support package for R7FA4W1AD2CNG + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Board support package for RA4W1 + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Board support package for RA4W1 - FSP Data + Renesas.RA_mcu_ra4w1.1.1.1.pack + + + Asynchronous General Purpose Timer + Renesas.RA.1.1.1.pack + + + Flash Memory Low Power + Renesas.RA.1.1.1.pack + + + General PWM Timer + Renesas.RA.1.1.1.pack + + + External Interrupt + Renesas.RA.1.1.1.pack + + + Bluetooth Low Energy Abstraction + Renesas.RA.1.1.1.pack + + + Renesas Bluetooth Low Energy Library + Renesas.RA.1.1.1.pack + + + FreeRTOS - Memory Management - Heap 4 + Amazon.AWS.1.1.1.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/app_main.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/app_main.c new file mode 100644 index 0000000000..aed8f4ca5a --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/app_main.c @@ -0,0 +1,684 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/****************************************************************************** +* File Name : app_main.c +* Device(s) : RA4W1 +* Tool-Chain : e2Studio +* Description : This is a application file for peripheral role. +*******************************************************************************/ + +/****************************************************************************** + Includes , "Project Includes" +*******************************************************************************/ +#include +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#include "rm_ble_abs_api.h" +#include "gatt_db.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "profile_cmn/r_ble_servc_if.h" +#include "hal_data.h" + +/* This code is needed for using FreeRTOS */ +#if (BSP_CFG_RTOS == 2) +#include "FreeRTOS.h" +#include "task.h" +#include "event_groups.h" +#define BLE_EVENT_PATTERN (0x0A0A) +EventGroupHandle_t g_ble_event_group_handle; +#endif +#include "r_ble_lss.h" + +/****************************************************************************** + User file includes +*******************************************************************************/ +/* Start user code for file includes. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +#define BLE_LOG_TAG "app_main" +#define BLE_GATTS_QUEUE_ELEMENTS_SIZE (14) +#define BLE_GATTS_QUEUE_BUFFER_LEN (245) +#define BLE_GATTS_QUEUE_NUM (1) + +/****************************************************************************** + User macro definitions +*******************************************************************************/ +/* Start user code for macro definitions. Do not edit comment generated here */ +#define BLE_CFG_BOARD_TYPE 1 + +#define BLE_BOARD_SW1_PIN BSP_IO_PORT_04_PIN_02 +#undef BLE_BOARD_SW2_PIN +#define BLE_BOARD_SW1_IRQ ELC_EVENT_ICU_IRQ4 +#undef BLE_BOARD_SW2_IRQ +#define BLE_BOARD_LED1_PIN BSP_IO_PORT_01_PIN_06 +#define BLE_BOARD_LED2_PIN BSP_IO_PORT_04_PIN_04 +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated function prototype declarations +*******************************************************************************/ +/* Internal functions */ +void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data); +void gatts_cb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data); +void gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data); +void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data); +ble_status_t ble_init(void); +void app_main(void); + +/****************************************************************************** + User function prototype declarations +*******************************************************************************/ +/* Start user code for function prototype declarations. Do not edit comment generated here */ +typedef enum +{ + BLE_BOARD_LED1, /**< LED1 */ + BLE_BOARD_LED2, /**< LED2 */ + + BLE_BOARD_LED_MAX +} e_ble_led_t; + +/*******************************************************************************************************************//** + * @brief Switch number. +***********************************************************************************************************************/ +typedef enum +{ + BLE_BOARD_SW1, /**< Switch1 */ + BLE_BOARD_SW2, /**< Switch2 */ + + BLE_BOARD_SW_MAX +} e_ble_sw_t; + + +typedef void (*ble_sw_cb_t)(void); +static void timer_update(); +static void sw_cb(void); +static void R_BLE_BOARD_Init(void); +static void R_BLE_BOARD_ToggleLEDState(e_ble_led_t led); +static void R_BLE_BOARD_SetLEDState(e_ble_led_t led, bool onoff); +static void R_BLE_BOARD_RegisterSwitchCb(e_ble_sw_t sw, ble_sw_cb_t cb); +static ble_sw_cb_t gs_sw_cb[BLE_BOARD_SW_MAX]; +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated global variables +*******************************************************************************/ +/* Advertising Data */ +static uint8_t gs_advertising_data[] = +{ + /* Flags */ + 0x02, /**< Data Size */ + 0x01, /**< Data Type */ + ( 0x1a ), /**< Data Value */ + + /* Shortened Local Name */ + 0x05, /**< Data Size */ + 0x08, /**< Data Type */ + 0x52, 0x42, 0x4c, 0x45, /**< Data Value */ +}; + +/* Scan Response Data */ +static uint8_t gs_scan_response_data[] = +{ + /* Complete Local Name */ + 0x0A, /**< Data Size */ + 0x09, /**< Data Type */ + 0x54, 0x45, 0x53, 0x54, 0x5f, 0x52, 0x42, 0x4c, 0x45, /**< Data Value */ +}; + +ble_abs_legacy_advertising_parameter_t g_ble_advertising_parameter = +{ + .p_peer_address = NULL, ///< Peer address. + .slow_advertising_interval = 0x00000060, ///< Slow advertising interval. 60.0(ms) + .slow_advertising_period = 0x0000, ///< Slow advertising period. + .p_advertising_data = gs_advertising_data, ///< Advertising data. If p_advertising_data is specified as NULL, advertising data is not set. + .advertising_data_length = ARRAY_SIZE(gs_advertising_data), ///< Advertising data length (in bytes). + .p_scan_response_data = gs_scan_response_data, ///< Scan response data. If p_scan_response_data is specified as NULL, scan response data is not set. + .scan_response_data_length = ARRAY_SIZE(gs_scan_response_data), ///< Scan response data length (in bytes). + .advertising_filter_policy = BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY, ///< Advertising Filter Policy. + .advertising_channel_map = ( BLE_GAP_ADV_CH_37 | BLE_GAP_ADV_CH_38 | BLE_GAP_ADV_CH_39 ), ///< Channel Map. + .own_bluetooth_address_type = BLE_GAP_ADDR_RAND, ///< Own Bluetooth address type. + .own_bluetooth_address = { 0 }, +}; + +/* GATT server callback parameters */ +ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[] = +{ + { + .gatt_server_callback_function = gatts_cb, + .gatt_server_callback_priority = 1, + }, + { + .gatt_server_callback_function = NULL, + } +}; + +/* GATT client callback parameters */ +ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[] = +{ + { + .gatt_client_callback_function = gattc_cb, + .gatt_client_callback_priority = 1, + }, + { + .gatt_client_callback_function = NULL, + } +}; + +/* GATT server Prepare Write Queue parameters */ +static st_ble_gatt_queue_elm_t gs_queue_elms[BLE_GATTS_QUEUE_ELEMENTS_SIZE]; +static uint8_t gs_buffer[BLE_GATTS_QUEUE_BUFFER_LEN]; +static st_ble_gatt_pre_queue_t gs_queue[BLE_GATTS_QUEUE_NUM] = { + { + .p_buf_start = gs_buffer, + .buffer_len = BLE_GATTS_QUEUE_BUFFER_LEN, + .p_queue = gs_queue_elms, + .queue_size = BLE_GATTS_QUEUE_ELEMENTS_SIZE, + } +}; + +/* Connection handle */ +uint16_t g_conn_hdl; + +/****************************************************************************** + User global variables +*******************************************************************************/ +/* Start user code for global variables. Do not edit comment generated here */ +static bool g_interval_update_flag = true; +static uint8_t g_current_blinky_interval = 0x88; +/* End user code. Do not edit comment generated here */ + +/****************************************************************************** + Generated function definitions +*******************************************************************************/ +/****************************************************************************** + * Function Name: gap_cb + * Description : Callback function for GAP API. + * Arguments : uint16_t type - + * Event type of GAP API. + * : ble_status_t result - + * Event result of GAP API. + * : st_ble_vs_evt_data_t *p_data - + * Event parameters of GAP API. + * Return Value : none + ******************************************************************************/ +void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GAP callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + switch(type) + { + case BLE_GAP_EVENT_STACK_ON: + { + /* Get BD address for Advertising */ + R_BLE_VS_GetBdAddr(BLE_VS_ADDR_AREA_REG, BLE_GAP_ADDR_RAND); + } break; + + case BLE_GAP_EVENT_CONN_IND: + { + if (BLE_SUCCESS == result) + { + /* Store connection handle */ + st_ble_gap_conn_evt_t *p_gap_conn_evt_param = (st_ble_gap_conn_evt_t *)p_data->p_param; + g_conn_hdl = p_gap_conn_evt_param->conn_hdl; + } + else + { + /* Restart advertising when connection failed */ + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } + } break; + + case BLE_GAP_EVENT_DISCONN_IND: + { + /* Restart advertising when disconnected */ + g_conn_hdl = BLE_GAP_INVALID_CONN_HDL; + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } break; + + case BLE_GAP_EVENT_CONN_PARAM_UPD_REQ: + { + /* Send connection update response with value received on connection update request */ + st_ble_gap_conn_upd_req_evt_t *p_conn_upd_req_evt_param = (st_ble_gap_conn_upd_req_evt_t *)p_data->p_param; + + st_ble_gap_conn_param_t conn_updt_param = { + .conn_intv_min = p_conn_upd_req_evt_param->conn_intv_min, + .conn_intv_max = p_conn_upd_req_evt_param->conn_intv_max, + .conn_latency = p_conn_upd_req_evt_param->conn_latency, + .sup_to = p_conn_upd_req_evt_param->sup_to, + }; + + R_BLE_GAP_UpdConn(p_conn_upd_req_evt_param->conn_hdl, + BLE_GAP_CONN_UPD_MODE_RSP, + BLE_GAP_CONN_UPD_ACCEPT, + &conn_updt_param); + } break; + +/* Hint: Add cases of GAP event macros defined as BLE_GAP_XXX */ +/* Start user code for GAP callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: gatts_cb + * Description : Callback function for GATT Server API. + * Arguments : uint16_t type - + * Event type of GATT Server API. + * : ble_status_t result - + * Event result of GATT Server API. + * : st_ble_gatts_evt_data_t *p_data - + * Event parameters of GATT Server API. + * Return Value : none + ******************************************************************************/ +void gatts_cb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GATT Server callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVS_GattsCb(type, result, p_data); + switch(type) + { +/* Hint: Add cases of GATT Server event macros defined as BLE_GATTS_XXX */ +/* Start user code for GATT Server callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: gattc_cb + * Description : Callback function for GATT Client API. + * Arguments : uint16_t type - + * Event type of GATT Client API. + * : ble_status_t result - + * Event result of GATT Client API. + * : st_ble_gattc_evt_data_t *p_data - + * Event parameters of GATT Client API. + * Return Value : none + ******************************************************************************/ +void gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for GATT Client callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVC_GattcCb(type, result, p_data); + switch(type) + { + +/* Hint: Add cases of GATT Client event macros defined as BLE_GATTC_XXX */ +/* Start user code for GATT Client callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: vs_cb + * Description : Callback function for Vendor Specific API. + * Arguments : uint16_t type - + * Event type of Vendor Specific API. + * : ble_status_t result - + * Event result of Vendor Specific API. + * : st_ble_vs_evt_data_t *p_data - + * Event parameters of Vendor Specific API. + * Return Value : none + ******************************************************************************/ +void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for vender specific callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + R_BLE_SERVS_VsCb(type, result, p_data); + switch(type) + { + case BLE_VS_EVENT_GET_ADDR_COMP: + { + /* Start advertising when BD address is ready */ + st_ble_vs_get_bd_addr_comp_evt_t * get_address = (st_ble_vs_get_bd_addr_comp_evt_t *)p_data->p_param; + memcpy(g_ble_advertising_parameter.own_bluetooth_address, get_address->addr.addr, BLE_BD_ADDR_LEN); + RM_BLE_ABS_StartLegacyAdvertising(&g_ble_abs0_ctrl, &g_ble_advertising_parameter); + } break; + +/* Hint: Add cases of vender specific event macros defined as BLE_VS_XXX */ +/* Start user code for vender specific callback function event process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + } +} + +/****************************************************************************** + * Function Name: lss_cb + * Description : Callback function for LED Switch Service server feature. + * Arguments : uint16_t type - + * Event type of LED Switch Service server feature. + * : ble_status_t result - + * Event result of LED Switch Service server feature. + * : st_ble_servs_evt_data_t *p_data - + * Event parameters of LED Switch Service server feature. + * Return Value : none + ******************************************************************************/ +static void lss_cb(uint16_t type, ble_status_t result, st_ble_servs_evt_data_t *p_data) +{ +/* Hint: Input common process of callback function such as variable definitions */ +/* Start user code for LED Switch Service Server callback function common process. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + switch(type) + { +/* Hint: Add cases of LED Switch Service server events defined in e_ble_lss_event_t */ +/* Start user code for LED Switch Service Server callback function event process. Do not edit comment generated here */ + case BLE_LSS_EVENT_BLINK_RATE_WRITE_REQ: + { + g_current_blinky_interval = *(uint8_t *)p_data->p_param; + + if (g_current_blinky_interval == 0x00) + { + R_BLE_BOARD_SetLEDState(BLE_BOARD_LED1, true); // LED OFF + } + else if (g_current_blinky_interval == 0xFF) + { + R_BLE_BOARD_SetLEDState(BLE_BOARD_LED1, false); // LED ON + } + g_interval_update_flag = true; + } break; + + default: + break; +/* End user code. Do not edit comment generated here */ + } +} +/****************************************************************************** + * Function Name: ble_init + * Description : Initialize BLE and profiles. + * Arguments : none + * Return Value : BLE_SUCCESS - SUCCESS + * BLE_ERR_INVALID_OPERATION - + * Failed to initialize BLE or profiles. + ******************************************************************************/ +ble_status_t ble_init(void) +{ + ble_status_t status; + fsp_err_t err; + + /* Initialize BLE */ + err = RM_BLE_ABS_Open(&g_ble_abs0_ctrl, &g_ble_abs0_cfg); + if (FSP_SUCCESS != err) + { + return err; + } + + /* Initialize GATT Database */ + status = R_BLE_GATTS_SetDbInst(&g_gatt_db_table); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /* Initialize GATT server */ + status = R_BLE_SERVS_Init(); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /*Initialize GATT client */ + status = R_BLE_SERVC_Init(); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + /* Set Prepare Write Queue */ + R_BLE_GATTS_SetPrepareQueue(gs_queue, BLE_GATTS_QUEUE_NUM); + + /* Initialize LED Switch Service server API */ + status = R_BLE_LSS_Init(lss_cb); + if (BLE_SUCCESS != status) + { + return BLE_ERR_INVALID_OPERATION; + } + + return status; +} + +/****************************************************************************** + * Function Name: app_main + * Description : Application main function with main loop + * Arguments : none + * Return Value : none + ******************************************************************************/ +void app_main(void) +{ +#if (BSP_CFG_RTOS == 2) + /* Create Event Group */ + g_ble_event_group_handle = xEventGroupCreate(); + assert(g_ble_event_group_handle); +#endif + + /* Initialize BLE and profiles */ + ble_init(); + +/* Hint: Input process that should be done before main loop such as calling initial function or variable definitions */ +/* Start user code for process before main loop. Do not edit comment generated here */ + R_BLE_BOARD_Init(); + R_BLE_BOARD_RegisterSwitchCb(BLE_BOARD_SW1, sw_cb); +/* End user code. Do not edit comment generated here */ + + /* main loop */ + while (1) + { + /* Process BLE Event */ + R_BLE_Execute(); + +/* When this BLE application works on the FreeRTOS */ +#if (BSP_CFG_RTOS == 2) + if(0 != R_BLE_IsTaskFree()) + { + /* If the BLE Task has no operation to be processed, it transits block state until the event from RF transciever occurs. */ + xEventGroupWaitBits(g_ble_event_group_handle, + (EventBits_t)BLE_EVENT_PATTERN, + pdTRUE, + pdFALSE, + portMAX_DELAY); + } +#endif + +/* Hint: Input process that should be done during main loop such as calling processing functions */ +/* Start user code for process during main loop. Do not edit comment generated here */ + timer_update(); +/* End user code. Do not edit comment generated here */ + } + +/* Hint: Input process that should be done after main loop such as calling closing functions */ +/* Start user code for process after main loop. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + /* Terminate BLE */ + RM_BLE_ABS_Close(&g_ble_abs0_ctrl); +} + +/****************************************************************************** + User function definitions +*******************************************************************************/ +/* Start user code for function definitions. Do not edit comment generated here */ +/****************************************************************************** + * Function Name: timer_cb + * Description : Callback function for timer for LED blink. + * Arguments : uint32_t timer_hdl - + * Timer handle identifying a expired timer. + * Return Value : none + ******************************************************************************/ +static void timer_update() +{ + static uint32_t remain_time; + + if(true == g_interval_update_flag){ + remain_time = 1 + (uint32_t) g_current_blinky_interval * 100 / 0xFF; + g_interval_update_flag = false; + }else if ((0 == remain_time)&&(0 != g_current_blinky_interval)&&(0xFF != g_current_blinky_interval)) + { + R_BLE_BOARD_ToggleLEDState (BLE_BOARD_LED1); + remain_time = 1 + (uint32_t) g_current_blinky_interval * 100 / 0xFF; + } + + remain_time--; + +} + +static void sw_cb(void) +{ + uint8_t state = 1; + +#if (BLE_CFG_BOARD_TYPE == 1) +#endif + R_BLE_LSS_NotifySwitchState(g_conn_hdl, &state); +} + +static void R_BLE_BOARD_SetLEDState(e_ble_led_t led, bool onoff) +{ + FSP_PARAMETER_NOT_USED (onoff); + + if (led == BLE_BOARD_LED1) + { +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); +#if (BLE_CFG_BOARD_TYPE == 1) + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (onoff) ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); +#else + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (onoff) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); +#endif + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } + else if (led == BLE_BOARD_LED2) + { +#ifdef BLE_BOARD_LED2_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); +#if (BLE_CFG_BOARD_TYPE == 1) + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (onoff) ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); +#else + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (onoff) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); +#endif + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } +} + +static void R_BLE_BOARD_ToggleLEDState(e_ble_led_t led) +{ + bsp_io_level_t level; + + if (led == BLE_BOARD_LED1) + { +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + g_ioport.p_api->pinRead(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, &level); + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, (level == BSP_IO_LEVEL_HIGH) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } + else if (led == BLE_BOARD_LED2) + { +#ifdef BLE_BOARD_LED2_PIN + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + g_ioport.p_api->pinRead(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, &level); + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, (level == BSP_IO_LEVEL_HIGH) ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH); + g_ioport.p_api->close(g_ioport.p_ctrl); +#endif /* BLE_BOARD_LED1_PIN */ + } +} + +static void R_BLE_BOARD_RegisterSwitchCb(e_ble_sw_t sw, ble_sw_cb_t cb) +{ + FSP_PARAMETER_NOT_USED (cb); + + if (sw == BLE_BOARD_SW1) + { +#ifdef BLE_BOARD_SW1_IRQ + gs_sw_cb[0] = cb; + g_ble_sw_irq.p_api->open(g_ble_sw_irq.p_ctrl, g_ble_sw_irq.p_cfg); + g_ble_sw_irq.p_api->enable(g_ble_sw_irq.p_ctrl); +#endif + } + else if (sw == BLE_BOARD_SW2) + { +#ifdef BLE_BOARD_SW2_IRQ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_NMI_PIN, cb); + R_ICU->NMIER_b.NMIEN = 1; +#endif + } +} + +static void irq_pin_set(void) +{ + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + +#if (BLE_CFG_BOARD_TYPE == 0) /* for customer board */ + +#elif (BLE_CFG_BOARD_TYPE == 1) /* Promotion board */ + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW1_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + +#elif (BLE_CFG_BOARD_TYPE == 2) /* Reserve */ + +#elif (BLE_CFG_BOARD_TYPE == 3) /* RF Evaluation board */ + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW1_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_SW2_PIN, + IOPORT_CFG_PORT_DIRECTION_INPUT|IOPORT_CFG_IRQ_ENABLE|IOPORT_CFG_EVENT_FALLING_EDGE|IOPORT_CFG_PULLUP_ENABLE); + +#endif /* BLE_CFG_BOARD_TYPE == x */ + + g_ioport.p_api->close(g_ioport.p_ctrl); +} + +static void R_BLE_BOARD_Init(void) +{ + g_ioport.p_api->open(g_ioport.p_ctrl, g_ioport.p_cfg); + +#ifdef BLE_BOARD_LED1_PIN + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_LED1_PIN, + IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_HIGH); +#endif +#if BLE_BOARD_LED2_PIN + g_ioport.p_api->pinCfg(g_ioport.p_ctrl, BLE_BOARD_LED2_PIN, + IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_LOW); +#endif + + g_ioport.p_api->close(g_ioport.p_ctrl); + + irq_pin_set(); + + /* Set wake up trigger */ +#if (BLE_CFG_BOARD_TYPE == 1) /* Promotion board */ +#elif (BLE_CFG_BOARD_TYPE == 2) /* RSSK */ +#elif (BLE_CFG_BOARD_TYPE == 3) /* Evaluation boars */ + R_BLE_BOARD_RegisterSwitchCb(BLE_BOARD_SW2, ble_sw_cb); +#endif +} + +void Callback_ble_sw_irq(external_irq_callback_args_t *p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + gs_sw_cb[0](); +} +/* End user code. Do not edit comment generated here */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c new file mode 100644 index 0000000000..29f53a1342 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.c @@ -0,0 +1,519 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include "r_ble_disc.h" + +static uint8_t gs_state; +static uint8_t gs_target_inc_serv_pos; + +/* Entries */ +static const st_ble_disc_entry_t *gs_prim_entries; +static uint8_t gs_num_of_prim_entries; +static uint8_t gs_prim_entry_pos; + +/* Primary Service */ +static st_ble_gatt_hdl_range_t gs_serv_range; +static uint8_t gs_num_of_servs; + +/* Included Srvice */ +static st_disc_inc_serv_param_t gs_inc_servs[BLE_DISC_INC_SERV_MAX_NUM]; +static uint8_t gs_inc_serv_pos; +static uint8_t gs_num_of_inc_servs; + +/* Characteristic */ +static st_disc_char_param_t gs_chars[BLE_DISC_CHAR_MAX_NUM]; +static uint8_t gs_num_of_chars; +static uint8_t gs_char_pos; + +/* Descriptor */ +static st_disc_desc_param_t gs_descs[BLE_DISC_DESC_MAX_NUM]; +static uint8_t gs_num_of_descs; + +static bool gs_in_progress; +static ble_disc_comp_cb_t gs_comp_cb; + +static void r_ble_start_serv_disc(uint16_t conn_hdl); +static void r_ble_start_inc_serv_disc(uint16_t conn_hdl); +static void r_ble_start_char_disc(uint16_t conn_hdl); +static void r_ble_start_desc_disc(uint16_t conn_hdl); + +static bool r_ble_disc_next_prim_serv(uint16_t conn_hdl) +{ + gs_prim_entry_pos++; + + if (gs_prim_entry_pos < gs_num_of_prim_entries) + { + gs_inc_serv_pos = 0; + gs_state = 0; + r_ble_start_serv_disc(conn_hdl); + } + else + { + if (NULL != gs_comp_cb) + { + gs_comp_cb(conn_hdl); + } + + gs_in_progress = false; + } + + return true; +} + +static bool r_ble_disc_next_inc_serv(uint16_t conn_hdl) +{ + if (gs_inc_serv_pos < gs_num_of_inc_servs) + { + gs_state = 1; + + for (uint8_t i = gs_inc_serv_pos; i < gs_num_of_inc_servs; i++) + { + for (uint8_t j = 0; j < gs_prim_entries[gs_prim_entry_pos].num_of_inc_servs; j++) + { + st_ble_disc_entry_t *p_inc_serv = &gs_prim_entries[gs_prim_entry_pos].inc_servs[j]; + + if (p_inc_serv->uuid_type == gs_inc_servs[i].uuid_type) + { + if ( + ((BLE_GATT_16_BIT_UUID_FORMAT == p_inc_serv->uuid_type) && + (((p_inc_serv->p_uuid[1] << 8) | (p_inc_serv->p_uuid[0])) == gs_inc_servs[i].value.inc_serv_16.service.uuid_16)) || + ((BLE_GATT_128_BIT_UUID_FORMAT == p_inc_serv->uuid_type) && + (0 == memcmp(p_inc_serv->p_uuid, gs_inc_servs[i].value.inc_serv_128.service.uuid_128, BLE_GATT_128_BIT_UUID_SIZE)))) + { + gs_serv_range.start_hdl = gs_inc_servs[i].value.inc_serv_16.service.range.start_hdl; + gs_serv_range.end_hdl = gs_inc_servs[i].value.inc_serv_16.service.range.end_hdl; + gs_inc_serv_pos = (uint8_t)(i + 1); + gs_target_inc_serv_pos = j; + r_ble_start_char_disc(conn_hdl); + return true; + } + } + } + } + } + + return false; +} + +static bool r_ble_disc_next_char(uint16_t conn_hdl) +{ + gs_char_pos++; + + if (gs_char_pos < gs_num_of_chars) + { + r_ble_start_desc_disc(conn_hdl); + return true; + } + + return false; +} + +static void r_ble_all_disc_process(uint16_t event, uint16_t conn_hdl) +{ + switch (event) + { + case BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP: + { + if (0 == gs_num_of_servs) + { + r_ble_disc_next_prim_serv(conn_hdl); + } + else + { + r_ble_start_inc_serv_disc(conn_hdl); + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_DISC_COMP: + { + r_ble_start_char_disc(conn_hdl); + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP: + { + r_ble_start_desc_disc(conn_hdl); + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP: + { + bool next; + + next = r_ble_disc_next_char(conn_hdl); + + if (false == next) + { + next = r_ble_disc_next_inc_serv(conn_hdl); + + if (false == next) + { + r_ble_disc_next_prim_serv(conn_hdl); + } + } + } break; + + default: + { + } break; + } +} + +static void r_ble_start_serv_disc(uint16_t conn_hdl) +{ + gs_num_of_servs = 0; + + memset(&gs_serv_range, 0x00, sizeof(gs_serv_range)); + + R_BLE_GATTC_DiscPrimServ(conn_hdl, + gs_prim_entries[gs_prim_entry_pos].p_uuid, + gs_prim_entries[gs_prim_entry_pos].uuid_type); +} + +static void r_ble_start_inc_serv_disc(uint16_t conn_hdl) +{ + gs_num_of_inc_servs = 0; + gs_inc_serv_pos = 0; + + for (uint8_t i = 0; i < BLE_DISC_INC_SERV_MAX_NUM; i++) + { + memset(&gs_inc_servs[i], 0x00, sizeof(gs_inc_servs[i])); + } + + R_BLE_GATTC_DiscIncServ(conn_hdl, &gs_serv_range); +} + +static void r_ble_start_char_disc(uint16_t conn_hdl) +{ + gs_num_of_chars = 0; + gs_char_pos = 0; + + for (uint8_t i = 0; i < BLE_DISC_CHAR_MAX_NUM; i++) + { + memset(&gs_chars[i], 0x00, sizeof(gs_chars[i])); + } + + R_BLE_GATTC_DiscAllChar(conn_hdl, &gs_serv_range); +} + +static void r_ble_start_desc_disc(uint16_t conn_hdl) +{ + gs_num_of_descs = 0; + + for (uint8_t i = 0; i < BLE_DISC_DESC_MAX_NUM; i++) + { + memset(&gs_descs[i], 0x00, sizeof(gs_descs[i])); + } + + st_ble_gatt_hdl_range_t range; + + if (BLE_GATT_16_BIT_UUID_FORMAT == gs_chars[gs_char_pos].uuid_type) + { + range.start_hdl = gs_chars[gs_char_pos].value.char_16.decl_hdl; + } + else + { + range.start_hdl = gs_chars[gs_char_pos].value.char_128.decl_hdl; + } + + if (gs_char_pos < (gs_num_of_chars - 1)) + { + if (BLE_GATT_16_BIT_UUID_FORMAT == gs_chars[gs_char_pos+1].uuid_type) + { + range.end_hdl = gs_chars[gs_char_pos+1].value.char_16.decl_hdl; + } + else + { + range.end_hdl = gs_chars[gs_char_pos+1].value.char_128.decl_hdl; + } + } + else + { + range.end_hdl = gs_serv_range.end_hdl; + } + + R_BLE_GATTC_DiscAllCharDesc(conn_hdl, &range); +} + +static void r_ble_disc_gattc_cb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t *p_data) // @suppress("Function length") +{ + /* unused arg */ + (void)result; + + switch (type) + { + case BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND: + { + st_ble_gattc_serv_16_evt_t *p_serv_uuid_16_evt_params = + (st_ble_gattc_serv_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_serv_16_evt_t)); i++) + { + if (gs_num_of_servs == gs_prim_entries[gs_prim_entry_pos].idx) + { + st_disc_serv_param_t serv_param = { + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .value.serv_16.range = p_serv_uuid_16_evt_params[i].range, + .value.serv_16.uuid_16 = p_serv_uuid_16_evt_params[i].uuid_16, + }; + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_FOUND, + &serv_param); + + memcpy(&gs_serv_range, &p_serv_uuid_16_evt_params[i].range, sizeof(gs_serv_range)); + } + + gs_num_of_servs++; + } + } break; + + case BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND: + { + st_ble_gattc_serv_128_evt_t *p_serv_uuid_128_evt_params = + (st_ble_gattc_serv_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_serv_128_evt_t)); i++) + { + if (gs_num_of_servs == gs_prim_entries[gs_prim_entry_pos].idx) + { + st_disc_serv_param_t serv_param = { + .uuid_type = BLE_GATT_128_BIT_UUID_FORMAT, + .value.serv_128.range = p_serv_uuid_128_evt_params[i].range, + }; + memcpy(serv_param.value.serv_128.uuid_128, p_serv_uuid_128_evt_params[i].uuid_128, BLE_GATT_128_BIT_UUID_SIZE); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_FOUND, + &serv_param); + memcpy(&gs_serv_range, &p_serv_uuid_128_evt_params[i].range, sizeof(gs_serv_range)); + } + + gs_num_of_servs++; + } + } break; + + case BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP: + { + if (0 == gs_num_of_servs) + { + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_PRIM_SERV_NOT_FOUND, + NULL); + } + + r_ble_all_disc_process(BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_INC_SERV_16_DISC_IND: + { + st_ble_gattc_inc_serv_16_evt_t *p_inc_serv_16_evt_param = + (st_ble_gattc_inc_serv_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_inc_serv_16_evt_t)); i++) + { + gs_inc_servs[gs_num_of_inc_servs].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_16, + &p_inc_serv_16_evt_param[0], + sizeof(gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_16)); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_INC_SERV_FOUND, + &gs_inc_servs[gs_num_of_inc_servs]); + + gs_num_of_inc_servs++; + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_128_DISC_IND: + { + st_ble_gattc_inc_serv_128_evt_t *p_inc_serv_128_evt_param = + (st_ble_gattc_inc_serv_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_inc_serv_128_evt_t)); i++) + { + gs_inc_servs[gs_num_of_inc_servs].uuid_type = BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_128, + p_inc_serv_128_evt_param, + sizeof(gs_inc_servs[gs_num_of_inc_servs].value.inc_serv_128)); + + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_INC_SERV_FOUND, + &gs_inc_servs[gs_num_of_inc_servs]); + + gs_num_of_inc_servs++; + } + } break; + + case BLE_GATTC_EVENT_INC_SERV_DISC_COMP: + { + r_ble_all_disc_process(BLE_GATTC_EVENT_INC_SERV_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_CHAR_16_DISC_IND: + { + st_ble_gattc_char_16_evt_t *p_char_16_evt_params = + (st_ble_gattc_char_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_16_evt_t)); i++) + { + gs_chars[gs_num_of_chars].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_chars[gs_num_of_chars].value.char_16, + &p_char_16_evt_params[i], + sizeof(gs_chars[gs_num_of_chars].value.char_16)); + + gs_num_of_chars++; + } + } break; + + case BLE_GATTC_EVENT_CHAR_128_DISC_IND: + { + st_ble_gattc_char_128_evt_t *p_char_128_evt_params = + (st_ble_gattc_char_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_128_evt_t)); i++) + { + gs_chars[gs_num_of_chars].uuid_type = BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_chars[gs_num_of_chars].value.char_128, + &p_char_128_evt_params[i], + sizeof(gs_chars[gs_num_of_chars].value.char_128)); + + gs_num_of_chars++; + } + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP: + { + r_ble_all_disc_process(BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + case BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND: + { + st_ble_gattc_char_desc_16_evt_t *p_char_desc_16_evt_params = + (st_ble_gattc_char_desc_16_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_desc_16_evt_t)); i++) + { + gs_descs[gs_num_of_descs].uuid_type = BLE_GATT_16_BIT_UUID_FORMAT; + + memcpy(&gs_descs[gs_num_of_descs].value.desc_16, + &p_char_desc_16_evt_params[i], + sizeof(gs_descs[gs_num_of_descs].value.desc_16)); + + gs_num_of_descs++; + } + } break; + + case BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND: + { + st_ble_gattc_char_desc_128_evt_t *p_char_desc_128_evt_params = + (st_ble_gattc_char_desc_128_evt_t *)p_data->p_param; + + for (uint8_t i = 0; i < (p_data->param_len / sizeof(st_ble_gattc_char_desc_128_evt_t)); i++) + { + gs_descs[gs_num_of_descs].uuid_type = + BLE_GATT_128_BIT_UUID_FORMAT; + + memcpy(&gs_descs[gs_num_of_descs].value.desc_128, + &p_char_desc_128_evt_params[i], + sizeof(gs_descs[gs_num_of_descs].value.desc_128)); + + gs_num_of_descs++; + } + } break; + + case BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP: + { + gs_chars[gs_char_pos].descs = gs_descs; + gs_chars[gs_char_pos].num_of_descs = gs_num_of_descs; + + if (0 == gs_state) + { + gs_prim_entries[gs_prim_entry_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].idx, + BLE_DISC_CHAR_FOUND, + &gs_chars[gs_char_pos]); + } + else if (1 == gs_state) + { + gs_prim_entries[gs_prim_entry_pos].inc_servs[gs_target_inc_serv_pos].serv_cb( + p_data->conn_hdl, + gs_prim_entries[gs_prim_entry_pos].inc_servs[gs_target_inc_serv_pos].idx, + BLE_DISC_CHAR_FOUND, + &gs_chars[gs_char_pos]); + } + else + { + /* Do nothing. */ + } + + r_ble_all_disc_process(BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP, p_data->conn_hdl); + } break; + + /* ################################################################################# */ + + default: + { + /* Do nothing. */ + } + } +} + +ble_status_t R_BLE_DISC_Init(void) // @suppress("API function naming") +{ + return R_BLE_GATTC_RegisterCb(r_ble_disc_gattc_cb, 1); +} + +ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, const st_ble_disc_entry_t *p_entries, uint8_t num_of_entires, ble_disc_comp_cb_t cb) // @suppress("API function naming") +{ + if (gs_in_progress) + { + return BLE_ERR_ALREADY_IN_PROGRESS; + } + + gs_prim_entries = p_entries; + gs_num_of_prim_entries = num_of_entires; + + gs_in_progress = true; + gs_comp_cb = cb; + gs_prim_entry_pos = 0; + + r_ble_start_serv_disc(conn_hdl); + + return BLE_SUCCESS; +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h new file mode 100644 index 0000000000..c7f6045a69 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/discovery/r_ble_disc.h @@ -0,0 +1,215 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup discovery GATT Discovery Library + * @{ + * @ingroup profile_cmn + * @brief GATT Discovery Library + * @details This library provides APIs to discovery remote GATT database. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#include "r_ble_rx23w_if.h" +#else +/*RA4W*/ +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef R_BLE_DISC_H +#define R_BLE_DISC_H + +/** @defgroup discovery_macro Macros + * @{ + * @brief Macro definition + */ +/*******************************************************************************************************************//** + * @brief Maximum number of services to discover. +***********************************************************************************************************************/ +#define BLE_DISC_PRIM_SERV_MAX_NUM (10) + +/*******************************************************************************************************************//** + * @brief Maximum number of included services to discover. +***********************************************************************************************************************/ +#define BLE_DISC_INC_SERV_MAX_NUM (2) + +/*******************************************************************************************************************//** + * @brief Maximum number of characteristics to discover in a service. +***********************************************************************************************************************/ +#define BLE_DISC_CHAR_MAX_NUM (40) + +/*******************************************************************************************************************//** + * @brief Maximum number of descriptors to discover in a characteristic +***********************************************************************************************************************/ +#define BLE_DISC_DESC_MAX_NUM (10) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief GATT Discovery event. +***********************************************************************************************************************/ +typedef enum +{ + BLE_DISC_PRIM_SERV_FOUND, /**< Service discovered event */ + BLE_DISC_INC_SERV_FOUND, /**< Included service discovered event */ + BLE_DISC_PRIM_SERV_NOT_FOUND, /**< Service not discovered event */ + BLE_DISC_CHAR_FOUND, /**< Characteristic discovered event */ +} e_ble_disc_evt_t; +/*@}*/ + +/** @defgroup discovery_callback Callbacks + * @{ + * @brief Callback definition + */ +/*******************************************************************************************************************//** + * @brief Callback invoked when discovery is completed. + * @param conn_hdl connection handle +***********************************************************************************************************************/ +typedef void (* ble_disc_comp_cb_t)(uint16_t conn_hdl); + +/*******************************************************************************************************************//** + * @brief Callback invoked when service discovered. + * @param conn_hdl connection handle +***********************************************************************************************************************/ +typedef void (* ble_disc_serv_cb_t)(uint16_t conn_hdl, uint8_t idx, uint16_t type, void *p_param); +/*@}*/ + +/** @defgroup discovery_struct Structures + * @{ + * @brief Structure definition + */ +/*******************************************************************************************************************//** + * @brief Structure of service uuid to discover. +***********************************************************************************************************************/ +typedef struct st_ble_disc_entry_t +{ + uint8_t idx; /**< Service Index */ + uint8_t *p_uuid; /**< Service UUID */ + uint8_t uuid_type; /**< Service UUID type */ + ble_disc_serv_cb_t serv_cb; /**< Service discovery callback */ + uint8_t num_of_inc_servs; /**< Number of included services */ + struct st_ble_disc_entry_t *inc_servs; /**< Included service entries */ +} st_ble_disc_entry_t; + +/*******************************************************************************************************************//** + * @brief Discovered service information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered service UUID type */ + union + { + st_ble_gattc_serv_16_evt_t serv_16; + st_ble_gattc_serv_128_evt_t serv_128; + } value; +} st_disc_serv_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered included service information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered service UUID type */ + union + { + st_ble_gattc_inc_serv_16_evt_t inc_serv_16; + st_ble_gattc_inc_serv_128_evt_t inc_serv_128; + } value; +} st_disc_inc_serv_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered descriptor information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered descriptor UUID type */ + union + { + st_ble_gattc_char_desc_16_evt_t desc_16; + st_ble_gattc_char_desc_128_evt_t desc_128; + } value; +} st_disc_desc_param_t; + +/*******************************************************************************************************************//** + * @brief Discovered characteristic information. +***********************************************************************************************************************/ +typedef struct +{ + uint8_t uuid_type; /**< Discovered characteristic UUID type */ + union + { + st_ble_gattc_char_16_evt_t char_16; + st_ble_gattc_char_128_evt_t char_128; + } value; + + uint8_t num_of_descs; + st_disc_desc_param_t *descs; +} st_disc_char_param_t; +/*@}*/ + +/** @defgroup discovery_func Functions + * @{ + * @brief Function definition + */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @fn ble_status_t R_BLE_DISC_Init(void) + * @brief Initialize the GATT services discovery function. + * @return See @ref ble_status_t +***********************************************************************************************************************/ +ble_status_t R_BLE_DISC_Init(void); + +/*******************************************************************************************************************//** + * @fn ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, + * const st_ble_disc_entry_t *p_entries, + * uint8_t num_of_entires, + * ble_disc_comp_cb_t cb + * ) + * @brief Start GATT service discovery. + * @param[in] conn_hdl connection handle + * @param[in] p_entries The information of services to be detected. + * @param[in] num_of_entires The number of services to be detected. + * @param[in] cb The callback function which is called when the service has been detected. + * @return See @ref ble_status_t +***********************************************************************************************************************/ +ble_status_t R_BLE_DISC_Start(uint16_t conn_hdl, const st_ble_disc_entry_t *p_entries, uint8_t num_of_entires, ble_disc_comp_cb_t cb); +/*@}*/ + +#endif /* R_BLE_DISC_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.c new file mode 100644 index 0000000000..978147b065 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.c @@ -0,0 +1,918 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/** + * GATT DATABASE QUICK REFERENCE TABLE: + * Abbreviations used for PROPERTIES: + * BC = Broadcast + * RD = Read + * WW = Write Without Response + * WR = Write + * NT = Notification + * IN = Indication + * RW = Reliable Write + * + * HANDLE | ATT_TYPE | PROPERTIES | ATT_VALUE | DEFINITION + * ============================================================================================ + * GAP Service + * ============================================================================================ + * 0x0001 | 0x28,0x00 | RD | 0x00,0x18 | GAP Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0002 | 0x28,0x03 | RD | 0x0A,0x03,0x00,0x00,0x2A | Device Name characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0003 | 0x00,0x2A | RD,WR | 0x00,0x00,0x00,0x00,0x00,0x00... | Device Name characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0004 | 0x28,0x03 | RD | 0x02,0x05,0x00,0x01,0x2A | Appearance characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0005 | 0x01,0x2A | RD | 0x00,0x00 | Appearance characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0006 | 0x28,0x03 | RD | 0x02,0x07,0x00,0x04,0x2A | Peripheral Preferred Connection Parameters characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0007 | 0x04,0x2A | RD | 0x00,0x00,0x00,0x00,0x00,0x00... | Peripheral Preferred Connection Parameters characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0008 | 0x28,0x03 | RD | 0x02,0x09,0x00,0xA6,0x2A | Central Address Resolution characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0009 | 0xA6,0x2A | RD | 0x00 | Central Address Resolution characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000A | 0x28,0x03 | RD | 0x02,0x0B,0x00,0xC9,0x2A | Resolvable Private Address Only characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000B | 0xC9,0x2A | RD | 0x00 | Resolvable Private Address Only characteristic value + * ============================================================================================ + * GATT Service + * ============================================================================================ + * 0x000C | 0x28,0x00 | RD | 0x01,0x18 | GATT Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000D | 0x28,0x03 | RD | 0x20,0x0E,0x00,0x05,0x2A | Service Changed characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000E | 0x05,0x2A | IN | 0x00,0x00,0x00,0x00 | Service Changed characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x000F | 0x02,0x29 | RD,WR | 0x00,0x00 | Client Characteristic Configuration descriptor + * ============================================================================================ + * LED Switch Service + * ============================================================================================ + * 0x0010 | 0x28,0x00 | RD | 0xE0,0xFC,0x8E,0x8E,0x96,0xB4... | LED Switch Service Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0011 | 0x28,0x03 | RD | 0x10,0x12,0x00,0xE0,0xFC,0x8E... | Switch State characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0012 | 0xE0,0xFC,0x8E... | NT | 0x00 | Switch State characteristic value + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0013 | 0x02,0x29 | RD,WR | 0x00,0x00 | Client Characteristic Configuration descriptor + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0014 | 0x28,0x03 | RD | 0x0A,0x15,0x00,0xE0,0xFC,0x8E... | LED Blink Rate characteristic Declaration + * -------+-------------------+-------------+----------------------------------+--------------- + * 0x0015 | 0xE0,0xFC,0x8E... | RD,WR | 0x00 | LED Blink Rate characteristic value + * ============================================================================================ + + */ + +/******************************************************************************* +* Includes , "Project Includes" +*******************************************************************************/ +#include +#include "gatt_db.h" + +/***************************************************************************** +* Global definition +******************************************************************************/ +static const uint8_t gs_gatt_const_uuid_arr[] = +{ + /* Primary Service Declaration : 0 */ + 0x00, 0x28, + + /* Secondary Service Declaration : 2 */ + 0x01, 0x28, + + /* Included Service Declaration : 4 */ + 0x02, 0x28, + + /* Characteristic Declaration : 6 */ + 0x03, 0x28, + + /* GAP Service : 8 */ + 0x00, 0x18, + + /* Device Name : 10 */ + 0x00, 0x2A, + + /* Appearance : 12 */ + 0x01, 0x2A, + + /* Peripheral Preferred Connection Parameters : 14 */ + 0x04, 0x2A, + + /* Central Address Resolution : 16 */ + 0xA6, 0x2A, + + /* Resolvable Private Address Only : 18 */ + 0xC9, 0x2A, + + /* GATT Service : 20 */ + 0x01, 0x18, + + /* Service Changed : 22 */ + 0x05, 0x2A, + + /* Client Characteristic Configuration : 24 */ + 0x02, 0x29, + + /* LED Switch Service : 26 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x26, 0x19, 0x83, 0x58, + + /* Switch State : 42 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x57, 0x7F, 0x83, 0x58, + + /* LED Blink Rate : 58 */ + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x2F, 0xC3, 0x83, 0x58, + +}; + +static uint8_t gs_gatt_value_arr[] = +{ + /* Device Name */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Appearance */ + 0x00, 0x00, + + /* Peripheral Preferred Connection Parameters */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Central Address Resolution */ + 0x00, + + /* Resolvable Private Address Only */ + 0x00, + + /* LED Blink Rate */ + 0x00, + +}; + +static const uint8_t gs_gatt_const_value_arr[] = +{ + /* Device Name */ + 0x0A, // Properties + 0x03, 0x00, // Attr Handle + 0x00, 0x2A, // UUID + + /* Appearance */ + 0x02, // Properties + 0x05, 0x00, // Attr Handle + 0x01, 0x2A, // UUID + + /* Peripheral Preferred Connection Parameters */ + 0x02, // Properties + 0x07, 0x00, // Attr Handle + 0x04, 0x2A, // UUID + + /* Central Address Resolution */ + 0x02, // Properties + 0x09, 0x00, // Attr Handle + 0xA6, 0x2A, // UUID + + /* Resolvable Private Address Only */ + 0x02, // Properties + 0x0B, 0x00, // Attr Handle + 0xC9, 0x2A, // UUID + + /* Service Changed */ + 0x20, // Properties + 0x0E, 0x00, // Attr Handle + 0x05, 0x2A, // UUID + + /* Switch State */ + 0x10, // Properties + 0x12, 0x00, // Attr Handle + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x57, 0x7F, 0x83, 0x58, // UUID + + /* LED Blink Rate */ + 0x0A, // Properties + 0x15, 0x00, // Attr Handle + 0xE0, 0xFC, 0x8E, 0x8E, 0x96, 0xB4, 0x01, 0xAB, 0x67, 0x42, 0x05, 0x5F, 0x2F, 0xC3, 0x83, 0x58, // UUID + +}; + +static uint8_t gs_gatt_db_peer_specific_val_arr[4*8]; + +static const uint8_t gs_gatt_db_const_peer_specific_val_arr[] = +{ + /* Service Changed : Client Characteristic Configuration */ + 0x00, 0x00, + + /* Switch State : Client Characteristic Configuration */ + 0x00, 0x00, + +}; + +static const st_ble_gatts_db_uuid_cfg_t gs_gatt_type_table[] = +{ + /* 0 : Primary Service Declaration */ + { + /* UUID Offset */ + 0, + /* First Occurrence for Type */ + 0x0001, + /* Last Occurrence for Type */ + 0x0010, + }, + + /* 1 : GAP Service */ + { + /* UUID Offset */ + 8, + /* First Occurrence for Type */ + 0x0001, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 2 : Characteristic Declaration */ + { + /* UUID Offset */ + 6, + /* First Occurrence for Type */ + 0x0002, + /* Last Occurrence for Type */ + 0x0014, + }, + + /* 3 : Device Name */ + { + /* UUID Offset */ + 10, + /* First Occurrence for Type */ + 0x0003, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 4 : Appearance */ + { + /* UUID Offset */ + 12, + /* First Occurrence for Type */ + 0x0005, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 5 : Peripheral Preferred Connection Parameters */ + { + /* UUID Offset */ + 14, + /* First Occurrence for Type */ + 0x0007, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 6 : Central Address Resolution */ + { + /* UUID Offset */ + 16, + /* First Occurrence for Type */ + 0x0009, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 7 : Resolvable Private Address Only */ + { + /* UUID Offset */ + 18, + /* First Occurrence for Type */ + 0x000B, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 8 : GATT Service */ + { + /* UUID Offset */ + 20, + /* First Occurrence for Type */ + 0x000C, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 9 : Service Changed */ + { + /* UUID Offset */ + 22, + /* First Occurrence for Type */ + 0x000E, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 10 : Client Characteristic Configuration */ + { + /* UUID Offset */ + 24, + /* First Occurrence for Type */ + 0x000F, + /* Last Occurrence for Type */ + 0x0013, + }, + + /* 11 : LED Switch Service */ + { + /* UUID Offset */ + 26, + /* First Occurrence for Type */ + 0x0010, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 12 : Switch State */ + { + /* UUID Offset */ + 42, + /* First Occurrence for Type */ + 0x0012, + /* Last Occurrence for Type */ + 0x0000, + }, + + /* 13 : LED Blink Rate */ + { + /* UUID Offset */ + 58, + /* First Occurrence for Type */ + 0x0015, + /* Last Occurrence for Type */ + 0x0000, + }, + +}; + +static const st_ble_gatts_db_attr_cfg_t gs_gatt_db_attr_table[] = +{ + /* Handle : 0x0000 */ + /* Blank */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_NO_AUXILIARY_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0001, + /* UUID Offset */ + 0, + /* Value */ + NULL, + }, + + /* Handle : 0x0001 */ + /* GAP Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x000C, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 8), + }, + + /* Handle : 0x0002 */ + /* Device Name : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0004, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 0), + }, + + /* Handle : 0x0003 */ + /* Device Name */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 128, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 10, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 0), + }, + + /* Handle : 0x0004 */ + /* Appearance : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0006, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 5), + }, + + /* Handle : 0x0005 */ + /* Appearance */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 12, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 128), + }, + + /* Handle : 0x0006 */ + /* Peripheral Preferred Connection Parameters : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0008, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 10), + }, + + /* Handle : 0x0007 */ + /* Peripheral Preferred Connection Parameters */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 8, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 14, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 130), + }, + + /* Handle : 0x0008 */ + /* Central Address Resolution : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x000A, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 15), + }, + + /* Handle : 0x0009 */ + /* Central Address Resolution */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 16, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 138), + }, + + /* Handle : 0x000A */ + /* Resolvable Private Address Only : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x000D, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 20), + }, + + /* Handle : 0x000B */ + /* Resolvable Private Address Only */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 18, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 139), + }, + + /* Handle : 0x000C */ + /* GATT Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0010, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 20), + }, + + /* Handle : 0x000D */ + /* Service Changed : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 5, + /* Next Attribute Type Index */ + 0x0011, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 25), + }, + + /* Handle : 0x000E */ + /* Service Changed */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 4, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 22, + /* Value */ + (NULL), + }, + + /* Handle : 0x000F */ + /* Service Changed : Client Characteristic Configuration */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0013, + /* UUID Offset */ + 24, + /* Value */ + (uint8_t *)(gs_gatt_db_peer_specific_val_arr + 0), + }, + + /* Handle : 0x0010 */ + /* LED Switch Service : Primary Service Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_SER_NO_SECURITY_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 16, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 0, + /* Value */ + (uint8_t *)(gs_gatt_const_uuid_arr + 26), + }, + + /* Handle : 0x0011 */ + /* Switch State : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 19, + /* Next Attribute Type Index */ + 0x0014, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 30), + }, + + /* Handle : 0x0012 */ + /* Switch State */ + { + /* Properties */ + 0, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 42, + /* Value */ + (NULL), + }, + + /* Handle : 0x0013 */ + /* Switch State : Client Characteristic Configuration */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY, + /* Value Size */ + 2, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 24, + /* Value */ + (uint8_t *)(gs_gatt_db_peer_specific_val_arr + 2), + }, + + /* Handle : 0x0014 */ + /* LED Blink Rate : Characteristic Declaration */ + { + /* Properties */ + BLE_GATT_DB_READ, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY, + /* Value Size */ + 19, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 6, + /* Value */ + (uint8_t *)(gs_gatt_const_value_arr + 49), + }, + + /* Handle : 0x0015 */ + /* LED Blink Rate */ + { + /* Properties */ + BLE_GATT_DB_READ | BLE_GATT_DB_WRITE, + /* Auxiliary Properties */ + BLE_GATT_DB_FIXED_LENGTH_PROPERTY | BLE_GATT_DB_128_BIT_UUID_FORMAT, + /* Value Size */ + 1, + /* Next Attribute Type Index */ + 0x0000, + /* UUID Offset */ + 58, + /* Value */ + (uint8_t *)(gs_gatt_value_arr + 140), + }, + +}; + +static const st_ble_gatts_db_char_cfg_t gs_gatt_characteristic[] = +{ + /* 0 : Device Name */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0002, + /* Service Index */ + 0, + }, + + /* 1 : Appearance */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0004, + /* Service Index */ + 0, + }, + + /* 2 : Peripheral Preferred Connection Parameters */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0006, + /* Service Index */ + 0, + }, + + /* 3 : Central Address Resolution */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0008, + /* Service Index */ + 0, + }, + + /* 4 : Resolvable Private Address Only */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x000A, + /* Service Index */ + 0, + }, + + /* 5 : Service Changed */ + { + /* Number of Attributes */ + { + 3, + }, + /* Start Handle */ + 0x000D, + /* Service Index */ + 1, + }, + + /* 6 : Switch State */ + { + /* Number of Attributes */ + { + 3, + }, + /* Start Handle */ + 0x0011, + /* Service Index */ + 2, + }, + + /* 7 : LED Blink Rate */ + { + /* Number of Attributes */ + { + 2, + }, + /* Start Handle */ + 0x0014, + /* Service Index */ + 2, + }, + +}; + +static const st_ble_gatts_db_serv_cfg_t gs_gatt_service[] = +{ + /* GAP Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x0001, + /* Service End Handle */ + 0x000B, + /* Characteristic Start Index */ + 0, + /* Characteristic End Index */ + 4, + }, + + /* GATT Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x000C, + /* Service End Handle */ + 0x000F, + /* Characteristic Start Index */ + 5, + /* Characteristic End Index */ + 5, + }, + + /* LED Switch Service */ + { + /* Num of Services */ + { + 1, + }, + /* Description */ + 0, + /* Service Start Handle */ + 0x0010, + /* Service End Handle */ + 0x0015, + /* Characteristic Start Index */ + 6, + /* Characteristic End Index */ + 7, + }, + +}; + +st_ble_gatts_db_cfg_t g_gatt_db_table = +{ + gs_gatt_const_uuid_arr, + gs_gatt_value_arr, + gs_gatt_const_value_arr, + gs_gatt_db_peer_specific_val_arr, + gs_gatt_db_const_peer_specific_val_arr, + gs_gatt_type_table, + gs_gatt_db_attr_table, + gs_gatt_characteristic, + gs_gatt_service, + ARRAY_SIZE(gs_gatt_service), + ARRAY_SIZE(gs_gatt_characteristic), + ARRAY_SIZE(gs_gatt_type_table), + ARRAY_SIZE(gs_gatt_db_const_peer_specific_val_arr), +}; \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.h new file mode 100644 index 0000000000..8fa92f9a9a --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/gatt_db.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef GATT_DB_H +#define GATT_DB_H + +#include "profile_cmn/r_ble_serv_common.h" + +extern st_ble_gatts_db_cfg_t g_gatt_db_table; + +typedef enum +{ + BLE_INVALID_ATTR_HDL = 0x0000, + BLE_GAPS_DECL_HDL = 0x0001, + BLE_GAPS_DEV_NAME_DECL_HDL = 0x0002, + BLE_GAPS_DEV_NAME_VAL_HDL = 0x0003, + BLE_GAPS_APPEARANCE_DECL_HDL = 0x0004, + BLE_GAPS_APPEARANCE_VAL_HDL = 0x0005, + BLE_GAPS_PER_PREF_CONN_PARAM_DECL_HDL = 0x0006, + BLE_GAPS_PER_PREF_CONN_PARAM_VAL_HDL = 0x0007, + BLE_GAPS_CENT_ADDR_RSLV_DECL_HDL = 0x0008, + BLE_GAPS_CENT_ADDR_RSLV_VAL_HDL = 0x0009, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_DECL_HDL = 0x000A, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_VAL_HDL = 0x000B, + BLE_GATS_DECL_HDL = 0x000C, + BLE_GATS_SERV_CHGED_DECL_HDL = 0x000D, + BLE_GATS_SERV_CHGED_VAL_HDL = 0x000E, + BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL = 0x000F, + BLE_LSS_DECL_HDL = 0x0010, + BLE_LSS_SWITCH_STATE_DECL_HDL = 0x0011, + BLE_LSS_SWITCH_STATE_VAL_HDL = 0x0012, + BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL = 0x0013, + BLE_LSS_BLINK_RATE_DECL_HDL = 0x0014, + BLE_LSS_BLINK_RATE_VAL_HDL = 0x0015, +} e_ble_attr_hdl_t; + +#define BLE_GAPS_DEV_NAME_LEN (128) +#define BLE_GAPS_APPEARANCE_LEN (2) +#define BLE_GAPS_PER_PREF_CONN_PARAM_LEN (8) +#define BLE_GAPS_CENT_ADDR_RSLV_LEN (1) +#define BLE_GAPS_RSLV_PRIV_ADDR_ONLY_LEN (1) +#define BLE_GATS_SERV_CHGED_LEN (4) +#define BLE_GATS_SERV_CHGED_CLI_CNFG_LEN (2) +#define BLE_LSS_SWITCH_STATE_LEN (1) +#define BLE_LSS_SWITCH_STATE_CLI_CNFG_LEN (2) +#define BLE_LSS_BLINK_RATE_LEN (1) + +#endif /* GATT_DB_H */ \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h new file mode 100644 index 0000000000..44259dc968 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_profile_cmn.h @@ -0,0 +1,252 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +#ifndef R_BLE_PROFILE_CMN_H +#define R_BLE_PROFILE_CMN_H + +#ifdef ENABLE_PROFILE_UT_TEST +#define UT_MOCK(name) __mock_ ## name +#else +#define UT_MOCK(name) name +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array)\ + (sizeof(array) / sizeof(array[0])) +#endif + +/** + * Packing Macros. + * + * Syntax: BT_PACK___BYTE + * + * Usage: Based on the endian-ness defined for each protocol/profile layer, + * appropriate packing macros to be used by each layer. + * + * Example: HCI is defined as little endian protocol, + * so if HCI defines HCI_PACK_2_BYTE for packing a parameter of size 2 byte, + * that shall be mapped to BT_PACK_LE_2_BYTE + * + * By default both the packing and unpaking macros uses pointer to + * a single or multi-octet variable which to be packed to or unpacked from + * a buffer (unsinged character array). + * + * For the packing macro, another variation is available, + * where the single or multi-octet variable itself is used (not its pointer). + * + * Syntax: BT_PACK___BYTE_VAL + */ +/* Little Endian Packing Macros */ +#ifndef BT_PACK_LE_1_BYTE +#define BT_PACK_LE_1_BYTE(dst, src) \ + { \ + uint8_t val; \ + val = (uint8_t)(*(src)); \ + BT_PACK_LE_1_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_1_BYTE_VAL +#define BT_PACK_LE_1_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (src); +#endif + +#ifndef BT_PACK_LE_2_BYTE +#define BT_PACK_LE_2_BYTE(dst, src) \ + { \ + uint16_t val; \ + val = (uint16_t)(*(src)); \ + BT_PACK_LE_2_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_2_BYTE_VAL +#define BT_PACK_LE_2_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src); \ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8); +#endif + +#ifndef BT_PACK_LE_3_BYTE +#define BT_PACK_LE_3_BYTE(dst, src) \ + { \ + uint32_t val; \ + val = (uint32_t)(*(src)); \ + BT_PACK_LE_3_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_3_BYTE_VAL +#define BT_PACK_LE_3_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src);\ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8);\ + *((uint8_t *)(dst) + 2) = (uint8_t)((src) >> 16); +#endif + +#ifndef BT_PACK_LE_4_BYTE +#define BT_PACK_LE_4_BYTE(dst, src) \ + { \ + uint32_t val; \ + val = (uint32_t)(*(src)); \ + BT_PACK_LE_4_BYTE_VAL((dst), val); \ + } +#endif + +#ifndef BT_PACK_LE_4_BYTE_VAL +#define BT_PACK_LE_4_BYTE_VAL(dst, src) \ + *((uint8_t *)(dst) + 0) = (uint8_t)(src);\ + *((uint8_t *)(dst) + 1) = (uint8_t)((src) >> 8);\ + *((uint8_t *)(dst) + 2) = (uint8_t)((src) >> 16);\ + *((uint8_t *)(dst) + 3) = (uint8_t)((src) >> 24); + +/* Update based on 64 Bit, 128 Bit Data Types */ +#endif + +#ifndef BT_PACK_LE_8_BYTE +#define BT_PACK_LE_8_BYTE(dst,val)\ + memcpy ((dst), (val), 8) +#endif + +#ifndef BT_PACK_LE_16_BYTE +#define BT_PACK_LE_16_BYTE(dst,val)\ + memcpy ((dst), (val), 16) +#endif + +#ifndef BT_PACK_LE_N_BYTE +#define BT_PACK_LE_N_BYTE(dst,val,n)\ + memcpy ((dst), (val), (n)) +#endif + +/** + * Unpacking Macros. + * + * Syntax: BT_UNPACK___BYTE + * + * Usage: Based on the endian-ness defined for each protocol/profile layer, + * appropriate unpacking macros to be used by each layer. + * + * Example: HCI is defined as little endian protocol, + * so if HCI defines HCI_UNPACK_4_BYTE for unpacking a parameter of size 4 byte, + * that shall be mapped to BT_UNPACK_LE_4_BYTE + */ +/* Little Endian Unpacking Macros */ +#ifndef BT_UNPACK_LE_1_BYTE +#define BT_UNPACK_LE_1_BYTE(dst,src)\ + *((uint8_t *)(dst)) = (uint8_t)(*((uint8_t *)(src))); +#endif + +#ifndef BT_UNPACK_LE_2_BYTE +#define BT_UNPACK_LE_2_BYTE(dst,src)\ + *((uint16_t *)(dst)) = (uint16_t)( \ + (((uint16_t)(*((src) + 0))) << 0) | \ + (((uint16_t)(*((src) + 1))) << 8) \ + ); +#endif + +#ifndef BT_UNPACK_LE_3_BYTE +#define BT_UNPACK_LE_3_BYTE(dst,src)\ + *((uint32_t *)(dst)) = (uint32_t)( \ + (((uint32_t)(*((src) + 0))) << 0) | \ + (((uint32_t)(*((src) + 1))) << 8) | \ + (((uint32_t)(*((src) + 2))) << 16) \ + ); +#endif + +#ifndef BT_UNPACK_LE_4_BYTE +#define BT_UNPACK_LE_4_BYTE(dst,src)\ + *((uint32_t *)(dst)) = (uint32_t)( \ + (((uint32_t)(*((src) + 0))) << 0) | \ + (((uint32_t)(*((src) + 1))) << 8) | \ + (((uint32_t)(*((src) + 2))) << 16) | \ + (((uint32_t)(*((src) + 3))) << 24) \ + ); +#endif + +/* Update based on 64 Bit, 128 Bit Data Types */ +#ifndef BT_UNPACK_LE_8_BYTE +#define BT_UNPACK_LE_8_BYTE(dst,src)\ + memcpy ((dst), (src), 8) +#endif + +#ifndef BT_UNPACK_LE_16_BYTE +#define BT_UNPACK_LE_16_BYTE(dst,src)\ + memcpy ((dst), (src), 16) +#endif + +#ifndef BT_UNPACK_LE_N_BYTE +#define BT_UNPACK_LE_N_BYTE(dst,src,n)\ + memcpy ((dst), (src), (n)) +#endif + +#ifndef MAX +#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +#endif + +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn Profile Common Library + * @{ + * @ingroup app_lib + * @brief Profile Common Library + * @details This library provides APIs to encode/decode default type and data types. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +/** @defgroup profile_cmn_struct Structures + * @{ + * @brief Structure definition + */ +/*******************************************************************************************************************//** + * @brief IEEE 11073 FLOAT type. +***********************************************************************************************************************/ +typedef struct { + int8_t exponent; /**< 8-bit exponent to base 10 */ + int32_t mantissa; /**< 24-bit mantissa */ +} st_ble_ieee11073_float_t; + +/*******************************************************************************************************************//** + * @brief IEEE 11073 short FLOAT type. +***********************************************************************************************************************/ +typedef struct { + int8_t exponent; /**< 4-bit exponent to base 10 */ + int16_t mantissa; /**< 12-bit mantissa */ +} st_ble_ieee11073_sfloat_t; + +/*******************************************************************************************************************//** + * @brief Date Time characteristic parameters. +***********************************************************************************************************************/ +typedef struct { + uint16_t year; /**< Year */ + uint8_t month; /**< Month */ + uint8_t day; /**< Day */ + uint8_t hours; /**< Hours */ + uint8_t minutes; /**< Minutes */ + uint8_t seconds; /**< Seconds */ +} st_ble_date_time_t; +/*@}*/ + +#endif /* R_BLE_PROFILE_CMN_H */ +/*@}*/ \ No newline at end of file diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c new file mode 100644 index 0000000000..0fc6e5ba25 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.c @@ -0,0 +1,267 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include + +#include "r_ble_serv_common.h" + +ble_status_t decode_8bit(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint8_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = p_gatt_value->p_value[0]; + + return BLE_SUCCESS; +} + +ble_status_t encode_8bit(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint8_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = *p_app_value; + + return BLE_SUCCESS; +} + +ble_status_t decode_16bit(uint16_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint16_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint16_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8)); + + return BLE_SUCCESS; +} + +ble_status_t encode_16bit(const uint16_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint16_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = (uint8_t)((*p_app_value) & 0xFF); + p_gatt_value->p_value[1] = (uint8_t)(((*p_app_value) >> 8) & 0xFF); + + return BLE_SUCCESS; +} + +ble_status_t decode_24bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != 3) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint32_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8) | + (p_gatt_value->p_value[2] << 16)); + + return BLE_SUCCESS; +} + +ble_status_t decode_32bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len != sizeof(uint32_t)) + { + return BLE_ERR_INVALID_DATA; + } + + *p_app_value = (uint32_t)((p_gatt_value->p_value[0]) | (p_gatt_value->p_value[1] << 8) | + (p_gatt_value->p_value[2] << 16) | (p_gatt_value->p_value[3] << 24)); + + return BLE_SUCCESS; +} + +ble_status_t encode_24bit(const uint32_t * p_app_value, st_ble_gatt_value_t * p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < 3) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = *p_app_value & 0xFF; + p_gatt_value->p_value[1] = (*p_app_value >> 8) & 0xFF; + p_gatt_value->p_value[2] = (*p_app_value >> 16) & 0xFF; + p_gatt_value->value_len = 3; + + return BLE_SUCCESS; +} + +ble_status_t encode_32bit(const uint32_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + if (p_gatt_value->value_len < sizeof(uint32_t)) + { + return BLE_ERR_INVALID_DATA; + } + + p_gatt_value->p_value[0] = (uint8_t)(*p_app_value & 0xFF); + p_gatt_value->p_value[1] = (uint8_t)((*p_app_value >> 8) & 0xFF); + p_gatt_value->p_value[2] = (uint8_t)((*p_app_value >> 16) & 0xFF); + p_gatt_value->p_value[3] = (uint8_t)((*p_app_value >> 24) & 0xFF); + + return BLE_SUCCESS; +} + +ble_status_t decode_allcopy(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + memcpy(p_app_value, p_gatt_value->p_value, p_gatt_value->value_len); + + return BLE_SUCCESS; +} + +ble_status_t encode_allcopy(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if ((NULL == p_app_value) || (NULL == p_gatt_value)) + { + return BLE_ERR_INVALID_PTR; + } + + memcpy(p_gatt_value->p_value, p_app_value, p_gatt_value->value_len); + + return BLE_SUCCESS; + +} + +ble_status_t decode_st_ble_seq_data_t(st_ble_seq_data_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + p_app_value->data = p_gatt_value->p_value; + p_app_value->len = p_gatt_value->value_len; + return BLE_SUCCESS; +} + +ble_status_t encode_st_ble_seq_data_t(const st_ble_seq_data_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (p_app_value->len > p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memcpy(p_gatt_value->p_value, p_app_value->data, p_app_value->len); + + /* for characteristic size */ + p_gatt_value->value_len = p_app_value->len; + + return BLE_SUCCESS; +} + +uint8_t pack_st_ble_ieee11073_sfloat_t(uint8_t *p_dst, const st_ble_ieee11073_sfloat_t *p_src) +{ + uint8_t pos = 0; + uint16_t sfloat = (uint16_t)((p_src->mantissa & 0x0FFF) | (p_src->exponent << 12)); + + p_dst[pos++] = (uint8_t)(sfloat & 0xFF); + p_dst[pos++] = (uint8_t)((sfloat >> 8) & 0xFF); + + return pos; +} + +uint8_t unpack_st_ble_ieee11073_sfloat_t(st_ble_ieee11073_sfloat_t *p_dst, const uint8_t *p_src) +{ + p_dst->mantissa = (int16_t)(p_src[0] | ((p_src[1] & 0x0F) << 8)); + p_dst->exponent = (int8_t)(p_src[1] >> 4); + + if (p_dst->exponent & 0x08) + { + p_dst->exponent = (int8_t)(p_dst->exponent | 0xF0); + } + + return 2; +} + +uint8_t pack_st_ble_date_time_t(uint8_t *p_dst, const st_ble_date_time_t *p_src) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_dst[pos], &p_src->year); + pos += 2; + p_dst[pos++] = p_src->month; + p_dst[pos++] = p_src->day; + p_dst[pos++] = p_src->hours; + p_dst[pos++] = p_src->minutes; + p_dst[pos++] = p_src->seconds; + + return (uint8_t)pos; +} + +uint8_t unpack_st_ble_date_time_t(st_ble_date_time_t *p_dst, const uint8_t *p_src) +{ + uint32_t pos = 0; + + BT_UNPACK_LE_2_BYTE(&p_dst->year, &p_src[pos]); + pos += 2; + p_dst->month = p_src[pos++]; + p_dst->day = p_src[pos++]; + p_dst->hours = p_src[pos++]; + p_dst->minutes = p_src[pos++]; + p_dst->seconds = p_src[pos++]; + + return (uint8_t)pos; +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h new file mode 100644 index 0000000000..ffff3fe868 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_serv_common.h @@ -0,0 +1,329 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn Profile Common Library + * @{ + * @ingroup app_lib + * @brief Profile Common Library + * @details This library provides APIs to encode/decode default type and data types. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +#ifndef R_BLE_SERV_COMMON_H +#define R_BLE_SERV_COMMON_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#include "r_ble_rx23w_if.h" +#else +/*RA4W*/ +#include "r_ble_api.h" +#include "rm_ble_abs.h" +#endif + +#include "r_ble_profile_cmn.h" + +/** @defgroup profile_cmn_macro Macros + * @{ + * @brief Macro definition + */ +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** + * @def BLE_PRF_MAX_NUM_OF_SERVS + * @brief Maximum Number of Services. + */ +#define BLE_PRF_MAX_NUM_OF_SERVS (10) + +/** + * @def BLE_SERV_CLI_CNFG_LEN + * @brief Length of Client Characteristic Configuration descriptor. + */ +#define BLE_SERV_CLI_CNFG_LEN (2) + +/** + * @def BLE_SERV_SER_CNFG_LEN + * @brief Length of Server Characteristic Configuration descriptor. + */ +#define BLE_SERV_SER_CNFG_LEN (2) + +/** + * @def BLE_SERV_CLI_CNFG_UUID + * @brief UUID of Client Characteristic Configuration descriptor. + */ +#define BLE_SERV_CLI_CNFG_UUID (0x2902) + +/** + * @def BLE_SERV_SER_CNFG_UUID + * @brief UUID of Server Characteristic Configuration descriptor. + */ +#define BLE_SERV_SER_CNFG_UUID (0x2903) + +#if defined(__CCRX__) || defined(__ICCRX__) +/*RX23W*/ +#define BLE_PRF_MTU_SIZE (BLE_CFG_GATT_MTU_SIZE) +#define BLE_PRF_CONN_MAX (BLE_CFG_RF_CONN_MAX) +#else +/*RA4W*/ +#define BLE_PRF_MTU_SIZE (BLE_ABS_CFG_GATT_MTU_SIZE) +#define BLE_PRF_CONN_MAX (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) +#endif +/*@}*/ + +/** @defgroup profile_cmn_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_seq_data_t + * @brief st_ble_seq_data_t is value field for variable length. + **********************************************************************************************************************/ +typedef struct { + /** + * @brief Data value. + */ + uint8_t *data; + /** + * @brief Data length. + */ + uint16_t len; +} st_ble_seq_data_t; +/*@}*/ + +/** @defgroup profile_cmn_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Decode data value for 8bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_8bit(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 8bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_8bit(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 16bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_16bit(uint16_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 16bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_16bit(const uint16_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 32bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_32bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 32bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_32bit(const uint32_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 24bit. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_24bit(uint32_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 24bit. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_24bit(const uint32_t * p_app_value, st_ble_gatt_value_t * p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for 8bit array. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_allcopy(uint8_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for 8bit array. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_allcopy(const uint8_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Decode data value for value type st_ble_seq_data_t. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t decode_st_ble_seq_data_t(st_ble_seq_data_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Encode data value for value type st_ble_seq_data_t. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value and length of characteristic or descriptor. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t encode_st_ble_seq_data_t(const st_ble_seq_data_t *p_app_value, st_ble_gatt_value_t *p_gatt_value); + +/******************************************************************************************************************//** + * @brief Pack value type of st_ble_ieee11073_sfloat_t to GATT DB. + * @param[out] p_dst GATT database value of characteristic or descriptor. + * @param[in] p_src Application value field which is st_ble_ieee11073_sfloat_t type. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t pack_st_ble_ieee11073_sfloat_t(uint8_t *p_dst, const st_ble_ieee11073_sfloat_t *p_src); + +/******************************************************************************************************************//** + * @brief Unpack value type of st_ble_ieee11073_sfloat_t from GATT DB. + * @param[out] p_dst Application value field which is st_ble_ieee11073_sfloat_t type. + * @param[in] p_src GATT database value of characteristic or descriptor. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t unpack_st_ble_ieee11073_sfloat_t(st_ble_ieee11073_sfloat_t *p_dst, const uint8_t *p_src); + +/******************************************************************************************************************//** + * @brief Pack value type of st_ble_date_time_t to GATT DB. + * @param[out] p_dst GATT database value of characteristic or descriptor. + * @param[in] p_src Application value field which is st_ble_date_time_t type. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t pack_st_ble_date_time_t(uint8_t *p_dst, const st_ble_date_time_t *p_src); + +/******************************************************************************************************************//** + * @brief Unpack value type of st_ble_date_time_t from GATT DB. + * @param[out] p_dst Application value field which is st_ble_date_time_t type. + * @param[in] p_src GATT database value of characteristic or descriptor. + * @return Position of Pointer. + **********************************************************************************************************************/ +uint8_t unpack_st_ble_date_time_t(st_ble_date_time_t *p_dst, const uint8_t *p_src); +/*@}*/ + +/** @defgroup profile_cmn_macro Macros + * @{ + * @brief Macro definition + */ +/** + * @def decode_uint8_t + * @brief Function macro for decoding uint8_t + */ +#define decode_uint8_t decode_8bit + +/** + * @def encode_uint8_t + * @brief Function macro for encoding uint8_t + */ +#define encode_uint8_t encode_8bit + +/** + * @def decode_int8_t + * @brief Function macro for decoding int8_t + */ +#define decode_int8_t decode_8bit + +/** + * @def encode_int8_t + * @brief Function macro for encoding int8_t + */ +#define encode_int8_t encode_8bit + +/** + * @def decode_uint16_t + * @brief Function macro for decoding uint16_t + */ +#define decode_uint16_t decode_16bit + +/** + * @def encode_uint16_t + * @brief Function macro for encoding uint16_t + */ +#define encode_uint16_t encode_16bit + +/** + * @def decode_int16_t + * @brief Function macro for decoding int16_t + */ +#define decode_int16_t decode_16bit + +/** + * @def encode_int16_t + * @brief Function macro for encoding int16_t + */ +#define encode_int16_t encode_16bit + +/** + * @def decode_uint32_t + * @brief Function macro for decoding uint32_t + */ +#define decode_uint32_t decode_32bit + +/** + * @def encode_uint32_t + * @brief Function macro for encoding uint32_t + */ +#define encode_uint32_t encode_32bit + +/** + * @def decode_int32_t + * @brief Function macro for decoding int32_t + */ +#define decode_int32_t decode_32bit + +/** + * @def encode_int32_t + * @brief Function macro for encoding int32_t + */ +#define encode_int32_t encode_32bit +/*@}*/ + +#endif /* R_BLE_SERV_COMMON_H */ +/*@}*/ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c new file mode 100644 index 0000000000..1937ffaf2a --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.c @@ -0,0 +1,1102 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include +#include "r_ble_servc_if.h" +#include "discovery/r_ble_disc.h" + +typedef struct { + st_ble_dev_addr_t bd_addr; + uint16_t conn_hdl; + uint8_t conn_idx; + + /* Used for Long Read */ + uint16_t read_attr_hdl; + uint8_t *p_read_buf; + uint16_t read_buf_pos; + + /* Used for Long Write */ + uint16_t write_attr_hdl; +} st_ble_conn_info_t; + +static st_ble_conn_info_t gs_conn_info[BLE_SERVC_MAX_NUM_OF_SAVED]; +static const st_ble_servc_info_t *gs_clients[BLE_SERVC_MAX_NUM_OF_CLIENTS]; +static uint8_t gs_num_of_clients; + +static uint8_t find_conn_idx_from_bd_addr(const st_ble_dev_addr_t *p_addr) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if ((gs_conn_info[i].bd_addr.type == p_addr->type) && + (0 == memcmp(gs_conn_info[i].bd_addr.addr, p_addr->addr, BLE_BD_ADDR_LEN))) + { + return i; + } + } + + return 0xFF; +} + +static uint8_t find_conn_idx_from_conn_hdl(uint16_t conn_hdl) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if (gs_conn_info[i].conn_hdl == conn_hdl) + { + return i; + } + } + + return 0xFF; +} + +static void set_conn_idx(uint16_t conn_hdl, const st_ble_dev_addr_t *p_addr) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + /* If we already have the peer attr hdls, use it. */ + if ((gs_conn_info[i].bd_addr.type == p_addr->type) && + (0 == memcmp(gs_conn_info[i].bd_addr.addr, p_addr->addr, BLE_BD_ADDR_LEN))) + { + gs_conn_info[i].conn_hdl = conn_hdl; + return; + } + } + + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + if (BLE_GAP_INVALID_CONN_HDL == gs_conn_info[i].conn_hdl) + { + memcpy(&gs_conn_info[i].bd_addr, p_addr, sizeof(gs_conn_info[i].bd_addr)); + gs_conn_info[i].conn_hdl = conn_hdl; + break; + } + } +} + +static void clear_conn_idx(uint16_t conn_hdl) +{ + uint8_t conn_idx; + + conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + if (0xFF != conn_idx) + { + gs_conn_info[conn_idx].conn_hdl = BLE_GAP_INVALID_CONN_HDL; + } +} + +static void find_attr(uint8_t conn_idx, + uint16_t attr_hdl, + const st_ble_servc_info_t **pp_client, + const st_ble_servc_char_info_t **pp_char) +{ + for (uint8_t s = 0; s < gs_num_of_clients; s++) + { + for (uint8_t c = 0; c < gs_clients[s]->num_of_chars; c++) + { + if ((gs_clients[s]->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl <= attr_hdl) && + (gs_clients[s]->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl >= attr_hdl)) + { + *pp_client = gs_clients[s]; + *pp_char = gs_clients[s]->pp_chars[c]; + } + } + } +} + +static void read_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t *p_value, ble_status_t result) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + /* Characteristic */ + if (attr_hdl == p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (BLE_SUCCESS == result) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + ret = p_attr->decode(p_app_value, p_value); + + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, conn_hdl, ret, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + else + { + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + } + /* Descriptor */ + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (attr_hdl == p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (BLE_SUCCESS == result) + { + ble_status_t ret; + uint8_t *p_app_value; + + p_app_value = malloc(p_attr->pp_descs[d]->app_size); + memset(p_app_value, 0x00, p_attr->pp_descs[d]->app_size); + + ret = p_attr->pp_descs[d]->decode(p_app_value, p_value); + + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(&p_attr->pp_descs[d], conn_hdl, ret, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_attr->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + else + { + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(&p_attr->pp_descs[d], conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + break; + } + } + } + } +} + +static void write_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, ble_status_t result) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + /* Characteristics */ + if (attr_hdl == p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (NULL != p_attr->write_rsp_cb) + { + p_attr->write_rsp_cb(p_attr, conn_hdl, result); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), result, &evt_data); + } + } + /* Descriptors */ + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (attr_hdl == p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (NULL != p_attr->pp_descs[d]->write_rsp_cb) + { + p_attr->pp_descs[d]->write_rsp_cb(&p_attr->pp_descs[d], conn_hdl, result); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), result, &evt_data); + } + break; + } + } + } + } +} + +void R_BLE_SERVC_GattcCb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t * p_data) +{ + switch (type) + { + case BLE_GATTC_EVENT_CONN_IND: + { + st_ble_gattc_conn_evt_t *p_conn_evt_param = + (st_ble_gattc_conn_evt_t *)p_data->p_param; + + set_conn_idx(p_data->conn_hdl, p_conn_evt_param->p_addr); + } break; + + case BLE_GATTC_EVENT_DISCONN_IND: + { + clear_conn_idx(p_data->conn_hdl); + } break; + + case BLE_GATTC_EVENT_CHAR_READ_RSP: + { + st_ble_gattc_rd_char_evt_t *p_rd_char_evt_param = + (st_ble_gattc_rd_char_evt_t *)p_data->p_param; + + read_evt_handler(p_data->conn_hdl, + p_rd_char_evt_param->read_data.attr_hdl, + &p_rd_char_evt_param->read_data.value, + result); + } break; + + case BLE_GATTC_EVENT_CHAR_PART_READ_RSP: + { + st_ble_gattc_rd_char_evt_t *p_rd_char_evt_param = + (st_ble_gattc_rd_char_evt_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_rd_char_evt_param->read_data.attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + if (p_rd_char_evt_param->read_data.attr_hdl == + p_attr->p_attr_hdls[conn_idx].start_hdl + 1) + { + if (BLE_SUCCESS == result) + { + if (NULL == gs_conn_info[conn_idx].p_read_buf) + { + gs_conn_info[conn_idx].p_read_buf = malloc(p_attr->db_size); + memset(gs_conn_info[conn_idx].p_read_buf, 0x00, p_attr->db_size); + + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = p_rd_char_evt_param->read_data.attr_hdl; + } + + memcpy(&gs_conn_info[conn_idx].p_read_buf[gs_conn_info[conn_idx].read_buf_pos], + p_rd_char_evt_param->read_data.value.p_value, + p_rd_char_evt_param->read_data.value.value_len); + gs_conn_info[conn_idx].read_buf_pos += p_rd_char_evt_param->read_data.value.value_len; + } + else + { + if (NULL != gs_conn_info[conn_idx].p_read_buf) + { + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } + + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, p_data->conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + } + else + { + for (uint8_t d = 0; d < p_attr->num_of_descs; d++) + { + if (p_rd_char_evt_param->read_data.attr_hdl == + p_attr->pp_descs[d]->p_attr_hdls[conn_idx]) + { + if (BLE_SUCCESS == result) + { + if (NULL == gs_conn_info[conn_idx].p_read_buf) + { + gs_conn_info[conn_idx].p_read_buf = malloc(p_attr->pp_descs[d]->db_size); + memset(gs_conn_info[conn_idx].p_read_buf, 0x00, p_attr->pp_descs[d]->db_size); + + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = p_rd_char_evt_param->read_data.attr_hdl; + } + + memcpy(&gs_conn_info[conn_idx].p_read_buf[gs_conn_info[conn_idx].read_buf_pos], + p_rd_char_evt_param->read_data.value.p_value, + p_rd_char_evt_param->read_data.value.value_len); + gs_conn_info[conn_idx].read_buf_pos += p_rd_char_evt_param->read_data.value.value_len; + } + else + { + if (NULL != gs_conn_info[conn_idx].p_read_buf) + { + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } + + if (NULL != p_attr->pp_descs[d]->read_rsp_cb) + { + p_attr->pp_descs[d]->read_rsp_cb(p_attr, p_data->conn_hdl, result, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->pp_descs[d]->desc_idx, p_attr->pp_descs[d]->inst_idx, BLE_SERVC_READ_RSP), result, &evt_data); + } + } + break; + } + } + } + } + } break; + + case BLE_GATTC_EVENT_LONG_CHAR_READ_COMP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + st_ble_gatt_value_t value = { + .p_value = gs_conn_info[conn_idx].p_read_buf, + .value_len = gs_conn_info[conn_idx].read_buf_pos, + }; + + read_evt_handler(p_data->conn_hdl, + gs_conn_info[conn_idx].read_attr_hdl, + &value, + result); + + free(gs_conn_info[conn_idx].p_read_buf); + gs_conn_info[conn_idx].p_read_buf = NULL; + gs_conn_info[conn_idx].read_buf_pos = 0; + gs_conn_info[conn_idx].read_attr_hdl = 0; + } break; + + case BLE_GATTC_EVENT_CHAR_WRITE_RSP: + { + st_ble_gattc_wr_char_evt_t *p_wr_char_evt_param = + (st_ble_gattc_wr_char_evt_t *)p_data->p_param; + write_evt_handler(p_data->conn_hdl, p_wr_char_evt_param->value_hdl, result); + } break; + + case BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + st_ble_gattc_char_part_wr_evt_t *p_char_part_wr_param = + (st_ble_gattc_char_part_wr_evt_t *)p_data->p_param; + + gs_conn_info[conn_idx].write_attr_hdl = p_char_part_wr_param->write_data.attr_hdl; + } break; + + case BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP: + { + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + write_evt_handler(p_data->conn_hdl, gs_conn_info[conn_idx].write_attr_hdl, result); + } break; + + case BLE_GATTC_EVENT_HDL_VAL_NTF: + { + st_ble_gatt_hdl_value_pair_t *p_hdl_value_pair_param = + (st_ble_gatt_hdl_value_pair_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_hdl_value_pair_param->attr_hdl, &p_client, &p_attr); + + if ((NULL != p_attr) && (NULL != p_attr->decode)) + { + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + p_attr->decode(p_app_value, &p_hdl_value_pair_param->value); + + if (NULL != p_attr->hdl_val_ntf_cb) + { + p_attr->hdl_val_ntf_cb(p_attr, p_data->conn_hdl, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_HDL_VAL_NTF), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTC_EVENT_HDL_VAL_IND: + { + st_ble_gatt_hdl_value_pair_t *p_hdl_value_pair_param = + (st_ble_gatt_hdl_value_pair_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_hdl_value_pair_param->attr_hdl, &p_client, &p_attr); + + if ((NULL != p_attr) && (NULL != p_attr->decode)) + { + void *p_app_value; + + p_app_value = malloc(p_attr->app_size); + memset(p_app_value, 0x00, p_attr->app_size); + + p_attr->decode(p_app_value, &p_hdl_value_pair_param->value); + + if (NULL != p_attr->hdl_val_ind_cb) + { + p_attr->hdl_val_ind_cb(p_attr, p_data->conn_hdl, p_app_value); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_attr->app_size, + .p_param = p_app_value, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_HDL_VAL_IND), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTC_EVENT_ERROR_RSP: + { + st_ble_gattc_err_rsp_evt_t *p_err_rsp_evt_param = + (st_ble_gattc_err_rsp_evt_t *)p_data->p_param; + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(p_data->conn_hdl); + + const st_ble_servc_info_t *p_client = NULL; + const st_ble_servc_char_info_t *p_attr = NULL; + find_attr(conn_idx, p_err_rsp_evt_param->attr_hdl, &p_client, &p_attr); + + if (NULL != p_attr) + { + switch (p_err_rsp_evt_param->op_code) + { + case 0x0A: /* Read Request */ + { + if (NULL != p_attr->read_rsp_cb) + { + p_attr->read_rsp_cb(p_attr, p_data->conn_hdl, p_err_rsp_evt_param->rsp_code, NULL); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 2, + .p_param = &p_err_rsp_evt_param->attr_hdl, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_READ_RSP), p_err_rsp_evt_param->rsp_code, &evt_data); + } + } break; + + case 0x12: /* Write Request) */ + { + if (NULL != p_attr->write_rsp_cb) + { + p_attr->write_rsp_cb(p_attr, p_data->conn_hdl, p_err_rsp_evt_param->rsp_code); + } + else + { + st_ble_servc_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 2, + .p_param = &p_err_rsp_evt_param->attr_hdl, + }; + p_client->cb(BLE_SERVC_MULTI_ATTR_EVENT(p_attr->char_idx, p_attr->inst_idx, BLE_SERVC_WRITE_RSP), p_err_rsp_evt_param->rsp_code, &evt_data); + } + } break; + } + } + } break; + + case BLE_GATTC_EVENT_INVALID: + { + } break; + + case BLE_GATTC_EVENT_EX_MTU_RSP: + case BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP: + case BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP: + case BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP: + case BLE_GATTC_EVENT_RELIABLE_WRITES_COMP: + default: + { + break; + } + } +} + +ble_status_t R_BLE_SERVC_Init(void) +{ + for (uint8_t i = 0; i < BLE_SERVC_MAX_NUM_OF_SAVED; i++) + { + gs_conn_info[i].conn_hdl = BLE_GAP_INVALID_CONN_HDL; + } + gs_num_of_clients = 0; + return BLE_SUCCESS; +} + +ble_status_t R_BLE_SERVC_RegisterClient(const st_ble_servc_info_t *p_info) +{ + ble_status_t ret; + if( BLE_SERVC_MAX_NUM_OF_CLIENTS > gs_num_of_clients ) + { + gs_clients[gs_num_of_clients++] = p_info; + ret = BLE_SUCCESS; + } + else + { + ret = BLE_ERR_CONTEXT_FULL; + } + + return ret; +} + +ble_status_t R_BLE_SERVC_ReadChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl) +{ + ble_status_t ret; + + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 3)) + { + ret = R_BLE_GATTC_ReadChar(conn_hdl, (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl+1)); + } + else + { + ret = R_BLE_GATTC_ReadLongChar(conn_hdl, (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl+1), 0); + } + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl + 1), + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_data.value.value_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteCmdChar( + const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = (uint16_t)(p_attr->p_attr_hdls[conn_idx].start_hdl + 1), + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + ret = R_BLE_GATTC_WriteCharWithoutRsp(conn_hdl, &write_data); + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_ReadDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl) +{ + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 1)) + { + return R_BLE_GATTC_ReadChar(conn_hdl, p_attr->p_attr_hdls[conn_idx]); + } + else + { + return R_BLE_GATTC_ReadLongChar(conn_hdl, p_attr->p_attr_hdls[conn_idx], 0); + } +} + +ble_status_t R_BLE_SERVC_ReadDesc_with_Type(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, int32_t type) +{ + if (NULL == p_attr) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (0 == type) + { + return R_BLE_GATTC_ReadChar(conn_hdl, p_attr->p_attr_hdls[conn_idx]); + } + else + { + return R_BLE_GATTC_ReadLongChar(conn_hdl, p_attr->p_attr_hdls[conn_idx], 0); + } +} + + + +ble_status_t R_BLE_SERVC_WriteDesc( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (p_attr->db_size <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + +ble_status_t R_BLE_SERVC_WriteDesc2( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + p_byte_value = malloc(p_attr->db_size); + memset(p_byte_value, 0x00, p_attr->db_size); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_data.value.value_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + + + +ble_status_t R_BLE_SERVC_WriteDesc_with_Size( + const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const st_ble_seq_data_t *p_app_value) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_app_value)) + { + return BLE_ERR_INVALID_ARG; + } + + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + if (0xFF == conn_idx) + { + return BLE_ERR_INVALID_HDL; + } + + uint8_t *p_byte_value; + uint16_t write_len; + write_len = (p_app_value->len < p_attr->db_size) ? p_app_value->len : p_attr->db_size; + + p_byte_value = malloc(write_len); + memset(p_byte_value, 0x00, write_len); + + st_ble_gatt_value_t gatt_value = { + .p_value = p_byte_value, + .value_len = write_len, + }; + + //ret = p_attr->encode(p_app_value, &gatt_value); + ret = p_attr->encode(p_app_value->data, &gatt_value); + + st_ble_gatt_hdl_value_pair_t write_data = { + .attr_hdl = p_attr->p_attr_hdls[conn_idx], + .value.p_value = gatt_value.p_value, + .value.value_len = gatt_value.value_len, + }; + + if (BLE_SUCCESS != ret) + { + return BLE_ERR_INVALID_DATA; + } + + uint16_t mtu = BLE_GATT_DEFAULT_MTU; + R_BLE_GATT_GetMtu(conn_hdl, &mtu); + + if (write_len <= (mtu - 3)) + { + ret = R_BLE_GATTC_WriteChar(conn_hdl, &write_data); + } + else + { + ret = R_BLE_GATTC_WriteLongChar(conn_hdl, &write_data, 0); + } + + free(p_byte_value); + + return ret; +} + + + + +void R_BLE_SERVC_ServDiscCb(const st_ble_servc_info_t *p_info, uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param) +{ + uint8_t conn_idx = find_conn_idx_from_conn_hdl(conn_hdl); + /* unused arg */ + (void)serv_idx; + + if (0xFF == conn_idx) + { + return; + } + + switch (type) + { + case BLE_DISC_PRIM_SERV_FOUND: + { + st_disc_serv_param_t *p_serv_param = (st_disc_serv_param_t *)p_param; + memcpy(&p_info->p_attr_hdls[conn_idx], &p_serv_param->value.serv_16.range, sizeof(p_info->p_attr_hdls[conn_idx])); + } break; + + case BLE_DISC_CHAR_FOUND: + { + st_disc_char_param_t *p_char_param = (st_disc_char_param_t *)p_param; + + for (uint8_t c = 0; c < p_info->num_of_chars; c++) + { + if ((BLE_GATT_16_BIT_UUID_FORMAT == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_type == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_16 == p_char_param->value.char_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl)) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl = p_char_param->value.char_16.decl_hdl; + + if (p_char_param->num_of_descs > 0) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = + p_char_param->descs[p_char_param->num_of_descs-1].value.desc_16.desc_hdl; + } + else + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = p_char_param->value.char_16.value_hdl; + } + + for (uint8_t d = 0; d < p_char_param->num_of_descs; d++) + { + for (uint8_t dd = 0; dd < p_info->pp_chars[c]->num_of_descs; dd++) + { + if ((p_info->pp_chars[c]->pp_descs[dd]->uuid_16 == p_char_param->descs[d].value.desc_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx])) + { + p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx] = p_char_param->descs[d].value.desc_16.desc_hdl; + break; + } + } + } + break; + } + else if ((BLE_GATT_128_BIT_UUID_FORMAT == p_char_param->uuid_type) && + (p_info->pp_chars[c]->uuid_type == p_char_param->uuid_type) && + (0 == memcmp(p_info->pp_chars[c]->uuid_128, p_char_param->value.char_128.uuid_128, 0x10)) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl)) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].start_hdl = p_char_param->value.char_128.decl_hdl; + + if (p_char_param->num_of_descs > 0) + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = + p_char_param->descs[p_char_param->num_of_descs-1].value.desc_16.desc_hdl; + } + else + { + p_info->pp_chars[c]->p_attr_hdls[conn_idx].end_hdl = p_char_param->value.char_128.value_hdl; + } + + for (uint8_t d = 0; d < p_char_param->num_of_descs; d++) + { + for (uint8_t dd = 0; dd < p_info->pp_chars[c]->num_of_descs; dd++) + { + if ((p_info->pp_chars[c]->pp_descs[dd]->uuid_16 == p_char_param->descs[d].value.desc_16.uuid_16) && + (BLE_GATT_INVALID_ATTR_HDL_VAL == p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx])) + { + p_info->pp_chars[c]->pp_descs[dd]->p_attr_hdls[conn_idx] = p_char_param->descs[d].value.desc_16.desc_hdl; + break; + } + } + } + break; + + } + } + } break; + + default: + { + /* Do nothing. */ + } break; + } +} + +uint8_t R_BLE_SERVC_GetConnIdx(const st_ble_dev_addr_t *p_addr) +{ + return find_conn_idx_from_bd_addr(p_addr); +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h new file mode 100644 index 0000000000..8757faf490 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servc_if.h @@ -0,0 +1,354 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn_cli Profile Common Client Library + * @{ + * @ingroup profile_cmn + * @brief Profile Common Client Library Library + * @details This library provides APIs to implement GATT profile client. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ + +#include "r_ble_serv_common.h" + +#ifndef R_BLE_SERVC_IF_H +#define R_BLE_SERVC_IF_H + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** @defgroup profile_cmn_cli_macro Macros + * @{ + * @brief Macro definition + */ + +/** + * @def BLE_SERVC_MAX_NUM_OF_SAVED + * @brief Max number of connection to be saved. + */ +#define BLE_SERVC_MAX_NUM_OF_SAVED (BLE_PRF_CONN_MAX) + +/** + * @def BLE_SERVC_MAX_NUM_OF_CLIENTS + * @brief Max number of client service to be saved. + */ +#define BLE_SERVC_MAX_NUM_OF_CLIENTS (10) + +/* attr_idx:6bit, inst_idx:4bit, type_idx:1bit, evt_idx:5bit */ +/** + * @def BLE_SERVC_MULTI_ATTR_EVENT + * @brief Event type used in callback. This macro is used if same service is used. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] inst_idx Service index. 4bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVC_MULTI_ATTR_EVENT(attr_idx, inst_idx, evt_idx) ((uint16_t)((attr_idx << 10) | (inst_idx << 6) | (evt_idx << 0))) + +/** + * @def BLE_SERVC_ATTR_EVENT + * @brief Event type used in callback. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVC_ATTR_EVENT(attr_idx, evt_idx) BLE_SERVC_MULTI_ATTR_EVENT(attr_idx, 0, evt_idx) + +/** + * @enum e_ble_servc_event_t + * @brief Client callback events. + */ +typedef enum { + /** + * @brief Receive a write response. + */ + BLE_SERVC_WRITE_RSP, + /** + * @brief Receive a read response. + */ + BLE_SERVC_READ_RSP, + /** + * @brief Receive a notification. + */ + BLE_SERVC_HDL_VAL_NTF, + /** + * @brief Receive a indication. + */ + BLE_SERVC_HDL_VAL_IND, +} e_ble_servc_event_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servc_evt_data_t + * @brief st_ble_servc_evt_data_t includes connection handle and value for connection parameter. + **********************************************************************************************************************/ +typedef struct { + uint16_t conn_hdl; /**< Connection handle. */ + uint16_t param_len; /**< Event parameter length. */ + const void *p_param; /**< Event parameter.\n Value is set after decode function is called. */ +} st_ble_servc_evt_data_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_callback Callbacks + * @{ + * @brief Callback definition + */ +/*************************************************************************************************************//** + * @brief Callback invoked when write response received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write response. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_write_rsp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result); + +/*************************************************************************************************************//** + * @brief Callback invoked when read response received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of read response. + * @param[in] p_app_value Characteristic value or descriptor value of read response. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_read_rsp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when notification received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value of notification. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_hdl_val_ntf_t)(const void *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when indication received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value of indication. +***********************************************************************************************************************/ +typedef void (*ble_servc_attr_hdl_val_ind_t)(const void *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when events defined in service occurred. + * @param[in] type Event type of callback. Refer e_ble_XXX_event_t of each service. + * @param[in] result Result of event. + * @param[in] p_data Event data. +***********************************************************************************************************************/ +typedef void (*ble_servc_app_cb_t)(uint16_t type, ble_status_t result, st_ble_servc_evt_data_t *p_data); +/*@}*/ + +/** @defgroup profile_cmn_cli_func Functions + * @{ + * @brief Function definition + */ +/*************************************************************************************************************//** + * @brief Decode function. Convert data from GATT database value to application data value. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servc_attr_decode_t)(void *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/*************************************************************************************************************//** + * @brief Encode function. Convert data from application data value to GATT database value. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servc_attr_encode_t)(const void *p_app_value, st_ble_gatt_value_t *p_gatt_value); +/*@}*/ + +/** @defgroup profile_cmn_cli_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servc_desc_info_t + * @brief st_ble_servc_desc_info_t includes information about descriptor. + **********************************************************************************************************************/ +typedef struct { + uint16_t uuid_16; /**< 16bit UUID of descriptor. */ + const uint8_t *uuid_128; /**< 128bit UUID of descriptor. */ + uint8_t uuid_type; /**< Select from 16bit UUID or 128bit UUID.\n 128bit UUID should be used for custom service.\n 16bit UUID = BLE_GATT_16_BIT_UUID_FORMAT\n 128bit UUID = BLE_GATT_128_BIT_UUID_FORMAT */ + uint8_t desc_idx; /**< Index of descriptor. */ + uint8_t inst_idx; /**< Index used if same descriptor is set in one characteristic. */ + uint16_t *p_attr_hdls; /**< Attribute handle for each connection. */ + uint16_t app_size; /**< Descriptor value size used in application. */ + uint16_t db_size; /**< Descriptor value size used in GATT database. */ + ble_servc_attr_write_rsp_t write_rsp_cb; /**< Write response callback function. Set function if needed. */ + ble_servc_attr_read_rsp_t read_rsp_cb; /**< Read response callback function. Set function if needed. */ + ble_servc_attr_decode_t decode; /**< Decode function. */ + ble_servc_attr_encode_t encode; /**< Encode function. */ +} st_ble_servc_desc_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servc_char_info_t + * @brief st_ble_servc_char_info_t includes information about characteristic. + **********************************************************************************************************************/ +typedef struct { + uint16_t uuid_16; /**< 16bit UUID of characteristic*/ + const uint8_t *uuid_128; /**< 128bit UUID of characteristic*/ + uint8_t uuid_type; /**< Select from 16bit UUID or 128bit UUID.\n 128bit UUID should be used for custom service.\n 16bit UUID = BLE_GATT_16_BIT_UUID_FORMAT\n 128bit UUID = BLE_GATT_128_BIT_UUID_FORMAT */ + st_ble_gatt_hdl_range_t *p_attr_hdls; /**< Attribute handle range of characteristic. */ + uint8_t char_idx; /**< Index of characteristic. */ + uint8_t inst_idx; /**< Index used if same characteristic is set in one service. */ + uint16_t app_size; /**< Size of characteristic value in Application. */ + uint16_t db_size; /**< Size of characteristic value in GATT database. */ + const st_ble_servc_desc_info_t **pp_descs; /**< Set all descriptor information structure included in this characteristic. */ + uint8_t num_of_descs; /**< Number of descriptors included in this characteristic. */ + ble_servc_attr_write_rsp_t write_rsp_cb; /**< Write response callback function. Set function if needed. */ + ble_servc_attr_read_rsp_t read_rsp_cb; /**< Read response callback function. Set function if needed. */ + ble_servc_attr_hdl_val_ntf_t hdl_val_ntf_cb; /**< Notification callback function. Set function if needed. */ + ble_servc_attr_hdl_val_ind_t hdl_val_ind_cb; /**< Indication callback function. Set function if needed. */ + ble_servc_attr_decode_t decode; /**< Decode function. */ + ble_servc_attr_encode_t encode; /**< Encode function. */ +} st_ble_servc_char_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servc_info_t + * @brief st_ble_servc_info_t includes information about service. + **********************************************************************************************************************/ +typedef struct { + const st_ble_servc_char_info_t **pp_chars; /**< Set all characteristic information structure included in this service. */ + uint16_t num_of_chars; /**< Number of characteristics included in this service. */ + st_ble_gatt_hdl_range_t *p_attr_hdls; /**< Attribute handle range of service. */ + ble_servc_app_cb_t cb; /**< Service event callback function. */ +} st_ble_servc_info_t; +/*@}*/ + +/** @defgroup profile_cmn_cli_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Initialize profile common client library. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_Init(void); + +/******************************************************************************************************************//** + * @brief Register client service to profile common client library. + * @param[in] p_info Client service to be registered. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_RegisterClient(const st_ble_servc_info_t *p_info); + +/******************************************************************************************************************//** + * @brief Callback function used for service discovery. + * @param[in] p_info Client server information structure to be discovered. + * @param[in] conn_hdl Connection handle. + * @param[in] serv_idx Index used if same service is included in one profile. + * @param[in] type Event type of discovery. + * @param[in] p_param Parameter of discovered information. + **********************************************************************************************************************/ +void R_BLE_SERVC_ServDiscCb(const st_ble_servc_info_t *p_info, uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param); + +/******************************************************************************************************************//** + * @brief Get connection handle from BD address. + * @param[in] p_addr BD address of connected device. + * @return connection handle. + **********************************************************************************************************************/ +uint8_t R_BLE_SERVC_GetConnIdx(const st_ble_dev_addr_t *p_addr); + +/******************************************************************************************************************//** + * @brief Send read request of characteristic value for read operation. + * @param[in] p_attr Characteristic sending read request. + * @param[in] conn_hdl Connection handle. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @brief Send write request of characteristic value for write operation. + * @param[in] p_attr Characteristic sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write command of characteristic value for write without request operation. + * @param[in] p_attr Characteristic sending write command. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write command. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteCmdChar(const st_ble_servc_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send read request of descriptor value for read operation. + * @param[in] p_attr Descriptor sending read request. + * @param[in] conn_hdl Connection handle. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @brief Send read request of descriptor value for read operation or read long operation. + * @param[in] p_attr Descriptor sending read request. + * @param[in] conn_hdl Connection handle. + * @param[in] type Defines read operation or read long operation.\n 0 = read operation\n Other value = read long operation + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_ReadDesc_with_Type(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, int32_t type); + +/******************************************************************************************************************//** + * @brief Send write request of descriptor value for write operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write request of variable descriptor value for write operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Data value and size to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc_with_Size(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const st_ble_seq_data_t *p_app_value); + +/******************************************************************************************************************//** + * @brief Send write request of descriptor value for write without request operation. + * @param[in] p_attr Descriptor sending write request. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on write request. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVC_WriteDesc2(const st_ble_servc_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Callback function used for GATT client events. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function to enable all client callback event included in profile. + **********************************************************************************************************************/ +void R_BLE_SERVC_GattcCb(uint16_t type, ble_status_t result, st_ble_gattc_evt_data_t * p_data); +/*@}*/ + +#endif /* R_BLE_SERVC_IF_H */ +/* @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c new file mode 100644 index 0000000000..6ced9b9dcc --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.c @@ -0,0 +1,738 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +#include +#include +#include "r_ble_servs_if.h" + +static const st_ble_servs_info_t *gs_servs[BLE_PRF_MAX_NUM_OF_SERVS]; +static uint8_t gs_num_of_servs; + +static void find_attr(uint16_t attr_hdl, + const st_ble_servs_info_t **pp_serv, + const st_ble_servs_char_info_t **pp_char) +{ + for (uint8_t s = 0; s < gs_num_of_servs; s++) + { + for (uint8_t c = 0; c < gs_servs[s]->num_of_chars; c++) + { + if ((gs_servs[s]->pp_chars[c]->start_hdl <= attr_hdl) && + (gs_servs[s]->pp_chars[c]->end_hdl >= attr_hdl)) + { + *pp_serv = gs_servs[s]; + *pp_char = gs_servs[s]->pp_chars[c]; + } + } + } +} + +static void desc_write_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t *p_value) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + ret = p_char->pp_descs[d]->decode(p_app_value, (const st_ble_gatt_value_t *)p_value); + + if (NULL != p_char->pp_descs[d]->write_req_cb) + { + p_char->pp_descs[d]->write_req_cb(&p_char->pp_descs[d], conn_hdl, ret, (const void *)p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_REQ), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } +} + +static void desc_read_evt_handler(uint16_t conn_hdl, uint16_t attr_hdl) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(conn_hdl, attr_hdl, &gatt_value); + p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->read_req_cb) + { + p_char->pp_descs[d]->read_req_cb(&p_char->pp_descs[d], conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_READ_REQ), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } +} + +static void ble_gatts_db_app_cb(uint16_t conn_hdl, uint8_t db_op, uint16_t attr_hdl, st_ble_gatt_value_t *p_value) +{ + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + + find_attr(attr_hdl, &p_serv, &p_char); + + if ((NULL == p_serv) || (NULL == p_char)) + { + return; + } + + switch (db_op) + { + case BLE_GATTS_OP_CHAR_PEER_READ_REQ: + { + if (NULL != p_char->read_req_cb) + { + p_char->read_req_cb(p_char, conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_READ_REQ), BLE_SUCCESS, &evt_data); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_WRITE_REQ: + { + if (NULL != p_char->decode) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_char->app_size); + ret = p_char->decode(p_app_value, p_value); + + if (NULL != p_char->write_req_cb) + { + p_char->write_req_cb(p_char, conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_REQ), ret, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_WRITE_CMD: + { + if (NULL != p_char->decode) + { + ble_status_t ret; + void *p_app_value; + + p_app_value = malloc(p_char->app_size); + ret = p_char->decode(p_app_value, p_value); + + if (NULL != p_char->write_cmd_cb) + { + p_char->write_cmd_cb(p_char, conn_hdl, ret, &p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_CMD), ret, &evt_data); + } + + free(p_app_value); + } + } break; + + case BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ: + case BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ: + { + desc_write_evt_handler(conn_hdl, attr_hdl, p_value); + } break; + + case BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ: + case BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ: + { + desc_read_evt_handler(conn_hdl, attr_hdl); + } break; + + case BLE_GATTS_OP_CHAR_REQ_AUTHOR: + { + } break; + + default: + { + /* Do nothing. */ + } break; + } +} + +void R_BLE_SERVS_GattsCb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data) +{ + static uint16_t s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + + switch (type) + { + case BLE_GATTS_EVENT_CONN_IND: + case BLE_GATTS_EVENT_DISCONN_IND: + break; + + case BLE_GATTS_EVENT_EX_MTU_REQ: + { + R_BLE_GATTS_RspExMtu(p_data->conn_hdl, BLE_PRF_MTU_SIZE); + } + break; + + case BLE_GATTS_EVENT_HDL_VAL_CNF: + { + const st_ble_gatts_cfm_evt_t *p_cfm_evt_param = + (st_ble_gatts_cfm_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(p_cfm_evt_param->attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if ((p_char->start_hdl + 1) == p_cfm_evt_param->attr_hdl) + { + if (NULL != p_char->hdl_val_cnf_cb) + { + p_char->hdl_val_cnf_cb(p_char, p_data->conn_hdl); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = 0, + .p_param = NULL, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_HDL_VAL_CNF), BLE_SUCCESS, &evt_data); + } + } + } + } break; + + case BLE_GATTS_EVENT_DB_ACCESS_IND: + { + const st_ble_gatts_db_access_evt_t *p_db_access_evt_param = + (st_ble_gatts_db_access_evt_t *)p_data->p_param; + + ble_gatts_db_app_cb(p_data->conn_hdl, + p_db_access_evt_param->p_params->db_op, + p_db_access_evt_param->p_params->attr_hdl, + &p_db_access_evt_param->p_params->value); + } break; + + case BLE_GATTS_EVENT_WRITE_RSP_COMP: + { + st_ble_gatts_write_rsp_evt_t *p_write_rsp_evt_param = + (st_ble_gatts_write_rsp_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(p_write_rsp_evt_param->attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + /* Characteristic */ + if (((p_char->start_hdl + 1) == p_write_rsp_evt_param->attr_hdl) && (NULL != p_char->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->app_size); + + ret = R_BLE_SERVS_GetChar(p_char, p_data->conn_hdl, p_app_value); + + if (NULL != p_char->write_comp_cb) + { + p_char->write_comp_cb(p_char, p_data->conn_hdl, result, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_COMP), ret, &evt_data); + } + + free(p_app_value); + } + /* Descriptor */ + else + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == p_write_rsp_evt_param->attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(p_data->conn_hdl, p_write_rsp_evt_param->attr_hdl, &gatt_value); + + ret = p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->write_comp_cb) + { + p_char->pp_descs[d]->write_comp_cb(&p_char->pp_descs[d], p_data->conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_COMP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + break; + } + } + } + } + } + } break; + + case BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP: + { + st_ble_gatts_prepare_write_rsp_evt_t *p_prepare_write_evt_param = + (st_ble_gatts_prepare_write_rsp_evt_t *)p_data->p_param; + + s_write_long_attr_hdl = p_prepare_write_evt_param->attr_hdl; + } break; + + case BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP: + { + st_ble_gatts_exe_write_rsp_evt_t *p_exe_write_evt_param = + (st_ble_gatts_exe_write_rsp_evt_t *)p_data->p_param; + + const st_ble_servs_info_t *p_serv = NULL; + const st_ble_servs_char_info_t *p_char = NULL; + + find_attr(s_write_long_attr_hdl, &p_serv, &p_char); + + if ((NULL != p_serv) && (NULL != p_char)) + { + if (BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG == p_exe_write_evt_param->exe_flag) { + /* Characteristic */ + if (((p_char->start_hdl + 1) == s_write_long_attr_hdl) && (NULL != p_char->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->app_size); + + ret = R_BLE_SERVS_GetChar(p_char, p_data->conn_hdl, p_app_value); + + if (NULL != p_char->write_comp_cb) + { + p_char->write_comp_cb(p_char, p_data->conn_hdl, result, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->char_idx, p_char->inst_idx, BLE_SERVS_WRITE_COMP), ret, &evt_data); + } + + free(p_app_value); + s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + } + /* Descriptor */ + else + { + if (NULL != p_char->pp_descs) + { + for (uint8_t d = 0; d < p_char->num_of_descs; d++) + { + if ((p_char->pp_descs[d]->attr_hdl == s_write_long_attr_hdl) && + (NULL != p_char->pp_descs[d]->decode)) + { + ble_status_t ret; + + void *p_app_value; + p_app_value = malloc(p_char->pp_descs[d]->app_size); + + st_ble_gatt_value_t gatt_value; + R_BLE_GATTS_GetAttr(p_data->conn_hdl, s_write_long_attr_hdl, &gatt_value); + + ret = p_char->pp_descs[d]->decode(p_app_value, &gatt_value); + + if (NULL != p_char->pp_descs[d]->write_comp_cb) + { + p_char->pp_descs[d]->write_comp_cb(&p_char->pp_descs[d], p_data->conn_hdl, ret, p_app_value); + } + else + { + st_ble_servs_evt_data_t evt_data = { + .conn_hdl = p_data->conn_hdl, + .param_len = p_char->pp_descs[d]->app_size, + .p_param = p_app_value, + }; + p_serv->cb(BLE_SERVS_MULTI_ATTR_EVENT(p_char->pp_descs[d]->desc_idx, p_char->pp_descs[d]->inst_idx, BLE_SERVS_WRITE_COMP), BLE_SUCCESS, &evt_data); + } + + free(p_app_value); + s_write_long_attr_hdl = BLE_GATT_INVALID_ATTR_HDL_VAL; + break; + } + } + } + } + } + } + } break; + + case BLE_GATTS_EVENT_READ_RSP_COMP: + case BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP: + case BLE_GATTS_EVENT_READ_BLOB_RSP_COMP: + case BLE_GATTS_EVENT_READ_MULTI_RSP_COMP: + case BLE_GATTS_EVENT_INVALID: + default: + { + } break; + } +} + +void R_BLE_SERVS_VsCb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t * p_data) +{ + /* unused arg */ + (void)result; + + switch (type) + { + case BLE_VS_EVENT_TX_FLOW_STATE_CHG: + { + st_ble_vs_tx_flow_chg_evt_t *p_tx_flow_chg_param = + (st_ble_vs_tx_flow_chg_evt_t *)p_data->p_param; + + uint32_t buffer_num; + R_BLE_VS_GetTxBufferNum(&buffer_num); + + if (BLE_VS_TX_FLOW_CTL_ON == p_tx_flow_chg_param->state) + { + for (uint8_t s = 0; s < gs_num_of_servs; s++) + { + for (uint8_t c = 0; c < gs_servs[s]->num_of_chars; c++) + { + if (NULL != gs_servs[s]->pp_chars[c]->flow_ctrl_cb) + { + gs_servs[s]->pp_chars[c]->flow_ctrl_cb(gs_servs[s]->pp_chars[c]); + } + } + } + } + } break; + + default: + { + /* Do nothing */ + } break; + } +} + +ble_status_t R_BLE_SERVS_Init(void) +{ + R_BLE_VS_StartTxFlowEvtNtf(); + + return BLE_SUCCESS; +} + +ble_status_t R_BLE_SERVS_RegisterServer(const st_ble_servs_info_t *p_info) +{ + ble_status_t ret; + if( BLE_PRF_MAX_NUM_OF_SERVS > gs_num_of_servs ) + { + gs_servs[gs_num_of_servs++] = p_info; + ret = BLE_SUCCESS; + } + else + { + ret = BLE_ERR_CONTEXT_FULL; + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SendHdlVal(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value, bool is_notify) +{ + ble_status_t ret; + + if ((NULL == p_attr) || (NULL == p_attr->encode) || (NULL == p_attr->pp_descs)) + { + return BLE_ERR_INVALID_PTR; + } + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if (BLE_GAP_INVALID_CONN_HDL == conn_hdl) + { + return BLE_ERR_INVALID_HDL; + } + + /* Check CCCD */ + uint16_t cccd = 0; + R_BLE_SERVS_GetDesc(p_attr->pp_descs[0], conn_hdl, &cccd); + if(0 == cccd) + { + return BLE_ERR_INVALID_OPERATION; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_hdl_value_pair_t hdl_val_data = { + .attr_hdl = (uint16_t)(p_attr->start_hdl + 1), + .value.value_len = p_attr->db_size, + .value.p_value = (uint8_t *)p_gatt_value, + }; + + ret = p_attr->encode(p_app_value, &hdl_val_data.value); + + if (BLE_SUCCESS == ret) + { + if (is_notify) + { + ret = R_BLE_GATTS_Notification(conn_hdl, &hdl_val_data); + } + else + { + ret = R_BLE_GATTS_Indication(conn_hdl, &hdl_val_data); + } + } + + free(p_gatt_value); + + return ret; +} + +ble_status_t R_BLE_SERVS_GetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->decode)) + { + return BLE_ERR_INVALID_PTR; + } + + st_ble_gatt_value_t gatt_value; + + ret = R_BLE_GATTS_GetAttr(conn_hdl, (uint16_t)(p_attr->start_hdl + 1), &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = p_attr->decode(p_app_value, &gatt_value); + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->encode)) + { + return BLE_ERR_INVALID_PTR; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_value_t gatt_value = { + .p_value = p_gatt_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = R_BLE_GATTS_SetAttr(conn_hdl, (uint16_t)(p_attr->start_hdl + 1), &gatt_value); + } + + free(p_gatt_value); + + return ret; +} + +ble_status_t R_BLE_SERVS_GetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->decode)) + { + return BLE_ERR_INVALID_PTR; + } + + st_ble_gatt_value_t gatt_value; + + ret = R_BLE_GATTS_GetAttr(conn_hdl, p_attr->attr_hdl, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = p_attr->decode(p_app_value, &gatt_value); + } + + return ret; +} + +ble_status_t R_BLE_SERVS_SetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value) +{ + ble_status_t ret; + + if (NULL == p_app_value) + { + return BLE_ERR_INVALID_ARG; + } + + if ((NULL == p_attr) || (NULL == p_attr->encode)) + { + return BLE_ERR_INVALID_PTR; + } + + void *p_gatt_value = malloc(p_attr->db_size); + + if (NULL == p_gatt_value) + { + return BLE_ERR_MEM_ALLOC_FAILED; + } + + st_ble_gatt_value_t gatt_value = { + .p_value = p_gatt_value, + .value_len = p_attr->db_size, + }; + + ret = p_attr->encode(p_app_value, &gatt_value); + + if (BLE_SUCCESS == ret) + { + ret = R_BLE_GATTS_SetAttr(conn_hdl, p_attr->attr_hdl, &gatt_value); + } + + free(p_gatt_value); + + return ret; +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h new file mode 100644 index 0000000000..b8ec78de3c --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/profile_cmn/r_ble_servs_if.h @@ -0,0 +1,304 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup profile_cmn_ser Profile Common Server Library + * @{ + * @ingroup profile_cmn + * @brief Profile Common Server Library Library + * @details This library provides APIs to implement GATT profile server. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 23.08.2019 1.00 First Release +* : 31.10.2019 1.01 Add doxygen comments. +***********************************************************************************************************************/ +#include "r_ble_serv_common.h" + +#ifndef R_BLE_SERVS_IF_H +#define R_BLE_SERVS_IF_H + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/** @defgroup profile_cmn_ser_macro Macros + * @{ + * @brief Macro definition + */ + +/* attr_idx:6bit, inst_idx:4bit, type_idx:1bit, evt_idx:5bit */ +/** + * @def BLE_SERVS_MULTI_ATTR_EVENT + * @brief Event type used in callback. This macro is used if same service is used. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] inst_idx Service index. 4bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVS_MULTI_ATTR_EVENT(attr_idx, inst_idx, evt_idx) ((uint16_t)((attr_idx << 10) | (inst_idx << 6) | (evt_idx << 0))) + +/** + * @def BLE_SERVS_ATTR_EVENT + * @brief Event type used in callback. + * @param[in] attr_idx Attribute index. 6bit is used. + * @param[in] evt_idx Event index. 5bit is used. + */ +#define BLE_SERVS_ATTR_EVENT(attr_idx, evt_idx) BLE_SERVS_MULTI_ATTR_EVENT(attr_idx, 0, evt_idx) + +/*******************************************************************************************************************//** + * @brief Server callback events. +***********************************************************************************************************************/ +typedef enum { + BLE_SERVS_WRITE_REQ = 0x00, /**< Receive a write request */ + BLE_SERVS_WRITE_CMD = 0x01, /**< Receive a write command */ + BLE_SERVS_WRITE_COMP = 0x02, /**< Send a write response */ + BLE_SERVS_READ_REQ = 0x03, /**< Receive a read request */ + BLE_SERVS_HDL_VAL_CNF = 0x04, /**< Receive a confirmation */ +} e_ble_servs_event_t; +/*@}*/ + +/** @defgroup profile_cmn_ser_struct Structures + * @{ + * @brief Structure definition + */ +typedef struct { + uint16_t conn_hdl; /**< Connection handle. */ + uint16_t param_len; /**< Event parameter length. */ + const void *p_param; /**< Event parameter.\n Value is set after decode function is called. */ +} st_ble_servs_evt_data_t; +/*@}*/ + +/** @defgroup profile_cmn_ser_callback Callbacks + * @{ + * @brief Callback definition + */ +/*************************************************************************************************************//** + * @brief Callback invoked when write request received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write request. + * @param[in] p_app_value Characteristic value or descriptor value of write request. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_req_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when write command received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write command. + * @param[in] p_app_value Characteristic value of write command. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_cmd_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when write response sent. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. + * @param[in] result Result of write response. + * @param[in] p_app_value Characteristic value or descriptor value of write response. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_write_comp_t)(const void *p_attr, uint16_t conn_hdl, ble_status_t result, const void *p_app_value); + +/*************************************************************************************************************//** + * @brief Callback invoked when read request received. + * @param[in] p_attr Information structure of characteristic or descriptor. + * @param[in] conn_hdl Connection handle. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_read_req_t)(const void *p_attr, uint16_t conn_hdl); + +/*************************************************************************************************************//** + * @brief Callback invoked when confirmation received. + * @param[in] p_attr Information structure of characteristic. + * @param[in] conn_hdl Connection handle. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_hdl_val_cnf_t)(const void *p_attr, uint16_t conn_hdl); + +/*************************************************************************************************************//** + * @brief Callback invoked when flow control callback occurred. + * @param[in] p_attr Information structure of characteristic. +***********************************************************************************************************************/ +typedef void (*ble_servs_attr_flow_ctrl_t)(const void *p_attr); + +/*************************************************************************************************************//** + * @brief Callback invoked when events defined in service occurred. + * @param[in] type Event type of callback. Refer e_ble_XXX_event_t of each service you will use. + * @param[in] result Result of event. + * @param[in] p_data Event data. +***********************************************************************************************************************/ +typedef void (*ble_servs_app_cb_t)(uint16_t type, ble_status_t result, st_ble_servs_evt_data_t *p_data); +/*@}*/ + +/** @defgroup profile_cmn_ser_func Functions + * @{ + * @brief Function definition + */ +/*************************************************************************************************************//** + * @brief Decode function. Convert data from GATT database value to application data value. + * @param[out] p_app_value Application data value of characteristic or descriptor. + * @param[in] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servs_attr_decode_t)(void *p_app_value, const st_ble_gatt_value_t *p_gatt_value); + +/*************************************************************************************************************//** + * @brief Encode function. Convert data from application data value to GATT database value. + * @param[in] p_app_value Application data value of characteristic or descriptor. + * @param[out] p_gatt_value GATT database value of characteristic or descriptor. +***********************************************************************************************************************/ +typedef ble_status_t (*ble_servs_attr_encode_t)(const void *p_app_value, st_ble_gatt_value_t *p_gatt_value); +/*@}*/ + +/** @defgroup profile_cmn_ser_struct Structures + * @{ + * @brief Structure definition + */ +/******************************************************************************************************************//** + * @struct st_ble_servs_desc_info_t + * @brief st_ble_servs_desc_info_t includes information about descriptor. + **********************************************************************************************************************/ +typedef struct _st_ble_desc_info_t{ + uint16_t attr_hdl; /**< Attribute handle of descriptor */ + uint8_t desc_idx; /**< Index of descriptor */ + uint8_t inst_idx; /**< Index used if same descriptor is set in one characteristic */ + uint16_t app_size; /**< Descriptor value size used in application. */ + uint16_t db_size; /**< Descriptor value size used in GATT database. */ + ble_servs_attr_write_req_t write_req_cb; /**< Write request callback function. Set function if needed. */ + ble_servs_attr_write_comp_t write_comp_cb; /**< Write response callback function. Set function if needed. */ + ble_servs_attr_read_req_t read_req_cb; /**< Read request callback function. Set function if needed. */ + ble_servs_attr_decode_t decode; /**< Decode function. */ + ble_servs_attr_encode_t encode; /**< Encode function. */ +} st_ble_servs_desc_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servs_char_info_t + * @brief st_ble_servs_char_info_t includes information about characteristic. + **********************************************************************************************************************/ +typedef struct _st_ble_char_info_t { + uint16_t start_hdl; /**< First Attribute handle of this characteristic */ + uint16_t end_hdl; /**< Last Attribute handle of this characteristic */ + uint8_t char_idx; /**< Index of characteristic */ + uint8_t inst_idx; /**< Index used if same characteristic is set in one service */ + uint16_t app_size; /**< Size of characteristic value in Application. */ + uint16_t db_size; /**< Size of characteristic value in GATT database. */ + const st_ble_servs_desc_info_t **pp_descs; /**< Set all descriptor information structure included in this characteristic. */ + uint8_t num_of_descs; /**< Number of descriptors included in this characteristic. */ + ble_servs_attr_write_req_t write_req_cb; /**< Write request callback function. Set function if needed. */ + ble_servs_attr_write_cmd_t write_cmd_cb; /**< Write command callback function. Set function if needed. */ + ble_servs_attr_write_comp_t write_comp_cb; /**< Write response callback function. Set function if needed. */ + ble_servs_attr_read_req_t read_req_cb; /**< Read request callback function. Set function if needed. */ + ble_servs_attr_hdl_val_cnf_t hdl_val_cnf_cb; /**< Confirmation callback function. Set function if needed. */ + ble_servs_attr_flow_ctrl_t flow_ctrl_cb; /**< Flow control callback function. Set function if needed. */ + ble_servs_attr_decode_t decode; /**< Decode function. */ + ble_servs_attr_encode_t encode; /**< Encode function. */ +} st_ble_servs_char_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_servs_info_t + * @brief st_ble_servs_info_t includes information about service. + **********************************************************************************************************************/ +typedef struct { + const st_ble_servs_char_info_t **pp_chars; /**< Set all characteristic information structure included in this service. */ + uint8_t num_of_chars; /**< Number of characteristics included in this service. */ + ble_servs_app_cb_t cb; /**< Service event callback function. */ +} st_ble_servs_info_t; +/*@}*/ +/**/ +/** @defgroup profile_cmn_ser_func Functions + * @{ + * @brief Function definition + */ +/******************************************************************************************************************//** + * @brief Initialize profile common server library. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_Init(void); + +/******************************************************************************************************************//** + * @brief Register server service information to profile common server library. + * @param[in] p_serv Server service to be registered. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_RegisterServer(const st_ble_servs_info_t *p_serv); + +/******************************************************************************************************************//** + * @brief Send notification or indication. + * @param[in] p_attr Characteristic sending notification or indication. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Value to be sent on notification or indication. + * @param[in] is_notify Defines notification or indication.\n true = notification\n false = indication + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SendHdlVal(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value, bool is_notify); + +/******************************************************************************************************************//** + * @brief Get characteristic value from GATT database. + * @param[in] p_attr Characteristic getting value. + * @param[in] conn_hdl Connection handle. + * @param[out] p_app_value Characteristic value getting from GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_GetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, void *p_app_value); + +/******************************************************************************************************************//** + * @brief Set characteristic value to GATT database. + * @param[in] p_attr Characteristic setting value. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Characteristic value setting to GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SetChar(const st_ble_servs_char_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Get descriptor value from GATT database. + * @param[in] p_attr Descriptor getting value. + * @param[in] conn_hdl Connection handle. + * @param[out] p_app_value Descriptor value getting from GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_GetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, void *p_app_value); + +/******************************************************************************************************************//** + * @brief Set descriptor value to GATT database. + * @param[in] p_attr Descriptor setting value. + * @param[in] conn_hdl Connection handle. + * @param[in] p_app_value Descriptor value setting to GATT database. + * @return See @ref ble_status_t + **********************************************************************************************************************/ +ble_status_t R_BLE_SERVS_SetDesc(const st_ble_servs_desc_info_t *p_attr, uint16_t conn_hdl, const void *p_app_value); + +/******************************************************************************************************************//** + * @brief Callback function used for GATT server event. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function to enable all server callback event included in profile. + **********************************************************************************************************************/ +void R_BLE_SERVS_GattsCb(uint16_t type, ble_status_t result, st_ble_gatts_evt_data_t *p_data); + +/******************************************************************************************************************//** + * @brief Callback function used for vender specific event. + * @param[in] type Type of event. + * @param[in] result Result of request sent to server. + * @param[in] p_data Event data. + * @details You need to call this function if you use flow control callback. + **********************************************************************************************************************/ +void R_BLE_SERVS_VsCb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t * p_data); +/*@}*/ + +#endif /* R_BLE_SERVS_IF_H */ +/* @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.c new file mode 100644 index 0000000000..4649739281 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.c @@ -0,0 +1,312 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gapc.c + * Version : 1.0 + * Description : The source file for Generic Access client. + **********************************************************************************************************************/ +#include +#include "r_ble_gapc.h" +#include "profile_cmn/r_ble_servc_if.h" + +static st_ble_servc_info_t gs_client_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Device Name characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_dev_name_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +static ble_status_t decode_st_ble_gapc_dev_name_t(st_ble_gapc_dev_name_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPC_DEV_NAME_LEN < p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memset(p_app_value->name, 0x00, BLE_GAPC_DEV_NAME_LEN); + + strcpy(p_app_value->name, (char *)p_gatt_value->p_value); + p_app_value->length = (uint8_t)p_gatt_value->value_len; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gapc_dev_name_t(const st_ble_gapc_dev_name_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPC_DEV_NAME_LEN < p_app_value->length) + { + return BLE_ERR_INVALID_DATA; + } + + strncpy((char *)p_gatt_value->p_value, p_app_value->name, p_app_value->length); + + return BLE_SUCCESS; +} + +/* Device Name characteristic definition */ +const st_ble_servc_char_info_t gs_dev_name_char = { + .uuid_16 = BLE_GAPC_DEV_NAME_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(st_ble_gapc_dev_name_t), + .db_size = BLE_GAPC_DEV_NAME_LEN, + .char_idx = BLE_GAPC_DEV_NAME_IDX, + .p_attr_hdls = gs_dev_name_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_st_ble_gapc_dev_name_t, + .encode = (ble_servc_attr_encode_t)encode_st_ble_gapc_dev_name_t, +}; + +ble_status_t R_BLE_GAPC_WriteDevName(uint16_t conn_hdl, const st_ble_gapc_dev_name_t *p_value) // @suppress("API function naming") +{ + return R_BLE_SERVC_WriteChar(&gs_dev_name_char, conn_hdl, p_value); +} + +ble_status_t R_BLE_GAPC_ReadDevName(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_dev_name_char, conn_hdl); +} + +void R_BLE_GAPC_GetDevNameAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_dev_name_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_dev_name_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Appearance characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_appearance_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Appearance characteristic definition */ +const st_ble_servc_char_info_t gs_appearance_char = { + .uuid_16 = BLE_GAPC_APPEARANCE_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint16_t), + .db_size = sizeof(uint16_t), + .char_idx = BLE_GAPC_APPEARANCE_IDX, + .p_attr_hdls = gs_appearance_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint16_t, + .encode = (ble_servc_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GAPC_ReadAppearance(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_appearance_char, conn_hdl); +} + +void R_BLE_GAPC_GetAppearanceAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_appearance_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_appearance_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Peripheral Preferred Connection Parameters characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_per_pref_conn_param_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +static ble_status_t decode_st_ble_gapc_per_pref_conn_param_t(st_ble_gapc_per_pref_conn_param_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GAPC_PER_PREF_CONN_PARAM_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->min_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->max_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->slave_latency, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->conn_sup_timeout_multiplier, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gapc_per_pref_conn_param_t(const st_ble_gapc_per_pref_conn_param_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->min_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->max_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->slave_latency); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->conn_sup_timeout_multiplier); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Peripheral Preferred Connection Parameters characteristic definition */ +const st_ble_servc_char_info_t gs_per_pref_conn_param_char = { + .uuid_16 = BLE_GAPC_PER_PREF_CONN_PARAM_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(st_ble_gapc_per_pref_conn_param_t), + .db_size = BLE_GAPC_PER_PREF_CONN_PARAM_LEN, + .char_idx = BLE_GAPC_PER_PREF_CONN_PARAM_IDX, + .p_attr_hdls = gs_per_pref_conn_param_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_st_ble_gapc_per_pref_conn_param_t, + .encode = (ble_servc_attr_encode_t)encode_st_ble_gapc_per_pref_conn_param_t, +}; + +ble_status_t R_BLE_GAPC_ReadPerPrefConnParam(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_per_pref_conn_param_char, conn_hdl); +} + +void R_BLE_GAPC_GetPerPrefConnParamAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_per_pref_conn_param_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_per_pref_conn_param_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Central Address Resolution characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_cent_addr_rslv_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Central Address Resolution characteristic definition */ +const st_ble_servc_char_info_t gs_cent_addr_rslv_char = { + .uuid_16 = BLE_GAPC_CENT_ADDR_RSLV_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint8_t), + .db_size = sizeof(uint8_t), + .char_idx = BLE_GAPC_CENT_ADDR_RSLV_IDX, + .p_attr_hdls = gs_cent_addr_rslv_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint8_t, + .encode = (ble_servc_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPC_ReadCentAddrRslv(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_cent_addr_rslv_char, conn_hdl); +} + +void R_BLE_GAPC_GetCentAddrRslvAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_cent_addr_rslv_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_cent_addr_rslv_char_ranges[conn_idx]; +} + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Resolvable Private Address Only characteristic attribute handles */ +static st_ble_gatt_hdl_range_t gs_rslv_priv_addr_only_char_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +/* Resolvable Private Address Only characteristic definition */ +const st_ble_servc_char_info_t gs_rslv_priv_addr_only_char = { + .uuid_16 = BLE_GAPC_RSLV_PRIV_ADDR_ONLY_UUID, + .uuid_type = BLE_GATT_16_BIT_UUID_FORMAT, + .app_size = sizeof(uint8_t), + .db_size = sizeof(uint8_t), + .char_idx = BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, + .p_attr_hdls = gs_rslv_priv_addr_only_char_ranges, + .decode = (ble_servc_attr_decode_t)decode_uint8_t, + .encode = (ble_servc_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPC_ReadRslvPrivAddrOnly(uint16_t conn_hdl) // @suppress("API function naming") +{ + return R_BLE_SERVC_ReadChar(&gs_rslv_priv_addr_only_char, conn_hdl); +} + +void R_BLE_GAPC_GetRslvPrivAddrOnlyAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_rslv_priv_addr_only_attr_hdl_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + p_hdl->range = gs_rslv_priv_addr_only_char_ranges[conn_idx]; +} + + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access client +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Access client attribute handles */ +static st_ble_gatt_hdl_range_t gs_gapc_ranges[BLE_SERVC_MAX_NUM_OF_SAVED]; + +const st_ble_servc_char_info_t *gspp_gapc_chars[] = { + &gs_dev_name_char, + &gs_appearance_char, + &gs_per_pref_conn_param_char, + &gs_cent_addr_rslv_char, + &gs_rslv_priv_addr_only_char, +}; + +static st_ble_servc_info_t gs_client_info = { + .pp_chars = gspp_gapc_chars, + .num_of_chars = ARRAY_SIZE(gspp_gapc_chars), + .p_attr_hdls = gs_gapc_ranges, +}; + +ble_status_t R_BLE_GAPC_Init(ble_servc_app_cb_t cb) // @suppress("API function naming") +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_client_info.cb = cb; + + return R_BLE_SERVC_RegisterClient(&gs_client_info); +} + +void R_BLE_GAPC_ServDiscCb(uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param) // @suppress("API function naming") +{ + R_BLE_SERVC_ServDiscCb(&gs_client_info, conn_hdl, serv_idx, type, p_param); +} + +void R_BLE_GAPC_GetServAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gatt_hdl_range_t *p_hdl) +{ + uint8_t conn_idx; + + conn_idx = R_BLE_SERVC_GetConnIdx(p_addr); + + *p_hdl = gs_gapc_ranges[conn_idx]; +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.h new file mode 100644 index 0000000000..5d87ae5a78 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gapc.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gapc.h + * Version : 1.0 + * Description : The header file for Generic Access client. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gapc Generic Access Client + * @{ + * @ingroup profile + * @brief This is the client for the Generic Access Service. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servc_if.h" + +#ifndef R_BLE_GAPC_H +#define R_BLE_GAPC_H + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_DEV_NAME_UUID (0x2A00) +#define BLE_GAPC_DEV_NAME_LEN (128) +/***************************************************************************//** + * @brief Device Name value structure. +*******************************************************************************/ +typedef struct { + char name[BLE_GAPC_DEV_NAME_LEN]; /**< Name */ + uint8_t length; /**< Length */ +} st_ble_gapc_dev_name_t; + +/***************************************************************************//** + * @brief Device Name attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_dev_name_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Device Name characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadDevName(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Write Device Name characteristic value to remote GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Device Name characteristic value to write. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_WriteDevName(uint16_t conn_hdl, const st_ble_gapc_dev_name_t *p_value); +; +/***************************************************************************//** + * @brief Get Device Name attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetDevNameAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_dev_name_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_APPEARANCE_UUID (0x2A01) +#define BLE_GAPC_APPEARANCE_LEN (2) +/***************************************************************************//** + * @brief Appearance Category enumeration. +*******************************************************************************/ +typedef enum { + BLE_GAPC_APPEARANCE_CATEGORY_UNKNOWN = 0, /**< Unknown */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_PHONE = 64, /**< Generic Phone */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_COMPUTER = 128, /**< Generic Computer */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_WATCH = 192, /**< Generic Watch */ + BLE_GAPC_APPEARANCE_CATEGORY_WATCH_SPORTS_WATCH = 193, /**< Watch: Sports Watch */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_CLOCK = 256, /**< Generic Clock */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_DISPLAY = 320, /**< Generic Display */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_REMOTE_CONTROL = 384, /**< Generic Remote Control */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_EYE_GLASSES = 448, /**< Generic Eye-glasses */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_TAG = 512, /**< Generic Tag */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_KEYRING = 576, /**< Generic Keyring */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_MEDIA_PLAYER = 640, /**< Generic Media Player */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_BARCODE_SCANNER = 704, /**< Generic Barcode Scanner */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_THERMOMETER = 768, /**< Generic Thermometer */ + BLE_GAPC_APPEARANCE_CATEGORY_THERMOMETER_EAR = 769, /**< Thermometer Ear */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_HEART_RATE_SENSOR = 832, /**< Generic Heart rate Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_HEART_RATE_SENSOR_HEART_RATE_BELT = 833, /**< Heart Rate Sensor Heart Rate Belt */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_BLOOD_PRESSURE = 896, /**< Generic Blood Pressure */ + BLE_GAPC_APPEARANCE_CATEGORY_BLOOD_PRESSURE_ARM = 897, /**< Blood Pressure: Arm */ + BLE_GAPC_APPEARANCE_CATEGORY_BLOOD_PRESSURE_WRIST = 898, /**< Blood Pressure: Wrist */ + BLE_GAPC_APPEARANCE_CATEGORY_HUMAN_INTERFACE_DEVICE = 960, /**< Human Interface Device (HID) */ + BLE_GAPC_APPEARANCE_CATEGORY_KEYBOARD = 961, /**< Keyboard */ + BLE_GAPC_APPEARANCE_CATEGORY_MOUSE = 962, /**< Mouse */ + BLE_GAPC_APPEARANCE_CATEGORY_JOYSTICK = 963, /**< Joystick */ + BLE_GAPC_APPEARANCE_CATEGORY_GAMEPAD = 964, /**< Gamepad */ + BLE_GAPC_APPEARANCE_CATEGORY_DIGITIZER_TABLET = 965, /**< Digitizer Tablet */ + BLE_GAPC_APPEARANCE_CATEGORY_CARD_READER = 966, /**< Card Reader */ + BLE_GAPC_APPEARANCE_CATEGORY_DIGITAL_PEN = 967, /**< Digital Pen */ + BLE_GAPC_APPEARANCE_CATEGORY_BARCODE_SCANNER = 968, /**< Barcode Scanner */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_GLUCOSE_METER = 1024, /**< Generic Glucose Meter */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_RUNNING_WALKING_SENSOR = 1088, /**< Generic: Running Walking Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_IN_SHOE = 1089, /**< Running Walking Sensor: In-Shoe */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_SHOE = 1090, /**< Running Walking Sensor: On-Shoe */ + BLE_GAPC_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_HIP = 1091, /**< Running Walking Sensor: On-Hip */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC__CYCLING = 1152, /**< Generic Cycling */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_CYCLING_COMPUTER = 1153, /**< Cycling Cycling Computer */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_SPEED_SENSOR = 1154, /**< Cycling Speed Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_CADENCE_SENSOR = 1155, /**< Cycling Cadence Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_POWER_SENSOR = 1156, /**< Cycling: Power Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, /**< Cycling Speed and Cadence Sensor */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_PULSE_OXIMETER = 3136, /**< Generic Pulse Oximeter */ + BLE_GAPC_APPEARANCE_CATEGORY_FINGERTIP = 3137, /**< Fingertip */ + BLE_GAPC_APPEARANCE_CATEGORY_WRIST_WORN = 3138, /**< Wrist Worn */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC__WEIGHT_SCALE = 3200, /**< Generic Weight Scale */ + BLE_GAPC_APPEARANCE_CATEGORY_GENERIC_OUTDOOR_SPORTS_ACTIVITY = 5184, /**< Generic Outdoor Sports Activity */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_DISPLAY_DEVICE = 5185, /**< Location Display Device */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, /**< Location and Navigation Display Device */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_POD = 5187, /**< Location Pod */ + BLE_GAPC_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_POD = 5188, /**< Location and Navigation Pod */ +} e_ble_appearance_category_t; + +/***************************************************************************//** + * @brief Appearance attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_appearance_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Appearance characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadAppearance(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Appearance attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetAppearanceAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_appearance_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_PER_PREF_CONN_PARAM_UUID (0x2A04) +#define BLE_GAPC_PER_PREF_CONN_PARAM_LEN (8) +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters value structure. +*******************************************************************************/ +typedef struct { + uint16_t min_conn_intv; /**< Minimum Connection Interval */ + uint16_t max_conn_intv; /**< Maximum Connection Interval */ + uint16_t slave_latency; /**< Slave Latency */ + uint16_t conn_sup_timeout_multiplier; /**< Connection Supervision Timeout Multiplier */ +} st_ble_gapc_per_pref_conn_param_t; + +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_per_pref_conn_param_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Peripheral Preferred Connection Parameters characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadPerPrefConnParam(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Peripheral Preferred Connection Parameters attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetPerPrefConnParamAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_per_pref_conn_param_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_CENT_ADDR_RSLV_UUID (0x2AA6) +#define BLE_GAPC_CENT_ADDR_RSLV_LEN (1) +/***************************************************************************//** + * @brief Central Address Resolution attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_cent_addr_rslv_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Central Address Resolution characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadCentAddrRslv(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Central Address Resolution attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetCentAddrRslvAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_cent_addr_rslv_attr_hdl_t *p_hdl); + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +#define BLE_GAPC_RSLV_PRIV_ADDR_ONLY_UUID (0x2AC9) +#define BLE_GAPC_RSLV_PRIV_ADDR_ONLY_LEN (1) +/***************************************************************************//** + * @brief Resolvable Private Address Only attribute handle value. +*******************************************************************************/ +typedef struct { + st_ble_gatt_hdl_range_t range; +} st_ble_gapc_rslv_priv_addr_only_attr_hdl_t; + +/***************************************************************************//** + * @brief Read Resolvable Private Address Only characteristic value from the remote GATT database. + * @param[in] conn_hdl Connection handle. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_ReadRslvPrivAddrOnly(uint16_t conn_hdl); + +/***************************************************************************//** + * @brief Get Resolvable Private Address Only attribute handles. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_GetRslvPrivAddrOnlyAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gapc_rslv_priv_addr_only_attr_hdl_t *p_hdl); + + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access Client +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Access client event data. +*******************************************************************************/ +typedef struct { + uint16_t conn_hdl; /**< Connection handle */ + uint16_t param_len; /**< Event parameter length */ + const void *p_param; /**< Event parameter */ +} st_ble_gapc_evt_data_t; + +/***************************************************************************//** + * @brief Generic Access characteristic ID. +*******************************************************************************/ +typedef enum { + BLE_GAPC_DEV_NAME_IDX, + BLE_GAPC_APPEARANCE_IDX, + BLE_GAPC_PER_PREF_CONN_PARAM_IDX, + BLE_GAPC_CENT_ADDR_RSLV_IDX, + BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, +} st_ble_gapc_char_idx_t; + +/***************************************************************************//** + * @brief Generic Access client event type. +*******************************************************************************/ +typedef enum { + /* Device Name */ + BLE_GAPC_EVENT_DEV_NAME_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_DEV_NAME_IDX, BLE_SERVC_READ_RSP), + BLE_GAPC_EVENT_DEV_NAME_WRITE_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_DEV_NAME_IDX, BLE_SERVC_WRITE_RSP), + /* Appearance */ + BLE_GAPC_EVENT_APPEARANCE_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_APPEARANCE_IDX, BLE_SERVC_READ_RSP), + /* Peripheral Preferred Connection Parameters */ + BLE_GAPC_EVENT_PER_PREF_CONN_PARAM_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_PER_PREF_CONN_PARAM_IDX, BLE_SERVC_READ_RSP), + /* Central Address Resolution */ + BLE_GAPC_EVENT_CENT_ADDR_RSLV_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_CENT_ADDR_RSLV_IDX, BLE_SERVC_READ_RSP), + /* Resolvable Private Address Only */ + BLE_GAPC_EVENT_RSLV_PRIV_ADDR_ONLY_READ_RSP = BLE_SERVC_ATTR_EVENT(BLE_GAPC_RSLV_PRIV_ADDR_ONLY_IDX, BLE_SERVC_READ_RSP), +} e_ble_gapc_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Access client. + * @param[in] cb Client callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPC_Init(ble_servc_app_cb_t cb); + +/***************************************************************************//** + * @brief Generic Access client discovery callback. + * @param[in] conn_hdl Connection handle + * @param[in] serv_idx Service instance index. + * @param[in] type Service discovery event type. + * @param[in] p_param Service discovery event parameter. + * @return @ref ble_status_t +*******************************************************************************/ +void R_BLE_GAPC_ServDiscCb(uint16_t conn_hdl, uint8_t serv_idx, uint16_t type, void *p_param); + +/***************************************************************************//** + * @brief Get Generic Access client attribute handle. + * @param[in] p_addr Bluetooth device address for the attribute handles. + * @param[out] p_hdl The pointer to store the retrieved attribute handles. +*******************************************************************************/ +void R_BLE_GAPC_GetServAttrHdl(const st_ble_dev_addr_t *p_addr, st_ble_gatt_hdl_range_t *p_hdl); + +#endif /* R_BLE_GAPC_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.c new file mode 100644 index 0000000000..d7ecd40fb7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.c @@ -0,0 +1,251 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gaps.c + * Version : 1.0 + * Description : The source file for Generic Access service. + **********************************************************************************************************************/ +#include +#include "r_ble_gaps.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gaps_dev_name_t(st_ble_gaps_dev_name_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPS_DEV_NAME_NAME_LEN < p_gatt_value->value_len) + { + return BLE_ERR_INVALID_DATA; + } + + memset(p_app_value->name, 0x00, BLE_GAPS_DEV_NAME_NAME_LEN); + + strcpy(p_app_value->name, (char *)p_gatt_value->p_value); + p_app_value->length = (uint8_t)p_gatt_value->value_len; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gaps_dev_name_t(const st_ble_gaps_dev_name_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + if (BLE_GAPS_DEV_NAME_NAME_LEN < p_app_value->length) + { + return BLE_ERR_INVALID_DATA; + } + + strncpy((char *)p_gatt_value->p_value, p_app_value->name, p_app_value->length); + + return BLE_SUCCESS; +} + +/* Device Name characteristic definition */ +static const st_ble_servs_char_info_t gs_dev_name_char = { + .start_hdl = BLE_GAPS_DEV_NAME_DECL_HDL, + .end_hdl = BLE_GAPS_DEV_NAME_VAL_HDL, + .char_idx = BLE_GAPS_DEV_NAME_IDX, + .app_size = sizeof(st_ble_gaps_dev_name_t), + .db_size = BLE_GAPS_DEV_NAME_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gaps_dev_name_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gaps_dev_name_t, +}; + +ble_status_t R_BLE_GAPS_SetDevName(const st_ble_gaps_dev_name_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_dev_name_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetDevName(st_ble_gaps_dev_name_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_dev_name_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Appearance characteristic definition */ +static const st_ble_servs_char_info_t gs_appearance_char = { + .start_hdl = BLE_GAPS_APPEARANCE_DECL_HDL, + .end_hdl = BLE_GAPS_APPEARANCE_VAL_HDL, + .char_idx = BLE_GAPS_APPEARANCE_IDX, + .app_size = sizeof(uint16_t), + .db_size = BLE_GAPS_APPEARANCE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GAPS_SetAppearance(const uint16_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_appearance_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetAppearance(uint16_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_appearance_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gaps_per_pref_conn_param_t(st_ble_gaps_per_pref_conn_param_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GAPS_PER_PREF_CONN_PARAM_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->min_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->max_conn_intv, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->slave_latency, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->conn_sup_timeout_multiplier, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gaps_per_pref_conn_param_t(const st_ble_gaps_per_pref_conn_param_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->min_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->max_conn_intv); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->slave_latency); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->conn_sup_timeout_multiplier); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Peripheral Preferred Connection Parameters characteristic definition */ +static const st_ble_servs_char_info_t gs_per_pref_conn_param_char = { + .start_hdl = BLE_GAPS_PER_PREF_CONN_PARAM_DECL_HDL, + .end_hdl = BLE_GAPS_PER_PREF_CONN_PARAM_VAL_HDL, + .char_idx = BLE_GAPS_PER_PREF_CONN_PARAM_IDX, + .app_size = sizeof(st_ble_gaps_per_pref_conn_param_t), + .db_size = BLE_GAPS_PER_PREF_CONN_PARAM_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gaps_per_pref_conn_param_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gaps_per_pref_conn_param_t, +}; + +ble_status_t R_BLE_GAPS_SetPerPrefConnParam(const st_ble_gaps_per_pref_conn_param_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_per_pref_conn_param_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetPerPrefConnParam(st_ble_gaps_per_pref_conn_param_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_per_pref_conn_param_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Central Address Resolution characteristic definition */ +static const st_ble_servs_char_info_t gs_cent_addr_rslv_char = { + .start_hdl = BLE_GAPS_CENT_ADDR_RSLV_DECL_HDL, + .end_hdl = BLE_GAPS_CENT_ADDR_RSLV_VAL_HDL, + .char_idx = BLE_GAPS_CENT_ADDR_RSLV_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_GAPS_CENT_ADDR_RSLV_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPS_SetCentAddrRslv(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_cent_addr_rslv_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetCentAddrRslv(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_cent_addr_rslv_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Resolvable Private Address Only characteristic definition */ +static const st_ble_servs_char_info_t gs_rslv_priv_addr_only_char = { + .start_hdl = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_DECL_HDL, + .end_hdl = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_VAL_HDL, + .char_idx = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_GAPS_RSLV_PRIV_ADDR_ONLY_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_GAPS_SetRslvPrivAddrOnly(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_rslv_priv_addr_only_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GAPS_GetRslvPrivAddrOnly(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_rslv_priv_addr_only_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access server +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Access characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_dev_name_char, + &gs_appearance_char, + &gs_per_pref_conn_param_char, + &gs_cent_addr_rslv_char, + &gs_rslv_priv_addr_only_char, +}; + +/* Generic Access service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_GAPS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.h new file mode 100644 index 0000000000..f1d66acb7c --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gaps.h @@ -0,0 +1,245 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gaps.h + * Version : 1.0 + * Description : The header file for Generic Access service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gaps Generic Access Service + * @{ + * @ingroup profile + * @brief The generic_access service contains generic information about the device. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_GAPS_H +#define R_BLE_GAPS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Device Name Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/** Name Length */ +#define BLE_GAPS_DEV_NAME_NAME_LEN (100) + +/***************************************************************************//** + * @brief Device Name value structure. +*******************************************************************************/ +typedef struct { + char name[BLE_GAPS_DEV_NAME_NAME_LEN]; /**< Name */ + uint8_t length; /**< Length */ +} st_ble_gaps_dev_name_t; + +/***************************************************************************//** + * @brief Set Device Name characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetDevName(const st_ble_gaps_dev_name_t *p_value); + +/***************************************************************************//** + * @brief Get Device Name characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetDevName(st_ble_gaps_dev_name_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Appearance Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Appearance Category enumeration. +*******************************************************************************/ +typedef enum { + BLE_GAPS_APPEARANCE_CATEGORY_UNKNOWN = 0, /**< Unknown */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_PHONE = 64, /**< Generic Phone */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_COMPUTER = 128, /**< Generic Computer */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_WATCH = 192, /**< Generic Watch */ + BLE_GAPS_APPEARANCE_CATEGORY_WATCH_SPORTS_WATCH = 193, /**< Watch: Sports Watch */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_CLOCK = 256, /**< Generic Clock */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_DISPLAY = 320, /**< Generic Display */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_REMOTE_CONTROL = 384, /**< Generic Remote Control */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_EYE_GLASSES = 448, /**< Generic Eye-glasses */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_TAG = 512, /**< Generic Tag */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_KEYRING = 576, /**< Generic Keyring */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_MEDIA_PLAYER = 640, /**< Generic Media Player */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_BARCODE_SCANNER = 704, /**< Generic Barcode Scanner */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_THERMOMETER = 768, /**< Generic Thermometer */ + BLE_GAPS_APPEARANCE_CATEGORY_THERMOMETER_EAR = 769, /**< Thermometer Ear */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_HEART_RATE_SENSOR = 832, /**< Generic Heart rate Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_HEART_RATE_SENSOR_HEART_RATE_BELT = 833, /**< Heart Rate Sensor Heart Rate Belt */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_BLOOD_PRESSURE = 896, /**< Generic Blood Pressure */ + BLE_GAPS_APPEARANCE_CATEGORY_BLOOD_PRESSURE_ARM = 897, /**< Blood Pressure: Arm */ + BLE_GAPS_APPEARANCE_CATEGORY_BLOOD_PRESSURE_WRIST = 898, /**< Blood Pressure: Wrist */ + BLE_GAPS_APPEARANCE_CATEGORY_HUMAN_INTERFACE_DEVICE = 960, /**< Human Interface Device (HID) */ + BLE_GAPS_APPEARANCE_CATEGORY_KEYBOARD = 961, /**< Keyboard */ + BLE_GAPS_APPEARANCE_CATEGORY_MOUSE = 962, /**< Mouse */ + BLE_GAPS_APPEARANCE_CATEGORY_JOYSTICK = 963, /**< Joystick */ + BLE_GAPS_APPEARANCE_CATEGORY_GAMEPAD = 964, /**< Gamepad */ + BLE_GAPS_APPEARANCE_CATEGORY_DIGITIZER_TABLET = 965, /**< Digitizer Tablet */ + BLE_GAPS_APPEARANCE_CATEGORY_CARD_READER = 966, /**< Card Reader */ + BLE_GAPS_APPEARANCE_CATEGORY_DIGITAL_PEN = 967, /**< Digital Pen */ + BLE_GAPS_APPEARANCE_CATEGORY_BARCODE_SCANNER = 968, /**< Barcode Scanner */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_GLUCOSE_METER = 1024, /**< Generic Glucose Meter */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_RUNNING_WALKING_SENSOR = 1088, /**< Generic: Running Walking Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_IN_SHOE = 1089, /**< Running Walking Sensor: In-Shoe */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_SHOE = 1090, /**< Running Walking Sensor: On-Shoe */ + BLE_GAPS_APPEARANCE_CATEGORY_RUNNING_WALKING_SENSOR_ON_HIP = 1091, /**< Running Walking Sensor: On-Hip */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC__CYCLING = 1152, /**< Generic Cycling */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_CYCLING_COMPUTER = 1153, /**< Cycling Cycling Computer */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_SPEED_SENSOR = 1154, /**< Cycling Speed Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_CADENCE_SENSOR = 1155, /**< Cycling Cadence Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_POWER_SENSOR = 1156, /**< Cycling: Power Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, /**< Cycling Speed and Cadence Sensor */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_PULSE_OXIMETER = 3136, /**< Generic Pulse Oximeter */ + BLE_GAPS_APPEARANCE_CATEGORY_FINGERTIP = 3137, /**< Fingertip */ + BLE_GAPS_APPEARANCE_CATEGORY_WRIST_WORN = 3138, /**< Wrist Worn */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC__WEIGHT_SCALE = 3200, /**< Generic Weight Scale */ + BLE_GAPS_APPEARANCE_CATEGORY_GENERIC_OUTDOOR_SPORTS_ACTIVITY = 5184, /**< Generic Outdoor Sports Activity */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_DISPLAY_DEVICE = 5185, /**< Location Display Device */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, /**< Location and Navigation Display Device */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_POD = 5187, /**< Location Pod */ + BLE_GAPS_APPEARANCE_CATEGORY_LOCATION_AND_NAVIGATION_POD = 5188, /**< Location and Navigation Pod */ +} e_ble_appearance_category_t; + +/***************************************************************************//** + * @brief Set Appearance characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetAppearance(const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Appearance characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetAppearance(uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Peripheral Preferred Connection Parameters Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Peripheral Preferred Connection Parameters value structure. +*******************************************************************************/ +typedef struct { + uint16_t min_conn_intv; /**< Minimum Connection Interval */ + uint16_t max_conn_intv; /**< Maximum Connection Interval */ + uint16_t slave_latency; /**< Slave Latency */ + uint16_t conn_sup_timeout_multiplier; /**< Connection Supervision Timeout Multiplier */ +} st_ble_gaps_per_pref_conn_param_t; + +/***************************************************************************//** + * @brief Set Peripheral Preferred Connection Parameters characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetPerPrefConnParam(const st_ble_gaps_per_pref_conn_param_t *p_value); + +/***************************************************************************//** + * @brief Get Peripheral Preferred Connection Parameters characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetPerPrefConnParam(st_ble_gaps_per_pref_conn_param_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Central Address Resolution Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set Central Address Resolution characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetCentAddrRslv(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get Central Address Resolution characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetCentAddrRslv(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Resolvable Private Address Only Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set Resolvable Private Address Only characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_SetRslvPrivAddrOnly(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get Resolvable Private Address Only characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_GetRslvPrivAddrOnly(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Access Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Access characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_GAPS_DEV_NAME_IDX, + BLE_GAPS_APPEARANCE_IDX, + BLE_GAPS_PER_PREF_CONN_PARAM_IDX, + BLE_GAPS_CENT_ADDR_RSLV_IDX, + BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, +} st_ble_gaps_char_idx_t; + +/***************************************************************************//** + * @brief Generic Access event type. +*******************************************************************************/ +typedef enum { + /* Device Name */ + BLE_GAPS_EVENT_DEV_NAME_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_WRITE_REQ), + BLE_GAPS_EVENT_DEV_NAME_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_WRITE_COMP), + BLE_GAPS_EVENT_DEV_NAME_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_DEV_NAME_IDX, BLE_SERVS_READ_REQ), + /* Appearance */ + BLE_GAPS_EVENT_APPEARANCE_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_APPEARANCE_IDX, BLE_SERVS_READ_REQ), + /* Peripheral Preferred Connection Parameters */ + BLE_GAPS_EVENT_PER_PREF_CONN_PARAM_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_PER_PREF_CONN_PARAM_IDX, BLE_SERVS_READ_REQ), + /* Central Address Resolution */ + BLE_GAPS_EVENT_CENT_ADDR_RSLV_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_CENT_ADDR_RSLV_IDX, BLE_SERVS_READ_REQ), + /* Resolvable Private Address Only */ + BLE_GAPS_EVENT_RSLV_PRIV_ADDR_ONLY_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_GAPS_RSLV_PRIV_ADDR_ONLY_IDX, BLE_SERVS_READ_REQ), +} e_ble_gaps_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Access service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GAPS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_GAPS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.c new file mode 100644 index 0000000000..65f4e14da7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.c @@ -0,0 +1,137 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gats.c + * Version : 1.0 + * Description : The source file for Generic Attribute service. + **********************************************************************************************************************/ + +#include "r_ble_gats.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed Client Characteristic Configuration descriptor +----------------------------------------------------------------------------------------------------------------------*/ + +static const st_ble_servs_desc_info_t gs_serv_changed_cli_cnfg = { + .attr_hdl = BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL, + .app_size = sizeof(uint16_t), + .desc_idx = BLE_GATS_SERV_CHGED_CLI_CNFG_IDX, + .db_size = BLE_GATS_SERV_CHGED_CLI_CNFG_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_GATS_SetServChangedCliCnfg(const uint16_t *p_value) +{ + return R_BLE_SERVS_SetDesc(&gs_serv_changed_cli_cnfg, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_GATS_GetServChangedCliCnfg(uint16_t *p_value) +{ + return R_BLE_SERVS_GetDesc(&gs_serv_changed_cli_cnfg, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +static ble_status_t decode_st_ble_gats_serv_changed_t(st_ble_gats_serv_changed_t *p_app_value, const st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + if (p_gatt_value->value_len < BLE_GATS_SERV_CHGED_LEN) + { + return BLE_ERR_INVALID_DATA; + } + + BT_UNPACK_LE_2_BYTE(&p_app_value->start_hdl, &p_gatt_value->p_value[pos]); + pos += 2; + BT_UNPACK_LE_2_BYTE(&p_app_value->end_hdl, &p_gatt_value->p_value[pos]); + pos += 2; + + return BLE_SUCCESS; +} + +static ble_status_t encode_st_ble_gats_serv_changed_t(const st_ble_gats_serv_changed_t *p_app_value, st_ble_gatt_value_t *p_gatt_value) +{ + uint32_t pos = 0; + + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->start_hdl); + pos += 2; + BT_PACK_LE_2_BYTE(&p_gatt_value->p_value[pos], &p_app_value->end_hdl); + pos += 2; + + p_gatt_value->value_len = (uint16_t)pos; + + return BLE_SUCCESS; +} + +/* Service Changed characteristic descriptor definition */ +static const st_ble_servs_desc_info_t *gspp_serv_changed_descs[] = { + &gs_serv_changed_cli_cnfg, +}; + +/* Service Changed characteristic definition */ +static const st_ble_servs_char_info_t gs_serv_changed_char = { + .start_hdl = BLE_GATS_SERV_CHGED_DECL_HDL, + .end_hdl = BLE_GATS_SERV_CHGED_CLI_CNFG_DESC_HDL, + .char_idx = BLE_GATS_SERV_CHGED_IDX, + .app_size = sizeof(st_ble_gats_serv_changed_t), + .db_size = BLE_GATS_SERV_CHGED_LEN, + .decode = (ble_servs_attr_decode_t)decode_st_ble_gats_serv_changed_t, + .encode = (ble_servs_attr_encode_t)encode_st_ble_gats_serv_changed_t, + .pp_descs = gspp_serv_changed_descs, + .num_of_descs = ARRAY_SIZE(gspp_serv_changed_descs), +}; + +ble_status_t R_BLE_GATS_IndicateServChanged(uint16_t conn_hdl, const st_ble_gats_serv_changed_t *p_value) +{ + return R_BLE_SERVS_SendHdlVal(&gs_serv_changed_char, conn_hdl, (const void *)p_value, false); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Attribute server +----------------------------------------------------------------------------------------------------------------------*/ + +/* Generic Attribute characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_serv_changed_char, +}; + +/* Generic Attribute service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_GATS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.h new file mode 100644 index 0000000000..2ba7f64500 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_gats.h @@ -0,0 +1,105 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_gats.h + * Version : 1.0 + * Description : The header file for Generic Attribute service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup gats Generic Attribute Service + * @{ + * @ingroup profile + * @brief The Generic Attribute Service contains generic information of the GATT attributes. + **********************************************************************************************************************/ +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_GATS_H +#define R_BLE_GATS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Service Changed Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Service Changed value structure. +*******************************************************************************/ +typedef struct { + uint16_t start_hdl; /**< Start of Affected Attribute Handle Range */ + uint16_t end_hdl; /**< End of Affected Attribute Handle Range */ +} st_ble_gats_serv_changed_t; + +/***************************************************************************//** + * @brief Send indication of Service Changed characteristic value to the remote device. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Characteristic value to send. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_IndicateServChanged(uint16_t conn_hdl, const st_ble_gats_serv_changed_t *p_value); + +/***************************************************************************//** + * @brief Set Service Changed cli cnfg descriptor value to the local GATT database. + * @param[in] p_value Descriptor value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_SetServChangedCliCnfg(const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Service Changed cli cnfg descriptor value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_GetServChangedCliCnfg(uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + Generic Attribute Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Generic Attribute characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_GATS_SERV_CHGED_IDX, + BLE_GATS_SERV_CHGED_CLI_CNFG_IDX, +} st_ble_gats_char_idx_t; + +/***************************************************************************//** + * @brief Generic Attribute event type. +*******************************************************************************/ +typedef enum { + /* Service Changed */ + BLE_GATS_EVENT_SERV_CHGED_HDL_VAL_CNF = BLE_SERVS_ATTR_EVENT(BLE_GATS_SERV_CHGED_IDX, BLE_SERVS_HDL_VAL_CNF), +} e_ble_gats_event_t; + +/***************************************************************************//** + * @brief Initialize Generic Attribute service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_GATS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_GATS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.c new file mode 100644 index 0000000000..734cbc9d90 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.c @@ -0,0 +1,132 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_lss.c + * Version : 1.0 + * Description : The source file for LED Switch service. + **********************************************************************************************************************/ + +#include "r_ble_lss.h" +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +static st_ble_servs_info_t gs_servs_info; + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State Client Characteristic Configuration descriptor +----------------------------------------------------------------------------------------------------------------------*/ + +static const st_ble_servs_desc_info_t gs_switch_state_cli_cnfg = { + .attr_hdl = BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL, + .app_size = sizeof(uint16_t), + .desc_idx = BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, + .db_size = BLE_LSS_SWITCH_STATE_CLI_CNFG_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint16_t, + .encode = (ble_servs_attr_encode_t)encode_uint16_t, +}; + +ble_status_t R_BLE_LSS_SetSwitchStateCliCnfg(uint16_t conn_hdl, const uint16_t *p_value) +{ + return R_BLE_SERVS_SetDesc(&gs_switch_state_cli_cnfg, conn_hdl, (const void *)p_value); +} + +ble_status_t R_BLE_LSS_GetSwitchStateCliCnfg(uint16_t conn_hdl, uint16_t *p_value) +{ + return R_BLE_SERVS_GetDesc(&gs_switch_state_cli_cnfg, conn_hdl, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* Switch State characteristic descriptor definition */ +static const st_ble_servs_desc_info_t *gspp_switch_state_descs[] = { + &gs_switch_state_cli_cnfg, +}; + +/* Switch State characteristic definition */ +static const st_ble_servs_char_info_t gs_switch_state_char = { + .start_hdl = BLE_LSS_SWITCH_STATE_DECL_HDL, + .end_hdl = BLE_LSS_SWITCH_STATE_CLI_CNFG_DESC_HDL, + .char_idx = BLE_LSS_SWITCH_STATE_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_LSS_SWITCH_STATE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, + .pp_descs = gspp_switch_state_descs, + .num_of_descs = ARRAY_SIZE(gspp_switch_state_descs), +}; + +ble_status_t R_BLE_LSS_NotifySwitchState(uint16_t conn_hdl, const uint8_t *p_value) +{ + return R_BLE_SERVS_SendHdlVal(&gs_switch_state_char, conn_hdl, (const void *)p_value, true); +} + +/*---------------------------------------------------------------------------------------------------------------------- + LED Blink Rate characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/* LED Blink Rate characteristic definition */ +static const st_ble_servs_char_info_t gs_blink_rate_char = { + .start_hdl = BLE_LSS_BLINK_RATE_DECL_HDL, + .end_hdl = BLE_LSS_BLINK_RATE_VAL_HDL, + .char_idx = BLE_LSS_BLINK_RATE_IDX, + .app_size = sizeof(uint8_t), + .db_size = BLE_LSS_BLINK_RATE_LEN, + .decode = (ble_servs_attr_decode_t)decode_uint8_t, + .encode = (ble_servs_attr_encode_t)encode_uint8_t, +}; + +ble_status_t R_BLE_LSS_SetBlinkRate(const uint8_t *p_value) +{ + return R_BLE_SERVS_SetChar(&gs_blink_rate_char, BLE_GAP_INVALID_CONN_HDL, (const void *)p_value); +} + +ble_status_t R_BLE_LSS_GetBlinkRate(uint8_t *p_value) +{ + return R_BLE_SERVS_GetChar(&gs_blink_rate_char, BLE_GAP_INVALID_CONN_HDL, (void *)p_value); +} + +/*---------------------------------------------------------------------------------------------------------------------- + LED Switch server +----------------------------------------------------------------------------------------------------------------------*/ + +/* LED Switch characteristics definition */ +static const st_ble_servs_char_info_t *gspp_chars[] = { + &gs_switch_state_char, + &gs_blink_rate_char, +}; + +/* LED Switch service definition */ +static st_ble_servs_info_t gs_servs_info = { + .pp_chars = gspp_chars, + .num_of_chars = ARRAY_SIZE(gspp_chars), +}; + +ble_status_t R_BLE_LSS_Init(ble_servs_app_cb_t cb) +{ + if (NULL == cb) + { + return BLE_ERR_INVALID_PTR; + } + + gs_servs_info.cb = cb; + + return R_BLE_SERVS_RegisterServer(&gs_servs_info); +} diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.h new file mode 100644 index 0000000000..a1a7607509 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/qe_gen/ble/r_ble_lss.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * File Name: r_ble_lss.h + * Version : 1.0 + * Description : The header file for LED Switch service. + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.12.2999 1.00 First Release + ***********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @file + * @defgroup lss LED Switch Service + * @{ + * @ingroup profile + * @brief This service exposes a control point to allow a peer device to control LEDs and switched on the device. + **********************************************************************************************************************/ + +#include "profile_cmn/r_ble_servs_if.h" +#include "gatt_db.h" + +#ifndef R_BLE_LSS_H +#define R_BLE_LSS_H + +/*---------------------------------------------------------------------------------------------------------------------- + Switch State Characteristic +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief Send notification of Switch State characteristic value to the remote device. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Characteristic value to send. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_NotifySwitchState(uint16_t conn_hdl, const uint8_t *p_value); + +/***************************************************************************//** + * @brief Set Switch State cli cnfg descriptor value to the local GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Descriptor value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_SetSwitchStateCliCnfg(uint16_t conn_hdl, const uint16_t *p_value); + +/***************************************************************************//** + * @brief Get Switch State cli cnfg descriptor value from the local GATT database. + * @param[in] conn_hdl Connection handle. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_GetSwitchStateCliCnfg(uint16_t conn_hdl, uint16_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + LED Blink Rate Characteristic +----------------------------------------------------------------------------------------------------------------------*/ +/***************************************************************************//** + * @brief Set LED Blink Rate characteristic value to the local GATT database. + * @param[in] p_value Characteristic value to set. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_SetBlinkRate(const uint8_t *p_value); + +/***************************************************************************//** + * @brief Get LED Blink Rate characteristic value from the local GATT database. + * @param[in] p_value Output location for the acquired descriptor value. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_GetBlinkRate(uint8_t *p_value); + +/*---------------------------------------------------------------------------------------------------------------------- + LED Switch Service +----------------------------------------------------------------------------------------------------------------------*/ + +/***************************************************************************//** + * @brief LED Switch characteristic Index. +*******************************************************************************/ +typedef enum { + BLE_LSS_SWITCH_STATE_IDX, + BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, + BLE_LSS_BLINK_RATE_IDX, +} e_ble_lss_char_idx_t; + +/***************************************************************************//** + * @brief LED Switch event type. +*******************************************************************************/ +typedef enum { + /* Switch State */ + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_WRITE_REQ), + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_WRITE_COMP), + BLE_LSS_EVENT_SWITCH_STATE_CLI_CNFG_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_SWITCH_STATE_CLI_CNFG_IDX, BLE_SERVS_READ_REQ), + /* LED Blink Rate */ + BLE_LSS_EVENT_BLINK_RATE_WRITE_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_WRITE_REQ), + BLE_LSS_EVENT_BLINK_RATE_WRITE_COMP = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_WRITE_COMP), + BLE_LSS_EVENT_BLINK_RATE_READ_REQ = BLE_SERVS_ATTR_EVENT(BLE_LSS_BLINK_RATE_IDX, BLE_SERVS_READ_REQ), +} e_ble_lss_event_t; + +/***************************************************************************//** + * @brief Initialize LED Switch service. + * @param[in] cb Service callback. + * @return @ref ble_status_t +*******************************************************************************/ +ble_status_t R_BLE_LSS_Init(ble_servs_app_cb_t cb); + +#endif /* R_BLE_LSS_H */ + +/** @} */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/event_groups.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/event_groups.c new file mode 100644 index 0000000000..090bf11659 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/event_groups.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t const * const pxEventBits = xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t const * pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/FreeRTOS.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/FreeRTOS.h new file mode 100644 index 0000000000..a3946b6756 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/FreeRTOS.h @@ -0,0 +1,1295 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. +The CBMC proofs need a way to track assumptions and assertions. +A configPRECONDITION statement should express an implicit invariant or +assumption made. A configASSERT statement should express an invariant that must +hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT(X) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void *pvDummy5; + TaskFunction_t pvDummy6; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/atomic.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/atomic.h new file mode 100644 index 0000000000..d4f87f96c1 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/atomic.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + + /* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + + /* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ +uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ +void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ +uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ATOMIC_H */ diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/deprecated_definitions.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/deprecated_definitions.h new file mode 100644 index 0000000000..381e9f5944 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/event_groups.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/event_groups.h new file mode 100644 index 0000000000..a373561c2e --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/event_groups.h @@ -0,0 +1,757 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/list.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/list.h new file mode 100644 index 0000000000..6eaa0b8357 --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/list.h @@ -0,0 +1,412 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/message_buffer.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/message_buffer.h new file mode 100644 index 0000000000..7430039abf --- /dev/null +++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/message_buffer.h @@ -0,0 +1,803 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 

+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_prototypes.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_prototypes.h
new file mode 100644
index 0000000000..58a233055c
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_wrappers.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_wrappers.h
new file mode 100644
index 0000000000..30506cdc6c
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/portable.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/portable.h
new file mode 100644
index 0000000000..6ee3f613cb
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/projdefs.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/projdefs.h
new file mode 100644
index 0000000000..3ada620a0e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/queue.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/queue.h
new file mode 100644
index 0000000000..a10ba67fb3
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/semphr.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/semphr.h
new file mode 100644
index 0000000000..1b61f53719
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stack_macros.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stack_macros.h
new file mode 100644
index 0000000000..c9d423aec6
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stream_buffer.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stream_buffer.h
new file mode 100644
index 0000000000..d3bb267ade
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+

+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/task.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/task.h
new file mode 100644
index 0000000000..8c2a3adcb8
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.0"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
uint32_t ulTaskGetIdleRunTimeCounter( void );

+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* 
uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );

+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )

+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );

+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * 
+	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ 

+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/timers.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/timers.h
new file mode 100644
index 0000000000..4ad023d1f1
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/list.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/list.c
new file mode 100644
index 0000000000..ce493e6311
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c
new file mode 100644
index 0000000000..80b926e6e7
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/queue.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/queue.c
new file mode 100644
index 0000000000..17ffc14140
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/queue.c
@@ -0,0 +1,2945 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/stream_buffer.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/stream_buffer.c
new file mode 100644
index 0000000000..01cb556cc3
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/tasks.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/tasks.c
new file mode 100644
index 0000000000..15d123123d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/timers.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/timers.c
new file mode 100644
index 0000000000..6bd2f43532
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/aws/amazon-freertos/freertos_kernel/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board.h
new file mode 100644
index 0000000000..ddd7c672bf
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board.h
@@ -0,0 +1,72 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARDS
+ * @defgroup BOARD_RA4W1_EK BSP for the EK-RA4W1
+ * @brief BSP for the EK-RA4W1
+ *
+ * The EK-RA4W1 is a development kit for the Renesas RA Flex RA4W1 microcontroller. This board has connections
+ * for PMOD and USB as well as headers for Arduino shield modules. An onboard Bluetooth antenna is available with an
+ * optional connection for an external antenna.
+ *
+ * @note This board does not ship with main or subclock oscillators populated.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP Board Specific Includes. */
+#include "board_init.h"
+#include "board_leds.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BOARD_RA4W1_EK
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED           (0)
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT                (9)
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE        (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED           (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE               (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS    (1000U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BOARD_RA4W1_EK) */
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.c
new file mode 100644
index 0000000000..79e035fb9f
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.c
@@ -0,0 +1,62 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_EK_RA4W1_INIT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if defined(BOARD_RA4W1_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Performs any initialization specific to this BSP.
+ *
+ * @param[in]  p_args         Pointer to arguments of the user's choice.
+ **********************************************************************************************************************/
+void bsp_init (void * p_args)
+{
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#endif
+
+/** @} (end addtogroup BOARD_EK_RA4W1_INIT) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.h
new file mode 100644
index 0000000000..1355cd0724
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_init.h
@@ -0,0 +1,53 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_EK_RA4W1
+ * @defgroup BOARD_EK_RA4W1_INIT
+ * @brief Board specific code for the EK-RA4W1
+ *
+ * This include file is specific to the EK-RA4W1.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_INIT_H
+#define BOARD_INIT_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+void bsp_init(void * p_args);
+
+#endif
+
+/** @} (end defgroup BOARD_EK_RA4W1_INIT) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c
new file mode 100644
index 0000000000..a299d2b08d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.c
@@ -0,0 +1,72 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BOARD_EK_RA4W1_LEDS
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+#if defined(BOARD_RA4W1_EK)
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Array of LED IOPORT pins. */
+static const uint16_t g_bsp_prv_leds[] =
+{
+    (uint16_t) BSP_IO_PORT_01_PIN_06,  ///< LED0
+    (uint16_t) BSP_IO_PORT_04_PIN_04,  ///< LED1
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** Structure with LED information for this board. */
+
+/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */
+const bsp_leds_t g_bsp_leds =
+{
+    .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
+    .p_leds    = &g_bsp_prv_leds[0]
+};
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
+
+/** @} (end addtogroup BOARD_EK_RA4W1_LEDS) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h
new file mode 100644
index 0000000000..013d6c63b5
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/board/ra4w1_ek/board_leds.h
@@ -0,0 +1,68 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BOARD_EK_RA4W1
+ * @defgroup BOARD_EK_RA4W1_LEDS Board LEDs
+ * @brief LED information for this board.
+ *
+ * This is code specific to the EK-RA4W1. It includes info on the number of LEDs and which pins are they
+ * are on.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BOARD_LEDS_H
+#define BOARD_LEDS_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Information on how many LEDs and what pins they are on. */
+typedef struct st_bsp_leds
+{
+    uint16_t         led_count;        ///< The number of LEDs on this board
+    uint16_t const * p_leds;           ///< Pointer to an array of IOPORT pins for controlling LEDs
+} bsp_leds_t;
+
+/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
+ * found in the bsp_leds_t structure. */
+typedef enum e_bsp_led
+{
+    BSP_LED_LED0 = 0,                  ///< LED0
+    BSP_LED_LED1 = 1,                  ///< LED1
+} bsp_led_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Public Functions
+ **********************************************************************************************************************/
+
+#endif
+
+/** @} (end defgroup BOARD_EK_RA4W1_LEDS) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/bsp_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/bsp_api.h
new file mode 100644
index 0000000000..54e0465e8b
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/bsp_api.h
@@ -0,0 +1,101 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_API_H
+#define BSP_API_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/* FSP Common Includes. */
+#include "../../inc/fsp_common_api.h"
+
+/* Gets MCU configuration information. */
+#include "bsp_cfg.h"
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+
+/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
+ * We are not modifying these files so we will ignore these warnings temporarily. */
+ #pragma GCC diagnostic ignored "-Wconversion"
+ #pragma GCC diagnostic ignored "-Wsign-conversion"
+#endif
+
+/* Vector information for this project. This is generated by the tooling. */
+#include "vector_data.h"
+
+/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
+#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
+#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+
+/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
+ #pragma GCC diagnostic pop
+#endif
+
+/* BSP Common Includes. */
+#include "../../src/bsp/mcu/all/bsp_common.h"
+
+/* BSP MCU Specific Includes. */
+#include "../../src/bsp/mcu/all/bsp_register_protection.h"
+#include "../../src/bsp/mcu/all/bsp_irq.h"
+#include "../../src/bsp/mcu/all/bsp_io.h"
+#include "../../src/bsp/mcu/all/bsp_group_irq.h"
+#include "../../src/bsp/mcu/all/bsp_clocks.h"
+#include "../../src/bsp/mcu/all/bsp_module_stop.h"
+
+/* Factory MCU information. */
+#include "../../inc/fsp_features.h"
+
+/* BSP Common Includes (Other than bsp_common.h) */
+#include "../../src/bsp/mcu/all/bsp_delay.h"
+
+#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
+
+/** @} (end addtogroup BSP_MCU) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h
new file mode 100644
index 0000000000..61cbae1495
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ble_api.h
@@ -0,0 +1,12575 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup BLE_API BLE Interface
+ * @brief Interface for Bluetooth Low Energy functions.
+ *
+ * @section BLE_API_SUMMARY Summary
+ * The BLE interface for the Bluetooth Low Energy (BLE) peripheral provides Bluetooth Low Energy functionality.
+ *
+ * The Bluetooth Low Energy interface can be implemented by:
+ * - @ref BLE
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_BLE_API_H
+#define R_BLE_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+#include "r_ble_cfg.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BLE_API_VERSION_MAJOR    (1U)
+#define BLE_API_VERSION_MINOR    (0U)
+
+/* =================================================== Main Macro =================================================== */
+
+/**
+ * @def BLE_VERSION_MAJOR
+ * BLE Module Major Version.
+ */
+#define BLE_VERSION_MAJOR        (0x0000)
+
+/**
+ * @def BLE_VERSION_MINOR
+ * BLE Module Minor Version.
+ */
+#define BLE_VERSION_MINOR        (0x0009)
+
+/**
+ * @def BLE_LIB_ALL_FEATS
+ * BLE Protocol Stack Library All Features type.
+ */
+#define BLE_LIB_ALL_FEATS        (0x00)
+
+/**
+ * @def BLE_LIB_BALANCE
+ * BLE Protocol Stack Library Balance type.
+ */
+#define BLE_LIB_BALANCE          (0x01)
+
+/**
+ * @def BLE_LIB_COMPACT
+ * BLE Protocol Stack Library Compacy type.
+ */
+#define BLE_LIB_COMPACT          (0x02)
+
+/* =============================================== Spec Error Group ID ============================================== */
+#define BLE_ERR_GROUP_HC         (0x1000)
+#define BLE_ERR_GROUP_GAP        (0x2000)
+#define BLE_ERR_GROUP_GATT       (0x3000)
+#define BLE_ERR_GROUP_L2CAP      (0x4000)
+#define BLE_ERR_GROUP_VS         (0x5000)
+
+/******************************************************************************************************************//**
+ * @typedef ble_status_t
+ **********************************************************************************************************************/
+typedef uint16_t ble_status_t;
+
+/* error code */
+enum RBLE_STATUS_enum
+{
+    BLE_SUCCESS = 0x0000,
+
+    /* commom error code */
+    BLE_ERR_INVALID_PTR         = 0x0001,
+    BLE_ERR_INVALID_DATA        = 0x0002,
+    BLE_ERR_INVALID_ARG         = 0x0003,
+    BLE_ERR_INVALID_FUNC        = 0x0004,
+    BLE_ERR_INVALID_CHAN        = 0x0005,
+    BLE_ERR_INVALID_MODE        = 0x0006,
+    BLE_ERR_UNSUPPORTED         = 0x0007,
+    BLE_ERR_INVALID_STATE       = 0x0008,
+    BLE_ERR_INVALID_OPERATION   = 0x0009,
+    BLE_ERR_ALREADY_IN_PROGRESS = 0x000A,
+    BLE_ERR_CONTEXT_FULL        = 0x000B,
+    BLE_ERR_MEM_ALLOC_FAILED    = 0x000C,
+    BLE_ERR_NOT_FOUND           = 0x000D,
+    BLE_ERR_INVALID_HDL         = 0x000E,
+    BLE_ERR_DISCONNECTED        = 0x000F,
+    BLE_ERR_LIMIT_EXCEEDED      = 0x0010,
+    BLE_ERR_RSP_TIMEOUT         = 0x0011,
+    BLE_ERR_NOT_YET_READY       = 0x0012,
+    BLE_ERR_UNSPECIFIED         = 0x0013,
+
+    /* HCI Spec Error */
+    BLE_ERR_HC_UNKNOWN_HCI_CMD              = 0x1001,
+    BLE_ERR_HC_NO_CONN                      = 0x1002,
+    BLE_ERR_HC_HW_FAIL                      = 0x1003,
+    BLE_ERR_HC_PAGE_TO                      = 0x1004,
+    BLE_ERR_HC_AUTH_FAIL                    = 0x1005,
+    BLE_ERR_HC_KEY_MISSING                  = 0x1006,
+    BLE_ERR_HC_MEM_FULL                     = 0x1007,
+    BLE_ERR_HC_CONN_TO                      = 0x1008,
+    BLE_ERR_HC_MAX_NUM_OF_CONN              = 0x1009,
+    BLE_ERR_HC_MAX_NUM_OF_SCO_CONN          = 0x100A,
+    BLE_ERR_HC_ACL_CONN_ALREADY_EXISTS      = 0x100B,
+    BLE_ERR_HC_CMD_DISALLOWED               = 0x100C,
+    BLE_ERR_HC_HOST_REJ_LIMITED_RESRC       = 0x100D,
+    BLE_ERR_HC_HOST_REJ_SEC_REASONS         = 0x100E,
+    BLE_ERR_HC_HOST_REJ_PERSONAL_DEV        = 0x100F,
+    BLE_ERR_HC_HOST_TO                      = 0x1010,
+    BLE_ERR_HC_UNSPRT_FEAT_OR_PARAM         = 0x1011,
+    BLE_ERR_HC_INVALID_HCI_CMD_PARAM        = 0x1012,
+    BLE_ERR_HC_OTHER_END_TERM_USER          = 0x1013,
+    BLE_ERR_HC_OTHER_END_TERM_LOW_RESRC     = 0x1014,
+    BLE_ERR_HC_OTHER_END_TERM_PW_OFF        = 0x1015,
+    BLE_ERR_HC_CONN_TERM_BY_LOCAL_HOST      = 0x1016,
+    BLE_ERR_HC_REPEATED_ATTEMPTS            = 0x1017,
+    BLE_ERR_HC_PAIRING_NOT_ALLOWED          = 0x1018,
+    BLE_ERR_HC_UNKNOWN_LMP_PDU              = 0x1019,
+    BLE_ERR_HC_UNSPRT_REM_FEAT              = 0x101A,
+    BLE_ERR_HC_SCO_OFFSET_REJ               = 0x101B,
+    BLE_ERR_HC_SCO_INTERVAL_REJ             = 0x101C,
+    BLE_ERR_HC_SCO_AIR_MODE_REJ             = 0x101D,
+    BLE_ERR_HC_INVALID_LMP_PARAM            = 0x101E,
+    BLE_ERR_HC_UNSPECIFIED_ERR              = 0x101F,
+    BLE_ERR_HC_UNSPRT_LMP_PARAM_VAL         = 0x1020,
+    BLE_ERR_HC_ROLE_CHANGE_NOT_ALLOWED      = 0x1021,
+    BLE_ERR_HC_LMP_RSP_TO                   = 0x1022,
+    BLE_ERR_HC_LMP_ERR_TX_COLLISION         = 0x1023,
+    BLE_ERR_HC_LMP_PDU_NOT_ALLOWED          = 0x1024,
+    BLE_ERR_HC_ENC_MODE_NOT_ACCEPTABLE      = 0x1025,
+    BLE_ERR_HC_UNIT_KEY_USED                = 0x1026,
+    BLE_ERR_HC_QOS_IS_NOT_SPRT              = 0x1027,
+    BLE_ERR_HC_INSTANT_PASSED               = 0x1028,
+    BLE_ERR_HC_PAIRING_UNIT_KEY_NOT_SPRT    = 0x1029,
+    BLE_ERR_HC_DIFF_TRANSACTION_COLLISION   = 0x102A,
+    BLE_ERR_HC_QOS_UNACCEPTABLE_PARAM       = 0x102C,
+    BLE_ERR_HC_QOS_REJ                      = 0x102D,
+    BLE_ERR_HC_CH_CLASSIFICATION_NOT_SPRT   = 0x102E,
+    BLE_ERR_HC_INSUFFICIENT_SEC             = 0x102F,
+    BLE_ERR_HC_PARAM_OUT_OF_MANDATORY_RANGE = 0x1030,
+    BLE_ERR_HC_ROLE_SWITCH_PENDING          = 0x1032,
+    BLE_ERR_HC_RESERVED_SLOT_VIOLATION      = 0x1034,
+    BLE_ERR_HC_ROLE_SWITCH_FAIL             = 0x1035,
+    BLE_ERR_HC_EXT_INQUIRY_RSP_TOO_LARGE    = 0x1036,
+    BLE_ERR_HC_SSP_NOT_SPRT_BY_HOST         = 0x1037,
+    BLE_ERR_HC_HOST_BUSY_PAIRING            = 0x1038,
+    BLE_ERR_HC_CONN_REJ_NO_SUIT_CH_FOUND    = 0x1039,
+    BLE_ERR_HC_CTRL_BUSY                    = 0x103A,
+    BLE_ERR_HC_UNACCEPTEBALE_CONN_INTERVAL  = 0x103B,
+    BLE_ERR_HC_ADV_TO = 0x103C,
+    BLE_ERR_HC_CONN_TREM_DUE_TO_MIC_FAIL = 0x103D,
+    BLE_ERR_HC_CONN_FAIL_TO_BE_EST       = 0x103E,
+    BLE_ERR_HC_MAC_CONN_FAIL             = 0x103F,
+    BLE_ERR_HC_COARSE_CLK_ADJUST_REJ     = 0x1040,
+    BLE_ERR_HC_TYPE0_SUBMAP_NOT_DEFINED  = 0x1041,
+    BLE_ERR_HC_UNKNOWN_ADV_ID            = 0x1042,
+    BLE_ERR_HC_LIMIT_REACHED             = 0x1043,
+    BLE_ERR_HC_OP_CANCELLED_BY_HOST      = 0x1044,
+
+    /* SMP Spec Error */
+    BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL        = 0x2001,
+    BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE    = 0x2002,
+    BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET          = 0x2003,
+    BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH     = 0x2004,
+    BLE_ERR_SMP_LE_PAIRING_NOT_SPRT          = 0x2005,
+    BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE = 0x2006,
+    BLE_ERR_SMP_LE_CMD_NOT_SPRT              = 0x2007,
+    BLE_ERR_SMP_LE_UNSPECIFIED_REASON        = 0x2008,
+    BLE_ERR_SMP_LE_REPEATED_ATTEMPTS         = 0x2009,
+    BLE_ERR_SMP_LE_INVALID_PARAM             = 0x200A,
+    BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL          = 0x200B,
+    BLE_ERR_SMP_LE_NUM_COMP_FAIL             = 0x200C,
+    BLE_ERR_SMP_LE_BREDR_PAIRING_IN_PROGRESS = 0x200D,
+    BLE_ERR_SMP_LE_CT_KEY_GEN_NOT_ALLOWED    = 0x200E,
+    BLE_ERR_SMP_LE_DISCONNECTED              = 0x200F,
+    BLE_ERR_SMP_LE_TO              = 0x2011,
+    BLE_ERR_SMP_LE_LOC_KEY_MISSING = 0x2014,
+
+    /* GATT Spec Error */
+    BLE_ERR_GATT_INVALID_HANDLE              = 0x3001,
+    BLE_ERR_GATT_READ_NOT_PERMITTED          = 0x3002,
+    BLE_ERR_GATT_WRITE_NOT_PERMITTED         = 0x3003,
+    BLE_ERR_GATT_INVALID_PDU                 = 0x3004,
+    BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION = 0x3005,
+    BLE_ERR_GATT_REQUEST_NOT_SUPPORTED       = 0x3006,
+    BLE_ERR_GATT_INVALID_OFFSET              = 0x3007,
+    BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION  = 0x3008,
+    BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL    = 0x3009,
+    BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND         = 0x300A,
+    BLE_ERR_GATT_ATTRIBUTE_NOT_LONG          = 0x300B,
+    BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE   = 0x300C,
+    BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN       = 0x300D,
+    BLE_ERR_GATT_UNLIKELY_ERROR              = 0x300E,
+    BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION     = 0x300F,
+    BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE      = 0x3010,
+    BLE_ERR_GATT_INSUFFICIENT_RESOURCES      = 0x3011,
+
+    /* defined in CSS */
+    BLE_ERR_GATT_WRITE_REQ_REJECTED       = 0x30FC,
+    BLE_ERR_GATT_CCCD_IMPROPERLY_CFG      = 0x30FD,
+    BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS = 0x30FE,
+    BLE_ERR_GATT_OUT_OF_RANGE             = 0x30FF,
+
+    /* L2CAP Spec Error */
+    BLE_ERR_L2CAP_PSM_NOT_SUPPORTED         = 0x4002,
+    BLE_ERR_L2CAP_NO_RESOURCE               = 0x4004,
+    BLE_ERR_L2CAP_INSUF_AUTHEN              = 0x4005,
+    BLE_ERR_L2CAP_INSUF_AUTHOR              = 0x4006,
+    BLE_ERR_L2CAP_INSUF_ENC_KEY_SIZE        = 0x4007,
+    BLE_ERR_L2CAP_REFUSE_INSUF_ENC          = 0x4008,
+    BLE_ERR_L2CAP_REFUSE_INVALID_SCID       = 0x4009,
+    BLE_ERR_L2CAP_REFUSE_SCID_ALREADY_ALLOC = 0x400A,
+    BLE_ERR_L2CAP_REFUSE_UNACCEPTABLE_PARAM = 0x400B,
+};
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup BLE_API)
+ **********************************************************************************************************************/
+
+/* =================================================== GAP Macro ==================================================== */
+
+/** @addtogroup GAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/**
+ * @ingroup GAP_API
+ * @def BLE_BD_ADDR_LEN
+ * Bluetooth Device Address Size
+ */
+#define BLE_BD_ADDR_LEN                                (0x06)
+
+/**
+ * @def BLE_MASTER
+ * Master Role.
+ */
+#define BLE_MASTER                                     (0x00)
+
+/**
+ * @def BLE_SLAVE
+ * Slave Role.
+ */
+#define BLE_SLAVE                                      (0x01)
+
+/* Bluetooth Device Address Type */
+
+/**
+ * @def BLE_GAP_ADDR_PUBLIC
+ * Public Address.
+ */
+#define BLE_GAP_ADDR_PUBLIC                            (0x00)
+
+/**
+ * @def BLE_GAP_ADDR_RAND
+ * Random Address.
+ */
+#define BLE_GAP_ADDR_RAND                              (0x01)
+
+/**
+ * @def BLE_GAP_ADDR_RPA_ID_PUBLIC
+ * @brief Resolvable Private Address.
+ * @details If the IRK of local device has not been registered in Resolving List,
+ *          public address is used.
+ */
+#define BLE_GAP_ADDR_RPA_ID_PUBLIC                     (0x02)
+
+/**
+ * @def BLE_GAP_ADDR_RPA_ID_RANDOM
+ * @brief Resolvable Private Address.
+ * @details If the IRK of local device has not been registered in Resolving List,
+ *          random address is used.
+ */
+#define BLE_GAP_ADDR_RPA_ID_RANDOM                     (0x03)
+
+/* Adv Flag */
+
+/**
+ * @def BLE_GAP_AD_FLAGS_LE_LIM_DISC_MODE
+ * @brief LE Limited Discoverable Mode flag used in AD type.
+ */
+#define BLE_GAP_AD_FLAGS_LE_LIM_DISC_MODE              (0x01)
+
+/**
+ * @def BLE_GAP_AD_FLAGS_LE_GEN_DISC_MODE
+ * @brief LE General Discoverable Mode flag used in AD type.
+ */
+#define BLE_GAP_AD_FLAGS_LE_GEN_DISC_MODE              (0x02)
+
+/**
+ * @def BLE_GAP_AD_FLAGS_BR_EDR_NOT_SUPPORTED
+ * @brief BR/EDR Not Supported flag used in AD type.
+ */
+#define BLE_GAP_AD_FLAGS_BR_EDR_NOT_SUPPORTED          (0x04)
+
+/**
+ * @def BLE_GAP_ADV_DATA_MODE
+ * @brief Advertising data.
+ */
+#define BLE_GAP_ADV_DATA_MODE                          (0x00)
+
+/**
+ * @def BLE_GAP_SCAN_RSP_DATA_MODE
+ * @brief Scan response data.
+ */
+#define BLE_GAP_SCAN_RSP_DATA_MODE                     (0x01)
+
+/**
+ * @def BLE_GAP_PERD_ADV_DATA_MODE
+ * @brief Periodic advertising data.
+ */
+#define BLE_GAP_PERD_ADV_DATA_MODE                     (0x02)
+
+/* Advertising channel map */
+
+/**
+ * @def BLE_GAP_ADV_CH_37
+ * @brief Use 37 CH.
+ */
+#define BLE_GAP_ADV_CH_37                              (0x01)
+
+/**
+ * @def BLE_GAP_ADV_CH_38
+ * @brief Use 38 CH.
+ */
+#define BLE_GAP_ADV_CH_38                              (0x02)
+
+/**
+ * @def BLE_GAP_ADV_CH_39
+ * @brief Use 39 CH.
+ */
+#define BLE_GAP_ADV_CH_39                              (0x04)
+
+/**
+ * @def BLE_GAP_ADV_CH_ALL
+ * @brief Use 37 - 39 CH.
+ */
+#define BLE_GAP_ADV_CH_ALL                             (0x07)
+
+/* Scan Type */
+
+/**
+ * @def BLE_GAP_SCAN_PASSIVE
+ * @brief Passive Scan.
+ */
+#define BLE_GAP_SCAN_PASSIVE                           (0x00)
+
+/**
+ * @def BLE_GAP_SCAN_ACTIVE
+ * @brief Active Scan.
+ */
+#define BLE_GAP_SCAN_ACTIVE                            (0x01)
+
+/*  Scan interval */
+
+/**
+ * @def BLE_GAP_SCAN_INTV_MIN
+ * @brief Active Scan.
+ */
+#define BLE_GAP_SCAN_INTV_MIN                          (0x0004)
+
+/*  Filter duplicates */
+
+/**
+ * @def BLE_GAP_SCAN_FILT_DUPLIC_DISABLE
+ * @brief Duplicate filter disabled.
+ */
+#define BLE_GAP_SCAN_FILT_DUPLIC_DISABLE               (0x00)
+
+/**
+ * @def BLE_GAP_SCAN_FILT_DUPLIC_ENABLE
+ * @brief Duplicate filter enabled.
+ */
+#define BLE_GAP_SCAN_FILT_DUPLIC_ENABLE                (0x01)
+
+/**
+ * @def BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD
+ * @brief Duplicate filtering enabled, reset for each scan period.
+ */
+#define BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD     (0x02)
+
+/*   Scan filter policy */
+
+/**
+ * @def BLE_GAP_SCAN_ALLOW_ADV_ALL
+ * @brief Accept all advertising and scan response PDUs except directed advertising PDUs not addressed to local device.
+ */
+#define BLE_GAP_SCAN_ALLOW_ADV_ALL                     (0x00)
+
+/**
+ * @def BLE_GAP_SCAN_ALLOW_ADV_WLST
+ * @brief Accept only advertising and scan response PDUs from remote devices
+ *        whose address is registered in the White List.
+ *        Directed advertising PDUs which are not addressed to local device is ignored.
+ */
+#define BLE_GAP_SCAN_ALLOW_ADV_WLST                    (0x01)
+
+/**
+ * @def BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED
+ * @brief Accept all advertising and scan response PDUs except directed advertising PDUs
+ *        whose the target address is identity address but doesn't address local device.
+ *        However directed advertising PDUs whose the target address is the local resolvable private address
+ *        are accepted.
+ */
+#define BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED         (0x02)
+
+/**
+ * @def BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST
+ * @brief Accept all advertising and scan response PDUs.

+ *        The following are excluded.
+ *        - Advertising and scan response PDUs where the advertiser's identity address is not in the White List.
+ *        - Directed advertising PDUs whose the target address is identity address
+ *          but doesn't address local device. However directed advertising PDUs
+ *          whose the target address is the local resolvable private address are accepted.
+ */
+#define BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST    (0x03)
+
+/*  Initiator Filter policy */
+
+/**
+ * @def BLE_GAP_INIT_FILT_USE_ADDR
+ * @brief White List is not used.
+ */
+#define BLE_GAP_INIT_FILT_USE_ADDR                     (0x00)
+
+/**
+ * @def BLE_GAP_INIT_FILT_USE_WLST
+ * @brief White List is used.
+ */
+#define BLE_GAP_INIT_FILT_USE_WLST                     (0x01)
+
+/**
+ * @def BLE_GAP_DATA_0_CLEAR
+ * @brief Clear the advertising data/scan response data/periodic advertising data in the advertising set.
+ */
+#define BLE_GAP_DATA_0_CLEAR                           (0x01)
+
+/**
+ * @def BLE_GAP_DATA_0_DID_UPD
+ * @brief Update Advertising DID without changing advertising data.
+ */
+#define BLE_GAP_DATA_0_DID_UPD                         (0x02)
+
+/* Privacy Mode related Definitions */
+
+/**
+ * @def BLE_GAP_NET_PRIV_MODE
+ * @brief Network Privacy Mode.
+ */
+#define BLE_GAP_NET_PRIV_MODE                          (0x00)
+
+/**
+ * @def BLE_GAP_DEV_PRIV_MODE
+ * @brief Device Privacy Mode.
+ */
+#define BLE_GAP_DEV_PRIV_MODE                          (0x01)
+
+/**
+ * @def BLE_GAP_REM_FEATURE_SIZE
+ * @brief The length of the features supported by a remote device.
+ */
+#define BLE_GAP_REM_FEATURE_SIZE                       (0x08)
+
+/* Authorization Flag Definitions */
+
+/**
+ * @def BLE_GAP_NOT_AUTHORIZED
+ * @brief Not authorize the remote device.
+ */
+#define BLE_GAP_NOT_AUTHORIZED                         (0x00)
+
+/**
+ * @def BLE_GAP_AUTHORIZED
+ * @brief Authorize the remote device.
+ */
+#define BLE_GAP_AUTHORIZED                             (0x01)
+
+/* Remove ADV Set related */
+
+/**
+ * @def BLE_GAP_RMV_ADV_SET_REM_OP
+ * @brief Delete an advertising set.
+ */
+#define BLE_GAP_RMV_ADV_SET_REM_OP                     (0x01)
+
+/**
+ * @def BLE_GAP_RMV_ADV_SET_CLR_OP
+ * @brief Delete all the advertising sets.
+ */
+#define BLE_GAP_RMV_ADV_SET_CLR_OP                     (0x02)
+
+/* scan procedure type */
+
+/**
+ * @def BLE_GAP_SC_PROC_GEN
+ * @brief General Discovery Procedure.
+ */
+#define BLE_GAP_SC_PROC_GEN                            (0x02)
+
+/**
+ * @def BLE_GAP_SC_PROC_LIM
+ * @brief Limited Discovery Procedure.
+ */
+#define BLE_GAP_SC_PROC_LIM                            (0x01)
+
+/**
+ * @def BLE_GAP_SC_PROC_OBS
+ * @brief Observation Procedure.
+ */
+#define BLE_GAP_SC_PROC_OBS                            (0x00)
+
+/* White List Operation */
+/* Resolvable List Operation */
+/* Periodic advertiser List Operation */
+
+/**
+ * @def BLE_GAP_LIST_ADD_DEV
+ * @brief Add the device to the list.
+ */
+#define BLE_GAP_LIST_ADD_DEV                (0x01)
+
+/**
+ * @def BLE_GAP_LIST_REM_DEV
+ * @brief Delete the device from the list.
+ */
+#define BLE_GAP_LIST_REM_DEV                (0x02)
+
+/**
+ * @def BLE_GAP_LIST_CLR
+ * @brief Clear the list.
+ */
+#define BLE_GAP_LIST_CLR                    (0x03)
+
+/**
+ * @def BLE_GAP_WHITE_LIST_MAX_ENTRY
+ * @brief The maximum entry number of White List.
+ */
+#define BLE_GAP_WHITE_LIST_MAX_ENTRY        (0x04)
+
+/**
+ * @def BLE_GAP_RSLV_LIST_MAX_ENTRY
+ * @brief The maximum entry number of Resolving List.
+ */
+#define BLE_GAP_RSLV_LIST_MAX_ENTRY         (0x08)
+
+/**
+ * @def BLE_GAP_PERD_LIST_MAX_ENTRY
+ * @brief The maximum entry number of Periodic Advertiser List.
+ */
+#define BLE_GAP_PERD_LIST_MAX_ENTRY         (0x04)
+
+/* Set Address Resolution */
+
+/**
+ * @def BLE_GAP_RPA_DISABLED
+ * @brief Disable RPA generation/resolution.
+ */
+#define BLE_GAP_RPA_DISABLED                (0x00)
+
+/**
+ * @def BLE_GAP_RPA_ENABLED
+ * @brief Enable RPA generation/resolution.
+ */
+#define BLE_GAP_RPA_ENABLED                 (0x01)
+
+/* Set Local IRK type */
+
+/**
+ * @def BLE_GAP_RL_LOC_KEY_ALL_ZERO
+ * @brief  All-zero IRK.
+ */
+#define BLE_GAP_RL_LOC_KEY_ALL_ZERO         (0x00)
+
+/**
+ * @def BLE_GAP_RL_LOC_KEY_REGISTERED
+ * @brief  The IRK registered by R_BLE_GAP_SetLocIdInfo().
+ */
+#define BLE_GAP_RL_LOC_KEY_REGISTERED       (0x01)
+
+/* Number of advertising set supported */
+
+/**
+ * @def BLE_MAX_NO_OF_ADV_SETS_SUPPORTED
+ * @brief  The maximum number of advertising set for the Abstraction API.
+ */
+#define BLE_MAX_NO_OF_ADV_SETS_SUPPORTED    (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM)
+
+/* Advertising Properties  */
+/* Legacy Advertising PDU */
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_IND
+ * @brief  Connectable and scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_IND               (0x0013)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND
+ * @brief  Connectable directed (low duty cycle) Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND        (0x0015)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND
+ * @brief  Connectable directed (high duty cycle) Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND    (0x001D)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_SCAN_IND
+ * @brief  Scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_SCAN_IND          (0x0012)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND
+ * @brief  Non-connectable and non-scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND       (0x0010)
+
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_IND
+ * @brief  Connectable and scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_IND               (0x0000)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND
+ * @brief  Connectable directed (low duty cycle) Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND        (0x0004)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND
+ * @brief  Connectable directed (high duty cycle) Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND    (0x0001)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_SCAN_IND
+ * @brief  Scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_SCAN_IND          (0x0002)
+
+/**
+ * @def BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND
+ * @brief  Non-connectable and non-scannable undirected Legacy Advertising Packet.
+ */
+ #define BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND       (0x0003)
+
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+/* Extended Advertising PDU */
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT
+ * @brief  Connectable and non-scannable undirected Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT        (0x0001)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT
+ * @brief  Connectable and non-scannable directed (low duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT          (0x0005)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT
+ * @brief  Connectable and non-scannable directed (high duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT      (0x000D)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT
+ * @brief  Non-connectable and scannable undirected Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT        (0x0002)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT
+ * @brief  Non-connectable and scannable directed (low duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT          (0x0006)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT
+ * @brief  Non-connectable and scannable directed (high duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT      (0x000E)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT
+ * @brief  Non-connectable and non-scannable undirected Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT      (0x0000)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT
+ * @brief  Non-connectable and non-scannable directed (low duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT        (0x0004)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT
+ * @brief  Non-connectable and non-scannable directed (high duty cycle) Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT    (0x000C)
+
+/* Anonymous advertising  */
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_ANONYMOUS
+ * @brief  Omit the advertiser address from Extended Advertising Packet.
+ */
+#define BLE_GAP_EXT_PROP_ADV_ANONYMOUS                   (0x0020)
+
+/**
+ * @def BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER
+ * @brief  Indicate that the advertising data includes TX Power.
+ */
+#define BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER            (0x0040)
+
+/* Advertising Filter Policy */
+
+/**
+ * @def BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY
+ * @brief  Process scan and connection requests from all devices.
+ */
+#define BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY              (0x00)
+
+/**
+ * @def BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY
+ * @brief  Process connection requests from all devices and scan requests from only devices that are in the White List.
+ */
+#define BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY             (0x01)
+
+/**
+ * @def BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST
+ * @brief  Process scan requests from all devices and connection requests from only devices that are in the White List.
+ */
+#define BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST             (0x02)
+
+/**
+ * @def BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST
+ * @brief  Process scan and connection requests from only devices in the White List.
+ */
+#define BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST            (0x03)
+
+/* Primary & Secondary Advertising PHY  */
+
+/**
+ * @def BLE_GAP_ADV_PHY_1M
+ * @brief  Use 1M PHY.
+ */
+#define BLE_GAP_ADV_PHY_1M                               (0x01)
+
+/**
+ * @def BLE_GAP_ADV_PHY_2M
+ * @brief  Use 2M PHY.
+ */
+#define BLE_GAP_ADV_PHY_2M                               (0x02)
+
+/**
+ * @def BLE_GAP_ADV_PHY_CD
+ * @brief  Use Coded PHY.
+ */
+#define BLE_GAP_ADV_PHY_CD                               (0x03)
+
+/* Scan Request Notification Enable */
+
+/**
+ * @def BLE_GAP_SCAN_REQ_NTF_DISABLE
+ * @brief  Disable Scan Request Notification.
+ */
+#define BLE_GAP_SCAN_REQ_NTF_DISABLE                     (0x00)
+
+/**
+ * @def BLE_GAP_SCAN_REQ_NTF_ENABLE
+ * @brief  Enable Scan Request Notification.
+ */
+#define BLE_GAP_SCAN_REQ_NTF_ENABLE                      (0x01)
+
+/* Periodic Advertising Properties  */
+
+/**
+ * @def BLE_GAP_PERD_PROP_TX_POWER
+ * @brief  Indicate that periodic advertising data includes Tx Power.
+ */
+#define BLE_GAP_PERD_PROP_TX_POWER                       (0x0040)
+
+/**
+ * @def BLE_GAP_INVALID_ADV_HDL
+ * @brief  Invalid advertising handle.
+ */
+#define BLE_GAP_INVALID_ADV_HDL                          (0xFF)
+
+/**
+ * @def BLE_GAP_SET_PHYS_HOST_PREF_1M
+ * @brief  Use 1M PHY.
+ */
+#define BLE_GAP_SET_PHYS_HOST_PREF_1M                    (0x01)
+
+/**
+ * @def BLE_GAP_SET_PHYS_HOST_PREF_2M
+ * @brief  Use 2M PHY.
+ */
+#define BLE_GAP_SET_PHYS_HOST_PREF_2M                    (0x02)
+
+/**
+ * @def BLE_GAP_SET_PHYS_HOST_PREF_CD
+ * @brief  Use Coded PHY.
+ */
+#define BLE_GAP_SET_PHYS_HOST_PREF_CD                    (0x04)
+
+/**
+ * @def BLE_GAP_SET_PHYS_OP_HOST_NO_PREF
+ * @brief  No preferred coding.
+ */
+#define BLE_GAP_SET_PHYS_OP_HOST_NO_PREF                 (0x00)
+
+/**
+ * @def BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2
+ * @brief  Use S=2 coding.
+ */
+#define BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2                (0x01)
+
+/**
+ * @def BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8
+ * @brief  Use S=8 coding.
+ */
+#define BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8                (0x02)
+
+/* connection update parameter */
+
+/**
+ * @def BLE_GAP_CONN_UPD_MODE_REQ
+ * @brief  Request for updating the connection parameters.
+ */
+#define BLE_GAP_CONN_UPD_MODE_REQ                        (0x01)
+
+/**
+ * @def BLE_GAP_CONN_UPD_MODE_RSP
+ * @brief  Reply a connection parameter update request.
+ */
+#define BLE_GAP_CONN_UPD_MODE_RSP                        (0x02)
+
+/* connection update response  */
+
+/**
+ * @def BLE_GAP_CONN_UPD_ACCEPT
+ * @brief  Accept the update request.
+ */
+#define BLE_GAP_CONN_UPD_ACCEPT                          (0x0000)
+
+/**
+ * @def BLE_GAP_CONN_UPD_REJECT
+ * @brief  Reject the update request.
+ */
+#define BLE_GAP_CONN_UPD_REJECT                          (0x0001)
+
+/* channel map size */
+
+/**
+ * @def BLE_GAP_CH_MAP_SIZE
+ * @brief  The size of channel map.
+ */
+#define BLE_GAP_CH_MAP_SIZE                              (0x05)
+
+/**
+ * @def BLE_GAP_INVALID_CONN_HDL
+ * @brief  Invalid Connection handle.
+ */
+#define BLE_GAP_INVALID_CONN_HDL                         (0xFFFF)
+
+/**
+ * @def BLE_GAP_NOT_USE_CONN_HDL
+ * @brief  This macro indicates that connection handle is not used.
+ */
+#define BLE_GAP_NOT_USE_CONN_HDL                         BLE_GAP_INVALID_CONN_HDL
+
+/**
+ * @def BLE_GAP_INIT_CONN_HDL
+ * @brief  Initial Connection handle.
+ */
+#define BLE_GAP_INIT_CONN_HDL                            BLE_GAP_INVALID_CONN_HDL
+
+/**
+ * @def BLE_GAP_PAIRING_ACCEPT
+ * @brief  Accept a request regarding pairing.
+ */
+#define BLE_GAP_PAIRING_ACCEPT                           (0x00)
+
+/**
+ * @def BLE_GAP_PAIRING_REJECT
+ * @brief  Reject a request regarding pairing.
+ */
+#define BLE_GAP_PAIRING_REJECT                           (0x01)
+
+/**
+ * @def BLE_GAP_LTK_REQ_ACCEPT
+ * @brief  Reply for the LTK request.
+ */
+#define BLE_GAP_LTK_REQ_ACCEPT                           (0x00)
+
+/**
+ * @def BLE_GAP_LTK_REQ_DENY
+ * @brief  Reject the LTK request.
+ */
+#define BLE_GAP_LTK_REQ_DENY                             (0x01)
+
+/**
+ * @def BLE_GAP_LESC_PASSKEY_ENTRY_STARTED
+ * @brief  Notify that passkey entry started.
+ */
+#define BLE_GAP_LESC_PASSKEY_ENTRY_STARTED               (0x00)
+
+/**
+ * @def BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED
+ * @brief  Notify that passkey digit entered.
+ */
+#define BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED               (0x01)
+
+/**
+ * @def BLE_GAP_LESC_PASSKEY_DIGIT_ERASED
+ * @brief  Notify that passkey digit erased.
+ */
+#define BLE_GAP_LESC_PASSKEY_DIGIT_ERASED                (0x02)
+
+/**
+ * @def BLE_GAP_LESC_PASSKEY_CLEARED
+ * @brief  Notify that passkey cleared.
+ */
+#define BLE_GAP_LESC_PASSKEY_CLEARED                     (0x03)
+
+/**
+ * @def BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED
+ * @brief  Notify that passkey entry completed.
+ */
+#define BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED             (0x04)
+
+/**
+ * @def BLE_GAP_SEC_MITM_BEST_EFFORT
+ * @brief  MITM Protection not required.
+ */
+#define BLE_GAP_SEC_MITM_BEST_EFFORT                     (0x00)
+
+/**
+ * @def BLE_GAP_SEC_MITM_STRICT
+ * @brief  MITM Protection required.
+ */
+#define BLE_GAP_SEC_MITM_STRICT                          (0x01)
+
+/**
+ * @def BLE_GAP_KEY_DIST_ENCKEY
+ * @brief  LTK
+ */
+#define BLE_GAP_KEY_DIST_ENCKEY                          (0x01)
+
+/**
+ * @def BLE_GAP_KEY_DIST_IDKEY
+ * @brief  IRK and Identity Address.
+ */
+#define BLE_GAP_KEY_DIST_IDKEY                           (0x02)
+
+/**
+ * @def BLE_GAP_KEY_DIST_SIGNKEY
+ * @brief  CSRK
+ */
+#define BLE_GAP_KEY_DIST_SIGNKEY                         (0x04)
+
+/**
+ * @def BLE_GAP_ID_ADDR_SIZE
+ * @brief  The size of identity address.
+ */
+#define BLE_GAP_ID_ADDR_SIZE                             (0x07)
+
+/**
+ * @def BLE_GAP_IRK_SIZE
+ * @brief  The size of IRK.
+ */
+#define BLE_GAP_IRK_SIZE                                 (0x10)
+
+/**
+ * @def BLE_GAP_CSRK_SIZE
+ * @brief  The size of CSRK.
+ */
+#define BLE_GAP_CSRK_SIZE                                (0x10)
+
+/**
+ * @def BLE_GAP_LTK_SIZE
+ * @brief  The size of LTK.
+ */
+#define BLE_GAP_LTK_SIZE                                 (0x10)
+
+/**
+ * @def BLE_GAP_EDIV_SIZE
+ * @brief  The size of EDIV.
+ */
+#define BLE_GAP_EDIV_SIZE                                (0x02)
+
+/**
+ * @def BLE_GAP_RAND_64_BIT_SIZE
+ * @brief The size of Rand.
+ */
+#define BLE_GAP_RAND_64_BIT_SIZE                         (0x08)
+
+/**
+ * @def BLE_GAP_UNAUTH_PAIRING
+ * @brief Unauthenticated pairing.
+ */
+#define BLE_GAP_UNAUTH_PAIRING                           (0x01)
+
+/**
+ * @def BLE_GAP_AUTH_PAIRING
+ * @brief Authenticated pairing.
+ */
+#define BLE_GAP_AUTH_PAIRING                             (0x02)
+
+/**
+ * @def BLE_GAP_LEGACY_PAIRING
+ * @brief  Legacy pairing.
+ */
+#define BLE_GAP_LEGACY_PAIRING                           (0x01)
+
+/**
+ * @def BLE_GAP_LESC_PAIRING
+ * @brief Secure Connections.
+ */
+#define BLE_GAP_LESC_PAIRING                             (0x02)
+
+/**
+ * @def BLE_GAP_BONDING_NONE
+ * @brief The device doesn't support Bonding.
+ */
+#define BLE_GAP_BONDING_NONE                             (0x00)
+
+/**
+ * @def BLE_GAP_BONDING
+ * @brief The device supports Bonding.
+ */
+#define BLE_GAP_BONDING                                  (0x01)
+
+/**
+ * @def BLE_GAP_IOCAP_DISPLAY_ONLY
+ * @brief Display Only iocapability.
+ * @details  Output function : Local device has the ability to display a 6 digit decimal number.\n
+ *           Input function : None
+ */
+#define BLE_GAP_IOCAP_DISPLAY_ONLY                       (0x00)
+
+/**
+ * @def BLE_GAP_IOCAP_DISPLAY_YESNO
+ * @brief Display Yes/No iocapability.
+ * @details  Output function : Output function : Local device has the ability to display a 6 digit decimal number.\n
+ *           Input function : Local device has the ability to indicate 'yes' or 'no'
+ */
+#define BLE_GAP_IOCAP_DISPLAY_YESNO                      (0x01)
+
+/**
+ * @def BLE_GAP_IOCAP_KEYBOARD_ONLY
+ * @brief Keyboard Only iocapability.
+ * @details  Output function : None\n
+ *           Input function : Local device has the ability to input the number '0' - '9'.
+ */
+#define BLE_GAP_IOCAP_KEYBOARD_ONLY                      (0x02)
+
+/**
+ * @def BLE_GAP_IOCAP_NOINPUT_NOOUTPUT
+ * @brief No Input No Output iocapability.
+ * @details  Output function : None\n
+ *           Input function : None
+ */
+#define BLE_GAP_IOCAP_NOINPUT_NOOUTPUT                   (0x03)
+
+/**
+ * @def BLE_GAP_IOCAP_KEYBOARD_DISPLAY
+ * @brief Keyboard Display iocapability.
+ * @details  Output function : Output function : Local device has the ability to display a 6 digit decimal number.\n
+ *           Input function : Local device has the ability to input the number '0' - '9'.
+ */
+#define BLE_GAP_IOCAP_KEYBOARD_DISPLAY                   (0x04)
+
+/**
+ * @def BLE_GAP_OOB_DATA_NOT_PRESENT
+ * @brief Reply that No OOB data has been received when pairing.
+ */
+#define BLE_GAP_OOB_DATA_NOT_PRESENT                     (0x00)
+
+/**
+ * @def BLE_GAP_OOB_DATA_PRESENT
+ * @brief Reply that the OOB data has been received when pairing.
+ */
+#define BLE_GAP_OOB_DATA_PRESENT                         (0x01)
+
+/**
+ * @def BLE_GAP_SC_BEST_EFFORT
+ * @brief Accept Legacy pairing and Secure Connections.
+ */
+#define BLE_GAP_SC_BEST_EFFORT                           (0x00)
+
+/**
+ * @def BLE_GAP_SC_STRICT
+ * @brief Accept only Secure Connections.
+ */
+#define BLE_GAP_SC_STRICT                                (0x01)
+
+/**
+ * @def BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT
+ * @brief Not support for Key Press Notification.
+ */
+#define BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT                (0x00)
+
+/**
+ * @def BLE_GAP_SC_KEY_PRESS_NTF_SPRT
+ * @brief Support for Key Press Notification.
+ */
+#define BLE_GAP_SC_KEY_PRESS_NTF_SPRT                    (0x01)
+
+/**
+ * @def BLE_GAP_LEGACY_OOB_SIZE
+ * @brief The size of Temporary Key for OOB in legacy pairing.
+ */
+#define BLE_GAP_LEGACY_OOB_SIZE                          (0x10)
+
+/**
+ * @def BLE_GAP_OOB_CONFIRM_VAL_SIZE
+ * @brief The size of Confirmation Value for OOB in Secure Connections.
+ */
+#define BLE_GAP_OOB_CONFIRM_VAL_SIZE                     (0x10)
+
+/**
+ * @def BLE_GAP_OOB_RANDOM_VAL_SIZE
+ * @brief The size of Rand for OOB in Secure Connections.
+ */
+#define BLE_GAP_OOB_RANDOM_VAL_SIZE                      (0x10)
+
+/**
+ * @def BLE_GAP_SEC_DEL_LOC_NONE
+ * @brief Delete no local keys.
+ */
+#define BLE_GAP_SEC_DEL_LOC_NONE                         (0x00)
+
+/**
+ * @def BLE_GAP_SEC_DEL_LOC_IRK
+ * @brief Delete local IRK.
+ */
+#define BLE_GAP_SEC_DEL_LOC_IRK                          (0x01)
+
+/**
+ * @def BLE_GAP_SEC_DEL_LOC_CSRK
+ * @brief Delete local CSRK.
+ */
+#define BLE_GAP_SEC_DEL_LOC_CSRK                         (0x02)
+
+/**
+ * @def BLE_GAP_SEC_DEL_LOC_ALL
+ * @brief Delete all local keys.
+ */
+#define BLE_GAP_SEC_DEL_LOC_ALL                          (0x03)
+
+/**
+ * @def BLE_GAP_SEC_DEL_REM_NONE
+ * @brief Delete no remote device keys.
+ */
+#define BLE_GAP_SEC_DEL_REM_NONE                         (0x00)
+
+/**
+ * @def BLE_GAP_SEC_DEL_REM_SA
+ * @brief Delete a key specified by the p_addr parameter.
+ */
+#define BLE_GAP_SEC_DEL_REM_SA                           (0x01)
+
+/**
+ * @def BLE_GAP_SEC_DEL_REM_NOT_CONN
+ * @brief Delete keys of not connected remote devices.
+ */
+#define BLE_GAP_SEC_DEL_REM_NOT_CONN                     (0x02)
+
+/**
+ * @def BLE_GAP_SEC_DEL_REM_ALL
+ * @brief Delete all remote device keys.
+ */
+#define BLE_GAP_SEC_DEL_REM_ALL                          (0x03)
+
+/**@} (end addtogroup GAP_API)*/
+
+/* =================================================== GATT Macro =================================================== */
+
+/** @addtogroup GATT_SERVER_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/* GATT Common Macro */
+
+/**
+ * @ingroup GATT_SERVER_API
+ * @def BLE_GATT_DEFAULT_MTU
+ * @brief GATT Default MTU.
+ */
+#define BLE_GATT_DEFAULT_MTU                         (23)
+
+/**
+ * @def BLE_GATT_16_BIT_UUID_FORMAT
+ * @brief GATT Identification for 16-bit UUID Format.
+ */
+#define BLE_GATT_16_BIT_UUID_FORMAT                  (0x01)
+
+/**
+ * @def BLE_GATT_128_BIT_UUID_FORMAT
+ * @brief GATT Identification for 128-bit UUID Format.
+ */
+#define BLE_GATT_128_BIT_UUID_FORMAT                 (0x02)
+
+/**
+ * @def BLE_GATT_16_BIT_UUID_SIZE
+ * @brief GATT 16-bit UUID Size.
+ */
+#define BLE_GATT_16_BIT_UUID_SIZE                    (2)
+
+/**
+ * @def BLE_GATT_128_BIT_UUID_SIZE
+ * @brief GATT 128-bit UUID Size.
+ */
+#define BLE_GATT_128_BIT_UUID_SIZE                   (16)
+
+/**
+ * @def BLE_GATT_INVALID_ATTR_HDL_VAL
+ * @brief GATT Invalid Attribute Handle Value.
+ */
+#define BLE_GATT_INVALID_ATTR_HDL_VAL                (0x0000)
+
+/**
+ * @def BLE_GATT_ATTR_HDL_START_RANGE
+ * @brief GATT Attribute Handle Start Range.
+ */
+#define BLE_GATT_ATTR_HDL_START_RANGE                (0x0001)
+
+/**
+ * @def BLE_GATT_ATTR_HDL_END_RANGE
+ * @brief GATT Attribute Handle End Range.
+ */
+#define BLE_GATT_ATTR_HDL_END_RANGE                  (0xFFFF)
+
+/* GATT Server Macro */
+
+/**
+ * @def BLE_GATTS_CLI_CNFG_NOTIFICATION
+ * @brief GATT Client Configuration values. Enable Notification.
+ */
+#define BLE_GATTS_CLI_CNFG_NOTIFICATION              (0x0001)
+
+/**
+ * @def BLE_GATTS_CLI_CNFG_INDICATION
+ * @brief GATT Client Configuration values. Enable Indication.
+ */
+#define BLE_GATTS_CLI_CNFG_INDICATION                (0x0002)
+
+/**
+ * @def BLE_GATTS_CLI_CNFG_DEFAULT
+ * @brief GATT Client Configuration values. Default value or disable notification/indication.
+ */
+#define BLE_GATTS_CLI_CNFG_DEFAULT                   (0x0000)
+
+/**
+ * @def BLE_GATTS_SER_CNFG_BROADCAST
+ * @brief GATT Server Configuration values. Enable broadcast.
+ */
+#define BLE_GATTS_SER_CNFG_BROADCAST                 (0x0001)
+
+/**
+ * @def BLE_GATTS_SER_CNFG_DEFAULT
+ * @brief GATT Server Configuration values. Default value.
+ */
+#define BLE_GATTS_SER_CNFG_DEFAULT                   (0x0000)
+
+/**
+ * @def BLE_GATTS_MAX_CB
+ * @brief GATT Server Callback Number.
+ */
+#define BLE_GATTS_MAX_CB                             (15)
+
+/* GATT Server Operation */
+
+/**
+ * @def BLE_GATTS_OP_CHAR_VALUE_READ_REQ
+ * @brief Characteristic Value Local Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_VALUE_READ_REQ             (0x01)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_VALUE_WRITE_REQ
+ * @brief Characteristic Value Local Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_VALUE_WRITE_REQ            (0x02)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_VALUE_WRITE_WITHOUT_REQ
+ * @brief Characteristic Value Local Write Without Response Operation.
+ */
+#define BLE_GATTS_OP_CHAR_VALUE_WRITE_WITHOUT_REQ    (0x03)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_CLI_CNFG_READ_REQ
+ * @brief Characteristic Client Configuration Local Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_CLI_CNFG_READ_REQ          (0x11)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_CLI_CNFG_WRITE_REQ
+ * @brief Characteristic Client Configuration Local Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_CLI_CNFG_WRITE_REQ         (0x12)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_SER_CNFG_READ_REQ
+ * @brief Characteristic Server Configuration Local Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_SER_CNFG_READ_REQ          (0x21)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_SER_CNFG_WRITE_REQ
+ * @brief Characteristic Server Configuration Local Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_SER_CNFG_WRITE_REQ         (0x22)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_READ_REQ
+ * @brief Characteristic Value Peer Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_READ_REQ              (0x81)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_WRITE_REQ
+ * @brief Characteristic Value Peer Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_WRITE_REQ             (0x82)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_WRITE_CMD
+ * @brief Characteristic Value Peer Write Command.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_WRITE_CMD             (0x84)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ
+ * @brief Characteristic Client Configuration Peer Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_READ_REQ     (0x91)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ
+ * @brief Characteristic Client Configuration Peer Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_CLI_CNFG_WRITE_REQ    (0x92)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ
+ * @brief Characteristic Server Configuration Peer Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_SER_CNFG_READ_REQ     (0xA1)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ
+ * @brief Characteristic Server Configuration Peer Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_SER_CNFG_WRITE_REQ    (0xA2)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ
+ * @brief Characteristic User Description Peer Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_USR_DESC_READ_REQ     (0xB1)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ
+ * @brief Characteristic User Description Peer Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_USR_DESC_WRITE_REQ    (0xB2)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ
+ * @brief Characteristic Higher Layer Defined Descriptor Peer Read Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_HLD_DESC_READ_REQ     (0xF1)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ
+ * @brief Characteristic Higher Layer Defined Descriptor Peer Write Operation.
+ */
+#define BLE_GATTS_OP_CHAR_PEER_HLD_DESC_WRITE_REQ    (0xF2)
+
+/**
+ * @def BLE_GATTS_OP_CHAR_REQ_AUTHOR
+ * @brief Operation Required Authorization.
+ */
+#define BLE_GATTS_OP_CHAR_REQ_AUTHOR                 (0x08)
+
+/* GATT Database */
+
+/**
+ * @def BLE_GATT_DB_READ
+ * @brief Allow clients to read.
+ */
+#define BLE_GATT_DB_READ                             (0x01)
+
+/**
+ * @def BLE_GATT_DB_WRITE
+ * @brief Allow clients to write.
+ */
+#define BLE_GATT_DB_WRITE                            (0x02)
+
+/**
+ * @def BLE_GATT_DB_WRITE_WITHOUT_RSP
+ * @brief Allow clients to write without response.
+ */
+#define BLE_GATT_DB_WRITE_WITHOUT_RSP                (0x04)
+
+/**
+ * @def BLE_GATT_DB_READ_WRITE
+ * @brief Allow clients to access of all.
+ */
+#define BLE_GATT_DB_READ_WRITE \
+    (BLE_GATT_DB_READ | BLE_GATT_DB_WRITE | BLE_GATT_DB_WRITE_WITHOUT_RSP)
+
+/**
+ * @def BLE_GATT_DB_NO_AUXILIARY_PROPERTY
+ * @brief No auxiliary properties.
+ */
+#define BLE_GATT_DB_NO_AUXILIARY_PROPERTY         (0x00)
+
+/**
+ * @def BLE_GATT_DB_FIXED_LENGTH_PROPERTY
+ * @brief Fixed length attribute value.
+ */
+#define BLE_GATT_DB_FIXED_LENGTH_PROPERTY         (0x01)
+
+/**
+ * @def BLE_GATT_DB_AUTHORIZATION_PROPERTY
+ * @brief  Attributes requiring authorization.
+ */
+#define BLE_GATT_DB_AUTHORIZATION_PROPERTY        (0x02)
+
+/**
+ * @def BLE_GATT_DB_ATTR_DISABLED
+ * @brief  The attribute is disabled.
+ *         If this value is set, the attribute cannot be found and accessed by a GATT Client.
+ */
+#define BLE_GATT_DB_ATTR_DISABLED                 (0x10)
+
+/**
+ * @def BLE_GATT_DB_128_BIT_UUID_FORMAT
+ * @brief Attribute with 128 bit UUID.
+ */
+#define BLE_GATT_DB_128_BIT_UUID_FORMAT           (0x20)
+
+/**
+ * @def BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY
+ * @brief Attribute managed by each GATT Client.
+ */
+#define BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY    (0x40)
+
+/**
+ * @def BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY
+ * @brief Fixed attribute value.
+ */
+#define BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY       (0x80)
+
+/**
+ * @def BLE_GATT_DB_SER_SECURITY_UNAUTH
+ * @brief Unauthenticated pairing(Security Mode1 Security Level 2, Security Mode 2 Security Level 1).
+ *        Unauthenticated pairing is required to access the service.
+ */
+#define BLE_GATT_DB_SER_SECURITY_UNAUTH           (0x00000001)
+
+/**
+ * @def BLE_GATT_DB_SER_SECURITY_AUTH
+ * @brief Authenticated pairing(Security Mode1 Security Level 3, Security Mode 2 Security Level 2).
+ *        Authenticated pairing is required to access the service.
+ */
+#define BLE_GATT_DB_SER_SECURITY_AUTH             (0x00000002)
+
+/**
+ * @def BLE_GATT_DB_SER_SECURITY_SECONN
+ * @brief Authenticated LE secure connections that generates 16bytes LTK(Security Mode1 Security Level 4).
+ *        Authenticated LE secure connections pairing that generates 16bytes LTK is required to access the service.
+ *        If this bit is set, bit24-27 are ignored.
+ */
+#define BLE_GATT_DB_SER_SECURITY_SECONN           (0x00000004)
+
+/**
+ * @def BLE_GATT_DB_SER_SECURITY_ENC
+ * @brief Encryption.
+ *        Encryption by the LTK exchanged in pairing is required to access.
+ */
+#define BLE_GATT_DB_SER_SECURITY_ENC              (0x00000010)
+
+/**
+ * @def BLE_GATT_DB_SER_NO_SECURITY_PROPERTY
+ * @brief No Security(Security Mode1 Security Level 1).
+ */
+#define BLE_GATT_DB_SER_NO_SECURITY_PROPERTY      (0x00000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE
+ * @brief 7-byte or larger encryption key.
+ */
+#define BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE    (0x00000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7
+ * @brief 7-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7        (0x01000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8
+ * @brief 8-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8        (0x02000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9
+ * @brief 9-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9        (0x03000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10
+ * @brief 10-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10       (0x04000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11
+ * @brief 11-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11       (0x05000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12
+ * @brief 12-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12       (0x06000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13
+ * @brief 13-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13       (0x07000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14
+ * @brief 14-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14       (0x08000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15
+ * @brief 15-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15       (0x09000000)
+
+/**
+ * @def BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16
+ * @brief 16-byte encryption key.
+ */
+#define BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16       (0x0A000000)
+
+/******************************************************************************************************************//**
+ * @enum e_r_ble_gatts_evt_t
+ * @brief  GATT Server Event Identifier
+ **********************************************************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief  MTU Exchange Request has been received.
+     *  @details
+     *  This event notifies the application layer that a MTU Exchange Request PDU has been received from a GATT Client.
+     *  Need to reply to the request by R_BLE_GATTS_RspExMtu().
+     *
+     * ## Event Code: 0x3002
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_ex_mtu_req_evt_t
+     */
+    BLE_GATTS_EVENT_EX_MTU_REQ = 0x3002,             //!< BLE_GATTS_EVENT_EX_MTU_REQ
+
+    /**
+     *  @brief   Read By Type Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Read By Type Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x3009
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_read_by_type_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP = 0x3009,  //!< BLE_GATTS_EVENT_READ_BY_TYPE_RSP_COMP
+
+    /**
+     *  @brief   Read Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Read Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x300B
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_read_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_READ_RSP_COMP = 0x300B,          //!< BLE_GATTS_EVENT_READ_RSP_COMP
+
+    /**
+     *  @brief   Read Blob Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Read Blob Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x300D
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_read_blob_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_READ_BLOB_RSP_COMP = 0x300D,     //!< BLE_GATTS_EVENT_READ_BLOB_RSP_COMP
+
+    /**
+     *  @brief   Read Multiple Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Read Multiple Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x300F
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_read_multi_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_READ_MULTI_RSP_COMP = 0x300F,    //!< BLE_GATTS_EVENT_READ_MULTI_RSP_COMP
+
+    /**
+     *  @brief   Write Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Write Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x3013
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_write_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_WRITE_RSP_COMP = 0x3013,         //!< BLE_GATTS_EVENT_WRITE_RSP_COMP
+
+    /**
+     *  @brief   Prepare Write Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Prepare Write Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x3017
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_prepare_write_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP = 0x3017, //!< BLE_GATTS_EVENT_PREPARE_WRITE_RSP_COMP
+
+    /**
+     *  @brief   Execute Write Response has been sent.
+     *  @details
+     *  This event notifies the application layer that a Execute Write Response PDU has been sent
+     *  from GATT Server to the GATT Client.
+     *
+     * ## Event Code: 0x3019
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_exe_write_rsp_evt_t
+     */
+    BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP = 0x3019,     //!< BLE_GATTS_EVENT_EXE_WRITE_RSP_COMP
+
+    /**
+     *  @brief   Confirmation has been received.
+     *  @details
+     *  This event notifies the application layer that a Confirmation PDU has been received from a GATT Client.
+     *
+     * ## Event Code: 0x301E
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_cfm_evt_t
+     */
+    BLE_GATTS_EVENT_HDL_VAL_CNF = 0x301E,            //!< BLE_GATTS_EVENT_HDL_VAL_CNF
+
+    /**
+     *  @brief   The GATT Database has been accessed from a GATT Client.
+     *  @details
+     *  This event notifies the application layer that the GATT Database has been accessed from a GATT Client.
+     *
+     * ## Event Code: 0x3040
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_db_access_evt_t
+     */
+    BLE_GATTS_EVENT_DB_ACCESS_IND = 0x3040,          //!< BLE_GATTS_EVENT_DB_ACCESS_IND
+
+    /**
+     *  @brief   A connection has been established.
+     *  @details
+     *  This event notifies the application layer that the link with the GATT Client has been established.
+     *
+     * ## Event Code: 0x3081
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_conn_evt_t
+     */
+    BLE_GATTS_EVENT_CONN_IND = 0x3081,               //!< BLE_GATTS_EVENT_CONN_IND
+
+    /**
+     *  @brief   A connection has been disconnected.
+     *  @details
+     *  This event notifies the application layer that the link with the GATT Client has been disconnected.
+     *
+     * ## Event Code: 0x3082
+     *
+     *  ## Event Data:
+     *  st_ble_gatts_disconn_evt_t
+     */
+    BLE_GATTS_EVENT_DISCONN_IND = 0x3082,            //!< BLE_GATTS_EVENT_DISCONN_IND
+
+    /**
+     *  @brief   Invalid GATT Server Event.
+     *
+     * ## Event Code: 0x30FF
+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTS_EVENT_INVALID = 0x30FF                 //!< BLE_GATTS_EVENT_INVALID
+} e_r_ble_gatts_evt_t;
+
+/*@}*/
+
+/** @addtogroup GATT_CLIENT_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/**
+ * @ingroup GATT_CLIENT_API
+ * @def BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG
+ * GATT Execute Write Cancel Flag.
+ */
+#define BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG        (0x00)
+
+/**
+ * @def BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG
+ * GATT Execute Write Execute Flag.
+ */
+#define BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG          (0x01)
+
+/**
+ * @def BLE_GATTC_MAX_CB
+ * @brief GATT Client Callback Number.
+ */
+#define BLE_GATTC_MAX_CB                           (15)
+
+/**
+ * @def BLE_GATTC_EXEC_AUTO
+ * @brief Auto execution.
+ */
+#define BLE_GATTC_EXEC_AUTO                        (0x01)
+
+/**
+ * @def BLE_GATTC_EXEC_NOT_AUTO
+ * @brief Not auto execution.
+ */
+#define BLE_GATTC_EXEC_NOT_AUTO                    (0x02)
+
+/* To be moved to parameter files */
+
+/**
+ * @def BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR
+ * @brief Length of the Queue used with Prepare Write procedure to write a characteristic
+ *        whose size is larger than MTU.
+ */
+#define BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR    (10)
+
+/******************************************************************************************************************//**
+ * @enum e_r_ble_gattc_evt_t
+ * @brief  GATT Client Event Identifier
+ **********************************************************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief  This event notifies the application layer that a problem has occurred in the GATT Server while
+     *          processing a request from GATT Client.
+     *  @details When GATT Client has received a Error Response PDU from a GATT Server, BLE_GATTC_EVENT_ERROR_RSP
+     *           event is notified the application layer.
+     *
+     * ## Event Code: 0x4001
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_err_rsp_evt_t
+     */
+    BLE_GATTC_EVENT_ERROR_RSP = 0x4001,                 //!< BLE_GATTC_EVENT_ERROR_RSP
+
+    /**
+     *  @brief  This event notifies the application layer that a MTU Exchange Response PDU has been received
+     *          from a GATT Server.
+     *
+     * ## Event Code: 0x4003
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response
+     *                      since GATT Client sent a Exchange MTU Request PDU to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_ex_mtu_rsp_evt_t
+     */
+    BLE_GATTC_EVENT_EX_MTU_RSP = 0x4003,                //!< BLE_GATTC_EVENT_EX_MTU_RSP
+
+    /**
+     *  @brief  When the read of Characteristic specified by UUID has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x4009
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response
+     *                      since GATT Client sent a Exchange MTU Request PDU to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_rd_char_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP = 0x4009,     //!< BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP
+
+    /**
+     *  @brief  When the read of Characteristic/Characteristic Descriptor has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x400B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response
+     *                      since GATT Client sent a request for read by R_BLE_GATTC_ReadCharUsingUuid()
+     *                      to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_rd_char_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_READ_RSP = 0x400B,             //!< BLE_GATTC_EVENT_CHAR_READ_RSP
+
+    /**
+     *  @brief  After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer
+     *          that the partial contents of Long Characteristic/Long Characteristic Descriptor
+     *          has been received from the GATT Server.
+     *
+     * ## Event Code: 0x400D
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response
+     *                      since GATT Client sent a request for read by R_BLE_GATTC_ReadLongChar() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_rd_char_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_PART_READ_RSP = 0x400D,        //!< BLE_GATTC_EVENT_CHAR_PART_READ_RSP
+
+    /**
+     *  @brief  This event notifies the application layer that
+     *          the read of multiple Characteristics has been completed.
+     *
+     * ## Event Code: 0x400F
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response
+     *                      since GATT Client sent a request for read by R_BLE_GATTC_ReadMultiChar() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_rd_multi_char_evt_t
+     */
+    BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP = 0x400F,       //!< BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP
+
+    /**
+     *  @brief  This event notifies the application layer that the write of
+     *          Characteristic/Characteristic Descriptor has been completed.
+     *
+     * ## Event Code: 0x4013
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a write response
+     *                      since GATT Client sent a request for write by R_BLE_GATTC_WriteChar() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_wr_char_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_WRITE_RSP = 0x4013,            //!< BLE_GATTC_EVENT_CHAR_WRITE_RSP
+
+    /**
+     *  @brief  This event notifies the application layer of the one of the following.
+     *          - A segmentation to be written to Long Characteristic/Long Characteristic Descriptor
+     *            has been sent to the GATT Server.
+     *          - The data written to one Characteristic by Reliable Writes has been sent to the GATT Server.
+     *
+     * ## Event Code: 0x4017
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a
+     *                      request for segmentation write by R_BLE_GATTC_WriteLongChar(),
+     *                      or 1 Characteristic write by R_BLE_GATTC_ReliableWrites() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_char_part_wr_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP = 0x4017,       //!< BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP
+
+    /**
+     *  @brief  This event notifies the application layer that a Notification has been received from a GATT Server.
+     *
+     * ## Event Code: 0x401B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_ntf_evt_t
+     */
+    BLE_GATTC_EVENT_HDL_VAL_NTF = 0x401B,               //!< BLE_GATTC_EVENT_HDL_VAL_NTF
+
+    /**
+     *  @brief  This event notifies the application layer that a Indication has been received from a GATT Server.
+     *  @details When the GATT Client has received a Indication, host stack automatically sends a Confirmation
+     *           to the GATT Server.
+     *
+     * ## Event Code: 0x401D
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_MEM_ALLOC_FAILED(0x000C)Insufficient resource is needed to generate the confirmation packet. 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_ind_evt_t
+     */
+    BLE_GATTC_EVENT_HDL_VAL_IND = 0x401D,               //!< BLE_GATTC_EVENT_HDL_VAL_IND
+
+    /**
+     *  @brief  This event notifies the application layer that the link with the GATT Server has been established.
+     *
+     * ## Event Code: 0x4081
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_conn_evt_t
+     */
+    BLE_GATTC_EVENT_CONN_IND = 0x4081,                  //!< BLE_GATTC_EVENT_CONN_IND
+
+    /**
+     *  @brief  This event notifies the application layer that the link with the GATT Server has been disconnected.
+     *
+     * ## Event Code: 0x4082
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_disconn_evt_t
+     */
+    BLE_GATTC_EVENT_DISCONN_IND = 0x4082,               //!< BLE_GATTC_EVENT_DISCONN_IND
+
+    /**
+     *  @brief  This event notifies the application layer that 16-bit UUID Primary Service has been discovered.
+     *
+     * ## Event Code: 0x40E0
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_serv_16_evt_t
+     */
+    BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND = 0x40E0,     //!< BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND
+
+    /**
+     *  @brief  This event notifies the application layer that 128-bit UUID Primary Service has been discovered.
+     *
+     * ## Event Code: 0x40E1
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_serv_128_evt_t
+     */
+    BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND = 0x40E1,    //!< BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND
+
+    /**
+     *  @brief  When the Primary Service discovery by R_BLE_GATTC_DiscAllPrimServ() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40E2
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP = 0x40E2,   //!< BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP
+
+    /**
+     *  @brief  When the Primary Service discovery by R_BLE_GATTC_DiscPrimServ() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40E3
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP = 0x40E3,       //!< BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP
+
+    /**
+     *  @brief  This event notifies the application layer that 16-bit UUID Secondary Service has been discovered.
+     *
+     * ## Event Code: 0x40E4
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_serv_16_evt_t
+     */
+    BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND = 0x40E4,   //!< BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND
+
+    /**
+     *  @brief  This event notifies the application layer that 128-bit UUID Secondary Service has been discovered.
+     *
+     * ## Event Code: 0x40E5
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_serv_128_evt_t
+     */
+    BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND = 0x40E5,  //!< BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND
+
+    /**
+     *  @brief  When the Primary Service discovery by R_BLE_GATTC_DiscAllSecondServ() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40E6
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP = 0x40E6, //!< BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP
+
+    /**
+     *  @brief  This event notifies the application layer that Included Service that
+     *          includes 16-bit UUID Service has been discovered.
+     *
+     * ## Event Code: 0x40E7
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_inc_serv_16_evt_t
+     */
+    BLE_GATTC_EVENT_INC_SERV_16_DISC_IND = 0x40E7,      //!< BLE_GATTC_EVENT_INC_SERV_16_DISC_IND
+
+    /**
+     *  @brief  This event notifies the application layer that Included Service that
+     *          includes 128-bit UUID Service has been discovered.
+     *
+     * ## Event Code: 0x40E8
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_inc_serv_128_evt_t
+     */
+    BLE_GATTC_EVENT_INC_SERV_128_DISC_IND = 0x40E8,     //!< BLE_GATTC_EVENT_INC_SERV_128_DISC_IND
+
+    /**
+     *  @brief  When the Included Service discovery by R_BLE_GATTC_DiscIncServ() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40E9
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_INC_SERV_DISC_COMP = 0x40E9,        //!< BLE_GATTC_EVENT_INC_SERV_DISC_COMP
+
+    /**
+     *  @brief  This event notifies the application layer that 16-bit UUID Characteristic has been discovered.
+     *
+     * ## Event Code: 0x40EA
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_char_16_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_16_DISC_IND = 0x40EA,          //!< BLE_GATTC_EVENT_CHAR_16_DISC_IND
+
+    /**
+     *  @brief  This event notifies the application layer that 128-bit UUID Characteristic has been discovered.
+     *
+     * ## Event Code: 0x40EB
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_char_128_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_128_DISC_IND = 0x40EB,         //!< BLE_GATTC_EVENT_CHAR_128_DISC_IND
+
+    /**
+     *  @brief  When the Characteristic discovery by R_BLE_GATTC_DiscAllChar() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40EC
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP = 0x40EC,        //!< BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP
+
+    /**
+     *  @brief  When the Characteristic discovery by R_BLE_GATTC_DiscCharByUuid() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40ED
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_CHAR_DISC_COMP = 0x40ED,            //!< BLE_GATTC_EVENT_CHAR_DISC_COMP
+
+    /**
+     *  @brief  This event notifies the application layer that 16-bit UUID Characteristic Descriptor
+     *          has been discovered.
+     *
+     * ## Event Code: 0x40EE
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_char_desc_16_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND = 0x40EE,     //!< BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND
+
+    /**
+     *  @brief  This event notifies the application layer that 128-bit UUID Characteristic Descriptor
+     *          has been discovered.
+     *
+     * ## Event Code: 0x40EF
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_char_desc_128_evt_t
+     */
+    BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND = 0x40EF,    //!< BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND
+
+    /**
+     *  @brief  When the Characteristic Descriptor discovery by R_BLE_GATTC_DiscAllCharDesc() has been completed,
+     *          this event is notified to the application layer.
+     *
+     * ## Event Code: 0x40F0
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP = 0x40F0,   //!< BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP
+
+    /**
+     *  @brief  After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer that all of
+     *          the contents of the Characteristic/Long Characteristic Descriptor has been received
+     *          from the GATT Server.
+     *
+     * ## Event Code: 0x40F1
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_LONG_CHAR_READ_COMP = 0x40F1,       //!< BLE_GATTC_EVENT_LONG_CHAR_READ_COMP
+
+    /**
+     *  @brief  This event notifies that the application layer that the write of
+     *          Long Characteristic/Long Characteristic Descriptor has been completed.
+     *
+     * ## Event Code: 0x40F2
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent
+     *                      a request for write by R_BLE_GATTC_WriteLongChar() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP = 0x40F2,      //!< BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP
+
+    /**
+     *  @brief  This event notifies that the application layer that
+     *          the GATT Server has received the data to be written to the Characteristics.
+     *
+     * ## Event Code: 0x40F3
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP = 0x40F3,   //!< BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP
+
+    /**
+     *  @brief  This event notifies the application layer that the Reliable Writes has been completed.
+     *
+     * ## Event Code: 0x40F4
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a
+     *                      request for execute write by R_BLE_GATTC_ReliableWrites() or
+     *                      R_BLE_GATTC_ExecWrite() to the GATT Server.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gattc_reliable_writes_comp_evt_t
+     */
+    BLE_GATTC_EVENT_RELIABLE_WRITES_COMP = 0x40F4,      //!< BLE_GATTC_EVENT_RELIABLE_WRITES_COMP
+
+    /**
+     *  @brief  Invalid GATT Client Event.
+     *
+     * ## Event Code: 0x40FF
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GATTC_EVENT_INVALID = 0x40FF                    //!< BLE_GATTC_EVENT_INVALID
+} e_r_ble_gattc_evt_t;
+
+/*@}*/
+
+/* ================================================== L2CAP Macro =================================================== */
+
+/** @addtogroup L2CAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/**
+ * @ingroup l2cap_api
+ * @def BLE_L2CAP_MAX_CBFC_PSM
+ * @brief The maximum number of callbacks that host stack can register.
+ */
+#define BLE_L2CAP_MAX_CBFC_PSM                (2)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_SUCCESS
+ * @brief Notify the remote device that the connection can be established.
+ */
+#define BLE_L2CAP_CF_RSP_SUCCESS              (0x0000)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH
+ * @brief Notify the remote device that the connection can not be established because of insufficient authentication.
+ */
+#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH       (0x0005)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ
+ * @brief Notify the remote device that the connection can not be established because of insufficient Authorization.
+ */
+#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ      (0x0006)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY
+ * @brief Notify the remote device that the connection can not be established because of Encryption Key Size.
+ */
+#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY    (0x0007)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC
+ * @brief Notify the remote device that the connection can not be established because of Encryption.
+ */
+#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC        (0x0008)
+
+/**
+ * @def BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM
+ * @brief Notify the remote device that the connection can not be established
+ *        because the parameters is unacceptable to local device.
+ */
+#define BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM      (0x000B)
+
+/*@}*/
+
+/* ============================================= Vendor Specific Macro ============================================== */
+
+/** @addtogroup VS_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/**
+ * @ingroup vs_api
+ * @def BLE_VS_TX_POWER_HIGH
+ * @brief High power level.
+ */
+#define BLE_VS_TX_POWER_HIGH            (0x00)
+
+/**
+ * @def BLE_VS_TX_POWER_MID
+ * @brief Middle power level.
+ */
+#define BLE_VS_TX_POWER_MID             (0x01)
+
+/**
+ * @def BLE_VS_TX_POWER_LOW
+ * @brief Low power level.
+ */
+#define BLE_VS_TX_POWER_LOW             (0x02)
+
+/**
+ * @def BLE_VS_ADDR_AREA_REG
+ * @brief Address in register is written or read.
+ */
+#define BLE_VS_ADDR_AREA_REG            (0x00)
+
+/**
+ * @def BLE_VS_ADDR_AREA_DATA_FLASH
+ * @brief Address in DataFlash is written or read.
+ */
+#define BLE_VS_ADDR_AREA_DATA_FLASH     (0x01)
+
+/**
+ * @def BLE_VS_EH_TX_PL_PRBS9
+ * @brief PRBS9 sequence '11111111100000111101..'.
+ */
+#define BLE_VS_EH_TX_PL_PRBS9           (0x00)
+
+/**
+ * @def BLE_VS_EH_TX_PL_11110000
+ * @brief Repeated '11110000'
+ */
+#define BLE_VS_EH_TX_PL_11110000        (0x01)
+
+/**
+ * @def BLE_VS_EH_TX_PL_10101010
+ * @brief Repeated '10101010'
+ */
+#define BLE_VS_EH_TX_PL_10101010        (0x02)
+
+/**
+ * @def BLE_VS_EH_TX_PL_PRBS15
+ * @brief PRBS15 sequence
+ */
+#define BLE_VS_EH_TX_PL_PRBS15          (0x03)
+
+/**
+ * @def BLE_VS_EH_TX_PL_11111111
+ * @brief Repeated '11111111'
+ */
+#define BLE_VS_EH_TX_PL_11111111        (0x04)
+
+/**
+ * @def BLE_VS_EH_TX_PL_00000000
+ * @brief Repeated '00000000'
+ */
+#define BLE_VS_EH_TX_PL_00000000        (0x05)
+
+/**
+ * @def BLE_VS_EH_TX_PL_00001111
+ * @brief Repeated '00001111'
+ */
+#define BLE_VS_EH_TX_PL_00001111        (0x06)
+
+/**
+ * @def BLE_VS_EH_TX_PL_01010101
+ * @brief Repeated '01010101'
+ */
+#define BLE_VS_EH_TX_PL_01010101        (0x07)
+
+/**
+ * @def BLE_VS_EH_TEST_PHY_1M
+ * @brief 1M PHY used in Transmitter/Receiver test.
+ */
+#define BLE_VS_EH_TEST_PHY_1M           (0x01)
+
+/**
+ * @def BLE_VS_EH_TEST_PHY_2M
+ * @brief 2M PHY used in Transmitter/Receiver test.
+ */
+#define BLE_VS_EH_TEST_PHY_2M           (0x02)
+
+/**
+ * @def BLE_VS_EH_TEST_PHY_CODED
+ * @brief Coded PHY used in Receiver test.
+ */
+#define BLE_VS_EH_TEST_PHY_CODED        (0x03)
+
+/**
+ * @def BLE_VS_EH_TEST_PHY_CODED_S_8
+ * @brief Coded PHY(S=8) used in Transmitter test.
+ */
+#define BLE_VS_EH_TEST_PHY_CODED_S_8    (0x03)
+
+/**
+ * @def BLE_VS_EH_TEST_PHY_CODED_S_2
+ * @brief Coded PHY(S=2) used in Transmitter test.
+ */
+#define BLE_VS_EH_TEST_PHY_CODED_S_2    (0x04)
+
+/**
+ * @def BLE_VS_RF_OFF
+ * @brief RF power off.
+ */
+#define BLE_VS_RF_OFF                   (0x00)
+
+/**
+ * @def BLE_VS_RF_ON
+ * @brief RF power on.
+ */
+#define BLE_VS_RF_ON                    (0x01)
+
+/**
+ * @def BLE_VS_RF_INIT_PARAM_NOT_CHG
+ * @brief The parameters are not changed in RF power on.
+ */
+#define BLE_VS_RF_INIT_PARAM_NOT_CHG    (0x00)
+
+/**
+ * @def BLE_VS_RF_INIT_PARAM_CHG
+ * @brief The parameters are changed in RF power on.
+ */
+#define BLE_VS_RF_INIT_PARAM_CHG        (0x01)
+
+/**
+ * @def BLE_VS_CS_PRIM_ADV_S_8
+ * @brief Coding scheme for Primary Advertising PHY(S=8).
+ */
+#define BLE_VS_CS_PRIM_ADV_S_8          (0x00)
+
+/**
+ * @def BLE_VS_CS_PRIM_ADV_S_2
+ * @brief Coding scheme for Primary Advertising PHY(S=2).
+ */
+#define BLE_VS_CS_PRIM_ADV_S_2          (0x01)
+
+/**
+ * @def BLE_VS_CS_SECOND_ADV_S_8
+ * @brief Coding scheme for Secondary Advertising PHY(S=8).
+ */
+#define BLE_VS_CS_SECOND_ADV_S_8        (0x00)
+
+/**
+ * @def BLE_VS_CS_SECOND_ADV_S_2
+ * @brief Coding scheme for Secondary Advertising PHY(S=2).
+ */
+#define BLE_VS_CS_SECOND_ADV_S_2        (0x02)
+
+/**
+ * @def BLE_VS_CS_CONN_S_8
+ * @brief Coding scheme for request for link establishment(S=8).
+ */
+#define BLE_VS_CS_CONN_S_8              (0x00)
+
+/**
+ * @def BLE_VS_CS_CONN_S_2
+ * @brief Coding scheme for request for link establishment(S=2).
+ */
+#define BLE_VS_CS_CONN_S_2              (0x04)
+
+/**
+ * @def BLE_VS_TX_FLOW_CTL_ON
+ * @brief  It means that the number of buffer has reached the High Water Mark from flow off state.
+ */
+#define BLE_VS_TX_FLOW_CTL_ON           (0x00)
+
+/**
+ * @def BLE_VS_TX_FLOW_CTL_OFF
+ * @brief  It means that the number of buffer has reached the Low Water Mark from flow on state.
+ */
+#define BLE_VS_TX_FLOW_CTL_OFF          (0x01)
+
+/*@}*/
+
+/* ============================================== GAP Type Definitions ============================================== */
+
+/** @addtogroup GAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @struct st_ble_evt_data_t
+ * @brief  st_ble_evt_data_t is the type of the data notified in a GAP Event.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The size of GAP Event parameters.
+     */
+    uint16_t param_len;
+
+    /**
+     *  @brief GAP Event parameters. This parameter differs in each GAP Event.
+     */
+    void * p_param;
+} st_ble_evt_data_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_dev_addr_t
+ *  @brief  st_ble_dev_addr_t is the type of bluetooth device address(BD_ADDR).
+ *  @note   The BD address setting format is little endian. \n
+ *          If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief BD_ADDR.
+     */
+    uint8_t addr[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief Bluetooth address type.
+     *  @details
+     *               |              macro        |   description     |
+     *               |:------------------------- |:----------------- |
+     *               | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address.   |
+     *               | BLE_GAP_ADDR_RAND(0x01)   | Random Address.   |
+     */
+    uint8_t type;
+} st_ble_dev_addr_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_gap_app_cb_t
+ * @brief   ble_gap_app_cb_t is the GAP Event callback function type.
+ * @param[in] event_type    The type of GAP Event.
+ * @param[in] event_result  The result of API call which generates the GAP Event.
+ * @param[in] p_event_data  Data notified in the GAP Event.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_gap_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data);
+
+/******************************************************************************************************************//**
+ * @typedef ble_gap_del_bond_cb_t
+ * @brief   ble_gap_del_bond_cb_t is the type of the callback function for delete bonding information
+ *          stored in non-volatile area. \n This type is used in R_BLE_GAP_DeleteBondInfo().
+ * @param[in] p_addr The parameter returns the address of the remote device whose keys are deleted
+ *            by R_BLE_GAP_DeleteBondInfo(). \n
+ *            If R_BLE_GAP_DeleteBondInfo() deletes the keys of all remote devices, the parameter returns NULL.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_gap_del_bond_cb_t)(st_ble_dev_addr_t * p_addr);
+
+/* =========================================== GAP API Params Definitions =========================================== */
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_ext_adv_param_t
+ * @brief  Advertising parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle identifying the advertising set to be set the advertising parameters.
+     *  @details
+     *  Valid range is 0x00 - 0x03.\n
+     *  In the first advertising parameters setting, the advertising set specified by adv_hdl is generated.\n
+     *  The Advertising Set ID(Advertising SID) of the advertising set is same as adv_hdl.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief Advertising packet type.
+     *  @details
+     *  Legacy advertising PDU type, or bitwise or of Extended advertising PDU type and Extended advertising option.
+     *  
+     *      
+     *          
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
categorymacrodescription
Legacy Advertising PDU typeBLE_GAP_LEGACY_PROP_ADV_IND(0x0013)Connectable and scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND(0x0015)Connectable directed (low duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND(0x001D)Connectable directed (high duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_SCAN_IND(0x0012)Scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND(0x0010)Non-connectable and non-scannable undirected Legacy Advertising Packet
Extended Advertising PDU typeBLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT(0x0001)Connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT(0x0005)Connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT(0x000D)Connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT(0x0002)Non-connectable and scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT(0x0006)Non-connectable and scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT(0x000E)Non-connectable and scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT(0x0000)Non-connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT(0x0004)Non-connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT(0x000C)Non-connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
Extended Advertising OptionBLE_GAP_EXT_PROP_ADV_ANONYMOUS(0x0020)Omit the advertiser address from Extended Advertising Packet.
BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER(0x0040)Indicate that the advertising data includes TX Power.

+     */
+    uint16_t adv_prop_type;
+
+    /**
+     *  @brief Minimum advertising interval.
+     *  @details
+     *  Time(ms) = adv_intv_min * 0.625.\n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t adv_intv_min;
+
+    /**
+     *  @brief Maximum Advertising interval.
+     *  @details
+     *  Time(ms) = adv_intv_max * 0.625.\n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t adv_intv_max;
+
+    /**
+     *  @brief The adv_ch_map is channels used in advertising with primary advertising channels.
+     *  @details
+     *  It is a bitwise OR of the following values.
+     *               |              macro        |   description     |
+     *               |:------------------------- |:----------------- |
+     *               | BLE_GAP_ADV_CH_37(0x01)   | Use 37 CH.        |
+     *               | BLE_GAP_ADV_CH_38(0x02)   | Use 38 CH.        |
+     *               | BLE_GAP_ADV_CH_39(0x04)   | Use 39 CH.        |
+     *               | BLE_GAP_ADV_CH_ALL(0x07)  | Use 37 - 39 CH.   |
+     */
+    uint8_t adv_ch_map;
+
+    /**
+     *  @brief Own BD Address Type.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)
+     *              Resolvable Private Address.

+     *              If the IRK of local device has not been registered in Resolving List,
+     *              public address is used.
+     *          
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03)
+     *              Resolvable Private Address.

+     *              If the IRK of local device has not been registered in Resolving List,
+     *              the random address specified by the o_addr field is used.
+     *          

+     */
+    uint8_t o_addr_type;
+
+    /**
+     *  @brief Random address set to the advertising set, when the o_addr_type field is BLE_GAP_ADDR_RAND.
+     *  @details When the o_addr_type field is other than BLE_GAP_ADDR_RAND, this field is ignored.
+     *  @note   The BD address setting format is little endian. \n
+     *          If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order
+     *          {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}.
+     */
+    uint8_t o_addr[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief Peer address type.
+     *  @details
+     *  When the Advertising PDU type is other than directed or the o_addr_type is BLE_GAP_ADDR_PUBLIC or
+     *  BLE_GAP_ADDR_RAND,this field is ignored.
+     *               |              macro        |   description     |
+     *               |:------------------------- |:----------------- |
+     *               | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address    |
+     *               | BLE_GAP_ADDR_RAND(0x01)   | Random Address    |
+     */
+    uint8_t p_addr_type;
+
+    /**
+     *  @brief Peer address.
+     *  @details When the Advertising PDU type is other than directed or
+     *           the o_addr_type is BLE_GAP_ADDR_PUBLIC or BLE_GAP_ADDR_RAND,this field is ignored.
+     *  @note   The BD address setting format is little endian. \n
+     *          If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order
+     *          {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}.
+     */
+    uint8_t p_addr[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief Advertising Filter Policy.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY(0x00)Process scan and connection requests from all devices.
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY(0x01)
+     *              Process connection requests from all devices and scan requests
+     *              from only devices that are in the White List.
+     *          
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST(0x02)
+     *              Process scan requests from all devices and connection requests from
+     *              only devices that are in the White List.
+     *          
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST(0x03)Process scan and connection requests from only devices in the White List.

+     */
+    uint8_t filter_policy;
+
+    /**
+     *  @brief Primary ADV PHY.
+     *  @details
+     *  In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified.
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_ADV_PHY_1M(0x01)
+     *              Use 1M PHY as Primary Advertising PHY.

+     *              When the adv_prop_type field is Legacy Advertising PDU type, 

+     *              this field shall be set to BLE_GAP_ADV_PHY_1M.
+     *          
BLE_GAP_ADV_PHY_CD(0x03)Use Coded PHY(S=8) as Primary Advertising PHY.
+     *               Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().

+     */
+    uint8_t adv_phy;
+
+    /**
+     *  @brief Secondary ADV Max Skip.
+     *  @details
+     *  Valid range is 0x00 - 0xFF.\n
+     *  When this field is 0x00, AUX_ADV_IND is sent before the next advertising event.\n
+     *  When the adv_prop_type field is Legacy Advertising PDU, this field is ignored.
+     */
+    uint8_t sec_adv_max_skip;
+
+    /**
+     *  @brief Secondary ADV Phy.
+     *  @details
+     *  When the adv_prop_type is Legacy Advertising PDU, this field is ignored.
+     *               |              macro        |   description                                    |
+     *               |:------------------------- |:------------------------------------------------ |
+     *               | BLE_GAP_ADV_PHY_1M(0x01)  | Use 1M PHY as Secondary Advertising PHY.         |
+     *               | BLE_GAP_ADV_PHY_2M(0x02)  | Use 2M PHY as Secondary Advertising PHY.         |
+     *               | BLE_GAP_ADV_PHY_CD(0x03)  | Use Coded PHY(S=8) as Secondary Advertising PHY. |
+     *
+     *  Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().
+     */
+    uint8_t sec_adv_phy;
+
+    /**
+     *  @brief Scan Request Notifications Flag.
+     *  @details
+     *  When the adv_prop_type field is non-scannable Advertising PDU, this field is ignored.
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_SCAN_REQ_NTF_DISABLE(0x00)Disable Scan Request Notification.
BLE_GAP_SCAN_REQ_NTF_ENABLE(0x01)
+     *                  Enable Scan Request Notification.

+     *                  When a Scan Request Packet from Scanner has been received,
+     *                  the BLE_GAP_EVENT_SCAN_REQ_RECV event is notified.
+     *              

+     */
+    uint8_t scan_req_ntf_flag;
+} st_ble_gap_ext_adv_param_t;
+
+/******************************************************************************************************************//**
+ * @brief  Advertising parameters.
+ * @sa st_ble_gap_ext_adv_param_t
+ **********************************************************************************************************************/
+typedef st_ble_gap_ext_adv_param_t st_ble_gap_adv_param_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_adv_data_t
+ * @brief  Advertising data/scan response data/periodic advertising data.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle identifying the advertising set to be
+     *         set advertising data/scan response/periodic advertising data.
+     *  @details
+     *  Valid range is 0x00 - 0x03.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief Data type.
+     *  @details
+     *               |              macro                 |   description              |
+     *               |:---------------------------------- |:-------------------------- |
+     *               | BLE_GAP_ADV_DATA_MODE (0x00)       | Advertising data.          |
+     *               | BLE_GAP_SCAN_RSP_DATA_MODE(0x01)   | Scan response data.        |
+     *               | BLE_GAP_PERD_ADV_DATA_MODE(0x02)   | Periodic advertising data. |
+     */
+    uint8_t data_type;
+
+    /**
+     *  @brief The length of advertising data/scan response data/periodic advertising data (in bytes).
+     *  @details
+     *   In case of Legacy Advertising PDU, the length is 0 - 31 bytes.\n
+     *   In case of Extended Advertising PDU, the length is 0 - 1650 bytes.\n
+     *   Note that the length of the advertising data/scan response data in
+     *   the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of the advertising sets may not exceed
+     *   the buffer size(4250 bytes) in Controller. \n
+     *   \n
+     *   In case of periodic advertising data, the length is 0 - 1650 bytes.\n
+     *   Note that the length of the periodic advertising data in the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of
+     *   the advertising sets may not exceed the buffer size(4306 bytes) in Controller.\n
+     *   \n
+     *   When this field is 0, the operations specified by the zero_length_flag is executed.
+     */
+    uint16_t data_length;
+
+    /**
+     *  @brief Advertising data/scan response data/periodic advertising data.
+     *  @details
+     *  When the data_length field is 0, this field is ignored.
+     */
+    uint8_t * p_data;
+
+    /**
+     *  @brief Operation when the data_length field is 0.
+     *  @details
+     *   If the data_length is other than 0, this field is ignored.
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_DATA_0_CLEAR(0x01)
+     *                  Clear the advertising data/scan response data/periodic advertising data
+     *                  in the advertising set.
+     *              
BLE_GAP_DATA_0_DID_UPD(0x02)Update Advertising DID without changing advertising data.
+     *                  If the data_type field is BLE_GAP_ADV_DATA_MODE, this value is allowed.
+     *              

+     */
+    uint8_t zero_length_flag;
+} st_ble_gap_adv_data_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_perd_adv_param_t
+ * @brief  Periodic advertising parameter.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle identifying the advertising set to be set periodic advertising parameter.
+     *  @details
+     *  Valid range is 0x00 - 0x03.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief Periodic ADV Properties.
+     *  @details
+     *  The prop_type field is set to the following values.\n
+     *  If the type of the periodic advertising data cannot be applied from the following, set 0x0000.
+     *    |              macro                 |   description                                                |
+     *    |:---------------------------------- |:------------------------------------------------------------ |
+     *    | BLE_GAP_PERD_PROP_TX_POWER(0x0040) |  Indicate that periodic advertising data includes Tx Power.  |
+     */
+    uint16_t prop_type;
+
+    /**
+     *  @brief Minimum Periodic Advertising Interval.
+     *  @details
+     *  Time(ms) = perd_intv_min * 1.25.\n
+     *  Valid range is 0x0006 - 0xFFFF.
+     */
+    uint16_t perd_intv_min;
+
+    /**
+     *  @brief Maximum Periodic Advertising Interval.
+     *  @details
+     *  Time(ms) = perd_intv_max * 1.25.\n
+     *  Valid range is 0x0006 - 0xFFFF.
+     */
+    uint16_t perd_intv_max;
+} st_ble_gap_perd_adv_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_scan_phy_param_t
+ *  @brief  Scan parameters per scan PHY.
+ *  @details In case of start scanning with both 1M PHY and Coded PHY,
+ *           adjust scan windows and scan intervals according to the following.\n
+ *           ``` p_phy_param_1M->scan_window / p_phy_param_1M->scan_intv +
+ *                p_phy_param_coded->scan_window / p_phy_param_coded->scan_intv <= 1  ```
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Scan type.
+     *  @details
+     *    |              macro             |   description               |
+     *    |:-------------------------------|:--------------------------- |
+     *    | BLE_GAP_SCAN_PASSIVE(0x00)     | Passive Scan.               |
+     *    | BLE_GAP_SCAN_ACTIVE(0x01)      | Active Scan.                |
+     */
+    uint8_t scan_type;
+
+    /**
+     *  @brief Scan interval.
+     *  @details
+     *  interval(ms) = scan_intv * 0.625.\n
+     *  Valid range is 0x0000 and 0x0004 - 0xFFFF.
+     */
+    uint16_t scan_intv;
+
+    /**
+     *  @brief Scan window.
+     *  @details
+     *  window(ms) = scan_window * 0.625.\n
+     *  Valid range is 0x0000 and 0x0004 - 0xFFFF.
+     */
+    uint16_t scan_window;
+} st_ble_gap_scan_phy_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_ext_scan_param_t
+ *  @brief  Scan parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Own BD Address Type.
+     *  @details
+     *  In case of passive scan, this field is ignored.
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)
+     *              Resolvable Private Address.

+     *              If the IRK of local device has not been registered in Resolving List,
+     *              public address is used.
+     *          
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03)
+     *              Resolvable Private Address.

+     *              If the IRK of local device has not been registered in Resolving List,
+     *              the random address set by R_BLE_GAP_SetRandAddr() is used.
+     *          

+     */
+    uint8_t o_addr_type;
+
+    /**
+     *  @brief Scan Filter Policy.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_SCAN_ALLOW_ADV_ALL(0x00)
+     *              Accept all advertising and scan response PDUs except directed advertising
+     *              PDUs not addressed to local device.
+     *          
BLE_GAP_SCAN_ALLOW_ADV_WLST(0x01)
+     *              Accept only advertising and scan response PDUs from remote devices
+     *              whose address is registered in the White List.

+     *              Directed advertising PDUs which are not addressed to local device is ignored.
+     *          
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED(0x02)
+     *              Accept all advertising and scan response PDUs except directed advertising
+     *              PDUs whose the target address is identity address but doesn't address local device.
+     *              However directed advertising PDUs whose the target address is the local resolvable private address
+     *              are accepted.
+     *          
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST(0x03)Accept all advertising and scan response PDUs.

+     *              The following are excluded.

+     *              
    
+     *                  
  • 
+     *                      Advertising and scan response PDUs where the advertiser's
+     *                      identity address is not in the White List.
+     *                  
    • 
+     *                  
  • 
+     *                      Directed advertising PDUs whose the target address is identity address
+     *                      but doesn't address local device.
+     *                      However directed advertising PDUs whose the target address is the local
+     *                      resolvable private address are accepted.
+     *                  
    • 
+     *              

+     *          

+     */
+    uint8_t filter_policy;
+
+    /**
+     *  @brief Scan parameters 1M PHY.
+     *  @details When this field is NULL, Controller doesn't set the scan parameters for 1M PHY.
+     */
+    st_ble_gap_scan_phy_param_t * p_phy_param_1M;
+
+    /**
+     *  @brief Scan parameters Coded PHY.
+     *  @details When this field is NULL, Controller doesn't set the scan parameters for Coded PHY.
+     */
+    st_ble_gap_scan_phy_param_t * p_phy_param_coded;
+} st_ble_gap_ext_scan_param_t;
+
+/******************************************************************************************************************//**
+ * @brief  Scan parameters.
+ * @sa st_ble_gap_ext_scan_param_t
+ **********************************************************************************************************************/
+typedef st_ble_gap_ext_scan_param_t st_ble_gap_scan_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_scan_on_t
+ *  @brief  Parameters configured when scanning starts.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Procedure type.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_SC_PROC_OBS(0x00)
+     *              Observation Procedure.

+     *              Notify all advertising PDUs.
+     *          
BLE_GAP_SC_PROC_LIM(0x01)
+     *              Limited Discovery Procedure.

+     *              Notify advertising PDUs from only devices in the limited discoverable mode.
+     *          
BLE_GAP_SC_PROC_GEN(0x02)
+     *              General Discovery Procedure.

+     *              Notify advertising PDUs from devices in the limited discoverable mode and
+     *              the general discoverable mode.
+     *          

+     */
+    uint8_t proc_type;
+
+    /**
+     *  @brief Filter duplicates.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
macrodescription
BLE_GAP_SCAN_FILT_DUPLIC_DISABLE(0x00)Duplicate filter disabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE(0x01)Duplicate filter enabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02)Duplicate filtering enabled, reset for each scan period

+     */
+    uint8_t filter_dups;
+
+    /**
+     *  @brief Scan duration.
+     *  @details Time(ms) = duration * 10.\n
+     *           Valid range is 0x0000 - 0xFFFF.\n
+     *           If this field is set to 0x0000, scanning is continued until R_BLE_GAP_StopScan() is called.\n
+     *           When the period field is zero and the time specified the duration field expires,
+     *           BLE_GAP_EVENT_SCAN_TO event notifies the application layer that scanning stops.
+     */
+    uint16_t duration;
+
+    /**
+     *  @brief Scan period.
+     *  @details Time(s) = N * 1.28.\n
+     *           Valid range is 0x0000 - 0xFFFF.\n
+     *           If the duration field is set to 0x0000, this field is ignored.
+     */
+    uint16_t period;
+} st_ble_gap_scan_on_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_conn_param_t
+ * @brief  Connection parameters included in connection interval, slave latency, supervision timeout, ce length.
+ * @details This structure is used in R_BLE_GAP_CreateConn() and R_BLE_GAP_UpdConn().
+ *
+ * Set the fields in this structure to match the following condition.
+ *
+ * Supervision_timeout(ms) >= (1 + conn_latency) * conn_intv_max_Time(ms)
+ *
+ *  conn_intv_max_Time(ms) = conn_intv_max * 1.25
+ *  Supervision_timeout(ms) = sup_to * 10
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Minimum connection interval.
+     *  @details
+     *           Time(ms) = conn_intv_min * 1.25.\n
+     *           Valid range is 0x0006 - 0x0C80.
+     */
+    uint16_t conn_intv_min;
+
+    /**
+     *  @brief Maximum connection interval.
+     *  @details
+     *           Time(ms) = conn_intv_max * 1.25.\n
+     *           Valid range is 0x0006 - 0x0C80.
+     */
+    uint16_t conn_intv_max;
+
+    /**
+     *  @brief Slave latency.
+     *  @details
+     *           Valid range is 0x0000 - 0x01F3.
+     */
+    uint16_t conn_latency;
+
+    /**
+     *  @brief Supervision timeout.
+     *  @details
+     *           Time(ms) = sup_to * 10.\n
+     *           Valid range is 0x000A - 0x0C80.
+     */
+    uint16_t sup_to;
+
+    /**
+     *  @brief Minimum CE Length.
+     *  @details
+     *           Valid range is 0x0000 - 0xFFFF.
+     */
+    uint16_t min_ce_length;
+
+    /**
+     *  @brief Maximum CE Length.
+     *  @details
+     *           Valid range is 0x0000 - 0xFFFF.
+     */
+    uint16_t max_ce_length;
+} st_ble_gap_conn_param_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_conn_phy_param_t
+ * @brief  Connection parameters per PHY.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  Scan interval.
+     *  @details
+     *  Time(ms) = scan_intv * 0.625.\n
+     *  Valid range is 0x0004 - 0xFFFF.
+     */
+    uint16_t scan_intv;
+
+    /**
+     *  @brief  Scan window.
+     *  @details
+     *  Time(ms) = scan_window  * 0.625.\n
+     *  Valid range is 0x0004 - 0xFFFF.
+     */
+    uint16_t scan_window;
+
+    /**
+     *  @brief  Connection interval, slave latency, supervision timeout, and CE length.
+     */
+    st_ble_gap_conn_param_t * p_conn_param;
+} st_ble_gap_conn_phy_param_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_gap_create_conn_param_t
+ * @brief  Connection parameters used in R_BLE_GAP_CreateConn().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief This field specifies whether the White List is used or not, when connecting with a remote device.
+     *  @details
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_INIT_FILT_USE_ADDR(0x00)White List is not used.

+     *                  The remote device to be connected is specified by the remote_bd_addr field and 

+     *                  the remote_bd_addr_type field is used.
+     *              
BLE_GAP_INIT_FILT_USE_WLST(0x01)White List is used.

+     *                  The remote device registered in White List is connected with local device.

+     *                  The remote_bd_addr field and the remote_bd_addr_type field are ignored.
+     *              

+     */
+    uint8_t init_filter_policy;
+
+    /**
+     *  @brief Address of the device to be connected.
+     *  @note   The BD address setting format is little endian. \n
+     *          If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order
+     *          {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}.
+     */
+    uint8_t remote_bd_addr[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief  Address type of the device to be connected.
+     *  @details
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address or Public Identity Address
BLE_GAP_ADDR_RAND(0x01)Random Address or Random (Static) Identity Address

+     */
+    uint8_t remote_bd_addr_type;
+
+    /**
+     *  @brief  Address type which local device uses in creating a link with the remote device.
+     *  @details
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)
+     *                  Resolvable Private Address.\n
+     *                  If the IRK of local device has not been registered in Resolving List,
+     *                  public address is used.
+     *              
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03)
+     *                  Resolvable Private Address.\n
+     *                  If the IRK of local device has not been registered in Resolving List,
+     *                  the random address set by R_BLE_GAP_SetRandAddr().
+     *              

+     */
+    uint8_t own_addr_type;
+
+    /**
+     *  @brief Connection parameters for 1M PHY.
+     *  @details If this field is set to NULL, 1M PHY is not used in connecting.
+     */
+    st_ble_gap_conn_phy_param_t * p_conn_param_1M;
+
+    /**
+     *  @brief Connection parameters for 2M PHY.
+     *  @details If this field is set to NULL, 2M PHY is not used in connecting.
+     */
+    st_ble_gap_conn_phy_param_t * p_conn_param_2M;
+
+    /**
+     *  @brief Connection parameters for Coded PHY.
+     *  @details If this field is set to NULL, Coded PHY is not used in connecting.
+     */
+    st_ble_gap_conn_phy_param_t * p_conn_param_coded;
+} st_ble_gap_create_conn_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rslv_list_key_set_t
+ *  @brief  IRK of a remote device and IRK type of local device used in R_BLE_GAP_ConfRslvList().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief IRK of a remote device to be registered in the Resolving List.
+     */
+    uint8_t remote_irk[BLE_GAP_IRK_SIZE];
+
+    /**
+     *  @brief IRK type of the local device to be registered in the Resolving List.
+     *  @details
+     *               |              macro                    |   description                                      |
+     *               |:------------------------------------- |:-------------------------------------------------- |
+     *               | BLE_GAP_RL_LOC_KEY_ALL_ZERO(0x00)     | All-zero IRK.                                      |
+     *               | BLE_GAP_RL_LOC_KEY_REGISTERED(0x01)    | The IRK registered by R_BLE_GAP_SetLocIdInfo().   |
+     */
+    uint8_t local_irk_type;
+} st_ble_gap_rslv_list_key_set_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_set_phy_param_t
+ *  @brief  PHY configuration parameters used in R_BLE_GAP_SetPhy().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Transmitter PHY preference.
+     *  @details The tx_phys field is set to a bitwise OR of the following values. All other values are ignored.
+     *               |              macro                    |   description                      |
+     *               |:------------------------------------- |:---------------------------------- |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01)   | Use 1M PHY for Transmitter PHY.    |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02)   | Use 2M PHY for Transmitter PHY.    |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04)   | Use Coded PHY for Transmitter PHY. |
+     */
+    uint8_t tx_phys;
+
+    /**
+     *  @brief Receiver PHY preference.
+     *  @details The rx_phys field is set to a bitwise OR of the following values. All other values are ignored.
+     *               |              macro                    |   description                      |
+     *               |:------------------------------------- |:---------------------------------- |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01)   | Use 1M PHY for Receiver PHY.       |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02)   | Use 2M PHY for Receiver PHY.       |
+     *               | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04)   | Use Coded PHY for Receiver PHY.    |
+     */
+    uint8_t rx_phys;
+
+    /**
+     *  @brief Coding scheme used in Coded PHY.
+     *  @details Select one of the following.
+     *               |              macro                       |   description           |
+     *               |:---------------------------------------- |:----------------------- |
+     *               | BLE_GAP_SET_PHYS_OP_HOST_NO_PREF(0x00)   | No preferred coding.    |
+     *               | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2(0x01)  | Use S=2 coding.         |
+     *               | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8(0x02)  | Use S=8 coding.         |
+     */
+    uint16_t phy_options;
+} st_ble_gap_set_phy_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_set_def_phy_param_t
+ *  @brief  PHY preferences which allows a remote device to set used in R_BLE_GAP_SetDefPhy().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Transmitter PHY preferences which a remote device may change.
+     *  @details The tx_phys field is set to a bitwise OR of the following values.
+     *           All other values are ignored.
+     *          |              macro                    |   description                                               |
+     *          |:------------------------------------- |:----------------------------------------------------------- |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01)   | Allow a remote device to set 1M PHY for transmitter PHY.    |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02)   | Allow a remote device to set 2M PHY for transmitter PHY.    |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04)   | Allow a remote device to set Coded PHY for transmitter PHY. |
+     */
+    uint8_t tx_phys;
+
+    /**
+     *  @brief Receiver PHY preferences which a remote device may change.
+     *  @details The rx_phys field is set to a bitwise OR of the following values.
+     *           All other values are ignored.
+     *          |              macro                    |   description                                            |
+     *          |:------------------------------------- |:-------------------------------------------------------- |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01)   | Allow a remote device to set 1M PHY for receiver PHY.    |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02)   | Allow a remote device to set 2M PHY for receiver PHY.    |
+     *          | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04)   | Allow a remote device to set Coded PHY for receiver PHY. |
+     */
+    uint8_t rx_phys;
+} st_ble_gap_set_def_phy_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_auth_info_t
+ *  @brief  Pairing parameters required from a remote device or
+ *          information about keys distributed from a remote device.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Security level.
+     *  @details
+     *    |  value  |   description                                         |
+     *    |:--------|:----------------------------------------------------- |
+     *    | 0x01    | The remote device requests Unauthenticated pairing.   |
+     *    | 0x02    | The remote device requests Authenticated pairing.     |
+     */
+    uint8_t security;
+
+    /**
+     *  @brief  Pairing mode.
+     *  @details
+     *    |  value  |   description                                         |
+     *    |:--------|:----------------------------------------------------- |
+     *    | 0x01    | The remote device requests Legacy pairing.            |
+     *    | 0x02    | The remote device requests Secure Connections.        |
+     */
+    uint8_t pair_mode;
+
+    /**
+     *  @brief  Bonding policy.
+     *  @details
+     *    |  value  |   description                                                   |
+     *    |:--------|:--------------------------------------------------------------- |
+     *    | 0x00    | The remote device does not store the Bonding information.       |
+     *    | 0x01    | The remote device stores the Bonding information.               |
+     */
+    uint8_t bonding;
+
+    /**
+     *  @brief  Encryption key size.
+     */
+    uint8_t ekey_size;
+} st_ble_gap_auth_info_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_key_dist_t
+ *  @brief  Keys distributed from a remote device.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   LTK.
+     */
+    uint8_t enc_info[BLE_GAP_LTK_SIZE];
+
+    /**
+     *  @brief   Ediv and rand.
+     *           The first two bytes is ediv, the remaining bytes are rand.
+     */
+    uint8_t mid_info[BLE_GAP_EDIV_SIZE + BLE_GAP_RAND_64_BIT_SIZE];
+
+    /**
+     *  @brief   IRK
+     */
+    uint8_t id_info[BLE_GAP_IRK_SIZE];
+
+    /**
+     *  @brief   Identity address. The first byte is address type. The remaining bytes are device address.
+     */
+    uint8_t id_addr_info[BLE_GAP_ID_ADDR_SIZE];
+
+    /**
+     *  @brief   CSRK
+     */
+    uint8_t sign_info[BLE_GAP_CSRK_SIZE];
+} st_ble_gap_key_dist_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_key_ex_param_t
+ *  @brief  This structure includes the distributed keys and negotiated LTK size.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Key information.
+     */
+    st_ble_gap_key_dist_t * p_keys_info;
+
+    /**
+     * @brief   Type of the distributed keys.
+     * @details
+     *  This field is a bitwise OR of the following values.
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
Bit Numberdescription
0
+     *              LTK and Master Identification.

+     *              LTK is distributed in Secure Connections, even if the bit is 1.
+     *          
1IRK and Identity Address Information.
2CSRK

+     */
+    uint8_t keys;
+
+    /**
+     *  @brief   The negotiated LTK size.
+     */
+    uint8_t ekey_size;
+} st_ble_gap_key_ex_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_pairing_param_t
+ *  @brief  Pairing parameters used in R_BLE_GAP_SetPairingParams().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  IO capabilities of local device.
+     *  @details
+     *   Select one of the following.
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_IOCAP_DISPLAY_ONLY(0x00)
+     *                  Output function : Local device has the ability to display a 6 digit decimal number.

+     *                  Input function  : None

+     *              
BLE_GAP_IOCAP_DISPLAY_YESNO(0x01)
+     *                  Output function : Output function : Local device has the ability to
+     *                                    display a 6 digit decimal number.

+     *                  Input function  : Local device has the ability to indicate 'yes' or 'no'

+     *              
BLE_GAP_IOCAP_KEYBOARD_ONLY(0x02)
+     *                  Output function : None

+     *                  Input function  : Local device has the ability to input the number '0' - '9'.

+     *              
BLE_GAP_IOCAP_NOINPUT_NOOUTPUT(0x03)
+     *                  Output function : None

+     *                  Input function  : None

+     *              
BLE_GAP_IOCAP_KEYBOARD_DISPLAY(0x04)
+     *                  Output function : Output function : Local device has the ability to
+     *                                                      display a 6 digit decimal number.

+     *                  Input function  : Local device has the ability to input the number '0' - '9'.

+     *              

+     */
+    uint8_t iocap;
+
+    /**
+     *  @brief  MITM protection policy.
+     *  @details
+     *   Select one of the following.
+     *    |              macro                 |  description                   |
+     *    |:---------------------------------- |:------------------------------ |
+     *    | BLE_GAP_SEC_MITM_BEST_EFFORT(0x00) | MITM Protection not required.  |
+     *    | BLE_GAP_SEC_MITM_STRICT (0x01)     | MITM Protection required.      |
+     */
+    uint8_t mitm;
+
+    /**
+     *  @brief  Bonding policy.
+     *  @details
+     *    |              macro                 |   description                                     |
+     *    |:---------------------------------- |:------------------------------------------------- |
+     *    | BLE_GAP_BONDING_NONE(0x00)         | Local device doesn't stores Bonding information.  |
+     *    | BLE_GAP_BONDING (0x01)             | Local device stores Bonding information.          |
+     */
+    uint8_t bonding;
+
+    /**
+     *  @brief Maximum LTK size(in bytes).
+     *  @details
+     *  Valid range is 7 - 16.\n
+     *  This field shall be set to a value not less than the min_key_size field.
+     */
+    uint8_t max_key_size;
+
+    /**
+     *  @brief Minimum LTK size(in bytes).
+     *  @details
+     *  Valid range is 7 - 16.\n
+     *  This field shall be set to a value not more than the max_key_size field.
+     */
+    uint8_t min_key_size;
+
+    /**
+     *  @brief Type of keys to be distributed from local device.
+     *  @details
+     *  The loc_key_dist field is set to a bitwise OR of the following values.
+     *    |              macro             |   description               |
+     *    |:-------------------------------|:--------------------------- |
+     *    | BLE_GAP_KEY_DIST_ENCKEY(0x01)  | LTK                         |
+     *    | BLE_GAP_KEY_DIST_IDKEY(0x02)   | IRK and Identity Address.   |
+     *    | BLE_GAP_KEY_DIST_SIGNKEY(0x04) | CSRK                        |
+     */
+    uint8_t loc_key_dist;
+
+    /**
+     *  @brief Type of keys which local device requests a remote device to distribute.
+     *  @details
+     *  The rem_key_dist field is set to a bitwise OR of the following values.
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GAP_KEY_DIST_ENCKEY(0x01)
+     *                  LTK. In case of Secure Connections, LTK is notified even if this bit is not set.
+     *              
BLE_GAP_KEY_DIST_IDKEY(0x02)
+     *                  IRK and Identity Address.
+     *              
BLE_GAP_KEY_DIST_SIGNKEY(0x04)
+     *                  CSRK
+     *              

+     */
+    uint8_t rem_key_dist;
+
+    /**
+     *  @brief Support for Key Press Notification in Passkey Entry.
+     *  @details
+     *    |              macro                       |   description                            |
+     *    |:-----------------------------------------|:---------------------------------------- |
+     *    | BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT(0x00)  | Not support for Key Press Notification.  |
+     *    | BLE_GAP_SC_KEY_PRESS_NTF_SPRT(0x01)      | Support for Key Press Notification.      |
+     */
+    uint8_t key_notf;
+
+    /**
+     *  @brief Determine whether to accept only Secure Connections or not.
+     *  @details
+     *    |              macro            |   description                                 |
+     *    |:------------------------------|:--------------------------------------------- |
+     *    | BLE_GAP_SC_BEST_EFFORT(0x00)  | Accept Legacy pairing and Secure Connections.  |
+     *    | BLE_GAP_SC_STRICT(0x01)       |  Accept only Secure Connections.               |
+     */
+    uint8_t sec_conn_only;
+} st_ble_gap_pairing_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_oob_data_t
+ *  @brief  Oob data received from the remote device. This is used in R_BLE_GAP_SetRemOobData().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief OOB data used in Legacy Pairing.
+     */
+    uint8_t legacy_oob[BLE_GAP_LEGACY_OOB_SIZE];
+
+    /**
+     *  @brief OOB confirmation value used in Secure Connections.
+     */
+    uint8_t sc_cnf_val[BLE_GAP_OOB_CONFIRM_VAL_SIZE];
+
+    /**
+     *  @brief OOB rand used in Secure Connections.
+     */
+    uint8_t sc_rand[BLE_GAP_OOB_RANDOM_VAL_SIZE];
+} st_ble_gap_oob_data_t;
+
+/* ============================================== GAP Event Parameters ============================================== */
+
+/*  Event Code : BLE_GAP_EVENT_STACK_ON  : none */
+
+/*  Event Code : BLE_GAP_EVENT_STACK_OFF : none */
+
+/*  Event Code : BLE_GAP_EVENT_LOC_VER_INFO : st_ble_gap_loc_dev_info_evt_t */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_ver_num_t
+ *  @brief  Version number of host stack.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  Major version number.
+     */
+    uint8_t major;
+
+    /**
+     *  @brief  Minor version number.
+     */
+    uint8_t minor;
+
+    /**
+     *  @brief  Subminor version number.
+     */
+    uint8_t subminor;
+} st_ble_gap_ver_num_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_loc_ver_info_t
+ *  @brief  Version number of Controller.
+ *  @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers).
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  Bluetooth HCI version.
+     */
+    uint8_t hci_ver;
+
+    /**
+     *  @brief   Bluetooth HCI revision.
+     */
+    uint16_t hci_rev;
+
+    /**
+     *  @brief   Link Layer revision.
+     */
+    uint8_t lmp_ver;
+
+    /**
+     *  @brief   Manufacturer ID.
+     */
+    uint16_t mnf_name;
+
+    /**
+     *  @brief   Link Layer subversion.
+     */
+    uint16_t lmp_sub_ver;
+} st_ble_gap_loc_ver_info_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_loc_dev_info_evt_t
+ *  @brief  Version information of local device.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Bluetooth Device Address.
+     */
+    st_ble_dev_addr_t l_dev_addr;
+
+    /**
+     *  @brief   Version number of host stack in local device.
+     */
+    st_ble_gap_ver_num_t l_ver_num;
+
+    /**
+     *  @brief   Version number of Controller in local device.
+     */
+    st_ble_gap_loc_ver_info_t l_bt_info;
+} st_ble_gap_loc_dev_info_evt_t;
+
+/*  Event Code : BLE_GAP_EVENT_HW_ERR : st_ble_gap_hw_err_evt_t */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_hw_err_evt_t
+ *  @brief  Hardware error that is notified from Controller.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   The hw_code field indicates the cause of the hardware error.
+     */
+    uint8_t hw_code;
+} st_ble_gap_hw_err_evt_t;
+
+/*  Event Code : BLE_GAP_EVENT_CMD_ERR: st_ble_gap_cmd_err_evt_t */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_cmd_err_evt_t
+ *  @brief  HCI Command error.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   The opcode of HCI Command which caused the error.
+     */
+    uint16_t op_code;
+
+    /**
+     *  @brief   Module ID which caused the error.
+     */
+    uint32_t module_id;
+} st_ble_gap_cmd_err_evt_t;
+
+/*  Event Code : BLE_GAP_EVENT_ADV_REPT_IND: st_ble_gap_adv_rept_evt_t */
+/* ADV report related Event defines */
+/* Legacy ADV Report related structure */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_adv_rept_t
+ *  @brief  Advertising Report.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The number of Advertising Reports received.
+     */
+    uint8_t num;
+
+    /**
+     *  @brief Type of Advertising Packet.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
valuerdescription
0x00Connectable and scannable undirected advertising(ADV_IND).
0x01Connectable directed advertising(ADV_DIRECT_IND).
0x02Scannable undirected advertising(ADV_SCAN_IND).
0x03Non-connectable undirected advertising(ADV_NONCONN_IND).
0x04Scan response(SCAN_RSP).

+     */
+    uint8_t adv_type;
+
+    /**
+     *  @brief Address type of the advertiser.
+     *  @details
+     *               |   value   |   description                                                   |
+     *               |:--------- |:--------------------------------------------------------------- |
+     *               | 0x00      | Public Address.                                                 |
+     *               | 0x01      | Random Address.                                                 |
+     *               | 0x02      | Public Identity Address which could be resolved in Controller.  |
+     *               | 0x03      | Random Identity Address which could be resolved in Controller.  |
+     */
+    uint8_t addr_type;
+
+    /**
+     *  @brief Address of the advertiser.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t * p_addr;
+
+    /**
+     *  @brief   Length of Advertising data(in bytes).
+     *  @details Valid range is 0 - 31.
+     */
+    uint8_t len;
+
+    /**
+     *  @brief  RSSI(in dBm).
+     *  @details Valid range is -127 <= tx_pwr <= 20 and 127.\n
+     *           If the tx_pwr is 127, it means that RSSI could not be retrieved.
+     */
+    int8_t rssi;
+
+    /**
+     *  @brief   Advertising data/Scan Response Data.
+     */
+    uint8_t * p_data;
+} st_ble_gap_adv_rept_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_ext_adv_rept_t
+ *  @brief  Extended Advertising Report.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The number of Advertising Reports received.
+     */
+    uint8_t num;
+
+    /**
+     *  @brief Type of Advertising Packet.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *  
Bit Numberdescription
0Connectable advertising.
1Scannable advertising.
2Directed advertising.
3Scan response.
4Legacy advertising PDU.
5-6The status of Advertising Data/Scan Response Data.

+     *          Data Status:

+     *          00b = Complete 

+     *          01b = Incomplete, more data come 

+     *          10b = Incomplete, data truncated, no more to come 

+     *          
All other bitsReserved for future use

+     */
+    uint16_t adv_type;
+
+    /**
+     *  @brief Address type of the advertiser.
+     *  @details
+     *               |   value   |   description                                                   |
+     *               |:--------- |:--------------------------------------------------------------- |
+     *               | 0x00      | Public Address.                                                 |
+     *               | 0x01      | Random Address.                                                 |
+     *               | 0x02      | Public Identity Address which could be resolved in Controller.  |
+     *               | 0x03      | Random Identity Address which could be resolved in Controller.  |
+     *               | 0xFF      | Anonymous advertisement.                                        |
+     */
+    uint8_t addr_type;
+
+    /**
+     *  @brief Address of the advertiser.
+     *  @note  The BD address setting format is little endian.
+     */
+    uint8_t * p_addr;
+
+    /**
+     *  @brief The primary PHY configuration of the advertiser.
+     *  @details
+     *   The primary PHY configuration of the advertiser.
+     *               |   value   |   description            |
+     *               |:--------- |:------------------------ |
+     *               | 0x01      | 1M PHY                   |
+     *               | 0x03      | Coded PHY                |
+     */
+    uint8_t adv_phy;
+
+    /**
+     *  @brief The secondary PHY configuration of the advertiser.
+     *  @details
+     *               |   value   |   description                                                    |
+     *               |:--------- |:---------------------------------------------------------------- |
+     *               | 0x00      | Nothing has been received with Secondary Advertising Channel.    |
+     *               | 0x01      | The Secondary Advertising PHY configuration was 1M PHY.          |
+     *               | 0x02      | The Secondary Advertising PHY configuration was 2M PHY.          |
+     *               | 0x03      | The Secondary Advertising PHY configuration was Coded PHY.       |
+     */
+    uint8_t sec_adv_phy;
+
+    /**
+     *  @brief Advertising SID included in the received Advertising Report.
+     *  @details Valid range is 0 <= adv_sid <= 0x0F and 0xFF.\n
+     *           If the adv_sid is 0xFF, there is no field which includes SID.
+     */
+    uint8_t adv_sid;
+
+    /**
+     *  @brief  TX power(in dBm).
+     *  @details Valid range is -127 <= tx_pwr <= 20 and 127.\n
+     *           If the tx_pwr is 127, it means that Tx power could not be retrieved.
+     */
+    int8_t tx_pwr;
+
+    /**
+     *  @brief  RSSI(in dBm).
+     *  @details Valid range is -127 <= tx_pwr <= 20 and 127.\n
+     *           If the tx_pwr is 127, it means that RSSI could not be retrieved.
+     */
+    int8_t rssi;
+
+    /**
+     *  @brief  Periodic Advertising interval.
+     *  @details If the perd_adv_intv is 0x0000, it means that this advertising is not periodic advertising.\n
+     *           If the perd_adv_intv is 0x0006 - 0xFFFF,
+     *           it means that this field is the Periodic Advertising interval.\n
+     *           Periodic Advertising interval = per_adv_intr * 1.25ms.
+     */
+    uint16_t perd_adv_intv;
+
+    /**
+     *  @brief The address type of Direct Advertising PDU.
+     *  @details
+     *               |   value   |   description                                                         |
+     *               |:--------- |:--------------------------------------------------------------------- |
+     *               | 0x00      | Public Address.                                                       |
+     *               | 0x01      | Random Address.                                                       |
+     *               | 0x02      | Public Identity Address which could be resolved in Controller.        |
+     *               | 0x03      | Random Identity Address which could be resolved in Controller.        |
+     *               | 0xFE      | Resolvable Privacy Address which could not be resolved in Controller. |
+     */
+    uint8_t dir_addr_type;
+
+    /**
+     *  @brief   Address of Direct Advertising PDU.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t * p_dir_addr;
+
+    /**
+     *  @brief   Length of Advertising data(in bytes).
+     *  @details Valid range is 0 - 229.
+     */
+    uint8_t len;
+
+    /**
+     *  @brief   Advertising data/Scan Response Data.
+     */
+    uint8_t * p_data;
+} st_ble_gap_ext_adv_rept_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_perd_adv_rept_t
+ *  @brief  Periodic Advertising Report.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Sync handle.
+     *  @details Valid range is 0x0000 - 0x0EFF.
+     */
+    uint16_t sync_hdl;
+
+    /**
+     *  @brief  TX power(in dBm).
+     *  @details Valid range is -127 <= tx_pwr <= 20 and 127.\n
+     *           If tx_pwr is 127, it means that Tx power could not be retrieved.
+     */
+    int8_t tx_pwr;
+
+    /**
+     *  @brief  RSSI(in dBm).
+     *  @details Valid range is -127 <= rssi <= 20 and 127.\n
+     *           If rssi is 127, it means that RSSI could not be retrieved.
+     */
+    int8_t rssi;
+
+    /**
+     *  @brief  Reserved for future use.
+     */
+    uint8_t rfu;
+
+    /**
+     *  @brief  Reserved for future use.
+     *  @details
+     *               |   value   |   description                                           |
+     *               |:--------- |:------------------------------------------------------- |
+     *               | 0x00      | Data Complete.                                          |
+     *               | 0x01      | Data incomplete, more data to come.                     |
+     *               | 0x02      | Data incomplete, data truncated, no more to come.       |
+     */
+    uint8_t data_status;
+
+    /**
+     *  @brief  Length of Periodic Advertising data(in bytes).
+     *  @details Valid range is 0 - 247.
+     */
+    uint8_t len;
+
+    /**
+     *  @brief  Periodic Advertising data.
+     */
+    uint8_t * p_data;
+} st_ble_gap_perd_adv_rept_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_adv_rept_evt_t
+ *  @brief  Advertising report.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Data type.
+     *  @details
+     *               |        value         |   description                   |
+     *               |:-------------------- |:---------------------------------- |
+     *               | 0x00                 | Advertising Report.                |
+     *               | 0x01                 |  Extended Advertising Report.   |
+     *               | 0x02                 | Periodic Advertising Report.    |
+     *
+     *   If the BLE Protocol Stack library type is "all features",
+     *   the adv_rpt_type field in a Legacy Advertising Report event is 0x01.
+     */
+    uint8_t adv_rpt_type;
+
+    /**
+     *  @brief Advertising Report.
+     */
+    union
+    {
+        /**
+         *  @brief Advertising Report.
+         */
+        st_ble_gap_adv_rept_t * p_adv_rpt;
+
+        /**
+         *  @brief Extended Advertising Report.
+         */
+        st_ble_gap_ext_adv_rept_t * p_ext_adv_rpt;
+
+        /**
+         *  @brief Periodic Advertising Report.
+         */
+        st_ble_gap_perd_adv_rept_t * p_per_adv_rpt;
+    } param;
+} st_ble_gap_adv_rept_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_ADV_PARAM_SET_COMP       : st_ble_gap_adv_set_evt_t */
+/* Event Code : BLE_GAP_EVENT_ADV_ON                   : st_ble_gap_adv_set_evt_t  */
+/* Event Code : BLE_GAP_EVENT_PERD_ADV_ON              : st_ble_gap_adv_set_evt_t */
+/* Event Code : BLE_GAP_EVENT_PERD_ADV_OFF             : st_ble_gap_adv_set_evt_t */
+/* Event Code : BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP  : st_ble_gap_adv_set_evt_t */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_adv_set_evt_t
+ *  @brief  Advertising handle.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle specifying the advertising set configured advertising parameters.
+     */
+    uint8_t adv_hdl;
+} st_ble_gap_adv_set_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_ADV_OFF              : st_ble_gap_adv_off_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_adv_off_evt_t
+ *  @brief  Information about the advertising set which stops advertising.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle identifying the advertising set which has stopped advertising.
+     *  @details Valid range is 0x00 - 0x03.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief  The reason for stopping advertising.
+     *  @details
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
valuedescription
0x01
+     *                  Advertising has been stopped by R_BLE_GAP_StopAdv().
+     *              
0x02
+     *                  Because the duration specified by R_BLE_GAP_StartAdv() was expired,
+     *                  advertising has terminated.
+     *              
0x03
+     *                  Because the max_extd_adv_evts parameter specified by R_BLE_GAP_StartAdv() was reached,
+     *                  advertising has terminated.
+     *              
0x04
+     *                   Because the connection was established with the remote device, advertising has terminated.
+     *              

+     */
+    uint8_t reason;
+
+    /**
+     *  @brief Connection handle.
+     *  @details  If the reason field is 0x04, this field indicates connection handle identifying
+     *            the remote device connected with local device.
+     *            If other reasons, ignore this field.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief  The number of the advertising event that has been received until advertising has terminated.
+     *  @details  If max_extd_adv_evts by R_BLE_GAP_StartAdv() is not 0, this parameter is valid.
+     */
+    uint8_t num_comp_ext_adv_evts;
+} st_ble_gap_adv_off_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_ADV_DATA_UPD_COMP : st_ble_gap_adv_data_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_adv_data_evt_t
+ *  @brief  This structure notifies that advertising data has been set to Controller by R_BLE_GAP_SetAdvSresData().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Advertising handle identifying the advertising set to
+     *         which advertising data/scan response data/periodic advertising data is set.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief Type of the data set to the advertising set.
+     *  @details
+     *    | value                                |   description               |
+     *    |:------------------------------------ |:--------------------------- |
+     *    | BLE_GAP_ADV_DATA_MODE(0x00)          |  Advertising data           |
+     *    | BLE_GAP_SCAN_RSP_DATA_MODE(0x01)     |  Scan response data         |
+     *    | BLE_GAP_PERD_ADV_DATA_MODE(0x02)     |  Periodic advertising data  |
+     */
+    uint8_t data_type;
+} st_ble_gap_adv_data_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_ADV_SET_REMOVE_COMP : st_ble_gap_rem_adv_set_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rem_adv_set_evt_t
+ *  @brief  This structure notifies that an advertising set has been removed.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  This field indicates that the advertising set has been removed or cleared.
+     *  @details
+     *    | value    |   description                           |
+     *    |:-------- |:--------------------------------------- |
+     *    | 0x01     |  The advertising set has been removed.  |
+     *    | 0x02     |  The advertising set has been cleared.  |
+     */
+    uint8_t remove_op;
+
+    /**
+     *  @brief Advertising handle identifying the advertising set which has been removed.
+     *  @details  If the advertising set has been cleared, this field is ignored.
+     */
+    uint8_t adv_hdl;
+} st_ble_gap_rem_adv_set_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_SCAN_ON  : none  */
+/* Event Code : BLE_GAP_EVENT_SCAN_OFF : none  */
+
+/* Event Code : BLE_GAP_EVENT_CONN_IND : st_ble_gap_conn_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_conn_evt_t
+ *  @brief  This structure notifies that a link has been established.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Connection handle identifying the created link.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief  The role of the link.
+     *  @details
+     *    | value    |   description  |
+     *    |:-------- |:-------------- |
+     *    | 0x00     |  Master        |
+     *    | 0x01     |  Slave         |
+     */
+    uint8_t role;
+
+    /**
+     *  @brief  Address type of the remote device.
+     *  @details
+     *  
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *      
+     *      
+     *          
+     *          
+     *  
valuedescription
0x00Public Address
0x01Random Address
0x02Public Identity Address.

+     *              It indicates that the Controller could resolve the resolvable private address of the remote device.
+     *          
0x03Random Identity Address.

+     *              It indicates that the Controller could resolve the resolvable private address of the remote device.
+     *          		
+     *      

+     */
+    uint8_t remote_addr_type;
+
+    /**
+     *  @brief Address of the remote device.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t remote_addr[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief Resolvable private address that local device used in connection procedure.
+     *  @details
+     *  The local device address used in creating the link when the address type was set to
+     *  BLE_GAP_ADDR_RPA_ID_PUBLIC or BLE_GAP_ADDR_RPA_ID_RANDOM by R_BLE_GAP_SetAdvParam() or
+     *  R_BLE_GAP_CreateConn().
+     *  If the address type was set to other than BLE_GAP_ADDR_RPA_ID_PUBLIC and
+     *  BLE_GAP_ADDR_RPA_ID_RANDOM, this field is set to all-zero.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t local_rpa[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief Resolvable private address that the remote device used in connection procedure.
+     *  @details
+     *  This field indicates the remote resolvable private address when remote_addr_type is 0x02 or 0x03.
+     *  If remote_addr_type is other than 0x02 and 0x03, this field is set to all-zero.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t remote_rpa[BLE_BD_ADDR_LEN];
+
+    /**
+     *  @brief  Connection interval.
+     *  @details
+     *  Valid range is 0x0006 - 0x0C80.\n
+     *  Time(ms) = conn_intv * 1.25.
+     */
+    uint16_t conn_intv;
+
+    /**
+     *  @brief  Slave latency.
+     *  @details
+     *  Valid range is 0x0000 - 0x01F3.
+     */
+    uint16_t conn_latency;
+
+    /**
+     *  @brief  Supervision timeout.
+     *  @details
+     *  Valid range is 0x000A - 0x0C80.Time(ms) = sup_to * 10.
+     */
+    uint16_t sup_to;
+
+    /**
+     *  @brief  Master_Clock_Accuracy.
+     *  @details
+     *    |  value   |   description               |
+     *    |:---------|:--------------------------- |
+     *    | 0x00     | 500ppm                      |
+     *    | 0x01     | 250ppm                      |
+     *    | 0x02     | 150ppm                      |
+     *    | 0x03     | 100ppm                      |
+     *    | 0x04     | 75ppm                       |
+     *    | 0x05     | 50ppm                       |
+     *    | 0x06     | 30ppm                       |
+     *    | 0x07     | 20ppm                       |
+     */
+    uint8_t clk_acc;
+} st_ble_gap_conn_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_DISCONN_IND : st_ble_gap_disconn_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_disconn_evt_t
+ *  @brief  This structure notifies that a link has been disconnected.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Connection handle identifying the link disconnected.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief   The reason for disconnection.
+     *  @details
+     *  Refer Core Specification Vol.2 Part D ,"2 Error Code Descriptions".
+     */
+    uint8_t reason;
+} st_ble_gap_disconn_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_CONN_CANCEL_COMP : none  */
+
+/* Event Code : BLE_GAP_EVENT_WHITE_LIST_CONF_COMP : st_ble_gap_white_list_conf_evt_t  */
+
+/* Event Code : BLE_GAP_EVENT_RAND_ADDR_SET_COMP : none  */
+
+/* Event Code : BLE_GAP_EVENT_CH_MAP_RD_COMP : st_ble_gap_rd_ch_map_evt_t  */
+/* Read Channel MAP */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rd_ch_map_evt_t
+ *  @brief  This structure notifies that Channel Map has been retrieved by R_BLE_GAP_ReadChMap().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Connection handle identifying the link whose Channel Map was retrieved.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief   Channel Map.
+     */
+    uint8_t ch_map[BLE_GAP_CH_MAP_SIZE];
+} st_ble_gap_rd_ch_map_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_CH_MAP_SET_COMP : none  */
+
+/* Event Code : BLE_GAP_EVENT_RSSI_RD_COMP  : st_ble_gap_rd_rssi_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rd_rssi_evt_t
+ *  @brief  This structure notifies that RSSI has been retrieved by R_BLE_GAP_ReadRssi().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Connection handle identifying the link whose RSSI was retrieved.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief    RSSI(in dBm).
+     *  @details
+     *  Valid range is -127 < rssi < 20 and 127.\n
+     *  If this field is 127, it indicates that RSSI could not be retrieved.
+     */
+    int8_t rssi;
+} st_ble_gap_rd_rssi_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_GET_REM_DEV_INFO  : st_ble_gap_dev_info_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_dev_info_evt_t
+ *  @brief This structure notifies that information about remote device has been retrieved by R_BLE_GAP_GetRemDevInfo().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device whose information has been retrieved.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief  Information about the remote device. This field is a bitwise OR of the following values.
+     *  @details
+     *    |  Bit Number        |   description                   |
+     *    |:-------------------|:------------------------------- |
+     *    | bit0               | Address                         |
+     *    | bit1               | Version, company_id, subversion |
+     *    | bit2               | Feature                         |
+     *    | All other bits     | Reserved for future use         |
+     */
+    uint8_t get_status;
+
+    /**
+     *  @brief      Address of the remote device.
+     */
+    st_ble_dev_addr_t addr;
+
+    /**
+     *  @brief    The version of Link Layer of the remote device.
+     *  @details
+     *  Refer to Bluetooth SIG Assigned Number
+     *  (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number.
+     */
+    uint8_t version;
+
+    /**
+     *  @brief    The manufacturer ID of the remote device.
+     *  @details
+     *  Refer to Bluetooth SIG Assigned Number
+     *  (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number.
+     */
+    uint16_t company_id;
+
+    /**
+     *  @brief       The subversion of Link Layer.
+     */
+    uint16_t subversion;
+
+    /**
+     *  @brief    LE feature supported in the remote device.
+     *  @details
+     *  Refer to Core Spec Vol 6, Part B 4.6 FEATURE SUPPORT.
+     */
+    uint8_t features[BLE_GAP_REM_FEATURE_SIZE];
+} st_ble_gap_dev_info_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_COMP  : st_ble_gap_conn_upd_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_conn_upd_evt_t
+ *  @brief  This structure notifies that connection parameters has been updated.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the connection whose parameters has been updated.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief    Updated Connection Interval.
+     *  @details
+     *  Valid range is 0x0006 - 0x0C80.\n
+     *  Time(ms) = conn_intv * 1.25.
+     */
+    uint16_t conn_intv;
+
+    /**
+     *  @brief    Updated slave latency.
+     *  @details
+     *  Valid range is 0x0000 - 0x01F3.
+     */
+    uint16_t conn_latency;
+
+    /**
+     *  @brief    Updated supervision timeout.
+     *  @details
+     *  Valid range is 0x000A - 0x0C80.\n
+     *  Time(ms) = sup_to * 10.
+     */
+    uint16_t sup_to;
+} st_ble_gap_conn_upd_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_REQ   : st_ble_gap_conn_upd_req_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_conn_upd_req_evt_t
+ *  @brief  This structure notifies that a request for connection parameters update has been received.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief      Connection handle identifying the link that was requested to update connection parameters.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Minimum connection interval.
+     *  @details
+     *  Valid range is 0x0006 - 0x0C80.\n
+     *  Time(ms) = conn_intv_min * 1.25.
+     */
+    uint16_t conn_intv_min;
+
+    /**
+     *  @brief     Maximum connection interval.
+     *  @details
+     *  Valid range is 0x0006 - 0x0C80.\n
+     *  Time(ms) = conn_intv_max * 1.25.
+     */
+    uint16_t conn_intv_max;
+
+    /**
+     *  @brief     Slave latency.
+     *  @details
+     *  Valid range is 0x0000 - 0x01F3.
+     */
+    uint16_t conn_latency;
+
+    /**
+     *  @brief     Supervision timeout.
+     *  @details
+     *  Valid range is 0x000A - 0x0C80.\n
+     *  Time(ms) = sup_to * 10
+     */
+    uint16_t sup_to;
+} st_ble_gap_conn_upd_req_evt_t;
+
+/* Event Code : RBLE_GAP_EVENT_CONN_PARAM_UPD_RSP        : st_ble_gap_conn_hdl_evt_t  */
+/* Event Code : BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED   : st_ble_gap_conn_hdl_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_conn_hdl_evt_t
+ *  @brief  This structure notifies that a GAP Event that includes only connection handle has occurred.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle.
+     */
+    uint16_t conn_hdl;
+} st_ble_gap_conn_hdl_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_DATA_LEN_CHG : st_ble_gap_data_len_chg_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_data_len_chg_evt_t
+ *  @brief  This structure notifies that the packet data length has been updated.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the link that updated Data Length.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Updated transmission packet size(in bytes).
+     *  @details
+     *  Valid range is 0x001B - 0x00FB.
+     */
+    uint16_t tx_octets;
+
+    /**
+     *  @brief     Updated transmission time(us).
+     *  @details
+     *  Valid range is 0x0148 - 0x4290.
+     */
+    uint16_t tx_time;
+
+    /**
+     *  @brief     Updated receive packet size(in bytes).
+     *  @details
+     *  Valid range is 0x001B - 0x00FB.
+     */
+    uint16_t rx_octets;
+
+    /**
+     *  @brief     Updated receive time(us).
+     *  @details
+     *  Valid range is 0x0148 - 0x4290.
+     */
+    uint16_t rx_time;
+} st_ble_gap_data_len_chg_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_RSLV_LIST_CONF_COMP : st_ble_gap_rslv_list_conf_evt_t  */
+
+/* Event Code : BLE_GAP_EVENT_RPA_EN_COMP : none  */
+/* Event Code : BLE_GAP_EVENT_SET_RPA_TO_COMP       : none  */
+/* Event Code : BLE_GAP_EVENT_RD_RPA_COMP           : st_ble_gap_rd_rpa_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rd_rpa_evt_t
+ *  @brief  This structure notifies that the local resolvable private address has been retrieved by R_BLE_GAP_ReadRpa().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The resolvable private address of local device.
+     */
+    st_ble_dev_addr_t addr;
+} st_ble_gap_rd_rpa_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PHY_UPD      : st_ble_gap_phy_upd_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_phy_upd_evt_t
+ *  @brief  This structure notifies that PHY for a connection has been updated.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the link that has been updated.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Transmitter PHY.
+     *  @details
+     *    |  value     |   description                                                |
+     *    |:-----------|:------------------------------------------------------------ |
+     *    | 0x01       | The transmitter PHY has been updated to 1M PHY.              |
+     *    | 0x02       | The transmitter PHY has been updated to 2M PHY.              |
+     *    | 0x03       | The transmitter PHY has been updated to Coded PHY.           |
+     */
+    uint8_t tx_phy;
+
+    /**
+     *  @brief     Receiver PHY.
+     *  @details
+     *    |  value     |   description                                                |
+     *    |:-----------|:------------------------------------------------------------ |
+     *    | 0x01       | The receiver PHY has been updated to 1M PHY.              |
+     *    | 0x02       | The receiver PHY has been updated to 2M PHY.              |
+     *    | 0x03       | The receiver PHY has been updated to Coded PHY.           |
+     */
+    uint8_t rx_phy;
+} st_ble_gap_phy_upd_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PHY_RD_COMP  : st_ble_gap_phy_rd_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_phy_rd_evt_t
+ *  @brief  This structure notifies that the PHY settings has been retrieved by R_BLE_GAP_ReadPhy().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the link that has been retrieved the PHY settings.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Transmitter PHY.
+     *  @details
+     *    |  value     |   description                                                |
+     *    |:-----------|:------------------------------------------------------------ |
+     *    | 0x01       | The transmitter PHY has been updated to 1M PHY.              |
+     *    | 0x02       | The transmitter PHY has been updated to 2M PHY.              |
+     *    | 0x03       | The transmitter PHY has been updated to Coded PHY.           |
+     */
+    uint8_t tx_phy;
+
+    /**
+     *  @brief     Receiver PHY.
+     *  @details
+     *    |  value     |   description                                                |
+     *    |:-----------|:------------------------------------------------------------ |
+     *    | 0x01       | The receiver PHY has been updated to 1M PHY.              |
+     *    | 0x02       | The receiver PHY has been updated to 2M PHY.              |
+     *    | 0x03       | The receiver PHY has been updated to Coded PHY.           |
+     */
+    uint8_t rx_phy;
+} st_ble_gap_phy_rd_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PHY_SET_COMP   : st_ble_gap_conn_hdl_evt_t  */
+/* Event Code : BLE_GAP_EVENT_SCAN_REQ_RECV  : st_ble_gap_scan_req_recv_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_scan_req_recv_evt_t
+ *  @brief  This structure notifies that a Scan Request packet has been received from a Scanner.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Advertising handle identifying the advertising set that has received the Scan Request.
+     */
+    uint8_t adv_hdl;
+
+    /**
+     *  @brief      Address type of the Scanner.
+     *  @details
+     *    |  value     |   description                                                  |
+     *    |:-----------|:-------------------------------------------------------------- |
+     *    | 0x00       | Public Address.                                                |
+     *    | 0x01       | Random Address.                                                |
+     *    | 0x02       | Public Identity Address which could be resolved in Controller. |
+     *    | 0x03       | Random Identity Address which could be resolved in Controller. |
+     */
+    uint8_t scanner_addr_type;
+
+    /**
+     *  @brief     Address of the Scanner.
+     *  @note      The BD address setting format is little endian.
+     */
+    uint8_t scanner_addr[BLE_BD_ADDR_LEN];
+} st_ble_gap_scan_req_recv_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_SYNC_EST  : st_ble_gap_sync_est_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_sync_est_evt_t
+ *  @brief  This structure notifies that a Periodic sync has been established.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Sync handle identifying the Periodic Sync that has been established.
+     */
+    uint16_t sync_hdl;
+
+    /**
+     *  @brief     Advertising SID identifying the advertising set that has established the Periodic Sync.
+     */
+    uint8_t adv_sid;
+
+    /**
+     *  @brief      Address type of the advertiser.
+     *  @details
+     *    |  value     |   description                                                  |
+     *    |:-----------|:-------------------------------------------------------------- |
+     *    | 0x00       | Public Address.                                                |
+     *    | 0x01       | Random Address.                                                |
+     *    | 0x02       | Public Identity Address which could be resolved in Controller. |
+     *    | 0x03       | Random Identity Address which could be resolved in Controller. |
+     */
+    uint8_t adv_addr_type;
+
+    /**
+     *  @brief     Address of the advertiser.
+     *  @note   The BD address setting format is little endian.
+     */
+    uint8_t * p_adv_addr;
+
+    /**
+     *  @brief      Advertising PHY.
+     *  @details
+     *    |  value     |   description                |
+     *    |:-----------|:---------------------------- |
+     *    | 0x01       | Advertiser PHY is 1M PHY.    |
+     *    | 0x02       | Advertiser PHY is 2M PHY.    |
+     *    | 0x03       | Advertiser PHY is Coded PHY. |
+     */
+    uint8_t adv_phy;
+
+    /**
+     *  @brief     Periodic Advertising Interval.
+     *  @details
+     *  Valid range is 0x0006 - 0xFFFF.\n
+     *  Time(ms) = perd_adv_intv * 1.25.
+     */
+    uint16_t perd_adv_intv;
+
+    /**
+     *  @brief  Advertiser Clock Accuracy.
+     *  @details
+     *    |  value   |   description               |
+     *    |:---------|:--------------------------- |
+     *    | 0x00     | 500ppm                      |
+     *    | 0x01     | 250ppm                      |
+     *    | 0x02     | 150ppm                      |
+     *    | 0x03     | 100ppm                      |
+     *    | 0x04     | 75ppm                       |
+     *    | 0x05     | 50ppm                       |
+     *    | 0x06     | 30ppm                       |
+     *    | 0x07     | 20ppm                       |
+     */
+    uint8_t adv_clk_acc;
+} st_ble_gap_sync_est_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_SYNC_TERM    : st_ble_gap_sync_hdl_evt_t  */
+/* Event Code : BLE_GAP_EVENT_SYNC_LOST         : st_ble_gap_sync_hdl_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_sync_hdl_evt_t
+ *  @brief  This structure notifies that a GAP Event that includes only sync handle has occurred.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Sync handle.
+     */
+    uint16_t sync_hdl;
+} st_ble_gap_sync_hdl_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP   : none  */
+/* Event Code : BLE_GAP_EVENT_PERD_LIST_CONF_COMP       : st_ble_gap_perd_list_conf_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_white_list_conf_evt_t
+ *  @brief  This structure notifies that White List has been configured.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The operation for White List.
+     *  @details
+     *    |  value   |   description                            |
+     *    |:---------|:---------------------------------------- |
+     *    | 0x01     | A device was added to White List.        |
+     *    | 0x02     | A device was deleted from White List.    |
+     *    | 0x03     | White List was cleared.                  |
+     */
+    uint8_t op_code;
+
+    /**
+     *  @brief     The number or devices which have been added to or deleted from White List.
+     */
+    uint8_t num;
+} st_ble_gap_white_list_conf_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_rslv_list_conf_evt_t
+ *  @brief  This structure notifies that Resolving List has been configured.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The operation for Resolving List.
+     *  @details
+     *    |  value   |   description                                |
+     *    |:---------|:-------------------------------------------- |
+     *    | 0x01     | A device was added to Resolving List.        |
+     *    | 0x02     | A device was deleted from Resolving List.    |
+     *    | 0x03     | Resolving List was cleared.                  |
+     */
+    uint8_t op_code;
+
+    /**
+     *  @brief     The number or devices which have been added to or deleted from Resolving List.
+     */
+    uint8_t num;
+} st_ble_gap_rslv_list_conf_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_perd_list_conf_evt_t
+ *  @brief  This structure notifies that Periodic Advertiser List has been configured.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The operation for Periodic Advertiser List.
+     *  @details
+     *    |  value   |   description                                          |
+     *    |:---------|:------------------------------------------------------ |
+     *    | 0x01     | A device was added to Periodic Advertiser List.        |
+     *    | 0x02     | A device was deleted from Periodic Advertiser List.    |
+     *    | 0x03     | Periodic Advertiser List was cleared.                  |
+     */
+    uint8_t op_code;
+
+    /**
+     *  @brief     The number or devices which have been added to or deleted from Periodic Advertiser List.
+     */
+    uint8_t num;
+} st_ble_gap_perd_list_conf_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PRIV_MODE_SET_COMP   : st_ble_gap_set_priv_mode_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_set_priv_mode_evt_t
+ *  @brief  This structure notifies that Privacy Mode has been configured.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The number or devices which have been set privacy mode.
+     */
+    uint8_t num;
+} st_ble_gap_set_priv_mode_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PAIRING_REQ   : st_ble_gap_pairing_req_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_pairing_req_evt_t
+ *  @brief  This structure notifies that a pairing request from a remote device has been received.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that sent the pairing request.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     The address of the remote device.
+     */
+    st_ble_dev_addr_t bd_addr;
+
+    /**
+     *  @brief     The Pairing parameters of the remote device.
+     */
+    st_ble_gap_auth_info_t auth_info;
+} st_ble_gap_pairing_req_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PASSKEY_ENTRY_REQ   : st_ble_gap_conn_hdl_evt_t  */
+
+/* Event Code : BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ   : st_ble_gap_passkey_display_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_passkey_display_evt_t
+ *  @brief  This structure notifies that a request for Passkey display in pairing has been received.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that requested Passkey display.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Passkey.
+     *  @details   This field is a 6 digit decimal number(000000-999999).
+     */
+    uint32_t passkey;
+} st_ble_gap_passkey_display_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_NUM_COMP_REQ   : st_ble_gap_num_comp_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_num_comp_evt_t
+ *  @brief  This structure notifies that a request for Numeric Comparison in pairing has been received.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that requested Numeric Comparison.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     The number to be confirmed in Numeric Comparison.
+     *  @details   This field is a 6 digit decimal number(000000-999999).
+     */
+    uint32_t numeric;
+} st_ble_gap_num_comp_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_KEY_PRESS_NTF     : st_ble_gap_key_press_ntf_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_key_press_ntf_evt_t
+ *  @brief  This structure notifies that the remote device has input a key in Passkey Entry
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that input a key.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Type of the key that the remote device input.
+     *  @details
+     *    |  value   |   description                 |
+     *    |:---------|:----------------------------- |
+     *    | 0x00     | Passkey entry started.        |
+     *    | 0x01     | Passkey digit entered.        |
+     *    | 0x02     | Passkey digit erased.         |
+     *    | 0x03     | Passkey cleared.              |
+     *    | 0x04     | Passkey entry completed.      |
+     */
+    uint8_t key_type;
+} st_ble_gap_key_press_ntf_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PAIRING_COMP   : st_ble_gap_pairing_info_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_pairing_info_evt_t
+ *  @brief  This structure notifies that the pairing has completed.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that the pairing has been done with.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Address of the remote device.
+     */
+    st_ble_dev_addr_t bd_addr;
+
+    /**
+     *  @brief     Key information exchanged in pairing.
+     *  @details   If local device supports bonding, store the information in non-volatile memory
+     *             in order to set it to host stack after power re-supply.
+     */
+    st_ble_gap_auth_info_t auth_info;
+} st_ble_gap_pairing_info_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_ENC_CHG   : st_ble_gap_enc_chg_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_enc_chg_evt_t
+ *  @brief  This structure notifies that the encryption status of a link has been changed.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the link that has been changed.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Encryption Status.
+     *  @details
+     *    |  value   |   description                                            |
+     *    |:---------|:-------------------------------------------------------- |
+     *    | 0x00     | Encryption OFF.                                          |
+     *    | 0x01     | Encryption ON.                                           |
+     *    | 0x03     | Encryption updated by Encryption Key Refresh Completed.  |
+     */
+    uint8_t enc_status;
+} st_ble_gap_enc_chg_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_PEER_KEY_INFO   : st_ble_gap_peer_key_info_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_peer_key_info_evt_t
+ *  @brief  This structure notifies that the remote device has distributed the keys.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device that has distributed the keys.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Address of the remote device.
+     */
+    st_ble_dev_addr_t bd_addr;
+
+    /**
+     *  @brief     Distributed keys.
+     *  @details
+     *  If local device supports bonding, store the keys in non-volatile memory and
+     *  at power re-supply set to the host stack by R_BLE_GAP_SetBondInfo().
+     */
+    st_ble_gap_key_ex_param_t key_ex_param;
+} st_ble_gap_peer_key_info_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_EX_KEY_REQ   : st_ble_gap_conn_hdl_evt_t  */
+
+/* Event Code : BLE_GAP_EVENT_LTK_REQ      : st_ble_gap_ltk_req_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_ltk_req_evt_t
+ *  @brief  This structure notifies that a LTK request from a remote device has been received.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device which requests for the LTK.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     Ediv.
+     */
+    uint16_t ediv;
+
+    /**
+     *  @brief     Rand.
+     */
+    uint8_t * p_peer_rand;
+} st_ble_gap_ltk_req_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_LTK_RSP_COMP      : st_ble_gap_ltk_req_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_ltk_rsp_evt_t
+ *  @brief  This structure notifies that local device has replied to the LTK request from the remote device.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Connection handle identifying the remote device to be sent the response to the LTK request.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief     The response to the LTK request.
+     *  @details
+     *    |  value   |   description                                                           |
+     *    |:---------|:----------------------------------------------------------------------- |
+     *    | 0x00     | Local device replied with the stored LTK.                               |
+     *    | 0x01     | Local device rejected the LTK request, because the LTK was not found.   |
+     */
+    uint8_t response;
+} st_ble_gap_ltk_rsp_evt_t;
+
+/* Event Code : BLE_GAP_EVENT_SC_OOB_CREATE_COMP      : st_ble_gap_sc_oob_data_evt_t  */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_sc_oob_data_evt_t
+ *  @brief  This structure notifies that OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Confirmation value(16 bytes) of OOB Data.
+     */
+    uint8_t * p_sc_oob_conf;
+
+    /**
+     *  @brief Rand(16bytes) of OOB Data.
+     */
+    uint8_t * p_sc_oob_rand;
+} st_ble_gap_sc_oob_data_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gap_bond_info_t
+ *  @brief  Bonding information used in R_BLE_GAP_SetBondInfo().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Address of the device which exchanged the keys.
+     */
+    st_ble_dev_addr_t * p_addr;
+
+    /**
+     *  @brief Information about the keys.
+     */
+    st_ble_gap_auth_info_t * p_auth_info;
+
+    /**
+     *  @brief Keys distributed from the remote device in paring.
+     */
+    st_ble_gap_key_ex_param_t * p_keys;
+} st_ble_gap_bond_info_t;
+
+/*@}*/
+
+/* ================================================= GAP Event Code ================================================= */
+
+/** @addtogroup GAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @enum e_ble_gap_evt_t
+ * @brief  GAP Event Identifier
+ **********************************************************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief  Invalid GAP Event.
+     *
+     * ## Event Code: 0x1001
+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_INVALID = 0x1001,
+
+    /* Range for Generic events - 0x01 to 0x0F */
+
+    /**
+     *  @brief  Host Stack has been initialized.
+     *  @details
+     *  When initializing host stack by R_BLE_GAP_Init() has been completed,
+     *  BLE_GAP_EVENT_STACK_ON event is notified.
+     *
+     * ## Event Code: 0x1002
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_STACK_ON,
+
+    /**
+     *  @brief  Host Stack has been terminated.
+     *  @details
+     *  When terminating host stack by R_BLE_GAP_Terminate() has been completed,
+     *  BLE_GAP_EVENT_STACK_OFF event is notified.
+     *
+     * ## Event Code: 0x1003
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_STATE(0x0008)When function was called, host stack has not yet been initialized.

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_STACK_OFF,
+
+    /**
+     *  @brief  Version information of local device.
+     *  @details
+     *  When version information of local device has been retrieved by R_BLE_GAP_GetVerInfo(),
+     *  BLE_GAP_EVENT_LOC_VER_INFO event is notified.
+     *
+     * ## Event Code: 0x1004
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_loc_dev_info_evt_t
+     */
+    BLE_GAP_EVENT_LOC_VER_INFO,
+
+    /**
+     *  @brief  Hardware Error.
+     *  @details
+     *  When hardware error has been received from Controller, BLE_GAP_EVENT_HW_ERR event is notified.
+     *
+     * ## Event Code: 0x1005
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_hw_err_evt_t
+     */
+    BLE_GAP_EVENT_HW_ERR,
+
+    /**
+     *  @brief  Command Status Error.
+     *  @details
+     *  When the error of HCI Command has occurred after a R_BLE GAP API call, BLE_GAP_EVENT_CMD_ERR event is notified.
+     *
+     * ## Event Code: 0x1101
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_cmd_err_evt_t
+     */
+    BLE_GAP_EVENT_CMD_ERR = 0x1101,
+
+    /**
+     *  @brief  Advertising Report.
+     *  @details
+     *  When advertising PDUs has been received after scanning was started by R_BLE_GAP_StartScan().
+     *
+     * ## Event Code: 0x1102
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_rept_evt_t
+     */
+    BLE_GAP_EVENT_ADV_REPT_IND,
+
+    /**
+     *  @brief  Advertising parameters have been set.
+     *  @details
+     *  Advertising parameters have been configured by R_BLE_GAP_SetAdvParam().
+     *
+     * ## Event Code: 0x1103
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The advertising type that doesn't support advertising data/scan response data was
+     *                      specified to the advertising set which has already set
+     *                      advertising data/scan response data.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                      The reason for this error is as follows.

+     *                      - Advertising parameters were configured to the advertising set in advertising.

+     *                      - The sec_adv_phy field in adv_paran was not specified
+     *                        when Periodic Advertising was started.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_ADV_PARAM_SET_COMP,
+
+    /**
+     *  @brief  Advertising data has been set.
+     *  @details
+     *  This event notifies that Advertising Data/Scan Response Data/Periodic Advertising Data has been
+     *  set to the advertising set by R_BLE_GAP_SetAdvSresData().
+     *
+     * ## Event Code: 0x1104
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                      The reason for this error is as follows.

+     *                      - The advertising set that doesn't support advertising data/scan response data
+     *                        was set to the data. 

+     *                      - The advertising set that supports legacy advertising was set to
+     *                        advertising data/scan response data larger than 31 bytes. 

+     *                      - The advertising set that has advertising data/scan response data greater
+     *                        than or equal to 252 bytes was set the data in advertising. 

+     *                      - The advertising set that has periodic advertising data greater than or equal to
+     *                        253 bytes was set the data in advertising.
+     *                  
BLE_ERR_MEM_ALLOC_FAILED(0x000C)
+     *                      Length exceeded the length that the advertising set could be set.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_SetAdvSresData() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_data_evt_t
+     */
+    BLE_GAP_EVENT_ADV_DATA_UPD_COMP,
+
+    /**
+     *  @brief   Advertising has started.
+     *  @details
+     *  When advertising has been started by R_BLE_GAP_StartAdv(), this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1105
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The reason for this error is as follows.

+     *                      - The advertising data length set to the advertising set
+     *                        for connectable extended advertising was invalid.

+     *                      - If o_addr_type field in adv_param used in R_BLE_GAP_SetAdvParam() is 0x03,
+     *                        the address which is set in o_addr field of adv_param
+     *                        has not been registered in Resolving List.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)Setting of advertising data/scan response data has not been completed.
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_StartAdv() has not been created.
+     *                  
BLE_ERR_LIMIT_EXCEEDED(0x0010)When the maximum connections are established, a new connectable advertising tried starting.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_ADV_ON,
+
+    /**
+     *  @brief   Advertising has stopped.
+     *  @details
+     *  This event notifies the application layer that advertising has stopped.
+     *
+     * ## Event Code: 0x1106
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_StopAdv() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_off_evt_t
+     */
+    BLE_GAP_EVENT_ADV_OFF,
+
+    /**
+     *  @brief   Periodic advertising parameters have been set.
+     *  @details
+     *  This event notifies the application layer that Periodic Advertising Parameters
+     *  has been configured by R_BLE_GAP_SetPerdAdvParam().
+     *
+     * ## Event Code: 0x1107
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The advertising set was the setting for anonymous advertising.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                      The advertising set was configured to the parameters in periodic advertising.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_SetPerdAdvParam() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP,
+
+    /**
+     *  @brief    Periodic advertising has started.
+     *  @details
+     *  When Periodic Advertising has been started by R_BLE_GAP_StartPerdAdv(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1108
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                      The periodic advertising data set in the advertising set has not been completed.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_StartPerdAdv() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_PERD_ADV_ON,
+
+    /**
+     *  @brief    Periodic advertising has stopped.
+     *  @details
+     *  When Periodic Advertising has terminated by R_BLE_GAP_StopPerdAdv(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1109
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_StopPerdAdv() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_PERD_ADV_OFF,
+
+    /**
+     *  @brief    Advertising set has been deleted.
+     *  @details
+     *  When the advertising set has been removed by R_BLE_GAP_RemoveAdvSet(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x110A
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       When the advertising set was in advertising, R_BLE_GAP_RemoveAdvSet() was called.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The advertising set specified by R_BLE_GAP_RemoveAdvSet() has not been created.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_rem_adv_set_evt_t
+     */
+    BLE_GAP_EVENT_ADV_SET_REMOVE_COMP,
+
+    /**
+     *  @brief    Scanning has started.
+     *  @details
+     *  When scanning has started by R_BLE_GAP_StartScan(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x110B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The reason for this error is as follows:

+     *                      - Scan interval or scan window was invalid.
+     *                      - When filter_dup field in scan_enable was BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02),
+     *                        period field in scan_enable was 0.
+     *                      - duration field in scan_enable was larger than period in scan_enable.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       In scanning, R_BLE_GAP_StartScan() was called.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_SCAN_ON,
+
+    /**
+     *  @brief    Scanning has stopped.
+     *  @details
+     *  When scanning has been stopped by R_BLE_GAP_StopScan(), this event is notified to the application layer.
+     *
+     * ## Event Code: 0x110C
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_SCAN_OFF,
+
+    /**
+     *  @brief    Scanning has stopped, because duration specified by API expired.
+     *  @details
+     *  When the scan duration specified by R_BLE_GAP_StartScan() has expired,
+     *  this event notifies scanning has stopped.
+     *
+     * ## Event Code: 0x110D
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_SCAN_TO,
+
+    /**
+     *  @brief    Connection Request has been sent to Controller.
+     *  @details
+     *  This event notifies a request for a connection has been sent to Controller.
+     *
+     * ## Event Code: 0x110E
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The reason for this error is as follows:

+     *                      - Scan interval or scan windows specified by R_BLE_GAP_CreateConn() is invalid.
+     *                      - Although the own_addr_type field in p_param was set to 0x03,
+     *                        random address had not been registered in Resolving List.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       R_BLE_GAP_CreateConn() was called while creating a link
+     *                       by previous R_BLE_GAP_CreateConn() call .
+     *                  
BLE_ERR_LIMIT_EXCEEDED(0x0010)
+     *                       When the maximum connections are established, R_BLE_GAP_CreateConn() was called.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_CREATE_CONN_COMP,
+
+    /**
+     *  @brief    Link has been established.
+     *  @details
+     *  This event notifies a link has been established.
+     *
+     * ## Event Code: 0x110F
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                       The request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn().
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_evt_t
+     */
+    BLE_GAP_EVENT_CONN_IND,
+
+    /**
+     *  @brief    Link has been disconnected.
+     *  @details
+     *  This event notifies a link has been disconnected.
+     *
+     * ## Event Code: 0x1110
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_disconn_evt_t
+     */
+    BLE_GAP_EVENT_DISCONN_IND,
+
+    /**
+     *  @brief    Connection Cancel Request has been sent to Controller.
+     *  @details
+     *  This event notifies the request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn().
+     *
+     * ## Event Code: 0x1111
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       When a request for a connection has not been sent to Controller,
+     *                       R_BLE_GAP_CancelCreateConn() was called.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_CONN_CANCEL_COMP,
+
+    /**
+     *  @brief    The White List has been configured.
+     *  @details
+     *  When White List has been configured, this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1112
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_STATE(0x0008)
+     *                       The add or delete operation was called, before the previous clear operation has been completed.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       While doing advertising or scanning or creating a link with the White List,
+     *                       R_BLE_GAP_ConfWhiteList() was called.
+     *                  
BLE_ERR_MEM_ALLOC_FAILED(0x000C)
+     *                       White List has already registered the maximum number of devices.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_white_list_conf_evt_t
+     */
+    BLE_GAP_EVENT_WHITE_LIST_CONF_COMP,
+
+    /**
+     *  @brief     Random address has been set to Controller.
+     *  @details
+     *  This event notifies Controller has been set the random address by R_BLE_GAP_SetRandAddr().
+     *
+     * ## Event Code: 0x1113
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       When local device was in legacy advertising, R_BLE_GAP_SetRandAddr() was called.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_RAND_ADDR_SET_COMP,
+
+    /**
+     *  @brief     Channel Map has been retrieved.
+     *  @details
+     *  This event notifies Channel Map has been retrieved by R_BLE_GAP_ReadChMap().
+     *
+     * ## Event Code: 0x1114
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                       The remote device specified by R_BLE_GAP_ReadChMap() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_rd_ch_map_evt_t
+     */
+    BLE_GAP_EVENT_CH_MAP_RD_COMP,
+
+    /**
+     *  @brief     Channel Map has set.
+     *  @details
+     *  This event notifies Channel Map has been configured by R_BLE_GAP_SetChMap().
+     *
+     * ## Event Code: 0x1115
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                       The channel map specified by R_BLE_GAP_SetChMap() was all-zero.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_CH_MAP_SET_COMP,
+
+    /**
+     *  @brief     RSSl has been retrieved.
+     *  @details
+     *  This event notifies RSSI has been retrieved by R_BLE_GAP_ReadRssi().
+     *
+     * ## Event Code: 0x1116
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                       The remote device specified by R_BLE_GAP_ReadRssi() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_rd_rssi_evt_t
+     */
+    BLE_GAP_EVENT_RSSI_RD_COMP,
+
+    /**
+     *  @brief     Information about the remote device has been retrieved.
+     *  @details
+     *  This event notifies information about the remote device has been retrieved by R_BLE_GAP_GetRemDevInfo().
+     *
+     * ## Event Code: 0x1117
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_dev_info_evt_t
+     */
+    BLE_GAP_EVENT_GET_REM_DEV_INFO,
+
+    /**
+     *  @brief     Connection parameters has been configured.
+     *  @details
+     *  This event notifies the connection parameters has been updated.
+     *
+     * ## Event Code: 0x1118
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_DATA(0x0002)
+     *                       Local device rejected the request for updating connection parameters.
+     *                  
BLE_ERR_INVALID_ARG(0x0003)
+     *                       The remote device rejected the connection parameters suggested from local device.
+     *                  
BLE_ERR_UNSUPPORTED(0x0007)
+     *                       The remote device doesn't support connection parameters update feature.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_upd_evt_t
+     */
+    BLE_GAP_EVENT_CONN_PARAM_UPD_COMP,
+
+    /**
+     *  @brief     Local device has received the request for configuration of connection parameters.
+     *  @details
+     *  This event notifies the request for connection parameters update has been received.
+     *
+     * ## Event Code: 0x1119
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_upd_req_evt_t
+     */
+    BLE_GAP_EVENT_CONN_PARAM_UPD_REQ,
+
+    /**
+     *  @brief     Authenticated Payload Timeout.
+     *  @details
+     *  This event notifies Authenticated Payload Timeout has occurred.
+     *
+     * ## Event Code: 0x111A
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_hdl_evt_t
+     */
+    BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED,
+
+    /**
+     *  @brief     The request for update transmission packet size and transmission time have been sent to Controller.
+     *  @details
+     *  This event notifies a request for updating packet data length and transmission timer has been sent to Controller.
+     *
+     * ## Event Code: 0x111B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                       The tx_octets or tx_time parameter specified by R_BLE_GAP_SetDataLen() is invalid.
+     *                  
BLE_ERR_UNSUPPORTED(0x0007)
+     *                       The remote device does not support updating packet data length and transmission time.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                        When R_BLE_GAP_SetDataLen() was called, the connection was not established.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_hdl_evt_t
+     */
+    BLE_GAP_EVENT_SET_DATA_LEN_COMP,
+
+    /**
+     *  @brief     Transmission packet size and transmission time have been changed.
+     *  @details
+     *  This event notifies packet data length and transmission time have been updated.
+     *
+     * ## Event Code: 0x111C
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_data_len_chg_evt_t
+     */
+    BLE_GAP_EVENT_DATA_LEN_CHG,
+
+    /**
+     *  @brief     The Resolving List has been configured.
+     *  @details
+     *  When Resolving List has been configured by R_BLE_GAP_ConfRslvList(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x111D
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_STATE(0x0008)
+     *                       The add or delete operation was called,
+     *                       before the previous clear operation has been completed.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       While doing advertising or scanning or creating a link with resolvable private address,
+     *                       R_BLE_GAP_ConfRslvList() was called.
+     *                  
BLE_ERR_MEM_ALLOC_FAILED(0x000C)
+     *                       Resolving List has already registered the maximum number of devices.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                       The specified Identity Address was not found in Resolving List.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_rslv_list_conf_evt_t
+     */
+    BLE_GAP_EVENT_RSLV_LIST_CONF_COMP,
+
+    /**
+     *  @brief     Resolvable private address function has been enabled or disabled.
+     *  @details
+     *  When Resolvable Private Address function in Controller has been enabled by R_BLE_GAP_EnableRpa(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x111E
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                      While advertising, scanning, or establishing a link with resolvable private address,
+     *                      R_BLE_GAP_EnableRpa() was called.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_RPA_EN_COMP,
+
+    /**
+     *  @brief      The update time of resolvable private address has been changed.
+     *  @details
+     *  When Resolvable Private Address Timeout in Controller has been updated by R_BLE_GAP_SetRpaTo(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x111F
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                      The rpa_timeout parameter specified by R_BLE_GAP_SetRpaTo() is out of range.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_SET_RPA_TO_COMP,
+
+    /**
+     *  @brief      The resolvable private address of local device has been retrieved.
+     *  @details
+     *  When the resolvable private address of local device has been retrieved by R_BLE_GAP_ReadRpa(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1120
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The identity address specified by R_BLE_GAP_ReadRpa() was not registered in Resolving List.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_rd_rpa_evt_t
+     */
+    BLE_GAP_EVENT_RD_RPA_COMP,
+
+    /**
+     *  @brief       PHY for connection has been changed.
+     *  @details
+     *  This event notifies the application layer that PHY for a connection has been updated.
+     *
+     * ## Event Code: 0x1121
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_phy_upd_evt_t
+     */
+    BLE_GAP_EVENT_PHY_UPD,
+
+    /**
+     *  @brief      The request for updating PHY for connection has been sent to Controller.
+     *  @details
+     *  When Controller has received a request for updating PHY for a connection by R_BLE_GAP_SetPhy(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1122
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The remote device specified by R_BLE_GAP_SetPhy() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_hdl_evt_t
+     */
+    BLE_GAP_EVENT_PHY_SET_COMP,
+
+    /**
+     *  @brief      The request for setting default PHY has been sent to Controller.
+     *  @details
+     *  When the PHY preferences which a remote device may change has been configured by R_BLE_GAP_SetDefPhy(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1123
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_DEF_PHY_SET_COMP,
+
+    /**
+     *  @brief      PHY configuration has been retrieved.
+     *  @details
+     *  When the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1124
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)
+     *                      The link specified by R_BLE_GAP_ReadPhy() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_phy_rd_evt_t
+     */
+    BLE_GAP_EVENT_PHY_RD_COMP,
+
+    /**
+     *  @brief      Scan Request has been received.
+     *  @details
+     *  This event notifies the application layer that a Scan Request packet has been received from a Scanner.
+     *
+     * ## Event Code: 0x1125
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_scan_req_recv_evt_t
+     */
+    BLE_GAP_EVENT_SCAN_REQ_RECV,
+
+    /**
+     *  @brief      The request for establishing a periodic sync has been sent to Controller.
+     *  @details
+     *  This event notifies the application layer that Controller has received a request
+     *  for a Periodic Sync establishment.
+     *
+     * ## Event Code: 0x1126
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       When R_BLE_GAP_CreateSync() was called,
+     *                       this event for previous the API call has not been received.
+     *                  
BLE_ERR_ALREADY_IN_PROGRESS(0x000A)
+     *                      The advertising set specified by R_BLE_GAP_CreateSync() has already established
+     *                      a periodic sync.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_CREATE_SYNC_COMP,
+
+    /**
+     *  @brief      The periodic advertising sync has been established.
+     *  @details
+     *  This event notifies the application layer that a Periodic sync has been established.
+     *
+     * ## Event Code: 0x1127
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_NOT_YET_READY(0x0012)
+     *                      The request for a Periodic Sync establishment was cancelled by R_BLE_GAP_CancelCreateSync().
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_sync_est_evt_t
+     */
+    BLE_GAP_EVENT_SYNC_EST,
+
+    /**
+     *  @brief       The periodic advertising sync has been terminated.
+     *  @details
+     *  This event notifies the application layer that the Periodic Sync has been terminated
+     *  by R_BLE_GAP_TerminateSync().
+     *
+     * ## Event Code: 0x1128
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       While establishing a Periodic Sync by R_BLE_GAP_CreateSync(),
+     *                       R_BLE_GAP_TerminateSync() was called.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                       The sync handle specified by R_BLE_GAP_TerminateSync() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_sync_hdl_evt_t
+     */
+    BLE_GAP_EVENT_SYNC_TERM,
+
+    /**
+     *  @brief       The periodic advertising sync has been lost.
+     *  @details
+     *  This event notifies the application layer that the Periodic Sync has been lost.
+     *
+     * ## Event Code: 0x1129
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_sync_hdl_evt_t
+     */
+    BLE_GAP_EVENT_SYNC_LOST,
+
+    /**
+     *  @brief       The request for cancel of establishing a periodic advertising sync has been sent to Controller.
+     *  @details
+     *  This event notifies the request for a Periodic Sync establishment has been cancelled
+     *  by R_BLE_GAP_CancelCreateSync().
+     *
+     * ## Event Code: 0x112A
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                       When R_BLE_GAP_CancelCreateSync() was called,
+     *                       a request for a Periodic Sync establishment by R_BLE_GAP_CreateSync()
+     *                       has not been sent to Controller.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP,
+
+    /**
+     *  @brief       The Periodic Advertiser list has been configured.
+     *  @details
+     *  When Periodic Advertiser List has been configured by R_BLE_GAP_ConfPerdAdvList(),
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x112B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)
+     *                        The advertiser has already been registered in Periodic Advertiser List.
+     *                  
BLE_ERR_INVALID_STATE(0x0008)
+     *                       The add or delete operation was called, before the previous clear operation has been completed.
+     *                  
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                         When establishing a periodic sync by R_BLE_GAP_CreateSync(),
+     *                         R_BLE_GAP_ConfPerdAdvList() was called.
+     *                  
BLE_ERR_MEM_ALLOC_FAILED(0x000C)
+     *                         Periodic Advertiser List has already registered the maximum number of devices.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                         The device specified by R_BLE_GAP_ConfPerdAdvList() was not found.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_perd_list_conf_evt_t
+     */
+    BLE_GAP_EVENT_PERD_LIST_CONF_COMP,
+
+    /**
+     *  @brief       Privacy Mode has been configured.
+     *  @details
+     *  This event notifies the application layer that the Privacy Mode has been configured by R_BLE_GAP_SetPrivMode().
+     *
+     * ## Event Code: 0x112B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)Address type or privacy mode is out of range.
BLE_ERR_INVALID_OPERATION(0x0009)
+     *                         While advertising, scanning, or establishing a link with resolvable private address,
+     *                         R_BLE_GAP_SetPrivMode() was called.
+     *                  
BLE_ERR_INVALID_HDL(0x000E)
+     *                         The address specified by R_BLE_GAP_SetPrivMode() has not been registered
+     *                         in Resolving List.
+     *                  

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_GAP_EVENT_PRIV_MODE_SET_COMP,
+
+    /**
+     *  @brief       The pairing request from a remote device has been received.
+     *  @details
+     *  This event notifies the application layer that a pairing request from a remote device has been received.
+     *
+     * ## Event Code: 0x1401
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_pairing_info_evt_t
+     */
+    BLE_GAP_EVENT_PAIRING_REQ = 0x1401,
+
+    /**
+     *  @brief       The request for input passkey has been received.
+     *  @details
+     *  This event notifies that a request for Passkey input in pairing has been received.
+     *
+     * ## Event Code: 0x1402
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_hdl_evt_t
+     */
+    BLE_GAP_EVENT_PASSKEY_ENTRY_REQ,
+
+    /**
+     *  @brief       The request for displaying a passkey has been received.
+     *  @details
+     *  This event notifies that a request for Passkey display in pairing has been received.
+     *
+     * ## Event Code: 0x1403
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_passkey_display_evt_t
+     */
+    BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ,
+
+    /**
+     *  @brief     The request for confirmation with Numeric Comparison has received.
+     *  @details
+     *  This event notifies that a request for Numeric Comparison in pairing has been received.
+     *
+     * ## Event Code: 0x1404
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_num_comp_evt_t
+     */
+    BLE_GAP_EVENT_NUM_COMP_REQ,
+
+    /**
+     *  @brief     Key Notification from a remote device has been received.
+     *  @details
+     *  This event notifies the application layer that the remote device has input a key in Passkey Entry.
+     *
+     * ## Event Code: 0x1405
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_key_press_ntf_evt_t
+     */
+    BLE_GAP_EVENT_KEY_PRESS_NTF,
+
+    /**
+     *  @brief     Pairing has been completed.
+     *  @details
+     *  This event notifies the application layer that the pairing has completed.
+     *
+     * ## Event Code: 0x1406
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL(0x2001)PassKey Entry is failed.
BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE(0x2002)OOB Data is not available.
BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET(0x2003)The requested pairing can not be performed because of IO Capability. 
BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH(0x2004)Confirmation value does not match.
BLE_ERR_SMP_LE_PAIRING_NOT_SPRT(0x2005)Pairing is not supported.
BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE(0x2006)Encryption Key Size is insufficient.
BLE_ERR_SMP_LE_CMD_NOT_SPRT(0x2007)The pairing command received is not supported.
BLE_ERR_SMP_LE_UNSPECIFIED_REASON(0x2008)Pairing failed with an unspecified reason.
BLE_ERR_SMP_LE_REPEATED_ATTEMPTS(0x2009)The number of repetition exceeded the upper limit.
BLE_ERR_SMP_LE_INVALID_PARAM(0x200A)Invalid parameter is set.
BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL(0x200B)DHKey Check error.
BLE_ERR_SMP_LE_NUM_COMP_FAIL(0x200C)Numeric Comparison failure.
BLE_ERR_SMP_LE_DISCONNECTED(0x200F)Disconnection in pairing.
BLE_ERR_SMP_LE_TO(0x2011) Failure due to timeout.
BLE_ERR_SMP_LE_LOC_KEY_MISSING(0x2014)Pairing/Encryption failure because local device lost the LTK.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_pairing_info_evt_t
+     */
+    BLE_GAP_EVENT_PAIRING_COMP,
+
+    /**
+     *  @brief     Key Notification from a remote device has been received.
+     *  @details
+     *  This event notifies the application layer that the encryption status of a link has been changed.
+     *
+     * ## Event Code: 0x1407
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_enc_chg_evt_t
+     */
+    BLE_GAP_EVENT_ENC_CHG,
+
+    /**
+     *  @brief     Keys has been received from a remote device.
+     *  @details
+     *  This event notifies the application layer that the remote device has distributed the keys.
+     *
+     * ## Event Code: 0x1408
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_peer_key_info_evt_t
+     */
+    BLE_GAP_EVENT_PEER_KEY_INFO,
+
+    /**
+     *  @brief     The request for key distribution has been received.
+     *  @details
+     *  When local device has been received a request for key distribution to remote device,
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x1409
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_conn_hdl_evt_t
+     */
+    BLE_GAP_EVENT_EX_KEY_REQ,
+
+    /**
+     *  @brief     LTK has been request from a remote device.
+     *  @details
+     *  When local device has been received a LTK request from a remote device,
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x140A
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_ltk_req_evt_t
+     */
+    BLE_GAP_EVENT_LTK_REQ,
+
+    /**
+     *  @brief     LTK reply has been sent to Controller.
+     *  @details
+     *  When local device has replied to the LTK request from the remote device,
+     *  this event is notified to the application layer.
+     *
+     * ## Event Code: 0x140B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_ltk_rsp_evt_t
+     */
+    BLE_GAP_EVENT_LTK_RSP_COMP,
+
+    /**
+     *  @brief     The authentication data to be used in Secure Connections OOB has been created.
+     *  @details
+     *  This event notifies OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData().
+     *
+     * ## Event Code: 0x140C
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_gap_sc_oob_data_evt_t
+     */
+    BLE_GAP_EVENT_SC_OOB_CREATE_COMP,
+} e_ble_gap_evt_t;
+
+/*@}*/
+
+/* ========================================== GATT Server Type Definitions ========================================== */
+
+/** @addtogroup GATT_SERVER_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_SERVER_API
+ * @ingroup GATT_CLIENT_API
+ *  @struct st_ble_gatt_value_t
+ *  @brief  Attribute Value.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Length of the attribute value.
+     */
+    uint16_t value_len;
+
+    /**
+     *  @brief     Attribute Value.
+     */
+    uint8_t * p_value;
+} st_ble_gatt_value_t;
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_SERVER_API
+ * @ingroup GATT_CLIENT_API
+ *  @struct st_ble_gatt_hdl_value_pair_t
+ *  @brief  Attribute handle and attribute Value.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Attribute Handle
+     */
+    uint16_t attr_hdl;
+
+    /**
+     *  @brief     Attribute Value
+     */
+    st_ble_gatt_value_t value;
+} st_ble_gatt_hdl_value_pair_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatt_queue_att_val_t
+ *  @brief  Queued writes Attribute Value.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Attribute Value for Queued Write .
+     */
+    uint8_t * p_value;
+
+    /**
+     *  @brief     Length of the attribute value.
+     */
+    uint16_t value_len;
+
+    /**
+     *  @brief     padding.
+     */
+    uint16_t padding;
+} st_ble_gatt_queue_att_val_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatt_queue_pair_t
+ *  @brief  Queued writes Attribute Value.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     Attribute Value for Queued Write
+     */
+    st_ble_gatt_queue_att_val_t queue_value;
+
+    /**
+     *  @brief     Attribute Handle
+     */
+    uint16_t attr_hdl;
+} st_ble_gatt_queue_pair_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatt_queue_elm_t
+ *  @brief  Prepare Write Queue element for long chracteristic.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Part of Long Characteristic Value and Characteristic Value Handle.
+     */
+    st_ble_gatt_queue_pair_t queue_value_pair;
+
+    /**
+     *  @brief    Offset that indicates the location to be written.
+     */
+    uint16_t offset;
+} st_ble_gatt_queue_elm_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatt_pre_queue_t
+ *  @brief  Prepare Write Queue for long chracteristic.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Buffer start address for Write Long Characteristic Request.
+     */
+    uint8_t * p_buf_start;
+
+    /**
+     *  @brief    Prepare Write Queue for Long Characteristic Value.
+     */
+    st_ble_gatt_queue_elm_t * p_queue;
+
+    /**
+     *  @brief    Buffer length.
+     */
+    uint16_t buffer_len;
+
+    /**
+     *  @brief    Connection Handle.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief    Current buffer offset.
+     */
+    uint16_t buf_offset;
+
+    /**
+     *  @brief    Number of elements in the prepare write queue.
+     */
+    uint8_t queue_size;
+
+    /**
+     *  @brief    Index of Prepare Write Queue.
+     */
+    uint8_t queue_idx;
+} st_ble_gatt_pre_queue_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_params_t
+ *  @brief  Attribute value to be set to or retrieved from the GATT Database and the access type from the GATT Client.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute value to be set to or retrieved from the GATT Database.
+     *            Note that the address of the value field in the value field is invalid in case of read access.
+     */
+    st_ble_gatt_value_t value;
+
+    /**
+     *  @brief    Attribute handle identifying the attribute to be set or retrieved.
+     */
+    uint16_t attr_hdl;
+
+    /**
+     *  @brief    Type of the access to GATT Database from the GATT Client.
+     *  @sa       access_type_to_gatt_database
+     */
+    uint8_t db_op;
+} st_ble_gatts_db_params_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_conn_hdl_t
+ *  @brief  Information about the service or the characteristic that the attribute belongs to.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Connection handle identifying the GATT Client that accesses to the GATT DataBase.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief    ID of the service that the attribute belongs to.
+     */
+    uint8_t service_id;
+
+    /**
+     *  @brief    ID of the Characteristic that the attribute belongs to.
+     */
+    uint8_t char_id;
+} st_ble_gatts_db_conn_hdl_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_access_evt_t
+ *  @brief  This structure notifies that the GATT Database has been accessed from a GATT Client.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Information about the service or the characteristic that the attribute belongs to.
+     */
+    st_ble_gatts_db_conn_hdl_t * p_handle;
+
+    /**
+     *  @brief    Attribute value to be set to or retrieved from the GATT Database
+     *            and the access type from the GATT Client.
+     */
+    st_ble_gatts_db_params_t * p_params;
+} st_ble_gatts_db_access_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_conn_evt_t
+ *  @brief  This structure notifies that the link with the GATT Client has been established.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Address of the GATT Client.
+     */
+    st_ble_dev_addr_t * p_addr;
+} st_ble_gatts_conn_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_disconn_evt_t
+ *  @brief  This structure notifies that the link with the GATT Client has been disconnected.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Address of the GATT Client.
+     */
+    st_ble_dev_addr_t * p_addr;
+} st_ble_gatts_disconn_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_ex_mtu_req_evt_t
+ *  @brief  This structure notifies that a MTU Exchange Request PDU has been received from a GATT Client.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Maximum receive MTU size by GATT Client.
+     */
+    uint16_t mtu;
+} st_ble_gatts_ex_mtu_req_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_cfm_evt_t
+ *  @brief  This structure notifies that a Confirmation PDU has been received from a GATT Client.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic sent by the Indication PDU.
+     */
+    uint16_t attr_hdl;
+} st_ble_gatts_cfm_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_read_by_type_rsp_evt_t
+ *  @brief  This structure notifies that a Read By Type Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic read by the Read By Type Request PDU.
+     */
+    uint16_t attr_hdl;
+} st_ble_gatts_read_by_type_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_read_rsp_evt_t
+ *  @brief  This structure notifies that a Read Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic read by the Read Request PDU.
+     */
+    uint16_t attr_hdl;
+} st_ble_gatts_read_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_read_blob_rsp_evt_t
+ *  @brief  This structure notifies that a Read Blob Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic read by the Read Blob Request PDU.
+     */
+    uint16_t attr_hdl;
+} st_ble_gatts_read_blob_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_read_multi_rsp_evt_t
+ *  @brief  This structure notifies that a Read Multiple Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The number of attribute read by the Read Multiple Request PDU.
+     */
+    uint8_t count;
+
+    /**
+     *  @brief    The list of attribute read by the Read Multiple Request PDU.
+     */
+    uint16_t * p_attr_hdl_list;
+} st_ble_gatts_read_multi_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_write_rsp_evt_t
+ *  @brief  This structure notifies that a Write Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic written by the Write Request PDU.
+     */
+    uint16_t attr_hdl;
+} st_ble_gatts_write_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_prepare_write_rsp_evt_t
+ *  @brief  This structure notifies that a Prepare Write Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle identifying the Characteristic written by the Prepare Write Request PDU.
+     */
+    uint16_t attr_hdl;
+
+    /**
+     *  @brief     The length of written bytes by the Prepare Write Request PDU.
+     */
+    uint16_t length;
+
+    /**
+     *  @brief     The offset of the first octet to be written.
+     */
+    uint16_t offset;
+} st_ble_gatts_prepare_write_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_exe_write_rsp_evt_t
+ *  @brief  This structure notifies that a Execute Write Response PDU has been sent from GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The flag that indicates whether execution or cancellation.
+     *  @details
+     *    |  value     |   description     |
+     *    |:-----------|:----------------- |
+     *    | 0x00       | Cancellation.     |
+     *    | 0x01       | Execution.        |
+     */
+    uint8_t exe_flag;
+} st_ble_gatts_exe_write_rsp_evt_t;
+
+/* GATT DB Structure */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_uuid_cfg_t
+ *  @brief  A structure that defines the information on the position where UUIDs are used.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The position of the defined UUID is specified by offset value in uuid_table of st_ble_gatts_db_cfg_t.
+     */
+    uint16_t offset;
+
+    /**
+     *  @brief    The attribute handle that indicates the first position in st_ble_gatts_db_attr_cfg_t
+     *            for the defined UUID is specified.
+     */
+    uint16_t first;
+
+    /**
+     *  @brief    The attribute handle that indicates the last position in st_ble_gatts_db_attr_cfg_t
+     *            for the defined UUID is specified.
+     */
+    uint16_t last;
+} st_ble_gatts_db_uuid_cfg_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_attr_cfg_t
+ *  @brief  A structure that defines the detailed information of the attributes.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The properties of attribute are specified.
+     *  @details  Set the following properties by a bitwise OR.
+     *    |              macro                        |   description                          |
+     *    |:------------------------------------------|:-------------------------------------- |
+     *    | BLE_GATT_DB_READ(0x01)                    | Allow clients to read.                 |
+     *    | BLE_GATT_DB_WRITE(0x02)                   |  Allow clients to write.               |
+     *    | BLE_GATT_DB_WRITE_WITHOUT_RSP(0x04)       |  Allow clients to write.               |
+     *    | BLE_GATT_DB_READ_WRITE(0x07)              |  Allow clients to access of all.       |
+     */
+    uint8_t desc_prop;
+
+    /**
+     *  @brief    The auxiliary properties of attribute are specified.
+     *  @details  Set the following properties by a bitwise OR.
+     *      
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *          
+     *              
+     *              
+     *          
+     *      
macrodescription
BLE_GATT_DB_NO_AUXILIARY_PROPERTY(0x00)
+     *                  No auxiliary properties.\n
+     *                  It is invalid when used with other properties at the same time.
+     *              
BLE_GATT_DB_FIXED_LENGTH_PROPERTY(0x01)
+     *                  Fixed length attribute value.
+     *              
BLE_GATT_DB_AUTHORIZATION_PROPERTY(0x02)
+     *                  Attributes requiring authorization.
+     *              
BLE_GATT_DB_ATTR_DISABLED(0x10)
+     *                  The attribute is disabled.
+     *                  If this value is set, the attribute cannot be found and accessed by a GATT Client.
+     *                  It is invalid when used with other properties at the same time.
+     *              
BLE_GATT_DB_128_BIT_UUID_FORMAT(0x20)
+     *                  Attribute with 128 bit UUID.\n
+     *                  If this macro is not set, the attribute value is 16-bits UUID.
+     *              
BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY(0x40)
+     *                  Attribute managed by each GATT Client.
+     *              
BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY(0x80)
+     *                  Fixed attribute value.\n
+     *                  Writing from Client and setting from Server are prohibited.
+     *              

+     */
+    uint8_t aux_prop;
+
+    /**
+     *  @brief    The length of the attribute value is specified.
+     */
+    uint16_t length;
+
+    /**
+     *  @brief    The position of the next attribute with the same UUID
+     *            as the defined attribute is specified by an attribute handle.
+     */
+    uint16_t next;
+
+    /**
+     *  @brief    The storage area of attribute value.
+     *  @details  UUID of the defined attribute is set by specifying the position of the UUID registered
+     *            in uuid_table of st_ble_gatts_db_cfg_t with the array offset value.
+     */
+    uint16_t uuid_offset;
+
+    /**
+     *  @brief    Storage area of attribute value.
+     *  @details  The address in the array registered in No.1-No.4 is specified to set the attribute value storage area of the defined attribute.
+     */
+    uint8_t * p_data_offset;
+} st_ble_gatts_db_attr_cfg_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_attr_list_t
+ *  @brief  The number of attributes are stored.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The number of the services or the characteristics.
+     */
+    uint8_t count;
+} st_ble_gatts_db_attr_list_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_char_cfg_t
+ *  @brief  A structure that defines the detailed information of the characteristics.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The total number of attributes in the defined characteristic is specified.
+     */
+    st_ble_gatts_db_attr_list_t list;
+
+    /**
+     *  @brief    The first attribute handle of the characteristic is specified.
+     */
+    uint16_t start_hdl;
+
+    /**
+     *  @brief    The index of service to which the characteristic belongs is specified.
+     */
+    uint8_t service_id;
+} st_ble_gatts_db_char_cfg_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_serv_cfg_t
+ *  @brief  A structure that defines the detailed information of the characteristics.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief     The total number of service declarations in the defined service is specified.
+     */
+    st_ble_gatts_db_attr_list_t list;
+
+    /**
+     *  @brief    The properties of the defined service are specified.
+     *  @details  Set the security level, the security mode and the key size with a bitwise OR.
+     *            The bit0-bit3 are specified as the security level.
+     *            Select one of the following.
+     *              
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *              
macrodescription
BLE_GATT_DB_SER_SECURITY_UNAUTH(0x00000001)Unauthenticated pairing(Security Mode1 Security Level 2, Security Mode 2 Security Level 1)

+     *                      Unauthenticated pairing is required to access the service.
+     *                      
BLE_GATT_DB_SER_SECURITY_AUTH(0x00000002)Authenticated pairing(Security Mode1 Security Level 3, Security Mode 2 Security Level 2)

+     *                      Authenticated pairing is required to access the service.
+     *                      
BLE_GATT_DB_SER_SECURITY_SECONN(0x00000004)Authenticated LE secure connections that generates 16bytes LTK(Security Mode1 Security Level 4)

+     *                      Authenticated LE secure connections pairing that generates 16bytes LTK is required to access the service. If this bit is set, bit24-27 are ignored.
+     *                      

+     *              

+     *              The bit4 is specified as the security mode.

+     *              
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *              
macrodescription
BLE_GATT_DB_SER_SECURITY_ENC(0x00000010)Encryption

+     *                      Encryption by the LTK exchanged in pairing is required to access.

+     *              

+     *              If the security requirement of the service is not needed,
+     *              specify the bit0-bit4 to BLE_GATT_DB_SER_NO_SECURITY_PROPERTY(0x00000000).(Security Mode1 Security Level 1)

+     *              The bit24-bit27 are specified as the key size required by the defined service.

+     *              Select one of the following.

+     *              
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *              
macrodescription
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7(0x01000000)7-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8(0x02000000)8-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9(0x03000000)9-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10(0x04000000)10-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11(0x05000000)11-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12(0x06000000)12-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13(0x07000000)13-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14(0x08000000)14-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15(0x09000000)15-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16(0x0A000000)16-byte encryption key.
BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE(0x00000000)7-byte or larger encryption key.

+     *              

+     *              Other bits are reserved.

+     */
+    uint32_t desc;
+
+    /**
+     *  @brief     The start attribute handle of the defined service is specified.
+     */
+    uint16_t start_hdl;
+
+    /**
+     *  @brief      The end attribute handle of the defined service is specified.
+     */
+    uint16_t end_hdl;
+
+    /**
+     *  @brief      The start index of the characteristic that belongs to the defined service is specified.
+     */
+    uint8_t char_start_idx;
+
+    /**
+     *  @brief      The end index of the characteristic that belongs to the defined service is specified.
+     */
+    uint8_t char_end_idx;
+} st_ble_gatts_db_serv_cfg_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_db_cfg_t
+ *  @brief  This is the structure of GATT Database that is specified in R_BLE_GATTS_SetDbInst().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief      The array to register the UUID to be used.
+     */
+    const uint8_t * p_uuid_table;
+
+    /**
+     *  @brief      The array to register variable attribute values.
+     */
+    uint8_t * p_attr_val_table;
+
+    /**
+     *  @brief      The array to register fixed attribute values.
+     */
+    const uint8_t * p_const_attr_val_table;
+
+    /**
+     *  @brief      The array to manage the attribute values handled for each GATT client.
+     */
+    uint8_t * p_rem_spec_val_table;
+
+    /**
+     *  @brief      The array to register the default of the attribute value handled by each GATT client.
+     */
+    const uint8_t * p_const_rem_spec_val_table;
+
+    /**
+     *  @brief      The array to register information on the position where UUIDs are used.
+     */
+    const st_ble_gatts_db_uuid_cfg_t * p_uuid_cfg;
+
+    /**
+     *  @brief      The array to register the detailed information of attributes.
+     */
+    const st_ble_gatts_db_attr_cfg_t * p_attr_cfg;
+
+    /**
+     *  @brief       The array to register the detailed information of characteristics.
+     */
+    const st_ble_gatts_db_char_cfg_t * p_char_cfg;
+
+    /**
+     *  @brief        The array to register the detailed information of services.
+     */
+    const st_ble_gatts_db_serv_cfg_t * p_serv_cfg;
+
+    /**
+     *  @brief        The number of services included in the GATT Database.
+     */
+    uint8_t serv_cnt;
+
+    /**
+     *  @brief        The number of characteristics included in the GATT Database.
+     */
+    uint8_t char_cnt;
+
+    /**
+     *  @brief        The number of UUIDs included in the GATT Database.
+     */
+    uint8_t uuid_type_cnt;
+
+    /**
+     *  @brief        The total size of attribute value that needs to be managed for each GATT client.
+     */
+    uint8_t peer_spec_val_cnt;
+} st_ble_gatts_db_cfg_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gatts_evt_data_t
+ *  @brief  st_ble_gatts_evt_data_t is the type of the data notified in a GATT Server Event.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief        Connection handle identifying the GATT Client.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief        The size of GATT Server Event parameters.
+     */
+    uint16_t param_len;
+
+    /**
+     *  @brief         GATT Server Event parameters. This parameter differs in each GATT Server Event.
+     */
+    void * p_param;
+} st_ble_gatts_evt_data_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_gatts_app_cb_t
+ * @brief   ble_gatts_app_cb_t is the GATT Server Event callback function type.
+ * @param[in] event_type    The type of GATT Server Event.
+ * @param[in] event_result  The result of GATT Server Event
+ * @param[in] p_event_data    Data notified by GATT Server Event.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_gatts_app_cb_t)(uint16_t event_type, ble_status_t event_result,
+                                    st_ble_gatts_evt_data_t * p_event_data);
+
+/*@}*/
+
+/* ========================================== GATT Client Type Definitions ========================================== */
+
+/** @addtogroup GATT_CLIENT_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ *  @ingroup GATT_CLIENT_API
+ *  @struct st_ble_gatt_hdl_range_t
+ *  @brief  Attribute handle range.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief          Start Attribute Handle.
+     */
+    uint16_t start_hdl;
+
+    /**
+     *  @brief         End Attribute Handle.
+     */
+    uint16_t end_hdl;
+} st_ble_gatt_hdl_range_t;
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_CLIENT_API
+ *  @struct st_ble_gattc_reliable_writes_char_pair_t
+ *  @brief  This is used in R_BLE_GATTC_ReliableWrites() to specify the pair of Characteristic Value and
+ *          Characteristic Value Handle.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief         Pair of Characteristic Value and Characteristic Value Handle.
+     */
+    st_ble_gatt_hdl_value_pair_t write_data;
+
+    /**
+     *  @brief         Offset that indicates the location to be written.
+     *  @details       Normally, set 0 to this parameter.\n
+     *                 If this parameter sets to a value other than 0,Adjust the offset parameter and the length of
+     *                 the value to be written not to exceed the length of the Characteristic.
+     */
+    uint16_t offset;
+} st_ble_gattc_reliable_writes_char_pair_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_conn_evt_t
+ *  @brief  This structure notifies that the link with the GATT Server has been established.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Address of the GATT Server.
+     */
+    st_ble_dev_addr_t * p_addr;
+} st_ble_gattc_conn_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_disconn_evt_t
+ *  @brief  This structure notifies that the link with the GATT Server has been disconnected.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Address of the GATT Server.
+     */
+    st_ble_dev_addr_t * p_addr;
+} st_ble_gattc_disconn_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_ex_mtu_rsp_evt_t
+ *  @brief  This structure notifies that a MTU Exchange Response PDU has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    MTU size(in bytes) that GATT Server can receive.
+     */
+    uint16_t mtu;
+} st_ble_gattc_ex_mtu_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_serv_16_evt_t
+ *  @brief  This structure notifies that a 16-bit UUID Service has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle range of the 16-bit UUID service.
+     */
+    st_ble_gatt_hdl_range_t range;
+
+    /**
+     *  @brief    Service UUID.
+     */
+    uint16_t uuid_16;
+} st_ble_gattc_serv_16_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_serv_128_evt_t
+ *  @brief  This structure notifies that a 128-bit UUID Service has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle range of the 128-bit UUID service.
+     */
+    st_ble_gatt_hdl_range_t range;
+
+    /**
+     *  @brief    Service UUID.
+     */
+    uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE];
+} st_ble_gattc_serv_128_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_inc_serv_16_evt_t
+ *  @brief  This structure notifies that a 16-bit UUID Included Service has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Service Declaration handle of the 16-bit UUID Included Service.
+     */
+    uint16_t decl_hdl;
+
+    /**
+     *  @brief    The contents of the Included Service.
+     */
+    st_ble_gattc_serv_16_evt_t service;
+} st_ble_gattc_inc_serv_16_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_inc_serv_128_evt_t
+ *  @brief  This structure notifies that a 128-bit UUID Included Service has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Service Declaration handle of the 128-bit UUID Included Service.
+     */
+    uint16_t decl_hdl;
+
+    /**
+     *  @brief    The contents of the Included Service.
+     */
+    st_ble_gattc_serv_128_evt_t service;
+} st_ble_gattc_inc_serv_128_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_char_16_evt_t
+ *  @brief  This structure notifies that a 16-bit UUID Characteristic has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute handle of Characteristic Declaration.
+     */
+    uint16_t decl_hdl;
+
+    /**
+     *  @brief    Characteristic Properties.
+     *  @details  It is a bitwise OR of the following values.\n
+     *            Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties"
+     *            regarding the details of the Characteristic Properties.
+     *            |  value     |   description                        |
+     *            |:-----------|:------------------------------------ |
+     *            | 0x01       | Broadcast property                   |
+     *            | 0x02       | Read property                        |
+     *            | 0x04       | Write Without Response property      |
+     *            | 0x08       | Write property                       |
+     *            | 0x10       | Notify property                      |
+     *            | 0x20       | Indicate property                    |
+     *            | 0x40       | Authenticated Signed Writes property |
+     *            | 0x80       | Extended Properties property         |
+     */
+    uint8_t cproperty;
+
+    /**
+     *  @brief    Value Handle of the Characteristic.
+     */
+    uint16_t value_hdl;
+
+    /**
+     *  @brief    Characteristic UUID.
+     */
+    uint16_t uuid_16;
+} st_ble_gattc_char_16_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_char_128_evt_t
+ *  @brief  This structure notifies that a 128-bit UUID Characteristic has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute Handle of Characteristic Declaration.
+     */
+    uint16_t decl_hdl;
+
+    /**
+     *  @brief    Characteristic Properties.
+     *  @details  It is a bitwise OR of the following values.\n
+     *            Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties"
+     *            regarding the details of the Characteristic Properties.
+     *            |  value     |   description                        |
+     *            |:-----------|:------------------------------------ |
+     *            | 0x01       | Broadcast property                   |
+     *            | 0x02       | Read property                        |
+     *            | 0x04       | Write Without Response property      |
+     *            | 0x08       | Write property                       |
+     *            | 0x10       | Notify property                      |
+     *            | 0x20       | Indicate property                    |
+     *            | 0x40       | Authenticated Signed Writes property |
+     *            | 0x80       | Extended Properties property         |
+     */
+    uint8_t cproperty;
+
+    /**
+     *  @brief    Value Handle of the Characteristic.
+     */
+    uint16_t value_hdl;
+
+    /**
+     *  @brief    Characteristic UUID.
+     */
+    uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE];
+} st_ble_gattc_char_128_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_char_desc_16_evt_t
+ *  @brief  This structure notifies that a 16-bit UUID Characteristic Descriptor has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute Handle of Characteristic Descriptor.
+     */
+    uint16_t desc_hdl;
+
+    /**
+     *  @brief    Characteristic Descriptor UUID.
+     */
+    uint16_t uuid_16;
+} st_ble_gattc_char_desc_16_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_char_desc_128_evt_t
+ *  @brief  This structure notifies that a 128-bit UUID Characteristic Descriptor has been discovered.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Attribute Handle of Characteristic Descriptor.
+     */
+    uint16_t desc_hdl;
+
+    /**
+     *  @brief    Characteristic Descriptor UUID.
+     */
+    uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE];
+} st_ble_gattc_char_desc_128_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_err_rsp_evt_t
+ *  @brief  This structure notifies that a Error Response PDU has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The op code of the ATT Request that causes the Error Response.
+     *            |             op_code                   |
+     *            |:--------------------------------------|
+     *            |  Exchange MTU Request(0x02)           |
+     *            |  Find Information Request(0x04)       |
+     *            |  Find By Type Value Request(0x06)     |
+     *            |  Read By Type Request(0x08)           |
+     *            |  Read Request(0x0A)                   |
+     *            |  Read Blob Request(0x0C)              |
+     *            |  Read Multiple Request(0x0E)          |
+     *            |  Read by Group Type Request(0x10)     |
+     *            |  Write Request(0x12)                  |
+     *            |  Prepare Write Request(0x16)          |
+     *            |  Execute Write Request(0x18)          |
+     */
+    uint8_t op_code;
+
+    /**
+     *  @brief    Attribute handle that is target for the request.
+     */
+    uint16_t attr_hdl;
+
+    /**
+     *  @brief    The error codes notified from the GATT Server.
+     *  @details  It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined in
+     *            Core Spec and Core Spec Supplement.
+     *              
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *                  
+     *                      
+     *                      
+     *                  
+     *              
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred,  the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute.
+     *                      
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported.
+     *                      
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient.
+     *                      
0x3080 - 0x309F
+     *                          Application Error.
+     *                          The upper layer defines the error codes.
+     *                      
0x30E0 - 0x30FF
+     *                          The error code defined in Common Profile and
+     *                          Service Error Core Specification Supplement(CSS).

+     *                          CSS ver.7 defines the error codes from 0x30FC to 0x30FF.
+     *                      
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC)
+     *                          The Write Request has not been completed due to the reason other than Permission.
+     *                      
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.

+     */
+    uint16_t rsp_code;
+} st_ble_gattc_err_rsp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_ntf_evt_t
+ *  @brief  This structure notifies that a Notification PDU has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Characteristic that causes the Notification.
+     */
+    st_ble_gatt_hdl_value_pair_t data;
+} st_ble_gattc_ntf_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_ind_evt_t
+ *  @brief  This structure notifies that a Indication PDU has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    Characteristic that causes the Indication.
+     */
+    st_ble_gatt_hdl_value_pair_t data;
+} st_ble_gattc_ind_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_rd_char_evt_t
+ *  @brief  This structure notifies that read response to R_BLE_GATTC_ReadChar() or R_BLE_GATTC_ReadCharUsingUuid()
+ *          has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief    The contents of the Characteristic that has been read.
+     */
+    st_ble_gatt_hdl_value_pair_t read_data;
+} st_ble_gattc_rd_char_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_wr_char_evt_t
+ *  @brief  This structure notifies that write response to R_BLE_GATTC_WriteChar() has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Value Handle of the Characteristic/Characteristic Descriptor that has been written.
+     */
+    uint16_t value_hdl;
+} st_ble_gattc_wr_char_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_rd_multi_char_evt_t
+ *  @brief  This structure notifies that read response to R_BLE_GATTC_ReadMultiChar() has been received
+ *          from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   The number of Value Handles of the Characteristics that has been read.
+     */
+    uint16_t value_hdl_num;
+
+    /**
+     *  @brief   The contents of multiple Characteristics that have been read.
+     */
+    st_ble_gatt_value_t multi_char_val;
+} st_ble_gattc_rd_multi_char_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_char_part_wr_evt_t
+ *  @brief  This structure notifies that write response to R_BLE_GATTC_WriteLongChar() or R_BLE_GATTC_ReliableWrites()
+ *          has been received from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   The data to be written to the Characteristic/Long Characteristic/Long Characteristic Descriptor.
+     */
+    st_ble_gatt_hdl_value_pair_t write_data;
+
+    /**
+     *  @brief   Offset that indicates the location to be written.
+     */
+    uint16_t offset;
+} st_ble_gattc_char_part_wr_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_reliable_writes_comp_evt_t
+ *  @brief  This structure notifies that a response to R_BLE_GATTC_ExecWrite() has been received
+ *          from a GATT Server.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   This field indicates the command of the Execute Write that has been done.
+     *  @details
+     *            |  value     |   description       |
+     *            |:-----------|:------------------- |
+     *            | 0x00       | Cancel the write.   |
+     *            | 0x01       | Execute the write.  |
+     */
+    uint8_t exe_flag;
+} st_ble_gattc_reliable_writes_comp_evt_t;
+
+/* RBLE GATT Client Command Parameters */
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_rd_multi_req_param_t
+ *  @brief  This is used in R_BLE_GATTC_ReadMultiChar() to specify multiple Characteristics to be read.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   List of Value Handles that point the Characteristics to be read.
+     */
+    uint16_t * p_hdl_list;
+
+    /**
+     *  @brief   The number of Value Handles included in the hdl_list parameter.
+     */
+    uint16_t list_count;
+} st_ble_gattc_rd_multi_req_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_gattc_evt_data_t
+ *  @brief  st_ble_gattc_evt_data_t is the type of the data notified in a GATT Client Event.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief   Connection handle identifying the GATT Server.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief    The size of GATT Client Event parameters.
+     */
+    uint16_t param_len;
+
+    /**
+     *  @brief   GATT Client Event parameters. This parameter differs in each GATT Client Event.
+     */
+    void * p_param;
+} st_ble_gattc_evt_data_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_gattc_app_cb_t
+ * @brief   ble_gattc_app_cb_t is the GATT Client Event callback function type.
+ * @param[in] event_type    The type of GATT Client Event.
+ * @param[in] event_result  The result of GATT Client Event
+ * @param[in] p_event_data  Data notified by GATT Client Event.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_gattc_app_cb_t)(uint16_t event_type, ble_status_t event_result,
+                                    st_ble_gattc_evt_data_t * p_event_data);
+
+/*@}*/
+
+/* ============================================= L2CAP Type Definitions ============================================= */
+
+/** @addtogroup L2CAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup L2CAP_API
+ * @struct st_ble_l2cap_conn_req_param_t
+ * @brief  L2CAP CBFC Channel connection request parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on local device.
+     */
+    uint16_t local_psm;
+
+    /**
+     *  @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on remote device.
+     */
+    uint16_t remote_psm;
+
+    /**
+     *  @brief MTU size(byte) receivable on L2CAP CBFC Channel.
+     */
+    uint16_t mtu;
+
+    /**
+     *  @brief MPS size(byte) receivable on L2CAP CBFC Channel.
+     */
+    uint16_t mps;
+
+    /**
+     *  @brief The number of LE-Frame that local device can receive.
+     */
+    uint16_t credit;
+} st_ble_l2cap_conn_req_param_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_conn_rsp_param_t
+ * @brief  L2CAP CBFC Channel connection response parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief CID identifying the L2CAP CBFC Channel on local device.
+     *         The valid range is 0x40-0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1.
+     */
+    uint16_t lcid;
+
+    /**
+     *  @brief  The response to the connection request. Select one of the following.
+     *                  
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                      
+     *                          
+     *                          
+     *                      
+     *                  
macrodescription
BLE_L2CAP_CF_RSP_SUCCESS(0x0000)Notify the remote device that the connection can be established.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH(0x0005)Notify the remote device that the connection can not be established
+     *                              because of insufficient authentication.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ(0x0006)Notify the remote device that the connection can not be established
+     *                              because of insufficient Authorization.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY(0x0007)Notify the remote device that the connection can not be established
+     *                              because of Encryption Key Size.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC(0x0008)Notify the remote device that the connection can not be established
+     *                              because of Encryption.
BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM(0x000B)Notify the remote device that the connection can not be established
+     *                              because the parameters is unacceptable to local device.

+     */
+    uint16_t response;
+
+    /**
+     *  @brief MTU(byte) of packet that L2CAP CBFC Channel on local device can receive.
+     */
+    uint16_t mtu;
+
+    /**
+     *  @brief MPS(byte) of packet that L2CAP CBFC Channel on local device can receive.
+     */
+    uint16_t mps;
+
+    /**
+     *  @brief The number of LE-Frame that L2CAP CBFC Channel on local device can receive.
+     */
+    uint16_t credit;
+} st_ble_l2cap_conn_rsp_param_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_cf_conn_evt_t
+ * @brief  L2CAP CBFC Channel connection parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief CID identifying the L2CAP CBFC Channel.
+     */
+    uint16_t cid;
+
+    /**
+     *  @brief PSM allocated by the cid field.
+     */
+    uint16_t psm;
+
+    /**
+     *  @brief MTU of local/remote device.
+     */
+    uint16_t mtu;
+
+    /**
+     *  @brief MPS of local/remote device.
+     */
+    uint16_t mps;
+
+    /**
+     *  @brief Credit of local/remote device.
+     */
+    uint16_t credit;
+} st_ble_l2cap_cf_conn_evt_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_cf_data_evt_t
+ * @brief  Sent/Received Data parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief CID identifying the L2CAP CBFC Channel that has sent or received the data .
+     */
+    uint16_t cid;
+
+    /**
+     *  @brief PSM allocated by the cid field.
+     */
+    uint16_t psm;
+
+    /**
+     *  @brief Data length.
+     */
+    uint16_t data_len;
+
+    /**
+     *  @brief Sent/Received data.
+     */
+    uint8_t * p_data;
+} st_ble_l2cap_cf_data_evt_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_cf_credit_evt_t
+ * @brief  Credit parameters of local or remote device.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief CID identifying the L2CAP CBFC Channel.
+     */
+    uint16_t cid;
+
+    /**
+     *  @brief PSM allocated by the cid field.
+     */
+    uint16_t psm;
+
+    /**
+     *  @brief Current credit of local/remote device.
+     */
+    uint16_t credit;
+} st_ble_l2cap_cf_credit_evt_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_cf_disconn_evt_t
+ * @brief  Disconnection parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief CID identifying the L2CAP CBFC Channel that has been disconnected.
+     */
+    uint16_t cid;
+} st_ble_l2cap_cf_disconn_evt_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_rej_evt_t
+ * @brief  Command Reject parameters.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  The reason that the remote device has sent Command Reject.
+     */
+    uint16_t reason;
+
+    /**
+     *  @brief  Optional information about the reason that the remote device has sent Command Reject.
+     */
+    uint16_t data_1;
+
+    /**
+     *  @brief  Optional information about the reason that the remote device has sent Command Reject.
+     */
+    uint16_t data_2;
+} st_ble_l2cap_rej_evt_t;
+
+/******************************************************************************************************************//**
+ * @struct st_ble_l2cap_cf_evt_data_t
+ * @brief st_ble_l2cap_cf_evt_data_t is the type of the data notified in a L2CAP Event.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief  Connection handle identifying the remote device.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief  The size of L2CAP Event parameters.
+     */
+    uint16_t param_len;
+
+    /**
+     *  @brief  L2CAP Event parameters. This parameter differs in each L2CAP Event.
+     */
+    void * p_param;
+} st_ble_l2cap_cf_evt_data_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_l2cap_cf_app_cb_t
+ * @brief   ble_l2cap_cf_app_cb_t is the L2CAP Event callback function type.
+ * @param[in] event_type    The type of L2CAP Event.
+ * @param[in] event_result  The result of L2CAP Event
+ * @param[in] p_event_data    Data notified by L2CAP Event.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_l2cap_cf_app_cb_t)(uint16_t event_type, ble_status_t event_result,
+                                       st_ble_l2cap_cf_evt_data_t * p_event_data);
+
+/*@}*/
+
+/* ================================================ L2CAP Event Code ================================================ */
+
+/** @addtogroup L2CAP_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup L2CAP_API
+ * @enum e_r_ble_l2cap_cf_evt_t
+ * @brief  L2CAP Event Identifier
+ **********************************************************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief After the connection request for L2CAP CBFC Channel has been sent with R_BLE_L2CAP_ReqCfConn(),
+     *         when the L2CAP CBFC Channel connection response has been received,
+     *         BLE_L2CAP_EVENT_CF_CONN_CNF event occurs.
+     *
+     * ## Event Code: 0x5001
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_RSP_TIMEOUT(0x0011)L2CAP Command timeout.
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.
BLE_ERR_L2CAP_NO_RESOURCE(0x4004)No resource for connection.
BLE_ERR_L2CAP_INSUF_AUTHEN(0x4005)Insufficient authentication.
BLE_ERR_L2CAP_INSUF_AUTHOR(0x4006)Insufficient authorization.
BLE_ERR_L2CAP_INSUF_ENC_KEY_SIZE(0x4007)Insufficient encryption key size.
BLE_ERR_L2CAP_REFUSE_INSUF_ENC(0x4008)Insufficient encryption.
BLE_ERR_L2CAP_REFUSE_INVALID_SCID(0x4009) Invalid Source CID. 
BLE_ERR_L2CAP_REFUSE_SCID_ALREADY_ALLOC(0x400A)Source CID already allocated.
BLE_ERR_L2CAP_REFUSE_UNACCEPTABLE_PARAM(0x400B)Unacceptable parameters.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_conn_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_CONN_CNF = 0x5001,
+
+    /**
+     *  @brief  When a connection request for L2CPA CBFC Channel has been received from a remote device,
+     *          BLE_L2CAP_EVENT_CF_CONN_IND event occurs.
+     *
+     * ## Event Code: 0x5002
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_NOT_FOUND(0x000D)CF connection request has not been received or lcid not found. 
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_conn_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_CONN_IND = 0x5002,
+
+    /**
+     *  @brief  After local device has sent a disconnection request for L2CAP CBFC Channel by
+     *          R_BLE_L2CAP_DisconnectCf(), when the local device has received the response,
+     *          BLE_L2CAP_EVENT_CF_DISCONN_CNF event occurs.
+     *
+     * ## Event Code: 0x5003
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_disconn_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_DISCONN_CNF = 0x5003,
+
+    /**
+     *  @brief  When local device has received a disconnection request for L2CAP CBFC Channel from the remote device,
+     *          BLE_L2CAP_EVENT_CF_DISCONN_IND event occurs.\n
+     *          Host stack automatically replies the to the disconnection request.
+     *
+     * ## Event Code: 0x5004
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_disconn_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_DISCONN_IND = 0x5004,
+
+    /**
+     *  @brief  When local device has received data on L2CAP CBFC Channel, BLE_L2CAP_EVENT_CF_RX_DATA_IND event occurs.
+     *
+     * ## Event Code: 0x5005
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_data_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_RX_DATA_IND = 0x5005,
+
+    /**
+     *  @brief  When the credit of the L2CAP CBFC Channel has reached the Low Water Mark,
+     *          BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event occurs.
+     *
+     * ## Event Code: 0x5006
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_credit_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND = 0x5006,
+
+    /**
+     *  @brief  When local device has received credit from a remote device, BLE_L2CAP_EVENT_CF_TX_CRD_IND event occurs.
+     *
+     * ## Event Code: 0x5007
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_credit_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_TX_CRD_IND = 0x5007,
+
+    /**
+     *  @brief  When the data transmission has been completed from host stack to Controller,
+     *          BLE_L2CAP_EVENT_CF_TX_DATA_CNF event occurs.
+     *
+     * ## Event Code: 0x5008
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_DISCONNECTED(0x000F)  While transmitting data, L2CAP CBFC Channel has been disconnected.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_cf_data_evt_t
+     */
+    BLE_L2CAP_EVENT_CF_TX_DATA_CNF = 0x5008,
+
+    /**
+     *  @brief  When local device has received Command Reject PDU, BLE_L2CAP_EVENT_CMD_REJ event occurs.
+     *
+     * ## Event Code: 0x5009
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_l2cap_rej_evt_t
+     */
+    BLE_L2CAP_EVENT_CMD_REJ = 0x5009
+} e_r_ble_l2cap_cf_evt_t;
+
+/*@}*/
+
+/* ======================================== Vendor Specific Type Definitions ======================================== */
+
+/** @addtogroup VS_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ *  @ingroup VS_API
+ *  @struct st_ble_vs_tx_test_param_t
+ *  @brief  This is the extended transmitter test parameters used in R_BLE_VS_StartTxTest().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Channel used in Tx test.
+     */
+    uint8_t ch;
+
+    /**
+     *  @brief Length(in bytes) of the packet used in Tx Test.
+     */
+    uint8_t test_data_len;
+
+    /**
+     *  @brief Packet Payload.
+     */
+    uint8_t packet_payload;
+
+    /**
+     *  @brief Transmitter PHY used in test.
+     */
+    uint8_t phy;
+
+    /**
+     *  @brief Tx Power Level used in DTM Tx Test.
+     */
+    uint8_t tx_power;
+
+    /**
+     *  @brief Option.
+     */
+    uint8_t option;
+
+    /**
+     *  @brief The number of packet to be sent.
+     */
+    uint16_t num_of_packet;
+} st_ble_vs_tx_test_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_rx_test_param_t
+ *  @brief  This is the extended receiver test parameters used in R_BLE_VS_StartRxTest().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Channel used in Rx test.
+     */
+    uint8_t ch;
+
+    /**
+     *  @brief Receiver PHY used in the test.
+     */
+    uint8_t phy;
+} st_ble_vs_rx_test_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_set_rf_ctrl_param_t
+ *  @brief  This is the RF parameters used in R_BLE_VS_SetRfControl().
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief RF power on/off.
+     */
+    uint8_t power;
+
+    /**
+     *  @brief This field indicates whether the parameters change in RF power on.
+     */
+    uint8_t option;
+
+    /**
+     *  @brief RF rapid clock frequency adjust value(OSC internal CL adjust).
+     */
+    uint8_t clval;
+
+    /**
+     *  @brief RF slow clock configurations.
+     */
+    uint8_t slow_clock;
+
+    /**
+     *  @brief Set tx power in power on.
+     */
+    uint8_t tx_power;
+
+    /**
+     *  @brief Set RF option.
+     */
+    uint8_t rf_option;
+} st_ble_vs_set_rf_ctrl_param_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_test_end_evt_t
+ *  @brief  This structure notifies that the extended test has been terminated.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The number of packet successfully received in the receiver test.
+     */
+    uint16_t num_of_packet;
+
+    /**
+     *  @brief The number of CRC error packets in the receiver test.
+     */
+    uint16_t num_of_crc_err_packet;
+
+    /**
+     *  @brief Average RSSI(dBm) in the receiver test.
+     */
+    int8_t ave_rssi;
+
+    /**
+     *  @brief Maximum RSSI(dBm) in the receiver test.
+     */
+    int8_t max_rssi;
+
+    /**
+     *  @brief Minimum RSSI(dBm) in the receiver test.
+     */
+    int8_t min_rssi;
+} st_ble_vs_test_end_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_set_tx_pwr_comp_evt_t
+ *  @brief  This structure notifies that tx power has been set.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Connection handle that identifying the link whose tx power has been set.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief Tx power that has been set(dBm).
+     */
+    int8_t curr_tx_pwr;
+} st_ble_vs_set_tx_pwr_comp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_get_tx_pwr_comp_evt_t
+ *  @brief  This structure notifies that tx power has been retrieved.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Connection handle that identifying the link whose tx power has been retrieved.
+     */
+    uint16_t conn_hdl;
+
+    /**
+     *  @brief Current tx power(dBm).
+     */
+    int8_t curr_tx_pwr;
+
+    /**
+     *  @brief Maximum tx power(dBm).
+     */
+    int8_t max_tx_pwr;
+} st_ble_vs_get_tx_pwr_comp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_set_rf_ctrl_comp_evt_t
+ *  @brief  This structure notifies that RF has been configured.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The result of RF power control.
+     */
+    uint8_t ctrl;
+} st_ble_vs_set_rf_ctrl_comp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_get_bd_addr_comp_evt_t
+ *  @brief  This structure notifies that BD_ADDR has been retrieved.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The area that public/random address has been retrieved.
+     *    |  value                              |   description       |
+     *    |:------------------------------------|:------------------- |
+     *    | BLE_VS_ADDR_AREA_REG(0x00)          | Register.           |
+     *    | BLE_VS_ADDR_AREA_DATA_FLASH(0x01)   | Data Flash.         |
+     */
+    uint8_t area;
+
+    /**
+     *  @brief The address that has been retrieved.
+     */
+    st_ble_dev_addr_t addr;
+} st_ble_vs_get_bd_addr_comp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_get_rand_comp_evt_t
+ *  @brief  This structure notifies that random number has been generated.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Length of random number.
+     */
+    uint8_t rand_size;
+
+    /**
+     *  @brief Random number.
+     */
+    uint8_t * p_rand;
+} st_ble_vs_get_rand_comp_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_tx_flow_chg_evt_t
+ *  @brief  This structure notifies that the state transition of TxFlow has been changed.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     * @brief The state of the flow control.
+     * |        value                 |   description                                                              |
+     * |:---------------------------- |:-------------------------------------------------------------------------- |
+     * | BLE_VS_TX_FLOW_CTL_ON(0x00)  | The number of buffer has reached the High Water Mark from flow off state.  |
+     * | BLE_VS_TX_FLOW_CTL_OFF(0x01) | The number of buffer has reached the Low Water Mark from flow on state.    |
+     */
+    uint8_t state;
+
+    /**
+     *  @brief The number of the current transmission buffers.
+     */
+    uint32_t buffer_num;
+} st_ble_vs_tx_flow_chg_evt_t;
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_vs_evt_data_t
+ *  @brief  st_ble_vs_evt_data_t is the type of the data notified in a Vendor Specific Event.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief The size of Vendor Specific Event parameters.
+     */
+    uint16_t param_len;
+
+    /**
+     *  @brief Vendor Specific Event parameters. This parameter differs in each Vendor Specific Event.
+     */
+    void * p_param;
+} st_ble_vs_evt_data_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_vs_app_cb_t
+ * @brief   ble_vs_app_cb_t is the Vendor Specific Event callback function type.
+ * @param[in] event_type    The type of Vendor Specific Event.
+ * @param[in] event_result  The result of API call which generates the Vendor Specific Event.
+ * @param[in] p_event_data  Data notified in the Vendor Specific Event.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_vs_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_vs_evt_data_t * p_event_data);
+
+/*@}*/
+
+/* =========================================== Vendor Specific Event Code =========================================== */
+
+/** @addtogroup VS_API
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup VS_API
+ * @enum e_r_ble_vs_evt_t
+ * @brief  Vendor Specific Event Identifier
+ **********************************************************************************************************************/
+typedef enum
+{
+    /**
+     *  @brief This event notifies that the tx power has been set by R_BLE_VS_SetTxPower().
+     *
+     * ## Event Code: 0x8001
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The tx_power parameter specified by R_BLE_VS_SetTxPower() is out of range.
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_SetTxPower() is not found.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_set_tx_pwr_comp_evt_t
+     */
+    BLE_VS_EVENT_SET_TX_POWER = 0x8001,
+
+    /**
+     *  @brief This event notifies that the tx power has been retrieved by R_BLE_VS_GetTxPower().
+     *
+     * ## Event Code: 0x8002
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_GetTxPower() is not found.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_get_tx_pwr_comp_evt_t
+     */
+    BLE_VS_EVENT_GET_TX_POWER = 0x8002,
+
+    /**
+     *  @brief This event notifies that the extended transmitter test has been started by R_BLE_VS_StartTxTest().
+     *
+     * ## Event Code: 0x8003
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartTxTest() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_TX_TEST_START = 0x8003,
+
+    /**
+     *  @brief This event notifies that the number specified by R_BLE_VS_StartTxTest() of packets has been sent.
+     *
+     * ## Event Code: 0x8004
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_TX_TEST_TERM = 0x8004,
+
+    /**
+     *  @brief This event notifies that the extended receiver test has been started by R_BLE_VS_StartRxTest().
+     *
+     * ## Event Code: 0x8005
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartRxTest() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_RX_TEST_START = 0x8005,
+
+    /**
+     *  @brief This event notifies that the extended test has been terminated by R_BLE_VS_EndTest().
+     *
+     * ## Event Code: 0x8006
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_test_end_evt_t
+     */
+    BLE_VS_EVENT_TEST_END = 0x8006,
+
+    /**
+     *  @brief This event notifies that the coding scheme has been configured by R_BLE_VS_SetCodingScheme().
+     *
+     * ## Event Code: 0x8007
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The coding_scheme parameter specified by R_BLE_VS_SetCodingScheme() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_SET_CODING_SCHEME_COMP = 0x8007,
+
+    /**
+     *  @brief This event notifies that the RF has been configured by R_BLE_VS_SetRfControl().
+     *
+     * ## Event Code: 0x8008
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_SetRfControl() is out of range.
BLE_ERR_INVALID_OPERATION(0x0009)During the power on or the power off, the same power state is specified
+     *                      by R_BLE_VS_SetRfControl().

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_set_rf_ctrl_comp_evt_t
+     */
+    BLE_VS_EVENT_RF_CONTROL_COMP = 0x8008,
+
+    /**
+     *  @brief This event notifies that public/random address has been set by R_BLE_VS_SetBdAddr().
+     *
+     * ## Event Code: 0x8009
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified
+     *                      by R_BLE_VS_SetBdAddr() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_SET_ADDR_COMP = 0x8009,
+
+    /**
+     *  @brief This event notifies that public/random address has been retrieved by R_BLE_VS_GetBdAddr().
+     *
+     * ## Event Code: 0x800A
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified
+     *                      by R_BLE_VS_GetBdAddr() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_get_bd_addr_comp_evt_t
+     */
+    BLE_VS_EVENT_GET_ADDR_COMP = 0x800A,
+
+    /**
+     *  @brief This event notifies the application layer that random number has been generated by R_BLE_VS_GetRand().
+     *
+     * ## Event Code: 0x800B
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 
BLE_ERR_INVALID_ARG(0x0003)The rand_size parameter specified by R_BLE_VS_GetRand() is out of range.

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_get_rand_comp_evt_t
+     */
+    BLE_VS_EVENT_GET_RAND = 0x800B,
+
+    /**
+     *  @brief This event notifies the application layer of the state transition of TxFlow.
+     *
+     * ## Event Code: 0x800C
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  st_ble_vs_tx_flow_chg_evt_t
+     */
+    BLE_VS_EVENT_TX_FLOW_STATE_CHG = 0x800C,
+
+    /**
+     *  @brief This event notifies a failure occurs in RF. After receiving the event, reset MCU or RF.
+     *
+     * ## Event Code: 0x800D
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  None
+     */
+    BLE_VS_EVENT_FAIL_DETECT = 0x800D,
+
+    /**
+     *  @brief  Invalid VS Event.
+     *
+     * ## Event Code: 0x80FF
+     *
+     *  ## result:
+     *  

+     *          
+     *              
+     *                  
+     *                  
+     *              
+     *          
BLE_SUCCESS(0x0000)Success 

+     *  

+     *
+     *  ## Event Data:
+     *  none
+     */
+    BLE_VS_EVENT_INVALID = 0x80FF
+} e_r_ble_vs_evt_t;
+
+/*@}*/
+
+/* ============================================= APP Callback Definition ============================================ */
+
+typedef void (* ble_app_init_cb_t)(uint8_t param);
+
+/* ============================================ Event Callback Definition =========================================== */
+
+/******************************************************************************************************************//**
+ * @ingroup BLE
+ * @typedef ble_event_cb_t
+ * @brief   ble_event_cb_t is the callback function type for R_BLE_SetEvent().
+ * @param[in] void
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_event_cb_t)(void);
+
+/* ============================================== MAIN API Declarations ============================================== */
+
+/** @addtogroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_Open(void)
+ * @brief   Open the BLE protocol stack.
+ * @details This function should be called once before using the BLE protocol stack.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ **********************************************************************************************************************/
+ble_status_t R_BLE_Open(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_Close(void)
+ * @brief   Close the BLE protocol stack.
+ * @details This function should be called once to close the BLE protocol stack.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ **********************************************************************************************************************/
+ble_status_t R_BLE_Close(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_Execute(void)
+ * @brief   Execute the BLE task.
+ * @details This  handles all the task queued in the BLE protocol stack internal task queue and return.
+ *          This function should be called repeatedly in the main loop.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ **********************************************************************************************************************/
+ble_status_t R_BLE_Execute(void);
+
+/******************************************************************************************************************//**
+ * @fn uint32_t R_BLE_IsTaskFree(void)
+ * @brief   Check the BLE task queue is free or not.
+ * @details This function returns the BLE task queue free status.
+ *          When this function returns 0x0, call R_BLE_Execute() to execute the BLE task.
+ * @retval  0x0 BLE task queue is not free
+ * @retval  0x1 BLE task queue is free
+ **********************************************************************************************************************/
+uint32_t R_BLE_IsTaskFree(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_SetEvent(ble_event_cb_t cb)
+ * @brief   Set event.
+ * @details This function add an event in the BLE protocol stack internal queue. The event is handled in R_BLE_Execute
+ *          just like Bluetooth event. This function is intended to be called in hardware interrupt context.
+ *          Even if calling this function with the same cb before the cb is invoked, only one event is registered.
+ *          The maximum number of the events can be registered at a time is eight.
+ * @param   cb The callback for the event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_ALREADY_IN_PROGRESS(0x000A) The event already registered with the callback.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) No free slot for the event.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_SetEvent(ble_event_cb_t cb);
+
+/******************************************************************************************************************//**
+ * @fn uint32_t R_BLE_GetVersion(void)
+ * @brief   Get the BLE FIT module version.
+ * @details This function returns the BLE FIT module version. \n
+ *          The major version(BLE_VERSION_MAJOR) is contained in the two most significant bytes,
+ *          and the minor version(BLE_VERSION_MINOR) occupies the remaining two bytes.
+ * @retval  "BLE_VERSION_MAJOR | BLE_VERSION_MINOR"
+ **********************************************************************************************************************/
+uint32_t R_BLE_GetVersion(void);
+
+/******************************************************************************************************************//**
+ * @fn uint32_t R_BLE_GetLibType(void)
+ * @brief   Get the type of BLE protocol stack library.
+ * @details This function returns the type of BLE protocol stack library.
+ * @retval  BLE_LIB_ALL_FEATS(0x00)  All Features
+ * @retval  BLE_LIB_BALANCE(0x01)    Balance
+ * @retval  BLE_LIB_COMPACT(0x02)    Compact
+ **********************************************************************************************************************/
+uint32_t R_BLE_GetLibType(void);
+
+/*@}*/
+
+/* ============================================== GAP API Declarations ============================================== */
+
+/** @defgroup GAP_API GAP
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup GAP_API
+ * @fn ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb)
+ * @brief   Initialize the Host Stack.
+ * @details Host stack is initialized with this function. Before using All the R_BLE APIs,
+ *          it's necessary to call this function. A callback function is registered with this function.
+ *          In order to receive the GAP event, it's necessary to register a callback function.
+ *          The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event.
+ * @param[in] gap_cb A callback function registered with this function.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) gap_cb is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *          - Host Stack was already initialized.
+ *          - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_Terminate(void)
+ * @brief   Terminate the Host Stack.
+ * @details Host stack is terminated with this function.
+ *          In order to reset all the Bluetooth functions, it's necessary to call this function.
+ *          The result of this API call is notified in BLE_GAP_EVENT_STACK_OFF event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) Host stack hasn't been initialized.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_Terminate(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_UpdConn(uint16_t conn_hdl,
+ *                                    uint8_t mode,
+ *                                    uint16_t accept,
+ *                                    st_ble_gap_conn_param_t * p_conn_updt_param
+ *                                   )
+ * @brief   Update the connection parameters.
+ * @details This function updates the connection parameters or replies a request for
+ *          updating connection parameters notified by BLE_GAP_EVENT_CONN_PARAM_UPD_REQ event.
+ *          When the connection parameters has been updated,
+ *          BLE_GAP_EVENT_CONN_PARAM_UPD_COMP event is notified to the application layer.
+ * @param[in]   conn_hdl Connection handle identifying the link to be updated.
+ * @param[in]   mode Connection parameter update request or response.
+ *               |              macro                     |           description                                |
+ *               |:-------------------------------------- |:---------------------------------------------------- |
+ *               | BLE_GAP_CONN_UPD_MODE_REQ (0x01)       | Request for updating the connection parameters.      |
+ *               | BLE_GAP_CONN_UPD_MODE_RSP (0x02)       | Reply a connection parameter update request.         |
+ *
+ * @param[in]   accept When mode is BLE_GAP_CONN_UPD_MODE_RSP,
+ *                     accept or reject the connection parameters update request.
+ *                     If mode is BLE_GAP_CONN_UPD_MODE_REQ, accept is ignored.
+ *               |              macro                     |           description             |
+ *               |:-------------------------------------- |:--------------------------------- |
+ *               | BLE_GAP_CONN_UPD_ACCEPT (0x0000)       | Accept the update request.        |
+ *               | BLE_GAP_CONN_UPD_REJECT (0x0001)       | Reject the update request.        |
+ *
+ * @param[in]   p_conn_updt_param Connection parameters to be updated.
+ *                                When mode is BLE_GAP_CONN_UPD_MODE_RSP and
+ *                                accept is BLE_GAP_CONN_UPD_REJECT, p_conn_updt_param is ignored.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) When accept is BLE_GAP_CONN_UPD_ACCEPT,
+ *                                      p_conn_updt_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following is out of range.
+ *                                      - mode
+ *                                      - accept
+ *                                      - conn_intv_min field in p_conn_updt_param
+ *                                      - conn_intv_max field in p_conn_updt_param
+ *                                      - conn_latency in p_conn_updt_param
+ *                                      - sup_to in p_conn_updt_param
+ *                                      - conn_hdl
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) Not connected with the remote device.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B)  Sending a L2CAP command, an error occurred.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_UpdConn(uint16_t                  conn_hdl,
+                               uint8_t                   mode,
+                               uint16_t                  accept,
+                               st_ble_gap_conn_param_t * p_conn_updt_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time)
+ * @brief   Update the packet size and the packet transmit time.
+ * @details This function requests for changing the maximum transmission packet size
+ *          and the maximum packet transmission time.
+ *          When Controller has received the request from host stack,
+ *          BLE_GAP_EVENT_SET_DATA_LEN_COMP event is notified to the application layer.
+ *          When the transmission packet size or the transmission time has been changed,
+ *          BLE_GAP_EVENT_DATA_LEN_CHG event is notified to the application layer.
+ * @param[in] conn_hdl  Connection handle identifying the link whose the transmission packet size or
+ *                      the transmission time to be changed.
+ * @param[in] tx_octets Maximum transmission packet size.
+ *                      Valid range is 0x001B - 0x00FB.
+ * @param[in] tx_time   Maximum transmission time(us).
+ *                     Valid range is 0x0148 - 0x4290.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason)
+ * @brief   Disconnect the link.
+ * @details This function disconnects a link.
+ *          When the link has disconnected, BLE_GAP_EVENT_DISCONN_IND event is notified to the application layer.
+ * @param[in]   conn_hdl Connection handle identifying the link to be disconnected.
+ * @param[in]   reason The reason for disconnection.
+ *                     Usually, set 0x13 which indicates that a user disconnects the link.
+ *                     If setting other than 0x13, refer the error code described
+ *                     in Core Specification Vol.2 Part D ,"2 Error Code Descriptions".
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param)
+ * @brief   Set the phy for connection.
+ * @details This function sets the PHY preferences for the connection.
+ *          The result of this API call is notified in BLE_GAP_EVENT_PHY_SET_COMP event.
+ *          When the PHY has been updated, BLE_GAP_EVENT_PHY_UPD event is notified to the application layer.
+ *
+ *          After PHY update, the PHY accept configuration of local device is the same as the values
+ *          in BLE_GAP_EVENT_PHY_UPD event. \n
+ *          For example, after calling R_BLE_GAP_SetPhy(), if tx_phy,
+ *          rx_phy by BLE_GAP_EVENT_PHY_UPD event are updated to 2M PHY,
+ *          the PHY accept configuration is 2M PHY only. \n
+ *          Therefore after receiving BLE_GAP_EVENT_PHY_UPD event, if local device wants to accept the other PHY
+ *          configuration, it needs to call R_BLE_GAP_SetPhy() with the desired PHY accept configuration.
+ *
+ *          Because the maximum transmission packet size or the maximum transmission time might be updated by
+ *          PHY update, if the same packet size or transmission time as the previous one is desired,
+ *          change the maximum transmission packet size or the maximum transmission time by @ref R_BLE_GAP_SetDataLen().
+ *
+ * @param[in] conn_hdl  Connection handle identifying the link whose PHY to be updated.
+ * @param[in] p_phy_param PHY preferences.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_phy_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) conn_hdl or option field in p_phy_param is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param)
+ * @brief   Set the default phy which allows remote device to change.
+ * @details This function sets the PHY preferences which a remote device may change.
+ *          The result of this API call is notified in BLE_GAP_EVENT_DEF_PHY_SET_COMP event.
+ * @param[in] p_def_phy_param  The PHY preference which a remote device may change.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_def_phy_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) tx_phys or tx_phys field in p_def_phy_param is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr,
+ *                                        uint8_t * p_privacy_mode,
+ *                                        uint8_t device_num
+ *                                       )
+ * @brief   Set the privacy mode.
+ * @details This function sets privacy mode for the remote device registered in Resolving List.
+ *          By default, Network Privacy Mode is set.\n
+ *          The result of this API call is notified in BLE_GAP_EVENT_PRIV_MODE_SET_COMP event.
+ * @param[in] p_addr  An array of identity address of the remote device to set privacy mode.
+ *                    The number of elements is specified by device_num.\n\n
+ * @param[in] p_privacy_mode  An array of privacy mode to set to remote device.
+ *            The number of elements is specified by device_num.\n
+ *            The following value is set as the privacy mode.
+ *               |              macro                     |           description             |
+ *               |:-------------------------------------- |:--------------------------------- |
+ *               | BLE_GAP_NET_PRIV_MODE (0x00)           | Network Privacy Mode.             |
+ *               | BLE_GAP_DEV_PRIV_MODE (0x01)           | Device Privacy Mode.              |
+ * @param[in] device_num  The number of devices to set privacy mode.
+ *                        Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_addr or p_privacy_mode is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range.
+ *                                       - The address type in p_addr.
+ *                                       - The privacy mode specified by p_privacy_mode.
+ *                                       - device_num
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                         - While configuring privacy mode, this function was called.
+ *                                         - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr, uint8_t * p_privacy_mode, uint8_t device_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num)
+ * @brief   Set White List.
+ * @details This function supports the following operations regarding White List.
+ *          - Add the device to White List.
+ *          - Delete the device from White List.
+ *          - Clear White List.
+ *
+ *           The total number of White List entries is defined as BLE_GAP_WHITE_LIST_MAX_ENTRY.
+ *           The result of this API call is notified in BLE_GAP_EVENT_WHITE_LIST_CONF_COMP event.
+ * @param[in]  op_code
+ *              The operation for  White List.
+ *               |              macro            |           description            |
+ *               |:----------------------------- |:-------------------------------- |
+ *               | BLE_GAP_LIST_ADD_DEV(0x01)    | Add the device to the list.      |
+ *               | BLE_GAP_LIST_REM_DEV(0x02)    | Delete the device from the list. |
+ *               | BLE_GAP_LIST_CLR(0x03)        | Clear the list.                  |
+ * @param[in]  p_addr An array of device address to add / delete to the list.
+ *                    The number of elements is specified by device_num.
+ *                    If op_code is BLE_GAP_LIST_CLR, p_addr is ignored.
+ * @param[in]  device_num The number of devices add / delete to the list.
+ *                        Valid range is 1-BLE_GAP_WHITE_LIST_MAX_ENTRY.
+ *                        If op_code is BLE_GAP_LIST_CLR, device_num is ignored.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV,
+ *                                      p_addr is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                        - While operating White List, this function was called.
+ *                                        - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the White List.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_GetVerInfo(void)
+ * @brief   Get the version number of the Controller and the host stack.
+ * @details This function retrieves the version information of local device.
+ *          The result of this API call is notified in BLE_GAP_EVENT_LOC_VER_INFO event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_GetVerInfo(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl)
+ * @brief   Get the phy settings.
+ * @details This function gets the PHY settings for the connection.
+ *          The result of this API call is notified in BLE_GAP_EVENT_PHY_RD_COMP event.
+ * @param[in] conn_hdl  Connection handle identifying the link whose PHY settings to be retrieved.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ConfRslvList(uint8_t op_code,
+ *                                         st_ble_dev_addr_t * p_addr,
+ *                                         st_ble_gap_rslv_list_key_set_t * p_peer_irk,
+ *                                         uint8_t device_num
+ *                                         )
+ * @brief   Set Resolving List.
+ * @details This function supports the following operations regarding Resolving List.
+ *          - Add the device to Resolving List.
+ *          - Delete the device from Resolving List.
+ *          - Clear Resolving List.
+ *
+ *           In order to generate a resolvable private address,
+ *           a local IRK needs to be registered by R_BLE_GAP_SetLocIdInfo().
+ *           If communicating with the identity address, register all-zero IRK as local IRK.
+ *           In order to resolve resolvable private address of the remote device,
+ *           the IRK distributed from the remote device needs to be added to Resolving List.
+ *           The total number of Resolving List entries is defined as BLE_GAP_RESOLV_LIST_MAX_ENTRY.
+ *           The result of this API call is notified in BLE_GAP_EVENT_RSLV_LIST_CONF_COMP event.
+ * @param[in]  op_code
+ *              The operation for Resolving List.
+ *               |              macro            |           description            |
+ *               |:----------------------------- |:-------------------------------- |
+ *               | BLE_GAP_LIST_ADD_DEV(0x01)    | Add the device to the list.      |
+ *               | BLE_GAP_LIST_REM_DEV(0x02)    | Delete the device from the list. |
+ *               | BLE_GAP_LIST_CLR(0x03)        | Clear the list.                  |
+ * @param[in]  p_addr An array of Identity Addresses to add / delete to the list.
+ *                    The number of elements is specified by device_num.
+ *                    If op_code is BLE_GAP_LIST_CLR, p_addr is ignored.
+ * @param[in]  p_peer_irk The remote IRK and the type of local IRK added to Resolving List.
+ *                        If op_code is other than BLE_GAP_LIST_ADD_DEV, p_peer_irk is ignored.
+ *                        The number of elements is specified by device_num.
+ * @param[in]  device_num The number of devices add / delete to the list.
+ *                        Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY.
+ *                        If op_code is BLE_GAP_LIST_CLR, device_num is ignored.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows:
+ *                                      - When added to or deleted from the list, p_addr is specified as NULL.
+ *                                      - When added to the list, p_peer_irk is specified as NULL.
+ *
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                                      - op_code is out of range.
+ *                                      - When op_code is BLE_GAP_LIST_ADD_DEV or
+ *                                        BLE_GAP_LIST_REM_DEV, device_num is out of range.
+ *                                      - When op_code is BLE_GAP_LIST_ADD_DEV or
+ *                                        BLE_GAP_LIST_REM_DEV, address type field in p_addr is out of range.
+ *
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                        - While operating Resolving List, this function was called.
+ *                                        - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the Resolving List.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The specified Identity Address was not found in Resolving List.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ConfRslvList(uint8_t                          op_code,
+                                    st_ble_dev_addr_t              * p_addr,
+                                    st_ble_gap_rslv_list_key_set_t * p_peer_irk,
+                                    uint8_t                          device_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable)
+ * @brief   Enable/Disable address resolution and generation of a resolvable private address.
+ * @details This function enables or disables RPA functionality. The RPA functionality includes the following.
+ *          - Generation of local resolvable private address
+ *          - Resolution of remote resolvable private address
+ *
+ *          In order to do advertising, scanning or creating a link with local resolvable private address,
+ *          the RPA functionality needs to be enabled.
+ *          After enabling the RPA functionality and the identity address of remote device and
+ *          the IRKs of local/remote device is registered,
+ *          local device can generate own resolvable private address in the time interval set by R_BLE_GAP_SetRpaTo(),
+ *          and can resolve a resolvable private address of a remote device.
+ *          It is recommended that the RPA functionality is called immediately
+ *          after the initialization by R_BLE_GAP_Init().
+ *          The result of this API call is notified in BLE_GAP_EVENT_RPA_EN_COMP event.
+ * @param[in] enable  Enable or disable address resolution function.
+ *               |              macro              |           description                     |
+ *               |:------------------------------- |:----------------------------------------- |
+ *               | BLE_GAP_RPA_DISABLED(0x00)      | Disable RPA generation/resolution.        |
+ *               | BLE_GAP_RPA_ENABLED(0x01)       | Enable RPA generation/resolution.         |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) enable is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout)
+ * @brief   Set the update time of resolvable private address.
+ * @details This function sets the time interval to update the resolvable private address.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SET_RPA_TO_COMP event.
+ * @param[in] rpa_timeout  Time interval to update resolvable private address in seconds.
+ *                         Valid range is 0x003C - 0xA1B8.
+ *                         Default is 900s.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr)
+ * @brief   Get the resolvable private address of local device.
+ * @details This function retrieves the local resolvable private address.
+ *          Before getting the address, enable the resolvable private address function by R_BLE_GAP_EnableRpa().
+ *          The result of this API call is notified in BLE_GAP_EVENT_RD_RPA_COMP event.
+ * @param[in] p_addr  Identity address registered in Resolving List.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) Address type in p_addr is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows.
+ *                                        - When retrieving the local resolvable private address,
+ *                                          this function was called.
+ *                                        - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl)
+ * @brief   Get RSSI.
+ * @details This function retrieves RSSI.
+ *          The result of this API call is notified in BLE_GAP_EVENT_RSSI_RD_COMP event.
+ * @param[in] conn_hdl  Connection handle identifying the link whose RSSI to be retrieved.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl)
+ * @brief   Get the Channel Map.
+ * @details This function retrieves the channel map.
+ *          The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_RD_COMP event.
+ * @param[in] conn_hdl  Connection handle identifying the link whose channel map to be retrieved.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr)
+ * @brief   Set a random address.
+ * @details This function sets static address or non-resolvable private address to Controller.
+ *          Refer to Core Specification Vol 6, PartB,
+ *          "1.3.2 Random Device Address" regarding the format of the random address.
+ *          Resolvable private address cannot set by this API.
+ *          The result of this API call is notified in BLE_GAP_EVENT_RAND_ADDR_SET_COMP event.
+ * @param[in] p_random_addr  Static address or non-resolvable private address. \n
+ *                           The BD address setting format is little endian.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_random_addr is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param)
+ * @brief   Set advertising parameters.
+ * @details This function sets advertising parameters.
+ *          It's possible to do advertising where the advertising parameters are different every each advertising set.
+ *          The number of advertising set in the Controller is defined as BLE_MAX_NO_OF_ADV_SETS_SUPPORTED.
+ *          Each advertising set is identified with advertising handle (0x00-0x03).
+ *          Create an advertising set with this function before start advertising,
+ *          setting periodic advertising parameters, start periodic advertising,
+ *          setting advertising data/scan response data/periodic advertising data.
+ *          The result of this API call is notified in BLE_GAP_EVENT_ADV_PARAM_SET_COMP event.
+ * @param[in]   p_adv_param Advertising parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_adv_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The below p_adv_param field value is out of range.
+ *          - adv_handle
+ *          - adv_intv_min/adv_intv_max
+ *          - adv_ch_map
+ *          - o_addr_type
+ *          - p_addr_type
+ *          - adv_phy
+ *          - sec_adv_phy
+ *          - scan_req_ntf_flag
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data)
+ * @brief   Set advertising data/scan response data/periodic advertising data.
+ * @details This function sets advertising data/scan response data/periodic advertising data to the advertising set.
+ *          It is necessary to create an advertising set by R_BLE_GAP_SetAdvParam(), before calling this function.
+ *          Set advertising data/scan response data/periodic advertising data, after allocating the memory for the data.
+ *          The following shall be applied regarding the adv_prop_type field and the data_type field in
+ *          st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam().
+ *
+ *          The following shall be applied regarding the adv_prop_type field and the data_type field in
+ *          st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam().
+ *          - When adv_prop_type is Legacy Advertising PDU type,
+ *            - it's possible to set advertising data/scan response data up to 31 bytes.
+ *            - advertising data/scan response data can be updated by this function in advertising.
+ *          - When adv_prop_type is Extended Advertising PDU type,
+ *            - it's possible to set at most 1650 bytes of data as advertising data/scan response data
+ *              per 1 advertising set.
+ *            - the total buffer size in Controller for advertising data/scan response data is 4250 bytes.
+ *              Therefore please note that more than 4250 bytes of advertising data/scan response data
+ *              can not be set to all the advertising sets.
+ *              Please refer to Figure 1.1 and Figure 1.2 about examples of setting advertising data/scan response data.
+ *            - it's possible to update advertising data/scan response data in advertising,
+ *              if the data_length field in st_ble_gap_adv_data_t parameter is up to 251 bytes.
+ *              @image html "adv_data_alloc_fail_en.svg" "Figure 1.1" width=700px
+ *              @image html "adv_data_alloc_success_en.svg" "Figure 1.2" width=700px
+ *          - When periodic advertising data is set,
+ *            - At most 1650 bytes of data can be set to 1 advertising set.
+ *            - The total buffer size in Controller for periodic advertising data is 4306 bytes.
+ *              Therefore please note that more than 4306 bytes of periodic advertising data can not be
+ *              set to all the advertising sets.
+ *            - it's possible to update periodic advertising data in advertising,
+ *              if the data_length field in st_ble_gap_adv_data_t parameter is up to 252 bytes.
+ *
+ *         The result of this API call is notified in @ref BLE_GAP_EVENT_ADV_DATA_UPD_COMP event.
+ *
+ * @param[in]   p_adv_srsp_data   Advertising data/scan response data/periodic advertising data.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows:
+ *          - p_adv_srsp_data is specified as NULL.
+ *          - data_length field in p_adv_srsp_data parameter is not 0 and p_data field is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following field in p_adv_srsp_data parameter is out of range.
+ *          - adv_hdl
+ *          - data_type
+ *          - data_length
+ *          - zero_length_flag
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts)
+ * @brief   Start advertising.
+ * @details This function starts advertising.
+ *          Create the advertising set specified with adv_hdl by R_BLE_GAP_SetAdvParam(),
+ *          before calling this function.
+ *          The result of this API call is notified in BLE_GAP_EVENT_ADV_ON event.
+ * @param[in]   adv_hdl
+ *              The advertising handle pointing to the advertising set which starts advertising.
+ *              The valid range is 0x00 - 0x03.
+ * @param[in]   duration
+ *              The duration for which the advertising set identified by adv_hdl is enabled.
+ *              Time = duration * 10ms.
+ *              When the duration expires, BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped.
+ *              The valid range is 0x0000 - 0xFFFF.
+ *              The duration parameter is ignored when the value is set to 0x0000.
+ * @param[in]   max_extd_adv_evts
+ *              The maximum number of advertising events that be sent during advertising.
+ *              When all the advertising events(max_extd_adv_evts) have been sent,
+ *              BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped.
+ *              The max_extd_adv_evts parameter is ignored when the value is set to 0x00.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl)
+ * @brief   Stop advertising.
+ * @details This function stops advertising. The result of this API call is notified in BLE_GAP_EVENT_ADV_OFF event.
+ * @param[in]   adv_hdl
+ *              The advertising handle pointing to the advertising set which stops advertising.
+ *              The valid range is 0x00 - 0x03.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param)
+ * @brief   Set periodic advertising parameters.
+ * @details This function sets periodic advertising parameters.
+ *          Create the advertising set which supports Non-Connectable,
+ *          Non-Scannable advertising by R_BLE_GAP_SetAdvParam() before setting periodic advertising parameters.
+ *          The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP event.
+ * @param[in]  p_perd_adv_param  Periodic advertising parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_perd_adv_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following field in the p_perd_adv_param parameter is out of range.
+ *          - adv_hdl
+ *          - perd_intv_min or perd_intv_max
+ *          - prop_type is neither 0x0000 nor 0x0040(BLE_GAP_PERD_PROP_TX_POWER)
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl)
+ * @brief   Start periodic advertising.
+ * @details This function starts periodic advertising.
+ *          Set periodic advertising parameters to the advertising set, before starting periodic advertising.
+ *          The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_ON event.
+ * @param[in]  adv_hdl   Advertising handle identifying the advertising set which starts periodic advertising.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl)
+ * @brief   Stop periodic advertising.
+ * @details This function stops periodic advertising.
+ *          If the return value of this API is BLE_SUCCESS, the result is notified in BLE_GAP_EVENT_PERD_ADV_OFF event.
+ * @param[in]  adv_hdl   Specify the handle of Advertising Set to stop Periodic Advertising.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size,
+ *                                                uint16_t * p_remain_perd_adv_data_size
+ *                                               )
+ * @brief   Get buffer size for advertising data/scan response data/periodic advertising data in the Controller.
+ * @details This function gets the total size of advertising data/scan response data/periodic advertising data
+ *          which can be currently set to Controller(all of the advertising sets).
+ *          The application layer gets the data sizes via the parameters.
+ *          By this API function call, no events occur.
+ * @param[out]  p_remain_adv_data_size
+ *              The free buffer size of Controller to which advertising data/scan response data can be currently set.
+ * @param[out]  p_remain_perd_adv_data_size
+ *              The free buffer size of Controller to which periodic advertising data can be currently set.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_remain_adv_data_size or p_remain_perd_adv_data_size is specified as NULL.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size, uint16_t * p_remain_perd_adv_data_size);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl)
+ * @brief   Delete advertising set.
+ * @details This function deletes an advertising set or deletes all the advertising sets.
+ *          The result of this API call is notified in BLE_GAP_EVENT_ADV_SET_REMOVE_COMP event.
+ * @param[in]  op_code The operation for delete or clear.
+ *               |              macro               |           description            |
+ *               |:-------------------------------- |:-------------------------------- |
+ *               | BLE_GAP_RMV_ADV_SET_REM_OP(0x01) | Delete an advertising set.       |
+ *               | BLE_GAP_RMV_ADV_SET_CLR_OP(0x02) | Delete all the advertising sets. |
+ * @param[in]  adv_hdl
+ *             Advertising handle identifying the advertising set deleted.
+ *             If op_code is BLE_GAP_RMV_ADV_SET_CLR_OP, adv_hdl is ignored.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                                      - op_code is out of range.
+ *                                      - When op_code is BLE_GAP_RMV_ADV_SET_REM_OP(0x01), adv_hdl is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param)
+ * @brief   Request for a link establishment.
+ * @details This function sends a connection request to a remote device to create a link.
+ *          When Controller has received a request for establishment of a link from host stack,
+ *          BLE_GAP_EVENT_CREATE_CONN_COMP event is notified to the application layer.
+ *          When the link is established, BLE_GAP_EVENT_CONN_IND event is notified to the application layer.
+ * @param[in] p_param Connection parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows:
+ *                                      - p_param is specified as NULL.
+ *                                      - p_conn_param_1M field and p_conn_param_2M and
+ *                                        p_conn_param_coded field in p_param are specified as NULL.
+ *                                      - When creating a link with 1M PHY, p_conn_param
+ *                                        in p_conn_param_1M field in p_param is specified as NULL.
+ *                                      - When creating a link with 2M PHY,
+ *                                        p_conn_param in p_conn_param_2M field in p_param is specified as NULL.
+ *                                      - When creating a link with coded MPHY,
+ *                                        p_conn_param in p_conn_param_coded field in p_param is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                                      - init_filter_policy in p_param is out of range.
+ *                                      - remote_bd_addr_type field or own_addr_type address field
+ *                                        in p_param is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_CancelCreateConn(void)
+ * @brief   Cancel the request for a link establishment.
+ * @details This function cancels a request for establishing a link.
+ *          When Controller has received the cancel request from host stack,
+ *          BLE_GAP_EVENT_CONN_CANCEL_COMP event is notified to the application layer.
+ *          When the cancel procedure has completed,
+ *          BLE_GAP_EVENT_CONN_IND event is notified to the application layer.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_CancelCreateConn(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map)
+ * @brief   Set the Channel Map.
+ * @details This function sets the channel map.
+ *          The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_SET_COMP event.
+ * @param[in] p_channel_map  Channel map.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_channel_map is specified as NULL.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param,
+ *                                      st_ble_gap_scan_on_t * p_scan_enable
+ *                                     )
+ * @brief   Set scan parameter and start scan.
+ * @details This function starts scanning.
+ *          When scanning for the first time, set the p_scan_param.
+ *          Setting scan parameters can be omitted by specifying p_scan_param as NULL after next time.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SCAN_ON event.
+ *          Advertising report is notified in BLE_GAP_EVENT_ADV_REPT_IND event.
+ *          Figure 1.3 shows the relationship between scan period, scan duration, scan interval and scan window.
+ *          @image html "scan_period_en.svg" "Figure 1.3"
+ *
+ *          When scan duration is non-zero, scan period is zero and scan duration expires,
+ *          BLE_GAP_EVENT_SCAN_TO event is notified to the application layer.
+ * @param[in]  p_scan_param
+ *              Scan parameter.
+ *              When p_scan_param is specified as NULL,
+ *              host stack doesn't set scan parameters and start scanning with the previous parameters.
+ * @param[in]  p_scan_enable
+ *             Scan period, scan duration, duplicate filter and procedure type.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows:
+ *                                      - p_scan_enable is specified as NULL.
+ *                                      - p_phy_param_1M field and p_phy_param_coded field in
+ *                                        p_scan_param are specified as NULL.
+ *
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                                      - proc_type field in p_scan_enable is out of range.
+ *                                      - filter_dups in p_scan_enable is out of range.
+ *                                      - o_addr_type in p_scan_param is out of range.
+ *                                      - filter_policy in p_scan_param is out of range.
+ *                                      - scan_type of p_scan_param's p_phy_param_1M or p_phy_param_coded is out of range.
+ *
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param, st_ble_gap_scan_on_t * p_scan_enable);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StopScan(void)
+ * @brief   Stop scan.
+ * @details This function stops scanning.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SCAN_OFF event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StopScan(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr,
+ *                                       uint8_t adv_sid,
+ *                                       uint16_t skip,
+ *                                       uint16_t sync_to
+ *                                      )
+ * @brief   Request for a periodic sync establishment.
+ * @details This function sends a request for establishment of a periodic sync to a advertiser.
+ *          In order to create a periodic sync, scan needs to be starting by R_BLE_GAP_StartScan().
+ *          When Controller has received the request from host stack,
+ *          BLE_GAP_EVENT_CREATE_SYNC_COMP event is notified to the application layer.
+ *          When the periodic sync is established, BLE_GAP_EVENT_SYNC_EST event is notified to the application layer.
+ * @param[in]  p_addr
+ *             The address of periodic advertiser.When p_addr is specified as NULL,
+ *             local device creates a periodic sync with the advertiser registered in Periodic Advertiser List.
+ * @param[in]  adv_sid
+ *             Advertising SID. When p_addr is specified as NULL, adv_sid is ignored.
+ *             Valid range is 0x00 - 0x0F.
+ * @param[in]  skip
+ *             The number of consecutive periodic advertising packets
+ *             that local device may skip after receiving a periodic advertising packet.
+ *             Valid range is 0x0000 - 0x01F3.
+ * @param[in]  sync_to
+ *             The maximum permitted time between successful receives.When sync_to expires,
+ *             the periodic sync is lost.
+ *             Time(ms) = sync_to * 10.
+ *             Valid range is 0x000A - 0x4000.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range.
+ *                                      - address type in p_addr
+ *                                      - adv_sid
+ *                                      - skip
+ *                                      - sync_to
+ *
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr, uint8_t adv_sid, uint16_t skip, uint16_t sync_to);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_CancelCreateSync(void)
+ * @brief   Cancel the request for a periodic sync establishment.
+ * @details This function cancels a request for establishing a periodic sync.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_CancelCreateSync(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl)
+ * @brief   Terminate the periodic sync.
+ * @details This function terminates a periodic sync.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SYNC_TERM event.
+ * @param[in]  sync_hdl Sync handle identifying the periodic sync to be terminated.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) sync_hdl is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t op_code,
+ *                                            st_ble_dev_addr_t * p_addr,
+ *                                            uint8_t * p_adv_sid_set,
+ *                                            uint8_t device_num
+ *                                           )
+ * @brief   Set Periodic Advertiser List.
+ * @details This function supports the following operations regarding Periodic Advertiser List.
+ *          - Add the device to Periodic Advertiser List.
+ *          - Delete the device from Periodic Advertiser List.
+ *          - Clear Periodic Advertiser List.
+ *
+ *           The total number of Periodic Advertiser List entries is defined as BLE_GAP_PERD_LIST_MAX_ENTRY.
+ *           The result of this API call is notified in BLE_GAP_EVENT_PERD_LIST_CONF_COMP event.
+ * @param[in]  op_code
+ *              The operation for Periodic Advertiser List.
+ *               |              macro            |           description            |
+ *               |:----------------------------- |:-------------------------------- |
+ *               | BLE_GAP_LIST_ADD_DEV(0x01)    | Add the device to the list.      |
+ *               | BLE_GAP_LIST_REM_DEV(0x02)    | Delete the device from the list. |
+ *               | BLE_GAP_LIST_CLR(0x03)        | Clear the list.                  |
+ * @param[in]  p_addr An array of device address to add / delete to the list.
+ *                    The number of elements is specified by device_num.
+ *                    If op_code is BLE_GAP_LIST_CLR, p_addr is ignored.
+ * @param[in]  p_adv_sid_set An array of SID of the advertiser to add / delete to the list.
+ *                           The number of elements is specified by device_num.
+ *                           If op_code is BLE_GAP_LIST_CLR, p_adv_sid_set is ignored.
+ * @param[in]  device_num The number of devices add / delete to the list.
+ *                        Valid range is 1-BLE_GAP_PERD_LIST_MAX_ENTRY.
+ *                        If op_code is BLE_GAP_LIST_CLR, device_num is ignored.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV,
+ *                                      p_addr or p_adv_sid_set is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr or p_adv_sid_set or
+ *                                      device_num is out of range.
+ * @retval  BLE_ERR_UNSUPPORTED(0x0007) Not supported.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                        - While operating Periodic Advertiser List, this function was called.
+ *                                        - The task for host stack is not running.
+ *
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating periodic advertiser.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t             op_code,
+                                       st_ble_dev_addr_t * p_addr,
+                                       uint8_t           * p_adv_sid_set,
+                                       uint8_t             device_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag)
+ * @brief   Authorize a remote device.
+ * @details User authorizes a remote device by this function.
+ *          This function is used when a remote device accesses a GATT Characteristic
+ *          in local device which requests user authorization.
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl  Connection handle identifying the remote device to be authorized or not by user.
+ * @param[in] author_flag  Authorize or not the remote device.
+ *               |              macro            |           description            |
+ *               |:----------------------------- |:-------------------------------- |
+ *               | BLE_GAP_NOT_AUTHORIZED(0x00)  | Not authorize the remote device. |
+ *               | BLE_GAP_AUTHORIZED(0x01)      | Authorize the remote device.     |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) author_flag is out of range.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl)
+ * @brief   Get the information about remote device.
+ * @details This function retrieves information about the remote device.
+ *          The information includes BD_ADDR, the version number and LE features.
+ *          The result of this API call is notified in BLE_GAP_EVENT_GET_REM_DEV_INFO event.
+ * @param[in] conn_hdl  Connection handle identifying the remote device whose information to be retrieved.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param)
+ * @brief   Set the parameters using pairing.
+ * @details This function sets the parameters used in pairing.
+ *          The parameters set by this API are sent to the remote device when pairing occurred.
+ *          The result of this API call is returned by a return value.
+ * @param[in] p_pair_param    Pairing parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The following field in p_pair_param is out of range.
+ *                                      - iocap
+ *                                      - max_key_size
+ *                                      - mitm
+ *                                      - bonding
+ *                                      - key_notf
+ *                                      - sec_conn_only
+ *
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk)
+ * @brief   Set the IRK and the identity address distributed to a remote device.
+ * @details This function registers local IRK and identity address of local device in host stack.
+ *          The IRK and the identity address are distributed to a remote device in pairing.
+ *          The result of this API call is returned by a return value.
+ * @param[in] p_lc_id_addr  Identity address to be registered in host stack.
+ * @param[in] p_lc_irk  IRK to be registered in host stack.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_lc_id_addr or p_lc_irk is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) Address type field in p_lc_id_addr is out of range.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk)
+ * @brief   Set the CSRK distributed to a remote device.
+ * @details This function registers local CSRK in host stack.
+ *          The CSRK is distributed to a remote device in pairing.
+ *          The result of this API call is returned by a return value.
+ * @param[in] p_local_csrk    CSRK to be registered in host stack.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_local_csrk is specified as NULL.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl)
+ * @brief   Start pairing.
+ * @details This function starts pairing with a remote device.
+ *          The result of this API call is returned by a return value.
+ *          The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event.
+ * @param[in] conn_hdl    Connection handle identifying the remote device which local device starts pairing with.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) While pairing, this function was called.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response)
+ * @brief   Reply the pairing request from a remote device.
+ * @details This function replies to the pairing request from the remote device.
+ *          The pairing request from the remote device is notified in BLE_GAP_EVENT_PAIRING_REQ event.
+ *          The result of this API call is returned by a return value.
+ *          The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event.
+ * @param[in] conn_hdl    Connection handle identifying the remote device which local device starts pairing with.
+ * @param[in] response    Accept or reject the pairing request from the remote device.
+ *               |              macro            |           description            |
+ *               |:----------------------------- |:-------------------------------- |
+ *               | BLE_GAP_PAIRING_ACCEPT(0x00)  | Accept the pairing request.      |
+ *               | BLE_GAP_PAIRING_REJECT(0x01)  | Reject the pairing request.      |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) response is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) When this function was called,
+ *                                        host stack has not yet received BLE_GAP_EVENT_PAIRING_REQ event.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl)
+ * @brief   Encryption the link.
+ * @details This function starts encryption of the link.
+ *          In case of master device, the local device requests for the encryption to a remote device.
+ *          In case of slave device, the local device sends a Security Request to a remote device.
+ *          After receiving the Security Request, the remote device requests for the encryption to the local device.
+ *          The result of the encryption is returned in BLE_GAP_EVENT_ENC_CHG event.
+ * @param[in] conn_hdl  Connection handle identifying the link which is encrypted.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                        - Pairing has not been completed.
+ *                                        - The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response)
+ * @brief   Reply the passkey entry request.
+ * @details When BLE_GAP_EVENT_PASSKEY_ENTRY_REQ event is notified,
+ *          the response to passkey entry is sent by this function.
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl    Connection handle identifying the remote device which the reply to passkey entry is sent.
+ * @param[in] passkey     Passkey.
+ *                        The valid range is 000000 - 999999 in decimal.
+ * @param[in] response    Active or negative reply to passkey entry.
+ *               |              macro            |           description              |
+ *               |:----------------------------- |:---------------------------------- |
+ *               | BLE_GAP_PAIRING_ACCEPT(0x00)  | Accept the passkey entry pairing.  |
+ *               | BLE_GAP_PAIRING_REJECT(0x01)  | Reject the passkey entry pairing.  |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) passkey or response is out of range.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response)
+ * @brief   Reply the numeric comparison request.
+ * @details When BLE_GAP_EVENT_NUM_COMP_REQ event is notified,
+ *          the response to Numeric Comparison is sent by this function.
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl  Connection handle identifying the remote device which the reply to Numeric Comparison is sent.
+ * @param[in] response  Active or negative reply in Numeric Comparison.
+ *            |              macro         |           description                                                   |
+ *            |:-------------------------- |:----------------------------------------------------------------------- |
+ *            |BLE_GAP_PAIRING_ACCEPT(0x00)| The number displayed in the local is the same as the one of the remote. |
+ *            |BLE_GAP_PAIRING_REJECT(0x01)| The number displayed in the local is differs from the one of the remote.|
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) response is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) When this function was called,
+ *                                        host stack has not yet received @ref BLE_GAP_EVENT_NUM_COMP_REQ event.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press)
+ * @brief   Notify the input key type which a remote device inputs in the passkey entry.
+ * @details This function notifies the input key type to the remote device in passkey entry.
+ *          The result is returned from this API.
+ * @param[in] conn_hdl  Connection handle identifying the remote device to which the key notification is sent.
+ * @param[in] key_press Input key type.
+ *               |              macro                         |           description                 |
+ *               |:------------------------------------------ |:------------------------------------- |
+ *               | BLE_GAP_LESC_PASSKEY_ENTRY_STARTED(0x00)   | Notify that passkey entry started.    |
+ *               | BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED(0x01)   | Notify that passkey digit entered.    |
+ *               | BLE_GAP_LESC_PASSKEY_DIGIT_ERASED(0x02)    | Notify that passkey digit erased.     |
+ *               | BLE_GAP_LESC_PASSKEY_CLEARED(0x03)         | Notify that passkey cleared.          |
+ *               | BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED(0x04) | Notify that passkey entry completed.  |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) key_press parameter is out of range.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info)
+ * @brief   Get the security information about the remote device.
+ * @details This function gets the parameters which has been negotiated with the remote device in pairing.
+ *          The parameters can be retrieved after pairing.
+ *          The result is returned by p_sec_info.
+ * @param[in] conn_hdl  Connection handle identifying the remote device whose bonding information is retrieved.
+ * @param[in] p_sec_info  Return the security information which has been negotiated in pairing.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_sec_info is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The remote device bonding information has not been set to host stack.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl)
+ * @brief   Distribute the keys of local device.
+ * @details When key exchange request is notified by BLE_GAP_EVENT_EX_KEY_REQ event at pairing,
+ *          keys of the local device are distributed.
+ *          The result is returned from this API.
+ * @param[in] conn_hdl  Connection handle identifying the remote device to which the key is distributed.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetRemOobData( st_ble_dev_addr_t * p_addr,
+ *                                           uint8_t oob_data_flag,
+ *                                           st_ble_gap_oob_data_t * p_oob
+ *                                         )
+ * @brief   Set the oob data from a remote device.
+ * @details This function registers the OOB data received from a remote device.
+ *          When oob_data_flag indicates that the OOB data has been received,
+ *          the setting regarding OOB data is reflected in pairing.
+ *          In order to do OOB pairing, set the OOB data received from the remote device before pairing.
+ *          The result is returned from this API.
+ * @param[in] p_addr The remote device address.
+ * @param[in] oob_data_flag This parameter indicates whether the local device has received the OOB data
+ *                          from the remote device or not.
+ *               |              macro                |           description                                   |
+ *               |:--------------------------------- |:------------------------------------------------------- |
+ *               | BLE_GAP_OOB_DATA_NOT_PRESENT(0x00)| Reply that No OOB data has been received when pairing.  |
+ *               | BLE_GAP_OOB_DATA_PRESENT(0x01)    | Reply that the OOB data has been received when pairing. |
+ * @param[in] p_oob The OOB data received from the remote device.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows.
+ *                                      - p_addr is specified as NULL.
+ *                                      - oob_data_flag is BLE_GAP_OOB_DATA_PRESENT and p_oob is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) oob_data_flag is out of range.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) There is no room to register the OOB data received from a remote device.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetRemOobData(st_ble_dev_addr_t * p_addr, uint8_t oob_data_flag, st_ble_gap_oob_data_t * p_oob);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_CreateScOobData(void)
+ * @brief   Create data for oob in secure connection.
+ * @details This function generates the OOB data distributed to a remote device in Secure Connections.
+ *          The result of this API call is notified in BLE_GAP_EVENT_SC_OOB_CREATE_COMP event.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows:
+ *                                        - This function was called in pairing.
+ *                                        - The task for host stack is not running.
+ * @retval  BLE_ERR_ALREADY_IN_PROGRESS(0x000A) This function was called in creating OOB data.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_CreateScOobData(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info,
+ *                                        uint8_t device_num,
+ *                                        uint8_t * p_set_num
+ *                                       )
+ * @brief   Set the bonding information stored in non-volatile memory to the host stack.
+ * @details Set the bonding information of the remote device in the host stack.
+ *          After power re-supply, when the remote device bonding information stored in non-volatile memory is
+ *          set to host stack, this function is used.
+ *          Host stack can be set the number specified by the device_num parameter of bonding information.
+ * @param[in] p_bond_info An array of bonding information. The number of elements is specified by device_num.
+ * @param[in] device_num  The number of the devices of which host stack registers bonding information.
+ * @param[in] p_set_num   The number of the devices whose bonding information was registered in host stack.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_bond_info or p_set_num is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) device_num is out of range.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) Host stack already has the maximum number of bonding information.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info, uint8_t device_num, uint8_t * p_set_num);
+
+/******************************************************************************************************************//**
+ * @fn void R_BLE_GAP_DeleteBondInfo(int32_t local,
+ *                                        int32_t remote,
+ *                                        st_ble_dev_addr_t * p_addr,
+ *                                        ble_gap_del_bond_cb_t gap_del_bond_cb)
+ * @brief This function deletes the bonding information in Host Stack.\n
+ *          When a function for deleting the bonding information stored in non-volatile area is registered by the
+ *          gap_del_bond_cb parameter, it is deleted as well as the bonding information in Host Stack.
+ *
+ * @param[in] local The type of the local bonding information to be deleted.
+ *               |              macro                |           description                                   |
+ *               |:--------------------------------- |:------------------------------------------------------- |
+ *               | BLE_GAP_SEC_DEL_LOC_NONE(0x00)    | Delete no local keys.                                   |
+ *               | BLE_GAP_SEC_DEL_LOC_IRK(0x01)     | Delete local IRK and identity address.                  |
+ *               | BLE_GAP_SEC_DEL_LOC_CSRK(0x02)    | Delete local CSRK.                                      |
+ *               | BLE_GAP_SEC_DEL_LOC_ALL(0x03)     | Delete all local keys.                                  |
+ * @param[in] remote The type of the remote bonding information to be deleted.
+ *               |              macro                |           description                                   |
+ *               |:--------------------------------- |:------------------------------------------------------- |
+ *               | BLE_GAP_SEC_DEL_REM_NONE(0x00)    | Delete no remote device keys.                           |
+ *               | BLE_GAP_SEC_DEL_REM_SA(0x01)      | Delete the keys specified by the p_addr parameter.      |
+ *               | BLE_GAP_SEC_DEL_REM_NOT_CONN(0x02)| Delete keys of not connected remote devices.            |
+ *               | BLE_GAP_SEC_DEL_REM_ALL(0x03)     | Delete all remote device keys.                          |
+ *               \n\n
+ * @param[in] p_addr p_addr is specified as the address of the remote device whose keys are deleted
+ *                   when the rem_info parameter is set to @ref BLE_GAP_SEC_DEL_REM_SA(0x01).
+ *                   \n\n
+ * @param[in] gap_del_bond_cb This parameter is a callback function which deletes the bonding information stored
+ *                            in non-volatile area. \n After deleting the bonding information stored in Host Stack,
+ *                            the callback function is called. If no bonding information is stored in
+ *                            non-volatile area, specify the parameter as NULL.
+ * @retval  none
+ **********************************************************************************************************************/
+void R_BLE_GAP_DeleteBondInfo(int32_t               local,
+                              int32_t               remote,
+                              st_ble_dev_addr_t   * p_addr,
+                              ble_gap_del_bond_cb_t gap_del_bond_cb);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl,
+ *                                        uint16_t ediv,
+ *                                        uint8_t * p_peer_rand,
+ *                                        uint8_t response
+ *                                       )
+ * @brief   Reply the LTK request from a remote device.
+ * @details This function replies to the LTK request in BLE_GAP_EVENT_LTK_REQ event from a remote device.
+ *          The result of the LTK reply is returned in BLE_GAP_EVENT_LTK_RSP_COMP event.
+ *          When the link encryption has completed, BLE_GAP_EVENT_ENC_CHG event is notified.
+ * @param[in] conn_hdl  Connection handle identifying the remote device which sent the LTK request.
+ * @param[in] ediv  Ediv notified in BLE_GAP_EVENT_LTK_REQ event.
+ * @param[in] p_peer_rand  Rand notified in BLE_GAP_EVENT_LTK_REQ event.
+ * @param[in] response  Response to the LTK request.
+ *                      If "BLE_GAP_LTK_REQ_ACCEPT" is specified,
+ *                      when no LTK has been exchanged in pairing, reject the LTK request.
+ *                      |              macro            |           description              |
+ *                      |:----------------------------- |:---------------------------------- |
+ *                      | BLE_GAP_LTK_REQ_ACCEPT(0x00)  | Reply for the LTK request.         |
+ *                      | BLE_GAP_LTK_REQ_DENY(0x01)    | Reject the LTK request.            |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) p_peer_rand is specified as NULL in case of legacy pairing.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) response is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, uint16_t ediv, uint8_t * p_peer_rand, uint8_t response);
+
+/*@}*/
+
+/* ========================================== GATT Common API Declarations ========================================== */
+
+/** @defgroup GATT_COMMON_API GATT_COMMON
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_COMMON_API
+ * @fn ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu)
+ * @brief   This function gets the current MTU used in GATT communication.
+ * @details Both GATT server and GATT Client can use this function. \n
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server or the GATT Client.
+ * @param[in] p_mtu The Current MTU. Before MTU exchange, this parameter is 23 bytes. \n
+ *                  After MTU exchange, this parameter is the negotiated MTU.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The mtu parameter is NULL.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server or the GATT Client specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu);
+
+/*@}*/
+
+/* ========================================== GATT Server API Declarations ========================================== */
+
+/** @defgroup GATT_SERVER_API GATT_SERVER
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_SERVER_API
+ * @fn ble_status_t R_BLE_GATTS_Init(uint8_t cb_num)
+ * @brief   This function initializes the GATT Server and registers the number of the callbacks for GATT Server event.
+ * @details Specify the cb_num parameter to a value between 1 and BLE_GATTS_MAX_CB.\n
+ *          R_BLE_GATTS_RegisterCb() registers the callback.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] cb_num The number of callbacks to be registered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_Init(uint8_t cb_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst)
+ * @brief   This function sets GATT Database to host stack.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] p_db_inst GATT Database to be set.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows.
+ *                                      - The db_inst parameter is specified as NULL.
+ *                                      - The array in the db_inst is specified as NULL.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority)
+ * @brief   This function registers a callback for GATT Server event.
+ * @details The number of the callback that may be registered by this function is the value specified
+ *          by R_BLE_GATTS_Init().\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] cb Callback function for GATT Server event.
+ * @param[in] priority  The priority of the callback function.\n
+ *                      Valid range is 1 <= priority <= BLE_GATTS_MAX_CB.\n
+ *                      A lower priority number means a higher priority level.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb)
+ * @brief   This function deregisters the callback function for GATT Server event.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] cb The callback function to be deregistered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data)
+ * @brief   This function sends a notification of an attribute's value.
+ * @details The maximum length of the attribute value that can be sent with notification is MTU-3.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl Connection handle identifying the remote device to be sent the notification.
+ * @param[in] p_ntf_data The attribute value to send.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_ntf_data parameter or the value field in the value field in
+ *                                      the p_ntf_data parameter is NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ntf_data parameter is 0
+ *                                      or the attr_hdl field in the p_ntf_data parameters is 0.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data)
+ * @brief   This function sends a indication of an attribute's value.
+ * @details  The maximum length of the attribute value that can be sent with indication is MTU-3.\n
+ *           The result of this API call is returned by a return value.\n
+ *           The remote device that receives a indication sends a confirmation.\n
+ *           BLE_GATTS_EVENT_HDL_VAL_CNF event notifies the application layer that the confirmation has been received.
+ * @param[in] conn_hdl Connection handle identifying the remote device to be sent the indication.
+ * @param[in] p_ind_data The attribute value to send.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_ind_data parameter or the value field in the value field in
+ *                                      the p_ind_data parameter is NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ind_data parameter is 0
+ *                                      or the attr_hdl field in the p_ind_data parameters is 0.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value)
+ * @brief   This function gets a attribute value from the GATT Database.
+ * @details  The result of this API call is returned by a return value.
+ * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved,
+ *                     specify the remote device with the conn_hdl parameter.
+ *                     When information about the remote device is not required,
+ *                     set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL.
+ * @param[in] attr_hdl The attribute handle of the attribute value to be retrieved.
+ * @param[out] p_value  The attribute value to be retrieved.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001)  The p_value parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle
+ *                                      of GATT Database.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be read.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be read.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to
+ *                                    any services or characteristics.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value)
+ * @brief   This function sets an attribute value to the GATT Database.
+ * @details  The result of this API call is returned by a return value.
+ * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved,
+ *                     specify the remote device with the conn_hdl parameter.
+ *                     When information about the remote device is not required,
+ *                     set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL.
+ * @param[in] attr_hdl The attribute handle of the attribute value to be set.
+ * @param[in] p_value  The attribute value to be set.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_value parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_DATA(0x0002) The write size is larger than the length of the attribute value.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle
+ *                                      of GATT Database.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be written.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be written.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to
+ *                                    any services or characteristics.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code)
+ * @brief   This function sends an error response to a remote device.
+ * @details  The result is returned from the API.\n
+ *           The error code specified in the callback is notified as Error Response to the remote device.\n
+ *           The result of this API call is returned by a return value.
+ * @param[in] error_code The error codes to be notified the client.\n
+ *                       It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined
+ *                       in Core Spec and Core Spec Supplement.
+ *                      
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                          
+ *                              
+ *                              
+ *                          
+ *                      
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred,  the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute.
+ *                              
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported.
+ *                              
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient.
+ *                              
0x3080 - 0x309FApplication Error.
+ *                              The upper layer defines the error codes.
0x30E0 - 0x30FF
+ *                                  The error code defined in Common Profile and Service Error
+ *                                  Core Specification Supplement(CSS).

+ *                                  CSS ver.7 defines the error codes from 0x30FC to 0x30FF.
+ *                              
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC)The Write Request has not been completed due to the reason other than Permission.
+ *                              
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.

+ *
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The Group ID of the error_code parameter is not 0x3000, or it is 0x3000.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other error response,this function was called.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu)
+ * @brief   This function replies to a MTU Exchange Request from a remote device.
+ * @details  BLE_GATTS_EVENT_EX_MTU_REQ event notifies the application layer
+ *           that a MTU Exchange Request has been received.
+ *           Therefore when the callback has received the event, call this function.\n
+ *           The new MTU is the minimum of the mtu parameter specified by this function
+ *           and the mtu field in BLE_GATTS_EVENT_EX_MTU_REQ event.\n
+ *           Default MTU size is 23 bytes.\n
+ *           The result of this API call is returned by a return value.\n
+ * @param[in] conn_hdl Connection handle identifying the remote device to be sent MTU Exchange Response.
+ * @param[in] mtu The maximum size(in bytes) of the GATT PDU that GATT Server can receive.\n
+ *                Valid range is 23 <= mtu <= 247.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num)
+ * @brief   Register prepare queue and buffer in Host Stack.
+ * @details  This function registers the prepare queue and buffer for long chracteristic write and reliable writes.
+ *           The result of this API call is returned by a return value.\n
+ * @param[in] p_pre_queues The prepare write queues to be registered.
+ * @param[in] queue_num The number of prepare write queues to be registered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_pre_queue parameter is specified as NULL.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num);
+
+/*@}*/
+
+/* ========================================== GATT Client API Declarations ========================================== */
+
+/** @defgroup GATT_CLIENT_API GATT_CLIENT
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup GATT_CLIENT_API
+ * @fn ble_status_t R_BLE_GATTC_Init(uint8_t cb_num)
+ * @brief   This function initializes the GATT Client and registers the number of the callbacks for GATT Client event.
+ * @details Specify the cb_num parameter to a value between 1 and BLE_GATTC_MAX_CB.\n
+ *          R_BLE_GATTC_RegisterCb() registers the callback.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] cb_num The number of callbacks to be registered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_Init(uint8_t cb_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority)
+ * @brief   This function registers a callback function for GATT Client event.
+ * @details The number of the callback that may be registered by this function is the value specified
+ *          by R_BLE_GATTC_Init().\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] cb Callback function for GATT Client event.
+ * @param[in] priority  The priority of the callback function.\n
+ *                      Valid range is 1 <= priority <= BLE_GATTC_MAX_CB.\n
+ *                      A lower priority number means a higher priority level.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb)
+ * @brief   This function deregisters the callback function for GATT Client event.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] cb The callback function to be deregistered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu)
+ * @brief   This function sends a MTU Exchange Request PDU to a GATT Server in order to change the current MTU.
+ * @details  MTU Exchange Response is notified by BLE_GATTC_EVENT_EX_MTU_RSP event.\n
+ *           The new MTU is the minimum value of the mtu parameter specified by this function and
+ *           the mtu field in BLE_GATTC_EVENT_EX_MTU_RSP event.
+ *           Default MTU size is 23 bytes.\n
+ *           The result of this API call is returned by a return value.\n
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be sent.
+ * @param[in] mtu  The maximum size(in bytes) of the GATT PDU that GATT Client can receive. \n
+ *                 Valid range is 23 <= mtu <= 247.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl)
+ * @brief   This function discovers all Primary Services in a GATT Server.
+ * @details  When 16-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When 128-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When the Primary Service discovery has been completed, BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP event
+ *           is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type)
+ * @brief   This function discovers Primary Service specified by p_uuid in a GATT Server.
+ * @details  When Primary Service whose uuid is the same as the specified uuid has been discovered,
+ *           BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event or BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event is
+ *           notified to the application layer.\n
+ *           When the Primary Service discovery has been completed, BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP event
+ *           is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @param[in] p_uuid UUID of Primary Service to be discovered.
+ * @param[in] uuid_type UUID type(16-bit or 128-bit).
+ *                      |              macro                 | description      |
+ *                      |:---------------------------------- |:---------------- |
+ *                      | BLE_GATT_16_BIT_UUID_FORMAT(0x01)  | 16-bit UUID      |
+ *                      | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | 128-bit UUID     |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscAllSecondServ( uint16_t conn_hdl)
+ * @brief   This function discovers all Secondary Services in a GATT Server.
+ * @details  When a 16-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When a 128-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When the Secondary Service discovery has been completed, BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP event
+ *           is notified to the application layer.\n
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscAllSecondServ(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range)
+ * @brief   This function discovers Included Services within the specified attribute handle range in a GATT Server.
+ * @details  When Included Service that includes 16-bit UUID Service has been discovered,
+ *           BLE_GATTC_EVENT_INC_SERV_16_DISC_IND event is notified to the application layer.\n
+ *           When Included Service that includes 128-bit UUID Service has been discovered,
+ *           BLE_GATTC_EVENT_INC_SERV_128_DISC_IND event is notified to the application layer.\n
+ *           When the Included Service discovery has been completed,
+ *           BLE_GATTC_EVENT_INC_SERV_DISC_COMP event is notified to the application layer.\n
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @param[in] p_range Retrieval range of Included Service.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range)
+ * @brief   This function discovers Characteristic within the specified attribute handle range in a GATT Server.
+ * @details  When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When the Characteristic discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP event
+ *           is notified to the application layer.\n
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @param[in] p_range Retrieval range of Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t conn_hdl,
+ *                                             uint8_t * p_uuid,
+ *                                             uint8_t uuid_type,
+ *                                             st_ble_gatt_hdl_range_t * p_range
+ *                                            )
+ * @brief   This function discovers Characteristic specified by uuid within the specified attribute handle range
+ *          in a GATT Server.
+ * @details  When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event
+ *           is notified to the application layer.\n
+ *           When the Characteristic discovery has been completed, BLE_GATTC_EVENT_CHAR_DISC_COMP event
+ *           is notified to the application layer.\n
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @param[in] p_uuid UUID of Characteristic to be discovered.
+ * @param[in] uuid_type UUID type of Characteristic to be discovered.
+ *                      |              macro                 |           description                 |
+ *                      |:---------------------------------- |:------------------------------------- |
+ *                      | BLE_GATT_16_BIT_UUID_FORMAT(0x01)  | The p_uuid parameter is 16-bit UUID.  |
+ *                      | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. |
+ * @param[in] p_range Retrieval range of Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t                  conn_hdl,
+                                        uint8_t                 * p_uuid,
+                                        uint8_t                   uuid_type,
+                                        st_ble_gatt_hdl_range_t * p_range);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range)
+ * @brief   This function discovers Characteristic Descriptor within the specified attribute handle range
+ *          in a GATT Server.
+ * @details When 16-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND
+ *          event is notified to the application layer.
+ *          When 128-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND
+ *          event is notified to the application layer.
+ *          When the Characteristic Descriptor discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP
+ *          event is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered.
+ * @param[in] p_range Retrieval range of Characteristic Descriptor.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl)
+ * @brief   This function reads a Characteristic/Characteristic Descriptor in a GATT Server.
+ * @details The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_RSP event.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be read.
+ * @param[in] value_hdl Value handle of the Characteristic/Characteristic Descriptor to be read.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t conn_hdl,
+ *                                             uint8_t * p_uuid,
+ *                                             uint8_t uuid_type,
+ *                                             st_ble_gatt_hdl_range_t * p_range
+ *                                            );
+ * @brief   This function reads a Characteristic in a GATT Server using a specified UUID.
+ * @details  The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP event.
+ * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server.
+ * @param[in] p_uuid UUID of the Characteristic to be read.
+ * @param[in] uuid_type  UUID type of the Characteristic to be read.
+ *                      |              macro                 |           description                 |
+ *                      |:---------------------------------- |:------------------------------------- |
+ *                      | BLE_GATT_16_BIT_UUID_FORMAT(0x01)  | The p_uuid parameter is 16-bit UUID.  |
+ *                      | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. |
+ * @param[in] p_range Retrieval range of Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t                  conn_hdl,
+                                           uint8_t                 * p_uuid,
+                                           uint8_t                   uuid_type,
+                                           st_ble_gatt_hdl_range_t * p_range);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset)
+ * @brief   This function reads a Long Characteristic in a GATT Server.
+ * @details The contents of the Long Characteristic that has been read is notified every MTU-1 bytes to
+ *          the application layer by BLE_GATTC_EVENT_CHAR_READ_RSP event.\n
+ *          When all of the contents has been received in GATT Client, BLE_GATTC_EVENT_LONG_CHAR_READ_COMP event
+ *          is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be read.
+ * @param[in] value_hdl Value handle of the Long Characteristic to be read.
+ * @param[in] offset Offset that indicates the location to be read.\n
+ *                   Normally, set 0 to this parameter.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list)
+ * @brief   This function reads multiple Characteristics in a GATT Server.
+ * @details The contents of the multiple Characteristics that has been read is notified to the application layer
+ *          by BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP event.
+ * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server.
+ * @param[in] p_list List of Value Handles that point the Characteristics to be read.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_list parameter or the p_hdl_list field in the p_list parameter is
+ *                                      specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the list_count field in the p_list parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data)
+ * @brief   This function writes a Characteristic in a GATT Server without response.
+ * @details The result is returned from the API.
+ * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server.
+ * @param[in] p_write_data Value to be written to the Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field
+ *                                      in the p_write_data parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                      - 0 is specified in the value_len field in the p_value field in the p_write_data parameter.
+ *                      - 0 is specified in the attr_hdl field in the p_write_data parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data)
+ * @brief   This function writes Signed Data to a Characteristic in a GATT Server without response.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be written.
+ * @param[in] p_write_data Signed Data to be written to the Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field
+ *                                      in the p_write_data parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                      - 0 is specified in the value_len field in the value field in the p_write_data parameter.
+ *                      - 0 is specified in the attr_hdl field in the p_write_data parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or Signed Data.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data)
+ * @brief   This function writes a Characteristic in a GATT Server.
+ * @details The result of the write is notified in BLE_GATTC_EVENT_CHAR_WRITE_RSP event.
+ * @param[in] conn_hdl  Connection handle identifying the GATT Server to be written.
+ * @param[in] p_write_data Value to be written to the Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field
+ *                                      in the p_write_data parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *                      - 0 is specified in the value_len field in the value field in the p_write_data parameter.
+ *                      - 0 is specified in the attr_hdl field in the p_write_data parameter.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl,
+ *                                            st_ble_gatt_hdl_value_pair_t * p_write_data,
+ *                                            uint16_t offset
+ *                                            )
+ * @brief   This function writes a Long Characteristic in a GATT Server.
+ * @details The result of a write that has been done every segmentation is notified to the application layer
+ *          in BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP event.\n
+ *          The maximum writable size to a Long Characteristic with this function is 512 bytes.\n
+ *          When all of the contents has been written to the Long Characteristic, BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP
+ *          event is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be written.
+ * @param[in] p_write_data Value to be written to the Long Characteristic.
+ * @param[in] offset Offset that indicates the location to be written.
+ *                   Normally, set 0 to this parameter.\n
+ *                   If this parameter sets to a value other than 0, adjust the offset parameter and
+ *                   the length of the value to be written not to exceed the length of the Long Characteristic.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field in
+ *                                      the p_write_data parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *            - The value_len field in the value field in the p_write_data parameter is 0.
+ *            - The sum of the value_len field in the value field in the p_write_data parameter
+ *              and the offset parameter larger than 512.
+ *            - The attr_hdl field in the p_write_data parameter is 0.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data, uint16_t offset);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t conn_hdl,
+ *                                             st_ble_gattc_reliable_writes_char_pair_t * p_char_pair,
+ *                                             uint8_t pair_num,
+ *                                             uint8_t auto_flag
+ *                                            )
+ * @brief   This function performs the Reliable Writes procedure described in GATT Specification.
+ * @details When the data written to the Characteristic has been transmitted, BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP
+ *          event is notified to the application layer.\n
+ *          If the data included in the event is different from the data that GATT Client has sent,
+ *          host stack automatically cancels the Reliable Writes.\n
+ *          After all of the contents has been sent to the GATT Server, if the auto_flag parameter has been set to
+ *          BLE_GATTC_EXEC_AUTO, the GATT Server automatically writes the data to the Characteristic.\n
+ *          If the auto_flag parameter has been set to BLE_GATTC_EXEC_NOT_AUTO,  BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP
+ *          event notifies the application layer in GATT Client that all of the contents has been sent to
+ *          the GATT Server. Then GATT Client requests for writing the data to the Characteristic to the GATT Server
+ *          with R_BLE_GATTC_ExecWrite().\n
+ *          When the write has been done, BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event is notified to
+ *          the application layer.
+ * @param[in] conn_hdl Connection handle identifying the GATT Server to be written.
+ * @param[in] p_char_pair Pair of Characteristic Value and Characteristic Value Handle identifying the Characteristic
+ *                        to be written by Reliable Writes.
+ * @param[in] pair_num The number of the pairs specified by the p_char_pair parameter.\n
+ *                   Valid range is 0 < pair_num <= BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR.
+ * @param[in] auto_flag  The flag that indicates whether auto execution or not.
+ *        |              macro             |   description       |
+ *        |:------------------------------ |:------------------- |
+ *        | BLE_GATTC_EXEC_AUTO(0x01)      | Auto execution.     |
+ *        | BLE_GATTC_EXEC_NOT_AUTO (0x02) | Not auto execution. |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows:
+ *       - The p_char_pair parameter is specified as NULL.
+ *       - The p_value field in the value field in the write_data field in the p_char_pair parameter
+ *         is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows:
+ *       - The pair_num parameter or the auto_flag parameter is out of range.
+ *       - The value_len field in the value field in the write_data field in the p_char_pair parameter is 0.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or
+ *                                           to store the temporary write data.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t                                   conn_hdl,
+                                        st_ble_gattc_reliable_writes_char_pair_t * p_char_pair,
+                                        uint8_t                                    pair_num,
+                                        uint8_t                                    auto_flag);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag)
+ * @brief   If the auto execute of Reliable Writes is not specified by R_BLE_GATTC_ReliableWrites(),
+ *          this function is used to execute a write to Characteristic.
+ * @details When all of the contents has been sent to the GATT Server, BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP event
+ *          notifies the application layer.\n
+ *          After this event has been received, execute the write by this function.\n
+ *          The result of the write is notified by BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event.
+ * @param[in] conn_hdl Connection handle identifying the target GATT Server.
+ * @param[in] exe_flag The flag that indicates whether execution or cancellation.
+ *        |              macro                          |   description       |
+ *        |:------------------------------------------- |:------------------- |
+ *        | BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG(0x00)   | Execute the write.  |
+ *        | BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG(0x01)     | Cancel the write.   |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The exe_flag parameter is out of range.
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) The reason for this error is as follows:
+ *           - GATT Client has not requested for Reliable Writes by R_BLE_GATTC_ReliableWrites().
+ *           - Although auto execution has been specified by R_BLE_GATTC_ReliableWrites(), this function was called.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag);
+
+/*@}*/
+
+/* ============================================= L2CAP API Declarations ============================================= */
+
+/** @defgroup L2CAP_API L2CAP
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup L2CAP_API
+ * @fn ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm)
+ * @brief   This function registers PSM that uses L2CAP CBFC Channel and a callback for L2CAP event.
+ * @details Only one callback is available per PSM. Configure in each PSM the Low Water Mark of the LE-Frames
+ *          that the local device can receive.\n
+ *          When the number of the credit reaches the Low Water Mark, BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event is
+ *          notified to the application layer.\n
+ *          The number of PSM is defined as BLE_L2CAP_MAX_CBFC_PSM.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] cb Callback function for L2CAP event.
+ * @param[in] psm  Identifier indicating the protocol/profile that uses L2CAP CBFC Channel.
+ *              
+ *                  
+ *                      
+ *                      
+ *                      
+ *                  
+ *                  
+ *                      
+ *                      
+ *                      
+ *                  
+ *                  
+ *                      
+ *                      
+ *                      
+ *                  
+ *              
typerangedescription
Fixed, SIG assigned0x0001 - 0x007FPSM defined by SIG. For more information on PSM, refer Bluetooth SIG Assigned Number
+ *                          (https://www.bluetooth.com/specifications/assigned-numbers).
+ *                      
Dynamic0x0080 - 0x00FF
+ *                          Statically allocated PSM by custom protocol or dynamically allocated PSM by GATT Service.
+ *                      

+ * @param[in] lwm Low Water Mark that indicates the LE-Frame numbers that the local device can receive.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The psm parameter is out of range.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) More than BLE_L2CAP_MAX_CBFC_PSM+1 PSMs, callbacks has been registered.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm)
+ * @brief   This function stops the use of the L2CAP CBFC Channel specified by the psm parameter and
+ *          deregisters the callback function for L2CAP event.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] psm PSM that is to be stopped to use the L2CAP CBFC Channel.\n
+ *                Set the PSM registered by R_BLE_L2CAP_RegisterCfPsm().
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) The callback function allocated by the psm parameter is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param)
+ * @brief   This function sends a connection request for L2CAP CBFC Channel.
+ * @details The connection response is notified by BLE_L2CAP_EVENT_CF_CONN_CNF event.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] conn_hdl Connection handle identifying the remote device that the connection request is sent to.
+ * @param[in] p_conn_req_param Connection request parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_conn_req_param parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The mtu parameter or the mps parameter is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) New CF Channel can not be registered or other L2CAP Command is processing.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found.
+ * @retval  BLE_ERR_NOT_YET_READY(0x0012) The psm parameter is not registered.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param)
+ * @brief   This function replies to the connection request for L2CAP CBFC Channel from the remote device.
+ * @details The connection request is notified by BLE_L2CAP_EVENT_CF_CONN_IND event.
+ *          The result of this API call is returned by a return value.
+ * @param[in] p_conn_rsp_param Connection response parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_conn_rsp_param parameter is specified as NULL.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) A connection request for L2CAP CBFC Channel has not been received,
+ *                                    or CID specified by the lcid field in the p_conn_rsp_param parameter is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid)
+ * @brief   This function sends a disconnection request for L2CAP CBFC Channel.
+ * @details When L2CAP CBFC Channel has been disconnected,
+ *          BLE_L2CAP_EVENT_CF_DISCONN_CNF event is notified to the application layer.
+ * @param[in] lcid CID identifying the L2CAP CBFC Channel that has been disconnected.\n
+ *                 The valid range is 0x40 - (0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1).
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_OPERATION(0x0009) CF Channel connection has not been established.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit)
+ * @brief   This function sends credit to a remote device.
+ * @details In L2CAP CBFC communication, if credit is 0, the remote device stops data transmission.\n
+ *          Therefore when processing the received data has been completed and local device affords to receive data,
+ *          the remote device is notified of the number of LE-Frame that local device can receive
+ *          by this function and local device can continue to receive data from the remote device.\n
+ *          The result of this API call is returned by a return value.
+ * @param[in] lcid CID identifying the L2CAP CBFC Channel on local device that sends credit.
+ * @param[in] credit  Credit to be sent to the remote device.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The credit parameter is set to 0.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu)
+ * @brief   This function sends the data to a remote device via L2CAP CBFC Channel.
+ * @details When the data transmission to Controller has been completed,
+ *          BLE_L2CAP_EVENT_CF_TX_DATA_CNF event is notified to the application layer.
+ * @param[in] conn_hdl Connection handle identifying the remote device to be sent the data.
+ * @param[in] lcid  CID identifying the L2CAP CBFC Channel on local device used in the data transmission.
+ * @param[in] data_len Length of the data.
+ * @param[in] p_sdu Service Data Unit. \n
+ *            Input the data length specified by the data_len parameter to the first 2 bytes (Little Endian).
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_data parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The length parameter is out of range.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established or the data whose length
+ *                                        exceeds the MTU has been sent.
+ * @retval  BLE_ERR_ALREADY_IN_PROGRESS(0x000A) Data transmission has been already started.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) L2CAP task queue is full.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command.
+ * @retval  BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found.
+ * @retval  BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter is not found.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu);
+
+/*@}*/
+
+/* ======================================== Vendor Specific API Declarations ======================================== */
+
+/** @defgroup VS_API VS
+ *  @ingroup BLE
+ *  @{
+ */
+
+/******************************************************************************************************************//**
+ * @ingroup VS_API
+ * @fn ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb)
+ * @brief   This function initializes Vendor Specific API and registers a callback function for Vendor Specific Event.
+ * @details The result of this API call is returned by a return value.
+ * @param[in] vs_cb Callback function to be registered.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The vs_cb parameter is specified as NULL.
+ * @retval  BLE_ERR_CONTEXT_FULL(0x000B) Callback function has already been registered.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param)
+ * @brief   This function starts extended Transmitter Test.
+ * @details The following extended transmitter test functions of DTM Tx are supported by this function.
+ *            - Tx Power
+ *            - Tx Modulation Enable/Modulation Disable
+ *            - Tx packet transmission/continuous transmission
+ *            - Tx packets count
+ *
+ *           The result of this API call is notified in BLE_VS_EVENT_TX_TEST_START event.\n
+ *           If the num_of_packet field in the p_tx_test_param parameter is other than 0x0000,
+ *           BLE_VS_EVENT_TX_TEST_TERM event notifies the application layer that the number of packet has been sent.\n
+ *           If R_BLE_VS_EndTest() is called before the specified number of packets completions,
+ *           BLE_VS_EVENT_TX_TEST_TERM event is not notified to the application layer.
+ *
+ *           The condition that phy field in the p_tx_test_param parameter is @ref BLE_VS_EH_TEST_PHY_CODED_S_8(0x03)
+ *           and option field is modulation(bit0:0) & continuous transmission(bit1:1) is not supported.
+ *
+ * @param[in] p_tx_test_param Tx Test parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_tx_test_param parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param)
+ * @brief   This function starts extended Receiver Test.
+ * @details The result of this API call is notified in BLE_VS_EVENT_RX_TEST_START event.
+ *          The following extended receiver test functions of DTM Rx are supported by this function.
+ *            - Calculating the maximum, the minimum and the average of RSSI in the receiver test.
+ *            - The number of CRC error packets in the receiver test.
+ *
+ *          The transmitter is configured to one of the following, the receiver can't receive the packets by this function.\n
+ *          - Tx Non-Modulation Enable
+ *          - Tx continuous transmission
+ *          \n
+ *          After R_BLE_VS_EndTest() has been called,
+ *          the receiver test result value are notified in BLE_VS_EVENT_TEST_END event.
+ *
+ * @param[in] p_rx_test_param The extended receiver test parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_rx_test_param parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_EndTest(void)
+ * @brief   This function terminates the extended transmitter or receiver test.
+ * @details The result of this API call is notified in BLE_VS_EVENT_TEST_END event.
+ *          In case of extended receiver test, this event notifies the application layer of
+ *          the result of the extended receiver test.
+ *
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_EndTest(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power)
+ * @brief   This function configures transmit power.
+ * @details This function configures the following transmit power.
+ *          - The transmit power used in sending advertising PDU, scan request PDU,
+ *             connection request PDU (in not connected state)
+ *          - The transmit power used in sending PDU in connected state.
+ *          When configuring the transmit power used in not connected state, set the conn_hdl parameter
+ *          to BLE_GAP_INIT_CONN_HDL(0xFFFF).\n
+ *          When the transmit power used in connected state is configured, set the conn_hdl parameter
+ *          to the connection handle of the link.\n
+ *          Select one of the following transmit power levels.
+ *          - High
+ *          - Middle
+ *          - Low
+ *
+ *          Max transmit power of "High" is dependent on the configuration of the firmware.
+ *          The result of this API call is notified in BLE_VS_EVENT_SET_TX_POWER event.
+ *
+ * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be configured.
+ *            If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF).
+ * @param[in] tx_power Transmission power. Select one of the following.
+ *                     - BLE_VS_TX_POWER_HIGH(0x00)
+ *                     - BLE_VS_TX_POWER_MID(0x01)
+ *                     - BLE_VS_TX_POWER_LOW(0x02)
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl)
+ * @brief   This function gets transmit power.
+ * @details This function gets the following transmit power.
+ *            - The transmit power used in sending advertising PDU, scan request PDU,
+ *              connection request PDU (in not connected state)
+ *            - The transmit power used in sending PDU in connected state.
+ *          When getting the transmit power used in not connected state, set the conn_hdl parameter to
+ *          BLE_GAP_INIT_CONN_HDL(0xFFFF).\n
+ *          When the transmit power used in connected state is retrieved, set the conn_hdl parameter to
+ *          the connection handle of the link.
+ *          The result of this API call is notified in BLE_VS_EVENT_GET_TX_POWER event.
+ *
+ * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be retrieved.
+ *                     If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF).
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme)
+ * @brief   This function configure default Coding scheme(S=8 or S=2) that is used in the case of selecting Coded PHY
+ *          in Primary advertising PHY or Secondary advertising PHY advertising or request for link establishment.
+ * @details After setting the default Coding scheme by this function, configure the advertising parameters
+ *          by R_BLE_GAP_SetAdvParam() or send a request for link establishment.\n
+ *          The result of this API call is notified in BLE_VS_EVENT_SET_CODING_SCHEME_COMP event.
+ * @param[in] coding_scheme Coding scheme for Primary advertising PHY, Secondary advertising PHY,
+ *                          request for link establishment.The coding_scheme field is set to a bitwise OR
+ *                          of the following values.
+ *        | bit            |   description                                                  |
+ *        |:-------------- |:-------------------------------------------------------------- |
+ *        | bit0           | Coding scheme for Primary Advertising PHY(0:S=8/1:S=2).        |
+ *        | bit1           | Coding scheme for Secondary Advertising PHY(0:S=8/1:S=2).      |
+ *        | bit2           | Coding scheme for request for link establishment(0:S=8/1:S=2). |
+ *        | All other bits | Reserved for future use.                                       |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl)
+ * @brief   This function performs power control on RF.
+ * @details If BLE communication is not used for a long time, RF reduces the power consumption by moving to
+ *          the RF Power-Down Mode.\n
+ *          When RF power on, RF initialization processing is executed.\n
+ *          After RF power off by this function, API functions other than this are not available
+ *          until RF power on again.\n
+ *          The result of this API call is notified in BLE_VS_EVENT_RF_CONTROL_COMP event.
+ *          After RF power on again with this function, call R_BLE_GAP_Terminate(),
+ *          R_BLE_GAP_Init() in order to restart the host stack.
+ * @param[in] p_rf_ctrl RF parameters.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_rf_ctrl parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr)
+ * @brief   This function sets public/random address of local device to the area specified by the parameter.
+ * @details If the address is written in non-volatile area, the address is used as default address
+ *          on the next MCU reset.\n
+ *          For more information on the random address, refer to Core Specification Vol 6, PartB,
+ *          "1.3.2 Random Device Address".\n
+ *          The result of this API call is notified in BLE_VS_EVENT_SET_ADDR_COMP event.
+ * @param[in] area The area that the address is to be written in.\n
+ *                 Select one of the following.
+ *                  
+ *                      
+ *                          
+ *                          
+ *                      
+ *                      
+ *                          
+ *                          
+ *                      
+ *                      
+ *                          
+ *                          
+ *                      
+ *                  
macrodescription
BLE_VS_ADDR_AREA_REG(0x00)
+ *                              Address writing to non-volatile area is not performed.

+ *                              Only the address in register is written.
+ *                          
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Address wiring to DataFlash area is performed.

+ * @param[in] p_addr The address to be set to the area.
+ *                   Set BLE_GAP_ADDR_PUBLIC(0x00) or BLE_GAP_ADDR_RAND(0x01) to the type field in the p_addr parameter.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_addr parameter is specified as NULL.
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type)
+ * @brief   This function gets currently configured public/random address.
+ * @details The area parameter specifies the place where this function retrieves public/random address.\n
+ *          The result of this API call is notified in BLE_VS_EVENT_GET_ADDR_COMP event.
+ * @param[in] area The area that the address is to be retrieved.\n
+ *                 Select one of the following.
+ *                  
+ *                      
+ *                          
+ *                          
+ *                      
+ *                      
+ *                          
+ *                          
+ *                      
+ *                      
+ *                          
+ *                          
+ *                      
+ *                  
macrodescription
BLE_VS_ADDR_AREA_REG(0x00)Retrieve the address in register.
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Retrieve the address in DataFlash area.

+ * @param[in] addr_type The address type that is type of the address to be retrieved.
+ *        | macro                     |   description      |
+ *        |:------------------------- |:------------------ |
+ *        | BLE_GAP_ADDR_PUBLIC(0x00) | Public address.    |
+ *        | BLE_GAP_ADDR_RAND(0x01)   | Random address.    |
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_GetRand(uint8_t rand_size)
+ * @brief   This function generates 4-16 bytes of random number used in creating keys.
+ * @details The result of this API call is notified in BLE_VS_EVENT_GET_RAND event.
+ * @param[in] rand_size Length of the random number (byte).\n
+ *                      The valid range is 4<=rand_size<=16.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running.
+ * @retval  BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_GetRand(uint8_t rand_size);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void)
+ * @brief   This function starts the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of
+ *          the state transition of TxFlow.
+ * @details If the number of the available transmission packet buffers is the following,
+ *          BLE_VS_EVENT_TX_FLOW_STATE_CHG event notifies the application layer of the state of the TxFlow.
+ *          - The number of the available transmission packet buffers is less than Low Water Mark.
+ *          - The number of the available transmission packet buffers is more than High Water Mark.
+ *          The result of this API call is returned by a return value.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void)
+ * @brief   This function stops the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of
+ *          the state transition of TxFlow.
+ * @details The result of this API call is returned by a return value.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num)
+ * @brief   This function retrieves the number of the available transmission packet buffers.
+ * @details The maximum number of the available buffers is 10.\n
+ *          The result of this API call is returned by a return value.
+ * @param[out] p_buffer_num The number of the available transmission packet buffers.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_PTR(0x0001) The p_buffer_num parameter is specified as NULL.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num);
+
+/******************************************************************************************************************//**
+ * @fn ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm)
+ * @brief   This function sets the threshold for notifying the application layer of the TxFlow state.
+ * @details Call this function before the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) has been started
+ *          by R_BLE_VS_StartTxFlowEvtNtf(). \n
+ *          The result is returned from this API.\n
+ *          Vendor Specific API supports the flow control function(TxFlow) for the transmission
+ *          on L2CAP fixed channel in Basic Mode such as GATT.\n
+ *          Host stack has 10 transmission packet buffers for the transmission.\n
+ *          When the number of the available transmission packet buffers has been less than Low Water Mark,
+ *          the state of TxFlow transmits into the TxFlow OFF state from the TxFlow ON state
+ *          that is the initial state and host stack notifies the application layer of
+ *          timing to stop packet transmission.\n
+ *          When host stack has sent the transmission packets to Controller and the number of the available
+ *          transmission packet buffers has been more than High Water Mark, the state of TxFlow transmits into
+ *          the TxFlow ON state from the TxFlow OFF state and host stack notifies the application layer of
+ *          timing to restart packet transmission.\n
+ *          It is possible to perform flow control on a fixed channel by using the event notification.
+ * @param[in] tx_queue_lwm Low Water Mark.
+ *                         Set 0-9 less than tx_queue_hwm to the parameter.
+ *                         When the number of the available transmission packet buffers has been less than the value
+ *                         specified by the tx_queue_lwm parameter, host stack notifies the application layer of
+ *                         the timing to stop packet transmission.
+ * @param[in] tx_queue_hwm High Water Mark.
+ *                         Set 1-10 more than tx_queue_lwm to the parameter.
+ *                         When the number of the available transmission packet buffers has been more than
+ *                         the value specified by the tx_queue_hwm parameter, host stack notifies
+ *                         the application layer of the timing to restart packet transmission.
+ * @retval  BLE_SUCCESS(0x0000) Success
+ * @retval  BLE_ERR_INVALID_ARG(0x0003) The tx_queue_lwm parameter or the tx_queue_hwm parameter is out of range.
+ **********************************************************************************************************************/
+ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm);
+
+/*@}*/
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup BLE_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h
new file mode 100644
index 0000000000..6e86d0e2fb
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_cgc_api.h
@@ -0,0 +1,356 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef R_CGC_API_H
+#define R_CGC_API_H
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup CGC_API CGC Interface
+ * @brief Interface for clock generation.
+ *
+ * @section CGC_API_SUMMARY Summary
+ *
+ * The CGC interface provides the ability to configure and use all of the CGC module's capabilities. Among the
+ * capabilities is the selection of several clock sources to use as the system clock source. Additionally, the
+ * system clocks can be divided down to provide a wide range of frequencies for various system and peripheral needs.
+ *
+ * Clock stability can be checked and clocks may also be stopped to save power when not needed. The API has a function
+ * to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect
+ * when the main oscillator has stopped, with the option of calling a user provided callback function.
+ *
+ * The CGC interface is implemented by:
+ * - @ref CGC
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Version Number of API. */
+#define CGC_API_VERSION_MAJOR    (1U)
+#define CGC_API_VERSION_MINOR    (0U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Events that can trigger a callback function */
+typedef enum e_cgc_event
+{
+    CGC_EVENT_OSC_STOP_DETECT          ///< Oscillator stop detection has caused the event
+} cgc_event_t;
+
+/** Callback function parameter data */
+typedef struct st_cgc_callback_args
+{
+    cgc_event_t  event;                ///< The event can be used to identify what caused the callback
+    void const * p_context;            ///< Placeholder for user data
+} cgc_callback_args_t;
+
+/** System clock source identifiers -  The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock
+ * divider */
+typedef enum e_cgc_clock
+{
+    CGC_CLOCK_HOCO     = 0,            ///< The high speed on chip oscillator
+    CGC_CLOCK_MOCO     = 1,            ///< The middle speed on chip oscillator
+    CGC_CLOCK_LOCO     = 2,            ///< The low speed on chip oscillator
+    CGC_CLOCK_MAIN_OSC = 3,            ///< The main oscillator
+    CGC_CLOCK_SUBCLOCK = 4,            ///< The subclock oscillator
+    CGC_CLOCK_PLL      = 5,            ///< The PLL oscillator
+} cgc_clock_t;
+
+/** PLL divider values */
+typedef enum e_cgc_pll_div
+{
+    CGC_PLL_DIV_1 = 0,                 ///< PLL divider of 1
+    CGC_PLL_DIV_2 = 1,                 ///< PLL divider of 2
+    CGC_PLL_DIV_3 = 2,                 ///< PLL divider of 3 (S7, S5 only)
+    CGC_PLL_DIV_4 = 3,                 ///< PLL divider of 4 (S3 only)
+} cgc_pll_div_t;
+
+/** PLL multiplier values */
+typedef enum e_cgc_pll_mul
+{
+    CGC_PLL_MUL_8_0  = 0xF,            ///< PLL multiplier of 8.0
+    CGC_PLL_MUL_9_0  = 0x11,           ///< PLL multiplier of 9.0
+    CGC_PLL_MUL_10_0 = 0x13,           ///< PLL multiplier of 10.0
+    CGC_PLL_MUL_10_5 = 0x14,           ///< PLL multiplier of 10.5
+    CGC_PLL_MUL_11_0 = 0x15,           ///< PLL multiplier of 11.0
+    CGC_PLL_MUL_11_5 = 0x16,           ///< PLL multiplier of 11.5
+    CGC_PLL_MUL_12_0 = 0x17,           ///< PLL multiplier of 12.0
+    CGC_PLL_MUL_12_5 = 0x18,           ///< PLL multiplier of 12.5
+    CGC_PLL_MUL_13_0 = 0x19,           ///< PLL multiplier of 13.0
+    CGC_PLL_MUL_13_5 = 0x1A,           ///< PLL multiplier of 13.5
+    CGC_PLL_MUL_14_0 = 0x1B,           ///< PLL multiplier of 14.0
+    CGC_PLL_MUL_14_5 = 0x1D,           ///< PLL multiplier of 14.5
+    CGC_PLL_MUL_15_0 = 0x1D,           ///< PLL multiplier of 15.0
+    CGC_PLL_MUL_15_5 = 0x1E,           ///< PLL multiplier of 15.5
+    CGC_PLL_MUL_16_0 = 0x1F,           ///< PLL multiplier of 16.0
+    CGC_PLL_MUL_16_5 = 0x20,           ///< PLL multiplier of 16.5
+    CGC_PLL_MUL_17_0 = 0x21,           ///< PLL multiplier of 17.0
+    CGC_PLL_MUL_17_5 = 0x22,           ///< PLL multiplier of 17.5
+    CGC_PLL_MUL_18_0 = 0x23,           ///< PLL multiplier of 18.0
+    CGC_PLL_MUL_18_5 = 0x24,           ///< PLL multiplier of 18.5
+    CGC_PLL_MUL_19_0 = 0x25,           ///< PLL multiplier of 19.0
+    CGC_PLL_MUL_19_5 = 0x26,           ///< PLL multiplier of 19.5
+    CGC_PLL_MUL_20_0 = 0x27,           ///< PLL multiplier of 20.0
+    CGC_PLL_MUL_20_5 = 0x28,           ///< PLL multiplier of 20.5
+    CGC_PLL_MUL_21_0 = 0x29,           ///< PLL multiplier of 21.0
+    CGC_PLL_MUL_21_5 = 0x2A,           ///< PLL multiplier of 21.5
+    CGC_PLL_MUL_22_0 = 0x2B,           ///< PLL multiplier of 22.0
+    CGC_PLL_MUL_22_5 = 0x2C,           ///< PLL multiplier of 22.5
+    CGC_PLL_MUL_23_0 = 0x2D,           ///< PLL multiplier of 23.0
+    CGC_PLL_MUL_23_5 = 0x2E,           ///< PLL multiplier of 23.5
+    CGC_PLL_MUL_24_0 = 0x2F,           ///< PLL multiplier of 24.0
+    CGC_PLL_MUL_24_5 = 0x30,           ///< PLL multiplier of 24.5
+    CGC_PLL_MUL_25_0 = 0x31,           ///< PLL multiplier of 25.0
+    CGC_PLL_MUL_25_5 = 0x32,           ///< PLL multiplier of 25.5
+    CGC_PLL_MUL_26_0 = 0x33,           ///< PLL multiplier of 26.0
+    CGC_PLL_MUL_26_5 = 0x34,           ///< PLL multiplier of 26.5
+    CGC_PLL_MUL_27_0 = 0x35,           ///< PLL multiplier of 27.0
+    CGC_PLL_MUL_27_5 = 0x36,           ///< PLL multiplier of 27.5
+    CGC_PLL_MUL_28_0 = 0x37,           ///< PLL multiplier of 28.0
+    CGC_PLL_MUL_28_5 = 0x38,           ///< PLL multiplier of 28.5
+    CGC_PLL_MUL_29_0 = 0x39,           ///< PLL multiplier of 29.0
+    CGC_PLL_MUL_29_5 = 0x3A,           ///< PLL multiplier of 29.5
+    CGC_PLL_MUL_30_0 = 0x3B,           ///< PLL multiplier of 30.0
+    CGC_PLL_MUL_31_0 = 0x3D,           ///< PLL multiplier of 31.0
+} cgc_pll_mul_t;
+
+/** System clock divider vlues - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK,
+ * PCLKS A-D.  */
+typedef enum e_cgc_sys_clock_div
+{
+    CGC_SYS_CLOCK_DIV_1  = 0,          ///< System clock divided by 1
+    CGC_SYS_CLOCK_DIV_2  = 1,          ///< System clock divided by 2
+    CGC_SYS_CLOCK_DIV_4  = 2,          ///< System clock divided by 4
+    CGC_SYS_CLOCK_DIV_8  = 3,          ///< System clock divided by 8
+    CGC_SYS_CLOCK_DIV_16 = 4,          ///< System clock divided by 16
+    CGC_SYS_CLOCK_DIV_32 = 5,          ///< System clock divided by 32
+    CGC_SYS_CLOCK_DIV_64 = 6,          ///< System clock divided by 64
+} cgc_sys_clock_div_t;
+
+/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */
+typedef struct st_cgc_pll_cfg
+{
+    cgc_clock_t   source_clock;        ///< PLL source clock (main oscillator or HOCO)
+    cgc_pll_div_t divider;             ///< PLL divider
+    cgc_pll_mul_t multiplier;          ///< PLL multiplier
+} cgc_pll_cfg_t;
+
+/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet
+ * functions. */
+typedef union u_cgc_divider_cfg
+{
+    uint32_t sckdivcr_w;               ///< (@ 0x4001E020) System clock Division control register
+
+    /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in FSP code. */
+    struct
+    {
+        cgc_sys_clock_div_t pclkd_div : 3; ///< Divider value for PCLKD
+        uint32_t                      : 1;
+        cgc_sys_clock_div_t pclkc_div : 3; ///< Divider value for PCLKC
+        uint32_t                      : 1;
+        cgc_sys_clock_div_t pclkb_div : 3; ///< Divider value for PCLKB
+        uint32_t                      : 1;
+        cgc_sys_clock_div_t pclka_div : 3; ///< Divider value for PCLKA
+        uint32_t                      : 1;
+        cgc_sys_clock_div_t bclk_div  : 3; ///< Divider value for BCLK
+        uint32_t                      : 5;
+        cgc_sys_clock_div_t iclk_div  : 3; ///< Divider value for ICLK
+        uint32_t                      : 1;
+        cgc_sys_clock_div_t fclk_div  : 3; ///< Divider value for FCLK
+    };
+} cgc_divider_cfg_t;
+
+/** USB clock divider values */
+typedef enum e_cgc_usb_clock_div
+{
+    CGC_USB_CLOCK_DIV_3 = 2,           ///< Divide USB source clock by 3
+    CGC_USB_CLOCK_DIV_4 = 3,           ///< Divide USB source clock by 4
+    CGC_USB_CLOCK_DIV_5 = 4,           ///< Divide USB source clock by 5
+} cgc_usb_clock_div_t;
+
+/** Clock options */
+typedef enum e_cgc_clock_change
+{
+    CGC_CLOCK_CHANGE_START = 0,        ///< Start the clock
+    CGC_CLOCK_CHANGE_STOP  = 1,        ///< Stop the clock
+    CGC_CLOCK_CHANGE_NONE  = 2,        ///< No change to the clock
+} cgc_clock_change_t;
+
+/** CGC control block.  Allocate an instance specific control block to pass into the CGC API calls.
+ * @par Implemented as
+ * - cgc_instance_ctrl_t
+ */
+typedef void cgc_ctrl_t;
+
+/** Configuration options. */
+typedef struct s_cgc_cfg
+{
+    void (* p_callback)(cgc_callback_args_t * p_args);
+} cgc_cfg_t;
+
+/** Clock configuration */
+typedef struct st_cgc_clocks_cfg
+{
+    cgc_clock_t        system_clock;   ///< System clock source enumeration
+    cgc_pll_cfg_t      pll_cfg;        ///< PLL configuration structure
+    cgc_divider_cfg_t  divider_cfg;    ///< Clock dividers structure
+    cgc_clock_change_t loco_state;     ///< State of LOCO
+    cgc_clock_change_t moco_state;     ///< State of MOCO
+    cgc_clock_change_t hoco_state;     ///< State of HOCO
+    cgc_clock_change_t mainosc_state;  ///< State of Main oscillator
+    cgc_clock_change_t pll_state;      ///< State of PLL
+} cgc_clocks_cfg_t;
+
+/** CGC functions implemented at the HAL layer follow this API. */
+typedef struct
+{
+    /** Initial configuration
+     * @par Implemented as
+     * - @ref R_CGC_Open()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   p_cfg          Pointer to configuration
+     */
+    fsp_err_t (* open)(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg);
+
+    /** Configure all system clocks.
+     * @par Implemented as
+     * - @ref R_CGC_ClocksCfg()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   p_clock_cfg    Pointer to desired configuration of system clocks
+     */
+    fsp_err_t (* clocksCfg)(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg);
+
+    /** Start a clock.
+     * @par Implemented as
+     * - @ref R_CGC_ClockStart()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   clock_source   Clock source to start
+     * @param[in]   p_pll_cfg      Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL
+     */
+    fsp_err_t (* clockStart)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source,
+                             cgc_pll_cfg_t const * const p_pll_cfg);
+
+    /** Stop a clock.
+     * @par Implemented as
+     * - @ref R_CGC_ClockStop()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   clock_source   The clock source to stop
+     */
+    fsp_err_t (* clockStop)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source);
+
+    /** Check the stability of the selected clock.
+     * @par Implemented as
+     * - @ref R_CGC_ClockCheck()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   clock_source   Which clock source to check for stability
+     */
+    fsp_err_t (* clockCheck)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source);
+
+    /** Set the system clock.
+     * @par Implemented as
+     * - @ref R_CGC_SystemClockSet()
+     * @param[in]   p_ctrl         Pointer to instance control block
+     * @param[in]   clock_source   Clock source to set as system clock
+     * @param[in]   p_divider_cfg  Pointer to the clock divider configuration
+     */
+    fsp_err_t (* systemClockSet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source,
+                                 cgc_divider_cfg_t const * const p_divider_cfg);
+
+    /** Get the system clock information.
+     * @par Implemented as
+     * - @ref R_CGC_SystemClockGet()
+     * @param[in]   p_ctrl          Pointer to instance control block
+     * @param[out]  p_clock_source  Returns the current system clock
+     * @param[out]  p_divider_cfg   Returns the current system clock dividers
+     */
+    fsp_err_t (* systemClockGet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t * const p_clock_source,
+                                 cgc_divider_cfg_t * const p_divider_cfg);
+
+    /** Enable and optionally register a callback for Main Oscillator stop detection.
+     * @par Implemented as
+     * - @ref R_CGC_OscStopDetectEnable()
+     * @param[in]   p_ctrl       Pointer to instance control block
+     * @param[in]   p_callback   Callback function that will be called by the NMI interrupt when an oscillation stop is
+     *                           detected. If the second argument is "false", then this argument can be NULL.
+     * @param[in]   enable       Enable/disable Oscillation Stop Detection
+     */
+    fsp_err_t (* oscStopDetectEnable)(cgc_ctrl_t * const p_ctrl);
+
+    /** Disable Main Oscillator stop detection.
+     * @par Implemented as
+     * - @ref R_CGC_OscStopDetectDisable()
+     * @param[in]   p_ctrl          Pointer to instance control block
+     */
+    fsp_err_t (* oscStopDetectDisable)(cgc_ctrl_t * const p_ctrl);
+
+    /** Clear the oscillator stop detection flag.
+     * @par Implemented as
+     * - @ref R_CGC_OscStopStatusClear()
+     * @param[in]   p_ctrl          Pointer to instance control block
+     */
+    fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl);
+
+    /** Close the CGC driver.
+     * @par Implemented as
+     * - @ref R_CGC_Close()
+     * @param[in]   p_ctrl          Pointer to instance control block
+     */
+    fsp_err_t (* close)(cgc_ctrl_t * const p_ctrl);
+
+    /** Gets the CGC driver version.
+     * @par Implemented as
+     * - @ref R_CGC_VersionGet()
+     * @param[out]  p_version   Code and API version used
+     */
+    fsp_err_t (* versionGet)(fsp_version_t * p_version);
+} cgc_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_cgc_instance
+{
+    cgc_ctrl_t      * p_ctrl;          ///< Pointer to the control structure for this instance
+    cgc_cfg_t const * p_cfg;           ///< Pointer to the configuration structure for this instance
+    cgc_api_t const * p_api;           ///< Pointer to the API structure for this instance
+} cgc_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup CGC_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_CGC_API_H
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h
new file mode 100644
index 0000000000..604616768c
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_external_irq_api.h
@@ -0,0 +1,170 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup EXTERNAL_IRQ_API External IRQ Interface
+ * @brief Interface for detecting external interrupts.
+ *
+ * @section EXTERNAL_IRQ_API_Summary Summary
+ * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
+ * external IRQ pin.
+ *
+ * The  External IRQ Interface can be implemented by:
+ * - @ref ICU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_EXTERNAL_IRQ_API_H
+#define R_EXTERNAL_IRQ_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ *********************************************************************************************************************/
+#define EXTERNAL_IRQ_API_VERSION_MAJOR    (1U) ///< EXTERNAL IRQ API version number (Major)
+#define EXTERNAL_IRQ_API_VERSION_MINOR    (0U) ///< EXTERNAL IRQ API version number (Minor)
+
+/*********************************************************************************************************************
+ * Typedef definitions
+ *********************************************************************************************************************/
+
+/** Callback function parameter data */
+typedef struct st_external_irq_callback_args
+{
+    /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
+    void const * p_context;
+    uint32_t     channel;              ///< The physical hardware channel that caused the interrupt.
+} external_irq_callback_args_t;
+
+/** Condition that will trigger an interrupt when detected. */
+typedef enum e_external_irq_trigger
+{
+    EXTERNAL_IRQ_TRIG_FALLING   = 0,   ///< Falling edge trigger
+    EXTERNAL_IRQ_TRIG_RISING    = 1,   ///< Rising edge trigger
+    EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2,   ///< Both edges trigger
+    EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3,   ///< Low level trigger
+} external_irq_trigger_t;
+
+/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
+ * conditions that are shorter than 3 periods of the filter clock.
+ */
+typedef enum e_external_irq_pclk_div
+{
+    EXTERNAL_IRQ_PCLK_DIV_BY_1  = 0,   ///< Filter using PCLK divided by 1
+    EXTERNAL_IRQ_PCLK_DIV_BY_8  = 1,   ///< Filter using PCLK divided by 8
+    EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2,   ///< Filter using PCLK divided by 32
+    EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3,   ///< Filter using PCLK divided by 64
+} external_irq_pclk_div_t;
+
+/** User configuration structure, used in open function */
+typedef struct st_external_irq_cfg
+{
+    uint8_t                 channel;   ///< Hardware channel used.
+    uint8_t                 ipl;       ///< Interrupt priority
+    IRQn_Type               irq;       ///< NVIC interrupt number assigned to this instance
+    external_irq_trigger_t  trigger;   ///< Trigger setting.
+    external_irq_pclk_div_t pclk_div;  ///< Digital filter clock divisor setting.
+    bool filter_enable;                ///< Digital filter enable/disable setting.
+
+    /** Callback provided external input trigger occurs. */
+    void (* p_callback)(external_irq_callback_args_t * p_args);
+
+    /** Placeholder for user data.  Passed to the user callback in @ref external_irq_callback_args_t. */
+    void const * p_context;
+    void const * p_extend;             ///< External IRQ hardware dependent configuration.
+} external_irq_cfg_t;
+
+/** External IRQ control block.  Allocate an instance specific control block to pass into the external IRQ API calls.
+ * @par Implemented as
+ * - icu_instance_ctrl_t
+ */
+typedef void external_irq_ctrl_t;
+
+/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
+typedef struct st_external_irq_api
+{
+    /** Initial configuration.
+     * @par Implemented as
+     * - @ref R_ICU_ExternalIrqOpen()
+     *
+     * @param[out]  p_ctrl  Pointer to control block. Must be declared by user. Value set here.
+     * @param[in]   p_cfg   Pointer to configuration structure. All elements of the structure must be set by user.
+     */
+    fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);
+
+    /** Enable callback when an external trigger condition occurs.
+     * @par Implemented as
+     * - @ref R_ICU_ExternalIrqEnable()
+     *
+     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
+     */
+    fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);
+
+    /** Disable callback when external trigger condition occurs.
+     * @par Implemented as
+     * - @ref R_ICU_ExternalIrqDisable()
+     *
+     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
+     */
+    fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);
+
+    /** Allow driver to be reconfigured. May reduce power consumption.
+     * @par Implemented as
+     * - @ref R_ICU_ExternalIrqClose()
+     *
+     * @param[in]  p_ctrl      Control block set in Open call for this external interrupt.
+     */
+    fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
+
+    /** Get version and store it in provided pointer p_version.
+     * @par Implemented as
+     * - @ref R_ICU_ExternalIrqVersionGet()
+     *
+     * @param[out]  p_version  Code and API version used.     */
+    fsp_err_t (* versionGet)(fsp_version_t * const p_version);
+} external_irq_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_external_irq_instance
+{
+    external_irq_ctrl_t      * p_ctrl; ///< Pointer to the control structure for this instance
+    external_irq_cfg_t const * p_cfg;  ///< Pointer to the configuration structure for this instance
+    external_irq_api_t const * p_api;  ///< Pointer to the API structure for this instance
+} external_irq_instance_t;
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup EXTERNAL_IRQ_API)
+ **********************************************************************************************************************/
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h
new file mode 100644
index 0000000000..417985d959
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_flash_api.h
@@ -0,0 +1,358 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup FLASH_API Flash Interface
+ * @brief Interface for the Flash Memory.
+ *
+ * @section FLASH_API_SUMMARY Summary
+ *
+ * The Flash interface provides the ability to read, write, erase, and blank check the code flash and data flash
+ * regions.
+ *
+ * The Flash interface is implemented by:
+ * - @ref FLASH_LP
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_FLASH_API_H
+#define R_FLASH_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ *********************************************************************************************************************/
+
+/* Version Number of API. */
+#define FLASH_API_VERSION_MAJOR    (1U)
+#define FLASH_API_VERSION_MINOR    (0U)
+
+/*********************************************************************************************************************
+ * Typedef definitions
+ *********************************************************************************************************************/
+
+/** Result type for certain operations */
+typedef enum e_flash_result
+{
+    FLASH_RESULT_BLANK,                ///< Return status for Blank Check Function
+    FLASH_RESULT_NOT_BLANK,            ///< Return status for Blank Check Function
+    FLASH_RESULT_BGO_ACTIVE            ///< Flash is configured for BGO mode. Result is returned in callback.
+} flash_result_t;
+
+/** Parameter for specifying the startup area swap being requested by startupAreaSelect() */
+typedef enum e_flash_startup_area_swap
+{
+    FLASH_STARTUP_AREA_BTFLG  = 0,     ///< Startup area will be set based on the value of the BTFLG
+    FLASH_STARTUP_AREA_BLOCK0 = 0x2,   ///< Startup area will be set to Block 0
+    FLASH_STARTUP_AREA_BLOCK1 = 0x3,   ///< Startup area will be set to Block 1
+} flash_startup_area_swap_t;
+
+/** Event types returned by the ISR callback when used in Data Flash BGO mode */
+typedef enum e_flash_event
+{
+    FLASH_EVENT_ERASE_COMPLETE,        ///< Erase operation successfully completed
+    FLASH_EVENT_WRITE_COMPLETE,        ///< Write operation successfully completed
+    FLASH_EVENT_BLANK,                 ///< Blank check operation successfully completed. Specified area is blank
+    FLASH_EVENT_NOT_BLANK,             ///< Blank check operation successfully completed. Specified area is NOT blank
+    FLASH_EVENT_ERR_DF_ACCESS,         ///< Data Flash operation failed. Can occur when writing an unerased section.
+    FLASH_EVENT_ERR_CF_ACCESS,         ///< Code Flash operation failed. Can occur when writing an unerased section.
+    FLASH_EVENT_ERR_CMD_LOCKED,        ///< Operation failed, FCU is in Locked state (often result of an illegal command)
+    FLASH_EVENT_ERR_FAILURE,           ///< Erase or Program Operation failed
+    FLASH_EVENT_ERR_ONE_BIT            ///< A 1-bit error has been corrected when reading the flash memory area by the sequencer.
+} flash_event_t;
+
+/** ID Code Modes for writing to ID code registers */
+typedef enum e_flash_id_code_mode
+{
+    FLASH_ID_CODE_MODE_UNLOCKED = 0,                            ///< ID code is ignored
+    FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT = 0xC000U, ///< ID code is checked. All erase is available.
+    FLASH_ID_CODE_MODE_LOCKED = 0x8000U                         ///< ID code is checked.
+} flash_id_code_mode_t;
+
+/** Flash status */
+typedef enum e_flash_status
+{
+    FLASH_STATUS_IDLE,                 ///< The flash is idle.
+    FLASH_STATUS_BUSY                  ///< The flash is currently processing a command.
+} flash_status_t;
+
+/** Flash block details stored in factory flash. */
+typedef struct st_flash_block_info
+{
+    uint32_t block_section_st_addr;    ///< Starting address for this block section (blocks of this size)
+    uint32_t block_section_end_addr;   ///< Ending address for this block section (blocks of this size)
+    uint32_t block_size;               ///< Flash erase block size
+    uint32_t block_size_write;         ///< Flash write block size
+} flash_block_info_t;
+
+/** Flash block details */
+typedef struct st_flash_regions
+{
+    uint32_t num_regions;                     ///< Length of block info array
+    flash_block_info_t const * p_block_array; ///< Block info array base address
+} flash_regions_t;
+
+/** Information about the flash blocks */
+typedef struct st_flash_info
+{
+    flash_regions_t code_flash;        ///< Information about the code flash regions
+    flash_regions_t data_flash;        ///< Information about the code flash regions
+} flash_info_t;
+
+/** Flash control block.  Allocate an instance specific control block to pass into the flash API calls.
+ * @par Implemented as
+ * - flash_lp_instance_ctrl_t
+ * - flash_hp_instance_ctrl_t
+ */
+typedef void flash_ctrl_t;
+
+/** Callback function parameter data */
+typedef struct st_flash_user_cb_data
+{
+    flash_event_t event;               ///< Event can be used to identify what caused the callback (flash ready or error).
+    void const  * p_context;           ///< Placeholder for user data.  Set in @ref flash_api_t::open function in::flash_cfg_t.
+} flash_callback_args_t;
+
+/** FLASH Configuration */
+typedef struct st_flash_cfg
+{
+    bool data_flash_bgo;                                 ///< True if BGO (Background Operation) is enabled for Data Flash.
+
+    /* Configuration for FLASH Event processing */
+    void (* p_callback)(flash_callback_args_t * p_args); ///< Callback provided when a Flash interrupt ISR occurs.
+
+    /* Pointer to FLASH peripheral specific configuration */
+    void const * p_extend;                               ///< FLASH hardware dependent configuration
+    void const * p_context;                              ///< Placeholder for user data.  Passed to user callback in @ref flash_callback_args_t.
+    uint8_t      ipl;                                    ///< Flash ready interrupt priority
+    IRQn_Type    irq;                                    ///< Flash ready interrupt number
+    uint8_t      err_ipl;                                ///< Flash error interrupt priority (unused in r_flash_lp)
+    IRQn_Type    err_irq;                                ///< Flash error interrupt number (unused in r_flash_lp)
+} flash_cfg_t;
+
+/** Shared Interface definition for FLASH */
+typedef struct st_flash_api
+{
+    /** Open FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_Open()
+     * - @ref R_FLASH_HP_Open()
+     *
+     * @param[out]  p_ctrl       Pointer to FLASH device control. Must be declared by user. Value set here.
+     * @param[in]   flash_cfg_t  Pointer to FLASH configuration structure. All elements of this structure
+     *                           must be set by the user.
+     */
+    fsp_err_t (* open)(flash_ctrl_t * const p_ctrl, flash_cfg_t const * const p_cfg);
+
+    /** Write FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_Write()
+     * - @ref R_FLASH_HP_Write()
+     *
+     * @param[in]   p_ctrl         Control for the FLASH device context.
+     * @param[in]   src_address    Address of the buffer containing the data to write to Flash.
+     * @param[in]   flash_address  Code Flash or Data Flash address to write. The address must be on a
+     *                             programming line boundary.
+     * @param[in]   num_bytes      The number of bytes to write. This number must be a multiple
+     *                             of the programming size. For Code Flash this is FLASH_MIN_PGM_SIZE_CF.
+     *                             For Data Flash this is FLASH_MIN_PGM_SIZE_DF.
+     *                             @warning Specifying a number that is not a multiple of the programming size
+     *                             will result in SF_FLASH_ERR_BYTES being returned and no data written.
+     */
+    fsp_err_t (* write)(flash_ctrl_t * const p_ctrl, uint32_t const src_address, uint32_t const flash_address,
+                        uint32_t const num_bytes);
+
+    /** Erase FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_Erase()
+     * - @ref R_FLASH_HP_Erase()
+     *
+     * @param[in]  p_ctrl               Control for the FLASH device.
+     * @param[in]  address              The block containing this address is the first block erased.
+     * @param[in]  num_blocks           Specifies the number of blocks to be erased, the starting block determined
+     *                                  by the block_erase_address.
+     */
+    fsp_err_t (* erase)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_blocks);
+
+    /** Blank check FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_BlankCheck()
+     * - @ref R_FLASH_HP_BlankCheck()
+     *
+     * @param[in]   p_ctrl    Control for the FLASH device context.
+     * @param[in]   address   The starting address of the Flash area to blank check.
+     * @param[in]   num_bytes Specifies the number of bytes that need to be checked.
+     *                        See the specific handler for details.
+     * @param[out]  p_blank_check_result  Pointer that will be populated by the API with the results of the blank check
+     *                                    operation in non-BGO (blocking) mode. In this case the blank check operation
+     *                                    completes here and the result is returned. In Data Flash BGO mode the blank
+     *                                    check operation is only started here and the result obtained later when the
+     *                                    supplied callback routine is called. In this case FLASH_RESULT_BGO_ACTIVE will
+     *                                    be returned in p_blank_check_result.
+     */
+    fsp_err_t (* blankCheck)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_bytes,
+                             flash_result_t * const p_blank_check_result);
+
+    /** Close FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_InfoGet()
+     * - @ref R_FLASH_HP_InfoGet()
+     *
+     * @param[in]   p_ctrl        Pointer to FLASH device control.
+     * @param[out]  p_info        Pointer to FLASH info structure.
+     */
+    fsp_err_t (* infoGet)(flash_ctrl_t * const p_ctrl, flash_info_t * const p_info);
+
+    /** Close FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_Close()
+     * - @ref R_FLASH_HP_Close()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     */
+    fsp_err_t (* close)(flash_ctrl_t * const p_ctrl);
+
+    /** Get Status for FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_StatusGet()
+     * - @ref R_FLASH_HP_StatusGet()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     * @param[out]  p_ctrl       Pointer to the current flash status.
+     */
+    fsp_err_t (* statusGet)(flash_ctrl_t * const p_ctrl, flash_status_t * const p_status);
+
+    /** Set Access Window for FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_AccessWindowSet()
+     * - @ref R_FLASH_HP_AccessWindowSet()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     * @param[in]  start_addr    Determines the Starting block for the Code Flash access window.
+     * @param[in]  end_addr      Determines the Ending block for the Code Flash access window. This address will not be
+     *                           within the access window.
+     */
+    fsp_err_t (* accessWindowSet)(flash_ctrl_t * const p_ctrl, uint32_t const start_addr, uint32_t const end_addr);
+
+    /** Clear any existing Code Flash access window for FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_AccessWindowClear()
+     * - @ref R_FLASH_HP_AccessWindowClear()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     * @param[in]  start_addr    Determines the Starting block for the Code Flash access window.
+     * @param[in]  end_addr      Determines the Ending block for the Code Flash access window.
+     */
+    fsp_err_t (* accessWindowClear)(flash_ctrl_t * const p_ctrl);
+
+    /** Set ID Code for FLASH device. Setting the ID code can restrict access to the device. The ID code will be
+     * required to connect to the device. Bits 126 and 127 are set based on the mode.
+     *
+     * For example, uint8_t id_bytes[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+     *                            0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x00};
+     * with mode FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT
+     * will result in an ID code of 00112233445566778899aabbccddeec0
+     *
+     * With mode FLASH_ID_CODE_MODE_LOCKED, it
+     * will result in an ID code of 00112233445566778899aabbccddee80
+     *
+     * @par Implemented as
+     * - @ref R_FLASH_LP_IdCodeSet()
+     * - @ref R_FLASH_HP_IdCodeSet()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     * @param[in]  p_id_bytes    Ponter to the ID Code to be written.
+     * @param[in]  mode          Mode used for checking the ID code.
+     */
+    fsp_err_t (* idCodeSet)(flash_ctrl_t * const p_ctrl, uint8_t const * const p_id_bytes, flash_id_code_mode_t mode);
+
+    /** Reset function for FLASH device.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_Reset()
+     * - @ref R_FLASH_HP_Reset()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     */
+    fsp_err_t (* reset)(flash_ctrl_t * const p_ctrl);
+
+    /** Update Flash clock frequency (FCLK) and recalculate timeout values
+     * @par Implemented as
+     * - @ref R_FLASH_LP_UpdateFlashClockFreq()
+     * - @ref R_FLASH_HP_UpdateFlashClockFreq()
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     */
+    fsp_err_t (* updateFlashClockFreq)(flash_ctrl_t * const p_ctrl);
+
+    /** Select which block - Default (Block 0) or Alternate (Block 1) is used as the start-up area block.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_StartUpAreaSelect()
+     * - @ref R_FLASH_HP_StartUpAreaSelect()
+     *
+     * @param[in]  p_ctrl        Pointer to FLASH device control.
+     * @param[in]  swap_type     FLASH_STARTUP_AREA_BLOCK0, FLASH_STARTUP_AREA_BLOCK1 or FLASH_STARTUP_AREA_BTFLG.
+     * @param[in]  is_temporary  True or false. See table below.
+     *
+     * | swap_type             |    is_temporary |   Operation |
+     * |-----------------------|-----------------|-------------|
+     * | FLASH_STARTUP_AREA_BLOCK0 |  false  |     On next reset Startup area will be Block 0. |
+     * | FLASH_STARTUP_AREA_BLOCK1 |  true   |     Startup area is immediately, but temporarily switched to Block 1. |
+     * | FLASH_STARTUP_AREA_BTFLG  |  true   |     Startup area is immediately, but temporarily switched to the Block determined by the Configuration BTFLG. |
+     *
+     */
+    fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type,
+                                    bool is_temporary);
+
+    /** Get Flash driver version.
+     * @par Implemented as
+     * - @ref R_FLASH_LP_VersionGet()
+     * - @ref R_FLASH_HP_VersionGet()
+     *
+     * @param[out]  p_version Returns version.
+     */
+    fsp_err_t (* versionGet)(fsp_version_t * p_version);
+} flash_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_flash_instance
+{
+    flash_ctrl_t      * p_ctrl;        ///< Pointer to the control structure for this instance
+    flash_cfg_t const * p_cfg;         ///< Pointer to the configuration structure for this instance
+    flash_api_t const * p_api;         ///< Pointer to the API structure for this instance
+} flash_instance_t;
+
+/******************************************************************************************************************//**
+ * @} (end defgroup FLASH_API)
+ *********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h
new file mode 100644
index 0000000000..245774889a
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_ioport_api.h
@@ -0,0 +1,362 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup IOPORT_API I/O Port Interface
+ * @brief Interface  for accessing I/O ports and configuring I/O functionality.
+ *
+ * @section IOPORT_API_SUMMARY Summary
+ * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
+ * Port and pin direction can be changed.
+ *
+ * IOPORT Interface description: @ref IOPORT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_IOPORT_API_H
+#define R_IOPORT_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Common error codes and definitions. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define IOPORT_API_VERSION_MAJOR      (1U)
+#define IOPORT_API_VERSION_MINOR      (0U)
+
+/* Private definition to set enumeration values. */
+#define IOPORT_PRV_PFS_PSEL_OFFSET    (24)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** IO port type used with ports */
+typedef uint16_t ioport_size_t;        ///< IO port size on this device
+
+/** Superset of all peripheral functions.  */
+typedef enum e_ioport_peripheral
+{
+    /** Pin will functions as an IO pin */
+    IOPORT_PERIPHERAL_IO = 0x00,
+
+    /** Pin will function as a DEBUG pin */
+    IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an AGT peripheral pin */
+    IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a GPT peripheral pin */
+    IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a GPT peripheral pin */
+    IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an SCI peripheral pin */
+    IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an SCI peripheral pin */
+    IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a SPI peripheral pin */
+    IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a IIC peripheral pin */
+    IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a KEY peripheral pin */
+    IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a clock/comparator/RTC peripheral pin */
+    IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a CAC/ADC peripheral pin */
+    IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a BUS peripheral pin */
+    IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a CTSU peripheral pin */
+    IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a segment LCD peripheral pin */
+    IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a DALI peripheral pin */
+    IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a CAN peripheral pin */
+    IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a QSPI peripheral pin */
+    IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an SSI peripheral pin */
+    IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a USB full speed peripheral pin */
+    IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a USB high speed peripheral pin */
+    IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an SD/MMC peripheral pin */
+    IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an Ethernet MMI peripheral pin */
+    IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as an Ethernet RMMI peripheral pin */
+    IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a PDC peripheral pin */
+    IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a graphics LCD peripheral pin */
+    IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Pin will function as a debug trace peripheral pin */
+    IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+    /** Marks end of enum - used by parameter checking */
+    IOPORT_PERIPHERAL_END
+} ioport_peripheral_t;
+
+/** Superset of Ethernet channels. */
+typedef enum e_ioport_eth_ch
+{
+    IOPORT_ETHERNET_CHANNEL_0 = 0x10,  ///< Used to select Ethernet channel 0
+    IOPORT_ETHERNET_CHANNEL_1 = 0x20,  ///< Used to select Ethernet channel 1
+    IOPORT_ETHERNET_CHANNEL_END        ///< Marks end of enum - used by parameter checking
+} ioport_ethernet_channel_t;
+
+/** Superset of Ethernet PHY modes. */
+typedef enum e_ioport_eth_mode
+{
+    IOPORT_ETHERNET_MODE_RMII = 0x00,  ///< Ethernet PHY mode set to MII
+    IOPORT_ETHERNET_MODE_MII  = 0x10,  ///< Ethernet PHY mode set to RMII
+    IOPORT_ETHERNET_MODE_END           ///< Marks end of enum - used by parameter checking
+} ioport_ethernet_mode_t;
+
+/** Options to configure pin functions  */
+typedef enum e_ioport_cfg_options
+{
+    IOPORT_CFG_PORT_DIRECTION_INPUT  = 0x00000000, ///< Sets the pin direction to input (default)
+    IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output
+    IOPORT_CFG_PORT_OUTPUT_LOW       = 0x00000000, ///< Sets the pin level to low
+    IOPORT_CFG_PORT_OUTPUT_HIGH      = 0x00000001, ///< Sets the pin level to high
+    IOPORT_CFG_PULLUP_ENABLE         = 0x00000010, ///< Enables the pin's internal pull-up
+    IOPORT_CFG_PIM_TTL               = 0x00000020, ///< Enables the pin's input mode
+    IOPORT_CFG_NMOS_ENABLE           = 0x00000040, ///< Enables the pin's NMOS open-drain output
+    IOPORT_CFG_PMOS_ENABLE           = 0x00000080, ///< Enables the pin's PMOS open-drain ouput
+    IOPORT_CFG_DRIVE_MID             = 0x00000400, ///< Sets pin drive output to medium
+    IOPORT_CFG_DRIVE_MID_IIC         = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port
+    IOPORT_CFG_DRIVE_HIGH            = 0x00000C00, ///< Sets pin drive output to high
+    IOPORT_CFG_EVENT_RISING_EDGE     = 0x00001000, ///< Sets pin event trigger to rising edge
+    IOPORT_CFG_EVENT_FALLING_EDGE    = 0x00002000, ///< Sets pin event trigger to falling edge
+    IOPORT_CFG_EVENT_BOTH_EDGES      = 0x00003000, ///< Sets pin event trigger to both edges
+    IOPORT_CFG_IRQ_ENABLE            = 0x00004000, ///< Sets pin as an IRQ pin
+    IOPORT_CFG_ANALOG_ENABLE         = 0x00008000, ///< Enables pin to operate as an analog pin
+    IOPORT_CFG_PERIPHERAL_PIN        = 0x00010000  ///< Enables pin to operate as a peripheral pin
+} ioport_cfg_options_t;
+
+/* PFS writing enable/disable. */
+typedef enum e_ioport_pwpr
+{
+    IOPORT_PFS_WRITE_DISABLE = 0,      ///< Disable PFS write access
+    IOPORT_PFS_WRITE_ENABLE  = 1       ///< Enable PFS write access
+} ioport_pwpr_t;
+
+/** Pin identifier and pin PFS pin configuration value */
+typedef struct st_ioport_pin_cfg
+{
+    uint32_t          pin_cfg;         ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
+    bsp_io_port_pin_t pin;             ///< Pin identifier
+} ioport_pin_cfg_t;
+
+/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init()  */
+typedef struct st_ioport_cfg
+{
+    uint16_t                 number_of_pins; ///< Number of pins for which there is configuration data
+    ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
+} ioport_cfg_t;
+
+/** IOPORT control block.  Allocate an instance specific control block to pass into the IOPORT API calls.
+ * @par Implemented as
+ * - ioport_instance_ctrl_t
+ */
+typedef void ioport_ctrl_t;
+
+/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
+typedef struct st_ioport_api
+{
+    /** Initialize internal driver data and initial pin configurations.  Called during startup.  Do
+     * not call this API during runtime.  Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
+     * multiple pins.
+     * @par Implemented as
+     * - @ref R_IOPORT_Open()
+     * @param[in]  p_cfg                Pointer to pin configuration data array.
+     */
+    fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+
+    /** Close the API.
+     * @par Implemented as
+     * - @ref R_IOPORT_Close()
+     *
+     * @param[in]   p_ctrl  Pointer to control structure.
+     **/
+    fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
+
+    /** Configure multiple pins.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinsCfg()
+     * @param[in]  p_cfg                Pointer to pin configuration data array.
+     */
+    fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+
+    /** Configure settings for an individual pin.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinCfg()
+     * @param[in]  pin                  Pin to be read.
+     * @param[in]  cfg                  Configuration options for the pin.
+     */
+    fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
+
+    /** Read the event input data of the specified pin and return the level.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinEventInputRead()
+     * @param[in]  pin                  Pin to be read.
+     * @param[in]  p_pin_event         Pointer to return the event data.
+     */
+    fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
+
+    /** Write pin event data.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinEventOutputWrite()
+     * @param[in]  pin                  Pin event data is to be written to.
+     * @param[in]  pin_value            Level to be written to pin output event.
+     */
+    fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
+
+    /** Configure the PHY mode of the Ethernet channels.
+     * @par Implemented as
+     * - @ref R_IOPORT_EthernetModeCfg()
+     * @param[in]  channel              Channel configuration will be set for.
+     * @param[in]  mode                 PHY mode to set the channel to.
+     */
+    fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
+                                     ioport_ethernet_mode_t mode);
+
+    /** Read level of a pin.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinRead()
+     * @param[in]  pin                  Pin to be read.
+     * @param[in]  p_pin_value          Pointer to return the pin level.
+     */
+    fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
+
+    /** Write specified level to a pin.
+     * @par Implemented as
+     * - @ref R_IOPORT_PinWrite()
+     * @param[in]  pin                  Pin to be written to.
+     * @param[in]  level                State to be written to the pin.
+     */
+    fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
+
+    /** Set the direction of one or more pins on a port.
+     * @par Implemented as
+     * - @ref R_IOPORT_PortDirectionSet()
+     * @param[in]  port                 Port being configured.
+     * @param[in]  direction_values     Value controlling direction of pins on port (1 - output, 0 - input).
+     * @param[in]  mask                 Mask controlling which pins on the port are to be configured.
+     */
+    fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
+                                   ioport_size_t mask);
+
+    /** Read captured event data for a port.
+     * @par Implemented as
+     * - @ref R_IOPORT_PortEventInputRead()
+     * @param[in]  port                 Port to be read.
+     * @param[in]  p_event_data         Pointer to return the event data.
+     */
+    fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
+
+    /** Write event output data for a port.
+     * @par Implemented as
+     * - @ref R_IOPORT_PortEventOutputWrite()
+     * @param[in]  port                 Port event data will be written to.
+     * @param[in]  event_data           Data to be written as event data to specified port.
+     * @param[in]  mask_value           Each bit set to 1 in the mask corresponds to that bit's value in event data.
+     * being written to port.
+     */
+    fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
+                                       ioport_size_t mask_value);
+
+    /** Read states of pins on the specified port.
+     * @par Implemented as
+     * - @ref R_IOPORT_PortRead()
+     * @param[in]  port                 Port to be read.
+     * @param[in]  p_port_value         Pointer to return the port value.
+     */
+    fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
+
+    /** Write to multiple pins on a port.
+     * @par Implemented as
+     * - @ref R_IOPORT_PortWrite()
+     * @param[in]  port                 Port to be written to.
+     * @param[in]  value                Value to be written to the port.
+     * @param[in]  mask                 Mask controlling which pins on the port are written to.
+     */
+    fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
+
+    /** Return the version of the IOPort driver.
+     * @par Implemented as
+     * - @ref R_IOPORT_VersionGet()
+     * @param[out]  p_data              Memory address to return version information to.
+     */
+    fsp_err_t (* versionGet)(fsp_version_t * p_data);
+} ioport_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ioport_instance
+{
+    ioport_ctrl_t      * p_ctrl;       ///< Pointer to the control structure for this instance
+    ioport_cfg_t const * p_cfg;        ///< Pointer to the configuration structure for this instance
+    ioport_api_t const * p_api;        ///< Pointer to the API structure for this instance
+} ioport_instance_t;
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup IOPORT_API)
+ **********************************************************************************************************************/
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h
new file mode 100644
index 0000000000..5703366216
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/r_timer_api.h
@@ -0,0 +1,321 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef R_TIMER_API_H
+#define R_TIMER_API_H
+
+/*******************************************************************************************************************//**
+ * @defgroup TIMER_API Timer Interface
+ * @ingroup RENESAS_INTERFACES
+ * @brief Interface for timer functions.
+ *
+ * @section TIMER_API_SUMMARY Summary
+ * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output,
+ * and free-running timer mode.  After each timer cycle (overflow or underflow), an interrupt can be triggered.
+ *
+ * If an instance supports output compare mode, it is provided in the extension configuration
+ * timer_on__cfg_t defined in r_.h.
+ *
+ * Implemented by:
+ * - @ref GPT
+ * - @ref AGT
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Leading zeroes removed to avoid coding standard violation. */
+#define TIMER_API_VERSION_MAJOR    (1U)
+#define TIMER_API_VERSION_MINOR    (1U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Events that can trigger a callback function */
+typedef enum e_timer_event
+{
+    TIMER_EVENT_CYCLE_END,                     ///< Requested timer delay has expired or timer has wrapped around
+    TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only)
+    TIMER_EVENT_CAPTURE_A,                     ///< A capture has occurred on signal A
+    TIMER_EVENT_CAPTURE_B,                     ///< A capture has occurred on signal B
+    TIMER_EVENT_TROUGH,                        ///< Timer trough event (counter is 0, triangle-wave PWM only
+} timer_event_t;
+
+/** Timer variant types. */
+typedef enum e_timer_variant
+{
+    TIMER_VARIANT_32_BIT,              ///< 32-bit timer
+    TIMER_VARIANT_16_BIT               ///< 16-bit timer
+} timer_variant_t;
+
+/** Callback function parameter data */
+typedef struct st_timer_callback_args
+{
+    /** Placeholder for user data.  Set in @ref timer_api_t::open function in @ref timer_cfg_t. */
+    void const  * p_context;
+    timer_event_t event;               ///< The event can be used to identify what caused the callback.
+
+    /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */
+    uint32_t capture;
+} timer_callback_args_t;
+
+/** Timer control block.  Allocate an instance specific control block to pass into the timer API calls.
+ * @par Implemented as
+ * - gpt_instance_ctrl_t
+ * - agt_instance_ctrl_t
+ */
+typedef void timer_ctrl_t;
+
+/** Possible status values returned by @ref timer_api_t::statusGet. */
+typedef enum e_timer_state
+{
+    TIMER_STATE_STOPPED  = 0,          ///< Timer is stopped
+    TIMER_STATE_COUNTING = 1,          ///< Timer is running
+} timer_state_t;
+
+/** Timer operational modes */
+typedef enum e_timer_mode
+{
+    TIMER_MODE_PERIODIC,                          ///< Timer restarts after period elapses.
+    TIMER_MODE_ONE_SHOT,                          ///< Timer stops after period elapses.
+    TIMER_MODE_PWM,                               ///< Timer generates saw-wave PWM output.
+    TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM  = 4U, ///< Timer generates symmetric triangle-wave PWM output.
+    TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output.
+} timer_mode_t;
+
+/** Direction of timer count */
+typedef enum e_timer_direction
+{
+    TIMER_DIRECTION_DOWN = 0,          ///< Timer count goes up
+    TIMER_DIRECTION_UP   = 1           ///< Timer count goes down
+} timer_direction_t;
+
+/** PCLK divisors */
+typedef enum e_timer_source_div
+{
+    TIMER_SOURCE_DIV_1    = 0,         ///< Timer clock source divided by 1
+    TIMER_SOURCE_DIV_2    = 1,         ///< Timer clock source divided by 2
+    TIMER_SOURCE_DIV_4    = 2,         ///< Timer clock source divided by 4
+    TIMER_SOURCE_DIV_8    = 3,         ///< Timer clock source divided by 8
+    TIMER_SOURCE_DIV_16   = 4,         ///< Timer clock source divided by 16
+    TIMER_SOURCE_DIV_32   = 5,         ///< Timer clock source divided by 32
+    TIMER_SOURCE_DIV_64   = 6,         ///< Timer clock source divided by 64
+    TIMER_SOURCE_DIV_128  = 7,         ///< Timer clock source divided by 128
+    TIMER_SOURCE_DIV_256  = 8,         ///< Timer clock source divided by 256
+    TIMER_SOURCE_DIV_1024 = 10,        ///< Timer clock source divided by 1024
+} timer_source_div_t;
+
+/** Timer information structure to store various information for a timer resource */
+typedef struct st_timer_info
+{
+    timer_direction_t count_direction; ///< Clock counting direction of the timer.
+    uint32_t          clock_frequency; ///< Clock frequency of the timer counter.
+
+    /** Period in raw timer counts.
+     * @note For triangle wave PWM modes, the full period is double this value.
+     */
+    uint32_t period_counts;
+} timer_info_t;
+
+/** Current timer status. */
+typedef struct st_timer_status
+{
+    uint32_t      counter;             ///< Current counter value
+    timer_state_t state;               ///< Current timer state (running or stopped)
+} timer_status_t;
+
+/** User configuration structure, used in open function */
+typedef struct st_timer_cfg
+{
+    timer_mode_t mode;                    ///< Select enumerated value from @ref timer_mode_t
+
+    /* Period in raw timer counts.
+     * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period.
+     */
+    uint32_t           period_counts;     ///< Period in raw timer counts
+    timer_source_div_t source_div;        ///< Source clock divider
+    uint32_t           duty_cycle_counts; ///< Duty cycle in counts
+
+    /** Select a channel corresponding to the channel number of the hardware. */
+    uint8_t   channel;
+    uint8_t   cycle_end_ipl;              ///< Cycle end interrupt priority
+    IRQn_Type cycle_end_irq;              ///< Cycle end interrupt
+
+    /** Callback provided when a timer ISR occurs.  Set to NULL for no CPU interrupt. */
+    void (* p_callback)(timer_callback_args_t * p_args);
+
+    /** Placeholder for user data.  Passed to the user callback in @ref timer_callback_args_t. */
+    void const * p_context;
+    void const * p_extend;             ///< Extension parameter for hardware specific settings.
+} timer_cfg_t;
+
+/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */
+typedef struct st_timer_api
+{
+    /** Initial configuration.
+     * @par Implemented as
+     * - @ref R_GPT_Open()
+     * - @ref R_AGT_Open()
+     *
+     * @param[in]   p_ctrl     Pointer to control block. Must be declared by user. Elements set here.
+     * @param[in]   p_cfg      Pointer to configuration structure. All elements of this structure must be set by user.
+     */
+    fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+
+    /** Start the counter.
+     * @par Implemented as
+     * - @ref R_GPT_Start()
+     * - @ref R_AGT_Start()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* start)(timer_ctrl_t * const p_ctrl);
+
+    /** Stop the counter.
+     * @par Implemented as
+     * - @ref R_GPT_Stop()
+     * - @ref R_AGT_Stop()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl);
+
+    /** Reset the counter to the initial value.
+     * @par Implemented as
+     * - @ref R_GPT_Reset()
+     * - @ref R_AGT_Reset()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl);
+
+    /** Enables input capture.
+     * @par Implemented as
+     * - @ref R_GPT_Enable()
+     * - @ref R_AGT_Enable()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl);
+
+    /** Disables input capture.
+     * @par Implemented as
+     * - @ref R_GPT_Disable()
+     * - @ref R_AGT_Disable()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl);
+
+    /** Set the time until the timer expires.  See implementation for details of period update timing.
+     *
+     * @par Implemented as
+     * - @ref R_GPT_PeriodSet()
+     * - @ref R_AGT_PeriodSet()
+     *
+     * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in
+     * @ref timer_api_t::open.
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[in]   p_period   Time until timer should expire.
+     */
+    fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period);
+
+    /** Sets the number of counts for the pin level to be high.  If the timer is counting, the updated duty cycle is
+     * reflected after the next timer expiration.
+     *
+     * @par Implemented as
+     * - @ref R_GPT_DutyCycleSet()
+     * - @ref R_AGT_DutyCycleSet()
+     *
+     * @param[in]   p_ctrl             Control block set in @ref timer_api_t::open call for this timer.
+     * @param[in]   duty_cycle_counts  Time until duty cycle should expire.
+     * @param[in]   pin                Which output pin to update.  See implementation for details.
+     */
+    fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+
+    /** Stores timer information in p_info.
+     * @par Implemented as
+     * - @ref R_GPT_InfoGet()
+     * - @ref R_AGT_InfoGet()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[out]  p_info     Collection of information for this timer.
+     */
+    fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+
+    /** Get the current counter value and timer state and store it in p_status.
+     * @par Implemented as
+     * - @ref R_GPT_StatusGet()
+     * - @ref R_AGT_StatusGet()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     * @param[out]  p_status   Current status of this timer.
+     */
+    fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+
+    /** Allows driver to be reconfigured and may reduce power consumption.
+     * @par Implemented as
+     * - @ref R_GPT_Close()
+     * - @ref R_AGT_Close()
+     *
+     * @param[in]   p_ctrl     Control block set in @ref timer_api_t::open call for this timer.
+     */
+    fsp_err_t (* close)(timer_ctrl_t * const p_ctrl);
+
+    /** Get version and store it in provided pointer p_version.
+     * @par Implemented as
+     * - @ref R_GPT_VersionGet()
+     * - @ref R_AGT_VersionGet()
+     *
+     * @param[out]  p_version  Code and API version used.
+     */
+    fsp_err_t (* versionGet)(fsp_version_t * const p_version);
+} timer_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_timer_instance
+{
+    timer_ctrl_t      * p_ctrl;        ///< Pointer to the control structure for this instance
+    timer_cfg_t const * p_cfg;         ///< Pointer to the configuration structure for this instance
+    timer_api_t const * p_api;         ///< Pointer to the API structure for this instance
+} timer_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup TIMER_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h
new file mode 100644
index 0000000000..d41cc08f3b
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/api/rm_ble_abs_api.h
@@ -0,0 +1,867 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef RM_BLE_ABS_API_H
+#define RM_BLE_ABS_API_H
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_INTERFACES
+ * @defgroup BLE_ABS_API BLE ABS Interface
+ * @brief Interface for Bluetooth Low Energy Abstraction functions.
+ *
+ * @section BLE_ABS_API_Summary Summary
+ * The BLE ABS interface for the Bluetooth Low Energy Abstraction (BLE ABS) peripheral provides Bluetooth Low Energy Abstraction functionality.
+ *
+ * The Bluetooth Low Energy Abstraction interface can be implemented by:
+ * - @ref BLE_ABS
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Register definitions, common services and error codes. */
+#include "bsp_api.h"
+#include "r_ble_api.h"
+#include "r_flash_api.h"
+#include "r_timer_api.h"
+
+#include "fsp_common_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BLE_ABS_API_VERSION_MAJOR         (1U)
+#define BLE_ABS_API_VERSION_MINOR         (0U)
+
+#define BLE_ABS_ADVERTISING_PHY_LEGACY    (0x00) ///< Non-Connectable Legacy Advertising phy setting.
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Advertising Filter Policy */
+typedef enum e_ble_abs_advertising_filter
+{
+    BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY        = 0x00, ///< Receive a connect request from all devices.
+    BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST = 0x01, ///< Receive a connect request from only the devices registered in White List.
+} ble_abs_advertising_filter_t;
+
+#define BLE_BD_ADDR_LEN    (0x06)
+
+/** st_ble_device_address is the type of bluetooth device address(BD_ADDR). */
+typedef struct st_ble_device_address
+{
+    uint8_t addr[BLE_BD_ADDR_LEN];     ///< bluetooth device address.
+    uint8_t type;                      ///< the type of bluetooth device address.
+} ble_device_address_t;
+
+/** ble_gap_application_callback_t is the GAP Event callback function type. */
+typedef void (* ble_gap_application_callback_t)(uint16_t event_type, ble_status_t event_result,
+                                                st_ble_evt_data_t * p_event_data);
+
+/** ble_vendor_specific_application_callback_t is the Vendor Specific Event callback function type. */
+typedef void (* ble_vendor_specific_application_callback_t)(uint16_t event_type, ble_status_t event_result,
+                                                            st_ble_vs_evt_data_t * p_event_data);
+
+/** ble_gatt_server_application_callback_t is the GATT Server Event callback function type. */
+typedef void (* ble_gatt_server_application_callback_t)(uint16_t event_type, ble_status_t event_result,
+                                                        st_ble_gatts_evt_data_t * p_event_data);
+
+/** ble_gatt_client_application_callback_t is the GATT Server Event callback function type. */
+typedef void (* ble_gatt_client_application_callback_t)(uint16_t event_type, ble_status_t event_result,
+                                                        st_ble_gattc_evt_data_t * p_event_data);
+
+/** ble_gap_connection_parameter_t is Connection parameters included in connection interval, slave latency, supervision timeout, ce length. */
+typedef struct st_ble_gap_connection_parameter
+{
+    uint16_t conn_intv_min;            ///< Minimum connection interval.
+    uint16_t conn_intv_max;            ///< Maximum connection interval.
+    uint16_t conn_latency;             ///< Slave latency.
+    uint16_t sup_to;                   ///< Supervision timeout.
+    uint16_t min_ce_length;            ///< Minimum CE Length.
+    uint16_t max_ce_length;            ///< Maximum CE Length.
+} ble_gap_connection_parameter_t;
+
+/** ble_gap_connection_phy_parameter_t is Connection parameters per PHY. */
+typedef struct st_ble_gap_connection_phy_parameter
+{
+    uint16_t scan_intv;                            ///< Scan interval.
+    uint16_t scan_window;                          ///< Scan window.
+    ble_gap_connection_parameter_t * p_conn_param; ///< Connection interval, slave latency, supervision timeout, and CE length.
+} ble_gap_connection_phy_parameter_t;
+
+/** Scan parameters per scan PHY. */
+typedef struct st_ble_gap_scan_phy_parameter
+{
+    uint8_t  scan_type;                ///< Scan type.
+    uint16_t scan_intv;                ///< Scan interval.
+    uint16_t scan_window;              ///< Scan window.
+} ble_gap_scan_phy_parameter_t;
+
+/**  Parameters configured when scanning starts. */
+typedef struct st_ble_gap_scan_on
+{
+    uint8_t  proc_type;                ///< Procedure type.
+    uint8_t  filter_dups;              ///< Filter duplicates.
+    uint16_t duration;                 ///< Scan duration.
+    uint16_t period;                   ///< Scan period.
+} ble_gap_scan_on_t;
+
+/** Callback function parameter data */
+typedef struct st_ble_abs_callback_args
+{
+    uint32_t       channel;            ///< Select a channel corresponding to the channel number of the hardware.
+    ble_event_cb_t ble_abs_event;      ///< The event can be used to identify what caused the callback.
+    void const   * p_context;          ///< Placeholder for user data.  Set in ble_abs_api_t::open function in ::ble_abs_cfg_t.
+} ble_abs_callback_args_t;
+
+/** BLE ABS control block.  Allocate an instance specific control block to pass into the BLE ABS API calls.
+ * @par Implemented as
+ * - ble_abs_instance_ctrl_t
+ */
+typedef void ble_abs_ctrl_t;
+
+/** st_ble_abs_pairing_parameter_t includes the pairing parameters. */
+typedef struct st_ble_abs_pairing_parameter
+{
+    uint8_t io_capabilitie_local_device; ///< IO capabilities of local device.
+    uint8_t mitm_protection_policy;      ///< MITM protection policy.
+    uint8_t secure_connection_only;      ///< Determine whether to accept only Secure Connections or not.
+    uint8_t local_key_distribute;        ///< Type of keys to be distributed from local device.
+    uint8_t remote_key_distribute;       ///< Type of keys which local device requests a remote device to distribute.
+    uint8_t maximum_key_size;            ///< Maximum LTK size.
+    uint8_t padding[2];                  ///< padding
+} ble_abs_pairing_parameter_t;
+
+/** GATT Server callback function and the priority. */
+typedef struct st_ble_abs_gatt_server_callback_set
+{
+    ble_gatt_server_application_callback_t gatt_server_callback_function; ///< GATT Server callback function.
+    uint8_t gatt_server_callback_priority;                                ///< The priority number of GATT Server callback function.
+} ble_abs_gatt_server_callback_set_t;
+
+/** GATT Client callback function and the priority. */
+typedef struct st_ble_abs_gatt_client_callback_set
+{
+    ble_gatt_client_application_callback_t gatt_client_callback_function; ///< GATT Client callback function.
+    uint8_t gatt_client_callback_priority;                                ///< The priority number of GATT Client callback function.
+} ble_abs_gatt_client_callback_set_t;
+
+/** st_ble_abs_legacy_advertising_parameter_t is the parameters for legacy advertising. */
+typedef struct st_ble_abs_legacy_advertising_parameter
+{
+    /**
+     *  @brief The remote device address.\n
+     *  If the p_peer_address parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n
+     *  If the p_peer_address parameter is NULL, Undirect Connectable Advertising is performed according to \n
+     *  the advertising filter policy specified by the filter parameter.
+     */
+    ble_device_address_t * p_peer_address;
+
+    /**
+     *  @brief Advertising Data. \n
+     *  If the p_advertising_data is specified as NULL, Advertising Data is not included in the advertising PDU.
+     */
+    uint8_t * p_advertising_data;
+
+    /**
+     *  @brief Scan Response Data. \n
+     *  If the p_scan_response_data is specified as NULL, Scan Response Data is not included in the advertising PDU.
+     */
+    uint8_t * p_scan_response_data;
+
+    /**
+     *  @brief  Advertising with the fast_advertising_interval parameter continues for the period specified \n
+     *  by the fast_period parameter.\n
+     *  Time(ms) = fast_advertising_interval * 0.625. \n
+     *  If the fast_period parameter is 0, this parameter is ignored.\n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t fast_advertising_interval;
+
+    /**
+     *  @brief After the elapse of the fast_period, advertising with the slow_advertising_interval parameter continues \n
+     *  for the period specified by the slow_advertising_interval parameter.\n
+     *  Time(ms) = slow_advertising_interval * 0.625. \n
+     *  If the slow_advertising_interval parameter is 0, this parameter is ignored.\n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t slow_advertising_interval;
+
+    /**
+     *  @brief The period which advertising with the fast_advertising_interval parameter continues for. \n
+     *  Time = duration * 10ms.\n
+     *  After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped.\n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the fast_advertising_period parameter is 0x0000, advertising with the fast_advertising_interval parameter is not performed.
+     */
+    uint16_t fast_advertising_period;
+
+    /**
+     *  @brief The period which advertising with the slow_advertising_interval parameter continues for. Time = duration * 10ms. \n
+     *  After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the slow_advertising_period parameter is 0x0000, the advertising continues.
+     */
+    uint16_t slow_advertising_period;
+
+    /**
+     *  @brief Advertising data length(byte). \n
+     *  Valid range is 0-31.  \n
+     *  If the advertising_data_length is 0, Advertising Data is not included in the advertising PDU.
+     */
+    uint16_t advertising_data_length;
+
+    /**
+     *  @brief Scan response data length (in bytes). \n
+     *  Scan Response Data(byte). \n
+     *  Valid range is 0-31. \n
+     *  If the scan_response_data_length is 0, Scan Response Data is not included in the advertising PDU.
+     */
+    uint16_t scan_response_data_length;
+
+    /**
+     *  @brief The channel map used for the advertising packet transmission. \n
+     *  It is a bitwise OR of the following values.\n
+     *    |  macro                    |   description   |
+     *    |:--------------------------|:--------------- |
+     *    | BLE_GAP_ADV_CH_37(0x01)   | Use 37 CH.      |
+     *    | BLE_GAP_ADV_CH_38(0x02)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_39(0x04)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_ALL(0x07)  | Use 37 - 39 CH. |
+     */
+    uint8_t advertising_channel_map;
+
+    /**
+     *  @brief Advertising filter policy. \n
+     *  If the p_peer_address parameter is NULL, the advertising is performed according to the advertising filter policy. \n
+     *  If the p_peer_address parameter is not NULL, this parameter is ignored. \n
+     *    |  macro                                              |   description                                                             |
+     *    |:----------------------------------------------------|:------------------------------------------------------------------------- |
+     *    | BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY(0x00)          | Process scan and connection requests from all devices.                    |
+     *    | BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST(0x01)   | Process scan and connection requests from only devices in the White List. |
+     */
+    uint8_t advertising_filter_policy;
+
+    /**
+     *  @brief  Own Bluetooth address type. \n Select one of the following.
+     *    |  macro                              |   description                                                                                                                |
+     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     */
+    uint8_t own_bluetooth_address_type;
+    uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
+    uint8_t padding[3];                ///< padding
+} ble_abs_legacy_advertising_parameter_t;
+
+/** st_ble_abs_extend_advertising_parameter_t is the parameters for extended advertising. */
+typedef struct st_ble_abs_extend_advertising_parameter
+{
+    /**
+     *  @brief The remote device address. \n
+     *  If the p_addr parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n
+     *  If the p_addr parameter is NULL, Undirect Connectable Advertising is performed \n
+     *  according to the advertising filter policy specified by the filter parameter.
+     */
+    ble_device_address_t * p_peer_address;
+
+    /**
+     *  @brief Advertising data. If p_adv_data is specified as NULL, advertising data is not set.
+     */
+    uint8_t * p_advertising_data;
+
+    /**
+     *  @brief Advertising with the fast_advertising_interval parameter continues for \n
+     *  the period specified by the fast_advertising_period parameter. \n
+     *  Time(ms) = fast_advertising_interval * 0.625. \n
+     *  If the fast_advertising_period parameter is 0, this parameter is ignored. \n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t fast_advertising_interval;
+
+    /**
+     *  @brief After the elapse of the fast_advertising_period, advertising with the slow_advertising_interval parameter \n
+     *  continues for the period specified by the slow_advertising_period parameter. \n
+     *  Time(ms) = fast_advertising_interval * 0.625. \n
+     *  If the fast_advertising_period parameter is 0, this parameter is ignored. \n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t slow_advertising_interval;
+
+    /**
+     *  @brief The period which advertising with the fast_advertising_interval parameter continues for. \n
+     *  Time = duration * 10ms. \n
+     *  After the elapse of the fast_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the fast_advertising_period parameter is 0x0000, the fast_advertising_interval parameter is ignored.
+     */
+    uint16_t fast_advertising_period;
+
+    /**
+     *  @brief The period which advertising with the slow_advertising_interval parameter continues for. \n
+     *  Time = duration * 10ms. \n
+     *  After the elapse of the slow_advertising_period, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the slow_advertising_period parameter is 0x0000, the advertising continues.
+     */
+    uint16_t slow_advertising_period;
+
+    /**
+     *  @brief Advertising data length (in bytes). \n
+     *  Valid range is 0-229. \n
+     *  If the adv_data_length is 0, Advertising Data is not included in the advertising PDU.
+     */
+    uint16_t advertising_data_length;
+
+    /**
+     *  @brief The channel map used for the advertising packet transmission. \n
+     *  It is a bitwise OR of the following values.
+     *    |  macro                    |   description   |
+     *    |:--------------------------|:--------------- |
+     *    | BLE_GAP_ADV_CH_37(0x01)   | Use 37 CH.      |
+     *    | BLE_GAP_ADV_CH_38(0x02)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_39(0x04)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_ALL(0x07)  | Use 37 - 39 CH. |
+     */
+    uint8_t advertising_channel_map;
+
+    /**
+     *  @brief Advertising filter policy. \n
+     *  If the p_peer_address parameter is NULL, the advertising is performed according to the advertising filter policy. \n
+     *  If the p_peer_address parameter is not NULL, this parameter is ignored. \n
+     *    |  macro                                              |   description                                                             |
+     *    |:----------------------------------------------------|:------------------------------------------------------------------------- |
+     *    | BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY(0x00)          | Process scan and connection requests from all devices.                    |
+     *    | BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST(0x01)   | Process scan and connection requests from only devices in the White List. |
+     */
+    uint8_t advertising_filter_policy;
+
+    /**
+     *  @brief  Own Bluetooth address type. Select one of the following. \n
+     *    |  macro                              |   description                                                                                                                |
+     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     */
+    uint8_t own_bluetooth_address_type;
+    uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
+
+    /**
+     *  @brief Primary advertising PHY. \n
+     *  In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. \n
+     *    |  macro                   |   description                                                                                                                                        |
+     *    |:-------------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Primary Advertising PHY. \n When the adv_prop_type field is Legacy Advertising PDU type, this field shall be set to BLE_GAP_ADV_PHY_1M.|
+     *    | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY as Primary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().                                         |
+     *
+     */
+    uint8_t primary_advertising_phy;
+
+    /**
+     *  @brief  Secondary advertising Phy. Select one of the following.
+     *    |  macro                     |   description                                                                                                       |
+     *    |:---------------------------|:------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADV_PHY_1M(0x01)   | Use 1M PHY as Secondary Advertising PHY.                                                                            |
+     *    | BLE_GAP_ADV_PHY_2M(0x02)   | Use 2M PHY as Secondary Advertising PHY.                                                                            |
+     *    | BLE_GAP_ADV_PHY_CD(0x03)   | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). |
+     */
+    uint8_t secondary_advertising_phy;
+    uint8_t padding[3];                ///< padding
+} ble_abs_extend_advertising_parameter_t;
+
+/** st_ble_abs_non_connectable_advertising_parameter_t is the parameters for non-connectable advertising. */
+typedef struct st_ble_abs_non_connectable_advertising_parameter
+{
+    /**
+     *  @brief The remote device address. \n
+     *  If the p_peer_address parameter is not NULL, Direct Connectable Advertising is performed to the remote address. \n
+     *  If the p_peer_address parameter is NULL, Undirect Connectable Advertising is performed \n
+     *  according to the advertising filter policy specified by the filter parameter.
+     */
+    ble_device_address_t * p_peer_address;
+
+    /**
+     *  @brief Advertising data. If p_adv_data is specified as NULL, advertising data is not set.
+     */
+    uint8_t * p_advertising_data;
+
+    /**
+     *  @brief Advertising with the advertising_interval parameter continues for the period specified by the duration parameter.\n
+     *  Time(ms) = advertising_interval * 0.625. \n
+     *  If the duration parameter is 0x0000, the advertising with the advertising_interval parameter continue. \n
+     *  Valid range is 0x00000020 - 0x00FFFFFF.
+     */
+    uint32_t advertising_interval;
+
+    /**
+     *  @brief The period which advertising with the advertising_interval parameter continues for. \n
+     *  Time = advertising_duration * 10ms.\n
+     *  After the elapse of the advertising_duration, @ref BLE_GAP_EVENT_ADV_OFF event notifies that the advertising has stopped. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the advertising_duration parameter is 0x0000, the advertising continues.
+     */
+    uint16_t advertising_duration;
+
+    /**
+     *  @brief Advertising data length (in bytes).\n
+     *  If the primary_advertising_phy parameter is @ref BLE_ABS_ADVERTISING_PHY_LEGACY(0x00), the valid range is 0-31. \n
+     *  If the primary_advertising_phy parameter is the other values, the valid range is 0-1650. \n
+     *  If the advertising_data_length parameter is 0, Advertising Data is not included in the advertising PDU.
+     */
+    uint16_t advertising_data_length;
+
+    /**
+     *  @brief The channel map used for the advertising packet transmission. \n
+     *  It is a bitwise OR of the following values.
+     *    |  macro                    |   description   |
+     *    |:--------------------------|:--------------- |
+     *    | BLE_GAP_ADV_CH_37(0x01)   | Use 37 CH.      |
+     *    | BLE_GAP_ADV_CH_38(0x02)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_39(0x04)   | Use 38 CH.      |
+     *    | BLE_GAP_ADV_CH_ALL(0x07)  | Use 37 - 39 CH. |
+     */
+    uint8_t advertising_channel_map;
+
+    /**
+     *  @brief  Own Bluetooth address type. Select one of the following. \n
+     *    |  macro                              |   description                                                                                                                |
+     *    |:------------------------------------|:---------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADDR_PUBLIC(0x00)           | Public Address                                                                                                               |
+     *    | BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02)    | Resolvable Private Address. \n If the IRK of local device has not been registered in Resolving List, public address is used. |
+     */
+    uint8_t own_bluetooth_address_type;
+    uint8_t own_bluetooth_address[6];  ///< Own Bluetooth address.
+
+    /**
+     *  @brief Primary advertising PHY. \n
+     *  In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. \n
+     *    |  macro                               |   description                                                                                                                                                             |
+     *    |:-------------------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_ABS_ADVERTISING_PHY_LEGACY(0x00) | Use 1M PHY as Primary Advertising PHY for Non-Connectable Legacy Advertising. \n If Periodic Advertising is performed, this value shall not set to the adv_phy parameter. |
+     *    | BLE_GAP_ADV_PHY_1M(0x01)             | Use 1M PHY as Primary Advertising PHY. \n When the adv_prop_type field is Legacy Advertising PDU type, this field shall be set to BLE_GAP_ADV_PHY_1M.                     |
+     *    | BLE_GAP_ADV_PHY_CD(0x03)             | Use Coded PHY as Primary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().                                                              |
+     */
+    uint8_t primary_advertising_phy;
+
+    /**
+     *  @brief  Secondary advertising Phy. Select one of the following.
+     *    |  macro                     |   description                                                                                                       |
+     *    |:---------------------------|:------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_ADV_PHY_1M(0x01)   | Use 1M PHY as Secondary Advertising PHY.                                                                            |
+     *    | BLE_GAP_ADV_PHY_2M(0x02)   | Use 2M PHY as Secondary Advertising PHY.                                                                            |
+     *    | BLE_GAP_ADV_PHY_CD(0x03)   | Use Coded PHY(S=8) as Secondary Advertising PHY. \n Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). |
+     */
+    uint8_t secondary_advertising_phy;
+    uint8_t padding[2];                ///< padding
+} ble_abs_non_connectable_advertising_parameter_t;
+
+/** st_ble_abs_periodic_advertising_parameter_t is the parameters for periodic advertising. */
+typedef struct st_ble_abs_periodic_advertising_parameter
+{
+    /**
+     *  @brief Advertising parameters.
+     */
+    ble_abs_non_connectable_advertising_parameter_t advertising_parameter;
+
+    /**
+     *  @brief Periodic advertising data. If p_perd_adv_data is specified as NULL, periodic advertising data is not set.
+     */
+    uint8_t * p_periodic_advertising_data;
+
+    /**
+     *  @brief Periodic advertising interval. \n
+     *  Time(ms) = periodic_advertising_interval * 1.25. \n
+     *  Valid range is 0x0006 - 0xFFFF.
+     */
+    uint16_t periodic_advertising_interval;
+
+    /**
+     *  @brief Periodic advertising data length (in bytes). \n
+     *  Valid range is 0 - 1650. \n
+     *  If the periodic_advertising_data_length is 0, Periodic Advertising Data is not included in the advertising PDU.
+     */
+    uint16_t periodic_advertising_data_length;
+} ble_abs_periodic_advertising_parameter_t;
+
+/** st_ble_abs_scan_phy_parameter_t is the phy parameters for scan. */
+typedef struct st_ble_abs_scan_phy_parameter
+{
+    /**
+     *  @brief Fast scan interval. \n
+     *  Interval(ms) = fast_scan_interval * 0.625. \n
+     *  Valid range is 0x0004 - 0xFFFF.
+     *
+     */
+    uint16_t fast_scan_interval;
+
+    /**
+     *  @brief Slow Scan interval. \n
+     *  Slow Scan interval(ms) = slow_scan_interval * 0.625. \n
+     *  Valid range is 0x0004 - 0xFFFF.
+     */
+    uint16_t slow_scan_interval;
+
+    /**
+     *  @brief Fast Scan window. \n
+     *  Fast Scan window(ms) = fast_scan_window * 0.625. \n
+     *  Valid range is 0x0004 - 0xFFFF.
+     */
+    uint16_t fast_scan_window;
+
+    /**
+     *  @brief Slow Scan window. \n
+     *  Slow Scan window(ms) = slow_scan_window * 0.625. \n
+     *  Valid range is 0x0004 - 0xFFFF.
+     */
+    uint16_t slow_scan_window;
+
+    /**
+     *  @brief Scan type.
+     *    |  macro                       |   description   |
+     *    |:-----------------------------|:--------------- |
+     *    | BLE_GAP_SCAN_PASSIVE(0x00)   | Passive Scan.   |
+     *    | BLE_GAP_SCAN_ACTIVE(0x01)    | Active Scan.    |
+     */
+    uint8_t scan_type;
+
+    /**
+     *  @brief padding.
+     */
+    uint8_t padding[3];
+} ble_abs_scan_phy_parameter_t;
+
+/** st_ble_abs_scan_parameter_t is the parameters for scan. */
+typedef struct st_ble_abs_scan_parameter
+{
+    /**
+     *  @brief Scan parameters for receiving the advertising packets in 1M PHY. \n
+     *  In case of not receiving the advertising packets in 1M PHY, this field is specified as NULL. \n
+     *  p_phy_parameter_1M or p_phy_parameter_coded field shall be set to scan parameters.
+     */
+    ble_abs_scan_phy_parameter_t * p_phy_parameter_1M;
+
+    /**
+     *  @brief Scan parameters for receiving the advertising packets in Coded PHY. \n
+     *  In case of not receiving the advertising packets in Coded PHY, this field is specified as NULL. \n
+     *  p_phy_parameter_1M or p_phy_parameter_coded field shall be set to scan parameters.
+     */
+    ble_abs_scan_phy_parameter_t * p_phy_parameter_coded;
+
+    /**
+     *  @brief Data for Advertising Data filtering. \n
+     *  The p_filter_data parameter is used for the advertising data in single advertising report. \n
+     *  The advertising data composed of multiple advertising reports is not filtered by this parameter. \n
+     *  If the p_filter_data parameter is specified as NULL, the filtering is not done.
+     */
+    uint8_t * p_filter_data;
+
+    /**
+     *  @brief The period which scan with the fast scan interval/fast scan window continues for. \n
+     *  Time(ms) = fast_scan_period * 10. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the fast_scan_period parameter is 0x0000, scan with the fast scan interval/fast scan window is not performed. \n
+     *  After the elapse of the fast_scan_period, @ref BLE_GAP_EVENT_SCAN_TO event notifies that the scan has stopped.
+     */
+    uint16_t fast_scan_period;
+
+    /**
+     *  @brief The period which scan with the slow scan interval/slow scan window continues for. \n
+     *  Time = slow_scan_period * 10ms. \n
+     *  Valid range is 0x0000 - 0xFFFF. \n
+     *  If the slow_scan_period parameter is 0x0000, the scan continues. \n
+     *  After the elapse of the slow_scan_period, @ref BLE_GAP_EVENT_SCAN_TO event notifies that the scan has stopped.
+     */
+    uint16_t slow_scan_period;
+
+    /**
+     *  @brief The length of the data specified by the p_filter_data parameter. \n
+     *  Valid range is 0x0000-0x0010. \n
+     *  If the filter_data_length parameter is 0, the filtering is not done.
+     */
+    uint16_t filter_data_length;
+
+    /**
+     *  @brief Scan Filter Policy. Select one of the following.
+     *    |  macro                                            |   description                                                                                                                                                                                                                                                                                                                                                                                                               |
+     *    |:--------------------------------------------------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_SCAN_ALLOW_ADV_ALL(0x00)                  | Accept all advertising and scan response PDUs except directed advertising PDUs not addressed to local device.                                                                                                                                                                                                                                                                                                               |
+     *    | BLE_GAP_SCAN_ALLOW_ADV_WLST(0x01)                 | Accept only advertising and scan response PDUs from remote devices whose address is registered in the White List. \n Directed advertising PDUs which are not addressed to local device is ignored.                                                                                                                                                                                                                          |
+     *    | BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED(0x02)      | Accept all advertising and scan response PDUs except directed advertising PDUs whose the target address is identity address but doesn't address local device. However directed advertising PDUs whose the target address is the local resolvable private address are accepted.                                                                                                                                              |
+     *    | BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST(0x03) | Accept all advertising and scan response PDUs. The following are excluded.  \n \arg Advertising and scan response PDUs where the advertiser's identity address is not in the White List. \n \arg Directed advertising PDUs whose the target address is identity address but doesn't address local device. However directed advertising PDUs whose the target address is the local resolvable private address are accepted.  |
+     */
+    uint8_t device_scan_filter_policy;
+
+    /**
+     *  @brief Filter duplicates. \n
+     *  Maximum number of filtered devices is 8. \n
+     *  The 9th and subsequent devices are not filtered by this parameter.  \n
+     *    |  macro                                            |   description                                            |
+     *    |:--------------------------------------------------|:-------------------------------------------------------- |
+     *    | BLE_GAP_SCAN_FILT_DUPLIC_DISABLE(0x00)            | Duplicate filter disabled.                               |
+     *    | BLE_GAP_SCAN_FILT_DUPLIC_ENABLE(0x01)             | Duplicate filter enabled.                                |
+     *    | BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02)) | Duplicate filtering enabled, reset for each scan period. |
+     *
+     */
+    uint8_t filter_duplicate;
+
+    /**
+     *  @brief The AD type of the data specified by the p_filter_data parameter.\n
+     *  The AD type identifier values are defined in Bluetooth SIG Assigned Number \n
+     *  (https://www.bluetooth.com/specifications/assigned-numbers).
+     */
+    uint8_t filter_ad_type;
+
+    /**
+     *  @brief Padding
+     */
+    uint8_t padding[3];
+} ble_abs_scan_parameter_t;
+
+/** st_ble_abs_connection_phy_parameter_t is the phy parameters for create connection. */
+typedef struct st_ble_abs_connection_phy_parameter
+{
+    /**
+     *  @brief Connection interval. \n
+     *  Time(ms) = connection_interval * 1.25. \n
+     *  Valid range is 0x0006 - 0x0C80.
+     */
+    uint16_t connection_interval;
+
+    /**
+     *  @brief Slave latency. \n
+     *  Valid range is 0x0000 - 0x01F3.
+     */
+    uint16_t connection_slave_latency;
+
+    /**
+     *  @brief Supervision timeout. \n
+     *  Time(ms) = supervision_timeout * 10. \n
+     *  Valid range is 0x000A - 0x0C80.
+     */
+    uint16_t supervision_timeout;
+
+    /**
+     *  @brief Padding
+     */
+    uint8_t padding[2];
+} ble_abs_connection_phy_parameter_t;
+
+/** st_ble_abs_connection_parameter_t is the parameters for create connection. */
+typedef struct st_ble_abs_connection_parameter
+{
+    /**
+     *  @brief Connection interval, slave latency, supervision timeout for 1M PHY. \n
+     *  The p_connection_phy_parameter_1M is specified as NULL, a connection request is not sent with 1M PHY.
+     */
+    ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_1M;
+
+    /**
+     *  @brief Connection interval, slave latency, supervision timeout for 2M PHY. \n
+     *  The p_connection_phy_parameter_2M is specified as NULL, a connection request is not sent with 2M PHY.
+     */
+    ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_2M;
+
+    /**
+     *  @brief Connection interval, slave latency, supervision timeout for Coded PHY.  \n
+     *  The p_connection_phy_parameter_coded is specified as NULL, a connection request is not sent with Coded PHY.
+     */
+    ble_abs_connection_phy_parameter_t * p_connection_phy_parameter_coded;
+
+    /**
+     *  @brief Address of the device to be connected. \n
+     *  If the filter field is @ref BLE_GAP_INIT_FILT_USE_WLST(0x01), this parameter is ignored.
+     */
+    ble_device_address_t * p_device_address;
+
+    /**
+     *  @brief The filter field specifies whether the White List is used or not, when connecting with a remote device.\n
+     *    |  macro                           |   description                                                                                                                      |
+     *    |:---------------------------------|:---------------------------------------------------------------------------------------------------------------------------------- |
+     *    | BLE_GAP_INIT_FILT_USE_ADDR(0x00) | White List is not used. \n The remote device to be connected is specified by the p_addr field is used.                             |
+     *    | BLE_GAP_INIT_FILT_USE_WLST(0x01) | White List is used. \n The remote device registered in White List is connected with local device. \n The p_addr field is ignored.  |
+     */
+    uint8_t filter_parameter;
+
+    /**
+     *  @brief The time(sec) to cancel the create connection request. \n
+     *  Valid range is 0 <= connection_timeout <= 10. \n
+     *  If the connection_timeout field is 0, the create connection request is not canceled. \n
+     */
+    uint8_t connection_timeout;
+
+    /**
+     *  @brief Padding
+     */
+    uint8_t padding[2];
+} ble_abs_connection_parameter_t;
+
+/** BLE ABS configuration parameters. */
+typedef struct st_ble_abs_cfg
+{
+    /** the parameters for initialization. */
+    uint32_t channel;                                                       ///< Select a channel corresponding to the channel number of the hardware.
+    ble_gap_application_callback_t             gap_callback;                ///< GAP callback function.
+    ble_vendor_specific_application_callback_t vendor_specific_callback;    ///< Vendor Specific callback function.
+    ble_abs_gatt_server_callback_set_t       * p_gatt_server_callback_list; ///< GATT Server callback set.
+    uint8_t gatt_server_callback_list_number;                               ///< The number of GATT Server callback functions.
+    ble_abs_gatt_client_callback_set_t * p_gatt_client_callback_list;       ///< GATT Client callback set.
+    uint8_t gatt_client_callback_list_number;                               ///< The number of GATT Client callback functions.
+    ble_abs_pairing_parameter_t * p_pairing_parameter;                      ///< Pairing parameters.
+
+    flash_instance_t const * p_flash_instance;                              ///< Pointer to flash instance.
+    timer_instance_t const * p_timer_instance;                              ///< Pointer to timer instance.
+
+    void (* p_callback)(ble_abs_callback_args_t * p_args);                  ///< Callback provided when a BLE ISR occurs.
+    void const * p_context;                                                 ///< Placeholder for user data.  Passed to the user callback in ble_abs_callback_args_t.
+    void const * p_extend;                                                  ///< Placeholder for user extension.
+} ble_abs_cfg_t;
+
+/** BLE ABS functions implemented at the HAL layer will follow this API. */
+typedef struct st_ble_abs_api
+{
+    /** Initialize the BLE ABS in register start mode.
+     * @par Implemented as
+     * - RM_BLE_ABS_Open()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_cfg        Pointer to pin configuration structure.
+     */
+    fsp_err_t (* open)(ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg);
+
+    /** Close the BLE ABS.
+     * @par Implemented as
+     * - RM_BLE_ABS_Close()
+     *
+     * @param[in]  p_ctrl       Pointer to control structure.
+     */
+    fsp_err_t (* close)(ble_abs_ctrl_t * const p_ctrl);
+
+    /** Close the BLE ABS.
+     * @par Implemented as
+     * - RM_BLE_ABS_Reset()
+     *
+     * @param[in]  p_ctrl        Pointer to control structure.
+     * @param[in]  init_callback callback function to initialize Host Stack.
+     */
+    fsp_err_t (* reset)(ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback);
+
+    /** Return the version of the driver.
+     * @par Implemented as
+     * - RM_BLE_ABS_VersionGet()
+     * @param[out] p_data       Memory address to return version information to.
+     */
+    fsp_err_t (* versionGet)(fsp_version_t * const p_data);
+
+    /** Start Legacy Connectable Advertising.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartLegacyAdvertising()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_advertising_parameter        Pointer to Advertising parameters for Legacy Advertising.
+     */
+    fsp_err_t (* startLegacyAdvertising)(ble_abs_ctrl_t * const                               p_ctrl,
+                                         ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter);
+
+    /** Start Extended Connectable Advertising.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartExtendedAdvertising()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_advertising_parameter        Pointer to Advertising parameters for extend Advertising.
+     */
+    fsp_err_t (* startExtendedAdvertising)(ble_abs_ctrl_t * const                               p_ctrl,
+                                           ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter);
+
+    /** Start Non-Connectable Advertising.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartNonConnectableAdvertising()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_advertising_parameter        Pointer to Advertising parameters for non-connectable Advertising.
+     */
+    fsp_err_t (* startNonConnectableAdvertising)(ble_abs_ctrl_t * const p_ctrl,
+                                                 ble_abs_non_connectable_advertising_parameter_t const * const
+                                                 p_advertising_parameter);
+
+    /** Start Periodic Advertising.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartPeriodicAdvertising()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_advertising_parameter        Pointer to Advertising parameters for periodic Advertising.
+     */
+    fsp_err_t (* startPeriodicAdvertising)(ble_abs_ctrl_t * const p_ctrl,
+                                           ble_abs_periodic_advertising_parameter_t const * const
+                                           p_advertising_parameter);
+
+    /** Start scanning.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartScanning()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_scan_parameter        Pointer to scan parameter.
+     */
+    fsp_err_t (* startScanning)(ble_abs_ctrl_t * const p_ctrl, ble_abs_scan_parameter_t const * const p_scan_parameter);
+
+    /** Request create connection.
+     * @par Implemented as
+     * - RM_BLE_ABS_CreateConnection()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_connection_parameter        Pointer to connection parameter.
+     */
+    fsp_err_t (* createConnection)(ble_abs_ctrl_t * const                       p_ctrl,
+                                   ble_abs_connection_parameter_t const * const p_connection_parameter);
+
+    /** Configure local device privacy.
+     * @par Implemented as
+     * - RM_BLE_ABS_SetLocalPrivacy()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  p_lc_irk        Pointer to IRK to be registered in the resolving list.
+     * @param[in]  privacy_mode        privacy_mode privacy mode.
+     */
+    fsp_err_t (* setLocalPrivacy)(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk, uint8_t privacy_mode);
+
+    /** Start pairing or encryption.
+     * @par Implemented as
+     * - RM_BLE_ABS_StartAuthentication()
+     * @param[in]  p_ctrl       Pointer to control structure.
+     * @param[in]  connection_handle        Connection handle identifying the remote device.
+     */
+    fsp_err_t (* startAuthentication)(ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle);
+} ble_abs_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_ble_abs_instance
+{
+    ble_abs_ctrl_t      * p_ctrl;      ///< Pointer to the control structure for this instance
+    ble_abs_cfg_t const * p_cfg;       ///< Pointer to the configuration structure for this instance
+    ble_abs_api_t const * p_api;       ///< Pointer to the API structure for this instance
+} ble_abs_instance_t;
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup BLE_ABS_API)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_common_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_common_api.h
new file mode 100644
index 0000000000..d86714a407
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_common_api.h
@@ -0,0 +1,342 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef FSP_COMMON_API_H
+#define FSP_COMMON_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include 
+#include 
+
+/* Includes FSP version macros. */
+#include "fsp_version.h"
+
+/*******************************************************************************************************************//**
+ * @ingroup RENESAS_COMMON
+ * @defgroup RENESAS_ERROR_CODES Common Error Codes
+ * All FSP modules share these common error codes.
+ * @{
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
+ * about using this implementation is that it does not take any extra RAM or ROM. */
+
+/*LDRA_INSPECTED 340 s */
+#define FSP_PARAMETER_NOT_USED(p)    (void) ((p))
+
+/** Determine if a C++ compiler is being used.
+ * If so, ensure that standard C is used to process the API information.  */
+#if defined(__cplusplus)
+ #define FSP_CPP_HEADER    extern "C" {
+ #define FSP_CPP_FOOTER    }
+#else
+ #define FSP_CPP_HEADER
+ #define FSP_CPP_FOOTER
+#endif
+
+/** FSP Header and Footer definitions */
+#define FSP_HEADER    FSP_CPP_HEADER
+#define FSP_FOOTER    FSP_CPP_FOOTER
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Common error codes */
+typedef enum e_fsp_err
+{
+    FSP_SUCCESS = 0,
+
+    FSP_ERR_ASSERTION             = 1,                      ///< A critical assertion has failed
+    FSP_ERR_INVALID_POINTER       = 2,                      ///< Pointer points to invalid memory location
+    FSP_ERR_INVALID_ARGUMENT      = 3,                      ///< Invalid input parameter
+    FSP_ERR_INVALID_CHANNEL       = 4,                      ///< Selected channel does not exist
+    FSP_ERR_INVALID_MODE          = 5,                      ///< Unsupported or incorrect mode
+    FSP_ERR_UNSUPPORTED           = 6,                      ///< Selected mode not supported by this API
+    FSP_ERR_NOT_OPEN              = 7,                      ///< Requested channel is not configured or API not open
+    FSP_ERR_IN_USE                = 8,                      ///< Channel/peripheral is running/busy
+    FSP_ERR_OUT_OF_MEMORY         = 9,                      ///< Allocate more memory in the driver's cfg.h
+    FSP_ERR_HW_LOCKED             = 10,                     ///< Hardware is locked
+    FSP_ERR_IRQ_BSP_DISABLED      = 11,                     ///< IRQ not enabled in BSP
+    FSP_ERR_OVERFLOW              = 12,                     ///< Hardware overflow
+    FSP_ERR_UNDERFLOW             = 13,                     ///< Hardware underflow
+    FSP_ERR_ALREADY_OPEN          = 14,                     ///< Requested channel is already open in a different configuration
+    FSP_ERR_APPROXIMATION         = 15,                     ///< Could not set value to exact result
+    FSP_ERR_CLAMPED               = 16,                     ///< Value had to be limited for some reason
+    FSP_ERR_INVALID_RATE          = 17,                     ///< Selected rate could not be met
+    FSP_ERR_ABORTED               = 18,                     ///< An operation was aborted
+    FSP_ERR_NOT_ENABLED           = 19,                     ///< Requested operation is not enabled
+    FSP_ERR_TIMEOUT               = 20,                     ///< Timeout error
+    FSP_ERR_INVALID_BLOCKS        = 21,                     ///< Invalid number of blocks supplied
+    FSP_ERR_INVALID_ADDRESS       = 22,                     ///< Invalid address supplied
+    FSP_ERR_INVALID_SIZE          = 23,                     ///< Invalid size/length supplied for operation
+    FSP_ERR_WRITE_FAILED          = 24,                     ///< Write operation failed
+    FSP_ERR_ERASE_FAILED          = 25,                     ///< Erase operation failed
+    FSP_ERR_INVALID_CALL          = 26,                     ///< Invalid function call is made
+    FSP_ERR_INVALID_HW_CONDITION  = 27,                     ///< Detected hardware is in invalid condition
+    FSP_ERR_INVALID_FACTORY_FLASH = 28,                     ///< Factory flash is not available on this MCU
+    FSP_ERR_INVALID_STATE         = 30,                     ///< API or command not valid in the current state
+    FSP_ERR_NOT_ERASED            = 31,                     ///< Erase verification failed
+    FSP_ERR_SECTOR_RELEASE_FAILED = 32,                     ///< Sector release failed
+    FSP_ERR_NOT_INITIALIZED       = 33,                     ///< Required initialization not complete
+
+    /* Start of RTOS only error codes */
+    FSP_ERR_INTERNAL     = 100,                             ///< Internal error
+    FSP_ERR_WAIT_ABORTED = 101,                             ///< Wait aborted
+
+    /* Start of UART specific */
+    FSP_ERR_FRAMING            = 200,                       ///< Framing error occurs
+    FSP_ERR_BREAK_DETECT       = 201,                       ///< Break signal detects
+    FSP_ERR_PARITY             = 202,                       ///< Parity error occurs
+    FSP_ERR_RXBUF_OVERFLOW     = 203,                       ///< Receive queue overflow
+    FSP_ERR_QUEUE_UNAVAILABLE  = 204,                       ///< Can't open s/w queue
+    FSP_ERR_INSUFFICIENT_SPACE = 205,                       ///< Not enough space in transmission circular buffer
+    FSP_ERR_INSUFFICIENT_DATA  = 206,                       ///< Not enough data in receive circular buffer
+
+    /* Start of SPI specific */
+    FSP_ERR_TRANSFER_ABORTED = 300,                         ///< The data transfer was aborted.
+    FSP_ERR_MODE_FAULT       = 301,                         ///< Mode fault error.
+    FSP_ERR_READ_OVERFLOW    = 302,                         ///< Read overflow.
+    FSP_ERR_SPI_PARITY       = 303,                         ///< Parity error.
+    FSP_ERR_OVERRUN          = 304,                         ///< Overrun error.
+
+    /* Start of CGC Specific */
+    FSP_ERR_CLOCK_INACTIVE        = 400,                    ///< Inactive clock specified as system clock.
+    FSP_ERR_CLOCK_ACTIVE          = 401,                    ///< Active clock source cannot be modified without stopping first.
+    FSP_ERR_NOT_STABILIZED        = 403,                    ///< Clock has not stabilized after its been turned on/off
+    FSP_ERR_PLL_SRC_INACTIVE      = 404,                    ///< PLL initialization attempted when PLL source is turned off
+    FSP_ERR_OSC_STOP_DET_ENABLED  = 405,                    ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
+    FSP_ERR_OSC_STOP_DETECTED     = 406,                    ///< The Oscillation stop detection status flag is set
+    FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407,                    ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
+    FSP_ERR_CLKOUT_EXCEEDED       = 408,                    ///< Output on target output clock pin exceeds maximum supported limit
+    FSP_ERR_USB_MODULE_ENABLED    = 409,                    ///< USB clock configure request with USB Module enabled
+    FSP_ERR_HARDWARE_TIMEOUT      = 410,                    ///< A register read or write timed out
+    FSP_ERR_LOW_VOLTAGE_MODE      = 411,                    ///< Invalid clock setting attempted in low voltage mode
+
+    /* Start of FLASH Specific */
+    FSP_ERR_PE_FAILURE             = 500,                   ///< Unable to enter Programming mode.
+    FSP_ERR_CMD_LOCKED             = 501,                   ///< Peripheral in command locked state
+    FSP_ERR_FCLK                   = 502,                   ///< FCLK must be >= 4 MHz
+    FSP_ERR_INVALID_LINKED_ADDRESS = 503,                   ///< Function or data are linked at an invalid region of memory
+    FSP_ERR_BLANK_CHECK_FAILED     = 504,                   ///< Blank check operation failed
+
+    /* Start of CAC Specific */
+    FSP_ERR_INVALID_CAC_REF_CLOCK = 600,                    ///< Measured clock rate < reference clock rate
+
+    /* Start of GLCD Specific */
+    FSP_ERR_CLOCK_GENERATION           = 1000,              ///< Clock cannot be specified as system clock
+    FSP_ERR_INVALID_TIMING_SETTING     = 1001,              ///< Invalid timing parameter
+    FSP_ERR_INVALID_LAYER_SETTING      = 1002,              ///< Invalid layer parameter
+    FSP_ERR_INVALID_ALIGNMENT          = 1003,              ///< Invalid memory alignment found
+    FSP_ERR_INVALID_GAMMA_SETTING      = 1004,              ///< Invalid gamma correction parameter
+    FSP_ERR_INVALID_LAYER_FORMAT       = 1005,              ///< Invalid color format in layer
+    FSP_ERR_INVALID_UPDATE_TIMING      = 1006,              ///< Invalid timing for register update
+    FSP_ERR_INVALID_CLUT_ACCESS        = 1007,              ///< Invalid access to CLUT entry
+    FSP_ERR_INVALID_FADE_SETTING       = 1008,              ///< Invalid fade-in/fade-out setting
+    FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009,              ///< Invalid gamma correction parameter
+
+    /* Start of JPEG Specific */
+    FSP_ERR_JPEG_ERR                                = 1100, ///< JPEG error
+    FSP_ERR_JPEG_SOI_NOT_DETECTED                   = 1101, ///< SOI not detected until EOI detected.
+    FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED              = 1102, ///< SOF1 to SOFF detected.
+    FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT           = 1103, ///< Unprovided pixel format detected.
+    FSP_ERR_JPEG_SOF_ACCURACY_ERROR                 = 1104, ///< SOF accuracy error: other than 8 detected.
+    FSP_ERR_JPEG_DQT_ACCURACY_ERROR                 = 1105, ///< DQT accuracy error: other than 0 detected.
+    FSP_ERR_JPEG_COMPONENT_ERROR1                   = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
+    FSP_ERR_JPEG_COMPONENT_ERROR2                   = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
+    FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED          = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
+    FSP_ERR_JPEG_SOS_NOT_DETECTED                   = 1109, ///< SOS not detected: SOS not detected until EOI detected.
+    FSP_ERR_JPEG_EOI_NOT_DETECTED                   = 1110, ///< EOI not detected (default)
+    FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
+    FSP_ERR_JPEG_IMAGE_SIZE_ERROR                   = 1112, ///< Image size error detected.
+    FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR         = 1113, ///< Last MCU data number error detected.
+    FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR            = 1114, ///< Block data number error detected.
+    FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH              = 1115, ///< User provided buffer size not enough
+    FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE             = 1116, ///< JPEG Image size is not aligned with MCU
+
+    /* Start of touch panel framework specific */
+    FSP_ERR_CALIBRATE_FAILED = 1200,                        ///< Calibration failed
+
+    /* Start of IP specific */
+    FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400,                 ///< Requested IP does not exist on this device
+    FSP_ERR_IP_UNIT_NOT_PRESENT     = 1401,                 ///< Requested unit does not exist on this device
+    FSP_ERR_IP_CHANNEL_NOT_PRESENT  = 1402,                 ///< Requested channel does not exist on this device
+
+    /* Start of USB specific */
+    FSP_ERR_USB_FAILED      = 1500,
+    FSP_ERR_USB_BUSY        = 1501,
+    FSP_ERR_USB_SIZE_SHORT  = 1502,
+    FSP_ERR_USB_SIZE_OVER   = 1503,
+    FSP_ERR_USB_NOT_OPEN    = 1504,
+    FSP_ERR_USB_NOT_SUSPEND = 1505,
+    FSP_ERR_USB_PARAMETER   = 1506,
+
+    /* Start of Message framework specific */
+    FSP_ERR_NO_MORE_BUFFER           = 2000,         ///< No more buffer found in the memory block pool
+    FSP_ERR_ILLEGAL_BUFFER_ADDRESS   = 2001,         ///< Buffer address is out of block memory pool
+    FSP_ERR_INVALID_WORKBUFFER_SIZE  = 2002,         ///< Work buffer size is invalid
+    FSP_ERR_INVALID_MSG_BUFFER_SIZE  = 2003,         ///< Message buffer size is invalid
+    FSP_ERR_TOO_MANY_BUFFERS         = 2004,         ///< Number of buffer is too many
+    FSP_ERR_NO_SUBSCRIBER_FOUND      = 2005,         ///< No message subscriber found
+    FSP_ERR_MESSAGE_QUEUE_EMPTY      = 2006,         ///< No message found in the message queue
+    FSP_ERR_MESSAGE_QUEUE_FULL       = 2007,         ///< No room for new message in the message queue
+    FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008,         ///< Message subscriber lists is illegal
+    FSP_ERR_BUFFER_RELEASED          = 2009,         ///< Buffer has been released
+
+    /* Start of 2DG Driver specific */
+    FSP_ERR_D2D_ERROR_INIT      = 3000,              ///< D/AVE 2D has an error in the initialization
+    FSP_ERR_D2D_ERROR_DEINIT    = 3001,              ///< D/AVE 2D has an error in the initialization
+    FSP_ERR_D2D_ERROR_RENDERING = 3002,              ///< D/AVE 2D has an error in the rendering
+    FSP_ERR_D2D_ERROR_SIZE      = 3003,              ///< D/AVE 2D has an error in the rendering
+
+    /* Start of ETHER Driver specific */
+    FSP_ERR_ETHER_ERROR_NO_DATA              = 4000, ///< No Data in Receive buffer.
+    FSP_ERR_ETHER_ERROR_LINK                 = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
+    FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE    = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
+    FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
+    FSP_ERR_ETHER_ERROR_FILTERING            = 4004, ///< Detect multicast frame when multicast frame filtering enable
+    FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION    = 4005, ///< ETHERC/EDMAC has an error in the phy communication
+
+    /* Start of ETHER_PHY Driver specific */
+    FSP_ERR_ETHER_PHY_ERROR_LINK = 5000,             ///< PHY is not link up.
+    FSP_ERR_ETHER_PHY_NOT_READY  = 5001,             ///< PHY has an error in the Auto-negotiation
+
+    /* Start of BYTEQ library specific */
+    FSP_ERR_QUEUE_FULL  = 10000,                     ///< Queue is full, cannot queue another data
+    FSP_ERR_QUEUE_EMPTY = 10001,                     ///< Queue is empty, no data to dequeue
+
+    /* Start of CTSU Driver specific */
+    FSP_ERR_CTSU_SCANNING          = 6000,           ///< Scanning.
+    FSP_ERR_CTSU_NOT_GET_DATA      = 6001,           ///< Not processed previous scan data.
+    FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002,           ///< Incomplete initial offset tuning.
+
+    /* Start of SDMMC specific */
+    FSP_ERR_CARD_INIT_FAILED     = 40000,            ///< SD card or eMMC device failed to initialize.
+    FSP_ERR_CARD_NOT_INSERTED    = 40001,            ///< SD card not installed.
+    FSP_ERR_DEVICE_BUSY          = 40002,            ///< Device is holding DAT0 low or another operation is ongoing.
+    FSP_ERR_CARD_NOT_INITIALIZED = 40004,            ///< SD card was removed.
+    FSP_ERR_CARD_WRITE_PROTECTED = 40005,            ///< Media is write protected.
+    FSP_ERR_TRANSFER_BUSY        = 40006,            ///< Transfer in progress.
+    FSP_ERR_RESPONSE             = 40007,            ///< Card did not respond or responded with an error.
+
+    /* Start of FX_IO specific */
+    FSP_ERR_MEDIA_FORMAT_FAILED = 50000,             ///< Media format failed.
+    FSP_ERR_MEDIA_OPEN_FAILED   = 50001,             ///< Media open failed.
+
+    /* Start of CAN specific */
+    FSP_ERR_CAN_DATA_UNAVAILABLE   = 60000,          ///< No data available.
+    FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001,          ///< Switching operation modes failed.
+    FSP_ERR_CAN_INIT_FAILED        = 60002,          ///< Hardware initialization failed.
+    FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003,          ///< Transmit in progress.
+    FSP_ERR_CAN_RECEIVE_MAILBOX    = 60004,          ///< Mailbox is setup as a receive mailbox.
+    FSP_ERR_CAN_TRANSMIT_MAILBOX   = 60005,          ///< Mailbox is setup as a transmit mailbox.
+    FSP_ERR_CAN_MESSAGE_LOST       = 60006,          ///< Receive message has been overwritten or overrun.
+
+    /* Start of SF_WIFI Specific */
+    FSP_ERR_WIFI_CONFIG_FAILED   = 70000,            ///< WiFi module Configuration failed.
+    FSP_ERR_WIFI_INIT_FAILED     = 70001,            ///< WiFi module initialization failed.
+    FSP_ERR_WIFI_TRANSMIT_FAILED = 70002,            ///< Transmission failed
+    FSP_ERR_WIFI_INVALID_MODE    = 70003,            ///< API called when provisioned in client mode
+    FSP_ERR_WIFI_FAILED          = 70004,            ///< WiFi Failed.
+
+    /* Start of SF_CELLULAR Specific */
+    FSP_ERR_CELLULAR_CONFIG_FAILED       = 80000,    ///< Cellular module Configuration failed.
+    FSP_ERR_CELLULAR_INIT_FAILED         = 80001,    ///< Cellular module initialization failed.
+    FSP_ERR_CELLULAR_TRANSMIT_FAILED     = 80002,    ///< Transmission failed
+    FSP_ERR_CELLULAR_FW_UPTODATE         = 80003,    ///< Firmware is uptodate
+    FSP_ERR_CELLULAR_FW_UPGRADE_FAILED   = 80004,    ///< Firmware upgrade failed
+    FSP_ERR_CELLULAR_FAILED              = 80005,    ///< Cellular Failed.
+    FSP_ERR_CELLULAR_INVALID_STATE       = 80006,    ///< API Called in invalid state.
+    FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007,    ///< Cellular Network registration failed
+
+    /* Start of SF_BLE specific */
+    FSP_ERR_BLE_FAILED              = 90001,         ///< BLE operation failed
+    FSP_ERR_BLE_INIT_FAILED         = 90002,         ///< BLE device initialization failed
+    FSP_ERR_BLE_CONFIG_FAILED       = 90003,         ///< BLE device configuration failed
+    FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004,         ///< BLE device Profile already enabled
+    FSP_ERR_BLE_PRF_NOT_ENABLED     = 90005,         ///< BLE device not enabled
+
+    /* Start of SF_BLE_ABS specific */
+    FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001,       ///< Invalid operation is executed.
+    FSP_ERR_BLE_ABS_NOT_FOUND         = 91002,       ///< Valid data or free space is not found.
+
+    /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
+    FSP_ERR_CRYPTO_CONTINUE              = 0x10000,  ///< Continue executing function
+    FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001,  ///< Hardware resource busy
+    FSP_ERR_CRYPTO_SCE_FAIL              = 0x10002,  ///< Internal I/O buffer is not empty
+    FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003,  ///< Invalid index
+    FSP_ERR_CRYPTO_SCE_RETRY             = 0x10004,  ///< Retry
+    FSP_ERR_CRYPTO_SCE_VERIFY_FAIL       = 0x10005,  ///< Verify is failed
+    FSP_ERR_CRYPTO_SCE_ALREADY_OPEN      = 0x10006,  ///< HW SCE module is already opened
+    FSP_ERR_CRYPTO_NOT_OPEN              = 0x10007,  ///< Hardware module is not initialized
+    FSP_ERR_CRYPTO_UNKNOWN               = 0x10008,  ///< Some unknown error occurred
+    FSP_ERR_CRYPTO_NULL_POINTER          = 0x10009,  ///< Null pointer input as a parameter
+    FSP_ERR_CRYPTO_NOT_IMPLEMENTED       = 0x1000a,  ///< Algorithm/size not implemented
+    FSP_ERR_CRYPTO_RNG_INVALID_PARAM     = 0x1000b,  ///< An invalid parameter is specified
+    FSP_ERR_CRYPTO_RNG_FATAL_ERROR       = 0x1000c,  ///< A fatal error occurred
+    FSP_ERR_CRYPTO_INVALID_SIZE          = 0x1000d,  ///< Size specified is invalid
+    FSP_ERR_CRYPTO_INVALID_STATE         = 0x1000e,  ///< Function used in an valid state
+    FSP_ERR_CRYPTO_ALREADY_OPEN          = 0x1000f,  ///< control block is already opened
+    FSP_ERR_CRYPTO_INSTALL_KEY_FAILED    = 0x10010,  ///< Specified input key is invalid.
+    FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011,  ///< Authentication failed
+
+    /* Start of SF_CRYPTO specific */
+    FSP_ERR_CRYPTO_COMMON_NOT_OPENED      = 0x20000, ///< Crypto Framework Common is not opened
+    FSP_ERR_CRYPTO_HAL_ERROR              = 0x20001, ///< Cryoto HAL module returned an error
+    FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH     = 0x20002, ///< Key buffer size is not enough to generate a key
+    FSP_ERR_CRYPTO_BUF_OVERFLOW           = 0x20003, ///< Attempt to write data larger than what the buffer can hold
+    FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
+    FSP_ERR_MESSAGE_TOO_LONG              = 0x20005, ///< Message for RSA encryption is too long.
+    FSP_ERR_RSA_DECRYPTION_ERROR          = 0x20006, ///< RSA Decryption error.
+
+    /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
+     *        Refer to sf_cryoto_err.h for Crypto error codes.
+     */
+} fsp_err_t;
+
+/** Common version structure */
+typedef union st_fsp_version
+{
+    /** Version id */
+    uint32_t version_id;
+
+    /** Code version parameters */
+    struct
+    {
+        uint8_t code_version_minor;    ///< Code minor version
+        uint8_t code_version_major;    ///< Code major version
+        uint8_t api_version_minor;     ///< API minor version
+        uint8_t api_version_major;     ///< API major version
+    };
+} fsp_version_t;
+
+/** @} */
+
+/***********************************************************************************************************************
+ * Function prototypes
+ **********************************************************************************************************************/
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_features.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_features.h
new file mode 100644
index 0000000000..c9a7918230
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_features.h
@@ -0,0 +1,285 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef FSP_FEATURES_H
+#define FSP_FEATURES_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/* C99 includes. */
+#include 
+#include 
+#include 
+#include 
+
+/* Different compiler support. */
+#include "fsp_common_api.h"
+#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Available modules. */
+typedef enum e_fsp_ip
+{
+    FSP_IP_CFLASH = 0,                 ///< Code Flash
+    FSP_IP_DFLASH = 1,                 ///< Data Flash
+    FSP_IP_RAM    = 2,                 ///< RAM
+    FSP_IP_LVD    = 3,                 ///< Low Voltage Detection
+    FSP_IP_CGC    = 3,                 ///< Clock Generation Circuit
+    FSP_IP_LPM    = 3,                 ///< Low Power Modes
+    FSP_IP_FCU    = 4,                 ///< Flash Control Unit
+    FSP_IP_ICU    = 6,                 ///< Interrupt Control Unit
+    FSP_IP_DMAC   = 7,                 ///< DMA Controller
+    FSP_IP_DTC    = 8,                 ///< Data Transfer Controller
+    FSP_IP_IOPORT = 9,                 ///< I/O Ports
+    FSP_IP_PFS    = 10,                ///< Pin Function Select
+    FSP_IP_ELC    = 11,                ///< Event Link Controller
+    FSP_IP_MPU    = 13,                ///< Memory Protection Unit
+    FSP_IP_MSTP   = 14,                ///< Module Stop
+    FSP_IP_MMF    = 15,                ///< Memory Mirror Function
+    FSP_IP_KEY    = 16,                ///< Key Interrupt Function
+    FSP_IP_CAC    = 17,                ///< Clock Frequency Accuracy Measurement Circuit
+    FSP_IP_DOC    = 18,                ///< Data Operation Circuit
+    FSP_IP_CRC    = 19,                ///< Cyclic Redundancy Check Calculator
+    FSP_IP_SCI    = 20,                ///< Serial Communications Interface
+    FSP_IP_IIC    = 21,                ///< I2C Bus Interface
+    FSP_IP_SPI    = 22,                ///< Serial Peripheral Interface
+    FSP_IP_CTSU   = 23,                ///< Capacitive Touch Sensing Unit
+    FSP_IP_SCE    = 24,                ///< Secure Cryptographic Engine
+    FSP_IP_SLCDC  = 25,                ///< Segment LCD Controller
+    FSP_IP_AES    = 26,                ///< Advanced Encryption Standard
+    FSP_IP_TRNG   = 27,                ///< True Random Number Generator
+    FSP_IP_FCACHE = 30,                ///< Flash Cache
+    FSP_IP_SRAM   = 31,                ///< SRAM
+    FSP_IP_ADC    = 32,                ///< A/D Converter
+    FSP_IP_DAC    = 33,                ///< 12-Bit D/A Converter
+    FSP_IP_TSN    = 34,                ///< Temperature Sensor
+    FSP_IP_DAAD   = 35,                ///< D/A A/D Synchronous Unit
+    FSP_IP_ACMPHS = 36,                ///< High Speed Analog Comparator
+    FSP_IP_ACMPLP = 37,                ///< Low Power Analog Comparator
+    FSP_IP_OPAMP  = 38,                ///< Operational Amplifier
+    FSP_IP_SDADC  = 39,                ///< Sigma Delta A/D Converter
+    FSP_IP_RTC    = 40,                ///< Real Time Clock
+    FSP_IP_WDT    = 41,                ///< Watch Dog Timer
+    FSP_IP_IWDT   = 42,                ///< Independent Watch Dog Timer
+    FSP_IP_GPT    = 43,                ///< General PWM Timer
+    FSP_IP_POEG   = 44,                ///< Port Output Enable for GPT
+    FSP_IP_OPS    = 45,                ///< Output Phase Switch
+    FSP_IP_AGT    = 47,                ///< Asynchronous General-Purpose Timer
+    FSP_IP_CAN    = 48,                ///< Controller Area Network
+    FSP_IP_IRDA   = 49,                ///< Infrared Data Association
+    FSP_IP_QSPI   = 50,                ///< Quad Serial Peripheral Interface
+    FSP_IP_USBFS  = 51,                ///< USB Full Speed
+    FSP_IP_SDHI   = 52,                ///< SD/MMC Host Interface
+    FSP_IP_SRC    = 53,                ///< Sampling Rate Converter
+    FSP_IP_SSI    = 54,                ///< Serial Sound Interface
+    FSP_IP_DALI   = 55,                ///< Digital Addressable Lighting Interface
+    FSP_IP_ETHER  = 64,                ///< Ethernet MAC Controller
+    FSP_IP_EDMAC  = 64,                ///< Ethernet DMA Controller
+    FSP_IP_EPTPC  = 65,                ///< Ethernet PTP Controller
+    FSP_IP_PDC    = 66,                ///< Parallel Data Capture Unit
+    FSP_IP_GLCDC  = 67,                ///< Graphics LCD Controller
+    FSP_IP_DRW    = 68,                ///< 2D Drawing Engine
+    FSP_IP_JPEG   = 69,                ///< JPEG
+    FSP_IP_DAC8   = 70,                ///< 8-Bit D/A Converter
+    FSP_IP_USBHS  = 71,                ///< USB High Speed
+} fsp_ip_t;
+
+/** Signals that can be mapped to an interrupt. */
+typedef enum e_fsp_signal
+{
+    FSP_SIGNAL_ADC_COMPARE_MATCH = 0,             ///< ADC COMPARE MATCH
+    FSP_SIGNAL_ADC_COMPARE_MISMATCH,              ///< ADC COMPARE MISMATCH
+    FSP_SIGNAL_ADC_SCAN_END,                      ///< ADC SCAN END
+    FSP_SIGNAL_ADC_SCAN_END_B,                    ///< ADC SCAN END B
+    FSP_SIGNAL_ADC_WINDOW_A,                      ///< ADC WINDOW A
+    FSP_SIGNAL_ADC_WINDOW_B,                      ///< ADC WINDOW B
+    FSP_SIGNAL_AES_RDREQ = 0,                     ///< AES RDREQ
+    FSP_SIGNAL_AES_WRREQ,                         ///< AES WRREQ
+    FSP_SIGNAL_AGT_COMPARE_A = 0,                 ///< AGT COMPARE A
+    FSP_SIGNAL_AGT_COMPARE_B,                     ///< AGT COMPARE B
+    FSP_SIGNAL_AGT_INT,                           ///< AGT INT
+    FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0,           ///< CAC FREQUENCY ERROR
+    FSP_SIGNAL_CAC_MEASUREMENT_END,               ///< CAC MEASUREMENT END
+    FSP_SIGNAL_CAC_OVERFLOW,                      ///< CAC OVERFLOW
+    FSP_SIGNAL_CAN_ERROR = 0,                     ///< CAN ERROR
+    FSP_SIGNAL_CAN_FIFO_RX,                       ///< CAN FIFO RX
+    FSP_SIGNAL_CAN_FIFO_TX,                       ///< CAN FIFO TX
+    FSP_SIGNAL_CAN_MAILBOX_RX,                    ///< CAN MAILBOX RX
+    FSP_SIGNAL_CAN_MAILBOX_TX,                    ///< CAN MAILBOX TX
+    FSP_SIGNAL_CGC_MOSC_STOP = 0,                 ///< CGC MOSC STOP
+    FSP_SIGNAL_LPM_SNOOZE_REQUEST,                ///< LPM SNOOZE REQUEST
+    FSP_SIGNAL_LVD_LVD1,                          ///< LVD LVD1
+    FSP_SIGNAL_LVD_LVD2,                          ///< LVD LVD2
+    FSP_SIGNAL_VBATT_LVD,                         ///< VBATT LVD
+    FSP_SIGNAL_LVD_VBATT  = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
+    FSP_SIGNAL_ACMPHS_INT = 0,                    ///< ACMPHS INT
+    FSP_SIGNAL_ACMPLP_INT = 0,                    ///< ACMPLP INT
+    FSP_SIGNAL_CTSU_END   = 0,                    ///< CTSU END
+    FSP_SIGNAL_CTSU_READ,                         ///< CTSU READ
+    FSP_SIGNAL_CTSU_WRITE,                        ///< CTSU WRITE
+    FSP_SIGNAL_DALI_DEI = 0,                      ///< DALI DEI
+    FSP_SIGNAL_DALI_CLI,                          ///< DALI CLI
+    FSP_SIGNAL_DALI_SDI,                          ///< DALI SDI
+    FSP_SIGNAL_DALI_BPI,                          ///< DALI BPI
+    FSP_SIGNAL_DALI_FEI,                          ///< DALI FEI
+    FSP_SIGNAL_DALI_SDI_OR_BPI,                   ///< DALI SDI OR BPI
+    FSP_SIGNAL_DMAC_INT     = 0,                  ///< DMAC INT
+    FSP_SIGNAL_DOC_INT      = 0,                  ///< DOC INT
+    FSP_SIGNAL_DRW_INT      = 0,                  ///< DRW INT
+    FSP_SIGNAL_DTC_COMPLETE = 0,                  ///< DTC COMPLETE
+    FSP_SIGNAL_DTC_END,                           ///< DTC END
+    FSP_SIGNAL_EDMAC_EINT           = 0,          ///< EDMAC EINT
+    FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0,          ///< ELC SOFTWARE EVENT 0
+    FSP_SIGNAL_ELC_SOFTWARE_EVENT_1,              ///< ELC SOFTWARE EVENT 1
+    FSP_SIGNAL_EPTPC_IPLS = 0,                    ///< EPTPC IPLS
+    FSP_SIGNAL_EPTPC_MINT,                        ///< EPTPC MINT
+    FSP_SIGNAL_EPTPC_PINT,                        ///< EPTPC PINT
+    FSP_SIGNAL_EPTPC_TIMER0_FALL,                 ///< EPTPC TIMER0 FALL
+    FSP_SIGNAL_EPTPC_TIMER0_RISE,                 ///< EPTPC TIMER0 RISE
+    FSP_SIGNAL_EPTPC_TIMER1_FALL,                 ///< EPTPC TIMER1 FALL
+    FSP_SIGNAL_EPTPC_TIMER1_RISE,                 ///< EPTPC TIMER1 RISE
+    FSP_SIGNAL_EPTPC_TIMER2_FALL,                 ///< EPTPC TIMER2 FALL
+    FSP_SIGNAL_EPTPC_TIMER2_RISE,                 ///< EPTPC TIMER2 RISE
+    FSP_SIGNAL_EPTPC_TIMER3_FALL,                 ///< EPTPC TIMER3 FALL
+    FSP_SIGNAL_EPTPC_TIMER3_RISE,                 ///< EPTPC TIMER3 RISE
+    FSP_SIGNAL_EPTPC_TIMER4_FALL,                 ///< EPTPC TIMER4 FALL
+    FSP_SIGNAL_EPTPC_TIMER4_RISE,                 ///< EPTPC TIMER4 RISE
+    FSP_SIGNAL_EPTPC_TIMER5_FALL,                 ///< EPTPC TIMER5 FALL
+    FSP_SIGNAL_EPTPC_TIMER5_RISE,                 ///< EPTPC TIMER5 RISE
+    FSP_SIGNAL_FCU_FIFERR = 0,                    ///< FCU FIFERR
+    FSP_SIGNAL_FCU_FRDYI,                         ///< FCU FRDYI
+    FSP_SIGNAL_GLCDC_LINE_DETECT = 0,             ///< GLCDC LINE DETECT
+    FSP_SIGNAL_GLCDC_UNDERFLOW_1,                 ///< GLCDC UNDERFLOW 1
+    FSP_SIGNAL_GLCDC_UNDERFLOW_2,                 ///< GLCDC UNDERFLOW 2
+    FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0,         ///< GPT CAPTURE COMPARE A
+    FSP_SIGNAL_GPT_CAPTURE_COMPARE_B,             ///< GPT CAPTURE COMPARE B
+    FSP_SIGNAL_GPT_COMPARE_C,                     ///< GPT COMPARE C
+    FSP_SIGNAL_GPT_COMPARE_D,                     ///< GPT COMPARE D
+    FSP_SIGNAL_GPT_COMPARE_E,                     ///< GPT COMPARE E
+    FSP_SIGNAL_GPT_COMPARE_F,                     ///< GPT COMPARE F
+    FSP_SIGNAL_GPT_COUNTER_OVERFLOW,              ///< GPT COUNTER OVERFLOW
+    FSP_SIGNAL_GPT_COUNTER_UNDERFLOW,             ///< GPT COUNTER UNDERFLOW
+    FSP_SIGNAL_GPT_AD_TRIG_A,                     ///< GPT AD TRIG A
+    FSP_SIGNAL_GPT_AD_TRIG_B,                     ///< GPT AD TRIG B
+    FSP_SIGNAL_OPS_UVW_EDGE,                      ///< OPS UVW EDGE
+    FSP_SIGNAL_ICU_IRQ0 = 0,                      ///< ICU IRQ0
+    FSP_SIGNAL_ICU_IRQ1,                          ///< ICU IRQ1
+    FSP_SIGNAL_ICU_IRQ2,                          ///< ICU IRQ2
+    FSP_SIGNAL_ICU_IRQ3,                          ///< ICU IRQ3
+    FSP_SIGNAL_ICU_IRQ4,                          ///< ICU IRQ4
+    FSP_SIGNAL_ICU_IRQ5,                          ///< ICU IRQ5
+    FSP_SIGNAL_ICU_IRQ6,                          ///< ICU IRQ6
+    FSP_SIGNAL_ICU_IRQ7,                          ///< ICU IRQ7
+    FSP_SIGNAL_ICU_IRQ8,                          ///< ICU IRQ8
+    FSP_SIGNAL_ICU_IRQ9,                          ///< ICU IRQ9
+    FSP_SIGNAL_ICU_IRQ10,                         ///< ICU IRQ10
+    FSP_SIGNAL_ICU_IRQ11,                         ///< ICU IRQ11
+    FSP_SIGNAL_ICU_IRQ12,                         ///< ICU IRQ12
+    FSP_SIGNAL_ICU_IRQ13,                         ///< ICU IRQ13
+    FSP_SIGNAL_ICU_IRQ14,                         ///< ICU IRQ14
+    FSP_SIGNAL_ICU_IRQ15,                         ///< ICU IRQ15
+    FSP_SIGNAL_ICU_SNOOZE_CANCEL,                 ///< ICU SNOOZE CANCEL
+    FSP_SIGNAL_IIC_ERI = 0,                       ///< IIC ERI
+    FSP_SIGNAL_IIC_RXI,                           ///< IIC RXI
+    FSP_SIGNAL_IIC_TEI,                           ///< IIC TEI
+    FSP_SIGNAL_IIC_TXI,                           ///< IIC TXI
+    FSP_SIGNAL_IIC_WUI,                           ///< IIC WUI
+    FSP_SIGNAL_IOPORT_EVENT_1 = 0,                ///< IOPORT EVENT 1
+    FSP_SIGNAL_IOPORT_EVENT_2,                    ///< IOPORT EVENT 2
+    FSP_SIGNAL_IOPORT_EVENT_3,                    ///< IOPORT EVENT 3
+    FSP_SIGNAL_IOPORT_EVENT_4,                    ///< IOPORT EVENT 4
+    FSP_SIGNAL_IWDT_UNDERFLOW = 0,                ///< IWDT UNDERFLOW
+    FSP_SIGNAL_JPEG_JDTI      = 0,                ///< JPEG JDTI
+    FSP_SIGNAL_JPEG_JEDI,                         ///< JPEG JEDI
+    FSP_SIGNAL_KEY_INT       = 0,                 ///< KEY INT
+    FSP_SIGNAL_PDC_FRAME_END = 0,                 ///< PDC FRAME END
+    FSP_SIGNAL_PDC_INT,                           ///< PDC INT
+    FSP_SIGNAL_PDC_RECEIVE_DATA_READY,            ///< PDC RECEIVE DATA READY
+    FSP_SIGNAL_POEG_EVENT = 0,                    ///< POEG EVENT
+    FSP_SIGNAL_QSPI_INT   = 0,                    ///< QSPI INT
+    FSP_SIGNAL_RTC_ALARM  = 0,                    ///< RTC ALARM
+    FSP_SIGNAL_RTC_PERIOD,                        ///< RTC PERIOD
+    FSP_SIGNAL_RTC_CARRY,                         ///< RTC CARRY
+    FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0,           ///< SCE INTEGRATE RDRDY
+    FSP_SIGNAL_SCE_INTEGRATE_WRRDY,               ///< SCE INTEGRATE WRRDY
+    FSP_SIGNAL_SCE_LONG_PLG,                      ///< SCE LONG PLG
+    FSP_SIGNAL_SCE_PROC_BUSY,                     ///< SCE PROC BUSY
+    FSP_SIGNAL_SCE_RDRDY_0,                       ///< SCE RDRDY 0
+    FSP_SIGNAL_SCE_RDRDY_1,                       ///< SCE RDRDY 1
+    FSP_SIGNAL_SCE_ROMOK,                         ///< SCE ROMOK
+    FSP_SIGNAL_SCE_TEST_BUSY,                     ///< SCE TEST BUSY
+    FSP_SIGNAL_SCE_WRRDY_0,                       ///< SCE WRRDY 0
+    FSP_SIGNAL_SCE_WRRDY_1,                       ///< SCE WRRDY 1
+    FSP_SIGNAL_SCE_WRRDY_4,                       ///< SCE WRRDY 4
+    FSP_SIGNAL_SCI_AM = 0,                        ///< SCI AM
+    FSP_SIGNAL_SCI_ERI,                           ///< SCI ERI
+    FSP_SIGNAL_SCI_RXI,                           ///< SCI RXI
+    FSP_SIGNAL_SCI_RXI_OR_ERI,                    ///< SCI RXI OR ERI
+    FSP_SIGNAL_SCI_TEI,                           ///< SCI TEI
+    FSP_SIGNAL_SCI_TXI,                           ///< SCI TXI
+    FSP_SIGNAL_SDADC_ADI = 0,                     ///< SDADC ADI
+    FSP_SIGNAL_SDADC_SCANEND,                     ///< SDADC SCANEND
+    FSP_SIGNAL_SDADC_CALIEND,                     ///< SDADC CALIEND
+    FSP_SIGNAL_SDHIMMC_ACCS = 0,                  ///< SDHIMMC ACCS
+    FSP_SIGNAL_SDHIMMC_CARD,                      ///< SDHIMMC CARD
+    FSP_SIGNAL_SDHIMMC_DMA_REQ,                   ///< SDHIMMC DMA REQ
+    FSP_SIGNAL_SDHIMMC_SDIO,                      ///< SDHIMMC SDIO
+    FSP_SIGNAL_SPI_ERI = 0,                       ///< SPI ERI
+    FSP_SIGNAL_SPI_IDLE,                          ///< SPI IDLE
+    FSP_SIGNAL_SPI_RXI,                           ///< SPI RXI
+    FSP_SIGNAL_SPI_TEI,                           ///< SPI TEI
+    FSP_SIGNAL_SPI_TXI,                           ///< SPI TXI
+    FSP_SIGNAL_SRC_CONVERSION_END = 0,            ///< SRC CONVERSION END
+    FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY,              ///< SRC INPUT FIFO EMPTY
+    FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL,              ///< SRC OUTPUT FIFO FULL
+    FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW,          ///< SRC OUTPUT FIFO OVERFLOW
+    FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW,         ///< SRC OUTPUT FIFO UNDERFLOW
+    FSP_SIGNAL_SSI_INT = 0,                       ///< SSI INT
+    FSP_SIGNAL_SSI_RXI,                           ///< SSI RXI
+    FSP_SIGNAL_SSI_TXI,                           ///< SSI TXI
+    FSP_SIGNAL_SSI_TXI_RXI,                       ///< SSI TXI RXI
+    FSP_SIGNAL_TRNG_RDREQ = 0,                    ///< TRNG RDREQ
+    FSP_SIGNAL_USB_FIFO_0 = 0,                    ///< USB FIFO 0
+    FSP_SIGNAL_USB_FIFO_1,                        ///< USB FIFO 1
+    FSP_SIGNAL_USB_INT,                           ///< USB INT
+    FSP_SIGNAL_USB_RESUME,                        ///< USB RESUME
+    FSP_SIGNAL_USB_USB_INT_RESUME,                ///< USB USB INT RESUME
+    FSP_SIGNAL_WDT_UNDERFLOW = 0,                 ///< WDT UNDERFLOW
+} fsp_signal_t;
+
+typedef void (* fsp_vector_t)(void);
+
+/** @} (end addtogroup BSP_MCU) */
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_version.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_version.h
new file mode 100644
index 0000000000..cffdc0235e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/fsp_version.h
@@ -0,0 +1,81 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef FSP_VERSION_H
+#define FSP_VERSION_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+
+/* Includes board and MCU related header files. */
+#include "bsp_api.h"
+
+/*******************************************************************************************************************//**
+ * @addtogroup RENESAS_COMMON
+ * @{
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** FSP pack major version. */
+#define FSP_VERSION_MAJOR (1U)
+
+/** FSP pack minor version. */
+#define FSP_VERSION_MINOR (1U)
+
+/** FSP pack patch version. */
+#define FSP_VERSION_PATCH (1U)
+
+/** FSP pack version build number (currently unused). */
+#define FSP_VERSION_BUILD           (0U)
+
+/** Public FSP version name. */
+#define FSP_VERSION_STRING          ("1.1.1")
+
+/** Unique FSP version ID. */
+#define FSP_VERSION_BUILD_STRING    ("Built with Renesas Arm Flexible Software Package version 1.1.1")
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** FSP Pack version structure */
+typedef union st_fsp_pack_version
+{
+    /** Version id */
+    uint32_t version_id;
+
+    /** Code version parameters, little endian order. */
+    /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in FSP code. */
+    struct
+    {
+        uint8_t build;                 ///< Build version of FSP Pack
+        uint8_t patch;                 ///< Patch version of FSP Pack
+        uint8_t minor;                 ///< Minor version of FSP Pack
+        uint8_t major;                 ///< Major version of FSP Pack
+    };
+} fsp_pack_version_t;
+
+/** @} */
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_agt.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_agt.h
new file mode 100644
index 0000000000..a57bc248af
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_agt.h
@@ -0,0 +1,184 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef R_AGT_H
+#define R_AGT_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_agt_cfg.h"
+#include "r_timer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Leading zeroes removed to avoid coding standards violation. */
+#define AGT_CODE_VERSION_MAJOR    (1U)
+#define AGT_CODE_VERSION_MINOR    (1U)
+
+/** Maximum number of clock counts in 16 bit timer. */
+#define AGT_MAX_CLOCK_COUNTS      (UINT16_MAX)
+
+/** Maximum period value allowed for AGT. */
+#define AGT_MAX_PERIOD            (UINT16_MAX + 1U)
+
+/*******************************************************************************************************************//**
+ * @addtogroup AGT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Count source */
+typedef enum e_agt_clock
+{
+    AGT_CLOCK_PCLKB          = 0x00,   ///< PCLKB count source, division by 1, 2, or 8 allowed
+    AGT_CLOCK_LOCO           = 0x40,   ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed
+    AGT_CLOCK_AGT0_UNDERFLOW = 0x50,   ///< Underflow event signal from AGT0, division must be 1
+    AGT_CLOCK_SUBCLOCK       = 0x60,   ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed
+    AGT_CLOCK_P402           = 0x92,   ///< Counts events on P402, events are counted in deep software standby mode
+    AGT_CLOCK_P403           = 0x93,   ///< Counts events on P403, events are counted in deep software standby mode
+    AGT_CLOCK_AGTIO          = 0x80,   ///< Counts events on AGTIOn, events are not counted in software standby modes
+} agt_clock_t;
+
+/** Enable pin for event counting mode. */
+typedef enum e_agt_measure
+{
+    AGT_MEASURE_DISABLED               = 1U,    ///< AGT used as a counter
+    AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL  = 3U,    ///< AGT used to measure low level pulse width
+    AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL = 0x13U, ///< AGT used to measure high level pulse width
+    AGT_MEASURE_PULSE_PERIOD           = 4U,    ///< AGT used to measure pulse period
+} agt_measure_t;
+
+/** Input filter, applies AGTIO in pulse period measurement, pulse width measurement, or event counter mode. The filter
+ * requires the signal to be at the same level for 3 successive reads at the specified filter frequency. */
+typedef enum e_agt_agtio_filter
+{
+    AGT_AGTIO_FILTER_NONE         = 0x00U, ///< No filter
+    AGT_AGTIO_FILTER_PCLKB        = 0x10U, ///< Filter at PCLKB
+    AGT_AGTIO_FILTER_PCLKB_DIV_8  = 0x20U, ///< Filter at PCLKB / 8
+    AGT_AGTIO_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32
+} agt_agtio_filter_t;
+
+/** Enable pin for event counting mode. */
+typedef enum e_agt_enable_pin
+{
+    AGT_ENABLE_PIN_NOT_USED    = 0U,    ///< AGTEE is not used
+    AGT_ENABLE_PIN_ACTIVE_LOW  = 0x40U, ///< Events are only counted when AGTEE is low
+    AGT_ENABLE_PIN_ACTIVE_HIGH = 0x44U, ///< Events are only counted when AGTEE is high
+} agt_enable_pin_t;
+
+/** Trigger edge for pulse period measurement mode and event counting mode. */
+typedef enum e_agt_trigger_edge
+{
+    AGT_TRIGGER_EDGE_RISING  = 0U,     ///< Measurement starts or events are counted on rising edge
+    AGT_TRIGGER_EDGE_FALLING = 1U,     ///< Measurement starts or events are counted on falling edge
+    AGT_TRIGGER_EDGE_BOTH    = 8U,     ///< Events are counted on both edges (n/a for pulse period mode)
+} agt_trigger_edge_t;
+
+/** Output pins, used to select which duty cycle to update in R_AGT_DutyCycleSet(). */
+typedef enum e_agt_output_pin
+{
+    AGT_OUTPUT_PIN_AGTOA = 0,          ///< GTIOCA
+    AGT_OUTPUT_PIN_AGTOB = 1,          ///< GTIOCB
+} agt_output_pin_t;
+
+/** Level of AGT pin */
+typedef enum e_agt_pin_cfg
+{
+    AGT_PIN_CFG_DISABLED         = 0,  ///< Not used as output pin
+    AGT_PIN_CFG_START_LEVEL_LOW  = 3,  ///< Pin level low
+    AGT_PIN_CFG_START_LEVEL_HIGH = 7,  ///< Pin level high
+} agt_pin_cfg_t;
+
+/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
+typedef struct st_agt_instance_ctrl
+{
+    uint32_t            open;          ///< Whether or not channel is open
+    const timer_cfg_t * p_cfg;         ///< Pointer to initial configurations
+    R_AGT0_Type       * p_reg;         ///< Base register for this channel
+    uint32_t            period;        ///< Current timer period (counts)
+} agt_instance_ctrl_t;
+
+/** Optional AGT extension data structure.*/
+typedef struct st_agt_extended_cfg
+{
+    agt_clock_t count_source;          ///< AGT channel clock source. Valid values are: AGT_CLOCK_PCLKB, AGT_CLOCK_LOCO, AGT_CLOCK_FSUB
+
+    /* Output pin settings. */
+    union
+    {
+        uint8_t agtoab_settings;
+        struct
+        {
+            agt_pin_cfg_t agtoa : 3;     ///< Configure AGTOA pin
+            uint8_t             : 1;
+            agt_pin_cfg_t agtob : 3;     ///< Configure AGTOB pin
+        };
+    };
+    agt_pin_cfg_t agto : 3;              ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO
+
+    /* Input pin settings. */
+    agt_measure_t      measurement_mode; ///< Measurement mode
+    agt_agtio_filter_t agtio_filter;     ///< Input filter for AGTIO
+    agt_enable_pin_t   enable_pin;       ///< Enable pin (event counting only)
+    agt_trigger_edge_t trigger_edge;     ///< Trigger edge to start pulse period measurement or count external event
+} agt_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const timer_api_t g_timer_on_agt;
+
+/** @endcond */
+
+fsp_err_t R_AGT_Close(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
+fsp_err_t R_AGT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+fsp_err_t R_AGT_Reset(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_Start(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_Enable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_Disable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+fsp_err_t R_AGT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+fsp_err_t R_AGT_Stop(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_AGT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+fsp_err_t R_AGT_VersionGet(fsp_version_t * const p_version);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup AGT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+
+FSP_FOOTER
+
+#endif                                 // R_AGT_H
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h
new file mode 100644
index 0000000000..d66a22db74
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_flash_lp.h
@@ -0,0 +1,141 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#ifndef R_FLASH_LP_H
+#define R_FLASH_LP_H
+
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#include "r_flash_api.h"
+#include "r_flash_lp_cfg.h"
+
+/*******************************************************************************************************************//**
+ * @ingroup HAL_Library
+ * @addtogroup FLASH_LP
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define FLASH_LP_CODE_VERSION_MAJOR    (1U)
+#define FLASH_LP_CODE_VERSION_MINOR    (1U)
+
+/* If Code Flash programming is enabled, then code flash functions must execute out of RAM. */
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+ #if defined(__ICCARM__)
+  #pragma section=".code_in_ram"
+ #endif
+ #if defined(__ARMCC_VERSION)
+  #define PLACE_IN_RAM_SECTION    BSP_PLACE_IN_SECTION(".code_in_ram") __attribute__((noinline))
+ #else
+  #define PLACE_IN_RAM_SECTION    BSP_PLACE_IN_SECTION(".code_in_ram")
+ #endif
+#else
+ #define PLACE_IN_RAM_SECTION
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* Possible Flash operation states */
+typedef enum e_flash_bgo_operation
+{
+    FLASH_OPERATION_NON_BGO,
+    FLASH_OPERATION_DF_BGO_WRITE,
+    FLASH_OPERATION_DF_BGO_ERASE,
+    FLASH_OPERATION_DF_BGO_BLANKCHECK,
+} flash_bgo_operation_t;
+
+/** Flash instance control block. DO NOT INITIALIZE. Initialization occurs when R_FLASH_LP_Open() is called. */
+typedef struct st_flash_lp_instance_ctrl
+{
+    uint32_t              opened;                   // To check whether api has been opened or not.
+    flash_cfg_t const   * p_cfg;                    // Pointer to the flash configuration block.
+    uint32_t              system_clock_frequency;   // System clock frequency
+    uint32_t              flash_clock_frequency;    // FlashIF clock frequency
+    uint32_t              timeout_write_cf;         // Timeout for writing code flash data
+    uint32_t              timeout_write_df;         // Timeout for writing data flash data
+    uint32_t              timeout_blank_check;      // Timeout for blank check operations
+    uint32_t              timeout_erase_cf_block;   // Timeout for erasing a code flash block
+    uint32_t              timeout_erase_df_block;   // Timeout for erasing a data flash block
+    uint32_t              timeout_write_extra_area; // Timeout for writing to the configuration area
+    uint32_t              source_start_address;     // Source/Start address of in progress operation
+    uint32_t              dest_end_address;         // Destination/End address of in progress operation
+    uint32_t              operations_remaining;     // Number of operations remaining
+    flash_bgo_operation_t current_operation;        // Type of BGO operation in progress.
+} flash_lp_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const flash_api_t g_flash_on_flash_lp;
+
+/** @endcond */
+
+fsp_err_t R_FLASH_LP_Open(flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg);
+fsp_err_t R_FLASH_LP_Write(flash_ctrl_t * const p_api_ctrl,
+                           uint32_t const       src_address,
+                           uint32_t             flash_address,
+                           uint32_t const       num_bytes);
+fsp_err_t R_FLASH_LP_Erase(flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks);
+fsp_err_t R_FLASH_LP_BlankCheck(flash_ctrl_t * const p_api_ctrl,
+                                uint32_t const       address,
+                                uint32_t             num_bytes,
+                                flash_result_t     * blank_check_result);
+fsp_err_t R_FLASH_LP_Close(flash_ctrl_t * const p_api_ctrl);
+fsp_err_t R_FLASH_LP_StatusGet(flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status);
+fsp_err_t R_FLASH_LP_AccessWindowSet(flash_ctrl_t * const p_api_ctrl, uint32_t const start_addr,
+                                     uint32_t const end_addr);
+fsp_err_t R_FLASH_LP_AccessWindowClear(flash_ctrl_t * const p_api_ctrl);
+fsp_err_t R_FLASH_LP_IdCodeSet(flash_ctrl_t * const  p_api_ctrl,
+                               uint8_t const * const p_id_code,
+                               flash_id_code_mode_t  mode);
+fsp_err_t R_FLASH_LP_Reset(flash_ctrl_t * const p_api_ctrl);
+fsp_err_t R_FLASH_LP_StartUpAreaSelect(flash_ctrl_t * const      p_api_ctrl,
+                                       flash_startup_area_swap_t swap_type,
+                                       bool                      is_temporary);
+fsp_err_t R_FLASH_LP_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl);
+fsp_err_t R_FLASH_LP_VersionGet(fsp_version_t * const p_version);
+fsp_err_t R_FLASH_LP_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info);
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup FLASH_LP)
+ **********************************************************************************************************************/
+
+/* This will generate a build error if this file is included and the target MCU used is NOT one of the following. */
+#if !BSP_FEATURE_FLASH_LP_VERSION
+ #error "r_flash_lp is not a supported module for this board type."
+#endif
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h
new file mode 100644
index 0000000000..0348d328dc
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_gpt.h
@@ -0,0 +1,358 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef R_GPT_H
+#define R_GPT_H
+
+/*******************************************************************************************************************//**
+ * @addtogroup GPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_timer_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define GPT_CODE_VERSION_MAJOR    (1U)
+#define GPT_CODE_VERSION_MINOR    (0U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */
+typedef enum e_gpt_io_pin
+{
+    GPT_IO_PIN_GTIOCA            = 0,  ///< GTIOCA
+    GPT_IO_PIN_GTIOCB            = 1,  ///< GTIOCB
+    GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2,  ///< GTIOCA and GTIOCB
+} gpt_io_pin_t;
+
+/** Level of GPT pin */
+typedef enum e_gpt_pin_level
+{
+    GPT_PIN_LEVEL_LOW  = 0,            ///< Pin level low
+    GPT_PIN_LEVEL_HIGH = 1,            ///< Pin level high
+} gpt_pin_level_t;
+
+/** GPT PWM shortest pin level */
+typedef enum e_gpt_shortest_level
+{
+    /** 1 extra PCLK in ON time. Minimum ON time will be limited to 2 PCLK raw counts. */
+    GPT_SHORTEST_LEVEL_OFF = 0,
+
+    /** 1 extra PCLK in OFF time. Minimum ON time will be limited to 1 PCLK raw counts. */
+    GPT_SHORTEST_LEVEL_ON = 1,
+} gpt_shortest_level_t;
+
+/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent
+ * a bitmask. Multiple sources can be ORed together. */
+typedef enum e_gpt_source
+{
+    /** No active event sources. */
+    GPT_SOURCE_NONE = 0U,
+
+    /** Action performed on GTETRGA rising edge. **/
+    GPT_SOURCE_GTETRGA_RISING = (1U << 0),
+
+    /** Action performed on GTETRGA falling edge. **/
+    GPT_SOURCE_GTETRGA_FALLING = (1U << 1),
+
+    /** Action performed on GTETRGB rising edge. **/
+    GPT_SOURCE_GTETRGB_RISING = (1U << 2),
+
+    /** Action performed on GTETRGB falling edge. **/
+    GPT_SOURCE_GTETRGB_FALLING = (1U << 3),
+
+    /** Action performed on GTETRGC rising edge. **/
+    GPT_SOURCE_GTETRGC_RISING = (1U << 4),
+
+    /** Action performed on GTETRGC falling edge. **/
+    GPT_SOURCE_GTETRGC_FALLING = (1U << 5),
+
+    /** Action performed on GTETRGB rising edge. **/
+    GPT_SOURCE_GTETRGD_RISING = (1U << 6),
+
+    /** Action performed on GTETRGB falling edge. **/
+    GPT_SOURCE_GTETRGD_FALLING = (1U << 7),
+
+    /** Action performed when GTIOCA input rises while GTIOCB is low. **/
+    GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8),
+
+    /** Action performed when GTIOCA input rises while GTIOCB is high. **/
+    GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9),
+
+    /** Action performed when GTIOCA input falls while GTIOCB is low. **/
+    GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10),
+
+    /** Action performed when GTIOCA input falls while GTIOCB is high. **/
+    GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11),
+
+    /** Action performed when GTIOCB input rises while GTIOCA is low. **/
+    GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12),
+
+    /** Action performed when GTIOCB input rises while GTIOCA is high. **/
+    GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13),
+
+    /** Action performed when GTIOCB input falls while GTIOCA is low. **/
+    GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14),
+
+    /** Action performed when GTIOCB input falls while GTIOCA is high. **/
+    GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15),
+
+    /** Action performed on ELC GPTA event. **/
+    GPT_SOURCE_GPT_A = (1U << 16),
+
+    /** Action performed on ELC GPTB event. **/
+    GPT_SOURCE_GPT_B = (1U << 17),
+
+    /** Action performed on ELC GPTC event. **/
+    GPT_SOURCE_GPT_C = (1U << 18),
+
+    /** Action performed on ELC GPTD event. **/
+    GPT_SOURCE_GPT_D = (1U << 19),
+
+    /** Action performed on ELC GPTE event. **/
+    GPT_SOURCE_GPT_E = (1U << 20),
+
+    /** Action performed on ELC GPTF event. **/
+    GPT_SOURCE_GPT_F = (1U << 21),
+
+    /** Action performed on ELC GPTG event. **/
+    GPT_SOURCE_GPT_G = (1U << 22),
+
+    /** Action performed on ELC GPTH event. **/
+    GPT_SOURCE_GPT_H = (1U << 23),
+} gpt_source_t;
+
+/** Configurations for output pins. */
+typedef struct s_gpt_output_pin
+{
+    bool            output_enabled;    ///< Set to true to enable output, false to disable output
+    gpt_pin_level_t stop_level;        ///< Select a stop level from ::gpt_pin_level_t
+} gpt_output_pin_t;
+
+/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB.
+ *   The noise filter samples the external signal at intervals of the PCLK divided by one of the values.
+ *   When 3 consecutive samples are at the same level (high or low), then that level is passed on as
+ *   the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section.
+ */
+typedef enum e_gpt_capture_filter
+{
+    GPT_CAPTURE_FILTER_NONE         = 0U, ///< None - no filtering
+    GPT_CAPTURE_FILTER_PCLKD_DIV_1  = 1U, ///< PCLK/1 - fast sampling
+    GPT_CAPTURE_FILTER_PCLKD_DIV_4  = 3U, ///< PCLK/4
+    GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16
+    GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling
+} gpt_capture_filter_t;
+
+/** Trigger options to start A/D conversion. */
+typedef enum e_gpt_adc_trigger
+{
+    GPT_ADC_TRIGGER_NONE                   = 0U,      ///< None - no output disable request
+    GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A   = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
+    GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
+    GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B   = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
+    GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
+} gpt_adc_trigger_t;
+
+/** POEG channel to link to this channel. */
+typedef enum e_gpt_poeg_link
+{
+    GPT_POEG_LINK_POEG0 = 0U,          ///< Link this GPT channel to POEG channel 0 (GTETRGA)
+    GPT_POEG_LINK_POEG1 = 1U,          ///< Link this GPT channel to POEG channel 1 (GTETRGB)
+    GPT_POEG_LINK_POEG2 = 2U,          ///< Link this GPT channel to POEG channel 2 (GTETRGC)
+    GPT_POEG_LINK_POEG3 = 3U,          ///< Link this GPT channel to POEG channel 3 (GTETRGD)
+} gpt_poeg_link_t;
+
+/** Select trigger to send output disable request to POEG. */
+typedef enum e_gpt_output_disable
+{
+    GPT_OUTPUT_DISABLE_NONE               = 0U,      ///< None - no output disable request
+    GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR    = 1U << 0, ///< Request output disable if a dead time error occurs
+    GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time
+    GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW  = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time
+} gpt_output_disable_t;
+
+/** Disable level options for GTIOC pins. */
+typedef enum e_gpt_gtioc_disable
+{
+    GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable
+    GPT_GTIOC_DISABLE_SET_HI_Z   = 1U, ///< Set GTIOC to high impedance when output is disabled
+    GPT_GTIOC_DISABLE_LEVEL_LOW  = 2U, ///< Set GTIOC level low when output is disabled
+    GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled
+} gpt_gtioc_disable_t;
+
+/** Trigger options to start A/D conversion. */
+typedef enum e_gpt_adc_compare_match
+{
+    GPT_ADC_COMPARE_MATCH_ADC_A = 0U,  ///< Set A/D conversion start request value for GPT A/D converter start request A
+    GPT_ADC_COMPARE_MATCH_ADC_B = 3U,  ///< Set A/D conversion start request value for GPT A/D converter start request B
+} gpt_adc_compare_match_t;
+
+/** Interrupt skipping modes */
+typedef enum e_gpt_interrupt_skip_source
+{
+    GPT_INTERRUPT_SKIP_SOURCE_NONE               = 0U, ///< Do not skip interrupts
+    GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts
+
+    /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
+     *  @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest
+     * interrupt. */
+    GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U,
+
+    /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
+     *  @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough
+     *  interrupt. */
+    GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U,
+} gpt_interrupt_skip_source_t;
+
+/** Number of interrupts to skip between events */
+typedef enum e_gpt_interrupt_skip_count
+{
+    GPT_INTERRUPT_SKIP_COUNT_0 = 0U,   ///< Do not skip interrupts
+    GPT_INTERRUPT_SKIP_COUNT_1,        ///< Skip one interrupt
+    GPT_INTERRUPT_SKIP_COUNT_2,        ///< Skip two interrupts
+    GPT_INTERRUPT_SKIP_COUNT_3,        ///< Skip three interrupts
+    GPT_INTERRUPT_SKIP_COUNT_4,        ///< Skip four interrupts
+    GPT_INTERRUPT_SKIP_COUNT_5,        ///< Skip five interrupts
+    GPT_INTERRUPT_SKIP_COUNT_6,        ///< Skip six interrupts
+    GPT_INTERRUPT_SKIP_COUNT_7,        ///< Skip seven interrupts
+} gpt_interrupt_skip_count_t;
+
+/** ADC events to skip during interrupt skipping */
+typedef enum e_gpt_interrupt_skip_adc
+{
+    GPT_INTERRUPT_SKIP_ADC_NONE    = 0U, ///< Do not skip ADC events
+    GPT_INTERRUPT_SKIP_ADC_A       = 1U, ///< Skip ADC A events
+    GPT_INTERRUPT_SKIP_ADC_B       = 4U, ///< Skip ADC B events
+    GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events
+} gpt_interrupt_skip_adc_t;
+
+/** Channel control block. DO NOT INITIALIZE.  Initialization occurs when @ref timer_api_t::open is called. */
+typedef struct st_gpt_instance_ctrl
+{
+    uint32_t            open;          // Whether or not channel is open
+    const timer_cfg_t * p_cfg;         // Pointer to initial configurations
+    R_GPT0_Type       * p_reg;         // Base register for this channel
+    uint32_t            channel_mask;  // Channel bitmask
+    timer_variant_t     variant;       // Timer variant
+} gpt_instance_ctrl_t;
+
+/** GPT extension for advanced PWM features. */
+typedef struct st_gpt_extended_pwm_cfg
+{
+    uint8_t                     trough_ipl;             ///< Trough interrupt priority
+    IRQn_Type                   trough_irq;             ///< Trough interrupt
+    gpt_poeg_link_t             poeg_link;              ///< Select which POEG channel controls output disable for this GPT channel
+    gpt_output_disable_t        output_disable;         ///< Select which trigger sources request output disable from POEG
+    gpt_adc_trigger_t           adc_trigger;            ///< Select trigger sources to start A/D conversion
+    uint32_t                    dead_time_count_up;     ///< Set a dead time value for counting up
+    uint32_t                    dead_time_count_down;   ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only)
+    uint32_t                    adc_a_compare_match;    ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_A
+    uint32_t                    adc_b_compare_match;    ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_B
+    gpt_interrupt_skip_source_t interrupt_skip_source;  ///< Interrupt source to count for interrupt skipping
+    gpt_interrupt_skip_count_t  interrupt_skip_count;   ///< Number of interrupts to skip between events
+    gpt_interrupt_skip_adc_t    interrupt_skip_adc;     ///< ADC events to skip when interrupt skipping is enabled
+    gpt_gtioc_disable_t         gtioca_disable_setting; ///< Select how to configure GTIOCA when output is disabled
+    gpt_gtioc_disable_t         gtiocb_disable_setting; ///< Select how to configure GTIOCB when output is disabled
+} gpt_extended_pwm_cfg_t;
+
+/** GPT extension configures the output pins for GPT. */
+typedef struct st_gpt_extended_cfg
+{
+    gpt_output_pin_t     gtioca;              ///< Configuration for GPT I/O pin A
+    gpt_output_pin_t     gtiocb;              ///< Configuration for GPT I/O pin B
+    gpt_shortest_level_t shortest_pwm_signal; ///< Shortest PWM signal level
+    gpt_source_t         start_source;        ///< Event sources that trigger the timer to start
+    gpt_source_t         stop_source;         ///< Event sources that trigger the timer to stop
+    gpt_source_t         clear_source;        ///< Event sources that trigger the timer to clear
+    gpt_source_t         capture_a_source;    ///< Event sources that trigger capture of GTIOCA
+    gpt_source_t         capture_b_source;    ///< Event sources that trigger capture of GTIOCB
+
+    /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source
+     * and count_down_source, then the timer count source is PCLK.  */
+    gpt_source_t count_up_source;
+
+    /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source
+     * and count_down_source, then the timer count source is PCLK.  */
+    gpt_source_t count_down_source;
+
+    /* Debounce filter for GTIOCxA input signal pin. */
+    gpt_capture_filter_t capture_filter_gtioca;
+
+    /* Debounce filter for GTIOCxB input signal pin. */
+    gpt_capture_filter_t capture_filter_gtiocb;
+
+    uint8_t   capture_a_ipl;                  ///< Capture A interrupt priority
+    uint8_t   capture_b_ipl;                  ///< Capture B interrupt priority
+    IRQn_Type capture_a_irq;                  ///< Capture A interrupt
+    IRQn_Type capture_b_irq;                  ///< Capture B interrupt
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional
+} gpt_extended_cfg_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const timer_api_t g_timer_on_gpt;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
+fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
+fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
+fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
+fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
+fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
+fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
+fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
+fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const    p_ctrl,
+                              gpt_adc_compare_match_t which_compare_match,
+                              uint32_t                compare_match_value);
+fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl);
+fsp_err_t R_GPT_VersionGet(fsp_version_t * const p_version);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup GPT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_icu.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_icu.h
new file mode 100644
index 0000000000..0089ebb226
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_icu.h
@@ -0,0 +1,92 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup ICU
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_ICU_H
+#define R_ICU_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "r_external_irq_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define ICU_CODE_VERSION_MAJOR    (1U)
+#define ICU_CODE_VERSION_MINOR    (0U)
+
+/*********************************************************************************************************************
+ * Typedef definitions
+ *********************************************************************************************************************/
+
+/** ICU private control block. DO NOT MODIFY.  Initialization occurs when R_ICU_ExternalIrqOpen is called. */
+typedef struct st_icu_instance_ctrl
+{
+    uint32_t  open;                    ///< Used to determine if channel control block is in use
+    IRQn_Type irq;                     ///< NVIC interrupt number
+    uint8_t   channel;                 ///< Channel
+
+    /** Callback provided when a external IRQ ISR occurs. Set to NULL for no CPU interrupt. */
+    void (* p_callback)(external_irq_callback_args_t * p_args);
+
+    /** Placeholder for user data.  Passed to the user callback in ::external_irq_callback_args_t. */
+    void const * p_context;
+} icu_instance_ctrl_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const external_irq_api_t g_external_irq_on_icu;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg);
+
+fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl);
+
+fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl);
+
+fsp_err_t R_ICU_ExternalIrqVersionGet(fsp_version_t * const p_version);
+
+fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup ICU)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_ICU_H
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h
new file mode 100644
index 0000000000..fe48ab6e4e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/r_ioport.h
@@ -0,0 +1,311 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup IOPORT
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef R_IOPORT_H
+#define R_IOPORT_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#include "r_ioport_api.h"
+#include "r_ioport_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define IOPORT_CODE_VERSION_MAJOR    (1U)
+#define IOPORT_CODE_VERSION_MINOR    (1U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
+typedef struct st_ioport_instance_ctrl
+{
+    uint32_t     open;
+    void const * p_context;
+} ioport_instance_ctrl_t;
+
+/* This typedef is here temporarily. See SWFLEX-144 for details. */
+/** Superset list of all possible IO port pins. */
+typedef enum e_ioport_port_pin_t
+{
+    IOPORT_PORT_00_PIN_00 = 0x0000,    ///< IO port 0 pin 0
+    IOPORT_PORT_00_PIN_01 = 0x0001,    ///< IO port 0 pin 1
+    IOPORT_PORT_00_PIN_02 = 0x0002,    ///< IO port 0 pin 2
+    IOPORT_PORT_00_PIN_03 = 0x0003,    ///< IO port 0 pin 3
+    IOPORT_PORT_00_PIN_04 = 0x0004,    ///< IO port 0 pin 4
+    IOPORT_PORT_00_PIN_05 = 0x0005,    ///< IO port 0 pin 5
+    IOPORT_PORT_00_PIN_06 = 0x0006,    ///< IO port 0 pin 6
+    IOPORT_PORT_00_PIN_07 = 0x0007,    ///< IO port 0 pin 7
+    IOPORT_PORT_00_PIN_08 = 0x0008,    ///< IO port 0 pin 8
+    IOPORT_PORT_00_PIN_09 = 0x0009,    ///< IO port 0 pin 9
+    IOPORT_PORT_00_PIN_10 = 0x000A,    ///< IO port 0 pin 10
+    IOPORT_PORT_00_PIN_11 = 0x000B,    ///< IO port 0 pin 11
+    IOPORT_PORT_00_PIN_12 = 0x000C,    ///< IO port 0 pin 12
+    IOPORT_PORT_00_PIN_13 = 0x000D,    ///< IO port 0 pin 13
+    IOPORT_PORT_00_PIN_14 = 0x000E,    ///< IO port 0 pin 14
+    IOPORT_PORT_00_PIN_15 = 0x000F,    ///< IO port 0 pin 15
+
+    IOPORT_PORT_01_PIN_00 = 0x0100,    ///< IO port 1 pin 0
+    IOPORT_PORT_01_PIN_01 = 0x0101,    ///< IO port 1 pin 1
+    IOPORT_PORT_01_PIN_02 = 0x0102,    ///< IO port 1 pin 2
+    IOPORT_PORT_01_PIN_03 = 0x0103,    ///< IO port 1 pin 3
+    IOPORT_PORT_01_PIN_04 = 0x0104,    ///< IO port 1 pin 4
+    IOPORT_PORT_01_PIN_05 = 0x0105,    ///< IO port 1 pin 5
+    IOPORT_PORT_01_PIN_06 = 0x0106,    ///< IO port 1 pin 6
+    IOPORT_PORT_01_PIN_07 = 0x0107,    ///< IO port 1 pin 7
+    IOPORT_PORT_01_PIN_08 = 0x0108,    ///< IO port 1 pin 8
+    IOPORT_PORT_01_PIN_09 = 0x0109,    ///< IO port 1 pin 9
+    IOPORT_PORT_01_PIN_10 = 0x010A,    ///< IO port 1 pin 10
+    IOPORT_PORT_01_PIN_11 = 0x010B,    ///< IO port 1 pin 11
+    IOPORT_PORT_01_PIN_12 = 0x010C,    ///< IO port 1 pin 12
+    IOPORT_PORT_01_PIN_13 = 0x010D,    ///< IO port 1 pin 13
+    IOPORT_PORT_01_PIN_14 = 0x010E,    ///< IO port 1 pin 14
+    IOPORT_PORT_01_PIN_15 = 0x010F,    ///< IO port 1 pin 15
+
+    IOPORT_PORT_02_PIN_00 = 0x0200,    ///< IO port 2 pin 0
+    IOPORT_PORT_02_PIN_01 = 0x0201,    ///< IO port 2 pin 1
+    IOPORT_PORT_02_PIN_02 = 0x0202,    ///< IO port 2 pin 2
+    IOPORT_PORT_02_PIN_03 = 0x0203,    ///< IO port 2 pin 3
+    IOPORT_PORT_02_PIN_04 = 0x0204,    ///< IO port 2 pin 4
+    IOPORT_PORT_02_PIN_05 = 0x0205,    ///< IO port 2 pin 5
+    IOPORT_PORT_02_PIN_06 = 0x0206,    ///< IO port 2 pin 6
+    IOPORT_PORT_02_PIN_07 = 0x0207,    ///< IO port 2 pin 7
+    IOPORT_PORT_02_PIN_08 = 0x0208,    ///< IO port 2 pin 8
+    IOPORT_PORT_02_PIN_09 = 0x0209,    ///< IO port 2 pin 9
+    IOPORT_PORT_02_PIN_10 = 0x020A,    ///< IO port 2 pin 10
+    IOPORT_PORT_02_PIN_11 = 0x020B,    ///< IO port 2 pin 11
+    IOPORT_PORT_02_PIN_12 = 0x020C,    ///< IO port 2 pin 12
+    IOPORT_PORT_02_PIN_13 = 0x020D,    ///< IO port 2 pin 13
+    IOPORT_PORT_02_PIN_14 = 0x020E,    ///< IO port 2 pin 14
+    IOPORT_PORT_02_PIN_15 = 0x020F,    ///< IO port 2 pin 15
+
+    IOPORT_PORT_03_PIN_00 = 0x0300,    ///< IO port 3 pin 0
+    IOPORT_PORT_03_PIN_01 = 0x0301,    ///< IO port 3 pin 1
+    IOPORT_PORT_03_PIN_02 = 0x0302,    ///< IO port 3 pin 2
+    IOPORT_PORT_03_PIN_03 = 0x0303,    ///< IO port 3 pin 3
+    IOPORT_PORT_03_PIN_04 = 0x0304,    ///< IO port 3 pin 4
+    IOPORT_PORT_03_PIN_05 = 0x0305,    ///< IO port 3 pin 5
+    IOPORT_PORT_03_PIN_06 = 0x0306,    ///< IO port 3 pin 6
+    IOPORT_PORT_03_PIN_07 = 0x0307,    ///< IO port 3 pin 7
+    IOPORT_PORT_03_PIN_08 = 0x0308,    ///< IO port 3 pin 8
+    IOPORT_PORT_03_PIN_09 = 0x0309,    ///< IO port 3 pin 9
+    IOPORT_PORT_03_PIN_10 = 0x030A,    ///< IO port 3 pin 10
+    IOPORT_PORT_03_PIN_11 = 0x030B,    ///< IO port 3 pin 11
+    IOPORT_PORT_03_PIN_12 = 0x030C,    ///< IO port 3 pin 12
+    IOPORT_PORT_03_PIN_13 = 0x030D,    ///< IO port 3 pin 13
+    IOPORT_PORT_03_PIN_14 = 0x030E,    ///< IO port 3 pin 14
+    IOPORT_PORT_03_PIN_15 = 0x030F,    ///< IO port 3 pin 15
+
+    IOPORT_PORT_04_PIN_00 = 0x0400,    ///< IO port 4 pin 0
+    IOPORT_PORT_04_PIN_01 = 0x0401,    ///< IO port 4 pin 1
+    IOPORT_PORT_04_PIN_02 = 0x0402,    ///< IO port 4 pin 2
+    IOPORT_PORT_04_PIN_03 = 0x0403,    ///< IO port 4 pin 3
+    IOPORT_PORT_04_PIN_04 = 0x0404,    ///< IO port 4 pin 4
+    IOPORT_PORT_04_PIN_05 = 0x0405,    ///< IO port 4 pin 5
+    IOPORT_PORT_04_PIN_06 = 0x0406,    ///< IO port 4 pin 6
+    IOPORT_PORT_04_PIN_07 = 0x0407,    ///< IO port 4 pin 7
+    IOPORT_PORT_04_PIN_08 = 0x0408,    ///< IO port 4 pin 8
+    IOPORT_PORT_04_PIN_09 = 0x0409,    ///< IO port 4 pin 9
+    IOPORT_PORT_04_PIN_10 = 0x040A,    ///< IO port 4 pin 10
+    IOPORT_PORT_04_PIN_11 = 0x040B,    ///< IO port 4 pin 11
+    IOPORT_PORT_04_PIN_12 = 0x040C,    ///< IO port 4 pin 12
+    IOPORT_PORT_04_PIN_13 = 0x040D,    ///< IO port 4 pin 13
+    IOPORT_PORT_04_PIN_14 = 0x040E,    ///< IO port 4 pin 14
+    IOPORT_PORT_04_PIN_15 = 0x040F,    ///< IO port 4 pin 15
+
+    IOPORT_PORT_05_PIN_00 = 0x0500,    ///< IO port 5 pin 0
+    IOPORT_PORT_05_PIN_01 = 0x0501,    ///< IO port 5 pin 1
+    IOPORT_PORT_05_PIN_02 = 0x0502,    ///< IO port 5 pin 2
+    IOPORT_PORT_05_PIN_03 = 0x0503,    ///< IO port 5 pin 3
+    IOPORT_PORT_05_PIN_04 = 0x0504,    ///< IO port 5 pin 4
+    IOPORT_PORT_05_PIN_05 = 0x0505,    ///< IO port 5 pin 5
+    IOPORT_PORT_05_PIN_06 = 0x0506,    ///< IO port 5 pin 6
+    IOPORT_PORT_05_PIN_07 = 0x0507,    ///< IO port 5 pin 7
+    IOPORT_PORT_05_PIN_08 = 0x0508,    ///< IO port 5 pin 8
+    IOPORT_PORT_05_PIN_09 = 0x0509,    ///< IO port 5 pin 9
+    IOPORT_PORT_05_PIN_10 = 0x050A,    ///< IO port 5 pin 10
+    IOPORT_PORT_05_PIN_11 = 0x050B,    ///< IO port 5 pin 11
+    IOPORT_PORT_05_PIN_12 = 0x050C,    ///< IO port 5 pin 12
+    IOPORT_PORT_05_PIN_13 = 0x050D,    ///< IO port 5 pin 13
+    IOPORT_PORT_05_PIN_14 = 0x050E,    ///< IO port 5 pin 14
+    IOPORT_PORT_05_PIN_15 = 0x050F,    ///< IO port 5 pin 15
+
+    IOPORT_PORT_06_PIN_00 = 0x0600,    ///< IO port 6 pin 0
+    IOPORT_PORT_06_PIN_01 = 0x0601,    ///< IO port 6 pin 1
+    IOPORT_PORT_06_PIN_02 = 0x0602,    ///< IO port 6 pin 2
+    IOPORT_PORT_06_PIN_03 = 0x0603,    ///< IO port 6 pin 3
+    IOPORT_PORT_06_PIN_04 = 0x0604,    ///< IO port 6 pin 4
+    IOPORT_PORT_06_PIN_05 = 0x0605,    ///< IO port 6 pin 5
+    IOPORT_PORT_06_PIN_06 = 0x0606,    ///< IO port 6 pin 6
+    IOPORT_PORT_06_PIN_07 = 0x0607,    ///< IO port 6 pin 7
+    IOPORT_PORT_06_PIN_08 = 0x0608,    ///< IO port 6 pin 8
+    IOPORT_PORT_06_PIN_09 = 0x0609,    ///< IO port 6 pin 9
+    IOPORT_PORT_06_PIN_10 = 0x060A,    ///< IO port 6 pin 10
+    IOPORT_PORT_06_PIN_11 = 0x060B,    ///< IO port 6 pin 11
+    IOPORT_PORT_06_PIN_12 = 0x060C,    ///< IO port 6 pin 12
+    IOPORT_PORT_06_PIN_13 = 0x060D,    ///< IO port 6 pin 13
+    IOPORT_PORT_06_PIN_14 = 0x060E,    ///< IO port 6 pin 14
+    IOPORT_PORT_06_PIN_15 = 0x060F,    ///< IO port 6 pin 15
+
+    IOPORT_PORT_07_PIN_00 = 0x0700,    ///< IO port 7 pin 0
+    IOPORT_PORT_07_PIN_01 = 0x0701,    ///< IO port 7 pin 1
+    IOPORT_PORT_07_PIN_02 = 0x0702,    ///< IO port 7 pin 2
+    IOPORT_PORT_07_PIN_03 = 0x0703,    ///< IO port 7 pin 3
+    IOPORT_PORT_07_PIN_04 = 0x0704,    ///< IO port 7 pin 4
+    IOPORT_PORT_07_PIN_05 = 0x0705,    ///< IO port 7 pin 5
+    IOPORT_PORT_07_PIN_06 = 0x0706,    ///< IO port 7 pin 6
+    IOPORT_PORT_07_PIN_07 = 0x0707,    ///< IO port 7 pin 7
+    IOPORT_PORT_07_PIN_08 = 0x0708,    ///< IO port 7 pin 8
+    IOPORT_PORT_07_PIN_09 = 0x0709,    ///< IO port 7 pin 9
+    IOPORT_PORT_07_PIN_10 = 0x070A,    ///< IO port 7 pin 10
+    IOPORT_PORT_07_PIN_11 = 0x070B,    ///< IO port 7 pin 11
+    IOPORT_PORT_07_PIN_12 = 0x070C,    ///< IO port 7 pin 12
+    IOPORT_PORT_07_PIN_13 = 0x070D,    ///< IO port 7 pin 13
+    IOPORT_PORT_07_PIN_14 = 0x070E,    ///< IO port 7 pin 14
+    IOPORT_PORT_07_PIN_15 = 0x070F,    ///< IO port 7 pin 15
+
+    IOPORT_PORT_08_PIN_00 = 0x0800,    ///< IO port 8 pin 0
+    IOPORT_PORT_08_PIN_01 = 0x0801,    ///< IO port 8 pin 1
+    IOPORT_PORT_08_PIN_02 = 0x0802,    ///< IO port 8 pin 2
+    IOPORT_PORT_08_PIN_03 = 0x0803,    ///< IO port 8 pin 3
+    IOPORT_PORT_08_PIN_04 = 0x0804,    ///< IO port 8 pin 4
+    IOPORT_PORT_08_PIN_05 = 0x0805,    ///< IO port 8 pin 5
+    IOPORT_PORT_08_PIN_06 = 0x0806,    ///< IO port 8 pin 6
+    IOPORT_PORT_08_PIN_07 = 0x0807,    ///< IO port 8 pin 7
+    IOPORT_PORT_08_PIN_08 = 0x0808,    ///< IO port 8 pin 8
+    IOPORT_PORT_08_PIN_09 = 0x0809,    ///< IO port 8 pin 9
+    IOPORT_PORT_08_PIN_10 = 0x080A,    ///< IO port 8 pin 10
+    IOPORT_PORT_08_PIN_11 = 0x080B,    ///< IO port 8 pin 11
+    IOPORT_PORT_08_PIN_12 = 0x080C,    ///< IO port 8 pin 12
+    IOPORT_PORT_08_PIN_13 = 0x080D,    ///< IO port 8 pin 13
+    IOPORT_PORT_08_PIN_14 = 0x080E,    ///< IO port 8 pin 14
+    IOPORT_PORT_08_PIN_15 = 0x080F,    ///< IO port 8 pin 15
+
+    IOPORT_PORT_09_PIN_00 = 0x0900,    ///< IO port 9 pin 0
+    IOPORT_PORT_09_PIN_01 = 0x0901,    ///< IO port 9 pin 1
+    IOPORT_PORT_09_PIN_02 = 0x0902,    ///< IO port 9 pin 2
+    IOPORT_PORT_09_PIN_03 = 0x0903,    ///< IO port 9 pin 3
+    IOPORT_PORT_09_PIN_04 = 0x0904,    ///< IO port 9 pin 4
+    IOPORT_PORT_09_PIN_05 = 0x0905,    ///< IO port 9 pin 5
+    IOPORT_PORT_09_PIN_06 = 0x0906,    ///< IO port 9 pin 6
+    IOPORT_PORT_09_PIN_07 = 0x0907,    ///< IO port 9 pin 7
+    IOPORT_PORT_09_PIN_08 = 0x0908,    ///< IO port 9 pin 8
+    IOPORT_PORT_09_PIN_09 = 0x0909,    ///< IO port 9 pin 9
+    IOPORT_PORT_09_PIN_10 = 0x090A,    ///< IO port 9 pin 10
+    IOPORT_PORT_09_PIN_11 = 0x090B,    ///< IO port 9 pin 11
+    IOPORT_PORT_09_PIN_12 = 0x090C,    ///< IO port 9 pin 12
+    IOPORT_PORT_09_PIN_13 = 0x090D,    ///< IO port 9 pin 13
+    IOPORT_PORT_09_PIN_14 = 0x090E,    ///< IO port 9 pin 14
+    IOPORT_PORT_09_PIN_15 = 0x090F,    ///< IO port 9 pin 15
+
+    IOPORT_PORT_10_PIN_00 = 0x0A00,    ///< IO port 10 pin 0
+    IOPORT_PORT_10_PIN_01 = 0x0A01,    ///< IO port 10 pin 1
+    IOPORT_PORT_10_PIN_02 = 0x0A02,    ///< IO port 10 pin 2
+    IOPORT_PORT_10_PIN_03 = 0x0A03,    ///< IO port 10 pin 3
+    IOPORT_PORT_10_PIN_04 = 0x0A04,    ///< IO port 10 pin 4
+    IOPORT_PORT_10_PIN_05 = 0x0A05,    ///< IO port 10 pin 5
+    IOPORT_PORT_10_PIN_06 = 0x0A06,    ///< IO port 10 pin 6
+    IOPORT_PORT_10_PIN_07 = 0x0A07,    ///< IO port 10 pin 7
+    IOPORT_PORT_10_PIN_08 = 0x0A08,    ///< IO port 10 pin 8
+    IOPORT_PORT_10_PIN_09 = 0x0A09,    ///< IO port 10 pin 9
+    IOPORT_PORT_10_PIN_10 = 0x0A0A,    ///< IO port 10 pin 10
+    IOPORT_PORT_10_PIN_11 = 0x0A0B,    ///< IO port 10 pin 11
+    IOPORT_PORT_10_PIN_12 = 0x0A0C,    ///< IO port 10 pin 12
+    IOPORT_PORT_10_PIN_13 = 0x0A0D,    ///< IO port 10 pin 13
+    IOPORT_PORT_10_PIN_14 = 0x0A0E,    ///< IO port 10 pin 14
+    IOPORT_PORT_10_PIN_15 = 0x0A0F,    ///< IO port 10 pin 15
+
+    IOPORT_PORT_11_PIN_00 = 0x0B00,    ///< IO port 11 pin 0
+    IOPORT_PORT_11_PIN_01 = 0x0B01,    ///< IO port 11 pin 1
+    IOPORT_PORT_11_PIN_02 = 0x0B02,    ///< IO port 11 pin 2
+    IOPORT_PORT_11_PIN_03 = 0x0B03,    ///< IO port 11 pin 3
+    IOPORT_PORT_11_PIN_04 = 0x0B04,    ///< IO port 11 pin 4
+    IOPORT_PORT_11_PIN_05 = 0x0B05,    ///< IO port 11 pin 5
+    IOPORT_PORT_11_PIN_06 = 0x0B06,    ///< IO port 11 pin 6
+    IOPORT_PORT_11_PIN_07 = 0x0B07,    ///< IO port 11 pin 7
+    IOPORT_PORT_11_PIN_08 = 0x0B08,    ///< IO port 11 pin 8
+    IOPORT_PORT_11_PIN_09 = 0x0B09,    ///< IO port 11 pin 9
+    IOPORT_PORT_11_PIN_10 = 0x0B0A,    ///< IO port 11 pin 10
+    IOPORT_PORT_11_PIN_11 = 0x0B0B,    ///< IO port 11 pin 11
+    IOPORT_PORT_11_PIN_12 = 0x0B0C,    ///< IO port 11 pin 12
+    IOPORT_PORT_11_PIN_13 = 0x0B0D,    ///< IO port 11 pin 13
+    IOPORT_PORT_11_PIN_14 = 0x0B0E,    ///< IO port 11 pin 14
+    IOPORT_PORT_11_PIN_15 = 0x0B0F,    ///< IO port 11 pin 15
+} ioport_port_pin_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ioport_api_t g_ioport_on_ioport;
+
+/** @endcond */
+
+/***********************************************************************************************************************
+ * Public APIs
+ **********************************************************************************************************************/
+
+fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
+fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
+fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
+fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
+fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
+fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
+fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
+fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
+                                    bsp_io_port_t         port,
+                                    ioport_size_t         direction_values,
+                                    ioport_size_t         mask);
+fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
+fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
+                                        bsp_io_port_t         port,
+                                        ioport_size_t         event_data,
+                                        ioport_size_t         mask_value);
+fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
+fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
+fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const     p_ctrl,
+                                   ioport_ethernet_channel_t channel,
+                                   ioport_ethernet_mode_t    mode);
+fsp_err_t R_IOPORT_VersionGet(fsp_version_t * p_data);
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup IOPORT)
+ **********************************************************************************************************************/
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // R_IOPORT_H
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h
new file mode 100644
index 0000000000..97652a2b43
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/inc/instances/rm_ble_abs.h
@@ -0,0 +1,258 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BLE_ABS BLE_ABS
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef RM_BLE_ABS_H
+#define RM_BLE_ABS_H
+
+#include "bsp_api.h"
+
+#include "rm_ble_abs_cfg.h"
+#include "rm_ble_abs_api.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BLE_ABS_CODE_VERSION_MAJOR                    (1U)
+#define BLE_ABS_CODE_VERSION_MINOR                    (0U)
+
+#define BLE_ABS_EVENT_NOTIFY_CONNECTION_START_POS     (0)
+#define BLE_ABS_EVENT_NOTIFY_ADVERTISING_POS          (1)
+#define BLE_ABS_EVENT_NOTIFY_SCANNING_POS             (2)
+#define BLE_ABS_EVENT_NOTIFY_INITIATING_START_POS     (3)
+#define BLE_ABS_EVENT_NOTIFY_CONNECTION_CLOSE_POS     (4)
+#define BLE_ABS_EVENT_NOTIFY_ADVERTISING_CLOSE_POS    (5)
+#define BLE_ABS_EVENT_NOTIFY_SCANNING_CLOSE_POS       (6)
+#define BLE_ABS_EVENT_NOTIFY_INITIATING_CLOSE_POS     (7)
+#define BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_START_POS     (8)
+#define BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP_POS    (9)
+
+#define BLE_EVENT_NOTIFY_ENABLE_VAL                   (                                                       \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_CONNECTION_START_POS) |   \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_CONNECTION_CLOSE_POS) |   \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_ADVERTISING_POS) |       \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_ADVERTISING_CLOSE_POS) | \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_SCANNING_POS) |             \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_SCANNING_CLOSE_POS) |       \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_INITIATING_START_POS) |   \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_CLOSE & 0x1U) << BLE_ABS_EVENT_NOTIFY_INITIATING_CLOSE_POS) |   \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_START & 0x1U) << BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_START_POS) |   \
+        ((BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP & 0x1U) << BLE_ABS_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP_POS) | \
+        (0x0))
+
+/** The timer type. */
+typedef enum
+{
+    BLE_TIMER_ONE_SHOT,                /**< One shot timer type  */
+    BLE_TIMER_PERIODIC                 /**< Periodic timer type */
+} e_ble_timer_type_t;
+
+/** The timer callback invoked when the timer expired. */
+typedef void (* ble_abs_timer_cb_t)(uint32_t timer_hdl);
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** advertising set parameters structure */
+typedef struct st_abs_advertising_parameter
+{
+    union
+    {
+        ble_abs_legacy_advertising_parameter_t          legacy_advertising_parameter;          ///< Legacy advertising parameters.
+        ble_abs_extend_advertising_parameter_t          extend_advertising_parameter;          ///< Extended advertising parameters.
+        ble_abs_non_connectable_advertising_parameter_t non_connectable_advertising_parameter; ///< Non-Connectable advertising parameters.
+        ble_abs_periodic_advertising_parameter_t        periodic_advertising_parameter;        ///< Periodic advertising parameters.
+    } advertising_parameter;                                                                   ///< Advertising parameters.
+
+    uint32_t advertising_status;                                                               ///< Advertising status.
+
+    ble_device_address_t remote_device_address;                                                ///< Remote device address for direct advertising.
+} abs_advertising_parameter_t;
+
+/** scan parameters structure */
+typedef struct st_abs_scan_parameter
+{
+    ble_abs_scan_parameter_t     scan_parameter;           ///< Scan parameters.
+    ble_abs_scan_phy_parameter_t scan_phy_parameter_1M;    ///< 1M phy parameters for scan.
+    ble_abs_scan_phy_parameter_t scan_phy_parameter_coded; ///< Coded phy parameters for scan. */
+    uint32_t scan_status;                                  /* Scan status. */
+} abs_scan_parameter_t;
+
+typedef enum
+{
+    BLE_TIMER_STATUS_FREE,
+    BLE_TIMER_STATUS_IDLE,
+    BLE_TIMER_STATUS_STARTED,
+    BLE_TIMER_STATUS_EXPIRED,
+} ble_abs_timer_status_t;
+
+typedef struct st_ble_abs_timer
+{
+    uint8_t            status;
+    uint32_t           timer_hdl;
+    uint32_t           timeout_ms;
+    uint32_t           remaining_time_ms;
+    uint8_t            type;
+    ble_abs_timer_cb_t cb;
+} ble_abs_timer_t;
+
+/** BLE ABS private control block. DO NOT MODIFY. Initialization occurs when RM_BLE_ABS_Open() is called. */
+typedef struct st_ble_abs_instance_ctrl
+{
+    uint32_t     open;                                                              ///< Indicates whether the open() API has been successfully called.
+    void const * p_context;                                                         ///< Placeholder for user data.  Passed to the user callback in ble_abs_callback_args_t.
+    ble_gap_application_callback_t             abs_gap_callback;                    ///< GAP callback function
+    ble_vendor_specific_application_callback_t abs_vendor_specific_callback;        ///< Vendor specific callback function
+    uint32_t connection_timer_handle;                                               ///< Cancel a request for connection timer.
+    uint32_t advertising_timer_handle;                                              ///< Advertising timer for legacy advertising
+    abs_advertising_parameter_t advertising_sets[BLE_MAX_NO_OF_ADV_SETS_SUPPORTED]; ///< Advertising set information.
+    abs_scan_parameter_t        abs_scan;                                           ///< Scan information.
+    st_ble_dev_addr_t           loc_bd_addr;                                        ///< Local device address.
+    uint8_t         privacy_mode;                                                   ///< Privacy mode.
+    uint32_t        set_privacy_status;                                             ///< Local privacy status.
+    ble_abs_timer_t timer[BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT];
+
+    uint32_t current_timeout_ms;                                                    ///< Current timeout.
+    uint32_t elapsed_timeout_ms;                                                    ///< Elapsed timeout.
+
+    ble_abs_cfg_t const * p_cfg;                                                    ///< Pointer to the BLE ABS configuration block.
+} ble_abs_instance_ctrl_t;
+
+/******************************************************************************************************************//**
+ * @typedef ble_mcu_clock_change_cb_t
+ * @brief   ble_mcu_clock_change_cb_t is the callback function type to use CLKOUT_RF as the MCU main clock source.
+ * @param none
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_mcu_clock_change_cb_t)(void);
+
+/******************************************************************************************************************//**
+ * @typedef ble_rf_notify_cb_t
+ * @brief   ble_rf_notify_cb_t is the RF event notify callback function type.
+ * @param[in] uint32_t     The infomation of RF event notification.
+ * @return none
+ **********************************************************************************************************************/
+typedef void (* ble_rf_notify_cb_t)(uint32_t);
+
+/******************************************************************************************************************//**
+ *  @struct st_ble_rf_notify_t
+ *  @brief  This structure is RF event notify management.
+ **********************************************************************************************************************/
+typedef struct
+{
+    /**
+     *  @brief Set enable/disable of each RF event notification
+     *  @details
+     *      Bit0  Notify Connection event start(0:Disable/1:Enable)\n
+     *      Bit1  Notify Advertising event start(0:Disable/1:Enable)\n
+     *      Bit2  Notify Scanning event start(0:Disable/1:Enable)\n
+     *      Bit3  Notify Initiating event start(0:Disable/1:Enable)\n
+     *      Bit4  Notify Connection event close(0:Disable/1:Enable)\n
+     *      Bit5  Notify Advertising event close(0:Disable/1:Enable)\n
+     *      Bit6  Notify Scanning event close(0:Disable/1:Enable)\n
+     *      Bit7  Notify Initiating event close(0:Disable/1:Enable)\n
+     *      Bit8  Notify RF_DEEP_SLEEP event start(0:Disable/1:Enable)\n
+     *      Bit9  Notify RF_DEEP_SLEEP event close(0:Disable/1:Enable)\n
+     *      Other Bit: Reserved for future use.\n
+     */
+    uint32_t enable;
+
+    /**
+     *  @brief Set callback function pointer for RF event start
+     */
+    ble_rf_notify_cb_t start_cb;
+
+    /**
+     *  @brief Set callback function pointer for RF event close
+     */
+    ble_rf_notify_cb_t close_cb;
+
+    /**
+     *  @brief Set callback function pointer for RF_DEEP_SLEEP
+     */
+    ble_rf_notify_cb_t dsleep_cb;
+} st_ble_rf_notify_t;
+
+/* prototype */
+void r_ble_rf_notify_event_start(uint32_t param);
+void r_ble_rf_notify_event_close(uint32_t param);
+void r_ble_rf_notify_deep_sleep(uint32_t param);
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure for this Instance. */
+extern const ble_abs_api_t g_ble_abs_on_ble;
+
+/** @endcond */
+
+/**********************************************************************************************************************
+ * Public Function Prototypes
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Open(ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg);
+
+fsp_err_t RM_BLE_ABS_Close(ble_abs_ctrl_t * const p_ctrl);
+
+fsp_err_t RM_BLE_ABS_Reset(ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback);
+
+fsp_err_t RM_BLE_ABS_VersionGet(fsp_version_t * const p_version);
+
+fsp_err_t RM_BLE_ABS_StartLegacyAdvertising(ble_abs_ctrl_t * const                               p_ctrl,
+                                            ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter);
+
+fsp_err_t RM_BLE_ABS_StartExtendedAdvertising(ble_abs_ctrl_t * const                               p_ctrl,
+                                              ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter);
+
+fsp_err_t RM_BLE_ABS_StartNonConnectableAdvertising(
+    ble_abs_ctrl_t * const                                        p_ctrl,
+    ble_abs_non_connectable_advertising_parameter_t const * const p_advertising_parameter);
+
+fsp_err_t RM_BLE_ABS_StartPeriodicAdvertising(ble_abs_ctrl_t * const                                 p_ctrl,
+                                              ble_abs_periodic_advertising_parameter_t const * const p_advertising_parameter);
+
+fsp_err_t RM_BLE_ABS_StartScanning(ble_abs_ctrl_t * const                 p_ctrl,
+                                   ble_abs_scan_parameter_t const * const p_scan_parameter);
+
+fsp_err_t RM_BLE_ABS_CreateConnection(ble_abs_ctrl_t * const                       p_ctrl,
+                                      ble_abs_connection_parameter_t const * const p_connection_parameter);
+
+fsp_err_t RM_BLE_ABS_SetLocalPrivacy(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk,
+                                     uint8_t privacy_mode);
+
+fsp_err_t RM_BLE_ABS_StartAuthentication(ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle);
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif                                 // RM_BLE_ABS_H
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup BLE_ABS)
+ **********************************************************************************************************************/
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all_freertos/libr_ble.a b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all_freertos/libr_ble.a
new file mode 100644
index 0000000000..a1dedf4e29
Binary files /dev/null and b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/lib/r_ble/cm4_gcc/all_freertos/libr_ble.a differ
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
new file mode 100644
index 0000000000..72b1b2c6a8
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
@@ -0,0 +1,26568 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/* Ensure Renesas MCU variation definitions are included to ensure MCU
+ * specific register variations are handled correctly. */
+#ifndef BSP_FEATURE_H
+ #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
+#endif
+
+/** @addtogroup Renesas
+ * @{
+ */
+
+/** @addtogroup RA
+ * @{
+ */
+
+#ifndef RA_H
+ #define RA_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+ #include "cmsis_compiler.h"
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+ #if   __ARM_ARCH_7EM__
+  #define RENESAS_CORTEX_M4
+ #elif __ARM_ARCH_6M__
+  #define RENESAS_CORTEX_M0PLUS
+ #elif __ARM_ARCH_8M_BASE__
+  #define RENESAS_CORTEX_M23
+ #elif __ARM_ARCH_8M_MAIN__
+  #define RENESAS_CORTEX_M33
+ #else
+  #warning Unsupported Architecture
+ #endif
+
+/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
+ #ifdef RENESAS_CORTEX_M4
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
+  #include "core_cm4.h"                /*!< Cortex-M4 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M0PLUS)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm0plus.h"            /*!< Cortex-M0 processor and core peripherals                              */
+ #elif defined(RENESAS_CORTEX_M23)
+  #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
+  #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
+  #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
+  #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
+  #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
+  #include "core_cm23.h"               /*!< Cortex-M23 processor and core peripherals                             */
+ #endif
+
+ #include "system.h"                   /*!< System                                                                */
+
+ #ifndef __IM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __IM     __I
+ #endif
+ #ifndef __OM                          /*!< Fallback for older CMSIS versions                                         */
+  #define __OM     __O
+ #endif
+ #ifndef __IOM                         /*!< Fallback for older CMSIS versions                                         */
+  #define __IOM    __IO
+ #endif
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+ #if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+ #elif defined(__ICCARM__)
+  #pragma language=extended
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+  #pragma clang diagnostic ignored "-Wnested-anon-types"
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning 586
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #else
+  #warning Not supported compiler type
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                              Device Specific Cluster Section                              ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+/**
+ * @brief R_BUS_CSa [CSa] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
+
+        struct
+        {
+            __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
+            uint16_t             : 2;
+            __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
+            uint16_t             : 4;
+            __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
+            __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
+            uint16_t             : 5;
+            __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
+        } MOD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
+
+        struct
+        {
+            __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
+                                          *   is valid only when the PWENB bit in CSnMOD is set to 1.                   */
+            uint32_t                : 5;
+            __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
+                                          *   is valid only when the PRENB bit in CSnMOD is set to 1.                   */
+            uint32_t               : 5;
+            __IOM uint32_t CSWWAIT : 5;  /*!< [20..16] Normal Write Cycle Wait Select                                   */
+            uint32_t               : 3;
+            __IOM uint32_t CSRWAIT : 5;  /*!< [28..24] Normal Read Cycle Wait Select                                    */
+            uint32_t               : 3;
+        } WCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
+
+        struct
+        {
+            __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
+            uint32_t              : 1;
+            __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
+            uint32_t              : 1;
+            __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
+            uint32_t              : 1;
+            __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
+            uint32_t              : 2;
+            __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
+            uint32_t              : 1;
+            __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
+            uint32_t              : 1;
+            __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
+            uint32_t              : 1;
+        } WCR2_b;
+    };
+    __IM uint32_t RESERVED1;
+} R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_CSb [CSb] (CS Registers)
+ */
+typedef struct
+{
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
+
+        struct
+        {
+            __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
+            uint16_t             : 3;
+            __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
+            uint16_t             : 2;
+            __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
+            uint16_t             : 3;
+            __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
+            uint16_t             : 3;
+        } CR_b;
+    };
+    __IM uint16_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
+
+        struct
+        {
+            __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
+            uint16_t            : 4;
+            __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
+            uint16_t            : 4;
+        } REC_b;
+    };
+    __IM uint16_t RESERVED2[2];
+} R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
+            uint8_t             : 3;
+            __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
+            uint8_t             : 2;
+        } SDCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
+            uint8_t             : 7;
+        } SDCMOD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
+
+        struct
+        {
+            __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
+            uint8_t          : 7;
+        } SDAMOD_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint32_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
+            uint8_t            : 7;
+        } SDSELF_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
+
+        struct
+        {
+            __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
+            __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
+                                        *   Setting. ( REFW+1 Cycles )                                                */
+        } SDRFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
+            uint8_t            : 7;
+        } SDRFEN_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
+
+        struct
+        {
+            __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
+            uint8_t             : 7;
+        } SDICR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
+
+        struct
+        {
+            __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
+            __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
+            __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
+                                        *   )                                                                         */
+            uint16_t : 5;
+        } SDIR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[6];
+
+    union
+    {
+        __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
+
+        struct
+        {
+            __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
+            uint8_t           : 6;
+        } SDADR_b;
+    };
+    __IM uint8_t  RESERVED10;
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
+            uint32_t           : 5;
+            __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
+            __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
+            __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
+            uint32_t           : 2;
+            __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
+            uint32_t           : 13;
+        } SDTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
+
+        struct
+        {
+            __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
+                                        *   set command is issued.                                                    */
+            uint16_t : 1;
+        } SDMOD_b;
+    };
+    __IM uint16_t RESERVED12;
+    __IM uint32_t RESERVED13;
+
+    union
+    {
+        __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
+
+        struct
+        {
+            __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
+            uint8_t            : 2;
+            __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
+            __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
+            uint8_t            : 3;
+        } SDSR_b;
+    };
+    __IM uint8_t  RESERVED14;
+    __IM uint16_t RESERVED15;
+} R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
+
+/**
+ * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
+
+        struct
+        {
+            __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
+                                        *   an error address.                                                         */
+        } ADD_b;
+    };
+
+    union
+    {
+        __IM uint8_t STAT;             /*!< (@ 0x00000004) Bus Error Status Register                                  */
+
+        struct
+        {
+            __IM uint8_t ACCSTAT : 1;  /*!< [0..0] Error access statusThe status at the time of the error             */
+            uint8_t              : 6;
+            __IM uint8_t ERRSTAT : 1;  /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs.          */
+        } STAT_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[2];
+} R_BUS_BUSERR_Type;                   /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
+
+        struct
+        {
+            uint16_t             : 15;
+            __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups              */
+            uint16_t              : 10;
+        } CNT_b;
+    };
+    __IM uint16_t RESERVED;
+} R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_CAN0_MB [MB] (Mailbox)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t ID;             /*!< (@ 0x00000000) Mailbox ID Register                                        */
+
+        struct
+        {
+            __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
+            __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
+            uint32_t           : 1;
+            __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
+            __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
+        } ID_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DL;             /*!< (@ 0x00000004) Mailbox DLC Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DLC : 4;    /*!< [3..0] Data Length Code                                                   */
+            uint16_t           : 12;
+        } DL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t D[8];            /*!< (@ 0x00000006) Mailbox Data Register                                      */
+
+        struct
+        {
+            __IOM uint8_t DATA : 8;    /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN
+                                        *   message data. Transmission or reception starts from DATA0.
+                                        *   The bit order on the CAN bus is MSB-first, and transmission
+                                        *   or reception starts from bit 7                                            */
+        } D_b[8];
+    };
+
+    union
+    {
+        __IOM uint16_t TS;             /*!< (@ 0x0000000E) Mailbox Timestamp Register                                 */
+
+        struct
+        {
+            __IOM uint16_t TSL : 8;    /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter
+                                        *   value of the time stamp when received messages are stored
+                                        *   in the mailbox.                                                           */
+            __IOM uint16_t TSH : 8;    /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter
+                                        *   value of the time stamp when received messages are stored
+                                        *   in the mailbox.                                                           */
+        } TS_b;
+    };
+} R_CAN0_MB_Type;                      /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
+
+        struct
+        {
+            __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
+            uint8_t          : 5;
+            __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
+            __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
+        } BY_b;
+    };
+    __IM uint8_t RESERVED;
+} R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
+
+        struct
+        {
+            __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
+            uint16_t           : 7;
+        } HA_b;
+    };
+    __IM uint16_t RESERVED;
+} R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t STTRU;            /*!< (@ 0x00000000) Timer Start Time Setting Register                          */
+
+        struct
+        {
+            __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                          *   bits of the start time of the pulse output timer in nanoseconds.          */
+        } STTRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STTRL;            /*!< (@ 0x00000004) Timer Start Time Setting Register                          */
+
+        struct
+        {
+            __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                          *   of the start time of the pulse output timer in nanoseconds.               */
+        } STTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CYCR;            /*!< (@ 0x00000008) Timer Cycle Setting Registers                              */
+
+        struct
+        {
+            __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in
+                                         *   nanoseconds. Set a value that is equivalent to at least
+                                         *   four cycles of the STCA clock.                                            */
+            uint32_t : 2;
+        } CYCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLSR;            /*!< (@ 0x0000000C) Timer Pulse Width Setting Register                         */
+
+        struct
+        {
+            __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse
+                                         *   signal from the timer in nanoseconds. Set a value that
+                                         *   is equivalent to at least two cycles of the STCA clock.                   */
+            uint32_t : 3;
+        } PLSR_b;
+    };
+} R_ETHERC_EPTPC_COMMON_TM_Type;        /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t MACRU;            /*!< (@ 0x00000000) Channel Local MAC Address Register                         */
+
+        struct
+        {
+            __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
+                                          *   bits of the local MAC address for Ethernet port 0.                        */
+            uint32_t : 8;
+        } MACRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MACRL;            /*!< (@ 0x00000004) Channel Local MAC Address Register                         */
+
+        struct
+        {
+            __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
+                                          *   bits of the local MAC address for Ethernet port 0.                        */
+            uint32_t : 8;
+        } MACRL_b;
+    };
+} R_ETHERC_EPTPC_COMMON_PR_Type;         /*!< Size = 8 (0x8)                                                            */
+
+/**
+ * @brief R_GLCDC_BG [BG] (Background Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t EN;             /*!< (@ 0x00000000) Background Plane Setting Operation Control Register        */
+
+        struct
+        {
+            __IOM uint32_t EN  : 1;    /*!< [0..0] Background plane generation module operation enable                */
+            uint32_t           : 7;
+            __IOM uint32_t VEN : 1;    /*!< [8..8] Control of LCDC internal register value reflection to
+                                        *   internal operations                                                       */
+            uint32_t             : 7;
+            __IOM uint32_t SWRST : 1;  /*!< [16..16] Entire module SW reset control                                   */
+            uint32_t             : 15;
+        } EN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERI;           /*!< (@ 0x00000004) Background Plane Setting Free-Running Period
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t FH : 11;    /*!< [10..0] Background plane horizontal synchronization signal period
+                                        *   on the basis of pixel clock (PXCLK).                                      */
+            uint32_t          : 5;
+            __IOM uint32_t FV : 11;    /*!< [26..16] Background plane vertical synchronization signal period
+                                        *   on the basis of line.                                                     */
+            uint32_t : 5;
+        } PERI_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNC;           /*!< (@ 0x00000008) Background Plane Setting Synchronization Position
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t HP : 4;     /*!< [3..0] Background plane horizontal synchronization signal assertion
+                                        *   position on the basis of pixel clock (PXCLK).                             */
+            uint32_t          : 12;
+            __IOM uint32_t VP : 4;     /*!< [19..16] Background plane vertical synchronization signal assertion
+                                        *   position on the basis of line.                                            */
+            uint32_t : 12;
+        } SYNC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VSIZE;          /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical
+                                        *                  Size Register                                              */
+
+        struct
+        {
+            __IOM uint32_t VW : 11;    /*!< [10..0] Background plane vertical valid pixel width on the basis
+                                        *   of line                                                                   */
+            uint32_t          : 5;
+            __IOM uint32_t VP : 11;    /*!< [26..16] Background plane vertical valid pixel start position
+                                        *   on the basis of line                                                      */
+            uint32_t : 5;
+        } VSIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HSIZE;          /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal
+                                        *                  Size Register                                              */
+
+        struct
+        {
+            __IOM uint32_t HW : 11;    /*!< [10..0] Background plane horizontall valid pixel width on the
+                                        *   basis of pixel clock (PXCLK) Note: When serial RGB is selected
+                                        *   as the output format for the output control block, add
+                                        *   two to the horizontal enable signal width and set the resulting
+                                        *   value to this field.                                                      */
+            uint32_t          : 5;
+            __IOM uint32_t HP : 11;    /*!< [26..16] Background plane horizontal valid pixel start position
+                                        *   on the basis of pixel clock (PXCLK).                                      */
+            uint32_t : 5;
+        } HSIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BGC;            /*!< (@ 0x00000014) Background Plane Setting Background Color Register         */
+
+        struct
+        {
+            __IOM uint32_t B : 8;      /*!< [7..0] B value for background plane valid pixel area Unsigned;
+                                        *   8-bit integer                                                             */
+            __IOM uint32_t G : 8;      /*!< [15..8] G value for background plane valid pixel area Unsigned;
+                                        *   8-bit integer                                                             */
+            __IOM uint32_t R : 8;      /*!< [23..16] R value for background plane valid pixel area. Unsigned;
+                                        *   8-bit integer.                                                            */
+            uint32_t : 8;
+        } BGC_b;
+    };
+
+    union
+    {
+        __IM uint32_t MON;             /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register           */
+
+        struct
+        {
+            __IM uint32_t EN  : 1;     /*!< [0..0] Background plane generation module operation state monitor.        */
+            uint32_t          : 7;
+            __IM uint32_t VEN : 1;     /*!< [8..8] Entire module internal operation reflection control signal
+                                        *   monitor. The signal state for controlling reflection of
+                                        *   the register values to the internal operations upon assertion
+                                        *   of the vertical synchronization signal.                                   */
+            uint32_t            : 7;
+            __IM uint32_t SWRST : 1;   /*!< [16..16] Entire module SW reset state monitor.                            */
+            uint32_t            : 15;
+        } MON_b;
+    };
+} R_GLCDC_BG_Type;                     /*!< Size = 28 (0x1c)                                                          */
+
+/**
+ * @brief R_GLCDC_GR [GR] (Layer Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t VEN;            /*!< (@ 0x00000000) Graphics Register Update Control Register                  */
+
+        struct
+        {
+            __IOM uint32_t PVEN : 1;   /*!< [0..0] Control of graphics n module register value reflection
+                                        *   to internal operations. Reflection of the register values
+                                        *   to the internal operation at the assertion of the vertical
+                                        *   synchronization signal (VS).                                              */
+            uint32_t : 31;
+        } VEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FLMRD;          /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register                */
+
+        struct
+        {
+            __IOM uint32_t RENB : 1;   /*!< [0..0] Graphics data (frame buffer data) read enable.                     */
+            uint32_t            : 31;
+        } FLMRD_b;
+    };
+
+    union
+    {
+        __IM uint32_t FLM1;            /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1                   */
+
+        struct
+        {
+            __IM uint32_t BSTMD : 2;   /*!< [1..0] Burst transfer control for graphics data (frame buffer
+                                        *   data) access                                                              */
+            uint32_t : 30;
+        } FLM1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FLM2;           /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2                   */
+
+        struct
+        {
+            __IOM uint32_t BASE : 32;  /*!< [31..0] Base address for accessing graphics data (frame buffer
+                                        *   data) Set the head address in the frame buffer where graphics
+                                        *   data is to be stored. GRn_FLM2.BASE[5:0] should be fixed
+                                        *   to 0 during 64-byte burst transfer.                                       */
+        } FLM2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FLM3;           /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3                   */
+
+        struct
+        {
+            uint32_t             : 16;
+            __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data
+                                        *   (frame buffer data) Signed; 16-bit integer                                */
+        } FLM3_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t FLM5;             /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5                   */
+
+        struct
+        {
+            __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing
+                                          *   graphics data (frame buffer data), where one transfer is
+                                          *   defined as 16-beat burst access (64-byte boundary)                        */
+            __IOM uint32_t LNNUM : 11;   /*!< [26..16] Number of lines per frame for accessing graphics data
+                                          *   (frame buffer data).                                                      */
+            uint32_t : 5;
+        } FLM5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FLM6;           /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6                   */
+
+        struct
+        {
+            uint32_t              : 28;
+            __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer
+                                        *   data).                                                                    */
+            uint32_t : 1;
+        } FLM6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB1;               /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1                 */
+
+        struct
+        {
+            __IOM uint32_t DISPSEL   : 2; /*!< [1..0] Graphics display plane control.                                    */
+            uint32_t                 : 2;
+            __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control.                        */
+            uint32_t                 : 3;
+            __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area
+                                           *   alpha blending.                                                           */
+            uint32_t             : 3;
+            __IOM uint32_t ARCON : 1;     /*!< [12..12] Rectangular area alpha blending control.                         */
+            uint32_t             : 19;
+        } AB1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB2;            /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2                 */
+
+        struct
+        {
+            __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area.                            */
+            uint32_t             : 5;
+            __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area.                  */
+            uint32_t             : 5;
+        } AB2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB3;            /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3                 */
+
+        struct
+        {
+            __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area.                          */
+            uint32_t             : 5;
+            __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area.                */
+            uint32_t             : 5;
+        } AB3_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB4;            /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4                 */
+
+        struct
+        {
+            __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image
+                                        *   area.                                                                     */
+            uint32_t             : 5;
+            __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending
+                                        *   image area                                                                */
+            uint32_t : 5;
+        } AB4_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB5;            /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5                 */
+
+        struct
+        {
+            __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending
+                                        *   image area.                                                               */
+            uint32_t             : 5;
+            __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha
+                                        *   blending image area.                                                      */
+            uint32_t : 5;
+        } AB5_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB6;             /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6                 */
+
+        struct
+        {
+            __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area.                 */
+            uint32_t               : 8;
+            __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular
+                                         *   area (-255 to 255). [8]: Sign (0: addition, 1: subtraction)
+                                         *   [7:0]: Variation (absolute value)                                         */
+            uint32_t : 7;
+        } AB6_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB7;            /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7                 */
+
+        struct
+        {
+            __IOM uint32_t CKON   : 1; /*!< [0..0] RGB-index chroma-key processing control.                           */
+            uint32_t              : 15;
+            __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular
+                                        *   area.                                                                     */
+            uint32_t : 8;
+        } AB7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB8;            /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8                 */
+
+        struct
+        {
+            __IOM uint32_t CKKR : 8;   /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned;
+                                        *   8 bits.                                                                   */
+            __IOM uint32_t CKKB : 8;   /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned;
+                                        *   8 bits.                                                                   */
+            __IOM uint32_t CKKG : 8;   /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned;
+                                        *   8 bits.                                                                   */
+            uint32_t : 8;
+        } AB8_b;
+    };
+
+    union
+    {
+        __IOM uint32_t AB9;            /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9                 */
+
+        struct
+        {
+            __IOM uint32_t CKR : 8;    /*!< [7..0] R value after RGB-index chroma-key processing replacement
+                                        *   Unsigned; 8 bits.                                                         */
+            __IOM uint32_t CKB : 8;    /*!< [15..8] B value after RGB-index chroma-key processing replacement
+                                        *   Unsigned; 8 bits.                                                         */
+            __IOM uint32_t CKG : 8;    /*!< [23..16] G value after RGB-index chroma-key processing replacement
+                                        *   Unsigned; 8 bits.                                                         */
+            __IOM uint32_t CKA : 8;    /*!< [31..24] A value after RGB-index chroma-key processing replacement.       */
+        } AB9_b;
+    };
+    __IM uint32_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint32_t BASE;           /*!< (@ 0x0000004C) Graphics Background Color Control Register                 */
+
+        struct
+        {
+            __IOM uint32_t R : 8;      /*!< [7..0] Background color R value Unsigned; 8 bits                          */
+            __IOM uint32_t B : 8;      /*!< [15..8] Background color B value Unsigned; 8 bits                         */
+            __IOM uint32_t G : 8;      /*!< [23..16] Background color G value Unsigned; 8 bits                        */
+            uint32_t         : 8;
+        } BASE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CLUTINT;        /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register             */
+
+        struct
+        {
+            __IOM uint32_t LINE : 11;  /*!< [10..0] Number of detection lines                                         */
+            uint32_t            : 5;
+            __IOM uint32_t SEL  : 1;   /*!< [16..16] CLUT table control                                               */
+            uint32_t            : 15;
+        } CLUTINT_b;
+    };
+
+    union
+    {
+        __IM uint32_t MON;             /*!< (@ 0x00000054) Graphics Status Monitor Register                           */
+
+        struct
+        {
+            __IM uint32_t ARCST   : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area              */
+            uint32_t              : 15;
+            __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow                                     */
+            uint32_t              : 15;
+        } MON_b;
+    };
+    __IM uint32_t RESERVED2[42];
+} R_GLCDC_GR_Type;                     /*!< Size = 256 (0x100)                                                        */
+
+/**
+ * @brief R_GLCDC_GAM [GAM] (Gamma Settings)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t LATCH;          /*!< (@ 0x00000000) Gamma Register Update Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t VEN : 1;    /*!< [0..0] Control of gamma correction x module register value reflection
+                                        *   to internal operations. The register values to be reflected
+                                        *   to the internal operations at the assertion of the vertical
+                                        *   synchronization signal (VS).                                              */
+            uint32_t : 31;
+        } LATCH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GAM_SW;         /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register            */
+
+        struct
+        {
+            __IOM uint32_t GAMON : 1;  /*!< [0..0] Gamma correction on/off control                                    */
+            uint32_t             : 31;
+        } GAM_SW_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LUT[8];         /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register              */
+
+        struct
+        {
+            __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point.                */
+            uint32_t             : 5;
+            __IOM uint32_t _LOW  : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point.               */
+            uint32_t             : 5;
+        } LUT_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t AREA[5];        /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer                  */
+            __IOM uint32_t _MID  : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer                */
+            __IOM uint32_t _LOW  : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer                */
+            uint32_t             : 2;
+        } AREA_b[5];
+    };
+    __IM uint32_t RESERVED;
+} R_GLCDC_GAM_Type;                    /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_GLCDC_OUT [OUT] (Output Control Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t VLATCH;         /*!< (@ 0x00000000) Output Control Block Register Update Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t VEN : 1;    /*!< [0..0] Control of output control module register value reflection
+                                        *   to internal operations. The register values to be reflected
+                                        *   to the internal operations at the assertion of the vertical
+                                        *   synchronization signal (VS).                                              */
+            uint32_t : 31;
+        } VLATCH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SET;              /*!< (@ 0x00000004) Output Control Block Output Interface Register             */
+
+        struct
+        {
+            __IOM uint32_t PHASE    : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK)                  */
+            uint32_t                : 2;
+            __IOM uint32_t DIRSEL   : 1; /*!< [4..4] Invalid data position control in serial RGB format                 */
+            uint32_t                : 3;
+            __IOM uint32_t FRQSEL   : 2; /*!< [9..8] Clock frequency division control                                   */
+            uint32_t                : 2;
+            __IOM uint32_t FORMAT   : 2; /*!< [13..12] Output format select                                             */
+            uint32_t                : 10;
+            __IOM uint32_t SWAPON   : 1; /*!< [24..24] Pixel order control                                              */
+            uint32_t                : 3;
+            __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control                                        */
+            uint32_t                : 3;
+        } SET_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BRIGHT1;        /*!< (@ 0x00000008) Output Control Block Brightness Correction Register
+                                        *                  1                                                          */
+
+        struct
+        {
+            __IOM uint32_t BRTG : 10;  /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits;
+                                        +512 with offset; integer                                                 */
+            uint32_t : 22;
+        } BRIGHT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BRIGHT2;        /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register
+                                        *                  2                                                          */
+
+        struct
+        {
+            __IOM uint32_t BRTR : 10;  /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits;
+                                        +512 with offset; integer                                                 */
+            uint32_t            : 6;
+            __IOM uint32_t BRTB : 10;  /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10
+                                        *   bits; +512 with offset; integer                                           */
+            uint32_t : 6;
+        } BRIGHT2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CONTRAST;       /*!< (@ 0x00000010) Output Control Block Contrast Correction Register          */
+
+        struct
+        {
+            __IOM uint32_t CONTR : 8;  /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits
+                                        *   fixed point                                                               */
+            __IOM uint32_t CONTB : 8;  /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits
+                                        *   fixed point                                                               */
+            __IOM uint32_t CONTG : 8;  /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8
+                                        *   bits fixed point.                                                         */
+            uint32_t : 8;
+        } CONTRAST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PDTHA;          /*!< (@ 0x00000014) Output Control Block Panel Dither Correction
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t PD : 2;     /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit
+                                        *   integer                                                                   */
+            uint32_t          : 2;
+            __IOM uint32_t PC : 2;     /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit
+                                        *   integer                                                                   */
+            uint32_t          : 2;
+            __IOM uint32_t PB : 2;     /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit
+                                        *   integer                                                                   */
+            uint32_t          : 2;
+            __IOM uint32_t PA : 2;     /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned
+                                        *   2-bit integer                                                             */
+            uint32_t            : 2;
+            __IOM uint32_t FORM : 2;   /*!< [17..16] Output format select                                             */
+            uint32_t            : 2;
+            __IOM uint32_t SEL  : 2;   /*!< [21..20] Operation mode                                                   */
+            uint32_t            : 10;
+        } PDTHA_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t CLKPHASE;       /*!< (@ 0x00000024) Output Control Block Output Phase Control Register         */
+
+        struct
+        {
+            uint32_t                 : 3;
+            __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control                                     */
+            __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control                                     */
+            __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control                                     */
+            __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control                                     */
+            uint32_t                 : 1;
+            __IOM uint32_t LCDEDGE   : 1; /*!< [8..8] LCD_DATA Output Phase Control                                      */
+            uint32_t                 : 3;
+            __IOM uint32_t FRONTGAM  : 1; /*!< [12..12] Correction control                                               */
+            uint32_t                 : 19;
+        } CLKPHASE_b;
+    };
+} R_GLCDC_OUT_Type;                       /*!< Size = 40 (0x28)                                                          */
+
+/**
+ * @brief R_GLCDC_TCON [TCON] (Timing Control Registers)
+ */
+typedef struct
+{
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t TIM;             /*!< (@ 0x00000004) TCON Reference Timing Setting Register                     */
+
+        struct
+        {
+            __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference
+                                         *   timing Sets the offset from the assertion of the internal
+                                         *   horizontal synchronization signal in terms of pixels.                     */
+            uint32_t            : 5;
+            __IOM uint32_t HALF : 11;   /*!< [26..16] Vertical synchronization signal generation change timing
+                                         *   Sets the delay from the assertion of the internal horizontal
+                                         *   synchronization signal in terms of pixels.                                */
+            uint32_t : 5;
+        } TIM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STVA1;          /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1                   */
+
+        struct
+        {
+            __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
+                                        *   width.                                                                    */
+            uint32_t          : 5;
+            __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
+            uint32_t          : 5;
+        } STVA1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STVA2;          /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2                   */
+
+        struct
+        {
+            __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
+                                        *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
+                                        *   register) pin                                                             */
+            uint32_t           : 1;
+            __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
+            uint32_t           : 27;
+        } STVA2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STVB1;          /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1                   */
+
+        struct
+        {
+            __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
+                                        *   width.                                                                    */
+            uint32_t          : 5;
+            __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
+            uint32_t          : 5;
+        } STVB1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STVB2;          /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2                   */
+
+        struct
+        {
+            __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
+                                        *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
+                                        *   register) pin                                                             */
+            uint32_t           : 1;
+            __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
+            uint32_t           : 27;
+        } STVB2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STHA1;          /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1              */
+
+        struct
+        {
+            __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
+                                        *   width.                                                                    */
+            uint32_t          : 5;
+            __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
+            uint32_t          : 5;
+        } STHA1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STHA2;          /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2              */
+
+        struct
+        {
+            __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
+                                        *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
+                                        *   register) pin.                                                            */
+            uint32_t             : 1;
+            __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
+            uint32_t             : 3;
+            __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
+            uint32_t             : 23;
+        } STHA2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STHB1;          /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1              */
+
+        struct
+        {
+            __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
+                                        *   width.                                                                    */
+            uint32_t          : 5;
+            __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
+            uint32_t          : 5;
+        } STHB1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STHB2;          /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2              */
+
+        struct
+        {
+            __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
+                                        *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
+                                        *   register) pin.                                                            */
+            uint32_t             : 1;
+            __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
+            uint32_t             : 3;
+            __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
+            uint32_t             : 23;
+        } STHB2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DE;             /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register                 */
+
+        struct
+        {
+            __IOM uint32_t INV : 1;    /*!< [0..0] DE signal polarity inversion control.                              */
+            uint32_t           : 31;
+        } DE_b;
+    };
+} R_GLCDC_TCON_Type;                   /*!< Size = 44 (0x2c)                                                          */
+
+/**
+ * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint32_t DTCTEN;            /*!< (@ 0x00000000) System control block State Detection Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t VPOSDTC   : 1; /*!< [0..0] Specified line detection control                                   */
+            __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control                             */
+            __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control                             */
+            uint32_t                 : 29;
+        } DTCTEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t INTEN;               /*!< (@ 0x00000004) System control block Interrupt Request Enable
+                                             *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t VPOSINTEN   : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control.                */
+            __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control.              */
+            __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control.              */
+            uint32_t                   : 29;
+        } INTEN_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STCLR;             /*!< (@ 0x00000008) System control block Status Clear Register                 */
+
+        struct
+        {
+            __IOM uint32_t VPOSCLR   : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field               */
+            __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field                    */
+            __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field                    */
+            uint32_t                 : 29;
+        } STCLR_b;
+    };
+
+    union
+    {
+        __IM uint32_t STMON;           /*!< (@ 0x0000000C) System control block Status Monitor Register               */
+
+        struct
+        {
+            __IM uint32_t VPOS   : 1;  /*!< [0..0] Graphics 2 specified line detection flag                           */
+            __IM uint32_t L1UNDF : 1;  /*!< [1..1] Graphics 1 underflow detection flag                                */
+            __IM uint32_t L2UNDF : 1;  /*!< [2..2] Graphics 2 underflow detection flag                                */
+            uint32_t             : 29;
+        } STMON_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PANEL_CLK;      /*!< (@ 0x00000010) System control block Version and Panel Clock
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t DCDR : 6;   /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1
+                                        *   for details about setting value. Note: Settings that are
+                                        *   not listed in table 2.7.1 are prohibited.                                 */
+            __IOM uint32_t CLKEN : 1;  /*!< [6..6] Panel clock output enable control Note: Before changing
+                                        *   the PIXSEL,CLKSEL or DCDR bit, this bit must be set to
+                                        *   0.                                                                        */
+            uint32_t              : 1;
+            __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select                                   */
+            uint32_t              : 3;
+            __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same
+                                        *   value as OUT_SET.FRQSEL[1].                                               */
+            uint32_t          : 3;
+            __IM uint32_t VER : 16;    /*!< [31..16] Version information Version information of the GLCDC             */
+        } PANEL_CLK_b;
+    };
+} R_GLCDC_SYSCNT_Type;                 /*!< Size = 20 (0x14)                                                          */
+
+/**
+ * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t A;              /*!< (@ 0x00000000) GTIOCA Output Delay Register                               */
+
+        struct
+        {
+            __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
+            uint16_t           : 11;
+        } A_b;
+    };
+
+    union
+    {
+        __IOM uint16_t B;              /*!< (@ 0x00000002) GTIOCB Output Delay Register                               */
+
+        struct
+        {
+            __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
+            uint16_t           : 11;
+        } B_b;
+    };
+} R_GPT_ODC_GTDLYR_Type;               /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
+
+        struct
+        {
+            __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
+                                        *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
+        } L_b;
+    };
+
+    union
+    {
+        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
+
+        struct
+        {
+            __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
+            __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
+            __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
+            uint8_t            : 5;
+        } U_b;
+    };
+} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t C;              /*!< (@ 0x00000000) Access Control Register                                    */
+
+        struct
+        {
+            __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
+            __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
+            __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
+            uint16_t              : 13;
+        } C_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t S;                /*!< (@ 0x00000004) Start Address Register                                     */
+
+        struct
+        {
+            __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE:
+                                          *   The low-order 2 bits are fixed to 0.                                      */
+        } S_b;
+    };
+
+    union
+    {
+        __IOM uint32_t E;                /*!< (@ 0x00000008) End Address Register                                       */
+
+        struct
+        {
+            __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region
+                                          *   end, for use in region determination.NOTE: The low-order
+                                          *   2 bits are fixed to 1.                                                    */
+        } E_b;
+    };
+    __IM uint32_t RESERVED1;
+} R_MPU_MMPU_MMPU_REGION_Type;           /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t CTL;            /*!< (@ 0x00000000) Bus Master MPU Control Register                            */
+
+        struct
+        {
+            __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable                                                */
+            __IOM uint16_t OAD    : 1; /*!< [1..1] Operation after detection                                          */
+            uint16_t              : 6;
+            __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+                                        *   stored.                                                                   */
+        } CTL_b;
+    };
+    __IM uint16_t RESERVED;
+    __IM uint32_t RESERVED1[63];
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint16_t PT;                        /*!< (@ 0x00000102) Protection of Register                                     */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1;           /*!< [0..0] Protection of region register                                      */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8;           /*!< [15..8] Write Keyword The data written to these bits are not
+                                                   *   stored.                                                                   */
+        } PT_b;
+    };
+    __IM uint32_t RESERVED3[63];
+    __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers                                   */
+} R_MPU_MMPU_MMPU_Type;                           /*!< Size = 1024 (0x400)                                                       */
+
+/**
+ * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t R;              /*!< (@ 0x00000000) Access Control Register for MBIU                           */
+
+        struct
+        {
+            uint16_t              : 2;
+            __IOM uint16_t RPGRPA : 1;   /*!< [2..2] Master Group A Read protection                                     */
+            __IOM uint16_t WPGRPA : 1;   /*!< [3..3] Master Group A Write protection                                    */
+            __IOM uint16_t RPGRPB : 1;   /*!< [4..4] Master Group B Read protection                                     */
+            __IOM uint16_t WPGRPB : 1;   /*!< [5..5] Master Group B Write protection                                    */
+            __IOM uint16_t RPGRPC : 1;   /*!< [6..6] Master Group C Read protection                                     */
+            __IOM uint16_t WPGRPC : 1;   /*!< [7..7] Master Group C Write protection                                    */
+            uint16_t              : 4;
+            __IOM uint16_t RPFLI  : 1;   /*!< [12..12] Code Flash Memory Read Protection                                */
+            __IOM uint16_t WPFLI  : 1;   /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
+                                          *   is read as 1. The write value should be 1.)                               */
+            __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection                                           */
+            __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection                                          */
+        } R_b;
+    };
+    __IM uint16_t RESERVED;
+} R_MPU_SMPU_SMPU_Type;                  /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
+            uint16_t           : 7;
+            __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
+                                        *   stored.                                                                   */
+        } OAD_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
+
+        struct
+        {
+            __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
+            uint16_t              : 7;
+            __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
+            uint16_t              : 7;
+        } CTL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
+
+        struct
+        {
+            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
+            uint16_t               : 7;
+            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
+                                         *   stored.                                                                   */
+        } PT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 0.                                      */
+        } SA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
+
+        struct
+        {
+            __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
+                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
+                                           *   The low-order 2 bits are fixed to 1.                                      */
+        } EA_b;
+    };
+} R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3])
+ */
+typedef struct
+{
+    __IOM uint8_t OS;                  /*!< (@ 0x00000000) Output Select Register                                     */
+    __IOM uint8_t MS;                  /*!< (@ 0x00000001) Minus Input Select Register                                */
+    __IOM uint8_t PS;                  /*!< (@ 0x00000002) Plus Input Select Register                                 */
+} R_OPAMP_AMP_Type;                    /*!< Size = 3 (0x3)                                                            */
+
+/**
+ * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t P;               /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register       */
+
+        struct
+        {
+            __IOM uint8_t TRMP : 5;    /*!< [4..0] AMPn input offset trimming Pch side                                */
+            uint8_t            : 3;
+        } P_b;
+    };
+
+    union
+    {
+        __IOM uint8_t N;               /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register       */
+
+        struct
+        {
+            __IOM uint8_t TRMN : 5;    /*!< [4..0] AMPn input offset trimming Nch side                                */
+            uint8_t            : 3;
+        } N_b;
+    };
+} R_OPAMP_AMPOT_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
+ */
+typedef struct
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
+
+            struct
+            {
+                __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                uint32_t             : 1;
+                __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                uint32_t             : 3;
+                __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
+                uint32_t             : 7;
+                __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
+                                           *   function. For individual pin functions, see the MPC table                 */
+                uint32_t : 3;
+            } PmnPFS_b;
+        };
+
+        struct
+        {
+            union
+            {
+                struct
+                {
+                    __IM uint16_t RESERVED;
+
+                    union
+                    {
+                        __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint16_t             : 1;
+                            __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint16_t             : 3;
+                            __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
+                            __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
+                            __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
+                            __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
+                        } PmnPFS_HA_b;
+                    };
+                };
+
+                struct
+                {
+                    __IM uint16_t RESERVED1;
+                    __IM uint8_t  RESERVED2;
+
+                    union
+                    {
+                        __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
+
+                        struct
+                        {
+                            __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
+                            __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
+                            __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
+                            uint8_t             : 1;
+                            __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
+                            __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
+                            __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
+                            uint8_t             : 1;
+                        } PmnPFS_BY_b;
+                    };
+                };
+            };
+        };
+    };
+} R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief R_PFS_PORT [PORT] (Port [0..11])
+ */
+typedef struct
+{
+    __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
+} R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
+
+/**
+ * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
+            __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
+            uint8_t            : 1;
+            __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
+            uint8_t            : 2;
+        } RTCCR_b;
+    };
+    __IM uint8_t RESERVED;
+} R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
+
+/**
+ * @brief R_RTC_CP [CP] (Capture registers)
+ */
+typedef struct
+{
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
+                                         *   seconds                                                                   */
+                __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
+                                         *   seconds                                                                   */
+                uint8_t : 1;
+            } RSEC_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
+                                           *   value when a time capture event is detected.                              */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
+
+            struct
+            {
+                __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                         *   minutes                                                                   */
+                __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
+                                         *   minutes                                                                   */
+                uint8_t : 1;
+            } RMIN_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
+                                           *   value when a time capture event is detected.                              */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
+                                        *   minutes                                                                   */
+                __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
+                                        *   minutes                                                                   */
+                __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
+                uint8_t         : 1;
+            } RHR_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
+                                           *   value when a time capture event is detected.                              */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3[3];
+
+    union
+    {
+        union
+        {
+            __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
+
+            struct
+            {
+                __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
+                __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
+                uint8_t             : 2;
+            } RDAY_b;
+        };
+
+        union
+        {
+            __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
+
+            struct
+            {
+                __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
+                                           *   value when a time capture event is detected.                              */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
+
+        struct
+        {
+            __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
+            __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
+                                        *   months                                                                    */
+            uint8_t : 3;
+        } RMON_b;
+    };
+    __IM uint8_t RESERVED5[3];
+} R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
+
+/**
+ * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+            uint16_t             : 6;
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
+
+/**
+ * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
+ */
+typedef struct
+{
+    union
+    {
+        __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
+            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
+        } E_b;
+    };
+
+    union
+    {
+        __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
+
+        struct
+        {
+            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
+        } N_b;
+    };
+} R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                           */
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ACMPHS0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief High-Speed Analog Comparator (R_ACMPHS0)
+ */
+
+typedef struct                         /*!< (@ 0x40085000) R_ACMPHS0 Structure                                        */
+{
+    union
+    {
+        __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
+            __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
+            __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
+            __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
+            __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
+            __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
+        } CMPCTL_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
+
+        struct
+        {
+            __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
+            uint8_t              : 4;
+        } CMPSEL0_b;
+    };
+    __IM uint8_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
+
+        struct
+        {
+            __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
+            uint8_t            : 2;
+        } CMPSEL1_b;
+    };
+    __IM uint8_t RESERVED2[3];
+
+    union
+    {
+        __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
+
+        struct
+        {
+            __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
+            uint8_t             : 7;
+        } CMPMON_b;
+    };
+    __IM uint8_t RESERVED3[3];
+
+    union
+    {
+        __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
+            uint8_t              : 6;
+            __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
+        } CPIOC_b;
+    };
+} R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ACMPLP                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Low-Power Analog Comparator (R_ACMPLP)
+ */
+
+typedef struct                         /*!< (@ 0x40085E00) R_ACMPLP Structure                                         */
+{
+    union
+    {
+        __IOM uint8_t COMPMDR;         /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */
+
+        struct
+        {
+            __IOM uint8_t C0ENB : 1;   /*!< [0..0] ACMPLP0 Operation Enable                                           */
+            __IOM uint8_t C0WDE : 1;   /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
+            __IOM uint8_t C0VRF : 1;   /*!< [2..2] ACMPLP0 Reference Voltage Selection                                */
+            __IM uint8_t  C0MON : 1;   /*!< [3..3] ACMPLP0 Monitor Flag                                               */
+            __IOM uint8_t C1ENB : 1;   /*!< [4..4] ACMPLP1 Operation Enable                                           */
+            __IOM uint8_t C1WDE : 1;   /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
+            __IOM uint8_t C1VRF : 1;   /*!< [6..6] ACMPLP1 Reference Voltage Selection                                */
+            __IM uint8_t  C1MON : 1;   /*!< [7..7] ACMPLP1 Monitor Flag                                               */
+        } COMPMDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t COMPFIR;         /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t C0FCK : 2;   /*!< [1..0] ACMPLP0 Filter Select                                              */
+            __IOM uint8_t C0EPO : 1;   /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
+            __IOM uint8_t C0EDG : 1;   /*!< [3..3] ACMPLP0 Edge Detection Selection                                   */
+            __IOM uint8_t C1FCK : 2;   /*!< [5..4] ACMPLP1 Filter Select                                              */
+            __IOM uint8_t C1EPO : 1;   /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
+            __IOM uint8_t C1EDG : 1;   /*!< [7..7] ACMPLP1 Edge Detection Selection                                   */
+        } COMPFIR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t COMPOCR;         /*!< (@ 0x00000002) ACMPLP Output Control Register                             */
+
+        struct
+        {
+            uint8_t             : 1;
+            __IOM uint8_t C0OE  : 1;   /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
+            __IOM uint8_t C0OP  : 1;   /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
+            uint8_t             : 2;
+            __IOM uint8_t C1OE  : 1;   /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
+            __IOM uint8_t C1OP  : 1;   /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
+            __IOM uint8_t SPDMD : 1;   /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
+        } COMPOCR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t COMPSEL0;        /*!< (@ 0x00000004) Comparator Input Select Register                           */
+
+        struct
+        {
+            __IOM uint8_t IVCMP0 : 3;  /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection                                   */
+            uint8_t              : 1;
+            __IOM uint8_t IVCMP1 : 3;  /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection                                   */
+            uint8_t              : 1;
+        } COMPSEL0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t COMPSEL1;        /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */
+
+        struct
+        {
+            __IOM uint8_t IVREF0 : 3;  /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
+            uint8_t              : 1;
+            __IOM uint8_t IVREF1 : 3;  /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
+            __IOM uint8_t C1VRF2 : 1;  /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
+        } COMPSEL1_b;
+    };
+} R_ACMPLP_Type;                       /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief A/D Converter (R_ADC0)
+ */
+
+typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
+                                        *   input channel for double triggered operation. The setting
+                                        *   is only effective while double trigger mode is selected.                  */
+            uint16_t              : 1;
+            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
+            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
+            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
+            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
+            __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
+            uint16_t              : 2;
+            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
+            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
+        } ADCSR_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSA_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
+            __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
+            __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
+        } ADADS_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
+                                        *   at the only setting of ADC[2:0] bits = 001b or 011b. When
+                                        *   average mode is selected by setting the ADADC.AVEE bit
+                                        *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
+                                        *   = 010b)                                                                   */
+            uint8_t            : 4;
+            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
+                                        *   by setting the ADADC.AVEE bit to 0, set the addition count
+                                        *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
+                                        *   can only be used with 12-bit accuracy selected. NOTE: AVEE
+                                        *   bit is valid at the only setting of ADC[2:0] bits = 001b
+                                        *   or 011b. When average mode is selected by setting the ADADC.AVEE
+                                        *   bit to 1, do not set the addition count to three times
+                                        *   (ADADC.ADC[2:0] = 010b)                                                   */
+        } ADADC_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
+
+        struct
+        {
+            uint16_t               : 1;
+            __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
+            uint16_t               : 2;
+            __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
+            uint16_t               : 2;
+            __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
+            __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
+            __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
+            uint16_t               : 2;
+            __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
+            __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
+        } ADCER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
+
+        struct
+        {
+            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
+                                        *   the A/D conversion start trigger for group B in group scan
+                                        *   mode.                                                                     */
+            uint16_t            : 2;
+            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
+                                        *   start trigger in single scan mode and continuous mode.
+                                        *   In group scan mode, the A/D conversion start trigger for
+                                        *   group A is selected.                                                      */
+            uint16_t : 2;
+        } ADSTRGR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
+
+        struct
+        {
+            __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
+                                        *   Mode Select                                                               */
+            uint16_t            : 6;
+            __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
+            __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
+            __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
+                                        *   Group B in group scan mode.                                               */
+            uint16_t : 4;
+        } ADEXICR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
+
+        struct
+        {
+            __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADANSB_b[2];
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                         *   result of A/D conversion in response to the second trigger
+                                         *   in double trigger mode.                                                   */
+        } ADDBLDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
+
+        struct
+        {
+            __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D conversion result of temperature sensor output.                       */
+        } ADTSDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
+
+        struct
+        {
+            __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
+                                        *   A/D result of internal reference voltage.                                 */
+        } ADOCDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
+
+            struct
+            {
+                __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
+                                           *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+                __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
+            } ADRD_RIGHT_b;
+        };
+
+        union
+        {
+            __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
+
+            struct
+            {
+                __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
+                __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
+                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
+            } ADRD_LEFT_b;
+        };
+    };
+
+    union
+    {
+        __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
+
+        struct
+        {
+            __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
+                                        *   storing the result of A/D conversion.                                     */
+        } ADDR_b[28];
+    };
+    __IM uint16_t RESERVED2[7];
+
+    union
+    {
+        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
+
+        struct
+        {
+            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
+                                        *   Setting Set the sampling time (4 to 255 states)                           */
+            __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
+            __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
+            uint16_t              : 5;
+        } ADSHCR_b;
+    };
+    __IM uint16_t RESERVED3[9];
+
+    union
+    {
+        __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
+
+        struct
+        {
+            __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
+            __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
+            uint8_t              : 3;
+        } ADDISCR_b;
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
+
+        struct
+        {
+            __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
+                                        *   Select                                                                    */
+            uint8_t : 7;
+        } ADSHMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
+            uint8_t            : 6;
+        } ADICR_b;
+    };
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IOM uint16_t ADGSPCR;        /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
+
+        struct
+        {
+            __IOM uint16_t PGS : 1;    /*!< [0..0] Group A priority control setting bit.Note: When the PGS
+                                        *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
+                                        *   set to 01b (group scan mode). If the bits are set to any
+                                        *   other values, proper operation is not guaranteed.                         */
+            __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
+                                        *   when PGS = 0.)                                                            */
+            uint16_t            : 13;
+            __IOM uint16_t GBRP : 1;   /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
+                                        *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
+                                        *   has been set to 1, single scan is performed continuously
+                                        *   for group B regardless of the setting of the GBRSCN bit.                  */
+        } ADGSPCR_b;
+    };
+    __IM uint16_t RESERVED6;
+
+    union
+    {
+        __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRA_b;
+    };
+
+    union
+    {
+        __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
+
+        struct
+        {
+            __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
+                                          *   the result of A/D conversion in response to the respective
+                                          *   triggers during extended operation in double trigger mode.                */
+        } ADDBLDRB_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
+            uint8_t             : 2;
+            __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
+            uint8_t             : 2;
+            __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
+        } ADHVREFCNT_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
+                                        *   result.This bit is valid when both window A operation and
+                                        *   window B operation are enabled.                                           */
+            uint8_t              : 3;
+            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
+            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
+            uint8_t              : 2;
+        } ADWINMON_b;
+    };
+    __IM uint8_t  RESERVED9;
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
+                                        *   are valid when both window A and window B are enabled (CMPAE
+                                        *   = 1 and CMPBE = 1).                                                       */
+            uint16_t              : 7;
+            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
+            uint16_t              : 1;
+            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
+            uint16_t              : 1;
+            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
+            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
+            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
+        } ADCMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
+                                        *                  Select Register                                            */
+
+        struct
+        {
+            __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
+            __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
+            uint8_t              : 6;
+        } ADCMPANSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
+                                        *                  Comparison Condition Setting Register                      */
+
+        struct
+        {
+            __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
+                                        *   Condition Select                                                          */
+            __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
+                                        *   Select                                                                    */
+            uint8_t : 6;
+        } ADCMPLER_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
+            __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
+            __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
+        } ADCMPANSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
+            __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
+            __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
+        } ADCMPLR_b[2];
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR0 sets the lower-side
+                                           *   level of window A.                                                        */
+        } ADCMPDR0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
+                                           *   compare window A function is used. ADCMPDR1 sets the upper-side
+                                           *   level of window A..                                                       */
+        } ADCMPDR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
+                                            *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
+            __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
+            __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
+        } ADCMPSR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
+                                         *                  Channel Status Register                                    */
+
+        struct
+        {
+            __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
+                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
+                                         *   this bit indicates the temperature sensor output comparison
+                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
+                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
+                                         *   time.                                                                     */
+            uint8_t : 6;
+        } ADCMPSER_b;
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
+                                        *   compares it on the condition of compare window B is selected.             */
+            uint8_t             : 1;
+            __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
+        } ADCMPBNSR_b;
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the lower level of the window B.                              */
+        } ADWINLLB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
+                                           *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
+                                           *   used to set the higher level of the window B.                             */
+        } ADWINULB_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
+
+        struct
+        {
+            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
+                                        *   the comparative result of CH (AN000-AN027, temperature
+                                        *   sensor, and internal reference voltage) made the object
+                                        *   of window B relation condition.                                           */
+            uint8_t : 7;
+        } ADCMPBSR_b;
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14[23];
+    __IM uint8_t  RESERVED15;
+
+    union
+    {
+        __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
+        } ADSSTRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
+        } ADSSTRT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
+        } ADSSTRO_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
+
+        struct
+        {
+            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
+        } ADSSTR_b[16];
+    };
+
+    union
+    {
+        __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
+
+        struct
+        {
+            __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
+            __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
+            uint16_t             : 12;
+        } ADANIM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
+            __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
+        } ADCALEXE_b;
+    };
+    __IM uint8_t RESERVED16;
+
+    union
+    {
+        __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
+                                          *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
+            __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
+            __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
+            __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
+            uint8_t                 : 2;
+            __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
+        } VREFAMPCNT_b;
+    };
+    __IM uint8_t  RESERVED17;
+    __IM uint16_t RESERVED18;
+
+    union
+    {
+        __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
+
+        struct
+        {
+            __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
+        } ADRD_b;
+    };
+
+    union
+    {
+        __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
+
+        struct
+        {
+            __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
+            uint8_t             : 6;
+        } ADRST_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20[82];
+
+    union
+    {
+        __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
+
+        struct
+        {
+            __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
+            __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
+            __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
+            __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
+            __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
+            __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
+            __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
+            __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
+            __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
+            __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
+            __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
+            __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
+            uint16_t                 : 4;
+        } ADPGACR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
+                                          *                  Register 0                                                 */
+
+        struct
+        {
+            __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
+                                          *   b) when the shingle end is input and each PGA P000 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
+            __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
+                                          *   b) when the shingle end is input and each PGA P001 is set.
+                                          *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
+                                          *   sets the gain magnification when the differential motion
+                                          *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
+            __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
+                                          *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
+                                          *   each PGA P002 is set. When the differential motion is input,
+                                          *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
+                                          *   the differential motion is input by the combination with
+                                          *   ADPGSDCR0.P002DG 1:0.                                                     */
+            uint16_t : 4;
+        } ADPGAGS0_b;
+    };
+    __IM uint16_t RESERVED21[6];
+
+    union
+    {
+        __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
+                                         *                  Input Control Register                                     */
+
+        struct
+        {
+            __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
+            __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
+            __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
+            uint16_t               : 1;
+            __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
+            __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
+                                         *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
+            uint16_t : 2;
+        } ADPGADCR0_b;
+    };
+} R_ADC0_Type;                          /*!< Size = 434 (0x1b2)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Asynchronous General Purpose Timer (R_AGT0)
+ */
+
+typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
+{
+    union
+    {
+        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
+
+        struct
+        {
+            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
+                                        *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
+                                        *   is forcibly stopped and set to FFFFH.                                     */
+        } AGT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCRn register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
+
+        struct
+        {
+            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
+                                         *   written to the TSTOP bit in the AGTCR register, set to
+                                         *   FFFFH                                                                     */
+        } AGTCMB_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
+            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
+            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
+            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
+            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
+            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
+        } AGTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
+            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
+            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
+            uint8_t              : 1;
+        } AGTMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
+                                        *   ratio                                                                     */
+            uint8_t           : 4;
+            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
+        } AGTMR2_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
+                                        *   mode.                                                                     */
+            uint8_t             : 1;
+            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
+            uint8_t             : 1;
+            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
+            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
+        } AGTIOC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
+
+        struct
+        {
+            uint8_t            : 2;
+            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
+            uint8_t            : 5;
+        } AGTISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
+
+        struct
+        {
+            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
+            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
+            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
+            uint8_t              : 1;
+            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
+            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
+            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
+            uint8_t              : 1;
+        } AGTCMSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
+            uint8_t            : 3;
+        } AGTIOSEL_b;
+    };
+} R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Interface (R_BUS)
+ */
+
+typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
+{
+    __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
+    __IM uint32_t        RESERVED[480];
+    __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
+
+    union
+    {
+        __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
+
+        struct
+        {
+            __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
+            __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
+            __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+            __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
+        } CSRECEN_b;
+    };
+    __IM uint16_t           RESERVED1;
+    __IM uint32_t           RESERVED2[223];
+    __IOM R_BUS_SDRAM_Type  SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
+    __IM uint32_t           RESERVED3[235];
+    __IOM R_BUS_BUSM_Type   BUSM[6];    /*!< (@ 0x00001000) Master Bus Control Register Array                          */
+    __IM uint32_t           RESERVED4[58];
+    __IOM R_BUS_BUSS_Type   BUSS[16];   /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
+    __IM uint32_t           RESERVED5[432];
+    __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers                                        */
+} R_BUS_Type;                           /*!< Size = 6320 (0x18b0)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
+ */
+
+typedef struct                         /*!< (@ 0x40044600) R_CAC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
+            uint8_t            : 7;
+        } CACR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
+            __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
+            __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
+            __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
+        } CACR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
+            __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
+            __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
+                                        *   Select                                                                    */
+            __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
+        } CACR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
+            __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
+            __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
+            uint8_t              : 1;
+            __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
+            __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
+            __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
+            uint8_t              : 1;
+        } CAICR_b;
+    };
+
+    union
+    {
+        __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
+            __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
+            __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
+            uint8_t            : 5;
+        } CASTR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
+                                         *   the upper-limit value of the frequency.                                   */
+        } CAULVR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
+
+        struct
+        {
+            __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
+                                         *   the lower-limit value of the frequency.                                   */
+        } CALLVR_b;
+    };
+
+    union
+    {
+        __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
+
+        struct
+        {
+            __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
+                                         *   the counter value at the time a valid reference signal
+                                         *   edge is input                                                             */
+        } CACNTBR_b;
+    };
+} R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CAN0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Controller Area Network (CAN) Module (R_CAN0)
+ */
+
+typedef struct                         /*!< (@ 0x40050000) R_CAN0 Structure                                           */
+{
+    __IM uint32_t        RESERVED[128];
+    __IOM R_CAN0_MB_Type MB[32];       /*!< (@ 0x00000200) Mailbox                                                    */
+
+    union
+    {
+        __IOM uint32_t MKR[8];         /*!< (@ 0x00000400) Mask Register                                              */
+
+        struct
+        {
+            __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
+            __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
+            uint32_t           : 3;
+        } MKR_b[8];
+    };
+
+    union
+    {
+        __IOM uint32_t FIDCR[2];       /*!< (@ 0x00000420) FIFO Received ID Compare Registers                         */
+
+        struct
+        {
+            __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
+            __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
+            uint32_t           : 1;
+            __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
+            __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
+        } FIDCR_b[2];
+    };
+
+    union
+    {
+        __IOM uint32_t MKIVLR;         /*!< (@ 0x00000428) Mask Invalid Register                                      */
+
+        struct
+        {
+            __IOM uint32_t MB0  : 1;   /*!< [0..0] mailbox 0 Mask Invalid                                             */
+            __IOM uint32_t MB1  : 1;   /*!< [1..1] mailbox 1 Mask Invalid                                             */
+            __IOM uint32_t MB2  : 1;   /*!< [2..2] mailbox 2 Mask Invalid                                             */
+            __IOM uint32_t MB3  : 1;   /*!< [3..3] mailbox 3 Mask Invalid                                             */
+            __IOM uint32_t MB4  : 1;   /*!< [4..4] mailbox 4 Mask Invalid                                             */
+            __IOM uint32_t MB5  : 1;   /*!< [5..5] mailbox 5 Mask Invalid                                             */
+            __IOM uint32_t MB6  : 1;   /*!< [6..6] mailbox 6 Mask Invalid                                             */
+            __IOM uint32_t MB7  : 1;   /*!< [7..7] mailbox 7 Mask Invalid                                             */
+            __IOM uint32_t MB8  : 1;   /*!< [8..8] mailbox 8 Mask Invalid                                             */
+            __IOM uint32_t MB9  : 1;   /*!< [9..9] mailbox 9 Mask Invalid                                             */
+            __IOM uint32_t MB10 : 1;   /*!< [10..10] mailbox 10 Mask Invalid                                          */
+            __IOM uint32_t MB11 : 1;   /*!< [11..11] mailbox 11 Mask Invalid                                          */
+            __IOM uint32_t MB12 : 1;   /*!< [12..12] mailbox 12 Mask Invalid                                          */
+            __IOM uint32_t MB13 : 1;   /*!< [13..13] mailbox 13 Mask Invalid                                          */
+            __IOM uint32_t MB14 : 1;   /*!< [14..14] mailbox 14 Mask Invalid                                          */
+            __IOM uint32_t MB15 : 1;   /*!< [15..15] mailbox 15 Mask Invalid                                          */
+            __IOM uint32_t MB16 : 1;   /*!< [16..16] mailbox 16 Mask Invalid                                          */
+            __IOM uint32_t MB17 : 1;   /*!< [17..17] mailbox 17 Mask Invalid                                          */
+            __IOM uint32_t MB18 : 1;   /*!< [18..18] mailbox 18 Mask Invalid                                          */
+            __IOM uint32_t MB19 : 1;   /*!< [19..19] mailbox 19 Mask Invalid                                          */
+            __IOM uint32_t MB20 : 1;   /*!< [20..20] mailbox 20 Mask Invalid                                          */
+            __IOM uint32_t MB21 : 1;   /*!< [21..21] mailbox 21 Mask Invalid                                          */
+            __IOM uint32_t MB22 : 1;   /*!< [22..22] mailbox 22 Mask Invalid                                          */
+            __IOM uint32_t MB23 : 1;   /*!< [23..23] mailbox 23 Mask Invalid                                          */
+            __IOM uint32_t MB24 : 1;   /*!< [24..24] mailbox 24 Mask Invalid                                          */
+            __IOM uint32_t MB25 : 1;   /*!< [25..25] mailbox 25 Mask Invalid                                          */
+            __IOM uint32_t MB26 : 1;   /*!< [26..26] mailbox 26 Mask Invalid                                          */
+            __IOM uint32_t MB27 : 1;   /*!< [27..27] mailbox 27 Mask Invalid                                          */
+            __IOM uint32_t MB28 : 1;   /*!< [28..28] mailbox 28 Mask Invalid                                          */
+            __IOM uint32_t MB29 : 1;   /*!< [29..29] mailbox 29 Mask Invalid                                          */
+            __IOM uint32_t MB30 : 1;   /*!< [30..30] mailbox 30 Mask Invalid                                          */
+            __IOM uint32_t MB31 : 1;   /*!< [31..31] mailbox 31 Mask Invalid                                          */
+        } MKIVLR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t MIER;         /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register                          */
+
+            struct
+            {
+                __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
+                __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
+                __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
+                __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
+                __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
+                __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
+                __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
+                __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
+                __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
+                __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
+                __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
+                __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
+                __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
+                __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
+                __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
+                __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
+                __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
+                __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
+                __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
+                __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
+                __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
+                __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
+                __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
+                __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
+                __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable                                      */
+                __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable                                      */
+                __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable                                      */
+                __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable                                      */
+                __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable                                      */
+                __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable                                      */
+                __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable                                      */
+                __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable                                      */
+            } MIER_b;
+        };
+
+        union
+        {
+            __IOM uint32_t MIER_FIFO;    /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox
+                                          *                  Mode                                                       */
+
+            struct
+            {
+                __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
+                __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
+                __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
+                __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
+                __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
+                __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
+                __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
+                __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
+                __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
+                __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
+                __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
+                __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
+                __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
+                __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
+                __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
+                __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
+                __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
+                __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
+                __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
+                __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
+                __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
+                __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
+                __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
+                __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
+                __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable                                   */
+                __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control                */
+                uint32_t            : 2;
+                __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable                                    */
+                __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control                 */
+                uint32_t            : 2;
+            } MIER_FIFO_b;
+        };
+    };
+    __IM uint32_t RESERVED1[252];
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t MCTL_TX[32];       /*!< (@ 0x00000820) Message Control Register for Transmit                      */
+
+            struct
+            {
+                __IOM uint8_t SENTDATA  : 1; /*!< [0..0] Transmission Complete Flag                                         */
+                __IM uint8_t  TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox
+                                              *   setting enabled)                                                          */
+                __IOM uint8_t TRMABT : 1;    /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting
+                                              *   enabled)                                                                  */
+                uint8_t               : 1;
+                __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
+                uint8_t               : 1;
+                __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
+                __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
+            } MCTL_TX_b[32];
+        };
+
+        union
+        {
+            __IOM uint8_t MCTL_RX[32];       /*!< (@ 0x00000820) Message Control Register for Receive                       */
+
+            struct
+            {
+                __IOM uint8_t NEWDATA   : 1; /*!< [0..0] Reception Complete Flag                                            */
+                __IM uint8_t  INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting
+                                              *   enabled)                                                                  */
+                __IOM uint8_t MSGLOST : 1;   /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled)                 */
+                uint8_t               : 1;
+                __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
+                uint8_t               : 1;
+                __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
+                __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
+            } MCTL_RX_b[32];
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CTLR;           /*!< (@ 0x00000840) Control Register                                           */
+
+        struct
+        {
+            __IOM uint16_t MBM  : 1;   /*!< [0..0] CAN Mailbox Mode Select                                            */
+            __IOM uint16_t IDFM : 2;   /*!< [2..1] ID Format Mode Select                                              */
+            __IOM uint16_t MLM  : 1;   /*!< [3..3] Message Lost Mode Select                                           */
+            __IOM uint16_t TPM  : 1;   /*!< [4..4] Transmission Priority Mode Select                                  */
+            __IOM uint16_t TSRC : 1;   /*!< [5..5] Time Stamp Counter Reset Command                                   */
+            __IOM uint16_t TSPS : 2;   /*!< [7..6] Time Stamp Prescaler Select                                        */
+            __IOM uint16_t CANM : 2;   /*!< [9..8] CAN Operating Mode Select                                          */
+            __IOM uint16_t SLPM : 1;   /*!< [10..10] CAN Sleep Mode                                                   */
+            __IOM uint16_t BOM  : 2;   /*!< [12..11] Bus-Off Recovery Mode by a program request                       */
+            __IOM uint16_t RBOC : 1;   /*!< [13..13] Forcible Return From Bus-Off                                     */
+            uint16_t            : 2;
+        } CTLR_b;
+    };
+
+    union
+    {
+        __IM uint16_t STR;             /*!< (@ 0x00000842) Status Register                                            */
+
+        struct
+        {
+            __IM uint16_t NDST  : 1;   /*!< [0..0] NEWDATA Status Flag                                                */
+            __IM uint16_t SDST  : 1;   /*!< [1..1] SENTDATA Status Flag                                               */
+            __IM uint16_t RFST  : 1;   /*!< [2..2] Receive FIFO Status Flag                                           */
+            __IM uint16_t TFST  : 1;   /*!< [3..3] Transmit FIFO Status Flag                                          */
+            __IM uint16_t NMLST : 1;   /*!< [4..4] Normal Mailbox Message Lost Status Flag                            */
+            __IM uint16_t FMLST : 1;   /*!< [5..5] FIFO Mailbox Message Lost Status Flag                              */
+            __IM uint16_t TABST : 1;   /*!< [6..6] Transmission Abort Status Flag                                     */
+            __IM uint16_t EST   : 1;   /*!< [7..7] Error Status Flag                                                  */
+            __IM uint16_t RSTST : 1;   /*!< [8..8] CAN Reset Status Flag                                              */
+            __IM uint16_t HLTST : 1;   /*!< [9..9] CAN Halt Status Flag                                               */
+            __IM uint16_t SLPST : 1;   /*!< [10..10] CAN Sleep Status Flag                                            */
+            __IM uint16_t EPST  : 1;   /*!< [11..11] Error-Passive Status Flag                                        */
+            __IM uint16_t BOST  : 1;   /*!< [12..12] Bus-Off Status Flag                                              */
+            __IM uint16_t TRMST : 1;   /*!< [13..13] Transmit Status Flag (transmitter)                               */
+            __IM uint16_t RECST : 1;   /*!< [14..14] Receive Status Flag (receiver)                                   */
+            uint16_t            : 1;
+        } STR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BCR;            /*!< (@ 0x00000844) Bit Configuration Register                                 */
+
+        struct
+        {
+            __IOM uint32_t CCLKS : 1;  /*!< [0..0] CAN Clock Source Selection                                         */
+            uint32_t             : 7;
+            __IOM uint32_t TSEG2 : 3;  /*!< [10..8] Time Segment 2 Control                                            */
+            uint32_t             : 1;
+            __IOM uint32_t SJW   : 2;  /*!< [13..12] Resynchronization Jump Width Control                             */
+            uint32_t             : 2;
+            __IOM uint32_t BRP   : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the
+                                        *   frequency of the CAN communication clock (fCANCLK).                       */
+            uint32_t             : 2;
+            __IOM uint32_t TSEG1 : 4;  /*!< [31..28] Time Segment 1 Control                                           */
+        } BCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RFCR;            /*!< (@ 0x00000848) Receive FIFO Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t RFE   : 1;   /*!< [0..0] Receive FIFO Enable                                                */
+            __IM uint8_t  RFUST : 3;   /*!< [3..1] Receive FIFO Unread Message Number Status                          */
+            __IOM uint8_t RFMLF : 1;   /*!< [4..4] Receive FIFO Message Lost Flag                                     */
+            __IM uint8_t  RFFST : 1;   /*!< [5..5] Receive FIFO Full Status Flag                                      */
+            __IM uint8_t  RFWST : 1;   /*!< [6..6] Receive FIFO Buffer Warning Status Flag                            */
+            __IM uint8_t  RFEST : 1;   /*!< [7..7] Receive FIFO Empty Status Flag                                     */
+        } RFCR_b;
+    };
+
+    union
+    {
+        __OM uint8_t RFPCR;            /*!< (@ 0x00000849) Receive FIFO Pointer Control Register                      */
+
+        struct
+        {
+            __OM uint8_t RFPCR : 8;    /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented
+                                        *   by writing FFh to RFPCR.                                                  */
+        } RFPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TFCR;            /*!< (@ 0x0000084A) Transmit FIFO Control Register                             */
+
+        struct
+        {
+            __IOM uint8_t TFE   : 1;   /*!< [0..0] Transmit FIFO Enable                                               */
+            __IM uint8_t  TFUST : 3;   /*!< [3..1] Transmit FIFO Unsent Message Number Status                         */
+            uint8_t             : 2;
+            __IM uint8_t TFFST  : 1;   /*!< [6..6] Transmit FIFO Full Status                                          */
+            __IM uint8_t TFEST  : 1;   /*!< [7..7] Transmit FIFO Empty Status                                         */
+        } TFCR_b;
+    };
+
+    union
+    {
+        __OM uint8_t TFPCR;            /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register                     */
+
+        struct
+        {
+            __OM uint8_t TFPCR : 8;    /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented
+                                        *   by writing FFh to TFPCR.                                                  */
+        } TFPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EIER;            /*!< (@ 0x0000084C) Error Interrupt Enable Register                            */
+
+        struct
+        {
+            __IOM uint8_t BEIE  : 1;   /*!< [0..0] Bus Error Interrupt Enable                                         */
+            __IOM uint8_t EWIE  : 1;   /*!< [1..1] Error-Warning Interrupt Enable                                     */
+            __IOM uint8_t EPIE  : 1;   /*!< [2..2] Error-Passive Interrupt Enable                                     */
+            __IOM uint8_t BOEIE : 1;   /*!< [3..3] Bus-Off Entry Interrupt Enable                                     */
+            __IOM uint8_t BORIE : 1;   /*!< [4..4] Bus-Off Recovery Interrupt Enable                                  */
+            __IOM uint8_t ORIE  : 1;   /*!< [5..5] Overrun Interrupt Enable                                           */
+            __IOM uint8_t OLIE  : 1;   /*!< [6..6] Overload Frame Transmit Interrupt Enable                           */
+            __IOM uint8_t BLIE  : 1;   /*!< [7..7] Bus Lock Interrupt Enable                                          */
+        } EIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t EIFR;            /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register                      */
+
+        struct
+        {
+            __IOM uint8_t BEIF  : 1;   /*!< [0..0] Bus Error Detect Flag                                              */
+            __IOM uint8_t EWIF  : 1;   /*!< [1..1] Error-Warning Detect Flag                                          */
+            __IOM uint8_t EPIF  : 1;   /*!< [2..2] Error-Passive Detect Flag                                          */
+            __IOM uint8_t BOEIF : 1;   /*!< [3..3] Bus-Off Entry Detect Flag                                          */
+            __IOM uint8_t BORIF : 1;   /*!< [4..4] Bus-Off Recovery Detect Flag                                       */
+            __IOM uint8_t ORIF  : 1;   /*!< [5..5] Receive Overrun Detect Flag                                        */
+            __IOM uint8_t OLIF  : 1;   /*!< [6..6] Overload Frame Transmission Detect Flag                            */
+            __IOM uint8_t BLIF  : 1;   /*!< [7..7] Bus Lock Detect Flag                                               */
+        } EIFR_b;
+    };
+
+    union
+    {
+        __IM uint8_t RECR;             /*!< (@ 0x0000084E) Receive Error Count Register                               */
+
+        struct
+        {
+            __IM uint8_t RECR : 8;     /*!< [7..0] Receive error count functionRECR increments or decrements
+                                        *   the counter value according to the error status of the
+                                        *   CAN module during reception.                                              */
+        } RECR_b;
+    };
+
+    union
+    {
+        __IM uint8_t TECR;             /*!< (@ 0x0000084F) Transmit Error Count Register                              */
+
+        struct
+        {
+            __IM uint8_t TECR : 8;     /*!< [7..0] Transmit error count functionTECR increments or decrements
+                                        *   the counter value according to the error status of the
+                                        *   CAN module during transmission.                                           */
+        } TECR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECSR;            /*!< (@ 0x00000850) Error Code Store Register                                  */
+
+        struct
+        {
+            __IOM uint8_t SEF  : 1;    /*!< [0..0] Stuff Error Flag                                                   */
+            __IOM uint8_t FEF  : 1;    /*!< [1..1] Form Error Flag                                                    */
+            __IOM uint8_t AEF  : 1;    /*!< [2..2] ACK Error Flag                                                     */
+            __IOM uint8_t CEF  : 1;    /*!< [3..3] CRC Error Flag                                                     */
+            __IOM uint8_t BE1F : 1;    /*!< [4..4] Bit Error (recessive) Flag                                         */
+            __IOM uint8_t BE0F : 1;    /*!< [5..5] Bit Error (dominant) Flag                                          */
+            __IOM uint8_t ADEF : 1;    /*!< [6..6] ACK Delimiter Error Flag                                           */
+            __IOM uint8_t EDPM : 1;    /*!< [7..7] Error Display Mode Select                                          */
+        } ECSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CSSR;            /*!< (@ 0x00000851) Channel Search Support Register                            */
+
+        struct
+        {
+            __IOM uint8_t CSSR : 8;    /*!< [7..0] When the value for the channel search is input, the channel
+                                        *   number is output to MSSR.                                                 */
+        } CSSR_b;
+    };
+
+    union
+    {
+        __IM uint8_t MSSR;             /*!< (@ 0x00000852) Mailbox Search Status Register                             */
+
+        struct
+        {
+            __IM uint8_t MBNST : 5;    /*!< [4..0] Search Result Mailbox Number Status These bits output
+                                        *   the smallest mailbox number that is searched in each mode
+                                        *   of MSMR.                                                                  */
+            uint8_t           : 2;
+            __IM uint8_t SEST : 1;     /*!< [7..7] Search Result Status                                               */
+        } MSSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MSMR;            /*!< (@ 0x00000853) Mailbox Search Mode Register                               */
+
+        struct
+        {
+            __IOM uint8_t MBSM : 2;    /*!< [1..0] Mailbox Search Mode Select                                         */
+            uint8_t            : 6;
+        } MSMR_b;
+    };
+
+    union
+    {
+        __IM uint16_t TSR;             /*!< (@ 0x00000854) Time Stamp Register                                        */
+
+        struct
+        {
+            __IM uint16_t TSR : 16;    /*!< [15..0] Free-running counter value for the time stamp function            */
+        } TSR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t AFSR;           /*!< (@ 0x00000856) Acceptance Filter Support Register                         */
+
+        struct
+        {
+            __IOM uint16_t AFSR : 16;  /*!< [15..0] After the standard ID of a received message is written,
+                                        *   the value converted for data table search can be read.                    */
+        } AFSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TCR;             /*!< (@ 0x00000858) Test Control Register                                      */
+
+        struct
+        {
+            __IOM uint8_t TSTE : 1;    /*!< [0..0] CAN Test Mode Enable                                               */
+            __IOM uint8_t TSTM : 2;    /*!< [2..1] CAN Test Mode Select                                               */
+            uint8_t            : 5;
+        } TCR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_CAN0_Type;                         /*!< Size = 2140 (0x85c)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
+ */
+
+typedef struct                         /*!< (@ 0x40074000) R_CRC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
+
+        struct
+        {
+            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
+            uint8_t              : 3;
+            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
+            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
+        } CRCCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
+            __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
+        } CRCCR1_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
+
+            struct
+            {
+                __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
+            } CRCDIR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
+                                              *   )                                                                         */
+            } CRCDIR_BY_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
+
+            struct
+            {
+                __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
+            } CRCDOR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
+
+            struct
+            {
+                __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
+                                                *   )                                                                         */
+            } CRCDOR_HA_b;
+        };
+
+        union
+        {
+            __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
+
+            struct
+            {
+                __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
+            } CRCDOR_BY_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
+
+        struct
+        {
+            __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
+            uint16_t             : 2;
+        } CRCSAR_b;
+    };
+    __IM uint16_t RESERVED1;
+} R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CTSU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Capacitive Touch Sensing Unit (R_CTSU)
+ */
+
+typedef struct                            /*!< (@ 0x40081000) R_CTSU Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t CTSUCR0;            /*!< (@ 0x00000000) CTSU Control Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t CTSUSTRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
+            __IOM uint8_t CTSUCAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
+            __IOM uint8_t CTSUSNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
+            __IOM uint8_t CTSUIOC    : 1; /*!< [3..3] CTSU Transmit Pin Control                                          */
+            __IOM uint8_t CTSUINIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
+            uint8_t                  : 2;
+            __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection                           */
+        } CTSUCR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUCR1;            /*!< (@ 0x00000001) CTSU Control Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t CTSUPON    : 1; /*!< [0..0] CTSU Power Supply Enable                                           */
+            __IOM uint8_t CTSUCSW    : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control                              */
+            __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting                           */
+            __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment                              */
+            __IOM uint8_t CTSUCLK    : 2; /*!< [5..4] CTSU Operating Clock Select                                        */
+            __IOM uint8_t CTSUMD     : 2; /*!< [7..6] CTSU Measurement Mode Select                                       */
+        } CTSUCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUSDPRS;           /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register          */
+
+        struct
+        {
+            __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
+                                            *   setting: 3 (0011b)                                                        */
+            __IOM uint8_t CTSUPRMODE : 2;  /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
+            __IOM uint8_t CTSUSOFF   : 1;  /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
+            uint8_t                  : 1;
+        } CTSUSDPRS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUSST;         /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register            */
+
+        struct
+        {
+            __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
+                                        *   of these bits should be fixed to 00010000b.                               */
+        } CTSUSST_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUMCH0;         /*!< (@ 0x00000004) CTSU Measurement Channel Register 0                        */
+
+        struct
+        {
+            __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
+                                         *   is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
+                                         *   bits = 00b).Note2: If the value of CTSUMCH0 was set to
+                                         *   b'111111 in mode other than self-capacitor single scan
+                                         *   mode, the measurement is stopped.                                         */
+            uint8_t : 2;
+        } CTSUMCH0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUMCH1;        /*!< (@ 0x00000005) CTSU Measurement Channel Register 1                        */
+
+        struct
+        {
+            __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
+                                        *   was set to b'111111, the measurement is stopped.                          */
+            uint8_t : 2;
+        } CTSUMCH1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUCHAC[5];     /*!< (@ 0x00000006) CTSU Channel Enable Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Enable Control                                        */
+            __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Enable Control                                        */
+        } CTSUCHAC_b[5];
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUCHTRC[5];    /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register             */
+
+        struct
+        {
+            __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Transmit/Receive Control                              */
+            __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Transmit/Receive Control                              */
+        } CTSUCHTRC_b[5];
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUDCLKC;         /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register            */
+
+        struct
+        {
+            __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
+                                          *   be set to 00b.                                                            */
+            uint8_t                 : 2;
+            __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
+                                          *   be set to 11b.                                                            */
+            uint8_t : 2;
+        } CTSUDCLKC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t CTSUST;           /*!< (@ 0x00000011) CTSU Status Register                                       */
+
+        struct
+        {
+            __IM uint8_t CTSUSTC   : 3; /*!< [2..0] CTSU Measurement Status Counter                                    */
+            uint8_t                : 1;
+            __IM uint8_t  CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag                                     */
+            __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag                                  */
+            __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag                               */
+            __IM uint8_t  CTSUPS   : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag                                */
+        } CTSUST_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CTSUSSC;        /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
+                                        *                  Control Register                                           */
+
+        struct
+        {
+            uint16_t                 : 8;
+            __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting                */
+            uint16_t                 : 4;
+        } CTSUSSC_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CTSUSO0;          /*!< (@ 0x00000014) CTSU Sensor Offset Register 0                              */
+
+        struct
+        {
+            __IOM uint16_t CTSUSO : 10;  /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
+                                          *   CTSUSO ( 0 to 1023 )                                                      */
+            __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting                                   */
+        } CTSUSO0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CTSUSO1;           /*!< (@ 0x00000016) CTSU Sensor Offset Register 1                              */
+
+        struct
+        {
+            __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
+                                           *   is CTSUSO ( 0 to 255 )                                                    */
+            __IOM uint16_t CTSUSDPA : 5;  /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
+                                           *   CTSUSDPA + 1 ) x 2                                                        */
+            __IOM uint16_t CTSUICOG : 2;  /*!< [14..13] CTSU ICO Gain Adjustment                                         */
+            uint16_t                : 1;
+        } CTSUSO1_b;
+    };
+
+    union
+    {
+        __IM uint16_t CTSUSC;          /*!< (@ 0x00000018) CTSU Sensor Counter                                        */
+
+        struct
+        {
+            __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
+                                        *   result of the CTSU. These bits indicate FFFFh when an overflow
+                                        *   occurs.                                                                   */
+        } CTSUSC_b;
+    };
+
+    union
+    {
+        __IM uint16_t CTSURC;          /*!< (@ 0x0000001A) CTSU Reference Counter                                     */
+
+        struct
+        {
+            __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
+                                        *   result of the reference ICO.These bits indicate FFFFh when
+                                        *   an overflow occurs.                                                       */
+        } CTSURC_b;
+    };
+
+    union
+    {
+        __IM uint16_t CTSUERRS;        /*!< (@ 0x0000001C) CTSU Error Status Register                                 */
+
+        struct
+        {
+            uint16_t                : 15;
+            __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor                                      */
+        } CTSUERRS_b;
+    };
+} R_CTSU_Type;                           /*!< Size = 30 (0x1e)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CTSU2                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Capacitive Touch Sensing Unit (R_CTSU2)
+ */
+
+typedef struct                         /*!< (@ 0x40082000) R_CTSU2 Structure                                          */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCRA;        /*!< (@ 0x00000000) CTSU Control Register A                                    */
+
+            struct
+            {
+                __IOM uint32_t STRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
+                __IOM uint32_t CAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
+                __IOM uint32_t SNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
+                __IOM uint32_t CFCON  : 1; /*!< [3..3] CTSU CFC Power on Control                                          */
+                __OM uint32_t  INIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
+                __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control                                         */
+                __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection                           */
+                __IOM uint32_t PON    : 1; /*!< [8..8] CTSU Power Supply Enable                                           */
+                __IOM uint32_t CSW    : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control                              */
+                __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting                         */
+                __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment                                    */
+                __IOM uint32_t CLK    : 2; /*!< [13..12] CTSU Operating Clock Select                                      */
+                __IOM uint32_t MD0    : 1; /*!< [14..14] CTSU Measurement Mode Select 0                                   */
+                __IOM uint32_t MD1    : 1; /*!< [15..15] CTSU Measurement Mode Select 1                                   */
+                __IOM uint32_t MD2    : 1; /*!< [16..16] CTSU Measurement Mode Select 2                                   */
+                __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment                                    */
+                __IOM uint32_t LOAD   : 2; /*!< [19..18] CTSU Measurement Load Control                                    */
+                __IOM uint32_t POSEL  : 2; /*!< [21..20] CTSU Non-measured Channel Output Select                          */
+                __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select                                   */
+                __IOM uint32_t FCMODE : 1; /*!< [23..23] CTSU SUCLK Control                                               */
+                __IOM uint32_t STCLK  : 6; /*!< [29..24] CTSU STCLK Select                                                */
+                __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select                             */
+                __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select                         */
+            } CTSUCRA_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUCRAL;   /*!< (@ 0x00000000) CTSU Control Register A                                    */
+
+                struct
+                {
+                    __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A                                    */
+                    __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A                                    */
+                };
+            };
+            __IOM uint8_t CTSUCR2;         /*!< (@ 0x00000002) CTSU Control Register A                                    */
+            __IOM uint8_t CTSUCR3;         /*!< (@ 0x00000003) CTSU Control Register A                                    */
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCRB;         /*!< (@ 0x00000004) CTSU Control Register B                                    */
+
+            struct
+            {
+                __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment                   */
+                __IOM uint32_t PRMODE  : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
+                __IOM uint32_t SOFF    : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
+                __IOM uint32_t PROFF   : 1; /*!< [7..7] CTSU Random Number Off Control                                     */
+                __IOM uint32_t SST     : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control                            */
+                uint32_t               : 8;
+                __IOM uint32_t SSMOD   : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select                                 */
+                uint32_t               : 1;
+                __IOM uint32_t SSCNT   : 2; /*!< [29..28] CTSU SUCLK Diffusion Control                                     */
+                uint32_t               : 2;
+            } CTSUCRB_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUCRBL;     /*!< (@ 0x00000004) CTSU Control Register B                                    */
+
+                struct
+                {
+                    __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B                                    */
+                    __IOM uint8_t CTSUSST;   /*!< (@ 0x00000005) CTSU Control Register B                                    */
+                };
+            };
+
+            union
+            {
+                __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B                                    */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED;
+                    __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUMCH;      /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
+
+            struct
+            {
+                __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0                                         */
+                uint32_t            : 2;
+                __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1                                        */
+                uint32_t            : 2;
+                __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control                                */
+                __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control                                */
+                __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control                                */
+                __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control                                */
+                uint32_t            : 12;
+            } CTSUMCH_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUMCHL;    /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
+
+                struct
+                {
+                    __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
+                    __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register                          */
+                };
+            };
+
+            union
+            {
+                __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
+                __IOM uint8_t  CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCHACA;      /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
+
+            struct
+            {
+                __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A                                      */
+                uint32_t              : 1;
+                __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A                                      */
+                uint32_t              : 1;
+                __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A                                      */
+                __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A                                    */
+                uint32_t              : 2;
+                __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A                                    */
+                __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A                                    */
+            } CTSUCHACA_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUCHACAL;   /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
+
+                struct
+                {
+                    __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
+                    __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A                     */
+                };
+            };
+
+            union
+            {
+                __IOM uint16_t CTSUCHACAH;   /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
+
+                struct
+                {
+                    __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
+                    __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A                     */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCHACB;      /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
+
+            struct
+            {
+                __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B                                      */
+                __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B                                      */
+                __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B                                      */
+                __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B                                      */
+                uint32_t              : 28;
+            } CTSUCHACB_b;
+        };
+        __IOM uint16_t CTSUCHACBL;         /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
+        __IOM uint8_t  CTSUCHAC4;          /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCHTRCA;      /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
+                                             *                  A                                                          */
+
+            struct
+            {
+                __IOM uint32_t CHTRC   : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A                            */
+                uint32_t               : 1;
+                __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A                            */
+                uint32_t               : 1;
+                __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A                            */
+                __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A                          */
+                uint32_t               : 2;
+                __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A                          */
+                __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A                          */
+            } CTSUCHTRCA_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUCHTRCAL;   /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+
+                struct
+                {
+                    __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+                    __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+                };
+            };
+
+            union
+            {
+                __IOM uint16_t CTSUCHTRCAH;   /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+
+                struct
+                {
+                    __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+                    __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register
+                                               *                  A                                                          */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCHTRCB;      /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
+                                             *                  B                                                          */
+
+            struct
+            {
+                __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B                            */
+                __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B                            */
+                __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B                            */
+                __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B                            */
+                uint32_t               : 28;
+            } CTSUCHTRCB_b;
+        };
+        __IOM uint16_t CTSUCHTRCBL;         /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
+                                             *                  B                                                          */
+        __IOM uint8_t CTSUCHTRC4;           /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
+                                             *                  B                                                          */
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUSR;          /*!< (@ 0x0000001C) CTSU Status Register                                       */
+
+            struct
+            {
+                __IOM uint32_t MFC     : 2; /*!< [1..0] CTSU Multi-clock Counter                                           */
+                uint32_t               : 3;
+                __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset                                         */
+                __IM uint32_t ICOMP1   : 1; /*!< [6..6] CTSU Sense Current Error Monitor                                   */
+                __IM uint32_t ICOMP0   : 1; /*!< [7..7] TSCAP Voltage Error Monitor                                        */
+                __IM uint32_t STC      : 3; /*!< [10..8] CTSU Measurement Status Counter                                   */
+                uint32_t               : 1;
+                __IM uint32_t  DTSR    : 1; /*!< [12..12] CTSU Data Transfer Status Flag                                   */
+                __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag                                */
+                uint32_t               : 1;
+                __IM uint32_t  PS      : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag                              */
+                __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select                                     */
+                uint32_t               : 10;
+            } CTSUSR_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CTSUSRL;    /*!< (@ 0x0000001C) CTSU Status Register                                       */
+
+                struct
+                {
+                    __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register                                       */
+                    __IOM uint8_t CTSUST;  /*!< (@ 0x0000001D) CTSU Status Register                                       */
+                };
+            };
+
+            union
+            {
+                __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register                                       */
+                __IOM uint8_t  CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register                                       */
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUSO;         /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
+
+            struct
+            {
+                __IOM uint32_t SO    : 10; /*!< [9..0] CTSU Sensor Offset Adjustment                                      */
+                __IOM uint32_t SNUM  : 8;  /*!< [17..10] CTSU Measurement Count Setting                                   */
+                uint32_t             : 2;
+                __IOM uint32_t SSDIV : 4;  /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting               */
+                __IOM uint32_t SDPA  : 8;  /*!< [31..24] CTSU Base Clock Setting                                          */
+            } CTSUSO_b;
+        };
+
+        struct
+        {
+            __IOM uint16_t CTSUSO0;    /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
+            __IOM uint16_t CTSUSO1;    /*!< (@ 0x00000022) CTSU Sensor Offset Register                                */
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t CTSUSCNT;         /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
+
+            struct
+            {
+                __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter                                               */
+                uint32_t              : 16;
+            } CTSUSCNT_b;
+        };
+        __IM uint16_t CTSUSC;               /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUCALIB;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
+
+            struct
+            {
+                uint32_t                : 2;
+                __IOM uint32_t TSOD     : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select                                   */
+                __IOM uint32_t DRV      : 1; /*!< [3..3] CTSU Calibration Setting Bit 1                                     */
+                uint32_t                : 2;
+                __IOM uint32_t SUCLKEN  : 1; /*!< [6..6] CTSU SUCLK Enable Control                                          */
+                __IOM uint32_t TSOC     : 1; /*!< [7..7] CTSU Calibration Setting Bit 2                                     */
+                uint32_t                : 1;
+                __IOM uint32_t IOC      : 1; /*!< [9..9] CTSU Transfer Pins Control                                         */
+                __IOM uint32_t CFCRDMD  : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select                                */
+                __IOM uint32_t DCOFF    : 1; /*!< [11..11] CTSU Down Converter Control                                      */
+                uint32_t                : 10;
+                __IOM uint32_t CFCMODE  : 1; /*!< [22..22] CTSU CFC Current Source Switching                                */
+                uint32_t                : 2;
+                __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control                      */
+                uint32_t                : 1;
+                __IOM uint32_t SUCARRY  : 1; /*!< [27..27] CTSU CCO Carry Control                                           */
+                __IOM uint32_t DACCLK   : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select                         */
+                __IOM uint32_t CCOCLK   : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select                         */
+                __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select                                 */
+                uint32_t                : 1;
+            } CTSUCALIB_b;
+        };
+
+        struct
+        {
+            __IOM uint16_t CTSUDBGR0;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
+            __IOM uint16_t CTSUDBGR1;  /*!< (@ 0x0000002A) CTSU Calibration Register                                  */
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t CTSUSUCLKA;     /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
+
+        struct
+        {
+            __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
+            __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A                  */
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t CTSUSUCLKB;       /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
+
+            struct
+            {
+                __IOM uint32_t SUADJ2   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
+                __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
+                __IOM uint32_t SUADJ3   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
+                __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
+            } CTSUSUCLKB_b;
+        };
+
+        struct
+        {
+            __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
+            __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B                  */
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t CTSUCFCCNT;      /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
+
+            struct
+            {
+                __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter                                                  */
+                uint32_t             : 16;
+            } CTSUCFCCNT_b;
+        };
+        __IM uint16_t CTSUCFCCNTL;         /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
+    };
+} R_CTSU2_Type;                            /*!< Size = 56 (0x38)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief D/A Converter (R_DAC)
+ */
+
+typedef struct                         /*!< (@ 0x4005E000) R_DAC Structure                                            */
+{
+    union
+    {
+        __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
+
+        struct
+        {
+            __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
+                                        *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
+                                        *   = 1, the low-order 4 bits are fixed to 0: left justified
+                                        *   format.                                                                   */
+        } DADR_b[2];
+    };
+
+    union
+    {
+        __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
+
+        struct
+        {
+            uint8_t             : 5;
+            __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
+            __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
+            __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
+        } DACR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
+        } DADPR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
+        } DAADSCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
+            uint8_t           : 5;
+        } DAVREFCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
+            __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
+        } DAAMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
+
+        struct
+        {
+            __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
+            uint8_t              : 7;
+        } DAPC_b;
+    };
+    __IM uint16_t RESERVED[9];
+
+    union
+    {
+        __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
+
+        struct
+        {
+            uint8_t              : 6;
+            __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   0. When the DAASW0 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 0 is output
+                                        *   through the output amplifier.                                             */
+            __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
+                                        *   to wait for stabilization of the output amplifier of D/A
+                                        *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
+                                        *   but the conversion result D/A is not output from channel
+                                        *   1. When the DAASW1 bit is 0, the stabilization wait time
+                                        *   stops, and the D/A conversion result of channel 1 is output
+                                        *   through the output amplifier.                                             */
+        } DAASWCR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2[2129];
+
+    union
+    {
+        __IOM uint8_t DAADUSR;         /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
+
+        struct
+        {
+            uint8_t                : 6;
+            __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for
+                                         *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
+                                         *   select unit 1 as the target synchronous unit for the MCU.
+                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
+                                         *   conversions, select the target unit in this register in
+                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
+                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
+                                         *   is set to 0.                                                              */
+            uint8_t : 1;
+        } DAADUSR_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DAC8                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 8-Bit D/A Converter (R_DAC8)
+ */
+
+typedef struct                         /*!< (@ 0x4009E000) R_DAC8 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t DACS[2];         /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1]               */
+
+        struct
+        {
+            __IOM uint8_t DACS : 8;    /*!< [7..0] DACS D/A conversion store data                                     */
+        } DACS_b[2];
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t DAM;             /*!< (@ 0x00000003) D/A Converter Mode Register                                */
+
+        struct
+        {
+            __IOM uint8_t DAMD0 : 1;   /*!< [0..0] D/A operation mode select 0                                        */
+            __IOM uint8_t DAMD1 : 1;   /*!< [1..1] D/A operation mode select 1                                        */
+            uint8_t             : 2;
+            __IOM uint8_t DACE0 : 1;   /*!< [4..4] D/A operation enable 0                                             */
+            __IOM uint8_t DACE1 : 1;   /*!< [5..5] D/A operation enable 1                                             */
+            uint8_t             : 2;
+        } DAM_b;
+    };
+    __IM uint8_t RESERVED1[2];
+
+    union
+    {
+        __IOM uint8_t DACADSCR;        /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion                                     */
+            uint8_t               : 7;
+        } DACADSCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DACPC;           /*!< (@ 0x00000007) D/A SW Charge Pump Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge pump enable                                                 */
+            uint8_t              : 7;
+        } DACPC_b;
+    };
+} R_DAC8_Type;                         /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DALI0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Digital Addressable Lighting Interface (R_DALI0)
+ */
+
+typedef struct                         /*!< (@ 0x4008F000) R_DALI0 Structure                                          */
+{
+    union
+    {
+        __IOM uint16_t BTVTHR1;        /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register
+                                        *                  1                                                          */
+
+        struct
+        {
+            __IOM uint16_t BTV1 : 7;   /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing
+                                        *   violation threshold value 1.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+            uint16_t            : 1;
+            __IOM uint16_t BTV2 : 8;   /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing
+                                        *   violation threshold value 2.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+        } BTVTHR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BTVTHR2;        /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register
+                                        *                  2                                                          */
+
+        struct
+        {
+            __IOM uint16_t BTV3 : 8;   /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing
+                                        *   violation threshold value 3.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+            __IOM uint16_t BTV4 : 8;   /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing
+                                        *   violation threshold value 4.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+        } BTVTHR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BTVTHR3;        /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register
+                                        *                  3                                                          */
+
+        struct
+        {
+            __IOM uint16_t BTV5 : 8;   /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing
+                                        *   violation threshold value 5.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+            uint16_t : 8;
+        } BTVTHR3_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BTVTHR4;        /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register
+                                        *                  4                                                          */
+
+        struct
+        {
+            __IOM uint16_t BTV6 : 9;   /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing
+                                        *   violation threshold value 6.Note 1. These bits must be
+                                        *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
+                                        *   bit is 0.                                                                 */
+            uint16_t : 7;
+        } BTVTHR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t COLTHR1;        /*!< (@ 0x00000008) DALI Collision Threshold Register 1                        */
+
+        struct
+        {
+            __IOM uint16_t COL1 : 6;   /*!< [5..0] Collision Threshold 1Specifies the collision threshold
+                                        *   value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t            : 2;
+            __IOM uint16_t COL2 : 6;   /*!< [13..8] Collision Threshold 2Specifies the collision threshold
+                                        *   value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t : 2;
+        } COLTHR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t COLTHR2;        /*!< (@ 0x0000000A) DALI Collision Threshold Register 2                        */
+
+        struct
+        {
+            __IOM uint16_t COL3 : 7;   /*!< [6..0] Collision Threshold 3Specifies the collision threshold
+                                        *   value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t            : 1;
+            __IOM uint16_t COL4 : 7;   /*!< [14..8] Collision Threshold 4Specifies the collision threshold
+                                        *   value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t : 1;
+        } COLTHR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t COLTHR3;        /*!< (@ 0x0000000C) DALI Collision Threshold Register 3                        */
+
+        struct
+        {
+            __IOM uint16_t COL5 : 7;   /*!< [6..0] Collision Threshold 5Specifies the collision threshold
+                                        *   value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t            : 1;
+            __IOM uint16_t COL6 : 7;   /*!< [14..8] Collision Threshold 6Specifies the collision threshold
+                                        *   value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t : 1;
+        } COLTHR3_b;
+    };
+
+    union
+    {
+        __IOM uint16_t COLTHR4;        /*!< (@ 0x0000000E) DALI Collision Threshold Register 4                        */
+
+        struct
+        {
+            __IOM uint16_t COL7 : 8;   /*!< [7..0] Collision Threshold 7Specifies the collision threshold
+                                        *   value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            __IOM uint16_t COL8 : 8;   /*!< [15..8] Collision Threshold 8Specifies the collision threshold
+                                        *   value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+        } COLTHR4_b;
+    };
+
+    union
+    {
+        __IOM uint16_t COLTHR5;        /*!< (@ 0x00000010) DALI Collision Threshold Register 5                        */
+
+        struct
+        {
+            __IOM uint16_t COL9 : 8;   /*!< [7..0] Collision Threshold 9Specifies the collision threshold
+                                        *   value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE
+                                        *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
+            uint16_t : 8;
+        } COLTHR5_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CNFR1;          /*!< (@ 0x00000012) DALI Configuration Register 1                              */
+
+        struct
+        {
+            __IOM uint16_t BR  : 8;    /*!< [7..0] Clock SelectBit rate setting example is shown in Table             */
+            __IOM uint16_t CKS : 2;    /*!< [9..8] Clock Select                                                       */
+            uint16_t           : 2;
+            __IOM uint16_t CHL : 3;    /*!< [14..12] Character Length                                                 */
+            uint16_t           : 1;
+        } CNFR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CNFR2;          /*!< (@ 0x00000014) DALI Configuration Register 2                              */
+
+        struct
+        {
+            __IOM uint16_t BTVE : 1;   /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified
+                                        *   only when the DALI0.STR1.BBF bit is 0.                                    */
+            __IOM uint16_t BTVM : 1;   /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified
+                                        *   only when the DALI0.STR1.BBF bit is 0.                                    */
+            __IOM uint16_t SGA : 1;    /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified
+                                        *   only when the DALI0.STR1.BBF bit is 0.                                    */
+            __IOM uint16_t TXWE : 1;   /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified
+                                        *   only when the DALI0.STR1.BBF bit is 0.                                    */
+            __IOM uint16_t CDE : 1;    /*!< [4..4] Collision Detect EnableNote: The bit must be modified
+                                        *   only when the DALI0.STR1.BBF bit is 0.                                    */
+            __IOM uint16_t CDM0 : 1;   /*!< [5..5] Collision Detect ModeNote: The bit must be modified only
+                                        *   when the DALI0.STR1.BBF bit is 0.                                         */
+            uint16_t : 10;
+        } CNFR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t TXWR1;          /*!< (@ 0x00000016) DALI DTX Width Register 1                                  */
+
+        struct
+        {
+            __IOM uint16_t TXLW : 7;   /*!< [6..0] DTX Low WidthDTX0 pin low level width                              */
+            uint16_t            : 9;
+        } TXWR1_b;
+    };
+    __IM uint16_t RESERVED[3];
+
+    union
+    {
+        __IOM uint16_t TDR1H;          /*!< (@ 0x0000001E) DALI Transmit Data Register 1H                             */
+
+        struct
+        {
+            __IOM uint16_t DTDR : 16;  /*!< [15..0] Upper 16-bit DALI transmit data                                   */
+        } TDR1H_b;
+    };
+
+    union
+    {
+        __IOM uint16_t TDR1L;          /*!< (@ 0x00000020) DALI Transmit Data Register 1L                             */
+
+        struct
+        {
+            __IOM uint16_t DTDR : 16;  /*!< [15..0] Lower 16-bit DALI transmit data                                   */
+        } TDR1L_b;
+    };
+
+    union
+    {
+        __OM uint16_t TRSTR1;          /*!< (@ 0x00000022) DALI Transmit Control Register 1                           */
+
+        struct
+        {
+            __OM uint16_t TRST : 1;    /*!< [0..0] Transmission Start Trigger                                         */
+            uint16_t           : 15;
+        } TRSTR1_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t CTR1;           /*!< (@ 0x00000026) DALI Control Register 1                                    */
+
+        struct
+        {
+            __IOM uint16_t TE   : 1;   /*!< [0..0] Transmit Enabling                                                  */
+            __IOM uint16_t RE   : 1;   /*!< [1..1] Receive Enabling                                                   */
+            uint16_t            : 6;
+            __IOM uint16_t SDIE : 1;   /*!< [8..8] DALI_SDI Output Enabling                                           */
+            __IOM uint16_t DEIE : 1;   /*!< [9..9] DALI_DEI Output Enabling                                           */
+            __IOM uint16_t CLIE : 1;   /*!< [10..10] DALI_CLI Output Enabling                                         */
+            __IOM uint16_t BPIE : 1;   /*!< [11..11] DALI_BPI Output Enabling                                         */
+            __IOM uint16_t FEIE : 1;   /*!< [12..12] DALI_FEI Output Enabling                                         */
+            uint16_t            : 3;
+        } CTR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t TXDCTR1;        /*!< (@ 0x00000028) DALI DTX Control Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t TXAS : 1;   /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only
+                                        *   when the DALI0.CTR1.TE bit is 0.                                          */
+            __IOM uint16_t TXASE : 1;  /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only
+                                        *   when the DALI0.CTR1.TE bit is 0.                                          */
+            uint16_t : 14;
+        } TXDCTR1_b;
+    };
+    __IM uint16_t RESERVED2[2];
+
+    union
+    {
+        __IM uint16_t RDR1H;           /*!< (@ 0x0000002E) DALI Reception Data Register 1H                            */
+
+        struct
+        {
+            __IM uint16_t DRDR : 16;   /*!< [15..0] Upper 16-bit of DALI receive data                                 */
+        } RDR1H_b;
+    };
+
+    union
+    {
+        __IM uint16_t RDR1L;           /*!< (@ 0x00000030) DALI Reception Data Register 1L                            */
+
+        struct
+        {
+            __IM uint16_t DRDR : 16;   /*!< [15..0] Lower 16-bit of DALI receive data                                 */
+        } RDR1L_b;
+    };
+
+    union
+    {
+        __IM uint16_t STR1;            /*!< (@ 0x00000032) DALI Status Register 1                                     */
+
+        struct
+        {
+            __IM uint16_t MFEF  : 1;   /*!< [0..0] Manchester Flaming Error Flag                                      */
+            __IM uint16_t OVF   : 1;   /*!< [1..1] Overrun Error Flag                                                 */
+            __IM uint16_t BTVF  : 1;   /*!< [2..2] Bit Timing Violation Flag                                          */
+            __IM uint16_t RDRF  : 1;   /*!< [3..3] Receive Data Register Full Flag                                    */
+            __IM uint16_t TENDF : 1;   /*!< [4..4] Transmit End Flag                                                  */
+            __IM uint16_t BBF   : 1;   /*!< [5..5] Bus BUSY Flag                                                      */
+            __IM uint16_t BPDF  : 1;   /*!< [6..6] Bus Power Down Flag                                                */
+            __IM uint16_t O32F  : 1;   /*!< [7..7] Over 32-Bit Data Reception Flag                                    */
+            __IM uint16_t CDF   : 1;   /*!< [8..8] Collision Detect Flag                                              */
+            __IM uint16_t DAF   : 1;   /*!< [9..9] Destroy Area Flag                                                  */
+            __IM uint16_t RDBL  : 6;   /*!< [15..10] Receive Data Bit LengthThese bits store the bit length
+                                        *   for data received successfully                                            */
+        } STR1_b;
+    };
+    __IM uint16_t RESERVED3;
+
+    union
+    {
+        __IM uint16_t COLR1;           /*!< (@ 0x00000036) DALI Collision Register 1                                  */
+
+        struct
+        {
+            __IM uint16_t CFTF2  : 4;  /*!< [3..0] Collision Detect Timing Flag 2                                     */
+            __IM uint16_t CDTF1  : 1;  /*!< [4..4] Collision Detect Timing Flag 1                                     */
+            uint16_t             : 5;
+            __IM uint16_t CLDAF  : 1;  /*!< [10..10] Collision Last Destroy Area Flag                                 */
+            __IM uint16_t RXDMON : 1;  /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after
+                                        *   the DRX0 pin is synchronized                                              */
+            __IM uint16_t RXDCEG : 1;  /*!< [12..12] DRX Collision Edge                                               */
+            __IM uint16_t TXDCV  : 1;  /*!< [13..13] DTX Collision Value                                              */
+            uint16_t             : 2;
+        } COLR1_b;
+    };
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __OM uint16_t FECR1;           /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1                           */
+
+        struct
+        {
+            __OM uint16_t MFEFC  : 1;  /*!< [0..0] Manchester Flaming Error Flag Clear                                */
+            __OM uint16_t OVFC   : 1;  /*!< [1..1] Overrun Error Flag Clear                                           */
+            __OM uint16_t BTVFC  : 1;  /*!< [2..2] Bit Timing Violation Flag Clear                                    */
+            __OM uint16_t RDRFC  : 1;  /*!< [3..3] Receive Data Register Full Flag Clear                              */
+            __OM uint16_t TENDFC : 1;  /*!< [4..4] Transmit End Flag Clear                                            */
+            __OM uint16_t BBFC   : 1;  /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
+                                        *   bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1.                     */
+            __OM uint16_t BPDFC : 1;   /*!< [6..6] Bus Power Down Flag Clear                                          */
+            __OM uint16_t O32FC : 1;   /*!< [7..7] Over 32-Bit Data Reception Flag Clear                              */
+            __OM uint16_t CDFC  : 1;   /*!< [8..8] Collision Detect Flag Clear                                        */
+            __OM uint16_t DAFC  : 1;   /*!< [9..9] Destroy Area Flag Clear                                            */
+            uint16_t            : 6;
+        } FECR1_b;
+    };
+
+    union
+    {
+        __OM uint16_t SWRR1;           /*!< (@ 0x0000003C) DALI Software Reset Register 1                             */
+
+        struct
+        {
+            __OM uint16_t SWR : 1;     /*!< [0..0] Software ResetWriting 1 to this bit causes a software
+                                        *   reset.                                                                    */
+            uint16_t : 15;
+        } SWRR1_b;
+    };
+} R_DALI0_Type;                        /*!< Size = 62 (0x3e)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Debug Function (R_DEBUG)
+ */
+
+typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
+{
+    union
+    {
+        __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
+
+        struct
+        {
+            uint32_t                   : 28;
+            __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
+            __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
+            uint32_t                   : 2;
+        } DBGSTR_b;
+    };
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
+
+        struct
+        {
+            __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
+            __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
+            uint32_t                     : 14;
+            __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
+            __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
+            uint32_t                     : 5;
+            __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
+            __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
+            uint32_t                     : 6;
+        } DBGSTOPCR_b;
+    };
+} R_DEBUG_Type;                               /*!< Size = 20 (0x14)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller Common (R_DMA)
+ */
+
+typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
+
+        struct
+        {
+            __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
+            uint8_t            : 7;
+        } DMAST_b;
+    };
+} R_DMA_Type;                          /*!< Size = 1 (0x1)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief DMA Controller (R_DMAC0)
+ */
+
+typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
+        } DMSAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
+
+        struct
+        {
+            __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
+        } DMDAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
+
+        struct
+        {
+            __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
+            __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
+            uint32_t              : 6;
+        } DMCRA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMCRB;          /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
+
+        struct
+        {
+            __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or
+                                        *   repeat transfer operations.                                               */
+        } DMCRB_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
+
+        struct
+        {
+            __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
+            uint16_t            : 6;
+            __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
+            uint16_t            : 2;
+            __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
+            __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
+        } DMTMD_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
+
+        struct
+        {
+            __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
+                                        *   Enable                                                                    */
+            __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
+            __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
+            __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
+            uint8_t             : 3;
+        } DMINT_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
+                                        *   extended repeat area on the destination address. For details
+                                        *   on the settings.                                                          */
+            uint16_t            : 1;
+            __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
+            __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
+                                        *   repeat area on the source address. For details on the settings.           */
+            uint16_t          : 1;
+            __IOM uint16_t SM : 2;     /*!< [15..14] Source Address Update Mode                                       */
+        } DMAMD_b;
+    };
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
+
+        struct
+        {
+            __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
+                                        *   as the address update mode for transfer source or destination.            */
+        } DMOFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
+
+        struct
+        {
+            __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
+            uint8_t           : 7;
+        } DMCNT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
+
+        struct
+        {
+            __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
+            uint8_t             : 3;
+            __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
+            uint8_t             : 3;
+        } DMREQ_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DMSTS;           /*!< (@ 0x0000001E) DMA Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t ESIF : 1;    /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
+            uint8_t            : 3;
+            __IOM uint8_t DTIF : 1;    /*!< [4..4] Transfer End Interrupt Flag                                        */
+            uint8_t            : 2;
+            __IM uint8_t ACT   : 1;    /*!< [7..7] DMA Active Flag                                                    */
+        } DMSTS_b;
+    };
+    __IM uint8_t RESERVED3;
+} R_DMAC0_Type;                        /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Operation Circuit (R_DOC)
+ */
+
+typedef struct                         /*!< (@ 0x40054100) R_DOC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
+            __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
+            uint8_t               : 2;
+            __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
+            __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
+            uint8_t               : 1;
+        } DOCR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
+
+        struct
+        {
+            __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
+                                        *   use in the operations are stored.                                         */
+        } DODIR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
+
+        struct
+        {
+            __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
+                                        *   in data comparison mode. This register also stores the
+                                        *   results of operations in data addition and data subtraction
+                                        *   modes.                                                                    */
+        } DODSR_b;
+    };
+} R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DRW                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief 2D Drawing Engine (R_DRW)
+ */
+
+typedef struct                         /*!< (@ 0x400E4000) R_DRW Structure                                            */
+{
+    union
+    {
+        union
+        {
+            __OM uint32_t CONTROL;               /*!< (@ 0x00000000) Geometry Control Register                                  */
+
+            struct
+            {
+                __OM uint32_t LIM1ENABLE    : 1; /*!< [0..0] Enable limiter 1                                                   */
+                __OM uint32_t LIM2ENABLE    : 1; /*!< [1..1] Enable limiter 2                                                   */
+                __OM uint32_t LIM3ENABLE    : 1; /*!< [2..2] Enable limiter 3                                                   */
+                __OM uint32_t LIM4ENABLE    : 1; /*!< [3..3] Enable limiter 4                                                   */
+                __OM uint32_t LIM5ENABLE    : 1; /*!< [4..4] Enable limiter 5                                                   */
+                __OM uint32_t LIM6ENABLE    : 1; /*!< [5..5] Enable limiter 6                                                   */
+                __OM uint32_t QUAD1ENABLE   : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2                      */
+                __OM uint32_t QUAD2ENABLE   : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4                      */
+                __OM uint32_t QUAD3ENABLE   : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6                      */
+                __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode                                    */
+                __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode                                  */
+                __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode                                  */
+                __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode                                  */
+                __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode                                  */
+                __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode                                  */
+                __OM uint32_t BAND1ENABLE   : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND)               */
+                __OM uint32_t BAND2ENABLE   : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND)               */
+                __OM uint32_t UNION12       : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A)               */
+                __OM uint32_t UNION34       : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B)               */
+                __OM uint32_t UNION56       : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D)               */
+                __OM uint32_t UNIONAB       : 1; /*!< [20..20] Combine outputs A & B as union (output is called C)              */
+                __OM uint32_t UNIONCD       : 1; /*!< [21..21] Combine outputs C & D as union (output is final)                 */
+                __OM uint32_t SPANABORT     : 1; /*!< [22..22] Shape is horizontally convex, only a single span per
+                                                  *   scanline                                                                  */
+                __OM uint32_t SPANSTORE : 1;     /*!< [23..23] Nextline span start is always equal or left to current-line
+                                                  *   span start                                                                */
+                uint32_t : 8;
+            } CONTROL_b;
+        };
+
+        union
+        {
+            __IM uint32_t STATUS;               /*!< (@ 0x00000000) Status Control Register                                    */
+
+            struct
+            {
+                __IM uint32_t BUSYENUM     : 1; /*!< [0..0] Enumeration unit status                                            */
+                __IM uint32_t BUSYWRITE    : 1; /*!< [1..1] Framebuffer writeback status                                       */
+                __IM uint32_t CACHEDIRTY   : 1; /*!< [2..2] Framebuffer cache status                                           */
+                __IM uint32_t DLISTACTIVE  : 1; /*!< [3..3] Display list reader status                                         */
+                __IM uint32_t ENUMIRQ      : 1; /*!< [4..4] enumeration finished interrupt triggered                           */
+                __IM uint32_t DLISTIRQ     : 1; /*!< [5..5] display list finished interrupt triggered                          */
+                __IM uint32_t BUSIRQ       : 1; /*!< [6..6] bus error interrupt triggered                                      */
+                uint32_t                   : 1;
+                __IM uint32_t BUSERRMFB    : 1; /*!< [8..8] framebuffer bus error interrupt triggered                          */
+                __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered                              */
+                __IM uint32_t BUSERRMDL    : 1; /*!< [10..10] display list bus error interrupt triggered                       */
+                uint32_t                   : 21;
+            } STATUS_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t CONTROL2;                /*!< (@ 0x00000004) Surface Control Register                                   */
+
+            struct
+            {
+                __OM uint32_t PATTERNENABLE : 1;   /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and
+                                                    *   COLOR2 depending on PATTERN and pattern index)                            */
+                __OM uint32_t TEXTUREENABLE : 1;   /*!< [1..1] Pixel source is read from texture and used as an alpha
+                                                    *   to blend between COLOR1 and COLOR2                                        */
+                __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default
+                                                    *   U limiter.Limiter 5 can be combined with limiter 6 to form
+                                                    *   a quadratic limiter which can be used to make quadratic
+                                                    *   pattern functions to draw radial patterns.                                */
+                __OM uint32_t USEACB       : 1;    /*!< [3..3] Alpha blend mode                                                   */
+                __OM uint32_t READFORMAT32 : 2;    /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT
+                                                    *   above for description                                                     */
+                __OM uint32_t BSFA : 1;            /*!< [6..6] Blend source factor for alpha channel in alpha channel
+                                                    *   blending mode (USEACB = 1)                                                */
+                __OM uint32_t BDFA : 1;            /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel
+                                                    *   blending mode (USEACB = 1)                                                */
+                __OM uint32_t WRITEFORMAT2 : 1;    /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above
+                                                    *   description.                                                              */
+                __OM uint32_t BSF : 1;             /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per
+                                                    *   default)                                                                  */
+                __OM uint32_t BDF : 1;             /*!< [10..10] Blend destination factordst factor is alpha (factor
+                                                    *   is 1 per default)                                                         */
+                __OM uint32_t BSI : 1;             /*!< [11..11] Blend source factor is invertedsrc factor will be inverted
+                                                    *   (meaning 1-a or 1-1 depending on BSF)                                     */
+                __OM uint32_t BDI : 1;             /*!< [12..12] Blend destination factor is inverteddst factor will
+                                                    *   be inverted (meaning 1-a or 1-1 depending on BDF)                         */
+                __OM uint32_t BC2           : 1;   /*!< [13..13] Blend color 2 instead of framebuffer pixel                       */
+                __OM uint32_t TEXTURECLAMPX : 1;   /*!< [14..14] Calculating U limiter outside use textureThe bit describes
+                                                    *   what happens if the U limiter (x direction in texture space)
+                                                    *   calculates a U value outside of the used texture                          */
+                __OM uint32_t TEXTURECLAMPY : 1;   /*!< [15..15] Calculating V limiter outside use textureThe bit describes
+                                                    *   what happens if the V limiter (y direction in texture space)
+                                                    *   calculates a V value outside of the used texture                          */
+                __OM uint32_t TEXTUREFILTERX : 1;  /*!< [16..16] Linear filtering on texture U axis                               */
+                __OM uint32_t TEXTUREFILTERY : 1;  /*!< [17..17] Linear filtering on texture V axis                               */
+                __OM uint32_t READFORMAT10   : 2;  /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000:
+                                                    *   8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011:
+                                                    *   16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44)
+                                                    *   4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8),
+                                                    *   8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4),
+                                                    *   4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2),
+                                                    *   2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1),
+                                                    *   1 bit indexed color/luminance                                             */
+                __OM uint32_t WRITEFORMAT10 : 2;   /*!< [21..20] Pixel format of the framebuffer                                  */
+                __OM uint32_t WRITEALPHA    : 2;   /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha
+                                                    *   source' for the framebuffer(USEACB = 0)Blend alpha in color
+                                                    *   2 instead of framebuffer alpha((USEACB = 1))In not alpha
+                                                    *   channel blending mode (USEACB = 0):Set the 'alpha source'
+                                                    *   for the framebuffer.In alpha channel blending mode (USEACB
+                                                    *   = 1):Blend alpha in color 2 instead of framebuffer alpha00B:
+                                                    *   BC2A = 1: use alpha from framebuffer as destination (DST_A)else:
+                                                    *   BC2A = 0: use alpha in color 2 as destination (DST_A)                     */
+                __OM uint32_t RLEENABLE    : 1;    /*!< [24..24] RLE enable                                                       */
+                __OM uint32_t CLUTENABLE   : 1;    /*!< [25..25] CLUT enable                                                      */
+                __OM uint32_t COLKEYENABLE : 1;    /*!< [26..26] color keying enable                                              */
+                __OM uint32_t CLUTFORMAT   : 1;    /*!< [27..27] Format of the CLUT                                               */
+                __OM uint32_t BSIA         : 1;    /*!< [28..28] Blend source factor inverted in alpha channel (USEACB
+                                                    *   = 1)                                                                      */
+                __OM uint32_t BDIA : 1;            /*!< [29..29] Blend destination factor inverted in alpha channel
+                                                    *   (USEACB = 1)                                                              */
+                __OM uint32_t RLEPIXELWIDTH : 2;   /*!< [31..30] Texel width for RLE unit                                         */
+            } CONTROL2_b;
+        };
+
+        union
+        {
+            __IM uint32_t HWREVISION;          /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register               */
+
+            struct
+            {
+                __IM uint32_t REV        : 12; /*!< [11..0] Revision number                                                   */
+                uint32_t                 : 5;
+                __IM uint32_t DLR        : 1;  /*!< [17..17] Display list reader feature                                      */
+                __IM uint32_t FBCACHE    : 1;  /*!< [18..18] Framebuffer cache feature                                        */
+                __IM uint32_t TXCACHE    : 1;  /*!< [19..19] Texture cache feature                                            */
+                __IM uint32_t PERFCOUNT  : 1;  /*!< [20..20] Two performance counter feature                                  */
+                __IM uint32_t TEXCLU     : 1;  /*!< [21..21] Texture CLUT with 16 or 256 entries feature                      */
+                uint32_t                 : 1;
+                __IM uint32_t RLEUNIT    : 1;  /*!< [23..23] RLE unit feature                                                 */
+                __IM uint32_t TEXCLUT256 : 1;  /*!< [24..24] Texture CLUT feature                                             */
+                __IM uint32_t COLORKEY   : 1;  /*!< [25..25] Colorkey feature                                                 */
+                uint32_t                 : 1;
+                __IM uint32_t ACBLEND    : 1;  /*!< [27..27] Alpha channel blending feature                                   */
+                uint32_t                 : 4;
+            } HWREVISION_b;
+        };
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __OM uint32_t L1START;         /*!< (@ 0x00000010) Limiter 1 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L1START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L2START;         /*!< (@ 0x00000014) Limiter 2 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L2START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L3START;         /*!< (@ 0x00000018) Limiter 3 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L3START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L4START;         /*!< (@ 0x0000001C) Limiter 4 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L4START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L5START;         /*!< (@ 0x00000020) Limiter 5 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L5START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L6START;         /*!< (@ 0x00000024) Limiter 6 Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
+        } L6START_b;
+    };
+
+    union
+    {
+        __OM uint32_t L1XADD;          /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L1XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L2XADD;          /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L2XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L3XADD;          /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L3XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L4XADD;          /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L4XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L5XADD;          /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L5XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L6XADD;          /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
+        } L6XADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L1YADD;          /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L1YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L2YADD;          /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L2YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L3YADD;          /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L3YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L4YADD;          /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L4YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L5YADD;          /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L5YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L6YADD;          /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
+        } L6YADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t L1BAND;          /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register                    */
+
+        struct
+        {
+            __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
+        } L1BAND_b;
+    };
+
+    union
+    {
+        __OM uint32_t L2BAND;          /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register                    */
+
+        struct
+        {
+            __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
+        } L2BAND_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __OM uint32_t COLOR1;          /*!< (@ 0x00000064) Base Color Register                                        */
+
+        struct
+        {
+            __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1                                            */
+            __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1                                          */
+            __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1                                           */
+            __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF:
+                                        *   opaque)                                                                   */
+        } COLOR1_b;
+    };
+
+    union
+    {
+        __OM uint32_t COLOR2;          /*!< (@ 0x00000068) Secondary Color Register                                   */
+
+        struct
+        {
+            __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2                                            */
+            __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2                                          */
+            __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2                                           */
+            __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF:
+                                        *   opaque)                                                                   */
+        } COLOR2_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __OM uint32_t PATTERN;         /*!< (@ 0x00000074) Pattern Register                                           */
+
+        struct
+        {
+            __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern                                              */
+            uint32_t              : 24;
+        } PATTERN_b;
+    };
+
+    union
+    {
+        __OM uint32_t SIZE;            /*!< (@ 0x00000078) Bounding Box Dimension Register                            */
+
+        struct
+        {
+            __OM uint32_t SIZEX : 16;  /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
+                                        *   1024                                                                      */
+            __OM uint32_t SIZEY : 16;  /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
+                                        *   to 1024                                                                   */
+        } SIZE_b;
+    };
+
+    union
+    {
+        __OM uint32_t PITCH;           /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register             */
+
+        struct
+        {
+            __OM uint32_t PITCH : 16;  /*!< [15..0] pitch of the framebuffer. A negative width can be used
+                                        *   to render bottom-up instead of top-down                                   */
+            __OM uint32_t SSD : 16;    /*!< [31..16] Spanstore delay                                                  */
+        } PITCH_b;
+    };
+
+    union
+    {
+        __OM uint32_t ORIGIN;          /*!< (@ 0x00000080) Framebuffer Base Address Register                          */
+
+        struct
+        {
+            __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer                         */
+        } ORIGIN_b;
+    };
+    __IM uint32_t RESERVED3[3];
+
+    union
+    {
+        __OM uint32_t LUSTART;          /*!< (@ 0x00000090) U Limiter Start Value Register                             */
+
+        struct
+        {
+            __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value                                             */
+        } LUSTART_b;
+    };
+
+    union
+    {
+        __OM uint32_t LUXADD;          /*!< (@ 0x00000094) U Limiter X-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment                                        */
+        } LUXADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t LUYADD;          /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register                        */
+
+        struct
+        {
+            __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment                                        */
+        } LUYADD_b;
+    };
+
+    union
+    {
+        __OM uint32_t LVSTARTI;          /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register                */
+
+        struct
+        {
+            __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part                                */
+        } LVSTARTI_b;
+    };
+
+    union
+    {
+        __OM uint32_t LVSTARTF;          /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register             */
+
+        struct
+        {
+            __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part                             */
+            uint32_t               : 16;
+        } LVSTARTF_b;
+    };
+
+    union
+    {
+        __OM uint32_t LVXADDI;          /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register           */
+
+        struct
+        {
+            __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part                           */
+        } LVXADDI_b;
+    };
+
+    union
+    {
+        __OM uint32_t LVYADDI;          /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register           */
+
+        struct
+        {
+            __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part                           */
+        } LVYADDI_b;
+    };
+
+    union
+    {
+        __OM uint32_t LVYXADDF;         /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register              */
+
+        struct
+        {
+            __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part                              */
+            __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part                            */
+        } LVYXADDF_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __OM uint32_t TEXPITCH;          /*!< (@ 0x000000B4) Texels Per Texture Line Register                           */
+
+        struct
+        {
+            __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048                     */
+        } TEXPITCH_b;
+    };
+
+    union
+    {
+        __OM uint32_t TEXMASK;           /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register              */
+
+        struct
+        {
+            __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture
+                                          *   wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width
+                                          *   must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX
+                                          *   = 1):all widths up to 2048 are allowed.                                   */
+            __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height
+                                          *   - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY =
+                                          *   0): texture_height must be a power of 2In texture clamping
+                                          *   mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024
+                                          *   are allowed.                                                              */
+        } TEXMASK_b;
+    };
+
+    union
+    {
+        __OM uint32_t TEXORIGIN;          /*!< (@ 0x000000BC) Texture Base Address Register                              */
+
+        struct
+        {
+            __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address                                              */
+        } TEXORIGIN_b;
+    };
+
+    union
+    {
+        __OM uint32_t IRQCTL;              /*!< (@ 0x000000C0) Interrupt Control Register                                 */
+
+        struct
+        {
+            __OM uint32_t ENUMIRQEN   : 1; /*!< [0..0] ENUMIRQ interrupt mask enable                                      */
+            __OM uint32_t DLISTIRQEN  : 1; /*!< [1..1] DLISTIRQ interrupt mask enable                                     */
+            __OM uint32_t ENUMIRQCLR  : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ                                */
+            __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ                              */
+            __OM uint32_t BUSIRQEN    : 1; /*!< [4..4] BUSIRQ interrupt mask enable                                       */
+            __OM uint32_t BUSIRQCLR   : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ                                   */
+            uint32_t                  : 26;
+        } IRQCTL_b;
+    };
+
+    union
+    {
+        __OM uint32_t CACHECTL;          /*!< (@ 0x000000C4) Cache Control Register                                     */
+
+        struct
+        {
+            __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable                                           */
+            __OM uint32_t CFLUSHFX  : 1; /*!< [1..1] Flush framebuffer cache                                            */
+            __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable                                               */
+            __OM uint32_t CFLUSHTX  : 1; /*!< [3..3] Flush texture cache                                                */
+            uint32_t                : 28;
+        } CACHECTL_b;
+    };
+
+    union
+    {
+        __OM uint32_t DLISTSTART;          /*!< (@ 0x000000C8) Display List Start Address Register                        */
+
+        struct
+        {
+            __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address                                        */
+        } DLISTSTART_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERFCOUNT1;         /*!< (@ 0x000000CC) Performance Counter 1                                      */
+
+        struct
+        {
+            __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
+                                            *   = 0000 0000H.                                                             */
+        } PERFCOUNT1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PERFCOUNT2;         /*!< (@ 0x000000D0) Performance Counter 2                                      */
+
+        struct
+        {
+            __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
+                                            *   = 0000 0000H.                                                             */
+        } PERFCOUNT2_b;
+    };
+
+    union
+    {
+        __OM uint32_t PERFTRIGGER;           /*!< (@ 0x000000D4) Performance Counters Control Register                      */
+
+        struct
+        {
+            __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1
+                                              *   register.                                                                 */
+            __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2
+                                              *   register                                                                  */
+        } PERFTRIGGER_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __OM uint32_t TEXCLADDR;       /*!< (@ 0x000000DC) CLUT Start Address Register                                */
+
+        struct
+        {
+            __OM uint32_t CLADDR : 8;  /*!< [7..0] Texture CLUT start address for indexed texture format              */
+            uint32_t             : 24;
+        } TEXCLADDR_b;
+    };
+
+    union
+    {
+        __OM uint32_t TEXCLDATA;       /*!< (@ 0x000000E0) CLUT Data Register                                         */
+
+        struct
+        {
+            __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format                      */
+        } TEXCLDATA_b;
+    };
+
+    union
+    {
+        __OM uint32_t TEXCLOFFSET;      /*!< (@ 0x000000E4) CLUT Offset Register                                       */
+
+        struct
+        {
+            __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0]
+                                         *   is or'ed with the original index                                          */
+            uint32_t : 24;
+        } TEXCLOFFSET_b;
+    };
+
+    union
+    {
+        __OM uint32_t COLKEY;          /*!< (@ 0x000000E8) Color Key Register                                         */
+
+        struct
+        {
+            __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key                                          */
+            __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key                                        */
+            __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key                                         */
+            uint32_t              : 8;
+        } COLKEY_b;
+    };
+} R_DRW_Type;                          /*!< Size = 236 (0xec)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Data Transfer Controller (R_DTC)
+ */
+
+typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
+            uint8_t           : 3;
+        } DTCCR_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
+
+        struct
+        {
+            __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
+                                         *   in the lower-order 10 bits. These bits are fixed to 0.                    */
+        } DTCVBR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
+
+        struct
+        {
+            __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
+            uint8_t             : 7;
+        } DTCST_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
+                                        *   the vector number for the activating source when DTC transfer
+                                        *   is in progress.The value is only valid if DTC transfer
+                                        *   is in progress (the value of the ACT flag is 1)                           */
+            uint16_t          : 7;
+            __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
+        } DTCSTS_b;
+    };
+} R_DTC_Type;                          /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Event Link Controller (R_ELC)
+ */
+
+typedef struct                         /*!< (@ 0x40041000) R_ELC Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
+
+        struct
+        {
+            uint8_t             : 7;
+            __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
+        } ELCR_b;
+    };
+    __IM uint8_t            RESERVED;
+    __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
+    __IM uint16_t           RESERVED1[5];
+    __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
+} R_ELC_Type;                          /*!< Size = 108 (0x6c)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ETHERC0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet MAC Controller (R_ETHERC0)
+ */
+
+typedef struct                         /*!< (@ 0x40064100) R_ETHERC0 Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
+
+        struct
+        {
+            __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
+            __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
+            __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
+            __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
+            uint32_t             : 1;
+            __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
+            __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
+            uint32_t             : 2;
+            __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
+            uint32_t             : 2;
+            __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
+            uint32_t             : 3;
+            __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
+            __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
+            __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
+            __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
+            __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
+            uint32_t             : 11;
+        } ECMR_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
+
+        struct
+        {
+            __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
+                                        *   maximum frame length. The minimum value that can be set
+                                        *   is 1,518 bytes, and the maximum value that can be set is
+                                        *   2,048 bytes. Values that are less than 1,518 bytes are
+                                        *   regarded as 1,518 bytes, and values larger than 2,048 bytes
+                                        *   are regarded as 2,048 bytes.                                              */
+            uint32_t : 20;
+        } RFLR_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
+
+        struct
+        {
+            __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
+            __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
+            __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
+            uint32_t             : 1;
+            __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
+            __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
+            uint32_t             : 26;
+        } ECSR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
+
+        struct
+        {
+            __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
+            __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
+            __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
+            uint32_t               : 1;
+            __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
+            __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
+            uint32_t               : 26;
+        } ECSIPR_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
+
+        struct
+        {
+            __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
+                                        *   from the ETn_MDC pin to supply the management data clock
+                                        *   to the MII or RMII.                                                       */
+            __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
+            __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
+                                        *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
+                                        *   value is not output when the MMD bit is 0 (read).                         */
+            __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
+                                        *   of the ETn_MDIO pin. The write value should be 0.                         */
+            uint32_t : 28;
+        } PIR_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
+                                        *   by connecting the link signal output from the PHY-LSI to
+                                        *   the ETn_LINKSTA pin. For details on the polarity, refer
+                                        *   to the specifications of the connected PHY-LSI.                           */
+            uint32_t : 31;
+        } PSR_b;
+    };
+    __IM uint32_t RESERVED5[5];
+
+    union
+    {
+        __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
+                                        *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
+            uint32_t           : 12;
+        } RDMLR_b;
+    };
+    __IM uint32_t RESERVED6[3];
+
+    union
+    {
+        __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
+
+        struct
+        {
+            __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)'       */
+            uint32_t           : 27;
+        } IPGR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
+
+        struct
+        {
+            __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
+                                        *   of the pause_time parameter for a PAUSE frame that is automatically
+                                        *   transmitted. Transmission is not performed until the set
+                                        *   value multiplied by 512 bit time has elapsed.                             */
+            uint32_t : 16;
+        } APR_b;
+    };
+
+    union
+    {
+        __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
+
+        struct
+        {
+            __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
+                                        *   the pause_time parameter for a PAUSE frame that is manually
+                                        *   transmitted. Transmission is not performed until the set
+                                        *   value multiplied by 512 bit time has elapsed. The read
+                                        *   value is undefined.                                                       */
+            uint32_t : 16;
+        } MPR_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
+
+        struct
+        {
+            __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
+            uint32_t             : 24;
+        } RFCF_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
+
+        struct
+        {
+            __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
+            uint32_t              : 16;
+        } TPAUSER_b;
+    };
+    __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
+
+    union
+    {
+        __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
+
+        struct
+        {
+            __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
+            uint32_t           : 16;
+        } BCFRR_b;
+    };
+    __IM uint32_t RESERVED8[20];
+
+    union
+    {
+        __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
+
+        struct
+        {
+            __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
+                                        *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
+        } MAHR_b;
+    };
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
+
+        struct
+        {
+            __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
+                                        *   the lower 16 bits of the 48-bit MAC address.                              */
+            uint32_t : 16;
+        } MALR_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
+
+        struct
+        {
+            __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
+                                        *   is a counter indicating the number of frames that fail
+                                        *   to be retransmitted.                                                      */
+        } TROCR_b;
+    };
+    __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
+
+    union
+    {
+        __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
+
+        struct
+        {
+            __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
+                                        *   counter indicating the number of times a loss of carrier
+                                        *   is detected during frame transmission.                                    */
+        } LCCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
+
+        struct
+        {
+            __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
+                                        *   is a counter indicating the number of times a carrier is
+                                        *   not detected during preamble transmission.                                */
+        } CNDCR_b;
+    };
+    __IM uint32_t RESERVED11;
+
+    union
+    {
+        __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
+
+        struct
+        {
+            __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
+                                        *   is a counter indicating the number of received frames where
+                                        *   a CRC error has been detected.                                            */
+        } CEFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
+
+        struct
+        {
+            __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
+                                        *   is a counter indicating the number of times a frame receive
+                                        *   error has occurred.                                                       */
+        } FRECR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
+
+        struct
+        {
+            __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
+                                         *   is a counter indicating the number of times a short frame
+                                         *   that is shorter than 64 bytes has been received.                          */
+        } TSFRCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
+
+        struct
+        {
+            __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
+                                         *   is a counter indicating the number of times a long frame
+                                         *   that is longer than the RFLR register value has been received.            */
+        } TLFRCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
+
+        struct
+        {
+            __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
+                                        *   register is a counter indicating the number of times a
+                                        *   frame has been received with the alignment error (frame
+                                        *   is not an integral number of octets).                                     */
+        } RFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
+
+        struct
+        {
+            __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
+                                        *   MAFCR register is a counter indicating the number of times
+                                        *   a frame where the multicast address is set has been received.             */
+        } MAFCR_b;
+    };
+} R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                      R_ETHERC_EDMAC                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
+ */
+
+typedef struct                         /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure                                   */
+{
+    union
+    {
+        __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
+
+        struct
+        {
+            __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
+            uint32_t          : 3;
+            __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
+            __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
+                                        *   applies to data for the transmit/receive buffer. It does
+                                        *   not apply to transmit/receive descriptors and registers.                  */
+            uint32_t : 25;
+        } EDMR_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
+
+        struct
+        {
+            __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
+            uint32_t         : 31;
+        } EDTRR_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
+
+        struct
+        {
+            __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
+            uint32_t          : 31;
+        } EDRRR_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
+
+        struct
+        {
+            __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
+                                        *   set. Set the start address according to the descriptor
+                                        *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
+                                        *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
+                                        *   boundary: Lower 6 bits = 000000b                                          */
+        } TDLAR_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
+
+        struct
+        {
+            __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
+                                        *   set. Set the start address according to the descriptor
+                                        *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
+                                        *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
+                                        *   boundary: Lower 6 bits = 000000b                                          */
+        } RDLAR_b;
+    };
+    __IM uint32_t RESERVED4;
+
+    union
+    {
+        __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
+
+        struct
+        {
+            __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
+            __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
+            __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
+            __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
+            __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
+            uint32_t            : 2;
+            __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
+            __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
+            __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
+            __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
+            __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
+            uint32_t            : 4;
+            __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
+            __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
+            __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
+            __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
+            __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
+            __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
+            __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
+                                        *   in the ETHERCn.ECSR register is cleared, the ECI flag is
+                                        *   also cleared.                                                             */
+            __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
+            __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
+            __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
+            __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
+            uint32_t             : 3;
+            __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
+            uint32_t             : 1;
+        } EESR_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
+
+        struct
+        {
+            __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
+            __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
+            __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
+            __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
+            __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
+            uint32_t               : 2;
+            __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
+            __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
+            __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
+            __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
+            __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
+            uint32_t               : 4;
+            __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
+            __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
+            __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
+            __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
+            __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
+            __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
+            __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
+            __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
+            __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
+            __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
+            __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
+            uint32_t               : 3;
+            __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
+            uint32_t               : 1;
+        } EESIPR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t              : 4;
+            __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
+            uint32_t              : 2;
+            __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
+            uint32_t              : 24;
+        } TRSCER_b;
+    };
+    __IM uint32_t RESERVED7;
+
+    union
+    {
+        __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
+
+        struct
+        {
+            __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
+                                        *   frames that are discarded and not transferred to the receive
+                                        *   buffer during reception.                                                  */
+            uint32_t : 16;
+        } RMFCR_b;
+    };
+    __IM uint32_t RESERVED8;
+
+    union
+    {
+        __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
+
+        struct
+        {
+            __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
+                                        *   the set value multiplied by 4. Example: 00Dh: 52 bytes
+                                        *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
+            uint32_t : 21;
+        } TFTR_b;
+    };
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
+
+        struct
+        {
+            __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
+            uint32_t           : 3;
+            __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
+            uint32_t           : 19;
+        } FDR_b;
+    };
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
+            uint32_t           : 31;
+        } RMCR_b;
+    };
+    __IM uint32_t RESERVED11[2];
+
+    union
+    {
+        __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
+
+        struct
+        {
+            __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
+                                        *   many times the transmit FIFO has underflowed. The counter
+                                        *   stops when the counter value reaches FFFFh.                               */
+            uint32_t : 16;
+        } TFUCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
+
+        struct
+        {
+            __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
+                                        *   times the receive FIFO has overflowed. The counter stops
+                                        *   when the counter value reaches FFFFh.                                     */
+            uint32_t : 16;
+        } RFOCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
+
+        struct
+        {
+            __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
+            uint32_t           : 31;
+        } IOSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
+                                        *   bytes of data is stored in the receive FIFO.)                             */
+            uint32_t            : 13;
+            __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
+                                        *   receive frames have been stored in the receive FIFO.)                     */
+            uint32_t : 13;
+        } FCFTR_b;
+    };
+    __IM uint32_t RESERVED12;
+
+    union
+    {
+        __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
+
+        struct
+        {
+            __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
+            uint32_t            : 10;
+            __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
+            uint32_t            : 14;
+        } RPADIR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
+
+        struct
+        {
+            __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
+                                        *   the mode selected by the TIM bit to notify an interrupt.                  */
+            uint32_t           : 3;
+            __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
+            uint32_t           : 27;
+        } TRIMD_b;
+    };
+    __IM uint32_t RESERVED13[18];
+
+    union
+    {
+        __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
+
+        struct
+        {
+            __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
+                                        *   indicates the last address that the EDMAC has written data
+                                        *   to when writing to the receive buffer.Refer to the address
+                                        *   indicated by the RBWAR register to recognize which address
+                                        *   in the receive buffer the EDMAC is writing data to. Note
+                                        *   that the address that the EDMAC is outputting to the receive
+                                        *   buffer may not match the read value of the RBWAR register
+                                        *   during data reception.                                                    */
+        } RBWAR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
+
+        struct
+        {
+            __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
+                                        *   indicates the start address of the last fetched receive
+                                        *   descriptor when the EDMAC fetches descriptor information
+                                        *   from the receive descriptor.Refer to the address indicated
+                                        *   by the RDFAR register to recognize which receive descriptor
+                                        *   information the EDMAC is using for the current processing.
+                                        *   Note that the address of the receive descriptor that the
+                                        *   EDMAC fetches may not match the read value of the RDFAR
+                                        *   register during data reception.                                           */
+        } RDFAR_b;
+    };
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
+
+        struct
+        {
+            __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
+                                        *   indicates the last address that the EDMAC has read data
+                                        *   from when reading data from the transmit buffer.Refer to
+                                        *   the address indicated by the TBRAR register to recognize
+                                        *   which address in the transmit buffer the EDMAC is reading
+                                        *   from. Note that the address that the EDMAC is outputting
+                                        *   to the transmit buffer may not match the read value of
+                                        *   the TBRAR register.                                                       */
+        } TBRAR_b;
+    };
+
+    union
+    {
+        __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
+
+        struct
+        {
+            __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
+                                        *   register indicates the start address of the last fetched
+                                        *   transmit descriptor when the EDMAC fetches descriptor information
+                                        *   from the transmit descriptor.Refer to the address indicated
+                                        *   by the TDFAR register to recognize which transmit descriptor
+                                        *   information the EDMAC is using for the current processing.
+                                        *   Note that the address of the transmit descriptor that the
+                                        *   EDMAC fetches may not match the read value of the TDFAR
+                                        *   register.                                                                 */
+        } TDFAR_b;
+    };
+} R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                      R_ETHERC_EPTPC                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet PTP Controller (R_ETHERC_EPTPC)
+ */
+
+typedef struct                         /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure                                   */
+{
+    union
+    {
+        __IOM uint32_t SYSR;           /*!< (@ 0x00000000) SYNFP Status Register                                      */
+
+        struct
+        {
+            __IOM uint32_t OFMUD  : 1; /*!< [0..0] offsetFromMaster Value Update Flag                                 */
+            __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag             */
+            __IOM uint32_t MPDUD  : 1; /*!< [2..2] meanPathDelay Value Update Flag                                    */
+            uint32_t              : 1;
+            __IOM uint32_t DRPTO  : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag            */
+            __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag                 */
+            __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag                   */
+            uint32_t              : 5;
+            __IOM uint32_t RECLP  : 1; /*!< [12..12] Loop Reception Detection Flag                                    */
+            uint32_t              : 1;
+            __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag                   */
+            uint32_t              : 1;
+            __IOM uint32_t RESDN  : 1; /*!< [16..16] Response Stop Completion Detection Flag                          */
+            __IOM uint32_t GENDN  : 1; /*!< [17..17] Generation Stop Completion Detection Flag                        */
+            uint32_t              : 14;
+        } SYSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYIPR;          /*!< (@ 0x00000004) SYNFP Status Notification Permission Register              */
+
+        struct
+        {
+            __IOM uint32_t OFMUD  : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission                          */
+            __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission                         */
+            __IOM uint32_t MPDUD  : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission                          */
+            uint32_t              : 1;
+            __IOM uint32_t DRPTO  : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission                          */
+            __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission                         */
+            __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission                         */
+            uint32_t              : 5;
+            __IOM uint32_t RECLP  : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission                        */
+            uint32_t              : 1;
+            __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission                       */
+            uint32_t              : 1;
+            __IOM uint32_t RESDN  : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission                        */
+            __IOM uint32_t GENDN  : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission                        */
+            uint32_t              : 14;
+        } SYIPR_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t SYMACRU;          /*!< (@ 0x00000010) SYNFP MAC Address Registers                                */
+
+        struct
+        {
+            __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
+                                          *   bits of the local MAC address.                                            */
+            uint32_t : 8;
+        } SYMACRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYMACRL;          /*!< (@ 0x00000014) SYNFP MAC Address Registers                                */
+
+        struct
+        {
+            __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
+                                          *   of the local MAC address.                                                 */
+            uint32_t : 8;
+        } SYMACRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYLLCCTLR;      /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register                               */
+
+        struct
+        {
+            __IOM uint32_t CTL : 8;    /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the
+                                        *   control field in the LLC sublayer when generating IEEE802.3
+                                        *   frames.                                                                   */
+            uint32_t : 24;
+        } SYLLCCTLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYIPADDRR;          /*!< (@ 0x0000001C) SYNFP Local IP Address Register                            */
+
+        struct
+        {
+            __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address.             */
+        } SYIPADDRR_b;
+    };
+    __IM uint32_t RESERVED1[8];
+
+    union
+    {
+        __IOM uint32_t SYSPVRR;        /*!< (@ 0x00000040) SYNFP Specification Version Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t VER : 4;    /*!< [3..0] versionPTP Field ValueThese bits are used to set the
+                                        *   versionPTP field value of the PTP v2 header.When a message
+                                        *   is received, this value is compared with the versionPTP
+                                        *   field of the received frame.In generating messages, the
+                                        *   value is used for the versionPTP field of the frame for
+                                        *   transmission.Set these bits to 0010b (PTP v2).                            */
+            __IOM uint32_t TRSP : 4;   /*!< [7..4] transportSpecific Field ValueThese bits are used to set
+                                        *   the transportSpecific field value of the PTP v2 header.When
+                                        *   a message is received, this value is compared with the
+                                        *   transportSpecific field of the received frame.In generating
+                                        *   messages, the value is used for the transportSpecific field
+                                        *   of the frame for transmission.Set these bits to 0000b (IEEE
+                                        *   1588).                                                                    */
+            uint32_t : 24;
+        } SYSPVRR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYDOMR;         /*!< (@ 0x00000044) SYNFP Domain Number Setting Register                       */
+
+        struct
+        {
+            __IOM uint32_t DNUM : 8;   /*!< [7..0] domainNumber Field Value SettingThese bits are used to
+                                        *   set the domainNumber field value of the PTP v2 header.When
+                                        *   a message is received, this value is compared with the
+                                        *   domainNumber field of the received frame as a condition
+                                        *   for PTP reception processing.In generating messages, the
+                                        *   value is used for the domainNumber field of the frame for
+                                        *   transmission.                                                             */
+            uint32_t : 24;
+        } SYDOMR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t ANFR;           /*!< (@ 0x00000050) Announce Message Flag Field Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t FLAG0 : 1;  /*!< [0..0] leap61This bit is used to set the logical value of the
+                                        *   leap61 member of timePropertiesDS.                                        */
+            __IOM uint32_t FLAG1 : 1;  /*!< [1..1] leap59This bit is used to set the logical value of the
+                                        *   leap59 member of timePropertiesDS.                                        */
+            __IOM uint32_t FLAG2 : 1;  /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical
+                                        *   value of the currentUtcOffsetValid member of timePropertiesDS.            */
+            __IOM uint32_t FLAG3 : 1;  /*!< [3..3] ptpTimescaleThis bit is used to set the logical value
+                                        *   of the ptpTimescale member of timePropertiesDS.                           */
+            __IOM uint32_t FLAG4 : 1;  /*!< [4..4] timeTraceableThis bit is used to set the logical value
+                                        *   of the timeTraceable member of timePropertiesDS.                          */
+            __IOM uint32_t FLAG5 : 1;  /*!< [5..5] frequencyTraceableThis bit is used to set the logical
+                                        *   value of the frequencyTraceable member of timePropertiesDS.               */
+            uint32_t              : 2;
+            __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
+            uint32_t              : 1;
+            __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
+            uint32_t              : 2;
+            __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
+            __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
+            uint32_t              : 17;
+        } ANFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNFR;          /*!< (@ 0x00000054) Sync Message Flag Field Setting Register                   */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
+            __IOM uint32_t FLAG9  : 1; /*!< [9..9] twoStepFlag                                                        */
+            __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
+            uint32_t              : 2;
+            __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
+            __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
+            uint32_t              : 17;
+        } SYNFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DYRQFR;         /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register              */
+
+        struct
+        {
+            uint32_t              : 10;
+            __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
+            uint32_t              : 2;
+            __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
+            __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
+            uint32_t              : 17;
+        } DYRQFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DYRPFR;         /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register             */
+
+        struct
+        {
+            uint32_t              : 8;
+            __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
+            __IOM uint32_t FLAG9  : 1; /*!< [9..9] woStepFlag                                                         */
+            __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
+            uint32_t              : 2;
+            __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
+            __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
+            uint32_t              : 17;
+        } DYRPFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYCIDRU;          /*!< (@ 0x00000060) SYNFP Local Clock ID Registers                             */
+
+        struct
+        {
+            __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                          *   bits of the clock-ID of your port.                                        */
+        } SYCIDRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYCIDRL;          /*!< (@ 0x00000064) SYNFP Local Clock ID Registers                             */
+
+        struct
+        {
+            __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                          *   of the clock-ID of your port.                                             */
+        } SYCIDRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYPNUMR;        /*!< (@ 0x00000068) SYNFP Local Port Number Register                           */
+
+        struct
+        {
+            __IOM uint32_t PNUM : 16;  /*!< [15..0] Local Port Number SettingThese bits hold the setting
+                                        *   for the port number of the local port.                                    */
+            uint32_t : 16;
+        } SYPNUMR_b;
+    };
+    __IM uint32_t RESERVED3[5];
+
+    union
+    {
+        __OM uint32_t SYRVLDR;         /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register               */
+
+        struct
+        {
+            __OM uint32_t BMUP : 1;    /*!< [0..0] BMC Update                                                         */
+            __OM uint32_t STUP : 1;    /*!< [1..1] State Update                                                       */
+            __OM uint32_t ANUP : 1;    /*!< [2..2] Announce Message Generation Information Update                     */
+            uint32_t           : 29;
+        } SYRVLDR_b;
+    };
+    __IM uint32_t RESERVED4[3];
+
+    union
+    {
+        __IOM uint32_t SYRFL1R;        /*!< (@ 0x00000090) SYNFP Reception Filter Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t ANCE0  : 1; /*!< [0..0] Announce Message Processing                                        */
+            __IOM uint32_t ANCE1  : 1; /*!< [1..1] Announce Message Processing                                        */
+            uint32_t              : 2;
+            __IOM uint32_t SYNC0  : 1; /*!< [4..4] Sync Message Processing                                            */
+            __IOM uint32_t SYNC1  : 1; /*!< [5..5] Sync Message Processing                                            */
+            __IOM uint32_t SYNC2  : 1; /*!< [6..6] Sync Message Processing                                            */
+            uint32_t              : 1;
+            __IOM uint32_t FUP0   : 1; /*!< [8..8] Follow_Up Message Processing                                       */
+            __IOM uint32_t FUP1   : 1; /*!< [9..9] Follow_Up Message Processing                                       */
+            __IOM uint32_t FUP2   : 1; /*!< [10..10] Follow_Up Message Processing                                     */
+            uint32_t              : 1;
+            __IOM uint32_t DRQ0   : 1; /*!< [12..12] Delay_Req Message Processing                                     */
+            __IOM uint32_t DRQ1   : 1; /*!< [13..13] Delay_Req Message Processing                                     */
+            __IOM uint32_t DRQ2   : 1; /*!< [14..14] Delay_Req Message Processing                                     */
+            uint32_t              : 1;
+            __IOM uint32_t DRP0   : 1; /*!< [16..16] Delay_Resp Message Processing                                    */
+            __IOM uint32_t DRP1   : 1; /*!< [17..17] Delay_Resp Message Processing                                    */
+            __IOM uint32_t DRP2   : 1; /*!< [18..18] Delay_Resp Message Processing                                    */
+            uint32_t              : 1;
+            __IOM uint32_t PDRQ0  : 1; /*!< [20..20] Pdelay_Req Message Processing                                    */
+            __IOM uint32_t PDRQ1  : 1; /*!< [21..21] Pdelay_Req Message Processing                                    */
+            __IOM uint32_t PDRQ2  : 1; /*!< [22..22] Pdelay_Req Message Processing                                    */
+            uint32_t              : 1;
+            __IOM uint32_t PDRP0  : 1; /*!< [24..24] Pdelay_Resp Message Processing                                   */
+            __IOM uint32_t PDRP1  : 1; /*!< [25..25] Pdelay_Resp Message Processing                                   */
+            __IOM uint32_t PDRP2  : 1; /*!< [26..26] Pdelay_Resp Message Processing                                   */
+            uint32_t              : 1;
+            __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing                         */
+            __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing                         */
+            __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing                         */
+            uint32_t              : 1;
+        } SYRFL1R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYRFL2R;        /*!< (@ 0x00000094) SYNFP Reception Filter Register 2                          */
+
+        struct
+        {
+            __IOM uint32_t MAN0 : 1;   /*!< [0..0] Management Message Processing Setting                              */
+            __IOM uint32_t MAN1 : 1;   /*!< [1..1] Management Message Processing Setting                              */
+            uint32_t            : 2;
+            __IOM uint32_t SIG0 : 1;   /*!< [4..4] Signaling Message Processing Setting                               */
+            __IOM uint32_t SIG1 : 1;   /*!< [5..5] Signaling Message Processing Setting                               */
+            uint32_t            : 22;
+            __IOM uint32_t ILL0 : 1;   /*!< [28..28] Illegal Message Processing Setting                               */
+            __IOM uint32_t ILL1 : 1;   /*!< [29..29] Illegal Message Processing Setting                               */
+            uint32_t            : 2;
+        } SYRFL2R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYTRENR;        /*!< (@ 0x00000098) SYNFP Transmission Enable Register                         */
+
+        struct
+        {
+            __IOM uint32_t ANCE : 1;   /*!< [0..0] Announce Message Transmission Enable                               */
+            uint32_t            : 3;
+            __IOM uint32_t SYNC : 1;   /*!< [4..4] Sync Message Transmission Enable                                   */
+            uint32_t            : 3;
+            __IOM uint32_t DRQ  : 1;   /*!< [8..8] Delay_Req Message Transmission Enable                              */
+            uint32_t            : 3;
+            __IOM uint32_t PDRQ : 1;   /*!< [12..12] Pdelay_Req Message Transmission Enable                           */
+            uint32_t            : 19;
+        } SYTRENR_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint32_t MTCIDU;          /*!< (@ 0x000000A0) Master Clock ID Registers                                  */
+
+        struct
+        {
+            __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                         *   bits of the clock-ID of the master clock.                                 */
+        } MTCIDU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTCIDL;          /*!< (@ 0x000000A4) Master Clock ID Registers                                  */
+
+        struct
+        {
+            __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                         *   of the clock-ID of the master clock.                                      */
+        } MTCIDL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MTPID;          /*!< (@ 0x000000A8) Master clock port number register                          */
+
+        struct
+        {
+            __IOM uint32_t PNUM : 16;  /*!< [15..0] Master Clock Port Number SettingThese bits hold the
+                                        *   setting for the port number of the master clock.                          */
+            uint32_t : 16;
+        } MTPID_b;
+    };
+    __IM uint32_t RESERVED6[5];
+
+    union
+    {
+        __IOM uint32_t SYTLIR;         /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register               */
+
+        struct
+        {
+            __IOM uint32_t ANCE : 8;   /*!< [7..0] Announce Message Transmission Interval SettingThese bits
+                                        *   set the interval for the transmission of Announce messages.               */
+            __IOM uint32_t SYNC : 8;   /*!< [15..8] Sync Message Transmission Interval SettingThese bits
+                                        *   set the interval for the transmission of Sync messages.
+                                        *   The setting is also placed in the logMessageInterval field
+                                        *   of transmitted Sync messages.                                             */
+            __IOM uint32_t DREQ : 8;   /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req
+                                        *   Transmission Interval SettingThe bits set the average interval
+                                        *   for the transmission of Delay_Req messages and the interval
+                                        *   for the transmission of Pdelay_Req messages.The setting
+                                        *   is also placed in the logMessageInterval field of Delay_Resp
+                                        *   messages.                                                                 */
+            uint32_t : 8;
+        } SYTLIR_b;
+    };
+
+    union
+    {
+        __IM uint32_t SYRLIR;          /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IM uint32_t ANCE : 8;    /*!< [7..0] Announce Message logMessageInterval Field IndicationThese
+                                        *   bits indicate the logMessageInterval field value of a received
+                                        *   Announce message.                                                         */
+            __IM uint32_t SYNC : 8;    /*!< [15..8] Sync Message logMessageInterval Field IndicationThese
+                                        *   bits indicate the logMessageInterval field value of a received
+                                        *   Sync message.                                                             */
+            __IM uint32_t DRESP : 8;   /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese
+                                        *   bits indicate the logMessageInterval field value of a received
+                                        *   Delay_Resp message.                                                       */
+            uint32_t : 8;
+        } SYRLIR_b;
+    };
+
+    union
+    {
+        __IM uint32_t OFMRU;           /*!< (@ 0x000000C8) offsetFromMaster Value Registers                           */
+
+        struct
+        {
+            __IM uint32_t OFMRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
+                                        *   calculated offsetFromMaster value.                                        */
+        } OFMRU_b;
+    };
+
+    union
+    {
+        __IM uint32_t OFMRL;           /*!< (@ 0x000000CC) offsetFromMaster Value Registers                           */
+
+        struct
+        {
+            __IM uint32_t OFMRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
+                                        *   offsetFromMaster value.                                                   */
+        } OFMRL_b;
+    };
+
+    union
+    {
+        __IM uint32_t MPDRU;           /*!< (@ 0x000000D0) meanPathDelay Value Registers                              */
+
+        struct
+        {
+            __IM uint32_t MPDRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
+                                        *   calculated meanPathDelay value.                                           */
+        } MPDRU_b;
+    };
+
+    union
+    {
+        __IM uint32_t MPDRL;           /*!< (@ 0x000000D4) meanPathDelay Value Registers                              */
+
+        struct
+        {
+            __IM uint32_t MPDRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
+                                        *   meanPathDelay value.                                                      */
+        } MPDRL_b;
+    };
+    __IM uint32_t RESERVED7[2];
+
+    union
+    {
+        __IOM uint32_t GMPR;           /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register                 */
+
+        struct
+        {
+            __IOM uint32_t GMPR2 : 8;  /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are
+                                        *   used to set the value of the grandmasterPriority2 fields
+                                        *   of Announce messages.                                                     */
+            uint32_t             : 8;
+            __IOM uint32_t GMPR1 : 8;  /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits
+                                        *   are used to set the value of the grandmasterPriority1 fields
+                                        *   of Announce messages.                                                     */
+            uint32_t : 8;
+        } GMPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GMCQR;          /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register             */
+
+        struct
+        {
+            __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality
+                                        *   fields of Announce messages. The correspondence between
+                                        *   bits and the grandmasterClockQuality fields is as listed
+                                        *   below.b31 to b24: clockClassb23 to b16: clockAccuracyb15
+                                        *   to b0: offsetScaledLogVariance                                            */
+        } GMCQR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GMIDRU;          /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers                */
+
+        struct
+        {
+            __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                         *   bits of the value of the grandmasterIdentity fields of
+                                         *   Announce messages.                                                        */
+        } GMIDRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GMIDRL;          /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers                */
+
+        struct
+        {
+            __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                         *   of the value of the grandmasterIdentity fields of Announce
+                                         *   messages.                                                                 */
+        } GMIDRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t CUOTSR;         /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register         */
+
+        struct
+        {
+            __IOM uint32_t TSRC : 8;   /*!< [7..0] timeSource Field SettingThese bits set the value of the
+                                        *   timeSource fields of Announce messages.                                   */
+            uint32_t            : 8;
+            __IOM uint32_t CUTO : 16;  /*!< [31..16] currentUtcOffset Field SettingThese bits set the value
+                                        *   of the currentUtcOffset fields of Announce messages.                      */
+        } CUOTSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SRR;            /*!< (@ 0x000000F4) stepsRemoved Field Setting Register                        */
+
+        struct
+        {
+            __IOM uint32_t SRMV : 16;  /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value
+                                        *   of the stepsRemoved fields of Announce messages.                          */
+            uint32_t : 16;
+        } SRR_b;
+    };
+    __IM uint32_t RESERVED8[2];
+
+    union
+    {
+        __IOM uint32_t PPMACRU;          /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting
+                                          *                  Registers                                                  */
+
+        struct
+        {
+            __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
+                                          *   bits of the destination MAC address for PTP-primary messages.             */
+            uint32_t : 8;
+        } PPMACRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PPMACRL;          /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting
+                                          *                  Registers                                                  */
+
+        struct
+        {
+            __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
+                                          *   of the destination MAC address for PTP-primary messages.                  */
+            uint32_t : 8;
+        } PPMACRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PDMACRU;          /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers           */
+
+        struct
+        {
+            __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
+                                          *   bits of the destination MAC address for PTP-pdelay messages.              */
+            uint32_t : 8;
+        } PDMACRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PDMACRL;          /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers           */
+
+        struct
+        {
+            __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
+                                          *   of the destination MAC address for PTP-pdelay messages.                   */
+            uint32_t : 8;
+        } PDMACRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PETYPER;        /*!< (@ 0x00000110) PTP Message EtherType Setting Register                     */
+
+        struct
+        {
+            __IOM uint32_t TYPE : 16;  /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the
+                                        *   setting for the EtherType field value for frames in the
+                                        *   Ethernet II format.                                                       */
+            uint32_t : 16;
+        } PETYPER_b;
+    };
+    __IM uint32_t RESERVED9[3];
+
+    union
+    {
+        __IOM uint32_t PPIPR;          /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
+                                        *   for PTPprimary messages.                                                  */
+        } PPIPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PDIPR;          /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
+                                        *   for PTPpdelay messages.                                                   */
+        } PDIPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PETOSR;         /*!< (@ 0x00000128) PTP Event Message TOS Setting Register                     */
+
+        struct
+        {
+            __IOM uint32_t EVTO : 8;   /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold
+                                        *   the setting for the value of the TOS field within the IPv4
+                                        *   headers of PTP event messages.                                            */
+            uint32_t : 24;
+        } PETOSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PGTOSR;         /*!< (@ 0x0000012C) PTP general Message TOS Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t GETO : 8;   /*!< [7..0] PTP general Message TOS Field Value SettingThese bits
+                                        *   hold the setting for the value of the TOS field within
+                                        *   the IPv4 headers of PTP general messages.                                 */
+            uint32_t : 24;
+        } PGTOSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PPTTLR;         /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t PRTL : 8;   /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits
+                                        *   hold the setting for the value of the TTL field within
+                                        *   the IPv4 headers of PTP-primary messages.                                 */
+            uint32_t : 24;
+        } PPTTLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PDTTLR;         /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t PDTL : 8;   /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the
+                                        *   setting for the value of the TTL field within the IPv4
+                                        *   headers of PTP-pdelay messages.                                           */
+            uint32_t : 24;
+        } PDTTLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PEUDPR;         /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number
+                                        *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese
+                                        *   bits hold the setting for the value of the destination
+                                        *   port number field within the UDP headers of PTP event messages.           */
+            uint32_t : 16;
+        } PEUDPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PGUDPR;         /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number
+                                        *                  Setting Register                                           */
+
+        struct
+        {
+            __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits
+                                        *   hold the setting for the value of the destination port
+                                        *   number field within the UDP headers of PTP general messages.              */
+            uint32_t : 16;
+        } PGUDPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FFLTR;          /*!< (@ 0x00000140) Frame Reception Filter Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t SEL : 1;    /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these
+                                        *   bits is only effective when EXTPRM=0, ENB=1and RPT=1.                     */
+            __IOM uint32_t PRT : 1;    /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits
+                                        *   is only effective when EXTPRM=0 and ENB=1.                                */
+            __IOM uint32_t ENB : 1;    /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits
+                                        *   is only effective when EXTPRM=0.                                          */
+            uint32_t              : 13;
+            __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting                                 */
+            uint32_t              : 15;
+        } FFLTR_b;
+    };
+    __IM uint32_t RESERVED10[31];
+
+    union
+    {
+        __IOM uint32_t DASYMRU;          /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers                         */
+
+        struct
+        {
+            __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
+                                          *   bits of the asymmetric delay value.                                       */
+            uint32_t : 16;
+        } DASYMRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DASYMRL;          /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers                         */
+
+        struct
+        {
+            __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                          *   of the asymmetric delay value.                                            */
+        } DASYMRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TSLATR;         /*!< (@ 0x000001C8) Timestamp Latency Setting Register                         */
+
+        struct
+        {
+            __IOM uint32_t EGP : 16;   /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold
+                                        *   the setting for the time stamp latency (ns) for the input
+                                        *   ports.                                                                    */
+            __IOM uint32_t INGP : 16;  /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold
+                                        *   the setting for the time stamp latency (ns) for the output
+                                        *   ports.                                                                    */
+        } TSLATR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYCONFR;        /*!< (@ 0x000001CC) SYNFP Operation Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t TCYC : 8;   /*!< [7..0] PTP Message Transmission Interval SettingThese bits are
+                                        *   used to set the time from the completion of one transmission
+                                        *   to the start of the next in cycles of the transmission
+                                        *   clock. A value n in these bits means that a transmission
+                                        *   interval of n cycles will be secured.No interval is secured
+                                        *   if the setting is 00h.We recommend the setting 28h (40
+                                        *   cycles).                                                                  */
+            uint32_t              : 4;
+            __IOM uint32_t SBDIS  : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable             */
+            uint32_t              : 3;
+            __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable                      */
+            uint32_t              : 3;
+            __IOM uint32_t TCMOD  : 1; /*!< [20..20] TC Mode Setting                                                  */
+            uint32_t              : 11;
+        } SYCONFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYFORMR;        /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register                        */
+
+        struct
+        {
+            __IOM uint32_t FORM0 : 1;  /*!< [0..0] Ethernet/UDP Encapsulation                                         */
+            __IOM uint32_t FORM1 : 1;  /*!< [1..1] Ethernet Frame Format Setting                                      */
+            uint32_t             : 30;
+        } SYFORMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t RSTOUTR;          /*!< (@ 0x000001D4) Response Message Reception Timeout Register                */
+
+        struct
+        {
+            __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response
+                                          *   message not being received within n x 1024 (ns), where
+                                          *   n is the setting, is judged to represent a timeout.                       */
+        } RSTOUTR_b;
+    };
+} R_ETHERC_EPTPC_Type;                   /*!< Size = 472 (0x1d8)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG)
+ */
+
+typedef struct                         /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure                               */
+{
+    union
+    {
+        __IOM uint32_t PTRSTR;         /*!< (@ 0x00000000) EPTPC Reset Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RESET : 1;  /*!< [0..0] EPTPC Software Reset                                               */
+            uint32_t             : 31;
+        } PTRSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STCSELR;         /*!< (@ 0x00000004) STCA Clock Select Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division                                     */
+            uint32_t               : 5;
+            __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select                                                 */
+            uint32_t               : 21;
+        } STCSELR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t BYPASS;          /*!< (@ 0x00000008) Bypass 1588 module Register                                */
+
+        struct
+        {
+            __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch                                   */
+            uint32_t               : 15;
+            __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch                                 */
+            uint32_t               : 15;
+        } BYPASS_b;
+    };
+} R_ETHERC_EPTPC_CFG_Type;              /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON)
+ */
+
+typedef struct                         /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure                            */
+{
+    union
+    {
+        __IOM uint32_t MIESR;          /*!< (@ 0x00000000) MINT Interrupt Source Status Register                      */
+
+        struct
+        {
+            __IM uint32_t ST    : 1;   /*!< [0..0] STCA Status Flag                                                   */
+            __IM uint32_t SY0   : 1;   /*!< [1..1] SYNFP0 Status Flag                                                 */
+            __IM uint32_t SY1   : 1;   /*!< [2..2] SYNFP1 Status Flag                                                 */
+            __IM uint32_t PRC   : 1;   /*!< [3..3] PRC-TC Status Flag                                                 */
+            uint32_t            : 12;
+            __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag                  */
+            __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag                  */
+            __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag                  */
+            __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag                  */
+            __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag                  */
+            __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag                  */
+            uint32_t            : 10;
+        } MIESR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MIEIPR;         /*!< (@ 0x00000004) MINT Interrupt Request Permission Register                 */
+
+        struct
+        {
+            __IOM uint32_t ST   : 1;   /*!< [0..0] STCA Status Interrupt Request Permission                           */
+            __IOM uint32_t SY0  : 1;   /*!< [1..1] SYNFP0 Status Interrupt Request Permission                         */
+            __IOM uint32_t SY1  : 1;   /*!< [2..2] SYNFP1 Status Interrupt Request Permission                         */
+            __IOM uint32_t PRC  : 1;   /*!< [3..3] PRC-TC Status Interrupt Request Permission                         */
+            uint32_t            : 12;
+            __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt
+                                        *   Request Permission                                                        */
+            uint32_t : 10;
+        } MIEIPR_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t ELIPPR;         /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t CYCP0 : 1;  /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCP1 : 1;  /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCP2 : 1;  /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCP3 : 1;  /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCP4 : 1;  /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCP5 : 1;  /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output
+                                        *   Enable                                                                    */
+            uint32_t             : 2;
+            __IOM uint32_t CYCN0 : 1;  /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCN1 : 1;  /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCN2 : 1;  /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCN3 : 1;  /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCN4 : 1;  /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            __IOM uint32_t CYCN5 : 1;  /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output
+                                        *   Enable                                                                    */
+            uint32_t            : 2;
+            __IOM uint32_t PLSP : 1;   /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt
+                                        *   Request Permission                                                        */
+            uint32_t            : 7;
+            __IOM uint32_t PLSN : 1;   /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt
+                                        *   Request Permission                                                        */
+            uint32_t : 7;
+        } ELIPPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ELIPACR;        /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic
+                                        *                  Clearing Register                                          */
+
+        struct
+        {
+            __IOM uint32_t CYCP0 : 1;  /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCP1 : 1;  /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCP2 : 1;  /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCP3 : 1;  /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCP4 : 1;  /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCP5 : 1;  /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing                                */
+            uint32_t             : 2;
+            __IOM uint32_t CYCN0 : 1;  /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCN1 : 1;  /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing                                */
+            __IOM uint32_t CYCN2 : 1;  /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing                              */
+            __IOM uint32_t CYCN3 : 1;  /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing                              */
+            __IOM uint32_t CYCN4 : 1;  /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing                              */
+            __IOM uint32_t CYCN5 : 1;  /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing                              */
+            uint32_t             : 2;
+            __IOM uint32_t PLSP  : 1;  /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing                               */
+            uint32_t             : 7;
+            __IOM uint32_t PLSN  : 1;  /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing                               */
+            uint32_t             : 7;
+        } ELIPACR_b;
+    };
+    __IM uint32_t RESERVED1[10];
+
+    union
+    {
+        __IOM uint32_t STSR;            /*!< (@ 0x00000040) STCA Status Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SYNC    : 1; /*!< [0..0] Synchronized State Detection Flag                                  */
+            __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag                                */
+            uint32_t               : 1;
+            __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag                      */
+            __IOM uint32_t W10D    : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag                               */
+            uint32_t               : 27;
+        } STSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STIPR;           /*!< (@ 0x00000044) STCA Status Notification Permission Register               */
+
+        struct
+        {
+            __IOM uint32_t SYNC    : 1; /*!< [0..0] SYNC Status Notification Enable                                    */
+            __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable                                 */
+            uint32_t               : 1;
+            __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable                                 */
+            __IOM uint32_t W10D    : 1; /*!< [4..4] W10D Status Notification Enable                                    */
+            uint32_t               : 27;
+        } STIPR_b;
+    };
+    __IM uint32_t RESERVED2[2];
+
+    union
+    {
+        __IOM uint32_t STCFR;          /*!< (@ 0x00000050) STCA Clock Frequency Setting Register                      */
+
+        struct
+        {
+            __IOM uint32_t STCF : 2;   /*!< [1..0] STCA Clock Frequency                                               */
+            uint32_t            : 30;
+        } STCFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STMR;           /*!< (@ 0x00000054) STCA Operating Mode Register                               */
+
+        struct
+        {
+            __IOM uint32_t WINT  : 8;  /*!< [7..0] Worst 10 Acquisition Time                                          */
+            uint32_t             : 5;
+            __IOM uint32_t CMOD  : 1;  /*!< [13..13] Time Synchronization Correction Mode                             */
+            uint32_t             : 1;
+            __IOM uint32_t W10S  : 1;  /*!< [15..15] Worst 10 Acquisition Control Select                              */
+            __IOM uint32_t SYTH  : 4;  /*!< [19..16] Synchronized State Detection Threshold Setting                   */
+            __IOM uint32_t DVTH  : 4;  /*!< [23..20] Synchronization Loss Detection Threshold Setting                 */
+            uint32_t             : 4;
+            __IOM uint32_t ALEN0 : 1;  /*!< [28..28] Alarm Detection Enable 0                                         */
+            __IOM uint32_t ALEN1 : 1;  /*!< [29..29] Alarm Detection Enable 1                                         */
+            uint32_t             : 2;
+        } STMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNTOR;          /*!< (@ 0x00000058) Sync Message Reception Timeout Register                    */
+
+        struct
+        {
+            __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns),
+                                         *   where n is the setting, leads to a timeout for reception
+                                         *   of Sync messages, leading to the STSR.SYNTOUT flag being
+                                         *   set to 1.                                                                 */
+        } SYNTOR_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t IPTSELR;         /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register               */
+
+        struct
+        {
+            __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select                                        */
+            __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select                                        */
+            __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select                                        */
+            __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select                                        */
+            __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select                                        */
+            __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select                                        */
+            uint32_t               : 26;
+        } IPTSELR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MITSELR;         /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register               */
+
+        struct
+        {
+            __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable                  */
+            __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable                  */
+            __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable                  */
+            __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable                  */
+            __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable                  */
+            __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable                  */
+            uint32_t               : 26;
+        } MITSELR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t ELTSELR;         /*!< (@ 0x00000068) ELC Output Timer Select Register                           */
+
+        struct
+        {
+            __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable                      */
+            __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable                      */
+            __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable                      */
+            __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable                      */
+            __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable                      */
+            __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable                      */
+            uint32_t               : 26;
+        } ELTSELR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t STCHSELR;       /*!< (@ 0x0000006C) Time Synchronization Channel Select Register               */
+
+        struct
+        {
+            __IOM uint32_t SYSEL : 1;  /*!< [0..0] Timer Information Input SelectNOTE: Do not change the
+                                        *   value of this bit while the SYNSTARTR.STR bit is 1.                       */
+            uint32_t : 31;
+        } STCHSELR_b;
+    };
+    __IM uint32_t RESERVED4[4];
+
+    union
+    {
+        __IOM uint32_t SYNSTARTR;      /*!< (@ 0x00000080) Slave Time Synchronization Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t STR : 1;    /*!< [0..0] Slave Time Synchronization Control                                 */
+            uint32_t           : 31;
+        } SYNSTARTR_b;
+    };
+
+    union
+    {
+        __OM uint32_t LCIVLDR;         /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __OM uint32_t LOAD : 1;    /*!< [0..0] Local Time Counter Initial Value Load Directive                    */
+            uint32_t           : 31;
+        } LCIVLDR_b;
+    };
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint32_t SYNTDARU;          /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers         */
+
+        struct
+        {
+            __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                           *   bits of the threshold for detection of loss of synchronization.           */
+        } SYNTDARU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNTDARL;          /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers         */
+
+        struct
+        {
+            __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                           *   of the threshold for detection of loss of synchronization.                */
+        } SYNTDARL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNTDBRU;          /*!< (@ 0x00000098) Synchronization Detection Threshold Registers              */
+
+        struct
+        {
+            __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
+                                           *   bits of the threshold for detection of synchronization.                   */
+        } SYNTDBRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SYNTDBRL;          /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers              */
+
+        struct
+        {
+            __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                           *   of the threshold for detection of synchronization.                        */
+        } SYNTDBRL_b;
+    };
+    __IM uint32_t RESERVED6[4];
+
+    union
+    {
+        __IOM uint32_t LCIVRU;          /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers                 */
+
+        struct
+        {
+            __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
+                                         *   bits of the integer portion of the initial value for the
+                                         *   local timer counter.                                                      */
+            uint32_t : 16;
+        } LCIVRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LCIVRM;          /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers                 */
+
+        struct
+        {
+            __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                         *   of the integer portion of the initial value for the local
+                                         *   timer counter.                                                            */
+        } LCIVRM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t LCIVRL;          /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers                 */
+
+        struct
+        {
+            __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion
+                                         *   of the initial value of the local timer counter in nanoseconds.           */
+        } LCIVRL_b;
+    };
+    __IM uint32_t RESERVED7[26];
+
+    union
+    {
+        __IOM uint32_t GETW10R;        /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register                    */
+
+        struct
+        {
+            __IOM uint32_t GW10 : 1;   /*!< [0..0] Worst 10 Acquisition Directive                                     */
+            uint32_t            : 31;
+        } GETW10R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLIMITRU;          /*!< (@ 0x00000128) Positive Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
+                                           *   bits of the limit for the positive gradient.                              */
+            uint32_t : 1;
+        } PLIMITRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLIMITRM;          /*!< (@ 0x0000012C) Positive Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
+                                           *   bits of the limit for the positive gradient.                              */
+        } PLIMITRM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PLIMITRL;          /*!< (@ 0x00000130) Positive Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                           *   of the limit for the positive gradient.                                   */
+        } PLIMITRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MLIMITRU;          /*!< (@ 0x00000134) Negative Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
+                                           *   bits of the limit for the negative gradient.                              */
+            uint32_t : 1;
+        } MLIMITRU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MLIMITRM;          /*!< (@ 0x00000138) Negative Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
+                                           *   bits of the limit for the negative gradient.                              */
+        } MLIMITRM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MLIMITRL;          /*!< (@ 0x0000013C) Negative Gradient Limit Registers                          */
+
+        struct
+        {
+            __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
+                                           *   of the limit for the negative gradient.                                   */
+        } MLIMITRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GETINFOR;       /*!< (@ 0x00000140) Statistical Information Retention Control Register         */
+
+        struct
+        {
+            __IOM uint32_t INFO : 1;   /*!< [0..0] Information Retention ControlNOTE: Once information fetching
+                                        *   is directed, values of various statistical information
+                                        *   read before completion of information fetching are not
+                                        *   guaranteed.                                                               */
+            uint32_t : 31;
+        } GETINFOR_b;
+    };
+    __IM uint32_t RESERVED8[11];
+
+    union
+    {
+        __IM uint32_t LCCVRU;          /*!< (@ 0x00000170) Local Time Counters                                        */
+
+        struct
+        {
+            __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits
+                                        *   of the integer portion of the local timer counter's value.                */
+            uint32_t : 16;
+        } LCCVRU_b;
+    };
+
+    union
+    {
+        __IM uint32_t LCCVRM;          /*!< (@ 0x00000174) Local Time Counters                                        */
+
+        struct
+        {
+            __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
+                                        *   the integer portion of the local timer counter's value.                   */
+        } LCCVRM_b;
+    };
+
+    union
+    {
+        __IM uint32_t LCCVRL;          /*!< (@ 0x00000178) Local Time Counters                                        */
+
+        struct
+        {
+            __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of
+                                        *   the local timer counter's value (in nanoseconds).                         */
+        } LCCVRL_b;
+    };
+    __IM uint32_t RESERVED9[37];
+
+    union
+    {
+        __IM uint32_t PW10VRU;          /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
+                                         *   of the positive gradient value.                                           */
+        } PW10VRU_b;
+    };
+
+    union
+    {
+        __IM uint32_t PW10VRM;          /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
+                                         *   of the positive gradient value.                                           */
+        } PW10VRM_b;
+    };
+
+    union
+    {
+        __IM uint32_t PW10VRL;          /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
+                                         *   the positive gradient value.                                              */
+        } PW10VRL_b;
+    };
+    __IM uint32_t RESERVED10[45];
+
+    union
+    {
+        __IM uint32_t MW10RU;          /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
+                                        *   of the negative gradient value.                                           */
+        } MW10RU_b;
+    };
+
+    union
+    {
+        __IM uint32_t MW10RM;          /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
+                                        *   of the negative gradient value.                                           */
+        } MW10RM_b;
+    };
+
+    union
+    {
+        __IM uint32_t MW10RL;                  /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers                 */
+
+        struct
+        {
+            __IM uint32_t MW10RL : 32;         /*!< [31..0] These bits are for reading the lower-order 32 bits of
+                                                *   the negative gradient value.                                              */
+        } MW10RL_b;
+    };
+    __IM uint32_t RESERVED11[9];
+    __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers                                    */
+    __IM uint32_t RESERVED12[7];
+
+    union
+    {
+        __IOM uint32_t TMSTARTR;       /*!< (@ 0x0000037C) Timer Start Register                                       */
+
+        struct
+        {
+            __IOM uint32_t EN0 : 1;    /*!< [0..0] Pulse Output Timer 0 Start                                         */
+            __IOM uint32_t EN1 : 1;    /*!< [1..1] Pulse Output Timer 1 Start                                         */
+            __IOM uint32_t EN2 : 1;    /*!< [2..2] Pulse Output Timer 2 Start                                         */
+            __IOM uint32_t EN3 : 1;    /*!< [3..3] Pulse Output Timer 3 Start                                         */
+            __IOM uint32_t EN4 : 1;    /*!< [4..4] Pulse Output Timer 4 Start                                         */
+            __IOM uint32_t EN5 : 1;    /*!< [5..5] Pulse Output Timer 5 Start                                         */
+            uint32_t           : 26;
+        } TMSTARTR_b;
+    };
+    __IM uint32_t RESERVED13[32];
+
+    union
+    {
+        __IOM uint32_t PRSR;           /*!< (@ 0x00000400) PRC-TC Status Register                                     */
+
+        struct
+        {
+            __IOM uint32_t OVRE0 : 1;  /*!< [0..0] Relay Packet Overflow Detection Flag 0                             */
+            __IOM uint32_t OVRE1 : 1;  /*!< [1..1] Relay Packet Overflow Detection Flag 1                             */
+            __IOM uint32_t OVRE2 : 1;  /*!< [2..2] Relay Packet Overflow Detection Flag 2                             */
+            __IOM uint32_t OVRE3 : 1;  /*!< [3..3] Relay Packet Overflow Detection Flag 3                             */
+            uint32_t             : 4;
+            __IOM uint32_t MACE  : 1;  /*!< [8..8] Originating MAC Address Mismatch Detection Flag                    */
+            uint32_t             : 19;
+            __IOM uint32_t URE0  : 1;  /*!< [28..28] Relay Packet Underflow Detection Flag 0                          */
+            __IOM uint32_t URE1  : 1;  /*!< [29..29] Relay Packet Underflow Detection Flag 1                          */
+            uint32_t             : 2;
+        } PRSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PRIPR;          /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register             */
+
+        struct
+        {
+            __IOM uint32_t OVRE0 : 1;  /*!< [0..0] PRSR.OVRE0 Status Notification Permission                          */
+            __IOM uint32_t OVRE1 : 1;  /*!< [1..1] PRSR.OVRE1 Status Notification Permission                          */
+            __IOM uint32_t OVRE2 : 1;  /*!< [2..2] PRSR.OVRE2 Status Notification Permission                          */
+            __IOM uint32_t OVRE3 : 1;  /*!< [3..3] PRSR.OVRE3 Status Notification Permission                          */
+            uint32_t             : 4;
+            __IOM uint32_t MACE  : 1;  /*!< [8..8] PRSR.MACE Status Notification Permission                           */
+            uint32_t             : 19;
+            __IOM uint32_t URE0  : 1;  /*!< [28..28] PRSR.URE0 Status Notification Permission                         */
+            __IOM uint32_t URE1  : 1;  /*!< [29..29] PRSR.URE1 Status Notification Permission                         */
+            uint32_t             : 2;
+        } PRIPR_b;
+    };
+    __IM uint32_t RESERVED14[2];
+    __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers                                */
+
+    union
+    {
+        __IOM uint32_t TRNDISR;                /*!< (@ 0x00000420) Packet Transmission Control Register                       */
+
+        struct
+        {
+            __IOM uint32_t TDIS : 2;           /*!< [1..0] Packet Transmission Control                                        */
+            uint32_t            : 30;
+        } TRNDISR_b;
+    };
+    __IM uint32_t RESERVED15[3];
+
+    union
+    {
+        __IOM uint32_t TRNMR;          /*!< (@ 0x00000430) Relay Mode Register                                        */
+
+        struct
+        {
+            __IOM uint32_t MOD  : 1;   /*!< [0..0] Cut-Through Mode                                                   */
+            uint32_t            : 7;
+            __IOM uint32_t FWD0 : 1;   /*!< [8..8] Channel 0 Relay Enable                                             */
+            __IOM uint32_t FWD1 : 1;   /*!< [9..9] Channel 1 Relay Enable                                             */
+            uint32_t            : 22;
+        } TRNMR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t TRNCTTDR;       /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register              */
+
+        struct
+        {
+            __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read
+                                        *   data from the relay FIFO in cut-through mode (specified
+                                        *   as the number of bytes)NOTE1: A value cannot be set in
+                                        *   the lower-order 2 bits. These bits are fixed to 0.NOTE2:
+                                        *   A value of less than 96 bytes cannot be set.                              */
+            uint32_t : 21;
+        } TRNCTTDR_b;
+    };
+} R_ETHERC_EPTPC_COMMON_Type;          /*!< Size = 1080 (0x438)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
+ */
+
+typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
+{
+    union
+    {
+        __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+        __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
+    };
+} R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface (R_FACI_HP)
+ */
+
+typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
+{
+    __IM uint32_t RESERVED[4];
+
+    union
+    {
+        __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
+
+        struct
+        {
+            __IM uint8_t ECRCT  : 1;   /*!< [0..0] ECRCT                                                              */
+            uint8_t             : 2;
+            __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
+            __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
+            uint8_t             : 2;
+            __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
+        } FASTAT_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
+
+        struct
+        {
+            __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable                                     */
+            uint8_t               : 2;
+            __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
+            __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
+            uint8_t               : 2;
+            __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
+        } FAEINT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
+
+        struct
+        {
+            __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
+            uint8_t              : 7;
+        } FRDYIE_b;
+    };
+    __IM uint8_t  RESERVED5;
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[5];
+
+    union
+    {
+        __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
+
+        struct
+        {
+            __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
+                                        *   These bits can be written when FRDY bit of FSTATR register
+                                        *   is "1". Writing to these bits in FRDY = "0" is ignored.                   */
+        } FSADDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
+
+        struct
+        {
+            __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
+                                        *   end address of target area in "Blank Check" command. These
+                                        *   bits can be written when FRDY bit of FSTATR register is
+                                        *   "1". Writing to these bits in FRDY = "0" is ignored.                      */
+        } FEADDR_b;
+    };
+    __IM uint32_t RESERVED8[18];
+
+    union
+    {
+        __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IM uint32_t TBLCRCT : 1; /*!< [2..2] Table Area ECC 1-Bit Error Correction Monitoring Bit               */
+            __IM uint32_t TBLDTCT : 1; /*!< [3..3] Table Area ECC 2-Bit Error Detection Monitoring Bit                */
+            __IM uint32_t CFGCRCT : 1; /*!< [4..4] Config Area ECC 1-Bit Error Correction Monitoring Bit              */
+            __IM uint32_t CFGDTCT : 1; /*!< [5..5] Config Area ECC 2-Bit Error Detection Monitoring Bit               */
+            __IM uint32_t FHVEERR : 1; /*!< [6..6] "fhve" Error                                                       */
+            __IM uint32_t FCUERR  : 1; /*!< [7..7] FCU Error                                                          */
+            __IM uint32_t PRGSPD  : 1; /*!< [8..8] Programming-Suspended Status                                       */
+            __IM uint32_t ERSSPD  : 1; /*!< [9..9] Erasure-Suspended Status                                           */
+            __IM uint32_t DBFULL  : 1; /*!< [10..10] Data Buffer Full                                                 */
+            __IM uint32_t SUSRDY  : 1; /*!< [11..11] Suspend Ready                                                    */
+            __IM uint32_t PRGERR  : 1; /*!< [12..12] Programming Error                                                */
+            __IM uint32_t ERSERR  : 1; /*!< [13..13] Erasure Error                                                    */
+            __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error                                            */
+            __IM uint32_t FRDY    : 1; /*!< [15..15] Flash Ready                                                      */
+            __IM uint32_t OTPCRCT : 1; /*!< [16..16] OTP Bit ECC 1-Bit Error Correction Monitoring Bit                */
+            __IM uint32_t OTPDTCT : 1; /*!< [17..17] OTP Bit ECC 2-Bit Error Detection Monitoring Bit                 */
+            __IM uint32_t EBFULL  : 1; /*!< [18..18] FDMYECC Buffer Full                                              */
+            uint32_t              : 13;
+        } FSTATR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
+
+        struct
+        {
+            __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is "1". Writing to this bit
+                                         *   in FRDY = "0" is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits                                               */
+            uint16_t               : 6;
+            __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
+                                         *   FRDY bit in FSTATR register is "1". Writing to this bit
+                                         *   in FRDY = "0" is ignored. Writing to these bits is enabled
+                                         *   only when this register is accessed in 16-bit size and
+                                         *   H'AA is written to KEY bits.                                              */
+            __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
+        } FENTRYR_b;
+    };
+    __IM uint16_t RESERVED9;
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
+
+        struct
+        {
+            __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
+                                        *   bit of FSTATR register is "1". Writing to this bit in FRDY
+                                        *   = "0" is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'2D
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 7;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUINITR_b;
+    };
+    __IM uint16_t RESERVED11;
+    __IM uint32_t RESERVED12[4];
+
+    union
+    {
+        __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
+
+        struct
+        {
+            __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
+            __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
+        } FCMDR_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14[7];
+
+    union
+    {
+        __IM uint16_t FPESTAT;         /*!< (@ 0x000000C0) Program/Erase Error Status                                 */
+
+        struct
+        {
+            __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status                                                   */
+            uint16_t              : 8;
+        } FPESTAT_b;
+    };
+    __IM uint16_t RESERVED15;
+    __IM uint32_t RESERVED16[3];
+
+    union
+    {
+        __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
+
+        struct
+        {
+            __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
+            uint8_t             : 7;
+        } FBCCNT_b;
+    };
+    __IM uint8_t  RESERVED17;
+    __IM uint16_t RESERVED18;
+
+    union
+    {
+        __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
+
+        struct
+        {
+            __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
+            uint8_t           : 7;
+        } FBCSTAT_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
+
+        struct
+        {
+            __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
+                                        *   of the first programmed data which is found in "Blank Check"
+                                        *   command execution.                                                        */
+            uint32_t : 13;
+        } FPSADDR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
+
+        struct
+        {
+            __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
+                                        *   indicate the start sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t           : 4;
+            __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
+                                        *   Flag and Temporary Boot Swap Control and "Config Clear"
+                                        *   command execution                                                         */
+            __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
+                                        *   indicate the end sector address for setting the access
+                                        *   window that is located in the configuration area.                         */
+            uint32_t            : 4;
+            __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
+        } FAWMON_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
+
+        struct
+        {
+            __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
+            uint16_t               : 15;
+        } FCPSR_b;
+    };
+    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
+
+        struct
+        {
+            __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
+                                        *   can be written when FRDY bit in FSTATR register is "1".
+                                        *   Writing to this bit in FRDY = "0" is ignored. Writing to
+                                        *   these bits is enabled only when this register is accessed
+                                        *   in 16-bit size and H'1E is written to KEY bits.                           */
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FPCKAR_b;
+    };
+    __IM uint16_t RESERVED22;
+
+    union
+    {
+        __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
+
+        struct
+        {
+            __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
+                                        *   bit in FSTATR register is "1". Writing to this bit in FRDY
+                                        *   = "0" is ignored. Writing to these bits is enabled only
+                                        *   when this register is accessed in 16-bit size and H'66
+                                        *   is written to KEY bits.                                                   */
+            uint16_t          : 6;
+            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
+        } FSUACR_b;
+    };
+    __IM uint16_t RESERVED23;
+} R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_LP                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Application Command Interface (R_FACI_LP)
+ */
+
+typedef struct                         /*!< (@ 0x407EC000) R_FACI_LP Structure                                        */
+{
+    __IM uint32_t RESERVED[36];
+    __IOM uint8_t DFLCTL;              /*!< (@ 0x00000090) Flash P/E Mode Control Register                            */
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3[27];
+
+    union
+    {
+        __IOM uint8_t FPMCR;           /*!< (@ 0x00000100) Flash P/E Mode Control Register                            */
+
+        struct
+        {
+            uint8_t            : 1;
+            __IOM uint8_t FMS0 : 1;    /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
+                                        *   011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
+                                        *   P/E mode 010: Data flash P/E mode Others: Setting prohibited.             */
+            uint8_t             : 1;
+            __IOM uint8_t RPDIS : 1;   /*!< [3..3] Code Flash P/E Disable                                             */
+            __IOM uint8_t FMS1  : 1;   /*!< [4..4] The bit to make data flash a programming modeRefer to
+                                        *   the description of the FMS0 bit.                                          */
+            uint8_t            : 1;
+            __IOM uint8_t VLPE : 1;    /*!< [6..6] Low-Voltage P/E Mode Enable                                        */
+            __IOM uint8_t FMS2 : 1;    /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
+                                        *   of the FMS0 bit.                                                          */
+        } FPMCR_b;
+    };
+    __IM uint8_t  RESERVED4;
+    __IM uint16_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t FASR;            /*!< (@ 0x00000104) Flash Area Select Register                                 */
+
+        struct
+        {
+            __IOM uint8_t EXS : 1;     /*!< [0..0] Extra area select                                                  */
+            uint8_t           : 7;
+        } FASR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t FSARL;             /*!< (@ 0x00000108) Flash Processing Start Address Register L                  */
+
+        struct
+        {
+            __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address                                                     */
+        } FSARL_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t FSARH;             /*!< (@ 0x00000110) Flash Processing Start Address Register H                  */
+
+        struct
+        {
+            __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address                                                      */
+            uint16_t                 : 4;
+            __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address                                                     */
+        } FSARH_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint8_t FCR;             /*!< (@ 0x00000114) Flash Control Register                                     */
+
+        struct
+        {
+            __IOM uint8_t CMD  : 4;    /*!< [3..0] Software Command Setting                                           */
+            __IOM uint8_t DRC  : 1;    /*!< [4..4] Data Read Completion                                               */
+            uint8_t            : 1;
+            __IOM uint8_t STOP : 1;    /*!< [6..6] Forced Processing Stop                                             */
+            __IOM uint8_t OPST : 1;    /*!< [7..7] Processing Start                                                   */
+        } FCR_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t FEARL;             /*!< (@ 0x00000118) Flash Processing End Address Register L                    */
+
+        struct
+        {
+            __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address                                                       */
+        } FEARL_b;
+    };
+    __IM uint16_t RESERVED13;
+    __IM uint32_t RESERVED14;
+
+    union
+    {
+        __IOM uint32_t FEARH;             /*!< (@ 0x00000120) Flash Processing End Address Register H                    */
+
+        struct
+        {
+            __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address                                                        */
+            uint32_t                 : 4;
+            __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address                                                       */
+            uint32_t                 : 16;
+        } FEARH_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FRESETR;        /*!< (@ 0x00000124) Flash Reset Register                                       */
+
+        struct
+        {
+            __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers                                    */
+            uint32_t              : 31;
+        } FRESETR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FSTATR00;         /*!< (@ 0x00000128) Flash Status Register00                                    */
+
+        struct
+        {
+            __IM uint32_t ERERR0   : 1; /*!< [0..0] Erase Error Flag0                                                  */
+            __IM uint32_t PRGERR0  : 1; /*!< [1..1] Program Error Flag0                                                */
+            __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
+            __IM uint32_t BCERR0   : 1; /*!< [3..3] Blank Check Error Flag0                                            */
+            __IM uint32_t ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
+            __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
+            uint32_t               : 26;
+        } FSTATR00_b;
+    };
+
+    union
+    {
+        __IM uint32_t FSTATR1;         /*!< (@ 0x0000012C) Flash Status Register1                                     */
+
+        struct
+        {
+            uint32_t            : 1;
+            __IM uint32_t DRRDY : 1;   /*!< [1..1] Data read request                                                  */
+            uint32_t            : 4;
+            __IM uint32_t FRDY  : 1;   /*!< [6..6] End status signal of a sequencer                                   */
+            __IM uint32_t EXRDY : 1;   /*!< [7..7] End status signal of a Extra programming sequencer                 */
+            uint32_t            : 24;
+        } FSTATR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FWBL0;          /*!< (@ 0x00000130) Flash Write Buffer Register L0                             */
+
+        struct
+        {
+            __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
+            uint32_t             : 16;
+        } FWBL0_b;
+    };
+    __IM uint32_t RESERVED15;
+
+    union
+    {
+        __IOM uint32_t FWBH0;          /*!< (@ 0x00000138) Flash Write Buffer Register H0                             */
+
+        struct
+        {
+            __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
+            uint32_t             : 16;
+        } FWBH0_b;
+    };
+
+    union
+    {
+        __IM uint32_t FSTATR01;        /*!< (@ 0x0000013C) Flash Status Register01                                    */
+
+        struct
+        {
+            __IM uint32_t ERERR1  : 1; /*!< [0..0] Erase Error Flag1                                                  */
+            __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1                                                */
+            uint32_t              : 1;
+            __IM uint32_t BCERR1  : 1; /*!< [3..3] Blank Check Error Flag1                                            */
+            uint32_t              : 28;
+        } FSTATR01_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FWBL1;               /*!< (@ 0x00000140) Flash Write Buffer Register L1                             */
+
+        struct
+        {
+            __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command                               */
+            uint32_t                  : 16;
+        } FWBL1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FWBH1;               /*!< (@ 0x00000144) Flash Write Buffer Register H1                             */
+
+        struct
+        {
+            __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command                               */
+            uint32_t                  : 16;
+        } FWBH1_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRBL1;               /*!< (@ 0x00000148) Flash Read Buffer Register L1                              */
+
+        struct
+        {
+            __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command                         */
+            uint32_t                 : 16;
+        } FRBL1_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRBH1;               /*!< (@ 0x0000014C) Flash Read Buffer Register H1                              */
+
+        struct
+        {
+            __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command                         */
+            uint32_t                 : 16;
+        } FRBH1_b;
+    };
+    __IM uint32_t RESERVED16[12];
+
+    union
+    {
+        __OM uint32_t FPR;             /*!< (@ 0x00000180) Protection Unlock Register                                 */
+
+        struct
+        {
+            __OM uint32_t FPR : 8;     /*!< [7..0] Protection Unlock Register                                         */
+            uint32_t          : 24;
+        } FPR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FPSR;            /*!< (@ 0x00000184) Protection Unlock Status Register                          */
+
+        struct
+        {
+            __IM uint32_t PERR : 1;    /*!< [0..0] Protect Error Flag                                                 */
+            uint32_t           : 31;
+        } FPSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FRBL0;           /*!< (@ 0x00000188) Flash Read Buffer Register L0                              */
+
+        struct
+        {
+            __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
+            uint32_t            : 16;
+        } FRBL0_b;
+    };
+    __IM uint32_t RESERVED17;
+
+    union
+    {
+        __IM uint32_t FRBH0;           /*!< (@ 0x00000190) Flash Read Buffer Register H0                              */
+
+        struct
+        {
+            __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
+            uint32_t            : 16;
+        } FRBH0_b;
+    };
+    __IM uint32_t RESERVED18[11];
+
+    union
+    {
+        __IM uint32_t FSCMR;           /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register                    */
+
+        struct
+        {
+            uint32_t            : 8;
+            __IM uint32_t SASMF : 1;   /*!< [8..8] Start-up Area Setting Monitor Flag                                 */
+            uint32_t            : 5;
+            __IM uint32_t FSPR  : 1;   /*!< [14..14] Access Window Protection Flag                                    */
+            uint32_t            : 17;
+        } FSCMR_b;
+    };
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IM uint32_t FAWSMR;          /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register         */
+
+        struct
+        {
+            __IM uint32_t FAWS : 12;   /*!< [11..0] Flash Access Window Start Address                                 */
+            uint32_t           : 20;
+        } FAWSMR_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IM uint32_t FAWEMR;          /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register           */
+
+        struct
+        {
+            __IM uint32_t FAWE : 12;   /*!< [11..0] Flash Access Window End Address                                   */
+            uint32_t           : 20;
+        } FAWEMR_b;
+    };
+    __IM uint32_t RESERVED21;
+
+    union
+    {
+        __IOM uint32_t FISR;           /*!< (@ 0x000001D8) Flash Initial Setting Register                             */
+
+        struct
+        {
+            __IOM uint32_t PCKA : 6;   /*!< [5..0] Peripheral Clock Notification                                      */
+            __IOM uint32_t SAS  : 2;   /*!< [7..6] Temporary boot swap mode                                           */
+            uint32_t            : 24;
+        } FISR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t FEXCR;          /*!< (@ 0x000001DC) Flash Extra Area Control Register                          */
+
+        struct
+        {
+            __IOM uint32_t CMD  : 3;   /*!< [2..0] Processing Start)                                                  */
+            uint32_t            : 4;
+            __IOM uint32_t OPST : 1;   /*!< [7..7] Software Command Setting                                           */
+            uint32_t            : 24;
+        } FEXCR_b;
+    };
+
+    union
+    {
+        __IM uint32_t FEAML;           /*!< (@ 0x000001E0) Flash Error Address Monitor Register L                     */
+
+        struct
+        {
+            __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
+            uint32_t           : 16;
+        } FEAML_b;
+    };
+    __IM uint32_t RESERVED22;
+
+    union
+    {
+        __IM uint32_t FEAMH;           /*!< (@ 0x000001E8) Flash Error Address Monitor Register H                     */
+
+        struct
+        {
+            __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
+            uint32_t           : 16;
+        } FEAMH_b;
+    };
+    __IM uint32_t RESERVED23;
+
+    union
+    {
+        __IM uint32_t FSTATR2;           /*!< (@ 0x000001F0) Flash Status Register2                                     */
+
+        struct
+        {
+            __IM uint32_t  ERERR    : 1; /*!< [0..0] Erase Error Flag                                                   */
+            __IM uint32_t  PRGERR1  : 1; /*!< [1..1] Program Error Flag                                                 */
+            __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
+            __IM uint32_t  BCERR    : 1; /*!< [3..3] Blank Check Error Flag                                             */
+            __IM uint32_t  ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
+            __IM uint32_t  EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
+            uint32_t                : 26;
+        } FSTATR2_b;
+    };
+    __IM uint32_t  RESERVED24[3951];
+    __IOM uint16_t FENTRYR_MF4;        /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4                      */
+    __IOM uint16_t FENTRYR;            /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register                              */
+    __IM uint32_t  RESERVED25[3];
+    __IOM uint8_t  FLWAITR;            /*!< (@ 0x00003FC0) Flash Wait Cycle Register                                  */
+    __IM uint8_t   RESERVED26;
+    __IM uint16_t  RESERVED27;
+    __IM uint32_t  RESERVED28;
+    __IOM uint8_t  PFBER;              /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register                            */
+    __IM uint8_t   RESERVED29;
+    __IM uint16_t  RESERVED30;
+} R_FACI_LP_Type;                      /*!< Size = 16332 (0x3fcc)                                                     */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Flash Memory Cache (R_FCACHE)
+ */
+
+typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
+{
+    __IM uint16_t RESERVED[128];
+
+    union
+    {
+        __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
+
+        struct
+        {
+            __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
+            uint16_t                : 15;
+        } FCACHEE_b;
+    };
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
+
+        struct
+        {
+            __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
+            uint16_t                : 15;
+        } FCACHEIV_b;
+    };
+    __IM uint16_t RESERVED2[11];
+
+    union
+    {
+        __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
+
+        struct
+        {
+            __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
+            uint8_t            : 5;
+        } FLWT_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+} R_FCACHE_Type;                       /*!< Size = 288 (0x120)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GLCDC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Graphics LCD Controller (R_GLCDC)
+ */
+
+typedef struct                         /*!< (@ 0x400E0000) R_GLCDC Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane                 */
+
+        struct
+        {
+            __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
+            __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
+            __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
+            __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
+                                        *   m Plane                                                                   */
+        } GR1_CLUT0_b[256];
+    };
+
+    union
+    {
+        __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane                 */
+
+        struct
+        {
+            __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
+            __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
+            __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
+            __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
+                                        *   m Plane                                                                   */
+        } GR1_CLUT1_b[256];
+    };
+
+    union
+    {
+        __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane                 */
+
+        struct
+        {
+            __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
+            __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
+            __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
+            __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
+                                        *   m Plane                                                                   */
+        } GR2_CLUT0_b[256];
+    };
+
+    union
+    {
+        __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane                 */
+
+        struct
+        {
+            __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
+            __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
+            __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
+            __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
+                                        *   m Plane                                                                   */
+        } GR2_CLUT1_b[256];
+    };
+    __IOM R_GLCDC_BG_Type     BG;      /*!< (@ 0x00001000) Background Registers                                       */
+    __IM uint32_t             RESERVED[57];
+    __IOM R_GLCDC_GR_Type     GR[2];   /*!< (@ 0x00001100) Layer Registers                                            */
+    __IOM R_GLCDC_GAM_Type    GAM[3];  /*!< (@ 0x00001300) Gamma Settings                                             */
+    __IOM R_GLCDC_OUT_Type    OUT;     /*!< (@ 0x000013C0) Output Control Registers                                   */
+    __IM uint32_t             RESERVED1[6];
+    __IOM R_GLCDC_TCON_Type   TCON;    /*!< (@ 0x00001400) Timing Control Registers                                   */
+    __IM uint32_t             RESERVED2[5];
+    __IOM R_GLCDC_SYSCNT_Type SYSCNT;  /*!< (@ 0x00001440) GLCDC System Control Registers                             */
+} R_GLCDC_Type;                        /*!< Size = 5204 (0x1454)                                                      */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief General PWM Timer (R_GPT0)
+ */
+
+typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
+
+        struct
+        {
+            __IOM uint32_t WP   : 1;   /*!< [0..0] Register Write Disable                                             */
+            uint32_t            : 7;
+            __OM uint32_t PRKEY : 8;   /*!< [15..8] GTWP Key Code                                                     */
+            uint32_t            : 16;
+        } GTWP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
+
+        struct
+        {
+            __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
+                                         *   means counter running.                                                    */
+            uint32_t : 18;
+        } GTSTR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
+
+        struct
+        {
+            __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
+                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
+                                         *   1 means counter stop.                                                     */
+            uint32_t : 18;
+        } GTSTP_b;
+    };
+
+    union
+    {
+        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
+
+        struct
+        {
+            __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
+            __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
+            __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
+            uint32_t             : 18;
+        } GTCLR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
+            __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
+            __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Start Enable                                                      */
+            __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
+            __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
+        } GTSSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
+
+        struct
+        {
+            __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
+            __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
+            __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Stop Enable                                                       */
+            __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
+            __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
+            uint32_t              : 7;
+            __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
+        } GTPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
+
+        struct
+        {
+            __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
+            __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
+            __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Clear Enable                                                      */
+            __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
+            __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
+            uint32_t              : 7;
+            __IOM uint32_t CCLR   : 1;   /*!< [31..31] Software Source Counter Clear Enable                             */
+        } GTCSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
+
+        struct
+        {
+            __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
+            __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
+            __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Up Enable                                                   */
+            __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
+            __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
+            uint32_t              : 8;
+        } GTUPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
+
+        struct
+        {
+            __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
+            __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
+            __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   Counter Count Down Enable                                                 */
+            __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
+            __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
+            uint32_t              : 8;
+        } GTDNSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
+                                          *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
+            __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRA Input Capture Enable                                               */
+            __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICASR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
+                                          *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
+            __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
+                                          *   Enable                                                                    */
+            __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
+                                          *   GTCCRB Input Capture Enable                                               */
+            __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
+            uint32_t              : 8;
+        } GTICBSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
+
+        struct
+        {
+            __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
+            uint32_t            : 15;
+            __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
+            uint32_t            : 5;
+            __IOM uint32_t TPCS : 3;   /*!< [26..24] Timer Prescaler Select                                           */
+            uint32_t            : 5;
+        } GTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
+            __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
+            uint32_t              : 14;
+            __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
+            __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
+            __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t              : 4;
+            __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
+            __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
+            __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
+                                        *   percent Duty Setting                                                      */
+            uint32_t : 4;
+        } GTUDDTYC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
+            uint32_t              : 1;
+            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
+            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
+            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
+            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
+            uint32_t              : 2;
+            __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
+            __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
+            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
+            uint32_t              : 1;
+            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
+            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
+            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
+            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
+            uint32_t              : 2;
+            __IOM uint32_t NFBEN  : 1; /*!< [29..29] Noise Filter B Enable                                            */
+            __IOM uint32_t NFCSB  : 2; /*!< [31..30] Noise Filter B Sampling Clock Select                             */
+        } GTIOR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
+
+        struct
+        {
+            uint32_t              : 24;
+            __IOM uint32_t GRP    : 2; /*!< [25..24] Output Disable Source Select                                     */
+            uint32_t              : 2;
+            __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
+            __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            uint32_t              : 1;
+        } GTINTAD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
+
+        struct
+        {
+            __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
+            __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
+            __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
+            __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
+            __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
+            __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
+            __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
+            __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
+            __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
+                                         *   for counting the number of times a timer interrupt has
+                                         *   been skipped.)                                                            */
+            uint32_t               : 4;
+            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
+            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
+                                         *   Request Interrupt Enable                                                  */
+            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
+                                         *   Request Flag                                                              */
+            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
+                                         *   Start Request Flag                                                        */
+            uint32_t            : 4;
+            __IM uint32_t ODF   : 1;    /*!< [24..24] Output Disable Flag                                              */
+            uint32_t            : 3;
+            __IM uint32_t DTEF  : 1;    /*!< [28..28] Dead Time Error Flag                                             */
+            __IM uint32_t OABHF : 1;    /*!< [29..29] Same Time Output Level High Disable Request Enable               */
+            __IM uint32_t OABLF : 1;    /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
+            uint32_t            : 1;
+        } GTST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
+
+        struct
+        {
+            __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
+            __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
+            __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
+            __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
+            uint32_t              : 12;
+            __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
+            __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
+            __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
+            __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
+                                        *   is read as 0.                                                             */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
+                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                        *   at an underflow (in down-counting) or overflow (in up-counting)
+                                        *   is performed.                                                             */
+            __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
+            uint32_t             : 1;
+            __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
+                                        *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
+                                        *   at an underflow (in down-counting) or overflow (in up-counting)
+                                        *   is performed.                                                             */
+            __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
+            uint32_t             : 1;
+        } GTBER_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
+                                        *                  Start Request Skipping Setting Register                    */
+
+        struct
+        {
+            __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
+            __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
+            __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
+            __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
+            __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
+            uint32_t             : 1;
+            __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
+            uint32_t             : 1;
+            __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
+            uint32_t             : 17;
+        } GTITC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
+
+        struct
+        {
+            __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
+        } GTCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
+
+        struct
+        {
+            __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
+        } GTCCR_b[6];
+    };
+
+    union
+    {
+        __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
+
+        struct
+        {
+            __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
+        } GTPR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
+
+        struct
+        {
+            __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
+        } GTPBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
+        } GTPDBR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
+        } GTADTRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
+                                           *                  A                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
+        } GTADTBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register A                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   A                                                                         */
+        } GTADTDBRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
+
+        struct
+        {
+            __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
+        } GTADTRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
+                                           *                  B                                                          */
+
+        struct
+        {
+            __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
+        } GTADTBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
+                                            *                  Register B                                                 */
+
+        struct
+        {
+            __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
+                                            *   B                                                                         */
+        } GTADTDBRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
+
+        struct
+        {
+            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
+            uint32_t             : 3;
+            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
+            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
+            uint32_t             : 2;
+            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
+            uint32_t             : 23;
+        } GTDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
+        } GTDVU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
+
+        struct
+        {
+            __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
+        } GTDVD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
+
+        struct
+        {
+            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
+        } GTDBU_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
+
+        struct
+        {
+            __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
+        } GTDBD_b;
+    };
+
+    union
+    {
+        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
+                                        *                  Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
+            uint32_t          : 30;
+        } GTSOS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
+                                        *                  Temporary Release Register                                 */
+
+        struct
+        {
+            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
+            uint32_t            : 31;
+        } GTSOTR_b;
+    };
+} R_GPT0_Type;                         /*!< Size = 164 (0xa4)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_ODC                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief PWM Delay Generation Circuit (R_GPT_ODC)
+ */
+
+typedef struct                         /*!< (@ 0x4007B000) R_GPT_ODC Structure                                        */
+{
+    union
+    {
+        __IOM uint16_t GTDLYCR1;       /*!< (@ 0x00000000) PWM Output Delay Control Register1                         */
+
+        struct
+        {
+            __IOM uint16_t DLLEN  : 1; /*!< [0..0] DLL Operation Enable                                               */
+            __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset                                 */
+            uint16_t              : 6;
+            __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select                                                    */
+            uint16_t              : 7;
+        } GTDLYCR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t GTDLYCR2;         /*!< (@ 0x00000002) PWM Output Delay Control Register2                         */
+
+        struct
+        {
+            __IOM uint16_t DLYBS0   : 1; /*!< [0..0] PWM Delay Generation Circuit bypass                                */
+            __IOM uint16_t DLYBS1   : 1; /*!< [1..1] PWM Delay Generation Circuit bypass                                */
+            __IOM uint16_t DLYBS2   : 1; /*!< [2..2] PWM Delay Generation Circuit bypass                                */
+            __IOM uint16_t DLYBS3   : 1; /*!< [3..3] PWM Delay Generation Circuit bypass                                */
+            uint16_t                : 4;
+            __IOM uint16_t DLYEN0   : 1; /*!< [8..8] PWM Delay Generation Circuit enable                                */
+            uint16_t                : 3;
+            __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB                */
+            uint16_t                : 3;
+        } GTDLYCR2_b;
+    };
+    __IM uint16_t               RESERVED[10];
+    __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING                                           */
+    __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING                                          */
+} R_GPT_ODC_Type;                          /*!< Size = 56 (0x38)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Output Phase Switching for GPT (R_GPT_OPS)
+ */
+
+typedef struct                         /*!< (@ 0x40078FF0) R_GPT_OPS Structure                                        */
+{
+    union
+    {
+        __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
+
+        struct
+        {
+            __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
+                                        *   by the software settings.This bit setting is valid when
+                                        *   the OPSCR.FB bit = 1.                                                     */
+            uint32_t        : 1;
+            __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
+                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
+                                        *   e settings (UF/VF/WF)                                                     */
+            uint32_t          : 1;
+            __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
+            uint32_t          : 7;
+            __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
+                                        *   input phase from the software settings and external input.                */
+            __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
+            __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
+            __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
+            __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
+            __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
+            uint32_t             : 2;
+            __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
+            __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
+            uint32_t             : 2;
+            __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
+            __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
+                                        *   sampling clock setting of the external input.                             */
+        } OPSCR_b;
+    };
+} R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Port Output Enable for GPT (R_GPT_POEG0)
+ */
+
+typedef struct                         /*!< (@ 0x40042000) R_GPT_POEG0 Structure                                      */
+{
+    union
+    {
+        __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */
+
+        struct
+        {
+            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
+            __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
+            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
+            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
+            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection EnableNote: Can be modified only
+                                        *   once after a reset.                                                       */
+            __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t             : 1;
+            __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
+                                        *   only once after a reset.                                                  */
+            uint32_t            : 2;
+            __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
+            uint32_t            : 11;
+            __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
+            __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
+            __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
+        } POEGG_b;
+    };
+} R_GPT_POEG0_Type;                    /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Controller Unit (R_ICU)
+ */
+
+typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
+
+        struct
+        {
+            __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
+            uint8_t               : 2;
+            __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
+            uint8_t               : 1;
+            __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
+        } IRQCR_b[16];
+    };
+    __IM uint32_t RESERVED[60];
+
+    union
+    {
+        __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
+            uint8_t                : 3;
+            __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
+            uint8_t                : 1;
+            __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
+        } NMICR_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+    __IM uint32_t RESERVED3[7];
+
+    union
+    {
+        __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
+
+        struct
+        {
+            __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
+            __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
+            __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
+            __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
+            __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
+            uint16_t               : 1;
+            __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
+            __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
+            __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
+            __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
+            __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
+            __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
+            __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
+            uint16_t               : 3;
+        } NMIER_b;
+    };
+    __IM uint16_t RESERVED4;
+    __IM uint32_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
+
+        struct
+        {
+            __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
+            __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
+            __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
+            __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
+            __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
+            uint16_t               : 1;
+            __OM uint16_t OSTCLR   : 1; /*!< [6..6] OST Clear                                                          */
+            __OM uint16_t NMICLR   : 1; /*!< [7..7] NMI Clear                                                          */
+            __OM uint16_t RPECLR   : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
+            __OM uint16_t RECCCLR  : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
+            __OM uint16_t BUSSCLR  : 1; /*!< [10..10] Bus Slave Error Clear                                            */
+            __OM uint16_t BUSMCLR  : 1; /*!< [11..11] Bus Master Error Clear                                           */
+            __OM uint16_t SPECLR   : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
+            uint16_t               : 3;
+        } NMICLR_b;
+    };
+    __IM uint16_t RESERVED6;
+    __IM uint32_t RESERVED7[3];
+
+    union
+    {
+        __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
+
+        struct
+        {
+            __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
+            __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
+            __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
+            __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
+            __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
+            uint16_t              : 1;
+            __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
+            __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
+            __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
+            __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
+            __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
+            __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
+            __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
+            uint16_t              : 3;
+        } NMISR_b;
+    };
+    __IM uint16_t RESERVED8;
+    __IM uint32_t RESERVED9[23];
+
+    union
+    {
+        __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
+            __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
+            __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
+            __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
+            __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
+            __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
+            __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
+            uint32_t                    : 1;
+            __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
+            __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
+            __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
+            __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
+            __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
+            __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
+            __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
+            __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
+                                              *   enable                                                                    */
+            __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
+        } WUPEN_b;
+    };
+    __IM uint32_t RESERVED10[23];
+
+    union
+    {
+        __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
+
+        struct
+        {
+            __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
+            uint16_t            : 7;
+        } SELSR0_b;
+    };
+    __IM uint16_t RESERVED11;
+    __IM uint32_t RESERVED12[31];
+
+    union
+    {
+        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
+
+        struct
+        {
+            __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
+                                        *   IR flag is prohibited.                                                    */
+            uint32_t : 15;
+        } DELSR_b[8];
+    };
+    __IM uint32_t RESERVED13[24];
+
+    union
+    {
+        __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
+
+        struct
+        {
+            __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
+                                        *   signal to be linked .                                                     */
+            uint32_t            : 7;
+            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
+            uint32_t            : 7;
+            __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
+            uint32_t            : 7;
+        } IELSR_b[96];
+    };
+} R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I2C Bus Interface (R_IIC0)
+ */
+
+typedef struct                         /*!< (@ 0x40053000) R_IIC0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
+
+        struct
+        {
+            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
+            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
+            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
+            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
+            __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
+            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
+            __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
+                                        *   is initiated using the IICRST bit for a bus hang-up occurred
+                                        *   during communication with the master device in slave mode,
+                                        *   the states may become different between the slave device
+                                        *   and the master device (due to the difference in the bit
+                                        *   counter information).                                                     */
+            __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
+        } ICCR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
+
+        struct
+        {
+            uint8_t          : 1;
+            __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
+                                        *   condition issuance request) when the BBSY flag is set to
+                                        *   0 (bus free state).                                                       */
+            __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
+                                        *   RS bit to 1 while issuing a stop condition.                               */
+            __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
+                                        *   bit is not possible while the setting of the BBSY flag
+                                        *   is 0 (bus free state).Note: Do not set the SP bit to 1
+                                        *   while a restart condition is being issued.                                */
+            uint8_t            : 1;
+            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
+            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
+            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
+        } ICCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
+
+        struct
+        {
+            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
+            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
+            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
+                                        *   / 2^CKS )                                                                 */
+            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
+        } ICMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
+            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
+            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
+            uint8_t            : 1;
+            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
+            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
+        } ICMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
+
+        struct
+        {
+            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
+            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
+            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
+            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
+            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
+            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
+                                        *   be sure to read the ICDRR beforehand.                                     */
+            __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
+        } ICMR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
+
+        struct
+        {
+            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
+            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
+            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
+            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
+            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
+            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
+            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
+            __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
+        } ICFER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
+
+        struct
+        {
+            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
+            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
+            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
+            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
+            uint8_t             : 1;
+            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
+            uint8_t             : 1;
+            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
+        } ICSER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
+
+        struct
+        {
+            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
+            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
+            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
+            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
+            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
+            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
+            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
+            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
+        } ICIER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
+
+        struct
+        {
+            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
+            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
+            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
+            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
+            uint8_t            : 1;
+            __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
+            uint8_t            : 1;
+            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
+        } ICSR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
+            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
+            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
+            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
+            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
+            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
+            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
+            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
+        } ICSR2_b;
+    };
+    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
+
+    union
+    {
+        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
+
+        struct
+        {
+            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
+            uint8_t           : 3;
+        } ICBRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
+
+        struct
+        {
+            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
+            uint8_t           : 3;
+        } ICBRH_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
+
+        struct
+        {
+            __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
+        } ICDRT_b;
+    };
+
+    union
+    {
+        __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
+
+        struct
+        {
+            __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
+        } ICDRR_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
+
+        struct
+        {
+            __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
+            uint8_t             : 3;
+            __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
+            __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
+            __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
+            __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
+        } ICWUR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
+
+        struct
+        {
+            __IM uint8_t WUSEN  : 1;   /*!< [0..0] Wake-up Function Synchronous Enable                                */
+            __IM uint8_t WUASYF : 1;   /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
+            __IM uint8_t WUSYF  : 1;   /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
+            uint8_t             : 5;
+        } ICWUR2_b;
+    };
+} R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IRDA                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief IrDA Interface (R_IRDA)
+ */
+
+typedef struct                         /*!< (@ 0x40070F00) R_IRDA Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t IRCR;            /*!< (@ 0x00000000) IrDA Control Register                                      */
+
+        struct
+        {
+            uint8_t               : 2;
+            __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching                                           */
+            __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching                                           */
+            uint8_t               : 3;
+            __IOM uint8_t IRE     : 1; /*!< [7..7] IrDA Enable                                                        */
+        } IRCR_b;
+    };
+} R_IRDA_Type;                         /*!< Size = 1 (0x1)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Independent Watchdog Timer (R_IWDT)
+ */
+
+typedef struct                         /*!< (@ 0x40044400) R_IWDT Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
+
+        struct
+        {
+            __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
+                                        *   0xFF to this register.                                                    */
+        } IWDTRR_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+
+    union
+    {
+        __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter                         */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } IWDTSR_b;
+    };
+} R_IWDT_Type;                          /*!< Size = 6 (0x6)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_JPEG                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief JPEG Codec (R_JPEG)
+ */
+
+typedef struct                         /*!< (@ 0x400E6000) R_JPEG Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t JCMOD;           /*!< (@ 0x00000000) JPEG Code Mode Register                                    */
+
+        struct
+        {
+            __IOM uint8_t REDU : 3;    /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression.                      */
+            __IOM uint8_t DSP  : 1;    /*!< [3..3] Compression/Decompression Set Note: When changing between
+                                        *   processing for compression and for decompression, be sure
+                                        *   to reset this module in advance by setting the JCUSRST
+                                        *   bit in the software reset control register 2 (SWRSTCR2)
+                                        *   of the power-downmodes.                                                   */
+            uint8_t : 4;
+        } JCMOD_b;
+    };
+
+    union
+    {
+        __OM uint8_t JCCMD;            /*!< (@ 0x00000001) JPEG Code Command Register                                 */
+
+        struct
+        {
+            __OM uint8_t JSRT : 1;     /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing,
+                                        *   set this bit to 1. Do not write this bit to 1 again while
+                                        *   this module is in operation.                                              */
+            __OM uint8_t JRST : 1;     /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped
+                                        *   state caused by requests to read the image size and pixel
+                                        *   format (enabled by the INT3 bit in JINTE0), set this bit
+                                        *   to 1.                                                                     */
+            __OM uint8_t JEND : 1;     /*!< [2..2] Interrupt Request Clear Command This bit is valid only
+                                        *   for the interrupt sources corresponding to bits INS6, INS5,
+                                        *   and INS3 in JINTS0. To clear an interrupt request, set
+                                        *   this bit to 1                                                             */
+            uint8_t           : 4;
+            __OM uint8_t BRST : 1;     /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the
+                                        *   bus reset command should not be issued.                                   */
+        } JCCMD_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t JCQTN;           /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register               */
+
+        struct
+        {
+            __IOM uint8_t QT1 : 2;     /*!< [1..0] Quantization table number for the first color componentNOTE:
+                                        *   Read-only in Decompression.                                               */
+            __IOM uint8_t QT2 : 2;     /*!< [3..2] Quantization table number for the second color component
+                                        *   NOTE: Read-only in Decompression.                                         */
+            __IOM uint8_t QT3 : 2;     /*!< [5..4] Quantization table number for the third color component
+                                        *   NOTE: Read-only in Decompression.                                         */
+            uint8_t : 2;
+        } JCQTN_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCHTN;           /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register                    */
+
+        struct
+        {
+            __IOM uint8_t HTD1 : 1;    /*!< [0..0] Huffman table number (DC) for the first color component
+                                        *   NOTE: Read-only in Decompression.                                         */
+            __IOM uint8_t HTA1 : 1;    /*!< [1..1] Huffman table number (AC) for the first color componentNOTE:
+                                        *   Read-only in Decompression.                                               */
+            __IOM uint8_t HTD2 : 1;    /*!< [2..2] Huffman table number (DC) for the second color component
+                                        *   NOTE: Read-only in Decompression.                                         */
+            __IOM uint8_t HTA2 : 1;    /*!< [3..3] Huffman table number (AC) for the second color componentNOTE:
+                                        *   Read-only in Decompression.                                               */
+            __IOM uint8_t HTD3 : 1;    /*!< [4..4] Huffman table number (DC) for the third color component
+                                        *   NOTE: Read-only in Decompression.                                         */
+            __IOM uint8_t HTA3 : 1;    /*!< [5..5] Huffman table number (AC) for the third color componentNOTE:
+                                        *   Read-only in Decompression.                                               */
+            uint8_t : 2;
+        } JCHTN_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCDRIU;          /*!< (@ 0x00000005) JPEG Code DRI Upper Register                               */
+
+        struct
+        {
+            __IOM uint8_t DRIU : 8;    /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper
+                                        *   and lower bytes are set to 00h, neither a DRI nor an RST
+                                        *   marker is placed.NOTE: Read-only in Decompression.                        */
+        } JCDRIU_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCDRID;          /*!< (@ 0x00000006) JPEG Code DRI Lower Register                               */
+
+        struct
+        {
+            __IOM uint8_t DRID : 8;    /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper
+                                        *   and lower bytes are set to 00h, neither a DRI nor an RST
+                                        *   marker is placed.NOTE: Read-only in Decompression.                        */
+        } JCDRID_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCVSZU;          /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register                     */
+
+        struct
+        {
+            __IOM uint8_t VSZU : 8;    /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process,
+                                        *   a downloaded value from the JPEG coded data is set. NOTE:
+                                        *   Read-only in Decompression.                                               */
+        } JCVSZU_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCVSZD;          /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register                     */
+
+        struct
+        {
+            __IOM uint8_t VSZD : 8;    /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process,
+                                        *   a downloaded value from the JPEG coded data is set. NOTE:
+                                        *   Read-only in Decompression.                                               */
+        } JCVSZD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCHSZU;          /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register                   */
+
+        struct
+        {
+            __IOM uint8_t HSZU : 8;    /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression
+                                        *   process, a downloaded value from the JPEG coded data is
+                                        *   set. NOTE: Read-only in Decompression.                                    */
+        } JCHSZU_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCHSZD;          /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register                  */
+
+        struct
+        {
+            __IOM uint8_t HSZD : 8;    /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression
+                                        *   process, a downloaded value from the JPEG coded data is
+                                        *   set. NOTE: Read-only in Decompression.                                    */
+        } JCHSZD_b;
+    };
+
+    union
+    {
+        __IM uint8_t JCDTCU;           /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register                        */
+
+        struct
+        {
+            __IM uint8_t DCU : 8;      /*!< [7..0] Upper bytes of the counted amount of data to be compressed
+                                        *   The values of this register are reset before compression
+                                        *   starts.NOTE: Read-only in Decompression.                                  */
+        } JCDTCU_b;
+    };
+
+    union
+    {
+        __IM uint8_t JCDTCM;           /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register                       */
+
+        struct
+        {
+            __IM uint8_t DCM : 8;      /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe
+                                        *   values of this register are reset before compression starts.
+                                        *   NOTE: Read-only in Decompression.                                         */
+        } JCDTCM_b;
+    };
+
+    union
+    {
+        __IM uint8_t JCDTCD;           /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register                        */
+
+        struct
+        {
+            __IM uint8_t DCD : 8;      /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe
+                                        *   values of this register are reset before compression starts.NOTE:
+                                        *   Read-only in Decompression.                                               */
+        } JCDTCD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JINTE0;          /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0                           */
+
+        struct
+        {
+            uint8_t            : 3;
+            __IOM uint8_t INT3 : 1;    /*!< [3..3] This bit enables an interrupt to be generated when it
+                                        *   has been determined that the image size and the subsampling
+                                        *   setting of the compressed data can be read through analyzing
+                                        *   the data.                                                                 */
+            uint8_t            : 1;
+            __IOM uint8_t INT5 : 1;    /*!< [5..5] This bit enables an interrupt to be generated when the
+                                        *   final number of MCU data in the Huffman-coding segment
+                                        *   is not correct in decompression. When this bit is not set
+                                        *   to enable interrupt generation, an error code is not returned.            */
+            __IOM uint8_t INT6 : 1;    /*!< [6..6] This bit enables an interrupt to be generated when the
+                                        *   total number of data in the Huffman-coding segment is not
+                                        *   correct in decompression. When this bit is not set to enable
+                                        *   interrupt generation, an error code is not returned.                      */
+            __IOM uint8_t INT7 : 1;    /*!< [7..7] This bit enables an interrupt to be generated when the
+                                        *   number of data in the restart interval of the Huffman-coding
+                                        *   segment is not correct in decompression.When this bit is
+                                        *   not set to enable interrupt generation, an error code is
+                                        *   not returned.                                                             */
+        } JINTE0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JINTS0;          /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0                           */
+
+        struct
+        {
+            uint8_t            : 3;
+            __IOM uint8_t INS3 : 1;    /*!< [3..3] This bit is set to 1 when the image size and pixel format
+                                        *   can be read. When an interrupt occurs, this module stops
+                                        *   processing and the state is indicated by the JCRST register.
+                                        *   To make this module resume processing, set the JPEG core
+                                        *   process stop clear command bit (JRST) in JCCMD.                           */
+            uint8_t            : 1;
+            __IOM uint8_t INS5 : 1;    /*!< [5..5] This bit is set to 1 when a compressed data error occurs.          */
+            __IOM uint8_t INS6 : 1;    /*!< [6..6] This bit is set to 1 when this module completes compression
+                                        *   process normally.                                                         */
+            uint8_t : 1;
+        } JINTS0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t JCDERR;          /*!< (@ 0x00000010) JPEG Code Decode Error Register                            */
+
+        struct
+        {
+            __IOM uint8_t ERR : 4;     /*!< [3..0] Error Code (See tables )Identify the type of the error
+                                        *   which has occurred in the compressed data analysis for
+                                        *   decompression.                                                            */
+            uint8_t : 4;
+        } JCDERR_b;
+    };
+
+    union
+    {
+        __IM uint8_t JCRST;            /*!< (@ 0x00000011) JPEG Code Reset Register                                   */
+
+        struct
+        {
+            __IM uint8_t RST : 1;      /*!< [0..0] Operating State                                                    */
+            uint8_t          : 7;
+        } JCRST_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[11];
+
+    union
+    {
+        __IOM uint32_t JIFECNT;          /*!< (@ 0x00000040) JPEG Interface Compression Control Register                */
+
+        struct
+        {
+            __IOM uint32_t DINSWAP : 3;  /*!< [2..0] Byte/Halfword Swap                                                 */
+            uint32_t               : 1;
+            __IOM uint32_t DINLC   : 1;  /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines             */
+            __OM uint32_t  DINRCMD : 1;  /*!< [5..5] Input Image Data Lines Resume Command This bit is valid
+                                          *   only when the count mode for stopping the input of image
+                                          *   data lines is on. Setting this bit to 1 resumes reading
+                                          *   input image data. This bit is always read as 0.                           */
+            __IOM uint32_t DINRINI : 1;  /*!< [6..6] Address Initialization when Resuming Input of Image Data
+                                          *   Lines This bit is only valid when the count mode for stopping
+                                          *   the input of image data lines is on. Set this bit before
+                                          *   writing 1 to the data-line resume command bit.                            */
+            uint32_t                : 1;
+            __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression
+                                          *   is swapped.                                                               */
+            uint32_t : 21;
+        } JIFECNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFESA;         /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register         */
+
+        struct
+        {
+            __IOM uint32_t ESA : 32;   /*!< [31..0] Input Image Data Source Address (in 8-byte units) The
+                                        *   lower three bits should be set to 0.                                      */
+        } JIFESA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFESOFST;      /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register            */
+
+        struct
+        {
+            __IOM uint32_t ESMW : 15;  /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower
+                                        *   three bits should be set to 0.                                            */
+            uint32_t : 17;
+        } JIFESOFST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFEDA;         /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t EDA : 32;   /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The
+                                        *   lower three bits should be set to 0.                                      */
+        } JIFEDA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFESLC;        /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line
+                                        *   units) The lower three bits should be set to 0.                           */
+            uint32_t : 16;
+        } JIFESLC_b;
+    };
+    __IM uint32_t RESERVED3;
+
+    union
+    {
+        __IOM uint32_t JIFDCNT;          /*!< (@ 0x00000058) JPEG Interface Decompression Control Register              */
+
+        struct
+        {
+            __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is
+                                          *   swapped.                                                                  */
+            uint32_t                : 1;
+            __IOM uint32_t DOUTLC   : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines                    */
+            __OM uint32_t  DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid
+                                          *   only when the count mode for stopping the output of image
+                                          *   data lines is on. Setting this bit to 1 resumes writing
+                                          *   image data. This bit is always read as 0.                                 */
+            __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image
+                                          *   Data Lines This bit is only valid when the count mode for
+                                          *   stopping the output of image data lines is on. Set this
+                                          *   bit before writing 1 to the data-line resume command bit.                 */
+            uint32_t               : 1;
+            __IOM uint32_t JINSWAP : 3;  /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression
+                                          *   is swapped.                                                               */
+            uint32_t               : 1;
+            __IOM uint32_t JINC    : 1;  /*!< [12..12] Count Mode Setting for Stopping Input Coded Data                 */
+            __OM uint32_t  JINRCMD : 1;  /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only
+                                          *   when the count mode for stopping the input of coded data
+                                          *   is on. Setting this bit to 1 resumes reading input coded
+                                          *   data. This bit is always read as 0.                                       */
+            __IOM uint32_t JINRINI : 1;  /*!< [14..14] Address Initialization when Input Coded Data is Resumed
+                                          *   This bit is only valid when the count mode for stopping
+                                          *   the input of coded data is on. Set this bit before writing
+                                          *   1 to the data resume command bit.                                         */
+            uint32_t              : 9;
+            __IOM uint32_t OPF    : 2;   /*!< [25..24] Specifies output image data pixel format.                        */
+            __IOM uint32_t HINTER : 2;   /*!< [27..26] Horizontal Subsampling Subsamples horizontal output
+                                          *   image data.                                                               */
+            __IOM uint32_t VINTER : 2;   /*!< [29..28] Vertical SubsamplingSubsamples vertical output image
+                                          *   data.                                                                     */
+            uint32_t : 2;
+        } JIFDCNT_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDSA;         /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register       */
+
+        struct
+        {
+            __IOM uint32_t DSA : 32;   /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source
+                                        *   Address (in 8-byte units) The lower three bits should be
+                                        *   set to 0.                                                                 */
+        } JIFDSA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDDOFST;      /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register          */
+
+        struct
+        {
+            __IOM uint32_t DDMW : 15;  /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The
+                                        *   lower three bits should be set to 0.                                      */
+            uint32_t : 17;
+        } JIFDDOFST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDDA;         /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DDA : 32;   /*!< [31..0] Output Image Data Destination Address (in 8-byte units)
+                                        *   The lower three bits should be set to 0.                                  */
+        } JIFDDA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDSDC;         /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count
+                                         *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units)
+                                         *   The lower three bits should be set to 0.                                  */
+            uint32_t : 16;
+        } JIFDSDC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDDLC;        /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line
+                                        *                  Count Register                                             */
+
+        struct
+        {
+            __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three
+                                        *   bits should be set to 0. These bits are read as0.Number
+                                        *   of input image data lines to be read, in 8-line units.                    */
+            uint32_t : 16;
+        } JIFDDLC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JIFDADT;        /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register            */
+
+        struct
+        {
+            __IOM uint32_t ALPHA : 8;  /*!< [7..0] Setting of the alpha value for output in ARGB8888 format.          */
+            uint32_t             : 24;
+        } JIFDADT_b;
+    };
+    __IM uint32_t RESERVED4[6];
+
+    union
+    {
+        __IOM uint32_t JINTE1;          /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1                           */
+
+        struct
+        {
+            __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt
+                                         *   request (JDTI) when the DOUTLF bit in JINTS1 is set to
+                                         *   1                                                                         */
+            __IOM uint32_t JINEN : 1;   /*!< [1..1] Enables or disables a data transfer processing interrupt
+                                         *   request (JDTI) when the JINF bit in JINTS1 is set to 1.                   */
+            __IOM uint32_t DBTEN : 1;   /*!< [2..2] Enables or disables a data transfer processing interrupt
+                                         *   request (JDTI) when the DBTF bit in JINTS1 is set to 1.                   */
+            uint32_t              : 2;
+            __IOM uint32_t DINLEN : 1;  /*!< [5..5] Enables or disables a data transfer processing interrupt
+                                         *   request (JDTI) when the DINLF bit in JINTS1 is set to 1.                  */
+            __IOM uint32_t CBTEN : 1;   /*!< [6..6] Enables or disables a data transfer processing interrupt
+                                         *   request (JDTI) when the CBTF bit in JINTS1 is set to 1.                   */
+            uint32_t : 25;
+        } JINTE1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t JINTS1;         /*!< (@ 0x00000090) JPEG Interrupt Status Register 1                           */
+
+        struct
+        {
+            __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number
+                                        *   of lines of output image data indicated by JIFDDLC have
+                                        *   been written. This bit is only valid when the DOUTLC bit
+                                        *   in JIFDCNT is set to 1.                                                   */
+            __IOM uint32_t JINF : 1;   /*!< [1..1] This bit is set to 1 when the amount of input coded data
+                                        *   indicated by JIFDSDC is read in decompression. This bit
+                                        *   is valid only when the JINC bit in JIFDCNT is set to 1.                   */
+            __IOM uint32_t DBTF : 1;   /*!< [2..2] This bit is set to 1 when the last output image data
+                                        *   is written in decompression.                                              */
+            uint32_t             : 2;
+            __IOM uint32_t DINLF : 1;  /*!< [5..5] This bit is set to 1 when the number of input image data
+                                        *   lines indicated by JIFESLC is read in compression. This
+                                        *   bit is valid only when the DINLC bit in JIFECNT is set
+                                        *   to 1.                                                                     */
+            __IOM uint32_t CBTF : 1;   /*!< [6..6] This bit is set to 1 when the last output coded data
+                                        *   is written in compression.                                                */
+            uint32_t : 25;
+        } JINTS1_b;
+    };
+    __IM uint32_t RESERVED5[27];
+    __OM uint8_t  JCQTBL0[64];         /*!< (@ 0x00000100) Quantization Table 0                                       */
+    __OM uint8_t  JCQTBL1[64];         /*!< (@ 0x00000140) Quantization Table 1                                       */
+    __OM uint8_t  JCQTBL2[64];         /*!< (@ 0x00000180) Quantization Table 2                                       */
+    __OM uint8_t  JCQTBL3[64];         /*!< (@ 0x000001C0) Quantization Table 3                                       */
+    __IOM uint8_t JCHTBD0[28];         /*!< (@ 0x00000200) DC Huffman Table 0                                         */
+    __IM uint32_t RESERVED6;
+    __IOM uint8_t JCHTBA0[178];        /*!< (@ 0x00000220) AC Huffman Table 0                                         */
+    __IM uint16_t RESERVED7;
+    __IM uint32_t RESERVED8[11];
+    __IOM uint8_t JCHTBD1[28];         /*!< (@ 0x00000300) DC Huffman Table 1                                         */
+    __IM uint32_t RESERVED9;
+    __IOM uint8_t JCHTBA1[178];        /*!< (@ 0x00000320) DC Huffman Table 1                                         */
+    __IM uint16_t RESERVED10;
+} R_JPEG_Type;                         /*!< Size = 980 (0x3d4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_KINT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Key Interrupt Function (R_KINT)
+ */
+
+typedef struct                         /*!< (@ 0x40080000) R_KINT Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t KRCTL;           /*!< (@ 0x00000000) KEY Return Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t KREG : 1;    /*!< [0..0] Detection Edge Selection (KRF0 to KRF7)                            */
+            uint8_t            : 6;
+            __IOM uint8_t KRMD : 1;    /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7)                           */
+        } KRCTL_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t KRF;             /*!< (@ 0x00000004) KEY Return Flag Register                                   */
+
+        struct
+        {
+            __IOM uint8_t KRF0 : 1;    /*!< [0..0] Key interrupt flag 0                                               */
+            __IOM uint8_t KRF1 : 1;    /*!< [1..1] Key interrupt flag 1                                               */
+            __IOM uint8_t KRF2 : 1;    /*!< [2..2] Key interrupt flag 2                                               */
+            __IOM uint8_t KRF3 : 1;    /*!< [3..3] Key interrupt flag 3                                               */
+            __IOM uint8_t KRF4 : 1;    /*!< [4..4] Key interrupt flag 4                                               */
+            __IOM uint8_t KRF5 : 1;    /*!< [5..5] Key interrupt flag 5                                               */
+            __IOM uint8_t KRF6 : 1;    /*!< [6..6] Key interrupt flag 6                                               */
+            __IOM uint8_t KRF7 : 1;    /*!< [7..7] Key interrupt flag 7                                               */
+        } KRF_b;
+    };
+    __IM uint8_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t KRM;             /*!< (@ 0x00000008) KEY Return Mode Register                                   */
+
+        struct
+        {
+            __IOM uint8_t KRM0 : 1;    /*!< [0..0] Key interrupt mode control 0                                       */
+            __IOM uint8_t KRM1 : 1;    /*!< [1..1] Key interrupt mode control 1                                       */
+            __IOM uint8_t KRM2 : 1;    /*!< [2..2] Key interrupt mode control 2                                       */
+            __IOM uint8_t KRM3 : 1;    /*!< [3..3] Key interrupt mode control 3                                       */
+            __IOM uint8_t KRM4 : 1;    /*!< [4..4] Key interrupt mode control 4                                       */
+            __IOM uint8_t KRM5 : 1;    /*!< [5..5] Key interrupt mode control 5                                       */
+            __IOM uint8_t KRM6 : 1;    /*!< [6..6] Key interrupt mode control 6                                       */
+            __IOM uint8_t KRM7 : 1;    /*!< [7..7] Key interrupt mode control 7                                       */
+        } KRM_b;
+    };
+} R_KINT_Type;                         /*!< Size = 9 (0x9)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MMF                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Memory Mirror Function (R_MMF)
+ */
+
+typedef struct                         /*!< (@ 0x40001000) R_MMF Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t MMSFR;          /*!< (@ 0x00000000) MemMirror Special Function Register                        */
+
+        struct
+        {
+            uint32_t                  : 7;
+            __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot
+                                             *   be set in the low-order 7 bits. These bits are fixed to
+                                             *   0.                                                                        */
+            uint32_t          : 1;
+            __OM uint32_t KEY : 8;          /*!< [31..24] MMSFR Key Code                                                   */
+        } MMSFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MMEN;           /*!< (@ 0x00000004) MemMirror Enable Register                                  */
+
+        struct
+        {
+            __IOM uint32_t EN : 1;     /*!< [0..0] Memory Mirror Function Enable                                      */
+            uint32_t          : 23;
+            __OM uint32_t KEY : 8;     /*!< [31..24] MMEN Key Code                                                    */
+        } MMEN_b;
+    };
+} R_MMF_Type;                          /*!< Size = 8 (0x8)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_MMPU                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Master MPU (R_MPU_MMPU)
+ */
+
+typedef struct                          /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
+{
+    __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers                                   */
+} R_MPU_MMPU_Type;                      /*!< Size = 3072 (0xc00)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SMPU                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Bus Slave MPU (R_MPU_SMPU)
+ */
+
+typedef struct                           /*!< (@ 0x40000C00) R_MPU_SMPU Structure                                       */
+{
+    union
+    {
+        __IOM uint16_t SMPUCTL;          /*!< (@ 0x00000000) Slave MPU Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t OAD     : 1;  /*!< [0..0] Master Group enable                                                */
+            __IOM uint16_t PROTECT : 1;  /*!< [1..1] Protection of register                                             */
+            uint16_t               : 6;
+            __OM uint16_t KEY      : 8;  /*!< [15..8] Key Code This bit is used to enable or disable rewriting
+                                          *   of the PROTECT and OAD bit.                                               */
+        } SMPUCTL_b;
+    };
+    __IM uint16_t              RESERVED[7];
+    __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU                          */
+} R_MPU_SMPU_Type;                       /*!< Size = 56 (0x38)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
+ */
+
+typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
+{
+    __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
+} R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System-Module Stop (R_MSTP)
+ */
+
+typedef struct                         /*!< (@ 0x40047000) R_MSTP Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t MSTPCRB;        /*!< (@ 0x00000000) Module Stop Control Register B                             */
+
+        struct
+        {
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB1  : 1; /*!< [1..1] RCAN1 Module Stop                                                  */
+            __IOM uint32_t MSTPB2  : 1; /*!< [2..2] RCAN0 Module Stop                                                  */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPB5  : 1; /*!< [5..5] IrDA Module Stop                                                   */
+            __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop                     */
+            __IOM uint32_t MSTPB7  : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop                                    */
+            __IOM uint32_t MSTPB8  : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop                                    */
+            __IOM uint32_t MSTPB9  : 1; /*!< [9..9] I2C Bus Interface 0 Module Stop                                    */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop                */
+            __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop                */
+            __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop                                   */
+            __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop                                   */
+            __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop                                   */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop                          */
+            __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop                        */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop                     */
+            __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop                     */
+            __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop                     */
+            __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop                     */
+            __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop                     */
+            __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop                     */
+            __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop                     */
+            __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop                     */
+            __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop                     */
+            __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop                     */
+        } MSTPCRB_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000004) Module Stop Control Register C                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPC0  : 1; /*!< [0..0] CAC Module Stop                                                    */
+            __IOM uint32_t MSTPC1  : 1; /*!< [1..1] CRC Calculator Module Stop                                         */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop                          */
+            __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Segment LCD Controller Module Stop                                 */
+            uint32_t               : 8;
+            __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop                               */
+            __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop                                */
+            uint32_t               : 13;
+            __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop                              */
+            uint32_t               : 2;
+            __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop                                                  */
+        } MSTPCRC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t MSTPCRD;        /*!< (@ 0x00000008) Module Stop Control Register D                             */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IOM uint32_t MSTPD2 : 1;  /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT1.                                                                  */
+            __IOM uint32_t MSTPD3 : 1;  /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state
+                                         *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
+                                         *   In case the count source is sub-clock or LOCO, this bit
+                                         *   should be set to 1 except when accessing the registers
+                                         *   of AGT0.                                                                  */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD5  : 1; /*!< [5..5] GPT ch0 Module Stop                                                */
+            __IOM uint32_t MSTPD6  : 1; /*!< [6..6] GPT ch6 - ch1 Module Stop                                          */
+            uint32_t               : 7;
+            __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop                                                 */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop                                 */
+            __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop                      */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop                                  */
+            __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop                                 */
+            uint32_t               : 7;
+            __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop                                              */
+            __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop                                        */
+            uint32_t               : 1;
+            __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop                                */
+        } MSTPCRD_b;
+    };
+} R_MSTP_Type;                          /*!< Size = 12 (0xc)                                                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_OPAMP                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Operational Amplifier (R_OPAMP)
+ */
+
+typedef struct                         /*!< (@ 0x40086000) R_OPAMP Structure                                          */
+{
+    __IM uint8_t RESERVED[8];
+
+    union
+    {
+        __IOM uint8_t AMPMC;           /*!< (@ 0x00000008) Operational amplifier mode control register                */
+
+        struct
+        {
+            __IOM uint8_t AMPPC0 : 1;  /*!< [0..0] Operational amplifier precharge control status                     */
+            __IOM uint8_t AMPPC1 : 1;  /*!< [1..1] Operational amplifier precharge control status                     */
+            __IOM uint8_t AMPPC2 : 1;  /*!< [2..2] Operational amplifier precharge control status                     */
+            uint8_t              : 4;
+            __IOM uint8_t AMPSP  : 1;  /*!< [7..7] Operation mode selection                                           */
+        } AMPMC_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AMPTRM;          /*!< (@ 0x00000009) Operational amplifier trigger mode control register        */
+
+        struct
+        {
+            __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger
+                                        *   control                                                                   */
+            __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger
+                                        *   control                                                                   */
+            __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger
+                                        *   control                                                                   */
+            __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger
+                                        *   control                                                                   */
+        } AMPTRM_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AMPTRS;          /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t AMPTRS : 2;  /*!< [1..0] ELC trigger selection Do not change the value of the
+                                        *   AMPTRS register after setting the AMPTRM register.                        */
+            uint8_t : 6;
+        } AMPTRS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t AMPC;            /*!< (@ 0x0000000B) Operational amplifier control register                     */
+
+        struct
+        {
+            __IOM uint8_t AMPE0 : 1;   /*!< [0..0] Operation control of operational amplifier                         */
+            __IOM uint8_t AMPE1 : 1;   /*!< [1..1] Operation control of operational amplifier                         */
+            __IOM uint8_t AMPE2 : 1;   /*!< [2..2] Operation control of operational amplifier                         */
+            __IOM uint8_t AMPE3 : 1;   /*!< [3..3] Operation control of operational amplifier                         */
+            uint8_t             : 3;
+            __IOM uint8_t IREFE : 1;   /*!< [7..7] Operation control of operational amplifier reference
+                                        *   current circuit                                                           */
+        } AMPC_b;
+    };
+
+    union
+    {
+        __IM uint8_t AMPMON;           /*!< (@ 0x0000000C) Operational amplifier monitor register                     */
+
+        struct
+        {
+            __IM uint8_t AMPMON0 : 1;  /*!< [0..0] Operational amplifier status                                       */
+            __IM uint8_t AMPMON1 : 1;  /*!< [1..1] Operational amplifier status                                       */
+            __IM uint8_t AMPMON2 : 1;  /*!< [2..2] Operational amplifier status                                       */
+            __IM uint8_t AMPMON3 : 1;  /*!< [3..3] Operational amplifier status                                       */
+            uint8_t              : 4;
+        } AMPMON_b;
+    };
+    __IM uint8_t           RESERVED1;
+    __IOM R_OPAMP_AMP_Type AMP[4];     /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier
+                                        *                  [0..3]                                                     */
+
+    union
+    {
+        __IOM uint8_t AMPCPC;          /*!< (@ 0x0000001A) Operational amplifier switch charge pump control
+                                        *                  register                                                   */
+
+        struct
+        {
+            __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable                                */
+            __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable                                */
+            __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable                                */
+            uint8_t               : 5;
+        } AMPCPC_b;
+    };
+    __IM uint8_t RESERVED2[4];
+
+    union
+    {
+        __IOM uint8_t AMPUOTE;         /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable
+                                        *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t AMP0TE : 1;  /*!< [0..0] AMP0OT write enable                                                */
+            __IOM uint8_t AMP1TE : 1;  /*!< [1..1] AMP1OT write enable                                                */
+            __IOM uint8_t AMP2TE : 1;  /*!< [2..2] AMP2OT write enable                                                */
+            uint8_t              : 5;
+        } AMPUOTE_b;
+    };
+    __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers          */
+} R_OPAMP_Type;                        /*!< Size = 38 (0x26)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PDC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Parallel Data Capture Unit (R_PDC)
+ */
+
+typedef struct                         /*!< (@ 0x40094000) R_PDC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t PCCR0;          /*!< (@ 0x00000000) PDC Control Register 0                                     */
+
+        struct
+        {
+            __IOM uint32_t PCKE   : 1; /*!< [0..0] Channel 0 GTCNT Count Clear                                        */
+            __IOM uint32_t VPS    : 1; /*!< [1..1] VSYNC Signal Polarity Select                                       */
+            __IOM uint32_t HPS    : 1; /*!< [2..2] HSYNC Signal Polarity Select                                       */
+            __OM uint32_t  PRST   : 1; /*!< [3..3] PDC Reset                                                          */
+            __IOM uint32_t DFIE   : 1; /*!< [4..4] Receive Data Ready Interrupt Enable                                */
+            __IOM uint32_t FEIE   : 1; /*!< [5..5] Frame End Interrupt Enable                                         */
+            __IOM uint32_t OVIE   : 1; /*!< [6..6] Overrun Interrupt Enable                                           */
+            __IOM uint32_t UDRIE  : 1; /*!< [7..7] Underrun Interrupt Enable                                          */
+            __IOM uint32_t VERIE  : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable                */
+            __IOM uint32_t HERIE  : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable              */
+            __IOM uint32_t PCKOE  : 1; /*!< [10..10] PCKO Output Enable                                               */
+            __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select                             */
+            __IOM uint32_t EDS    : 1; /*!< [14..14] Endian Select                                                    */
+            uint32_t              : 17;
+        } PCCR0_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCCR1;          /*!< (@ 0x00000004) PDC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint32_t PCE : 1;    /*!< [0..0] PDC Operation Enable                                               */
+            uint32_t           : 31;
+        } PCCR1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t PCSR;           /*!< (@ 0x00000008) PDC Status Register                                        */
+
+        struct
+        {
+            __IM uint32_t  FBSY  : 1;  /*!< [0..0] Frame Busy Flag                                                    */
+            __IM uint32_t  FEMPF : 1;  /*!< [1..1] FIFO Empty Flag                                                    */
+            __IOM uint32_t FEF   : 1;  /*!< [2..2] Frame End Flag                                                     */
+            __IOM uint32_t OVRF  : 1;  /*!< [3..3] Overrun Flag                                                       */
+            __IOM uint32_t UDRF  : 1;  /*!< [4..4] Underrun Flag                                                      */
+            __IOM uint32_t VERF  : 1;  /*!< [5..5] Vertical Line Number Setting Error Flag                            */
+            __IOM uint32_t HERF  : 1;  /*!< [6..6] Horizontal Byte Number Setting Error Flag                          */
+            uint32_t             : 25;
+        } PCSR_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCMONR;          /*!< (@ 0x0000000C) PDC Pin Monitor Register                                   */
+
+        struct
+        {
+            __IM uint32_t VSYNC : 1;   /*!< [0..0] VSYNC Signal Status Flag                                           */
+            __IM uint32_t HSYNC : 1;   /*!< [1..1] HSYNC Signal Status Flag                                           */
+            uint32_t            : 30;
+        } PCMONR_b;
+    };
+
+    union
+    {
+        __IM uint32_t PCDR;            /*!< (@ 0x00000010) PDC Receive Data Register                                  */
+
+        struct
+        {
+            __IM uint32_t PCDR : 32;   /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the
+                                        *   storage of captured data. The PCDR register is a 4-byte
+                                        *   space to which the FIFO is mapped, and four bytes of data
+                                        *   are read from the PCDR register at a time.                                */
+        } PCDR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t VCR;            /*!< (@ 0x00000014) Vertical Capture Register                                  */
+
+        struct
+        {
+            __IOM uint32_t VST : 12;   /*!< [11..0] Vertical Capture Start Line PositionNumber of the line
+                                        *   where capture is to start.                                                */
+            uint32_t           : 4;
+            __IOM uint32_t VSZ : 12;   /*!< [27..16] Vertical Capture Size Number of lines to be captured.            */
+            uint32_t           : 4;
+        } VCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t HCR;            /*!< (@ 0x00000018) Horizontal Capture Register                                */
+
+        struct
+        {
+            __IOM uint32_t HST : 12;   /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position
+                                        *   in bytes where capture is to start.                                       */
+            uint32_t           : 4;
+            __IOM uint32_t HSZ : 12;   /*!< [27..16] Horizontal Capture Size Number of bytes to capture
+                                        *   horizontally.                                                             */
+            uint32_t : 4;
+        } HCR_b;
+    };
+} R_PDC_Type;                          /*!< Size = 28 (0x1c)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports (R_PORT0)
+ */
+
+typedef struct                         /*!< (@ 0x40040000) R_PORT0 Structure                                          */
+{
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
+
+            struct
+            {
+                __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
+                __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
+            } PCNTR1_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
+
+                struct
+                {
+                    __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
+                    __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
+                    __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
+                } PODR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
+
+                struct
+                {
+                    __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
+                    __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
+                    __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
+                    __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
+                    __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
+                    __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
+                    __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
+                    __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
+                    __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
+                    __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
+                    __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
+                    __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
+                    __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
+                    __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
+                    __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
+                    __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
+                } PDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
+
+            struct
+            {
+                __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
+                __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
+            } PCNTR2_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
+
+                struct
+                {
+                    __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
+                    __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
+                    __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
+                } EIDR_b;
+            };
+
+            union
+            {
+                __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
+
+                struct
+                {
+                    __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
+                    __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
+                    __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
+                } PIDR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
+
+            struct
+            {
+                __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
+                __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
+            } PCNTR3_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
+
+                struct
+                {
+                    __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
+                    __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
+                    __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
+                } PORR_b;
+            };
+
+            union
+            {
+                __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
+
+                struct
+                {
+                    __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
+                    __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
+                    __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
+                    __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
+                    __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
+                    __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
+                    __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
+                    __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
+                    __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
+                    __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
+                    __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
+                    __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
+                    __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
+                    __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
+                    __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
+                    __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
+                } POSR_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
+
+            struct
+            {
+                __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
+                __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
+            } PCNTR4_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
+
+                struct
+                {
+                    __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
+                    __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
+                    __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
+                } EORR_b;
+            };
+
+            union
+            {
+                __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
+
+                struct
+                {
+                    __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
+                    __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
+                    __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
+                } EOSR_b;
+            };
+        };
+    };
+} R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-PFS (R_PFS)
+ */
+
+typedef struct                         /*!< (@ 0x40040800) R_PFS Structure                                            */
+{
+    __IOM R_PFS_PORT_Type PORT[12];    /*!< (@ 0x00000000) Port [0..11]                                               */
+} R_PFS_Type;                          /*!< Size = 768 (0x300)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief I/O Ports-MISC (R_PMISC)
+ */
+
+typedef struct                         /*!< (@ 0x40040D00) R_PMISC Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
+
+        struct
+        {
+            uint8_t                : 4;
+            __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
+            __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
+            uint8_t                : 2;
+        } PFENET_b;
+    };
+    __IM uint8_t RESERVED[2];
+
+    union
+    {
+        __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
+
+        struct
+        {
+            uint8_t             : 6;
+            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
+            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
+        } PWPR_b;
+    };
+} R_PMISC_Type;                        /*!< Size = 4 (0x4)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_QSPI                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Quad Serial Peripheral Interface (R_QSPI)
+ */
+
+typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
+
+        struct
+        {
+            __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
+            uint32_t              : 1;
+            __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
+            __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
+            __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
+                                        *   other than on byte boundaries                                             */
+            __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
+                                        *   input to CFGMD3.                                                          */
+            __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
+                                        *   the serial interface                                                      */
+            __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
+            __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
+            uint32_t              : 3;
+            __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
+            uint32_t              : 16;
+        } SFMSMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
+            __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
+            __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
+            uint32_t              : 26;
+        } SFMSSC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
+
+        struct
+        {
+            __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
+                                        *   to the irregularity.)NOTE: When PCLKA multiplied by an
+                                        *   odd number is selected, the high-level width of the SCK
+                                        *   signal is longer than the low-level width by 1 x PCLKA
+                                        *   before duty ratio correction.                                             */
+            __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
+                                        *   SCK signal                                                                */
+            uint32_t : 26;
+        } SFMSKC_b;
+    };
+
+    union
+    {
+        __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
+                                        *   (No combination other than the above is available.)                       */
+            uint32_t            : 1;
+            __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
+            __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
+            uint32_t            : 24;
+        } SFMSST_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
+
+        struct
+        {
+            __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
+                                        *   to and from this port is converted to a SPIbus cycle. This
+                                        *   port is accessible in the direct communication mode (DCOM=1)
+                                        *   only.Access to this port is ignored in the ROM access mode.               */
+            uint32_t : 24;
+        } SFMCOM_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
+
+        struct
+        {
+            __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
+            uint32_t            : 31;
+        } SFMCMD_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
+
+        struct
+        {
+            __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
+            uint32_t             : 6;
+            __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
+                                        *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
+                                        *   ignored.                                                                  */
+            uint32_t : 24;
+        } SFMCST_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
+
+        struct
+        {
+            __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
+            uint32_t              : 24;
+        } SFMSIC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
+            uint32_t              : 2;
+            __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
+                                        *   Interface address width is selected 4 bytes.                              */
+            uint32_t : 27;
+        } SFMSAC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
+
+        struct
+        {
+            __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
+                                        *   instructions                                                              */
+            uint32_t              : 2;
+            __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
+            __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
+            __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
+            uint32_t              : 16;
+        } SFMSDC_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
+
+        struct
+        {
+            __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
+                                        *   is required to be set by software separately.                             */
+            uint32_t              : 2;
+            __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
+                                        *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
+            uint32_t : 27;
+        } SFMSPC_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
+
+        struct
+        {
+            uint32_t              : 2;
+            __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
+            uint32_t              : 29;
+        } SFMPMD_b;
+    };
+    __IM uint32_t RESERVED2[499];
+
+    union
+    {
+        __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
+
+        struct
+        {
+            uint32_t                : 26;
+            __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
+                                          *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
+                                          *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
+        } SFMCNT1_b;
+    };
+} R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Realtime Clock (R_RTC)
+ */
+
+typedef struct                         /*!< (@ 0x40044000) R_RTC Structure                                            */
+{
+    union
+    {
+        __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
+
+        struct
+        {
+            __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
+            __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
+            __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
+            __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
+            __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
+            __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
+            __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
+            uint8_t            : 1;
+        } R64CNT_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
+                uint8_t             : 1;
+            } RSECCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
+                                          *   counter b7 to b0.                                                         */
+            } BCNT0_b;
+        };
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
+
+            struct
+            {
+                __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
+                                          *   a carry is generated, 1 is added to the tens place.                       */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
+                uint8_t             : 1;
+            } RMINCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
+                                          *   counter b15 to b8.                                                        */
+            } BCNT1_b;
+        };
+    };
+    __IM uint8_t RESERVED2;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
+
+            struct
+            {
+                __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
+                                         *   carry is generated, 1 is added to the tens place.                         */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
+                                         *   the ones place.                                                           */
+                __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                uint8_t          : 1;
+            } RHRCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
+                                          *   counter b23 to b16.                                                       */
+            } BCNT2_b;
+        };
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 5;
+            } RWKCNT_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
+
+            struct
+            {
+                __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
+                                          *   counter b31 to b24.                                                       */
+            } BCNT3_b;
+        };
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
+
+        struct
+        {
+            __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
+                                        *   is generated, 1 is added to the tens place.                               */
+            __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
+                                        *   ones place.                                                               */
+            uint8_t : 2;
+        } RDAYCNT_b;
+    };
+    __IM uint8_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
+
+        struct
+        {
+            __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
+                                        *   a carry is generated, 1 is added to the tens place.                       */
+            __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
+                                        *   the ones place.                                                           */
+            uint8_t : 3;
+        } RMONCNT_b;
+    };
+    __IM uint8_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
+
+        struct
+        {
+            __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
+                                        *   carry is generated, 1 is added to the tens place.                         */
+            __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
+                                        *   ones place. When a carry is generated in the tens place,
+                                        *   1 is added to the hundreds place.                                         */
+            uint16_t : 8;
+        } RYRCNT_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
+
+            struct
+            {
+                __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
+                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RSECAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b7 to b0.                          */
+            } BCNT0AR_b;
+        };
+    };
+    __IM uint8_t RESERVED7;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
+
+            struct
+            {
+                __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
+                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMINAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
+                                            *   corresponding to 32-bit binary counter b15 to b8.                         */
+            } BCNT1AR_b;
+        };
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
+                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
+                __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RHRAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
+                                            *   counter b23 to b16.                                                       */
+            } BCNT2AR_b;
+        };
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
+
+            struct
+            {
+                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
+                uint8_t            : 4;
+                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
+            } RWKAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
+
+            struct
+            {
+                __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
+                                            *   counter b31 to b24.                                                       */
+            } BCNT3AR_b;
+        };
+    };
+    __IM uint8_t RESERVED10;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
+                __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
+                uint8_t              : 1;
+                __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
+            } RDAYAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b7 to b0.                                                         */
+            } BCNT0AER_b;
+        };
+    };
+    __IM uint8_t RESERVED11;
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
+
+            struct
+            {
+                __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
+                __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
+                uint8_t             : 2;
+                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
+            } RMONAR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b15 to b8.                                                        */
+            } BCNT1AER_b;
+        };
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
+
+            struct
+            {
+                __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
+                __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
+                uint16_t            : 8;
+            } RYRAR_b;
+        };
+
+        union
+        {
+            __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
+                                         *   for setting the alarm enable corresponding to 32-bit binary
+                                         *   counter b23 to b16.                                                       */
+                uint16_t : 8;
+            } BCNT2AER_b;
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
+
+            struct
+            {
+                uint8_t           : 7;
+                __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
+            } RYRAREN_b;
+        };
+
+        union
+        {
+            __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
+
+            struct
+            {
+                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
+                                        *   for setting the alarm enable corresponding to 32-bit binary
+                                        *   counter b31 to b24.                                                       */
+            } BCNT3AER_b;
+        };
+    };
+    __IM uint8_t  RESERVED13;
+    __IM uint16_t RESERVED14;
+
+    union
+    {
+        __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
+            __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
+            __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
+            __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
+            __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
+        } RCR1_b;
+    };
+    __IM uint8_t RESERVED15;
+
+    union
+    {
+        __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
+            __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
+            __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
+            __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
+            __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
+                                        *   the setting of this bit is disabled.)                                     */
+            __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
+                                        *   is selected, the setting of this bit is disabled.)                        */
+            __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
+            __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
+        } RCR2_b;
+    };
+    __IM uint8_t  RESERVED16;
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
+
+        struct
+        {
+            __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
+            uint8_t              : 6;
+            __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
+        } RCR4_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
+                                        *   clock from the LOCOclock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+            uint16_t : 15;
+        } RFRH_b;
+    };
+
+    union
+    {
+        __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
+
+        struct
+        {
+            __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
+                                        *   clock from the main clock, this bit sets the comparison
+                                        *   value of the 128-Hz clock cycle.                                          */
+        } RFRL_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
+
+        struct
+        {
+            __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
+                                        *   from the prescaler.                                                       */
+            __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
+        } RADJ_b;
+    };
+    __IM uint8_t           RESERVED19;
+    __IM uint16_t          RESERVED20[8];
+    __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
+    __IM uint16_t          RESERVED21[5];
+    __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
+} R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Communications Interface (R_SCI0)
+ */
+
+typedef struct                         /*!< (@ 0x40070000) R_SCI0 Structure                                           */
+{
+    union
+    {
+        union
+        {
+            __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
+                __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
+                __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
+                __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
+            } SMR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
+
+            struct
+            {
+                __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
+                __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
+                __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
+                __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
+                __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
+                __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
+            } SMR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
+
+        struct
+        {
+            __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
+        } BRR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
+                                         *   mode when SMR.MP = 1)                                                     */
+                __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
+
+            struct
+            {
+                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
+                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
+                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
+                __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
+                __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
+                __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
+                __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
+            } SCR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
+
+        struct
+        {
+            __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
+        } TDR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
+                __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
+
+            struct
+            {
+                __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
+                                         *   multi-processor) and FIFO selected)                                       */
+                uint8_t            : 1;
+                __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
+                __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
+            } SSR_FIFO_b;
+        };
+
+        union
+        {
+            __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
+
+            struct
+            {
+                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
+                                         *   card interface mode.                                                      */
+                __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
+                                         *   mode.                                                                     */
+                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
+                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
+                __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
+                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
+                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
+                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
+            } SSR_SMCI_b;
+        };
+    };
+
+    union
+    {
+        __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
+
+        struct
+        {
+            __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
+        } RDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
+            uint8_t            : 1;
+            __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
+                                        *   operation is to be in simple I2C mode.                                    */
+            __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
+                                        *   setting is invalid and a fixed data length of 8 bits is
+                                        *   used in modes other than asynchronous mode.Set this bit
+                                        *   to 1 if operation is to be in simple I2C mode.                            */
+            __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
+            uint8_t            : 2;
+            __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
+                                        *   in combination with the SMR.BCP[1:0] bits                                 */
+        } SCMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
+
+        struct
+        {
+            uint8_t             : 2;
+            __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
+            __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
+                                        *   only in asynchronous mode and SCR.CKE[1]=0)                               */
+            __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
+                                        *   mode)                                                                     */
+            __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
+                                        *   be 0 without simple I2C mode and asynchronous mode.)In
+                                        *   asynchronous mode, for RXDn input only. In simple I2C mode,
+                                        *   for RXDn/TxDn input.                                                      */
+            __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
+                                        *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
+            __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
+                                        *   in asynchronous mode)                                                     */
+        } SEMR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
+
+        struct
+        {
+            __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
+            uint8_t            : 5;
+        } SNFR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
+            uint8_t             : 2;
+            __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
+                                        *   signal from the on-chip baud rate generator.                              */
+        } SIMR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
+
+        struct
+        {
+            __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
+            __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
+            uint8_t               : 3;
+            __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
+            uint8_t               : 2;
+        } SIMR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
+
+        struct
+        {
+            __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
+            __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
+            __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
+            __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
+                                           *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
+            __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
+            __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
+        } SIMR3_b;
+    };
+
+    union
+    {
+        __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
+
+        struct
+        {
+            __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
+            uint8_t              : 7;
+        } SISR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
+
+        struct
+        {
+            __IOM uint8_t SSE   : 1;   /*!< [0..0] SSn Pin Function Enable                                            */
+            __IOM uint8_t CTSE  : 1;   /*!< [1..1] CTS Enable                                                         */
+            __IOM uint8_t MSS   : 1;   /*!< [2..2] Master Slave Select                                                */
+            uint8_t             : 1;
+            __IOM uint8_t MFF   : 1;   /*!< [4..4] Mode Fault Flag                                                    */
+            uint8_t             : 1;
+            __IOM uint8_t CKPOL : 1;   /*!< [6..6] Clock Polarity Select                                              */
+            __IOM uint8_t CKPH  : 1;   /*!< [7..7] Clock Phase Select                                                 */
+        } SPMR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
+
+            struct
+            {
+                __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
+            } TDRHL_b;
+        };
+
+        union
+        {
+            __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
+
+            struct
+            {
+                __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
+                                         *   mode and SMR.MP=1 and FIFO selected)                                      */
+                uint16_t : 6;
+            } FTDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
+
+                struct
+                {
+                    __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                    __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
+                                             *   mode and SMR.MP=1 and FIFO selected)                                      */
+                    uint8_t : 6;
+                } FTDRH_b;
+            };
+
+            union
+            {
+                __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
+
+                struct
+                {
+                    __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
+                                             *   mode(including multi-processor) or clock synchronous mode,
+                                             *   and FIFO selected)                                                        */
+                } FTDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
+
+            struct
+            {
+                __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
+            } RDRHL_b;
+        };
+
+        union
+        {
+            __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
+
+            struct
+            {
+                __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
+                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
+                                         *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                         *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
+                __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
+                __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
+                __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
+                __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
+                uint16_t           : 1;
+            } FRDRHL_b;
+        };
+
+        struct
+        {
+            union
+            {
+                __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
+
+                struct
+                {
+                    __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+                    __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
+                                             *   with SMR.MP=1 and FIFO selected) It can read multi-processor
+                                             *   bit corresponded to serial receive data(RDATA[8:0])                       */
+                    __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
+                    __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
+                    __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
+                    __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
+                    __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
+                    uint8_t           : 1;
+                } FRDRH_b;
+            };
+
+            union
+            {
+                __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
+
+                struct
+                {
+                    __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
+                                             *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
+                                             *   When reading both of FRDRH register and FRDRL register,
+                                             *   please read by an order of the FRDRH register and the FRDRL
+                                             *   register.                                                                 */
+                } FRDRL_b;
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
+
+        struct
+        {
+            __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
+        } MDDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
+            uint8_t             : 2;
+            __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
+            __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
+            uint8_t             : 1;
+            __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
+                                        *   multi-processor)                                                          */
+            __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
+                                        *   mode(including multi-processor)                                           */
+        } DCCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode)                               */
+            __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
+            __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
+            __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
+                                        *   reception data ready, the interrupt request is selected.)                 */
+            __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode)                */
+            __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
+                                        *   in asynchronous mode(including multi-processor) or clock
+                                        *   synchronous mode)                                                         */
+        } FCR_b;
+    };
+
+    union
+    {
+        __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
+
+        struct
+        {
+            __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
+                                        *   data stored in FRDRH and FRDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t        : 3;
+            __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
+                                        *   data stored in FTDRH and FTDRL(Valid only in asynchronous
+                                        *   mode(including multi-processor) or clock synchronous mode,
+                                        *   while FCR.FM=1)                                                           */
+            uint16_t : 3;
+        } FDR_b;
+    };
+
+    union
+    {
+        __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
+
+        struct
+        {
+            __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
+                                        *   multi-processor) or clock synchronous mode, and FIFO selected)            */
+            uint16_t           : 1;
+            __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
+                                        *   a framing error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t           : 1;
+            __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
+                                        *   a parity error among the receive data stored in the receive
+                                        *   FIFO data register (FRDRH and FRDRL).                                     */
+            uint16_t : 3;
+        } LSR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
+
+        struct
+        {
+            __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
+                                        *   wake-up function                                                          */
+            uint16_t : 7;
+        } CDR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
+
+        struct
+        {
+            __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
+                                        *   is shown.)                                                                */
+            __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
+                                        *   TxD terminal is selected when SCR.TE = 0.)                                */
+            __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
+                                        *   of SPB2DT is output to TxD terminal.)                                     */
+            uint8_t : 5;
+        } SPTR_b;
+    };
+    __IM uint8_t  RESERVED;
+    __IM uint16_t RESERVED1;
+} R_SCI0_Type;                         /*!< Size = 32 (0x20)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SDADC0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief R_SDADC0 (R_SDADC0)
+ */
+
+typedef struct                          /*!< (@ 0x4009C000) R_SDADC0 Structure                                         */
+{
+    union
+    {
+        __IOM uint16_t STC1;            /*!< (@ 0x00000000) Startup Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint16_t CLKDIV  : 4; /*!< [3..0] SDADC24 Reference Clock Division                                   */
+            uint16_t               : 3;
+            __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select                              */
+            __IOM uint16_t VSBIAS  : 4; /*!< [11..8] Reference voltage select                                          */
+            uint16_t               : 3;
+            __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select                                                 */
+        } STC1_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t STC2;            /*!< (@ 0x00000004) Startup Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint8_t BGRPON  : 1; /*!< [0..0] BGR part power control                                             */
+            __IOM uint8_t ADCPON  : 1; /*!< [1..1] ADREG forced power-down                                            */
+            __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part                                          */
+            uint8_t               : 5;
+        } STC2_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t PGAC[5];        /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register                  */
+
+        struct
+        {
+            __IOM uint32_t PGAGC : 5;  /*!< [4..0] Gain selection of a programmable gain instrumentation
+                                        *   amplifier ( Gset1, Gset2, Gtotal )                                        */
+            __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select                                          */
+            __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select                                             */
+            uint32_t              : 1;
+            __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select                                                  */
+            __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select                                 */
+            __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count
+                                        *   (N) in AUTOSCAN                                                           */
+            __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count
+                                        *   (N) in AUTOSCAN                                                           */
+            __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged                   */
+            __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing                                */
+            __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
+            uint32_t              : 1;
+            __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable                                               */
+            __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of
+                                        *   A/D conversions in ADSCAN                                                 */
+        } PGAC_b[5];
+    };
+
+    union
+    {
+        __IOM uint32_t ADC1;            /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1               */
+
+        struct
+        {
+            __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode                                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal                         */
+            uint32_t               : 3;
+            __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer       */
+            uint32_t               : 3;
+            __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection                               */
+            __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting                           */
+            uint32_t               : 2;
+            __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable                                 */
+            uint32_t               : 11;
+        } ADC1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ADC2;            /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2               */
+
+        struct
+        {
+            __IOM uint8_t SDADST : 1;  /*!< [0..0] Control of A/D conversion                                          */
+            uint8_t              : 7;
+        } ADC2_b;
+    };
+    __IM uint8_t  RESERVED3;
+    __IM uint16_t RESERVED4;
+
+    union
+    {
+        __IOM uint32_t ADCR;            /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register       */
+
+        struct
+        {
+            __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result                                  */
+            __IM uint32_t SDADCRS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
+            __IM uint32_t SDADCRC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
+            uint32_t              : 4;
+        } ADCR_b;
+    };
+
+    union
+    {
+        __IM uint32_t ADAR;             /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register           */
+
+        struct
+        {
+            __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value                                      */
+            __IM uint32_t SDADMVS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
+            __IM uint32_t SDADMVC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
+            uint32_t              : 4;
+        } ADAR_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t CLBC;            /*!< (@ 0x00000030) Calibration Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t CLBMD : 2;   /*!< [1..0] These bits are read as 0. The write value should be 0.             */
+            uint8_t             : 6;
+        } CLBC_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t CLBSTR;          /*!< (@ 0x00000034) Calibration Start Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t CLBST : 1;   /*!< [0..0] Calibration start control                                          */
+            uint8_t             : 7;
+        } CLBSTR_b;
+    };
+    __IM uint8_t  RESERVED8;
+    __IM uint16_t RESERVED9;
+    __IM uint32_t RESERVED10;
+
+    union
+    {
+        __IM uint8_t CLBSSR;           /*!< (@ 0x0000003C) Calibration Status Register                                */
+
+        struct
+        {
+            __IM uint8_t CLBSS : 1;    /*!< [0..0] Calibration status                                                 */
+            uint8_t            : 7;
+        } CLBSSR_b;
+    };
+    __IM uint8_t  RESERVED11;
+    __IM uint16_t RESERVED12;
+} R_SDADC0_Type;                       /*!< Size = 64 (0x40)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SDHI0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SD/MMC Host Interface (R_SDHI0)
+ */
+
+typedef struct                          /*!< (@ 0x40062000) R_SDHI0 Structure                                          */
+{
+    union
+    {
+        __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
+
+        struct
+        {
+            __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
+                                         *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
+                                         *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
+            __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
+            __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
+                                         *   in normal mode, see section 1.4.10, Example of SD_CMD Register
+                                         *   Setting to select mode/response type.                                     */
+            __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
+            __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
+                                         *   is handled)                                                               */
+            __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
+                                         *   with data is handled)                                                     */
+            __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
+                                         *   transfer)                                                                 */
+            uint32_t : 16;
+        } SD_CMD_b;
+    };
+    __IM uint32_t RESERVED;
+
+    union
+    {
+        __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
+
+        struct
+        {
+            __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
+        } SD_ARG_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
+            uint32_t               : 16;
+        } SD_ARG1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
+
+        struct
+        {
+            __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
+                                        *   CMD12 is issued to halt the transfer through the SD host
+                                        *   interface.However, if a command sequence is halted because
+                                        *   of a communications error or timeout, CMD12 is not issued.
+                                        *   Although continued buffer access is possible even after
+                                        *   STP has been set to 1, the buffer access error bit (ERR5
+                                        *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
+                                        *   has been set to 1 during transfer for single block write,
+                                        *   the access end flag is set when SD_BUF becomes e                          */
+            uint32_t           : 7;
+            __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
+                                        *   SD_CMD is set as follows to start the command sequence
+                                        *   while SEC is set to 1, CMD12 is automatically issued to
+                                        *   stop multi-block transfer with the number of blocks which
+                                        *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
+                                        *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
+                                        *   automatically issued, multiple block transfer)When the
+                                        *   command sequence is halted because of a communications
+                                        *   error or timeout, CMD12 is not automatically                              */
+            uint32_t : 23;
+        } SD_STOP_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
+
+        struct
+        {
+            __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
+                                            *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
+        } SD_SECCNT_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
+
+        struct
+        {
+            __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
+        } SD_RSP10_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
+
+        struct
+        {
+            __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
+            uint32_t              : 16;
+        } SD_RSP1_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
+
+        struct
+        {
+            __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
+        } SD_RSP32_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
+
+        struct
+        {
+            __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
+            uint32_t              : 16;
+        } SD_RSP3_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
+
+        struct
+        {
+            __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
+        } SD_RSP54_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
+
+        struct
+        {
+            __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
+            uint32_t              : 16;
+        } SD_RSP5_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
+
+        struct
+        {
+            __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
+            uint32_t               : 8;
+        } SD_RSP76_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
+
+        struct
+        {
+            __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
+            uint32_t              : 24;
+        } SD_RSP7_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
+
+        struct
+        {
+            __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
+            uint32_t               : 1;
+            __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
+            __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
+            __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
+            __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
+            uint32_t               : 1;
+            __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
+            __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
+            __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
+            __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
+            uint32_t               : 21;
+        } SD_INFO1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
+
+        struct
+        {
+            __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
+            __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
+            __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
+            __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
+            __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
+            __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
+            __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
+            __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
+                                              *   by SD_PORTSEL.                                                            */
+            __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
+            __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
+            uint32_t                    : 3;
+            __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
+                                              *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
+                                              *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
+                                              *   cycles of SDCLK have elapsed after setting of the CBSY
+                                              *   bit to 0 due to completion of the command sequence.                       */
+            __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
+            __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
+            uint32_t            : 16;
+        } SD_INFO2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
+
+        struct
+        {
+            __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
+            uint32_t               : 1;
+            __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
+            __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
+            __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
+            uint32_t               : 3;
+            __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
+            __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
+            uint32_t               : 22;
+        } SD_INFO1_MASK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
+
+        struct
+        {
+            __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
+            __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
+            __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
+            __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
+            __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
+            __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
+            __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
+            uint32_t              : 1;
+            __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
+            __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
+            uint32_t              : 5;
+            __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
+            uint32_t              : 16;
+        } SD_INFO2_MASK_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
+
+        struct
+        {
+            __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
+            __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
+            __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
+            uint32_t                 : 22;
+        } SD_CLK_CTRL_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
+
+        struct
+        {
+            __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
+                                        *   and 512 bytes for the transfer of single blocks.In cases
+                                        *   of multiple block transfer with automatic issuing of CMD12
+                                        *   (CMD18 and CMD25), the only specifiable transfer data size
+                                        *   is 512 bytes. Furthermore, in cases of multiple block transfer
+                                        *   without automatic issuing of CMD12, as well as 512 bytes,
+                                        *   32, 64, 128, and 256 bytes are specifiable. However, in
+                                        *   the reading of 32, 64, 128, and 256 bytes for the transfer
+                                        *   of multiple blocks, this is restricted to mu                              */
+            uint32_t : 22;
+        } SD_SIZE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
+
+        struct
+        {
+            __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
+            __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
+            __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
+                                          *   timeout, software reset should be executed to terminate
+                                          *   command sequence.                                                         */
+            uint32_t              : 4;
+            __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
+            uint32_t              : 1;
+            __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
+                                          *   and when the SOFT_RST.SDRST flag is 0.                                    */
+            uint32_t : 16;
+        } SD_OPTION_b;
+    };
+    __IM uint32_t RESERVED1;
+
+    union
+    {
+        __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
+
+        struct
+        {
+            __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
+                                         *   issued within a command sequence                                          */
+            __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
+                                         *   setting a command index in SD_CMD, this is Indicated in
+                                         *   CMDE0.                                                                    */
+            __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
+                                         *   a command issued within a command sequence                                */
+            __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
+                                         *   issued by setting a command index in SD_CMD, this is indicated
+                                         *   in RSPLENE0.                                                              */
+            __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
+            __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
+            uint32_t               : 2;
+            __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
+                                         *   command issued within a command sequence                                  */
+            __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
+                                         *   by setting a command index in SD_CMD, this is indicated
+                                         *   in RSPCRCE0.                                                              */
+            __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
+            __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
+            __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
+                                         *   value is 010b)                                                            */
+            uint32_t : 17;
+        } SD_ERR_STS1_b;
+    };
+
+    union
+    {
+        __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
+
+        struct
+        {
+            __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
+            __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
+            __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
+            __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
+            __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
+            __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
+            __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
+            uint32_t               : 25;
+        } SD_ERR_STS2_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
+
+        struct
+        {
+            __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
+                                         *   data is written to this register. When reading from the
+                                         *   SD card, the read data is read from this register. This
+                                         *   register is internally connected to two 512-byte buffers.If
+                                         *   both buffers are not empty when executing multiple block
+                                         *   read, SD/MMC clock is stopped to suspend receiving data.
+                                         *   When one of buffers is empty, SD/MMC clock is supplied
+                                         *   to resume receiving data.                                                 */
+        } SD_BUF0_b;
+    };
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
+
+        struct
+        {
+            __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
+            uint32_t              : 1;
+            __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
+            uint32_t              : 5;
+            __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
+            __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
+            uint32_t              : 22;
+        } SDIO_MODE_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
+
+        struct
+        {
+            __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
+            uint32_t               : 13;
+            __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
+            __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
+            uint32_t               : 16;
+        } SDIO_INFO1_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
+
+        struct
+        {
+            __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
+            uint32_t                : 13;
+            __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
+            __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
+            uint32_t                : 16;
+        } SDIO_INFO1_MASK_b;
+    };
+    __IM uint32_t RESERVED3[79];
+
+    union
+    {
+        __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
+
+        struct
+        {
+            uint32_t             : 1;
+            __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
+            uint32_t             : 30;
+        } SD_DMAEN_b;
+    };
+    __IM uint32_t RESERVED4[3];
+
+    union
+    {
+        __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
+
+        struct
+        {
+            __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
+            uint32_t             : 31;
+        } SOFT_RST_b;
+    };
+    __IM uint32_t RESERVED5[2];
+
+    union
+    {
+        __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
+
+        struct
+        {
+            uint32_t               : 8;
+            __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
+            uint32_t               : 23;
+        } SDIF_MODE_b;
+    };
+    __IM uint32_t RESERVED6[4];
+
+    union
+    {
+        __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
+
+        struct
+        {
+            uint32_t             : 6;
+            __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
+            __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
+            uint32_t             : 24;
+        } EXT_SWAP_b;
+    };
+} R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SLCDC                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Segment LCD Controller/Driver (R_SLCDC)
+ */
+
+typedef struct                         /*!< (@ 0x40082000) R_SLCDC Structure                                          */
+{
+    union
+    {
+        __IOM uint8_t LCDM0;           /*!< (@ 0x00000000) LCD Mode Register 0                                        */
+
+        struct
+        {
+            __IOM uint8_t LBAS  : 2;   /*!< [1..0] LCD Display Bias Method Select                                     */
+            __IOM uint8_t LDTY  : 3;   /*!< [4..2] Time Slice of LCD Display Select                                   */
+            __IOM uint8_t LWAVE : 1;   /*!< [5..5] LCD display waveform selection                                     */
+            __IOM uint8_t MDSET : 2;   /*!< [7..6] LCD drive voltage generator selection                              */
+        } LCDM0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LCDM1;           /*!< (@ 0x00000001) LCD Mode Register 1                                        */
+
+        struct
+        {
+            __IOM uint8_t LCDVLM : 1;  /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control               */
+            uint8_t              : 2;
+            __IOM uint8_t LCDSEL : 1;  /*!< [3..3] Display data area control                                          */
+            __IOM uint8_t BLON   : 1;  /*!< [4..4] Display data area control                                          */
+            __IOM uint8_t VLCON  : 1;  /*!< [5..5] Voltage boost circuit or capacitor split circuit operation
+                                        *   enable/disable                                                            */
+            __IOM uint8_t SCOC  : 1;   /*!< [6..6] LCD Display Enable/Disable                                         */
+            __IOM uint8_t LCDON : 1;   /*!< [7..7] LCD Display Enable/Disable                                         */
+        } LCDM1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LCDC0;           /*!< (@ 0x00000002) LCD Clock Control Register 0                               */
+
+        struct
+        {
+            __IOM uint8_t LCDC : 6;    /*!< [5..0] LCD clock (LCDCL)                                                  */
+            uint8_t            : 2;
+        } LCDC0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VLCD;            /*!< (@ 0x00000003) LCD Boost Level Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t VLCD : 5;    /*!< [4..0] Reference Voltage(Contrast Adjustment) Select                      */
+            uint8_t            : 3;
+        } VLCD_b;
+    };
+    __IM uint8_t RESERVED[252];
+
+    union
+    {
+        __IOM uint8_t SEG[38];         /*!< (@ 0x00000100) LCD Display Data Array                                     */
+
+        struct
+        {
+            __IOM uint8_t A : 4;       /*!< [3..0] A-Pattern Area                                                     */
+            __IOM uint8_t B : 4;       /*!< [7..4] B-Pattern Area                                                     */
+        } SEG_b[38];
+    };
+} R_SLCDC_Type;                        /*!< Size = 294 (0x126)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Peripheral Interface (R_SPI0)
+ */
+
+typedef struct                         /*!< (@ 0x40072000) R_SPI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
+            __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
+            __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
+            __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
+            __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
+            __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
+            __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
+            __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
+        } SPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
+
+        struct
+        {
+            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
+            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
+            uint8_t             : 4;
+        } SSLP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
+            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
+            uint8_t             : 2;
+            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
+            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
+            uint8_t             : 2;
+        } SPPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
+
+        struct
+        {
+            __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
+            __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
+            __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
+            __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
+            __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
+            __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
+            uint8_t             : 1;
+            __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
+        } SPSR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
+        __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
+        __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
+    };
+
+    union
+    {
+        __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
+                                        *   the SPCMD0 to SPCMD07 registers are to be referenced is
+                                        *   changed in accordance with the sequence length that is
+                                        *   set in these bits. The relationship among the setting of
+                                        *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
+                                        *   referenced by the RSPI is shown above. However, the RSPI
+                                        *   in slave mode always references SPCMD0.                                   */
+            uint8_t : 5;
+        } SPSCR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
+
+        struct
+        {
+            __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
+        } SPBR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
+            uint8_t              : 2;
+            __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
+            __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
+            __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
+            uint8_t              : 1;
+        } SPDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
+            uint8_t             : 5;
+        } SPCKD_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
+
+        struct
+        {
+            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
+            uint8_t             : 5;
+        } SSLND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
+
+        struct
+        {
+            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
+            uint8_t             : 5;
+        } SPND_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
+            __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
+            __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
+            __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
+            __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
+            uint8_t              : 3;
+        } SPCR2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
+
+        struct
+        {
+            __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
+            __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
+            __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
+            __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
+            __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
+            __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
+            __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
+            __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
+            __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
+            __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
+        } SPCMD_b[8];
+    };
+
+    union
+    {
+        __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
+
+        struct
+        {
+            __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
+            uint8_t            : 7;
+        } SPDCR2_b;
+    };
+    __IM uint8_t  RESERVED1;
+    __IM uint16_t RESERVED2;
+} R_SPI0_Type;                         /*!< Size = 36 (0x24)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief SRAM (R_SRAM)
+ */
+
+typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
+{
+    union
+    {
+        __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } PARIOAD_b;
+    };
+    __IM uint8_t RESERVED[3];
+
+    union
+    {
+        __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
+
+        struct
+        {
+            __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
+        } SRAMPRCR_b;
+    };
+    __IM uint8_t RESERVED1[3];
+
+    union
+    {
+        __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECCRAMWRWTEN : 1; /*!< [0..0] ECCRAM Write Wait Enable                                           */
+            __IOM uint8_t ECCRAMRDWTEN : 1; /*!< [1..1] ECCRAM Read wait enable                                            */
+            __IOM uint8_t SRAM0WTEN    : 1; /*!< [2..2] SRAM0 Wait Enable                                                  */
+            __IOM uint8_t SRAM1WTEN    : 1; /*!< [3..3] SRAM1 Wait Enable                                                  */
+            __IOM uint8_t SRAMHSWTEN   : 1; /*!< [4..4] SRAMHS Wait Enable                                                 */
+            uint8_t                    : 3;
+        } SRAMWTSC_b;
+    };
+    __IM uint8_t RESERVED2[183];
+
+    union
+    {
+        __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
+            uint8_t              : 6;
+        } ECCMODE_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC2STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
+
+        struct
+        {
+            __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
+            uint8_t               : 7;
+        } ECC1STSEN_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
+
+        struct
+        {
+            __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
+            uint8_t               : 7;
+        } ECC1STS_b;
+    };
+
+    union
+    {
+        __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR_b;
+    };
+    __IM uint8_t RESERVED3[11];
+
+    union
+    {
+        __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
+
+        struct
+        {
+            __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
+            __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
+        } ECCPRCR2_b;
+    };
+    __IM uint8_t RESERVED4[3];
+
+    union
+    {
+        __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
+
+        struct
+        {
+            __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
+            uint8_t              : 7;
+        } ECCETST_b;
+    };
+    __IM uint8_t RESERVED5[3];
+
+    union
+    {
+        __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
+
+        struct
+        {
+            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
+            uint8_t           : 7;
+        } ECCOAD_b;
+    };
+} R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_SRC                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Sampling Rate Converter (R_SRC)
+ */
+
+typedef struct                           /*!< (@ 0x40048000) R_SRC Structure                                            */
+{
+    union
+    {
+        __IOM uint32_t SRCFCTR[5552];    /*!< (@ 0x00000000) Filter Coefficient Table [0..5551]                         */
+
+        struct
+        {
+            __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value.                                */
+            uint32_t               : 10;
+        } SRCFCTR_b[5552];
+    };
+    __IM uint32_t RESERVED[588];
+
+    union
+    {
+        __OM uint32_t SRCID;           /*!< (@ 0x00005FF0) Input Data Register                                        */
+
+        struct
+        {
+            __OM uint32_t SRCID : 32;  /*!< [31..0] SRCID is a 32-bit writ-only register that is used to
+                                        *   input the data before sampling rate conversion. All the
+                                        *   bits are read as 0.                                                       */
+        } SRCID_b;
+    };
+
+    union
+    {
+        __IM uint32_t SRCOD;           /*!< (@ 0x00005FF4) Output Data Register                                       */
+
+        struct
+        {
+            __IM uint32_t SRCOD : 32;  /*!< [31..0] SRCOD is a 32-bit read-only register used to output
+                                        *   the data after sampling rate conversion. The data in the
+                                        *   16-stage output data FIFO is read through SRCOD. When the
+                                        *   number of data in the output data FIFO is zero after the
+                                        *   start of conversion, the value previously read is read
+                                        *   again.                                                                    */
+        } SRCOD_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SRCIDCTRL;      /*!< (@ 0x00005FF8) Input Data Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t IFTRG : 2;  /*!< [1..0] Input FIFO Data Triggering Number                                  */
+            uint16_t             : 6;
+            __IOM uint16_t IEN   : 1;  /*!< [8..8] Input FIFO Empty Interrupt Enable                                  */
+            __IOM uint16_t IED   : 1;  /*!< [9..9] Input Data Endian                                                  */
+            uint16_t             : 6;
+        } SRCIDCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SRCODCTRL;      /*!< (@ 0x00005FFA) Output Data Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t OFTRG : 2;  /*!< [1..0] Output FIFO Data Trigger Number                                    */
+            uint16_t             : 6;
+            __IOM uint16_t OEN   : 1;  /*!< [8..8] Output Data FIFO Full Interrupt Enable                             */
+            __IOM uint16_t OED   : 1;  /*!< [9..9] Output Data Endian                                                 */
+            __IOM uint16_t OCH   : 1;  /*!< [10..10] Output Data Channel Exchange                                     */
+            uint16_t             : 5;
+        } SRCODCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SRCCTRL;        /*!< (@ 0x00005FFC) Control Register                                           */
+
+        struct
+        {
+            __IOM uint16_t OFS    : 3; /*!< [2..0] Output Sampling Rate                                               */
+            uint16_t              : 1;
+            __IOM uint16_t IFS    : 4; /*!< [7..4] Input Sampling Rate                                                */
+            __IOM uint16_t CL     : 1; /*!< [8..8] Internal Work Memory Clear                                         */
+            __IOM uint16_t FL     : 1; /*!< [9..9] Internal Work Memory Flush                                         */
+            __IOM uint16_t OVEN   : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable                      */
+            __IOM uint16_t UDEN   : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable                      */
+            __IOM uint16_t SRCEN  : 1; /*!< [12..12] Module Enable                                                    */
+            __IOM uint16_t CEEN   : 1; /*!< [13..13] Conversion End Interrupt Enable                                  */
+            uint16_t              : 1;
+            __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable                           */
+        } SRCCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SRCSTAT;        /*!< (@ 0x00005FFE) Status Register                                            */
+
+        struct
+        {
+            __IOM uint16_t OINT : 1;   /*!< [0..0] Output Data FIFO Full Interrupt Request Flag                       */
+            __IOM uint16_t IINT : 1;   /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag                       */
+            __IOM uint16_t OVF  : 1;   /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag                  */
+            __IOM uint16_t UDF  : 1;   /*!< [3..3] Output FIFO Underflow Interrupt Request Flag                       */
+            __IM uint16_t  FLF  : 1;   /*!< [4..4] Flush Processing Status Flag                                       */
+            __IOM uint16_t CEF  : 1;   /*!< [5..5] Conversion End Flag                                                */
+            uint16_t            : 1;
+            __IOM uint16_t IFDN : 4;   /*!< [10..7] Input FIFO Data CountIndicates the number of data units
+                                        *   in the input FIFO.                                                        */
+            __IOM uint16_t OFDN : 5;   /*!< [15..11] Output FIFO Data CountIndicates the number of data
+                                        *   units in the output FIFO.                                                 */
+        } SRCSTAT_b;
+    };
+} R_SRC_Type;                          /*!< Size = 24576 (0x6000)                                                     */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
+ */
+
+typedef struct                         /*!< (@ 0x4004E000) R_SSI0 Structure                                           */
+{
+    union
+    {
+        __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
+
+        struct
+        {
+            __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
+            __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
+            uint32_t            : 1;
+            __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
+                                        *   of outputting serial data is rewritten to 0 but data transmission
+                                        *   is not stopped. Write dummy data to the SSIFTDR not to
+                                        *   generate a transmit underflow because the number of data
+                                        *   in the transmit FIFO is decreasing.                                       */
+            __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
+            __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
+            __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
+            __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
+            __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
+            __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
+            __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
+            __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
+                                        *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
+                                        *   are prohibited.                                                           */
+            uint32_t           : 1;
+            __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
+                                        *   bit clock frequency/2 fs.                                                 */
+            __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
+            __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
+            uint32_t             : 1;
+            __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
+            __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
+            __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
+            __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
+            __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
+            __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
+            uint32_t             : 1;
+        } SSICR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
+
+        struct
+        {
+            __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
+            __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
+            __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
+            __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
+            __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
+            uint32_t             : 18;
+            __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
+            __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
+                                        *   Writable only to clear the flag. Confirm the value is 1
+                                        *   and then write 0.                                                         */
+            uint32_t : 2;
+        } SSISR_b;
+    };
+    __IM uint32_t RESERVED[2];
+
+    union
+    {
+        __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
+
+        struct
+        {
+            __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
+            __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
+            __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
+                                        *   clearing either the RDF flag (see the description of the
+                                        *   RDF bit for details) or RIE bit.                                          */
+            __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
+                                        *   clearing either the TDE flag (see the description of the
+                                        *   TDE bit for details) or TIE bit.                                          */
+            __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
+            __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
+                                        *   are the number of empty stages in SSIFTDR at which the
+                                        *   TDE flag is set.                                                          */
+            uint32_t              : 8;
+            __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
+            uint32_t              : 14;
+            __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
+        } SSIFCR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
+
+        struct
+        {
+            __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
+                                        *   is a 32-byte FIFO register, the maximum number of data
+                                        *   bytes that can be read from it while the RDF flag is 1
+                                        *   is indicated in the RDC[3:0] flags. If reading data from
+                                        *   the SSIFRDR register is continued after all the data is
+                                        *   read, undefined values will be read.                                      */
+            uint32_t          : 7;
+            __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
+                                        *   units stored in SSIFRDR)                                                  */
+            uint32_t           : 2;
+            __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
+                                        *   is a 32-byte FIFO register, the maximum number of bytes
+                                        *   that can be written to it while the TDE flag is 1 is 8
+                                        *   - TDC[3:0]. If writing data to the SSIFTDR register is
+                                        *   continued after all the data is written, writing will be
+                                        *   invalid and an overflow occurs.                                           */
+            uint32_t          : 7;
+            __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
+                                        *   data units stored in SSIFTDR)                                             */
+            uint32_t : 2;
+        } SSIFSR_b;
+    };
+
+    union
+    {
+        union
+        {
+            __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+
+            struct
+            {
+                __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
+                                             *   eight stages of 32-bit registers for storing data to be
+                                             *   serially transmitted. NOTE: that when the SSIFTDR register
+                                             *   is full of data (32 bytes), the next data cannot be written
+                                             *   to it. If writing is attempted, it will be ignored and
+                                             *   an overflow occurs.                                                       */
+            } SSIFTDR_b;
+        };
+        __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+        __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
+    };
+
+    union
+    {
+        union
+        {
+            __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+
+            struct
+            {
+                __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
+                                             *   stages of 32-bit registers for storing serially received
+                                             *   data.                                                                     */
+            } SSIFRDR_b;
+        };
+        __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+        __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
+    };
+
+    union
+    {
+        __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
+
+        struct
+        {
+            __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
+            uint32_t               : 6;
+            __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
+            __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
+                                         *   Idle Status                                                               */
+            uint32_t : 22;
+        } SSIOFR_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
+
+        struct
+        {
+            __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
+            uint32_t            : 3;
+            __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
+            uint32_t            : 19;
+        } SSISCR_b;
+    };
+} R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief System Pins (R_SYSTEM)
+ */
+
+typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
+{
+    __IM uint32_t RESERVED[3];
+
+    union
+    {
+        __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
+
+        struct
+        {
+            uint16_t            : 14;
+            __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
+            __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
+        } SBYCR_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2[3];
+
+    union
+    {
+        __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
+
+        struct
+        {
+            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
+            __IOM uint32_t MSTPA1  : 1; /*!< [1..1] RAM1 Module Stop                                                   */
+            uint32_t               : 3;
+            __IOM uint32_t MSTPA5  : 1; /*!< [5..5] High-Speed RAM Module Stop                                         */
+            __IOM uint32_t MSTPA6  : 1; /*!< [6..6] ECCRAM Module Stop                                                 */
+            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
+            uint32_t               : 14;
+            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
+            uint32_t               : 9;
+        } MSTPCRA_b;
+    };
+
+    union
+    {
+        __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
+
+        struct
+        {
+            __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
+            uint32_t            : 1;
+            __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
+            uint32_t            : 1;
+            __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
+            uint32_t            : 1;
+            __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
+            uint32_t            : 5;
+            __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
+            uint32_t            : 1;
+            __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
+            uint32_t            : 1;
+        } SCKDIVCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
+
+        struct
+        {
+            uint8_t           : 4;
+            __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
+            uint8_t           : 1;
+        } SCKDIVCR2_b;
+    };
+    __IM uint8_t RESERVED3;
+
+    union
+    {
+        __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
+            uint8_t             : 5;
+        } SCKSCR_b;
+    };
+    __IM uint8_t RESERVED4;
+
+    union
+    {
+        __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
+            uint16_t                : 2;
+            __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
+            uint16_t                : 3;
+            __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
+                                          *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
+                                          *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
+                                          *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
+                                          *   111011: x30.0                                                             */
+            uint16_t : 2;
+        } PLLCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
+
+        struct
+        {
+            __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
+            uint8_t              : 7;
+        } PLLCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
+
+        struct
+        {
+            __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
+            uint8_t              : 1;
+            __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
+        } PLLCCR2_b;
+    };
+    __IM uint32_t RESERVED5;
+
+    union
+    {
+        __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
+            uint8_t               : 7;
+        } BCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
+                                        *   is prohibited when SCKDIVCR.ICK selects division by 1 and
+                                        *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
+                                        *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
+            uint8_t : 7;
+        } MEMWAIT_b;
+    };
+
+    union
+    {
+        __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
+            uint8_t             : 7;
+        } MOSCCR_b;
+    };
+    __IM uint8_t  RESERVED6;
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
+
+        struct
+        {
+            __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
+            uint8_t             : 7;
+        } HOCOCR_b;
+    };
+    __IM uint8_t RESERVED8;
+
+    union
+    {
+        __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
+
+        struct
+        {
+            __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
+            uint8_t             : 7;
+        } MOCOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
+
+        struct
+        {
+            __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
+            uint8_t             : 7;
+        } FLLCR1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
+
+        struct
+        {
+            __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
+                                          *   FLL reference clock select                                                */
+            uint16_t : 5;
+        } FLLCR2_b;
+    };
+
+    union
+    {
+        __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
+
+        struct
+        {
+            __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
+                                        *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
+                                        *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
+            uint8_t             : 2;
+            __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
+            uint8_t             : 1;
+            __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
+            uint8_t             : 2;
+        } OSCSF_b;
+    };
+    __IM uint8_t RESERVED9;
+
+    union
+    {
+        __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
+            uint8_t              : 1;
+            __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
+            __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
+        } CKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
+            uint8_t              : 3;
+            __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
+        } TRCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
+
+        struct
+        {
+            __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
+            uint8_t              : 6;
+            __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
+        } OSTDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
+
+        struct
+        {
+            __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
+            uint8_t             : 7;
+        } OSTDSR_b;
+    };
+    __IM uint16_t RESERVED10;
+    __IM uint32_t RESERVED11[3];
+
+    union
+    {
+        __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
+
+        struct
+        {
+            __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
+            uint8_t                 : 4;
+            __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
+        } SLCDSCKCR_b;
+    };
+    __IM uint8_t RESERVED12;
+
+    union
+    {
+        __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
+            uint8_t               : 7;
+        } EBCKOCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
+            uint8_t               : 7;
+        } SDCKOCR_b;
+    };
+    __IM uint32_t RESERVED13[3];
+    __IM uint8_t  RESERVED14;
+
+    union
+    {
+        __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original MOCO
+                                         *   trimming bits                                                             */
+        } MOCOUTCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original HOCO
+                                         *   trimming bits                                                             */
+        } HOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED15;
+    __IM uint32_t RESERVED16[11];
+    __IM uint16_t RESERVED17;
+
+    union
+    {
+        __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
+
+        struct
+        {
+            __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
+                                         *   than in asynchronous mode.                                                */
+            __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
+            uint8_t                : 5;
+            __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
+        } SNZCR_b;
+    };
+    __IM uint8_t RESERVED18;
+
+    union
+    {
+        __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
+
+        struct
+        {
+            __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
+            __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
+            __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
+            __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
+            __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
+            __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
+            __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
+            __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
+                                          *   to 1 other than in asynchronous mode.                                     */
+        } SNZEDCR_b;
+    };
+    __IM uint8_t  RESERVED19;
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
+
+        struct
+        {
+            __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
+            __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
+            __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
+            __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
+            __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
+            __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
+            __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
+            __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
+            __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
+            __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
+            __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
+            __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
+            __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
+            __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
+            __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
+            __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
+            uint32_t                  : 1;
+            __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
+            uint32_t                  : 4;
+            __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
+            __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
+            uint32_t                  : 2;
+            __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
+                                            *   request                                                                   */
+            __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
+                                            *   snooze request                                                            */
+            __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
+                                            *   snooze request                                                            */
+            uint32_t : 1;
+        } SNZREQCR_b;
+    };
+    __IM uint16_t RESERVED21;
+
+    union
+    {
+        __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
+            uint8_t              : 3;
+            __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
+            uint8_t              : 3;
+        } FLSTOP_b;
+    };
+
+    union
+    {
+        __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
+
+        struct
+        {
+            __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
+            uint8_t            : 6;
+        } PSMCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
+
+        struct
+        {
+            __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
+            uint8_t              : 2;
+            __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
+            uint8_t              : 3;
+        } OPCCR_b;
+    };
+    __IM uint8_t RESERVED22;
+
+    union
+    {
+        __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
+
+        struct
+        {
+            __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
+            uint8_t            : 4;
+        } MOSCWTCR_b;
+    };
+    __IM uint8_t RESERVED23[2];
+
+    union
+    {
+        __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
+
+        struct
+        {
+            __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
+                                        *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
+            uint8_t : 5;
+        } HOCOWTCR_b;
+    };
+    __IM uint16_t RESERVED24[2];
+
+    union
+    {
+        __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
+
+        struct
+        {
+            __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
+            uint8_t               : 3;
+            __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
+            uint8_t               : 3;
+        } SOPCCR_b;
+    };
+    __IM uint8_t  RESERVED25;
+    __IM uint32_t RESERVED26[5];
+
+    union
+    {
+        __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
+
+        struct
+        {
+            __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
+                                        *   only to clear the flag. Confirm the value is 1 and then
+                                        *   write 0.                                                                  */
+            __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            uint16_t             : 5;
+            __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+            __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            uint16_t : 3;
+        } RSTSR1_b;
+    };
+    __IM uint16_t RESERVED27;
+    __IM uint32_t RESERVED28[3];
+
+    union
+    {
+        __IOM uint8_t USBCKCR;           /*!< (@ 0x000000D0) USB Clock Control Register                                 */
+
+        struct
+        {
+            __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
+                                          *   (UCLK).                                                                   */
+            uint8_t : 7;
+        } USBCKCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
+            uint8_t                  : 6;
+            __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
+        } SDADCCKCR_b;
+    };
+    __IM uint16_t RESERVED29;
+    __IM uint32_t RESERVED30[3];
+
+    union
+    {
+        __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD1CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD1SR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
+
+        struct
+        {
+            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
+            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
+            uint8_t              : 5;
+        } LVD2CR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
+
+        struct
+        {
+            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
+                                        *   0 can be written to this bit. After writing 0 to this bit,
+                                        *   it takes 2 system clock cycles for the bit to be read as
+                                        *   0.                                                                        */
+            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
+            uint8_t          : 6;
+        } LVD2SR_b;
+    };
+    __IM uint32_t RESERVED31[198];
+    __IM uint16_t RESERVED32;
+
+    union
+    {
+        __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
+
+        struct
+        {
+            __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
+                                        *   generation circuit.                                                       */
+            __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
+                                        *   modes, the low power consumption modes and the battery
+                                        *   backup function.                                                          */
+            uint16_t            : 1;
+            __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
+            uint16_t            : 4;
+            __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
+        } PRCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
+            uint8_t               : 4;
+            __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
+            __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
+        } DPSBYCR_b;
+    };
+    __IM uint8_t RESERVED33;
+
+    union
+    {
+        __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
+            __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
+        } DPSIER1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
+            __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
+            __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
+            __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
+            uint8_t                : 3;
+        } DPSIER2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
+            __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
+            uint8_t                : 5;
+        } DPSIER3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
+            __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
+        } DPSIFR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
+            __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
+            __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
+            __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
+            uint8_t                : 3;
+        } DPSIFR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
+
+        struct
+        {
+            __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
+            __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
+            uint8_t                : 5;
+        } DPSIFR3_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
+
+        struct
+        {
+            __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
+            __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
+        } DPSIEGR1_b;
+    };
+
+    union
+    {
+        __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
+
+        struct
+        {
+            __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
+            __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
+            uint8_t                : 2;
+            __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
+            uint8_t                : 3;
+        } DPSIEGR2_b;
+    };
+    __IM uint8_t RESERVED34;
+
+    union
+    {
+        __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
+            uint8_t             : 6;
+            __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
+        } SYOCDCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
+
+        struct
+        {
+            __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
+            uint8_t             : 6;
+        } STCONR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
+
+        struct
+        {
+            __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
+                                        *   the flag. Confirm the value is 1 and then write 0.                        */
+            __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
+                                        *   to clear the flag. Confirm the value is 1 and then write
+                                        *   0.                                                                        */
+            uint8_t               : 3;
+            __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
+                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
+        } RSTSR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
+
+        struct
+        {
+            __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
+            uint8_t            : 7;
+        } RSTSR2_b;
+    };
+    __IM uint8_t RESERVED35;
+
+    union
+    {
+        __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint8_t                 : 3;
+            __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
+            __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
+            __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
+            __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
+                                          *   Enable                                                                    */
+        } MOMCR_b;
+    };
+    __IM uint16_t RESERVED36;
+
+    union
+    {
+        __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
+
+        struct
+        {
+            __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
+            uint8_t            : 6;
+        } FWEPROR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVCMPCR;         /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
+
+        struct
+        {
+            uint8_t             : 5;
+            __IOM uint8_t LVD1E : 1;   /*!< [5..5] Voltage Detection 1 Enable                                         */
+            __IOM uint8_t LVD2E : 1;   /*!< [6..6] Voltage Detection 2 Enable                                         */
+            uint8_t             : 1;
+        } LVCMPCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
+
+        struct
+        {
+            __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
+                                        *   fall in voltage)                                                          */
+            __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
+                                        *   fall in voltage)                                                          */
+        } LVDLVLR_b;
+    };
+    __IM uint8_t RESERVED37;
+
+    union
+    {
+        __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD1CR0_b;
+    };
+
+    union
+    {
+        __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
+
+        struct
+        {
+            __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
+            __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
+            __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
+            uint8_t             : 1;
+            __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
+            __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
+            __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
+        } LVD2CR0_b;
+    };
+    __IM uint16_t RESERVED38;
+    __IM uint8_t  RESERVED39;
+
+    union
+    {
+        __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
+
+        struct
+        {
+            __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
+            uint8_t                : 7;
+        } VBTCR1_b;
+    };
+    __IM uint32_t RESERVED40[24];
+
+    union
+    {
+        __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
+
+        struct
+        {
+            __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
+            uint8_t             : 7;
+        } SOSCCR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
+
+        struct
+        {
+            __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
+            uint8_t             : 6;
+        } SOMCR_b;
+    };
+    __IM uint16_t RESERVED41;
+    __IM uint32_t RESERVED42[3];
+
+    union
+    {
+        __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
+
+        struct
+        {
+            __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
+            uint8_t             : 7;
+        } LOCOCR_b;
+    };
+    __IM uint8_t RESERVED43;
+
+    union
+    {
+        __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
+
+        struct
+        {
+            __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
+                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
+                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
+                                         +126 0111_1111 : +127These bits are added to original LOCO
+                                         *   trimming bits                                                             */
+        } LOCOUTCR_b;
+    };
+    __IM uint8_t  RESERVED44;
+    __IM uint32_t RESERVED45[7];
+
+    union
+    {
+        __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
+
+        struct
+        {
+            uint8_t                 : 4;
+            __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
+            uint8_t                 : 1;
+            __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
+        } VBTCR2_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
+
+        struct
+        {
+            __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
+            __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
+            uint8_t               : 2;
+            __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
+            uint8_t               : 3;
+        } VBTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
+
+        struct
+        {
+            __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
+            uint8_t               : 7;
+        } VBTCMPCR_b;
+    };
+    __IM uint8_t RESERVED46;
+
+    union
+    {
+        __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
+            __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
+            uint8_t                  : 6;
+        } VBTLVDICR_b;
+    };
+    __IM uint8_t RESERVED47;
+
+    union
+    {
+        __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
+
+        struct
+        {
+            __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
+            uint8_t            : 7;
+        } VBTWCTLR_b;
+    };
+    __IM uint8_t RESERVED48;
+
+    union
+    {
+        __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
+
+        struct
+        {
+            uint8_t                  : 1;
+            __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
+            __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH0OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
+            __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH1OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
+
+        struct
+        {
+            __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
+            __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
+            uint8_t                  : 1;
+            __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
+            __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
+            __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
+            uint8_t                  : 2;
+        } VBTWCH2OTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
+
+        struct
+        {
+            __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
+            __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
+            __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
+            uint8_t                : 5;
+        } VBTICTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
+
+        struct
+        {
+            __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
+            __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
+            __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
+            __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
+            __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
+            __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
+            uint8_t                 : 2;
+        } VBTOCTLR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
+
+        struct
+        {
+            __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
+            __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
+            __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
+            __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
+            __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
+            __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
+            uint8_t              : 2;
+        } VBTWTER_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
+            __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
+            uint8_t              : 5;
+        } VBTWEGR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
+
+        struct
+        {
+            __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
+            __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
+            __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
+            __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
+            uint8_t              : 2;
+        } VBTWFR_b;
+    };
+    __IM uint32_t RESERVED49[16];
+
+    union
+    {
+        __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
+
+        struct
+        {
+            __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
+                                        *   data powered by VBATT.The value of this register is retained
+                                        *   even when VCC is not powered but VBATT is powered.VBTBKR
+                                        *   is initialized by VBATT selected voltage power-on-reset.                  */
+        } VBTBKR_b[512];
+    };
+} R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TSN                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN)
+ */
+
+typedef struct                         /*!< (@ 0x407EC000) R_TSN Structure                                            */
+{
+    __IM uint8_t RESERVED[552];
+
+    union
+    {
+        __IM uint8_t TSCDRL;           /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
+                                        *                  L                                                          */
+
+        struct
+        {
+            __IM uint8_t TSCDRL : 8;   /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
+        } TSCDRL_b;
+    };
+
+    union
+    {
+        __IM uint8_t TSCDRH;           /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
+                                        *                  H                                                          */
+
+        struct
+        {
+            __IM uint8_t TSCDRH : 8;   /*!< [7..0] The calibration data stores the higher 8 bits of the
+                                        *   convertedvalue.                                                           */
+        } TSCDRH_b;
+    };
+} R_TSN_Type;                          /*!< Size = 554 (0x22a)                                                        */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Temperature Sensor (R_TSN_CTRL)
+ */
+
+typedef struct                         /*!< (@ 0x4005D000) R_TSN_CTRL Structure                                       */
+{
+    union
+    {
+        __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
+
+        struct
+        {
+            uint8_t            : 4;
+            __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
+            uint8_t            : 2;
+            __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
+        } TSCR_b;
+    };
+} R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Module (R_USB_FS0)
+ */
+
+typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
+            uint16_t             : 2;
+            __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
+            __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
+            uint16_t             : 1;
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
+            uint16_t             : 1;
+            __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
+            uint16_t             : 5;
+        } SYSCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+                                        *   access cycles)                                                            */
+            uint16_t : 12;
+        } BUSWAIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
+
+        struct
+        {
+            __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
+            __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
+            uint16_t            : 2;
+            __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
+                                        *   Selected.                                                                 */
+            __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
+            uint16_t             : 7;
+            __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
+                                        *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+                                        *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+                                        *   pin.                                                                      */
+        } SYSSTS0_b;
+    };
+
+    union
+    {
+        __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
+            uint16_t              : 15;
+        } PLLSTA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
+            uint16_t               : 1;
+            __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
+            __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
+            __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
+            __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
+            __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
+            __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
+            __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
+            __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
+                                         *   used when switching from device B to device A while in
+                                         *   OTG mode. If the HNPBTOA bit is 1, the internal function
+                                         *   control keeps the suspended state until the HNP processing
+                                         *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
+                                         *   set.                                                                      */
+            uint16_t : 4;
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+            uint16_t            : 12;
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
+            };
+
+            union
+            {
+                __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED3;
+                    __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED4;
+                    __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED5;
+                    __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
+            uint16_t                  : 3;
+            __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
+            __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
+            __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
+            uint16_t                  : 4;
+            __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
+            __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
+            uint16_t                  : 1;
+            __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
+            __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
+            uint16_t                  : 6;
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
+
+        struct
+        {
+            uint16_t                : 4;
+            __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
+            __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
+            uint16_t                : 1;
+            __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
+            uint16_t                : 7;
+        } SOFCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
+            __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
+            uint16_t                : 1;
+            __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
+            __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
+            uint16_t                : 2;
+            __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
+            uint16_t                : 1;
+            __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
+            uint16_t                : 3;
+            __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
+        } PHYSET_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
+            uint16_t                 : 3;
+            __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
+            __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
+            __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
+            uint16_t                 : 1;
+            __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
+            __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
+            __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
+            uint16_t                 : 1;
+            __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
+            __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
+            uint16_t                 : 6;
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
+
+        struct
+        {
+            __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
+            uint16_t             : 12;
+            __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
+                                           *   the USB address assigned by the host when the USBHS processed
+                                           *   the SET_ADDRESS request successfully.                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
+            uint16_t                 : 5;
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
+                                               *   value.                                                                    */
+            __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+            uint16_t              : 7;
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
+                                        *   of data (maximum packet size) in payloads for the DCP.                    */
+            uint16_t              : 5;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t                : 2;
+            __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
+            __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+            uint16_t               : 12;
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
+                                        *   for the selected pipe.Setting 0000b means unused pipe.                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            uint16_t              : 1;
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+    __IM uint16_t RESERVED12;
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
+                                        *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
+                                        *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
+                                        *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
+                                        *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
+            uint16_t              : 3;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
+                                        *   error detection timing for the selected pipe in terms of
+                                        *   frames, which is expressed as nth power of 2.                             */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+            uint16_t            : 3;
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 1;
+            __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+                                        *   Split Transaction of the relevant pipe                                    */
+            __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+                                        *   the CSSTS bit of the relevant pipe                                        */
+            __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t                RESERVED13;
+    __IM uint32_t                RESERVED14[3];
+    __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
+    __IM uint32_t                RESERVED15[3];
+
+    union
+    {
+        __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
+
+        struct
+        {
+            __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
+            __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
+            __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
+            __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
+            __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
+            uint16_t                  : 1;
+            __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
+            __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
+            __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
+            uint16_t                  : 6;
+        } USBBCCTRL0_b;
+    };
+    __IM uint16_t RESERVED16;
+    __IM uint32_t RESERVED17[4];
+
+    union
+    {
+        __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
+
+        struct
+        {
+            __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
+            uint16_t               : 15;
+        } UCKSEL_b;
+    };
+    __IM uint16_t RESERVED18;
+    __IM uint32_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
+            uint16_t               : 6;
+            __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
+            uint16_t               : 8;
+        } USBMC_b;
+    };
+    __IM uint16_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
+
+        struct
+        {
+            uint16_t               : 6;
+            __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
+            __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
+            __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
+            uint16_t               : 1;
+        } DEVADD_b[10];
+    };
+    __IM uint32_t RESERVED21[3];
+
+    union
+    {
+        __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
+
+        struct
+        {
+            __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
+            __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
+            __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
+            uint32_t               : 28;
+        } PHYSLEW_b;
+    };
+    __IM uint32_t RESERVED22[3];
+
+    union
+    {
+        __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
+
+        struct
+        {
+            uint16_t             : 7;
+            __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
+            uint16_t             : 8;
+        } LPCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t                : 14;
+            __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
+            uint16_t                : 1;
+        } LPSTS_b;
+    };
+    __IM uint32_t RESERVED23[15];
+
+    union
+    {
+        __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
+
+        struct
+        {
+            __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
+            __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
+            __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
+            __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
+            __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
+            __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
+            uint16_t                : 2;
+            __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
+            __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
+            uint16_t                : 6;
+        } BCCTRL_b;
+    };
+    __IM uint16_t RESERVED24;
+
+    union
+    {
+        __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
+
+        struct
+        {
+            __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
+            __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
+            __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+                                          *   only when the L1RESPMD[1:0] value is 2'b11.                               */
+            __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+                                          *   the L1 state together with the device state bits DVSQ[2:0].               */
+            __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+                                          *   value used for L1NEGOMD.The format is the same as the HIRD
+                                          *   field in HL1CTRL.                                                         */
+            uint16_t               : 2;
+            __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
+            uint16_t               : 1;
+        } PL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
+
+        struct
+        {
+            uint16_t               : 8;
+            __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
+            __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
+            uint16_t               : 3;
+        } PL1CTRL2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
+            __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
+            uint16_t                : 13;
+        } HL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+                                        *   be set in the ADDR field of LPM token.                                    */
+            uint16_t             : 4;
+            __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
+            __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+                                        *   value to be set in the RWE field of LPM token.                            */
+            uint16_t            : 2;
+            __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+                                        *   period at the time of L1 Resume.                                          */
+        } HL1CTRL2_b;
+    };
+    __IM uint32_t RESERVED25[5];
+
+    union
+    {
+        __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t              : 20;
+            __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+                                         *   HS side of USB port.                                                      */
+            __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+                                         *   HS side of USB port.                                                      */
+            uint32_t               : 1;
+            __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+                                         *   of USB port.                                                              */
+            uint32_t : 8;
+        } DPUSR0R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
+            __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
+            uint32_t                : 1;
+            __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
+            uint32_t                : 12;
+            __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
+            __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
+            uint32_t                : 1;
+            __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
+            uint32_t                : 8;
+        } DPUSR1R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
+            __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
+            uint16_t            : 2;
+            __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+                                        *   port.                                                                     */
+            __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+                                        *   port.                                                                     */
+            uint16_t              : 2;
+            __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
+            __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
+            uint16_t              : 6;
+        } DPUSR2R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
+
+        struct
+        {
+            __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
+            __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
+            uint16_t                : 14;
+        } DPUSRCR_b;
+    };
+    __IM uint32_t RESERVED26[165];
+
+    union
+    {
+        __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
+                                         *                  Monitor Register                                           */
+
+        struct
+        {
+            __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
+            __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
+            uint32_t               : 1;
+            __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
+            __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
+            uint32_t               : 11;
+            __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
+            __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
+            uint32_t               : 2;
+            __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
+                                         *   of the USB.                                                               */
+            __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
+                                         *   of the USB.                                                               */
+            uint32_t              : 1;
+            __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
+                                         *   USB.                                                                      */
+            uint32_t : 8;
+        } DPUSR0R_FS_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
+                                           *                  Register                                                   */
+
+        struct
+        {
+            __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
+            __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
+            uint32_t                 : 2;
+            __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
+            __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
+            uint32_t                 : 1;
+            __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
+            uint32_t                 : 8;
+            __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
+            __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
+            uint32_t                 : 2;
+            __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
+            __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
+            uint32_t                 : 1;
+            __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
+            uint32_t                 : 8;
+        } DPUSR1R_FS_b;
+    };
+} R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_USB_HS0                                          ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief USB 2.0 Module (R_USB_HS0)
+ */
+
+typedef struct                         /*!< (@ 0x40090000) R_USB_HS0 Structure                                          */
+{
+    union
+    {
+        __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
+
+        struct
+        {
+            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
+            uint16_t             : 3;
+            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
+            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
+            __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
+            __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                          */
+            __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
+            uint16_t             : 1;
+            __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
+        } SYSCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
+
+        struct
+        {
+            __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
+                                        *   access cycles)                                                            */
+        } BUSWAIT_b;
+    };
+
+    union
+    {
+        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
+
+        struct
+        {
+            __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
+            __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
+            uint16_t            : 2;
+            __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
+                                        *   Selected.                                                                 */
+            __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
+            uint16_t             : 7;
+            __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
+                                        *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
+                                        *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
+                                        *   pin.                                                                      */
+        } SYSSTS0_b;
+    };
+
+    union
+    {
+        __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
+        } PLLSTA_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
+
+        struct
+        {
+            __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
+            uint16_t               : 1;
+            __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
+            __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
+            __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
+            __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
+            __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
+            __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
+            __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
+            __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
+                                         *   used when switching from device B to device A while in
+                                         *   OTG mode. If the HNPBTOA bit is 1, the internal function
+                                         *   control keeps the suspended state until the HNP processing
+                                         *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
+                                         *   set.                                                                      */
+        } DVSTCTR0_b;
+    };
+    __IM uint16_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
+
+        struct
+        {
+            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
+        } TESTMODE_b;
+    };
+    __IM uint16_t RESERVED1;
+    __IM uint32_t RESERVED2;
+
+    union
+    {
+        __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
+                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
+            };
+
+            union
+            {
+                __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED3;
+                    __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
+                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED4;
+                    __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
+
+        struct
+        {
+            union
+            {
+                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
+                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
+            };
+
+            union
+            {
+                __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
+
+                struct
+                {
+                    __IM uint8_t  RESERVED5;
+                    __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
+                };
+            };
+        };
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
+            uint16_t               : 1;
+            __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
+            uint16_t               : 2;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
+            uint16_t               : 2;
+            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
+        } CFIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } CFIFOCTR_b;
+    };
+    __IM uint32_t RESERVED6;
+
+    union
+    {
+        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D0FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D0FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
+            uint16_t               : 4;
+            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
+            uint16_t               : 1;
+            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
+            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
+            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
+                                         *   Pipe Data is Read                                                         */
+            __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
+            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
+        } D1FIFOSEL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
+
+        struct
+        {
+            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
+                                        *   data.                                                                     */
+            uint16_t            : 1;
+            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
+            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
+            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
+        } D1FIFOCTR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                  */
+
+        struct
+        {
+            uint16_t             : 8;
+            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
+            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
+            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
+            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
+            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
+            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
+            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
+            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
+        } INTENB0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
+            uint16_t                  : 3;
+            __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
+            __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
+            __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
+            uint16_t                  : 1;
+            __IOM uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
+            __IOM uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
+            uint16_t                  : 1;
+            __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
+            __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
+            uint16_t                  : 1;
+            __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
+            __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
+        } INTENB1_b;
+    };
+    __IM uint16_t RESERVED7;
+
+    union
+    {
+        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
+        } BRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
+        } NRDYENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
+            __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
+        } BEMPENB_b;
+    };
+
+    union
+    {
+        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
+
+        struct
+        {
+            uint16_t                : 4;
+            __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
+            __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
+            __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
+            uint16_t                : 1;
+            __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
+        } SOFCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
+
+        struct
+        {
+            __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
+            __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
+            uint16_t                : 1;
+            __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
+            __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
+            uint16_t                : 2;
+            __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
+            uint16_t                : 1;
+            __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
+            uint16_t                : 3;
+            __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
+        } PHYSET_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
+
+        struct
+        {
+            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
+            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
+            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
+            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
+            __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
+            __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
+            __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
+            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
+            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
+            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
+            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
+            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
+        } INTSTS0_b;
+    };
+
+    union
+    {
+        __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
+
+        struct
+        {
+            __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
+            uint16_t                 : 3;
+            __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
+            __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
+            __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
+            uint16_t                 : 1;
+            __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
+            __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
+            __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
+            uint16_t                 : 1;
+            __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
+            __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
+        } INTSTS1_b;
+    };
+    __IM uint16_t RESERVED8;
+
+    union
+    {
+        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
+        } BRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
+        } NRDYSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
+
+        struct
+        {
+            __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
+            __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
+        } BEMPSTS_b;
+    };
+
+    union
+    {
+        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
+
+        struct
+        {
+            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
+            uint16_t            : 3;
+            __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
+            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
+        } FRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
+
+        struct
+        {
+            __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
+            uint16_t             : 12;
+            __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
+        } UFRMNUM_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
+
+        struct
+        {
+            __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
+                                           *   the USB address assigned by the host when the USBHS processed
+                                           *   the SET_ADDRESS request successfully.                                     */
+            uint16_t                 : 1;
+            __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
+        } USBADDR_b;
+    };
+    __IM uint16_t RESERVED9;
+
+    union
+    {
+        __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
+
+        struct
+        {
+            __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
+                                               *   value.                                                                    */
+            __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
+        } USBREQ_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
+        } USBVAL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
+
+        struct
+        {
+            __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
+        } USBINDX_b;
+    };
+
+    union
+    {
+        __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
+
+        struct
+        {
+            __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
+        } USBLENG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
+
+        struct
+        {
+            uint16_t              : 4;
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
+        } DCPCFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
+                                        *   of data (maximum packet size) in payloads for the DCP.                    */
+            uint16_t              : 5;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } DCPMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
+            __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
+            uint16_t                : 1;
+            __IOM uint16_t PINGE    : 1; /*!< [4..4] PING Token Issue Enable                                            */
+            __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
+            __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            uint16_t                : 2;
+            __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
+            __IM uint16_t  CSSTS    : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                                                  */
+            __IOM uint16_t CSCLR    : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear                                                  */
+            __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
+            __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
+        } DCPCTR_b;
+    };
+    __IM uint16_t RESERVED10;
+
+    union
+    {
+        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
+
+        struct
+        {
+            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
+        } PIPESEL_b;
+    };
+    __IM uint16_t RESERVED11;
+
+    union
+    {
+        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
+
+        struct
+        {
+            __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
+                                        *   for the selected pipe.Setting 0000b means unused pipe.                    */
+            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
+            uint16_t              : 2;
+            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
+            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                   */
+            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
+            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
+            uint16_t              : 3;
+            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
+        } PIPECFG_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEBUF;          /*!< (@ 0x0000006A)Pipe Buffer Register                                         */
+
+        struct
+        {
+            __IOM uint16_t BUFNMB :  8;  /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the
+                                          *   selected pipe (04h to 87h).                                         */
+            uint16_t               :  2;
+            __IOM uint16_t BUFSIZE :  5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes   */
+        } PIPEBUF_b;                     /*!< BitSize                                                             */
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
+
+        struct
+        {
+            __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
+                                        *   1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
+                                        *   (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not
+                                        *   provided.)PIPE6 to PIPE9: 1 byte (001h) to
+                                        *   64 bytes (040h) (Bits [10:7] are not provided.)                      */
+            uint16_t              : 1;
+            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
+        } PIPEMAXP_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
+
+        struct
+        {
+            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
+                                        *   error detection timing for the selected pipe in terms of
+                                        *   frames, which is expressed as nth power of 2.                             */
+            uint16_t            : 9;
+            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
+        } PIPEPERI_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
+
+        struct
+        {
+            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
+            uint16_t              : 3;
+            __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
+            __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
+            __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
+            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
+            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
+            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
+            uint16_t              : 1;
+            __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
+                                        *   Split Transaction of the relevant pipe                                    */
+            __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
+                                        *   the CSSTS bit of the relevant pipe                                        */
+            __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
+            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
+        } PIPE_CTR_b[9];
+    };
+    __IM uint16_t                RESERVED13;
+    __IM uint32_t                RESERVED14[3];
+    __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
+    __IM uint32_t                RESERVED15[11];
+
+    union
+    {
+        __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
+
+        struct
+        {
+            uint16_t               : 6;
+            __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
+            __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
+            __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
+        } DEVADD_b[10];
+    };
+    __IM uint16_t RESERVED16;
+    __IM uint32_t RESERVED17[6];
+
+    union
+    {
+        __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
+
+        struct
+        {
+            uint16_t             : 7;
+            __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
+        } LPCTRL_b;
+    };
+
+    union
+    {
+        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
+
+        struct
+        {
+            uint16_t                : 14;
+            __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
+        } LPSTS_b;
+    };
+    __IM uint32_t RESERVED18[15];
+
+    union
+    {
+        __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
+
+        struct
+        {
+            __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
+            __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
+            __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
+            __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
+            __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
+            __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
+            uint16_t                : 2;
+            __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
+            __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
+        } BCCTRL_b;
+    };
+    __IM uint16_t RESERVED19;
+
+    union
+    {
+        __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
+
+        struct
+        {
+            __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
+            __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
+            __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
+                                          *   only when the L1RESPMD[1:0] value is 2'b11.                               */
+            __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
+                                          *   the L1 state together with the device state bits DVSQ[2:0].               */
+            __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
+                                          *   value used for L1NEGOMD.The format is the same as the HIRD
+                                          *   field in HL1CTRL.                                                         */
+            uint16_t               : 2;
+            __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
+        } PL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
+
+        struct
+        {
+            uint16_t               : 8;
+            __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
+            __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
+        } PL1CTRL2_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
+
+        struct
+        {
+            __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
+            __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
+        } HL1CTRL1_b;
+    };
+
+    union
+    {
+        __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
+
+        struct
+        {
+            __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
+                                        *   be set in the ADDR field of LPM token.                                    */
+            uint16_t             : 4;
+            __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
+            __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
+                                        *   value to be set in the RWE field of LPM token.                            */
+            uint16_t            : 2;
+            __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
+                                        *   period at the time of L1 Resume.                                          */
+        } HL1CTRL2_b;
+    };
+    __IM uint32_t RESERVED20;
+
+    union
+    {
+        __IOM uint16_t PHYTRIM1;           /*!< (@ 0x00000150)PHY Timing Register 1                                                 */
+
+        struct
+        {
+            __IOM uint16_t DRISE     :  2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function                 */
+            __IOM uint16_t DFALL     :  2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function                */
+            uint16_t                 :  3;
+            __IOM uint16_t PCOMPENB  :  1; /*!< [7..7]PVDD Start-up Detection                                               */
+            __IOM uint16_t HSIUP     :  4; /*!< [11..8]HS Output Level Setting                                               */
+            __IOM uint16_t IMPOFFSET :  3; /*!< [14..12]terminating resistance offset value setting.Offset value for
+                                            * adjusting the terminating resistance.                                 */
+        } PHYTRIM1_b;                      /*!< BitSize                                                               */
+    };
+
+    union
+    {
+        __IOM uint16_t PHYTRIM2;          /*!< (@ 0x00000152)PHY Timing Register 2                                                 */
+
+        struct
+        {
+            __IOM uint16_t SQU      :  4; /*!< [3..0]Squelch Detection Level                                               */
+            uint16_t                :  3;
+            __IOM uint16_t HSRXENMO :  1; /*!< [7..7]HS Receive Enable Control Mode                                        */
+            __IOM uint16_t PDR      :  2; /*!< [9..8]HS Output Adjustment Function                                         */
+            uint16_t                :  2;
+            __IOM uint16_t DIS      :  3; /*!< [14..12]Disconnect Detection Level                                            */
+        } PHYTRIM2_b;                     /*!< BitSize                                                               */
+    };
+    __IM uint32_t RESERVED21[3];
+
+    union
+    {
+        __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
+                                        *                  Register                                                   */
+
+        struct
+        {
+            uint32_t              : 20;
+            __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
+                                         *   HS side of USB port.                                                      */
+            __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
+                                         *   HS side of USB port.                                                      */
+            uint32_t               : 1;
+            __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
+                                         *   of USB port.                                                              */
+        } DPUSR0R_b;
+    };
+
+    union
+    {
+        __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            uint32_t                : 4;
+            __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
+            __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
+            uint32_t                : 1;
+            __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
+            uint32_t                : 12;
+            __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
+            __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
+            uint32_t                : 1;
+            __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
+        } DPUSR1R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
+
+        struct
+        {
+            __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
+            __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
+            uint16_t            : 2;
+            __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
+                                        *   port.                                                                     */
+            __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
+                                        *   port.                                                                     */
+            uint16_t              : 2;
+            __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
+            __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
+        } DPUSR2R_b;
+    };
+
+    union
+    {
+        __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
+
+        struct
+        {
+            __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
+            __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
+        } DPUSRCR_b;
+    };
+} R_USB_HS0_Type;                        /*!< Size = 1032 (0x408)                                                       */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Watchdog Timer (R_WDT)
+ */
+
+typedef struct                         /*!< (@ 0x40044200) R_WDT Structure                                            */
+{
+    union
+    {
+        __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
+
+        struct
+        {
+            __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
+                                        *   of the WDT.                                                               */
+        } WDTRR_b;
+    };
+    __IM uint8_t RESERVED;
+
+    union
+    {
+        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
+
+        struct
+        {
+            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
+            uint16_t            : 2;
+            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
+            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
+            uint16_t            : 2;
+            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
+            uint16_t            : 2;
+        } WDTCR_b;
+    };
+
+    union
+    {
+        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
+
+        struct
+        {
+            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
+            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
+            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
+        } WDTSR_b;
+    };
+
+    union
+    {
+        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
+
+        struct
+        {
+            uint8_t               : 7;
+            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
+        } WDTRCR_b;
+    };
+    __IM uint8_t RESERVED1;
+
+    union
+    {
+        __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
+
+        struct
+        {
+            uint8_t              : 7;
+            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
+        } WDTCSTPR_b;
+    };
+    __IM uint8_t  RESERVED2;
+    __IM uint16_t RESERVED3;
+} R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+ #define R_ACMPHS0_BASE                0x40085000UL
+ #define R_ACMPHS1_BASE                0x40085100UL
+ #define R_ACMPHS2_BASE                0x40085200UL
+ #define R_ACMPHS3_BASE                0x40085300UL
+ #define R_ACMPHS4_BASE                0x40085400UL
+ #define R_ACMPHS5_BASE                0x40085500UL
+ #define R_ACMPLP_BASE                 0x40085E00UL
+ #define R_ADC0_BASE                   0x4005C000UL
+ #define R_ADC1_BASE                   0x4005C200UL
+ #define R_AGT0_BASE                   0x40084000UL
+ #define R_AGT1_BASE                   0x40084100UL
+ #define R_BUS_BASE                    0x40003000UL
+ #define R_CAC_BASE                    0x40044600UL
+ #define R_CAN0_BASE                   0x40050000UL
+ #define R_CAN1_BASE                   0x40051000UL
+ #define R_CRC_BASE                    0x40074000UL
+ #define R_CTSU_BASE                   0x40081000UL
+ #define R_CTSU2_BASE                  0x40082000UL
+ #define R_DAC_BASE                    0x4005E000UL
+ #define R_DAC8_BASE                   0x4009E000UL
+ #define R_DALI0_BASE                  0x4008F000UL
+ #define R_DEBUG_BASE                  0x4001B000UL
+ #define R_DMA_BASE                    0x40005200UL
+ #define R_DMAC0_BASE                  0x40005000UL
+ #define R_DMAC1_BASE                  0x40005040UL
+ #define R_DMAC2_BASE                  0x40005080UL
+ #define R_DMAC3_BASE                  0x400050C0UL
+ #define R_DMAC4_BASE                  0x40005100UL
+ #define R_DMAC5_BASE                  0x40005140UL
+ #define R_DMAC6_BASE                  0x40005180UL
+ #define R_DMAC7_BASE                  0x400051C0UL
+ #define R_DOC_BASE                    0x40054100UL
+ #define R_DRW_BASE                    0x400E4000UL
+ #define R_DTC_BASE                    0x40005400UL
+ #define R_ELC_BASE                    0x40041000UL
+ #define R_ETHERC0_BASE                0x40064100UL
+ #define R_ETHERC_EDMAC_BASE           0x40064000UL
+ #define R_ETHERC_EPTPC_BASE           0x40065800UL
+ #define R_ETHERC_EPTPC1_BASE          0x40065C00UL
+ #define R_ETHERC_EPTPC_CFG_BASE       0x40064500UL
+ #define R_ETHERC_EPTPC_COMMON_BASE    0x40065000UL
+ #define R_FACI_HP_CMD_BASE            0x407E0000UL
+ #define R_FACI_HP_BASE                0x407FE000UL
+ #define R_FACI_LP_BASE                0x407EC000UL
+ #define R_FCACHE_BASE                 0x4001C000UL
+ #define R_GLCDC_BASE                  0x400E0000UL
+ #define R_GPT0_BASE                   0x40078000UL
+ #define R_GPT1_BASE                   0x40078100UL
+ #define R_GPT2_BASE                   0x40078200UL
+ #define R_GPT3_BASE                   0x40078300UL
+ #define R_GPT4_BASE                   0x40078400UL
+ #define R_GPT5_BASE                   0x40078500UL
+ #define R_GPT6_BASE                   0x40078600UL
+ #define R_GPT7_BASE                   0x40078700UL
+ #define R_GPT8_BASE                   0x40078800UL
+ #define R_GPT9_BASE                   0x40078900UL
+ #define R_GPT10_BASE                  0x40078A00UL
+ #define R_GPT11_BASE                  0x40078B00UL
+ #define R_GPT12_BASE                  0x40078C00UL
+ #define R_GPT13_BASE                  0x40078D00UL
+ #define R_GPT_ODC_BASE                0x4007B000UL
+ #define R_GPT_OPS_BASE                0x40078FF0UL
+ #define R_GPT_POEG0_BASE              0x40042000UL
+ #define R_GPT_POEG1_BASE              0x40042100UL
+ #define R_GPT_POEG2_BASE              0x40042200UL
+ #define R_GPT_POEG3_BASE              0x40042300UL
+ #define R_ICU_BASE                    0x40006000UL
+ #define R_IIC0_BASE                   0x40053000UL
+ #define R_IIC1_BASE                   0x40053100UL
+ #define R_IIC2_BASE                   0x40053200UL
+ #define R_IRDA_BASE                   0x40070F00UL
+ #define R_IWDT_BASE                   0x40044400UL
+ #define R_JPEG_BASE                   0x400E6000UL
+ #define R_KINT_BASE                   0x40080000UL
+ #define R_MMF_BASE                    0x40001000UL
+ #define R_MPU_MMPU_BASE               0x40000000UL
+ #define R_MPU_SMPU_BASE               0x40000C00UL
+ #define R_MPU_SPMON_BASE              0x40000D00UL
+ #define R_MSTP_BASE                   0x40047000UL
+ #define R_OPAMP_BASE                  0x40086000UL
+ #define R_OPAMP2_BASE                 0x400867F8UL
+ #define R_PDC_BASE                    0x40094000UL
+ #define R_PORT0_BASE                  0x40040000UL
+ #define R_PORT1_BASE                  0x40040020UL
+ #define R_PORT2_BASE                  0x40040040UL
+ #define R_PORT3_BASE                  0x40040060UL
+ #define R_PORT4_BASE                  0x40040080UL
+ #define R_PORT5_BASE                  0x400400A0UL
+ #define R_PORT6_BASE                  0x400400C0UL
+ #define R_PORT7_BASE                  0x400400E0UL
+ #define R_PORT8_BASE                  0x40040100UL
+ #define R_PORT9_BASE                  0x40040120UL
+ #define R_PORT10_BASE                 0x40040140UL
+ #define R_PORT11_BASE                 0x40040160UL
+ #define R_PFS_BASE                    0x40040800UL
+ #define R_PMISC_BASE                  0x40040D00UL
+ #define R_QSPI_BASE                   0x64000000UL
+ #define R_RTC_BASE                    0x40044000UL
+ #define R_SCI0_BASE                   0x40070000UL
+ #define R_SCI1_BASE                   0x40070020UL
+ #define R_SCI2_BASE                   0x40070040UL
+ #define R_SCI3_BASE                   0x40070060UL
+ #define R_SCI4_BASE                   0x40070080UL
+ #define R_SCI5_BASE                   0x400700A0UL
+ #define R_SCI6_BASE                   0x400700C0UL
+ #define R_SCI7_BASE                   0x400700E0UL
+ #define R_SCI8_BASE                   0x40070100UL
+ #define R_SCI9_BASE                   0x40070120UL
+ #define R_SDADC0_BASE                 0x4009C000UL
+ #define R_SDHI0_BASE                  0x40062000UL
+ #define R_SDHI1_BASE                  0x40062400UL
+ #define R_SLCDC_BASE                  0x40082000UL
+ #define R_SPI0_BASE                   0x40072000UL
+ #define R_SPI1_BASE                   0x40072100UL
+ #define R_SRAM_BASE                   0x40002000UL
+ #define R_SRC_BASE                    0x40048000UL
+ #define R_SSI0_BASE                   0x4004E000UL
+ #define R_SSI1_BASE                   0x4004E100UL
+ #define R_SYSTEM_BASE                 0x4001E000UL
+ #define R_TSN_BASE                    0x407EC000UL
+ #define R_TSN_CTRL_BASE               0x4005D000UL
+ #define R_USB_FS0_BASE                0x40090000UL
+ #define R_USB_HS0_BASE                0x40060000UL
+ #define R_WDT_BASE                    0x40044200UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+ #define R_ACMPHS0                ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
+ #define R_ACMPHS1                ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
+ #define R_ACMPHS2                ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
+ #define R_ACMPHS3                ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
+ #define R_ACMPHS4                ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
+ #define R_ACMPHS5                ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
+ #define R_ACMPLP                 ((R_ACMPLP_Type *) R_ACMPLP_BASE)
+ #define R_ADC0                   ((R_ADC0_Type *) R_ADC0_BASE)
+ #define R_ADC1                   ((R_ADC0_Type *) R_ADC1_BASE)
+ #define R_AGT0                   ((R_AGT0_Type *) R_AGT0_BASE)
+ #define R_AGT1                   ((R_AGT0_Type *) R_AGT1_BASE)
+ #define R_BUS                    ((R_BUS_Type *) R_BUS_BASE)
+ #define R_CAC                    ((R_CAC_Type *) R_CAC_BASE)
+ #define R_CAN0                   ((R_CAN0_Type *) R_CAN0_BASE)
+ #define R_CAN1                   ((R_CAN0_Type *) R_CAN1_BASE)
+ #define R_CRC                    ((R_CRC_Type *) R_CRC_BASE)
+ #if (BSP_FEATURE_CTSU_VERSION == 2)
+  #define R_CTSU                  ((R_CTSU2_Type *) R_CTSU2_BASE)
+ #else
+  #define R_CTSU                  ((R_CTSU_Type *) R_CTSU_BASE)
+ #endif
+ #define R_CTSU2                  ((R_CTSU2_Type *) R_CTSU2_BASE)
+ #define R_DAC                    ((R_DAC_Type *) R_DAC_BASE)
+ #define R_DAC8                   ((R_DAC8_Type *) R_DAC8_BASE)
+ #define R_DALI0                  ((R_DALI0_Type *) R_DALI0_BASE)
+ #define R_DEBUG                  ((R_DEBUG_Type *) R_DEBUG_BASE)
+ #define R_DMA                    ((R_DMA_Type *) R_DMA_BASE)
+ #define R_DMAC0                  ((R_DMAC0_Type *) R_DMAC0_BASE)
+ #define R_DMAC1                  ((R_DMAC0_Type *) R_DMAC1_BASE)
+ #define R_DMAC2                  ((R_DMAC0_Type *) R_DMAC2_BASE)
+ #define R_DMAC3                  ((R_DMAC0_Type *) R_DMAC3_BASE)
+ #define R_DMAC4                  ((R_DMAC0_Type *) R_DMAC4_BASE)
+ #define R_DMAC5                  ((R_DMAC0_Type *) R_DMAC5_BASE)
+ #define R_DMAC6                  ((R_DMAC0_Type *) R_DMAC6_BASE)
+ #define R_DMAC7                  ((R_DMAC0_Type *) R_DMAC7_BASE)
+ #define R_DOC                    ((R_DOC_Type *) R_DOC_BASE)
+ #define R_DRW                    ((R_DRW_Type *) R_DRW_BASE)
+ #define R_DTC                    ((R_DTC_Type *) R_DTC_BASE)
+ #define R_ELC                    ((R_ELC_Type *) R_ELC_BASE)
+ #define R_ETHERC0                ((R_ETHERC0_Type *) R_ETHERC0_BASE)
+ #define R_ETHERC_EDMAC           ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
+ #define R_ETHERC_EPTPC           ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
+ #define R_ETHERC_EPTPC1          ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE)
+ #define R_ETHERC_EPTPC_CFG       ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
+ #define R_ETHERC_EPTPC_COMMON    ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
+ #define R_FACI_HP_CMD            ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
+ #define R_FACI_HP                ((R_FACI_HP_Type *) R_FACI_HP_BASE)
+ #define R_FACI_LP                ((R_FACI_LP_Type *) R_FACI_LP_BASE)
+ #define R_FCACHE                 ((R_FCACHE_Type *) R_FCACHE_BASE)
+ #define R_GLCDC                  ((R_GLCDC_Type *) R_GLCDC_BASE)
+ #define R_GPT0                   ((R_GPT0_Type *) R_GPT0_BASE)
+ #define R_GPT1                   ((R_GPT0_Type *) R_GPT1_BASE)
+ #define R_GPT2                   ((R_GPT0_Type *) R_GPT2_BASE)
+ #define R_GPT3                   ((R_GPT0_Type *) R_GPT3_BASE)
+ #define R_GPT4                   ((R_GPT0_Type *) R_GPT4_BASE)
+ #define R_GPT5                   ((R_GPT0_Type *) R_GPT5_BASE)
+ #define R_GPT6                   ((R_GPT0_Type *) R_GPT6_BASE)
+ #define R_GPT7                   ((R_GPT0_Type *) R_GPT7_BASE)
+ #define R_GPT8                   ((R_GPT0_Type *) R_GPT8_BASE)
+ #define R_GPT9                   ((R_GPT0_Type *) R_GPT9_BASE)
+ #define R_GPT10                  ((R_GPT0_Type *) R_GPT10_BASE)
+ #define R_GPT11                  ((R_GPT0_Type *) R_GPT11_BASE)
+ #define R_GPT12                  ((R_GPT0_Type *) R_GPT12_BASE)
+ #define R_GPT13                  ((R_GPT0_Type *) R_GPT13_BASE)
+ #define R_GPT_ODC                ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
+ #define R_GPT_OPS                ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
+ #define R_GPT_POEG0              ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
+ #define R_GPT_POEG1              ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
+ #define R_GPT_POEG2              ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
+ #define R_GPT_POEG3              ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
+ #define R_ICU                    ((R_ICU_Type *) R_ICU_BASE)
+ #define R_IIC0                   ((R_IIC0_Type *) R_IIC0_BASE)
+ #define R_IIC1                   ((R_IIC0_Type *) R_IIC1_BASE)
+ #define R_IIC2                   ((R_IIC0_Type *) R_IIC2_BASE)
+ #define R_IRDA                   ((R_IRDA_Type *) R_IRDA_BASE)
+ #define R_IWDT                   ((R_IWDT_Type *) R_IWDT_BASE)
+ #define R_JPEG                   ((R_JPEG_Type *) R_JPEG_BASE)
+ #define R_KINT                   ((R_KINT_Type *) R_KINT_BASE)
+ #define R_MMF                    ((R_MMF_Type *) R_MMF_BASE)
+ #define R_MPU_MMPU               ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
+ #define R_MPU_SMPU               ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
+ #define R_MPU_SPMON              ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
+ #define R_MSTP                   ((R_MSTP_Type *) R_MSTP_BASE)
+ #if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U)
+  #define R_OPAMP                 ((R_OPAMP_Type *) R_OPAMP2_BASE)
+ #else
+  #define R_OPAMP                 ((R_OPAMP_Type *) R_OPAMP_BASE)
+ #endif
+ #define R_PDC                    ((R_PDC_Type *) R_PDC_BASE)
+ #define R_PORT0                  ((R_PORT0_Type *) R_PORT0_BASE)
+ #define R_PORT1                  ((R_PORT0_Type *) R_PORT1_BASE)
+ #define R_PORT2                  ((R_PORT0_Type *) R_PORT2_BASE)
+ #define R_PORT3                  ((R_PORT0_Type *) R_PORT3_BASE)
+ #define R_PORT4                  ((R_PORT0_Type *) R_PORT4_BASE)
+ #define R_PORT5                  ((R_PORT0_Type *) R_PORT5_BASE)
+ #define R_PORT6                  ((R_PORT0_Type *) R_PORT6_BASE)
+ #define R_PORT7                  ((R_PORT0_Type *) R_PORT7_BASE)
+ #define R_PORT8                  ((R_PORT0_Type *) R_PORT8_BASE)
+ #define R_PORT9                  ((R_PORT0_Type *) R_PORT9_BASE)
+ #define R_PORT10                 ((R_PORT0_Type *) R_PORT10_BASE)
+ #define R_PORT11                 ((R_PORT0_Type *) R_PORT11_BASE)
+ #define R_PFS                    ((R_PFS_Type *) R_PFS_BASE)
+ #define R_PMISC                  ((R_PMISC_Type *) R_PMISC_BASE)
+ #define R_QSPI                   ((R_QSPI_Type *) R_QSPI_BASE)
+ #define R_RTC                    ((R_RTC_Type *) R_RTC_BASE)
+ #define R_SCI0                   ((R_SCI0_Type *) R_SCI0_BASE)
+ #define R_SCI1                   ((R_SCI0_Type *) R_SCI1_BASE)
+ #define R_SCI2                   ((R_SCI0_Type *) R_SCI2_BASE)
+ #define R_SCI3                   ((R_SCI0_Type *) R_SCI3_BASE)
+ #define R_SCI4                   ((R_SCI0_Type *) R_SCI4_BASE)
+ #define R_SCI5                   ((R_SCI0_Type *) R_SCI5_BASE)
+ #define R_SCI6                   ((R_SCI0_Type *) R_SCI6_BASE)
+ #define R_SCI7                   ((R_SCI0_Type *) R_SCI7_BASE)
+ #define R_SCI8                   ((R_SCI0_Type *) R_SCI8_BASE)
+ #define R_SCI9                   ((R_SCI0_Type *) R_SCI9_BASE)
+ #define R_SDADC0                 ((R_SDADC0_Type *) R_SDADC0_BASE)
+ #define R_SDHI0                  ((R_SDHI0_Type *) R_SDHI0_BASE)
+ #define R_SDHI1                  ((R_SDHI0_Type *) R_SDHI1_BASE)
+ #define R_SLCDC                  ((R_SLCDC_Type *) R_SLCDC_BASE)
+ #define R_SPI0                   ((R_SPI0_Type *) R_SPI0_BASE)
+ #define R_SPI1                   ((R_SPI0_Type *) R_SPI1_BASE)
+ #define R_SRAM                   ((R_SRAM_Type *) R_SRAM_BASE)
+ #define R_SRC                    ((R_SRC_Type *) R_SRC_BASE)
+ #define R_SSI0                   ((R_SSI0_Type *) R_SSI0_BASE)
+ #define R_SSI1                   ((R_SSI0_Type *) R_SSI1_BASE)
+ #define R_SYSTEM                 ((R_SYSTEM_Type *) R_SYSTEM_BASE)
+ #define R_TSN                    ((R_TSN_Type *) R_TSN_BASE)
+ #define R_TSN_CTRL               ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
+ #define R_USB_FS0                ((R_USB_FS0_Type *) R_USB_FS0_BASE)
+ #define R_USB_HS0                ((R_USB_HS0_Type *) R_USB_HS0_BASE)
+ #define R_WDT                    ((R_WDT_Type *) R_WDT_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+ #if defined(__CC_ARM)
+  #pragma pop
+ #elif defined(__ICCARM__)
+
+/* leave anonymous unions enabled */
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+ #elif defined(__GNUC__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TMS470__)
+
+/* anonymous unions are enabled by default */
+ #elif defined(__TASKING__)
+  #pragma warning restore
+ #elif defined(__CSMC__)
+
+/* anonymous unions are enabled by default */
+ #endif
+
+/* =========================================================================================================================== */
+/* ================                                 Pos/Mask Cluster Section                                  ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_clusters
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                            CSa                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MOD  ========================================================== */
+ #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
+ #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
+ #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
+ #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
+ #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
+ #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  WCR1  ========================================================== */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
+ #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
+ #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
+/* =========================================================  WCR2  ========================================================== */
+ #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
+ #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
+ #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
+ #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
+ #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
+ #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
+ #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
+ #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
+ #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
+ #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
+ #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
+ #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            CSb                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CR  =========================================================== */
+ #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
+ #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
+ #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  REC  ========================================================== */
+ #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
+ #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
+ #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           SDRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SDCCR  ========================================================= */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDCMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SDAMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  SDSELF  ========================================================= */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SDRFCR  ========================================================= */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
+ #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
+/* ========================================================  SDRFEN  ========================================================= */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SDICR  ========================================================= */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SDIR  ========================================================== */
+ #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
+ #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
+ #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
+ #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  SDADR  ========================================================= */
+ #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
+ #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
+/* =========================================================  SDTR  ========================================================== */
+ #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
+ #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
+ #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
+ #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
+ #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
+ #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
+ #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
+ #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
+ #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
+/* =========================================================  SDMOD  ========================================================= */
+ #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
+ #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
+/* =========================================================  SDSR  ========================================================== */
+ #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
+ #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
+ #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
+ #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
+ #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          BUSERR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ADD  ========================================================== */
+ #define R_BUS_BUSERR_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
+ #define R_BUS_BUSERR_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  STAT  ========================================================== */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
+ #define R_BUS_BUSERR_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
+ #define R_BUS_BUSERR_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSM                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
+ #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           BUSS                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CNT  ========================================================== */
+ #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
+ #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            MB                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  ID  =========================================================== */
+ #define R_CAN0_MB_ID_IDE_Pos    (31UL)         /*!< IDE (Bit 31)                                          */
+ #define R_CAN0_MB_ID_IDE_Msk    (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MB_ID_RTR_Pos    (30UL)         /*!< RTR (Bit 30)                                          */
+ #define R_CAN0_MB_ID_RTR_Msk    (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MB_ID_SID_Pos    (18UL)         /*!< SID (Bit 18)                                          */
+ #define R_CAN0_MB_ID_SID_Msk    (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
+ #define R_CAN0_MB_ID_EID_Pos    (0UL)          /*!< EID (Bit 0)                                           */
+ #define R_CAN0_MB_ID_EID_Msk    (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
+/* ==========================================================  DL  =========================================================== */
+ #define R_CAN0_MB_DL_DLC_Pos    (0UL)          /*!< DLC (Bit 0)                                           */
+ #define R_CAN0_MB_DL_DLC_Msk    (0xfUL)        /*!< DLC (Bitfield-Mask: 0x0f)                             */
+/* ===========================================================  D  =========================================================== */
+ #define R_CAN0_MB_D_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
+ #define R_CAN0_MB_D_DATA_Msk    (0xffUL)       /*!< DATA (Bitfield-Mask: 0xff)                            */
+/* ==========================================================  TS  =========================================================== */
+ #define R_CAN0_MB_TS_TSH_Pos    (8UL)          /*!< TSH (Bit 8)                                           */
+ #define R_CAN0_MB_TS_TSH_Msk    (0xff00UL)     /*!< TSH (Bitfield-Mask: 0xff)                             */
+ #define R_CAN0_MB_TS_TSL_Pos    (0UL)          /*!< TSL (Bit 0)                                           */
+ #define R_CAN0_MB_TS_TSL_Msk    (0xffUL)       /*!< TSL (Bitfield-Mask: 0xff)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          ELSEGR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  BY  =========================================================== */
+ #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
+ #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
+ #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
+ #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
+ #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           ELSR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  HA  =========================================================== */
+ #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
+ #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            TM                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  STTRU  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos    (0UL)          /*!< TMSTTRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk    (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff)                   */
+/* =========================================================  STTRL  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos    (0UL)          /*!< TMSTTRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk    (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff)                   */
+/* =========================================================  CYCR  ========================================================== */
+ #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos      (0UL)          /*!< TMCYCR (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk      (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff)                    */
+/* =========================================================  PLSR  ========================================================== */
+ #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos      (0UL)          /*!< TMPLSR (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk      (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff)                    */
+
+/* =========================================================================================================================== */
+/* ================                                            PR                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  MACRU  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos    (0UL)        /*!< PRMACRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk    (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff)                     */
+/* =========================================================  MACRL  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos    (0UL)        /*!< PRMACRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk    (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                            BG                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  EN  =========================================================== */
+ #define R_GLCDC_BG_EN_SWRST_Pos     (16UL)        /*!< SWRST (Bit 16)                                        */
+ #define R_GLCDC_BG_EN_SWRST_Msk     (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_BG_EN_VEN_Pos       (8UL)         /*!< VEN (Bit 8)                                           */
+ #define R_GLCDC_BG_EN_VEN_Msk       (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_BG_EN_EN_Pos        (0UL)         /*!< EN (Bit 0)                                            */
+ #define R_GLCDC_BG_EN_EN_Msk        (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
+/* =========================================================  PERI  ========================================================== */
+ #define R_GLCDC_BG_PERI_FV_Pos      (16UL)        /*!< FV (Bit 16)                                           */
+ #define R_GLCDC_BG_PERI_FV_Msk      (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_BG_PERI_FH_Pos      (0UL)         /*!< FH (Bit 0)                                            */
+ #define R_GLCDC_BG_PERI_FH_Msk      (0x7ffUL)     /*!< FH (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  SYNC  ========================================================== */
+ #define R_GLCDC_BG_SYNC_VP_Pos      (16UL)        /*!< VP (Bit 16)                                           */
+ #define R_GLCDC_BG_SYNC_VP_Msk      (0xf0000UL)   /*!< VP (Bitfield-Mask: 0x0f)                              */
+ #define R_GLCDC_BG_SYNC_HP_Pos      (0UL)         /*!< HP (Bit 0)                                            */
+ #define R_GLCDC_BG_SYNC_HP_Msk      (0xfUL)       /*!< HP (Bitfield-Mask: 0x0f)                              */
+/* =========================================================  VSIZE  ========================================================= */
+ #define R_GLCDC_BG_VSIZE_VP_Pos     (16UL)        /*!< VP (Bit 16)                                           */
+ #define R_GLCDC_BG_VSIZE_VP_Msk     (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_BG_VSIZE_VW_Pos     (0UL)         /*!< VW (Bit 0)                                            */
+ #define R_GLCDC_BG_VSIZE_VW_Msk     (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  HSIZE  ========================================================= */
+ #define R_GLCDC_BG_HSIZE_HP_Pos     (16UL)        /*!< HP (Bit 16)                                           */
+ #define R_GLCDC_BG_HSIZE_HP_Msk     (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_BG_HSIZE_HW_Pos     (0UL)         /*!< HW (Bit 0)                                            */
+ #define R_GLCDC_BG_HSIZE_HW_Msk     (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
+/* ==========================================================  BGC  ========================================================== */
+ #define R_GLCDC_BG_BGC_R_Pos        (16UL)        /*!< R (Bit 16)                                            */
+ #define R_GLCDC_BG_BGC_R_Msk        (0xff0000UL)  /*!< R (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_BG_BGC_G_Pos        (8UL)         /*!< G (Bit 8)                                             */
+ #define R_GLCDC_BG_BGC_G_Msk        (0xff00UL)    /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_BG_BGC_B_Pos        (0UL)         /*!< B (Bit 0)                                             */
+ #define R_GLCDC_BG_BGC_B_Msk        (0xffUL)      /*!< B (Bitfield-Mask: 0xff)                               */
+/* ==========================================================  MON  ========================================================== */
+ #define R_GLCDC_BG_MON_SWRST_Pos    (16UL)        /*!< SWRST (Bit 16)                                        */
+ #define R_GLCDC_BG_MON_SWRST_Msk    (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_BG_MON_VEN_Pos      (8UL)         /*!< VEN (Bit 8)                                           */
+ #define R_GLCDC_BG_MON_VEN_Msk      (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_BG_MON_EN_Pos       (0UL)         /*!< EN (Bit 0)                                            */
+ #define R_GLCDC_BG_MON_EN_Msk       (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                            GR                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  VEN  ========================================================== */
+ #define R_GLCDC_GR_VEN_PVEN_Pos         (0UL)          /*!< PVEN (Bit 0)                                          */
+ #define R_GLCDC_GR_VEN_PVEN_Msk         (0x1UL)        /*!< PVEN (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FLMRD  ========================================================= */
+ #define R_GLCDC_GR_FLMRD_RENB_Pos       (0UL)          /*!< RENB (Bit 0)                                          */
+ #define R_GLCDC_GR_FLMRD_RENB_Msk       (0x1UL)        /*!< RENB (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FLM1  ========================================================== */
+ #define R_GLCDC_GR_FLM1_BSTMD_Pos       (0UL)          /*!< BSTMD (Bit 0)                                         */
+ #define R_GLCDC_GR_FLM1_BSTMD_Msk       (0x3UL)        /*!< BSTMD (Bitfield-Mask: 0x03)                           */
+/* =========================================================  FLM2  ========================================================== */
+ #define R_GLCDC_GR_FLM2_BASE_Pos        (0UL)          /*!< BASE (Bit 0)                                          */
+ #define R_GLCDC_GR_FLM2_BASE_Msk        (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  FLM3  ========================================================== */
+ #define R_GLCDC_GR_FLM3_LNOFF_Pos       (16UL)         /*!< LNOFF (Bit 16)                                        */
+ #define R_GLCDC_GR_FLM3_LNOFF_Msk       (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  FLM5  ========================================================== */
+ #define R_GLCDC_GR_FLM5_LNNUM_Pos       (16UL)         /*!< LNNUM (Bit 16)                                        */
+ #define R_GLCDC_GR_FLM5_LNNUM_Msk       (0x7ff0000UL)  /*!< LNNUM (Bitfield-Mask: 0x7ff)                          */
+ #define R_GLCDC_GR_FLM5_DATANUM_Pos     (0UL)          /*!< DATANUM (Bit 0)                                       */
+ #define R_GLCDC_GR_FLM5_DATANUM_Msk     (0xffffUL)     /*!< DATANUM (Bitfield-Mask: 0xffff)                       */
+/* =========================================================  FLM6  ========================================================== */
+ #define R_GLCDC_GR_FLM6_FORMAT_Pos      (28UL)         /*!< FORMAT (Bit 28)                                       */
+ #define R_GLCDC_GR_FLM6_FORMAT_Msk      (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07)                          */
+/* ==========================================================  AB1  ========================================================== */
+ #define R_GLCDC_GR_AB1_ARCON_Pos        (12UL)         /*!< ARCON (Bit 12)                                        */
+ #define R_GLCDC_GR_AB1_ARCON_Msk        (0x1000UL)     /*!< ARCON (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_GR_AB1_ARCDISPON_Pos    (8UL)          /*!< ARCDISPON (Bit 8)                                     */
+ #define R_GLCDC_GR_AB1_ARCDISPON_Msk    (0x100UL)      /*!< ARCDISPON (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_GR_AB1_GRCDISPON_Pos    (4UL)          /*!< GRCDISPON (Bit 4)                                     */
+ #define R_GLCDC_GR_AB1_GRCDISPON_Msk    (0x10UL)       /*!< GRCDISPON (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_GR_AB1_DISPSEL_Pos      (0UL)          /*!< DISPSEL (Bit 0)                                       */
+ #define R_GLCDC_GR_AB1_DISPSEL_Msk      (0x3UL)        /*!< DISPSEL (Bitfield-Mask: 0x03)                         */
+/* ==========================================================  AB2  ========================================================== */
+ #define R_GLCDC_GR_AB2_GRCVS_Pos        (16UL)         /*!< GRCVS (Bit 16)                                        */
+ #define R_GLCDC_GR_AB2_GRCVS_Msk        (0x7ff0000UL)  /*!< GRCVS (Bitfield-Mask: 0x7ff)                          */
+ #define R_GLCDC_GR_AB2_GRCVW_Pos        (0UL)          /*!< GRCVW (Bit 0)                                         */
+ #define R_GLCDC_GR_AB2_GRCVW_Msk        (0x7ffUL)      /*!< GRCVW (Bitfield-Mask: 0x7ff)                          */
+/* ==========================================================  AB3  ========================================================== */
+ #define R_GLCDC_GR_AB3_GRCHS_Pos        (16UL)         /*!< GRCHS (Bit 16)                                        */
+ #define R_GLCDC_GR_AB3_GRCHS_Msk        (0x7ff0000UL)  /*!< GRCHS (Bitfield-Mask: 0x7ff)                          */
+ #define R_GLCDC_GR_AB3_GRCHW_Pos        (0UL)          /*!< GRCHW (Bit 0)                                         */
+ #define R_GLCDC_GR_AB3_GRCHW_Msk        (0x7ffUL)      /*!< GRCHW (Bitfield-Mask: 0x7ff)                          */
+/* ==========================================================  AB4  ========================================================== */
+ #define R_GLCDC_GR_AB4_ARCVS_Pos        (16UL)         /*!< ARCVS (Bit 16)                                        */
+ #define R_GLCDC_GR_AB4_ARCVS_Msk        (0x7ff0000UL)  /*!< ARCVS (Bitfield-Mask: 0x7ff)                          */
+ #define R_GLCDC_GR_AB4_ARCVW_Pos        (0UL)          /*!< ARCVW (Bit 0)                                         */
+ #define R_GLCDC_GR_AB4_ARCVW_Msk        (0x7ffUL)      /*!< ARCVW (Bitfield-Mask: 0x7ff)                          */
+/* ==========================================================  AB5  ========================================================== */
+ #define R_GLCDC_GR_AB5_ARCHS_Pos        (16UL)         /*!< ARCHS (Bit 16)                                        */
+ #define R_GLCDC_GR_AB5_ARCHS_Msk        (0x7ff0000UL)  /*!< ARCHS (Bitfield-Mask: 0x7ff)                          */
+ #define R_GLCDC_GR_AB5_ARCHW_Pos        (0UL)          /*!< ARCHW (Bit 0)                                         */
+ #define R_GLCDC_GR_AB5_ARCHW_Msk        (0x7ffUL)      /*!< ARCHW (Bitfield-Mask: 0x7ff)                          */
+/* ==========================================================  AB6  ========================================================== */
+ #define R_GLCDC_GR_AB6_ARCCOEF_Pos      (16UL)         /*!< ARCCOEF (Bit 16)                                      */
+ #define R_GLCDC_GR_AB6_ARCCOEF_Msk      (0x1ff0000UL)  /*!< ARCCOEF (Bitfield-Mask: 0x1ff)                        */
+ #define R_GLCDC_GR_AB6_ARCRATE_Pos      (0UL)          /*!< ARCRATE (Bit 0)                                       */
+ #define R_GLCDC_GR_AB6_ARCRATE_Msk      (0xffUL)       /*!< ARCRATE (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  AB7  ========================================================== */
+ #define R_GLCDC_GR_AB7_ARCDEF_Pos       (16UL)         /*!< ARCDEF (Bit 16)                                       */
+ #define R_GLCDC_GR_AB7_ARCDEF_Msk       (0xff0000UL)   /*!< ARCDEF (Bitfield-Mask: 0xff)                          */
+ #define R_GLCDC_GR_AB7_CKON_Pos         (0UL)          /*!< CKON (Bit 0)                                          */
+ #define R_GLCDC_GR_AB7_CKON_Msk         (0x1UL)        /*!< CKON (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  AB8  ========================================================== */
+ #define R_GLCDC_GR_AB8_CKKG_Pos         (16UL)         /*!< CKKG (Bit 16)                                         */
+ #define R_GLCDC_GR_AB8_CKKG_Msk         (0xff0000UL)   /*!< CKKG (Bitfield-Mask: 0xff)                            */
+ #define R_GLCDC_GR_AB8_CKKB_Pos         (8UL)          /*!< CKKB (Bit 8)                                          */
+ #define R_GLCDC_GR_AB8_CKKB_Msk         (0xff00UL)     /*!< CKKB (Bitfield-Mask: 0xff)                            */
+ #define R_GLCDC_GR_AB8_CKKR_Pos         (0UL)          /*!< CKKR (Bit 0)                                          */
+ #define R_GLCDC_GR_AB8_CKKR_Msk         (0xffUL)       /*!< CKKR (Bitfield-Mask: 0xff)                            */
+/* ==========================================================  AB9  ========================================================== */
+ #define R_GLCDC_GR_AB9_CKA_Pos          (24UL)         /*!< CKA (Bit 24)                                          */
+ #define R_GLCDC_GR_AB9_CKA_Msk          (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff)                             */
+ #define R_GLCDC_GR_AB9_CKG_Pos          (16UL)         /*!< CKG (Bit 16)                                          */
+ #define R_GLCDC_GR_AB9_CKG_Msk          (0xff0000UL)   /*!< CKG (Bitfield-Mask: 0xff)                             */
+ #define R_GLCDC_GR_AB9_CKB_Pos          (8UL)          /*!< CKB (Bit 8)                                           */
+ #define R_GLCDC_GR_AB9_CKB_Msk          (0xff00UL)     /*!< CKB (Bitfield-Mask: 0xff)                             */
+ #define R_GLCDC_GR_AB9_CKR_Pos          (0UL)          /*!< CKR (Bit 0)                                           */
+ #define R_GLCDC_GR_AB9_CKR_Msk          (0xffUL)       /*!< CKR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  BASE  ========================================================== */
+ #define R_GLCDC_GR_BASE_G_Pos           (16UL)         /*!< G (Bit 16)                                            */
+ #define R_GLCDC_GR_BASE_G_Msk           (0xff0000UL)   /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR_BASE_B_Pos           (8UL)          /*!< B (Bit 8)                                             */
+ #define R_GLCDC_GR_BASE_B_Msk           (0xff00UL)     /*!< B (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR_BASE_R_Pos           (0UL)          /*!< R (Bit 0)                                             */
+ #define R_GLCDC_GR_BASE_R_Msk           (0xffUL)       /*!< R (Bitfield-Mask: 0xff)                               */
+/* ========================================================  CLUTINT  ======================================================== */
+ #define R_GLCDC_GR_CLUTINT_SEL_Pos      (16UL)         /*!< SEL (Bit 16)                                          */
+ #define R_GLCDC_GR_CLUTINT_SEL_Msk      (0x10000UL)    /*!< SEL (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_GR_CLUTINT_LINE_Pos     (0UL)          /*!< LINE (Bit 0)                                          */
+ #define R_GLCDC_GR_CLUTINT_LINE_Msk     (0x7ffUL)      /*!< LINE (Bitfield-Mask: 0x7ff)                           */
+/* ==========================================================  MON  ========================================================== */
+ #define R_GLCDC_GR_MON_UNDFLST_Pos      (16UL)         /*!< UNDFLST (Bit 16)                                      */
+ #define R_GLCDC_GR_MON_UNDFLST_Msk      (0x10000UL)    /*!< UNDFLST (Bitfield-Mask: 0x01)                         */
+ #define R_GLCDC_GR_MON_ARCST_Pos        (0UL)          /*!< ARCST (Bit 0)                                         */
+ #define R_GLCDC_GR_MON_ARCST_Msk        (0x1UL)        /*!< ARCST (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                            GAM                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  LATCH  ========================================================= */
+ #define R_GLCDC_GAM_LATCH_VEN_Pos       (0UL)     /*!< VEN (Bit 0)                                           */
+ #define R_GLCDC_GAM_LATCH_VEN_Msk       (0x1UL)   /*!< VEN (Bitfield-Mask: 0x01)                             */
+/* ========================================================  GAM_SW  ========================================================= */
+ #define R_GLCDC_GAM_GAM_SW_GAMON_Pos    (0UL)     /*!< GAMON (Bit 0)                                         */
+ #define R_GLCDC_GAM_GAM_SW_GAMON_Msk    (0x1UL)   /*!< GAMON (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  LUT  ========================================================== */
+ #define R_GLCDC_GAM_LUT___Pos           (0UL)     /*!< _ (Bit 0)                                             */
+ #define R_GLCDC_GAM_LUT___Msk           (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff)                              */
+/* =========================================================  AREA  ========================================================== */
+ #define R_GLCDC_GAM_AREA___Pos          (0UL)     /*!< _ (Bit 0)                                             */
+ #define R_GLCDC_GAM_AREA___Msk          (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff)                              */
+
+/* =========================================================================================================================== */
+/* ================                                            OUT                                            ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  VLATCH  ========================================================= */
+ #define R_GLCDC_OUT_VLATCH_VEN_Pos            (0UL)          /*!< VEN (Bit 0)                                           */
+ #define R_GLCDC_OUT_VLATCH_VEN_Msk            (0x1UL)        /*!< VEN (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  SET  ========================================================== */
+ #define R_GLCDC_OUT_SET_ENDIANON_Pos          (28UL)         /*!< ENDIANON (Bit 28)                                     */
+ #define R_GLCDC_OUT_SET_ENDIANON_Msk          (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01)                        */
+ #define R_GLCDC_OUT_SET_SWAPON_Pos            (24UL)         /*!< SWAPON (Bit 24)                                       */
+ #define R_GLCDC_OUT_SET_SWAPON_Msk            (0x1000000UL)  /*!< SWAPON (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_OUT_SET_FORMAT_Pos            (12UL)         /*!< FORMAT (Bit 12)                                       */
+ #define R_GLCDC_OUT_SET_FORMAT_Msk            (0x3000UL)     /*!< FORMAT (Bitfield-Mask: 0x03)                          */
+ #define R_GLCDC_OUT_SET_FRQSEL_Pos            (8UL)          /*!< FRQSEL (Bit 8)                                        */
+ #define R_GLCDC_OUT_SET_FRQSEL_Msk            (0x300UL)      /*!< FRQSEL (Bitfield-Mask: 0x03)                          */
+ #define R_GLCDC_OUT_SET_DIRSEL_Pos            (4UL)          /*!< DIRSEL (Bit 4)                                        */
+ #define R_GLCDC_OUT_SET_DIRSEL_Msk            (0x10UL)       /*!< DIRSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_OUT_SET_PHASE_Pos             (0UL)          /*!< PHASE (Bit 0)                                         */
+ #define R_GLCDC_OUT_SET_PHASE_Msk             (0x3UL)        /*!< PHASE (Bitfield-Mask: 0x03)                           */
+/* ========================================================  BRIGHT1  ======================================================== */
+ #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos          (0UL)          /*!< BRTG (Bit 0)                                          */
+ #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk          (0x3ffUL)      /*!< BRTG (Bitfield-Mask: 0x3ff)                           */
+/* ========================================================  BRIGHT2  ======================================================== */
+ #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos          (16UL)         /*!< BRTB (Bit 16)                                         */
+ #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk          (0x3ff0000UL)  /*!< BRTB (Bitfield-Mask: 0x3ff)                           */
+ #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos          (0UL)          /*!< BRTR (Bit 0)                                          */
+ #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk          (0x3ffUL)      /*!< BRTR (Bitfield-Mask: 0x3ff)                           */
+/* =======================================================  CONTRAST  ======================================================== */
+ #define R_GLCDC_OUT_CONTRAST_CONTG_Pos        (16UL)         /*!< CONTG (Bit 16)                                        */
+ #define R_GLCDC_OUT_CONTRAST_CONTG_Msk        (0xff0000UL)   /*!< CONTG (Bitfield-Mask: 0xff)                           */
+ #define R_GLCDC_OUT_CONTRAST_CONTB_Pos        (8UL)          /*!< CONTB (Bit 8)                                         */
+ #define R_GLCDC_OUT_CONTRAST_CONTB_Msk        (0xff00UL)     /*!< CONTB (Bitfield-Mask: 0xff)                           */
+ #define R_GLCDC_OUT_CONTRAST_CONTR_Pos        (0UL)          /*!< CONTR (Bit 0)                                         */
+ #define R_GLCDC_OUT_CONTRAST_CONTR_Msk        (0xffUL)       /*!< CONTR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  PDTHA  ========================================================= */
+ #define R_GLCDC_OUT_PDTHA_SEL_Pos             (20UL)         /*!< SEL (Bit 20)                                          */
+ #define R_GLCDC_OUT_PDTHA_SEL_Msk             (0x300000UL)   /*!< SEL (Bitfield-Mask: 0x03)                             */
+ #define R_GLCDC_OUT_PDTHA_FORM_Pos            (16UL)         /*!< FORM (Bit 16)                                         */
+ #define R_GLCDC_OUT_PDTHA_FORM_Msk            (0x30000UL)    /*!< FORM (Bitfield-Mask: 0x03)                            */
+ #define R_GLCDC_OUT_PDTHA_PA_Pos              (12UL)         /*!< PA (Bit 12)                                           */
+ #define R_GLCDC_OUT_PDTHA_PA_Msk              (0x3000UL)     /*!< PA (Bitfield-Mask: 0x03)                              */
+ #define R_GLCDC_OUT_PDTHA_PB_Pos              (8UL)          /*!< PB (Bit 8)                                            */
+ #define R_GLCDC_OUT_PDTHA_PB_Msk              (0x300UL)      /*!< PB (Bitfield-Mask: 0x03)                              */
+ #define R_GLCDC_OUT_PDTHA_PC_Pos              (4UL)          /*!< PC (Bit 4)                                            */
+ #define R_GLCDC_OUT_PDTHA_PC_Msk              (0x30UL)       /*!< PC (Bitfield-Mask: 0x03)                              */
+ #define R_GLCDC_OUT_PDTHA_PD_Pos              (0UL)          /*!< PD (Bit 0)                                            */
+ #define R_GLCDC_OUT_PDTHA_PD_Msk              (0x3UL)        /*!< PD (Bitfield-Mask: 0x03)                              */
+/* =======================================================  CLKPHASE  ======================================================== */
+ #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos     (12UL)         /*!< FRONTGAM (Bit 12)                                     */
+ #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk     (0x1000UL)     /*!< FRONTGAM (Bitfield-Mask: 0x01)                        */
+ #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos      (8UL)          /*!< LCDEDGE (Bit 8)                                       */
+ #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk      (0x100UL)      /*!< LCDEDGE (Bitfield-Mask: 0x01)                         */
+ #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos    (6UL)          /*!< TCON0EDGE (Bit 6)                                     */
+ #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk    (0x40UL)       /*!< TCON0EDGE (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos    (5UL)          /*!< TCON1EDGE (Bit 5)                                     */
+ #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk    (0x20UL)       /*!< TCON1EDGE (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos    (4UL)          /*!< TCON2EDGE (Bit 4)                                     */
+ #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk    (0x10UL)       /*!< TCON2EDGE (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos    (3UL)          /*!< TCON3EDGE (Bit 3)                                     */
+ #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk    (0x8UL)        /*!< TCON3EDGE (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                           TCON                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  TIM  ========================================================== */
+ #define R_GLCDC_TCON_TIM_HALF_Pos       (16UL)        /*!< HALF (Bit 16)                                         */
+ #define R_GLCDC_TCON_TIM_HALF_Msk       (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff)                           */
+ #define R_GLCDC_TCON_TIM_OFFSET_Pos     (0UL)         /*!< OFFSET (Bit 0)                                        */
+ #define R_GLCDC_TCON_TIM_OFFSET_Msk     (0x7ffUL)     /*!< OFFSET (Bitfield-Mask: 0x7ff)                         */
+/* =========================================================  STVA1  ========================================================= */
+ #define R_GLCDC_TCON_STVA1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
+ #define R_GLCDC_TCON_STVA1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_TCON_STVA1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
+ #define R_GLCDC_TCON_STVA1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  STVB1  ========================================================= */
+ #define R_GLCDC_TCON_STVB1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
+ #define R_GLCDC_TCON_STVB1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_TCON_STVB1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
+ #define R_GLCDC_TCON_STVB1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  STVA2  ========================================================= */
+ #define R_GLCDC_TCON_STVA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
+ #define R_GLCDC_TCON_STVA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_TCON_STVA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
+ #define R_GLCDC_TCON_STVA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
+/* =========================================================  STVB2  ========================================================= */
+ #define R_GLCDC_TCON_STVB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
+ #define R_GLCDC_TCON_STVB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_TCON_STVB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
+ #define R_GLCDC_TCON_STVB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
+/* =========================================================  STHA1  ========================================================= */
+ #define R_GLCDC_TCON_STHA1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
+ #define R_GLCDC_TCON_STHA1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_TCON_STHA1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
+ #define R_GLCDC_TCON_STHA1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  STHB1  ========================================================= */
+ #define R_GLCDC_TCON_STHB1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
+ #define R_GLCDC_TCON_STHB1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
+ #define R_GLCDC_TCON_STHB1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
+ #define R_GLCDC_TCON_STHB1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
+/* =========================================================  STHA2  ========================================================= */
+ #define R_GLCDC_TCON_STHA2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
+ #define R_GLCDC_TCON_STHA2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_TCON_STHA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
+ #define R_GLCDC_TCON_STHA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_TCON_STHA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
+ #define R_GLCDC_TCON_STHA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
+/* =========================================================  STHB2  ========================================================= */
+ #define R_GLCDC_TCON_STHB2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
+ #define R_GLCDC_TCON_STHB2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_TCON_STHB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
+ #define R_GLCDC_TCON_STHB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GLCDC_TCON_STHB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
+ #define R_GLCDC_TCON_STHB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
+/* ==========================================================  DE  =========================================================== */
+ #define R_GLCDC_TCON_DE_INV_Pos         (0UL)         /*!< INV (Bit 0)                                           */
+ #define R_GLCDC_TCON_DE_INV_Msk         (0x1UL)       /*!< INV (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          SYSCNT                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DTCTEN  ========================================================= */
+ #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos     (2UL)          /*!< L2UNDFDTC (Bit 2)                                     */
+ #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk     (0x4UL)        /*!< L2UNDFDTC (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos     (1UL)          /*!< L1UNDFDTC (Bit 1)                                     */
+ #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk     (0x2UL)        /*!< L1UNDFDTC (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos       (0UL)          /*!< VPOSDTC (Bit 0)                                       */
+ #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk       (0x1UL)        /*!< VPOSDTC (Bitfield-Mask: 0x01)                         */
+/* =========================================================  INTEN  ========================================================= */
+ #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos    (2UL)          /*!< L2UNDFINTEN (Bit 2)                                   */
+ #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk    (0x4UL)        /*!< L2UNDFINTEN (Bitfield-Mask: 0x01)                     */
+ #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos    (1UL)          /*!< L1UNDFINTEN (Bit 1)                                   */
+ #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk    (0x2UL)        /*!< L1UNDFINTEN (Bitfield-Mask: 0x01)                     */
+ #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos      (0UL)          /*!< VPOSINTEN (Bit 0)                                     */
+ #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk      (0x1UL)        /*!< VPOSINTEN (Bitfield-Mask: 0x01)                       */
+/* =========================================================  STCLR  ========================================================= */
+ #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos      (2UL)          /*!< L2UNDFCLR (Bit 2)                                     */
+ #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk      (0x4UL)        /*!< L2UNDFCLR (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos      (1UL)          /*!< L1UNDFCLR (Bit 1)                                     */
+ #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk      (0x2UL)        /*!< L1UNDFCLR (Bitfield-Mask: 0x01)                       */
+ #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos        (0UL)          /*!< VPOSCLR (Bit 0)                                       */
+ #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk        (0x1UL)        /*!< VPOSCLR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  STMON  ========================================================= */
+ #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos         (2UL)          /*!< L2UNDF (Bit 2)                                        */
+ #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk         (0x4UL)        /*!< L2UNDF (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos         (1UL)          /*!< L1UNDF (Bit 1)                                        */
+ #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk         (0x2UL)        /*!< L1UNDF (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_SYSCNT_STMON_VPOS_Pos           (0UL)          /*!< VPOS (Bit 0)                                          */
+ #define R_GLCDC_SYSCNT_STMON_VPOS_Msk           (0x1UL)        /*!< VPOS (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PANEL_CLK  ======================================================= */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos        (16UL)         /*!< VER (Bit 16)                                          */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk        (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff)                           */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos     (12UL)         /*!< PIXSEL (Bit 12)                                       */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk     (0x1000UL)     /*!< PIXSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos     (8UL)          /*!< CLKSEL (Bit 8)                                        */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk     (0x100UL)      /*!< CLKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos      (6UL)          /*!< CLKEN (Bit 6)                                         */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk      (0x40UL)       /*!< CLKEN (Bitfield-Mask: 0x01)                           */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos       (0UL)          /*!< DCDR (Bit 0)                                          */
+ #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk       (0x3fUL)       /*!< DCDR (Bitfield-Mask: 0x3f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          GTDLYR                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  A  =========================================================== */
+ #define R_GPT_ODC_GTDLYR_A_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
+ #define R_GPT_ODC_GTDLYR_A_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
+/* ===========================================================  B  =========================================================== */
+ #define R_GPT_ODC_GTDLYR_B_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
+ #define R_GPT_ODC_GTDLYR_B_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
+
+/* =========================================================================================================================== */
+/* ================                                            SAR                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  L  =========================================================== */
+ #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
+ #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
+/* ===========================================================  U  =========================================================== */
+ #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
+ #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
+ #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
+ #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                          REGION                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  C  =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos         (2UL)          /*!< WP (Bit 2)                                            */
+ #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk         (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+ #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos         (1UL)          /*!< RP (Bit 1)                                            */
+ #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk         (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
+ #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ===========================================================  S  =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos    (0UL)          /*!< MMPUSmn (Bit 0)                                       */
+ #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk    (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff)                   */
+/* ===========================================================  E  =========================================================== */
+ #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos    (0UL)          /*!< MMPUEmn (Bit 0)                                       */
+ #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk    (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                           MMPU                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  CTL  ========================================================== */
+ #define R_MPU_MMPU_MMPU_CTL_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_MPU_MMPU_MMPU_CTL_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_MMPU_MMPU_CTL_OAD_Pos       (1UL)      /*!< OAD (Bit 1)                                           */
+ #define R_MPU_MMPU_MMPU_CTL_OAD_Msk       (0x2UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
+ #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos    (0UL)      /*!< ENABLE (Bit 0)                                        */
+ #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk    (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PT  =========================================================== */
+ #define R_MPU_MMPU_MMPU_PT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_MPU_MMPU_MMPU_PT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
+ #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           SMPU                                            ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  R  =========================================================== */
+ #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos    (15UL)     /*!< WPSRAMHS (Bit 15)                                     */
+ #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk    (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01)                        */
+ #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos    (14UL)     /*!< RPSRAMHS (Bit 14)                                     */
+ #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk    (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01)                        */
+ #define R_MPU_SMPU_SMPU_R_WPFLI_Pos       (13UL)     /*!< WPFLI (Bit 13)                                        */
+ #define R_MPU_SMPU_SMPU_R_WPFLI_Msk       (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01)                           */
+ #define R_MPU_SMPU_SMPU_R_RPFLI_Pos       (12UL)     /*!< RPFLI (Bit 12)                                        */
+ #define R_MPU_SMPU_SMPU_R_RPFLI_Msk       (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01)                           */
+ #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos      (7UL)      /*!< WPGRPC (Bit 7)                                        */
+ #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk      (0x80UL)   /*!< WPGRPC (Bitfield-Mask: 0x01)                          */
+ #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos      (6UL)      /*!< RPGRPC (Bit 6)                                        */
+ #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk      (0x40UL)   /*!< RPGRPC (Bitfield-Mask: 0x01)                          */
+ #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos      (5UL)      /*!< WPGRPB (Bit 5)                                        */
+ #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk      (0x20UL)   /*!< WPGRPB (Bitfield-Mask: 0x01)                          */
+ #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos      (4UL)      /*!< RPGRPB (Bit 4)                                        */
+ #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk      (0x10UL)   /*!< RPGRPB (Bitfield-Mask: 0x01)                          */
+ #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos      (3UL)      /*!< WPGRPA (Bit 3)                                        */
+ #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk      (0x8UL)    /*!< WPGRPA (Bitfield-Mask: 0x01)                          */
+ #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos      (2UL)      /*!< RPGRPA (Bit 2)                                        */
+ #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk      (0x4UL)    /*!< RPGRPA (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                            SP                                             ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  OAD  ========================================================== */
+ #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
+ #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  CTL  ========================================================== */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
+ #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
+/* ==========================================================  PT  =========================================================== */
+ #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
+ #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+/* ==========================================================  SA  =========================================================== */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
+/* ==========================================================  EA  =========================================================== */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
+
+/* =========================================================================================================================== */
+/* ================                                            AMP                                            ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  OS  =========================================================== */
+/* ==========================================================  PS  =========================================================== */
+/* ==========================================================  MS  =========================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           AMPOT                                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  P  =========================================================== */
+ #define R_OPAMP_AMPOT_P_TRMP_Pos    (0UL)    /*!< TRMP (Bit 0)                                          */
+ #define R_OPAMP_AMPOT_P_TRMP_Msk    (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f)                            */
+/* ===========================================================  N  =========================================================== */
+ #define R_OPAMP_AMPOT_N_TRMN_Pos    (0UL)    /*!< TRMN (Bit 0)                                          */
+ #define R_OPAMP_AMPOT_N_TRMN_Msk    (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            PIN                                            ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  PmnPFS_BY  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PmnPFS_HA  ======================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PmnPFS  ========================================================= */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           PORT                                            ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           RTCCR                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RTCCR  ========================================================= */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
+ #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                            CP                                             ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  RSEC  ========================================================== */
+ #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMIN  ========================================================== */
+ #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
+/* ==========================================================  RHR  ========================================================== */
+ #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
+ #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RDAY  ========================================================== */
+ #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
+ #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RMON  ========================================================== */
+ #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          PIPE_TR                                          ================ */
+/* =========================================================================================================================== */
+
+/* ===========================================================  E  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
+/* ===========================================================  N  =========================================================== */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
+
+/** @} */ /* End of group PosMask_clusters */
+
+/* =========================================================================================================================== */
+/* ================                                Pos/Mask Peripheral Section                                ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ACMPHS0                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CMPCTL  ========================================================= */
+ #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
+ #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
+ #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
+ #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
+ #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
+ #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
+ #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
+ #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
+ #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
+ #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
+ #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
+/* ========================================================  CMPSEL0  ======================================================== */
+ #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
+ #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  CMPSEL1  ======================================================== */
+ #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
+ #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  CMPMON  ========================================================= */
+ #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
+ #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CPIOC  ========================================================= */
+ #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
+ #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
+ #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
+ #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ACMPLP                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  COMPMDR  ======================================================== */
+ #define R_ACMPLP_COMPMDR_C1MON_Pos      (7UL)    /*!< C1MON (Bit 7)                                         */
+ #define R_ACMPLP_COMPMDR_C1MON_Msk      (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C1VRF_Pos      (6UL)    /*!< C1VRF (Bit 6)                                         */
+ #define R_ACMPLP_COMPMDR_C1VRF_Msk      (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C1WDE_Pos      (5UL)    /*!< C1WDE (Bit 5)                                         */
+ #define R_ACMPLP_COMPMDR_C1WDE_Msk      (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C1ENB_Pos      (4UL)    /*!< C1ENB (Bit 4)                                         */
+ #define R_ACMPLP_COMPMDR_C1ENB_Msk      (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C0MON_Pos      (3UL)    /*!< C0MON (Bit 3)                                         */
+ #define R_ACMPLP_COMPMDR_C0MON_Msk      (0x8UL)  /*!< C0MON (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C0WDE_Pos      (1UL)    /*!< C0WDE (Bit 1)                                         */
+ #define R_ACMPLP_COMPMDR_C0WDE_Msk      (0x2UL)  /*!< C0WDE (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C0VRF_Pos      (2UL)    /*!< C0VRF (Bit 2)                                         */
+ #define R_ACMPLP_COMPMDR_C0VRF_Msk      (0x4UL)  /*!< C0VRF (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPMDR_C0ENB_Pos      (0UL)    /*!< C0ENB (Bit 0)                                         */
+ #define R_ACMPLP_COMPMDR_C0ENB_Msk      (0x1UL)  /*!< C0ENB (Bitfield-Mask: 0x01)                           */
+/* ========================================================  COMPFIR  ======================================================== */
+ #define R_ACMPLP_COMPFIR_C1EDG_Pos      (7UL)    /*!< C1EDG (Bit 7)                                         */
+ #define R_ACMPLP_COMPFIR_C1EDG_Msk      (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPFIR_C1EPO_Pos      (6UL)    /*!< C1EPO (Bit 6)                                         */
+ #define R_ACMPLP_COMPFIR_C1EPO_Msk      (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPFIR_C1FCK_Pos      (4UL)    /*!< C1FCK (Bit 4)                                         */
+ #define R_ACMPLP_COMPFIR_C1FCK_Msk      (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03)                           */
+ #define R_ACMPLP_COMPFIR_C0EDG_Pos      (3UL)    /*!< C0EDG (Bit 3)                                         */
+ #define R_ACMPLP_COMPFIR_C0EDG_Msk      (0x8UL)  /*!< C0EDG (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPFIR_C0EPO_Pos      (2UL)    /*!< C0EPO (Bit 2)                                         */
+ #define R_ACMPLP_COMPFIR_C0EPO_Msk      (0x4UL)  /*!< C0EPO (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPFIR_C0FCK_Pos      (0UL)    /*!< C0FCK (Bit 0)                                         */
+ #define R_ACMPLP_COMPFIR_C0FCK_Msk      (0x3UL)  /*!< C0FCK (Bitfield-Mask: 0x03)                           */
+/* ========================================================  COMPOCR  ======================================================== */
+ #define R_ACMPLP_COMPOCR_SPDMD_Pos      (7UL)    /*!< SPDMD (Bit 7)                                         */
+ #define R_ACMPLP_COMPOCR_SPDMD_Msk      (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01)                           */
+ #define R_ACMPLP_COMPOCR_C1OP_Pos       (6UL)    /*!< C1OP (Bit 6)                                          */
+ #define R_ACMPLP_COMPOCR_C1OP_Msk       (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01)                            */
+ #define R_ACMPLP_COMPOCR_C1OE_Pos       (5UL)    /*!< C1OE (Bit 5)                                          */
+ #define R_ACMPLP_COMPOCR_C1OE_Msk       (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01)                            */
+ #define R_ACMPLP_COMPOCR_C0OP_Pos       (2UL)    /*!< C0OP (Bit 2)                                          */
+ #define R_ACMPLP_COMPOCR_C0OP_Msk       (0x4UL)  /*!< C0OP (Bitfield-Mask: 0x01)                            */
+ #define R_ACMPLP_COMPOCR_C0OE_Pos       (1UL)    /*!< C0OE (Bit 1)                                          */
+ #define R_ACMPLP_COMPOCR_C0OE_Msk       (0x2UL)  /*!< C0OE (Bitfield-Mask: 0x01)                            */
+/* =======================================================  COMPSEL0  ======================================================== */
+ #define R_ACMPLP_COMPSEL0_IVCMP1_Pos    (4UL)    /*!< IVCMP1 (Bit 4)                                        */
+ #define R_ACMPLP_COMPSEL0_IVCMP1_Msk    (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07)                          */
+ #define R_ACMPLP_COMPSEL0_IVCMP0_Pos    (0UL)    /*!< IVCMP0 (Bit 0)                                        */
+ #define R_ACMPLP_COMPSEL0_IVCMP0_Msk    (0x7UL)  /*!< IVCMP0 (Bitfield-Mask: 0x07)                          */
+/* =======================================================  COMPSEL1  ======================================================== */
+ #define R_ACMPLP_COMPSEL1_C1VRF2_Pos    (7UL)    /*!< C1VRF2 (Bit 7)                                        */
+ #define R_ACMPLP_COMPSEL1_C1VRF2_Msk    (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01)                          */
+ #define R_ACMPLP_COMPSEL1_IVREF1_Pos    (4UL)    /*!< IVREF1 (Bit 4)                                        */
+ #define R_ACMPLP_COMPSEL1_IVREF1_Msk    (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07)                          */
+ #define R_ACMPLP_COMPSEL1_IVREF0_Pos    (0UL)    /*!< IVREF0 (Bit 0)                                        */
+ #define R_ACMPLP_COMPSEL1_IVREF0_Msk    (0x7UL)  /*!< IVREF0 (Bitfield-Mask: 0x07)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_ADC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ADCSR  ========================================================= */
+ #define R_ADC0_ADCSR_ADST_Pos              (15UL)     /*!< ADST (Bit 15)                                         */
+ #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_ADCS_Pos              (13UL)     /*!< ADCS (Bit 13)                                         */
+ #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
+ #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)     /*!< ADHSC (Bit 10)                                        */
+ #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)  /*!< ADHSC (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_TRGE_Pos              (9UL)      /*!< TRGE (Bit 9)                                          */
+ #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)      /*!< EXTRG (Bit 8)                                         */
+ #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCSR_DBLE_Pos              (7UL)      /*!< DBLE (Bit 7)                                          */
+ #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)      /*!< GBADIE (Bit 6)                                        */
+ #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)      /*!< DBLANS (Bit 0)                                        */
+ #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
+/* ========================================================  ADANSA  ========================================================= */
+ #define R_ADC0_ADANSA_ANSA_Pos             (0UL)      /*!< ANSA (Bit 0)                                          */
+ #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)    /*!< ANSA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADADS  ========================================================= */
+ #define R_ADC0_ADADS_ADS_Pos               (0UL)      /*!< ADS (Bit 0)                                           */
+ #define R_ADC0_ADADS_ADS_Msk               (0x1UL)    /*!< ADS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ADADC  ========================================================= */
+ #define R_ADC0_ADADC_ADC_Pos               (0UL)      /*!< ADC (Bit 0)                                           */
+ #define R_ADC0_ADADC_ADC_Msk               (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
+ #define R_ADC0_ADADC_AVEE_Pos              (7UL)      /*!< AVEE (Bit 7)                                          */
+ #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ADCER  ========================================================= */
+ #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)     /*!< ADRFMT (Bit 15)                                       */
+ #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_ADINV_Pos             (14UL)     /*!< ADINV (Bit 14)                                        */
+ #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGM_Pos             (11UL)     /*!< DIAGM (Bit 11)                                        */
+ #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)  /*!< DIAGM (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)     /*!< DIAGLD (Bit 10)                                       */
+ #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)  /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)      /*!< DIAGVAL (Bit 8)                                       */
+ #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)  /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
+ #define R_ADC0_ADCER_ACE_Pos               (5UL)      /*!< ACE (Bit 5)                                           */
+ #define R_ADC0_ADCER_ACE_Msk               (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
+ #define R_ADC0_ADCER_ADPRC_Pos             (1UL)      /*!< ADPRC (Bit 1)                                         */
+ #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
+/* ========================================================  ADSTRGR  ======================================================== */
+ #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)      /*!< TRSA (Bit 8)                                          */
+ #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
+ #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)      /*!< TRSB (Bit 0)                                          */
+ #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  ADEXICR  ======================================================== */
+ #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)     /*!< OCSB (Bit 11)                                         */
+ #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)  /*!< OCSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)     /*!< TSSB (Bit 10)                                         */
+ #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)  /*!< TSSB (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)      /*!< OCSA (Bit 9)                                          */
+ #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)  /*!< OCSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)      /*!< TSSA (Bit 8)                                          */
+ #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)  /*!< TSSA (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)      /*!< OCSAD (Bit 1)                                         */
+ #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)    /*!< OCSAD (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)      /*!< TSSAD (Bit 0)                                         */
+ #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)    /*!< TSSAD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ADANSB  ========================================================= */
+ #define R_ADC0_ADANSB_ANSB_Pos             (0UL)      /*!< ANSB (Bit 0)                                          */
+ #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)    /*!< ANSB (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADDBLDR  ======================================================== */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)      /*!< ADDBLDR (Bit 0)                                       */
+ #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  ADTSDR  ========================================================= */
+ #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)      /*!< ADTSDR (Bit 0)                                        */
+ #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  ADOCDR  ========================================================= */
+ #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)      /*!< ADOCDR (Bit 0)                                        */
+ #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  ADRD_RIGHT  ======================================================= */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)     /*!< DIAGST (Bit 14)                                       */
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)      /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff)                            */
+/* =======================================================  ADRD_LEFT  ======================================================= */
+ #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)      /*!< AD (Bit 2)                                            */
+ #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff)                            */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)      /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)    /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* =========================================================  ADDR  ========================================================== */
+ #define R_ADC0_ADDR_ADDR_Pos               (0UL)      /*!< ADDR (Bit 0)                                          */
+ #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  ADSHCR  ========================================================= */
+ #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)     /*!< SHANS2 (Bit 10)                                       */
+ #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)  /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)      /*!< SHANS1 (Bit 9)                                        */
+ #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)  /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)      /*!< SHANS0 (Bit 8)                                        */
+ #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)  /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)      /*!< SSTSH (Bit 0)                                         */
+ #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
+/* ========================================================  ADDISCR  ======================================================== */
+ #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)      /*!< CHARGE (Bit 4)                                        */
+ #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)   /*!< CHARGE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)      /*!< ADNDIS (Bit 0)                                        */
+ #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)    /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  ADSHMSR  ======================================================== */
+ #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)      /*!< SHMD (Bit 0)                                          */
+ #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)    /*!< SHMD (Bitfield-Mask: 0x01)                            */
+/* ========================================================  ADGSPCR  ======================================================== */
+ #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)     /*!< GBRP (Bit 15)                                         */
+ #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
+ #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)      /*!< GBRSCN (Bit 1)                                        */
+ #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)      /*!< PGS (Bit 0)                                           */
+ #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  ADICR  ========================================================= */
+ #define R_ADC0_ADICR_ADIC_Pos              (0UL)      /*!< ADIC (Bit 0)                                          */
+ #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)    /*!< ADIC (Bitfield-Mask: 0x03)                            */
+/* =======================================================  ADDBLDRA  ======================================================== */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)      /*!< ADDBLDRA (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADDBLDRB  ======================================================== */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)      /*!< ADDBLDRB (Bit 0)                                      */
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
+/* ======================================================  ADHVREFCNT  ======================================================= */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)      /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)   /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)      /*!< LVSEL (Bit 4)                                         */
+ #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)   /*!< LVSEL (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)      /*!< HVSEL (Bit 0)                                         */
+ #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)    /*!< HVSEL (Bitfield-Mask: 0x03)                           */
+/* =======================================================  ADWINMON  ======================================================== */
+ #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)      /*!< MONCMPB (Bit 5)                                       */
+ #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)      /*!< MONCMPA (Bit 4)                                       */
+ #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)      /*!< MONCOMB (Bit 0)                                       */
+ #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ADCMPCR  ======================================================== */
+ #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)     /*!< CMPAIE (Bit 15)                                       */
+ #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)     /*!< WCMPE (Bit 14)                                        */
+ #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)     /*!< CMPBIE (Bit 13)                                       */
+ #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)     /*!< CMPAE (Bit 11)                                        */
+ #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)      /*!< CMPBE (Bit 9)                                         */
+ #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)      /*!< CMPAB (Bit 0)                                         */
+ #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
+/* ======================================================  ADCMPANSER  ======================================================= */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)      /*!< CMPOCA (Bit 1)                                        */
+ #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)    /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)      /*!< CMPTSA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)    /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
+/* =======================================================  ADCMPLER  ======================================================== */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)      /*!< CMPLOCA (Bit 1)                                       */
+ #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)    /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)      /*!< CMPLTSA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)    /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPANSR  ======================================================= */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)      /*!< CMPCHA (Bit 0)                                        */
+ #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)    /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADCMPLR  ======================================================== */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)      /*!< CMPLCHA (Bit 0)                                       */
+ #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)    /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ADCMPDR0  ======================================================== */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)      /*!< ADCMPDR0 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPDR1  ======================================================== */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)      /*!< ADCMPDR1 (Bit 0)                                      */
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  ADCMPSR  ======================================================== */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)      /*!< CMPSTCHA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)    /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPSER  ======================================================== */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)      /*!< CMPSTOCA (Bit 1)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)    /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)      /*!< CMPSTTSA (Bit 0)                                      */
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)    /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
+/* =======================================================  ADCMPBNSR  ======================================================= */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)      /*!< CMPLB (Bit 7)                                         */
+ #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)      /*!< CMPCHB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
+/* =======================================================  ADWINLLB  ======================================================== */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)      /*!< ADWINLLB (Bit 0)                                      */
+ #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADWINULB  ======================================================== */
+ #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)      /*!< ADWINULB (Bit 0)                                      */
+ #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
+/* =======================================================  ADCMPBSR  ======================================================== */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)      /*!< CMPSTB (Bit 0)                                        */
+ #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADSSTRL  ======================================================== */
+ #define R_ADC0_ADSSTRL_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRT  ======================================================== */
+ #define R_ADC0_ADSSTRT_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTRO  ======================================================== */
+ #define R_ADC0_ADSSTRO_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADSSTR  ========================================================= */
+ #define R_ADC0_ADSSTR_SST_Pos              (0UL)      /*!< SST (Bit 0)                                           */
+ #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
+/* ========================================================  ADPGACR  ======================================================== */
+ #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)     /*!< P002GEN (Bit 11)                                      */
+ #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)  /*!< P002GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)     /*!< P002ENAMP (Bit 10)                                    */
+ #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)  /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)      /*!< P002SEL1 (Bit 9)                                      */
+ #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)  /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)      /*!< P002SEL0 (Bit 8)                                      */
+ #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)  /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)      /*!< P001GEN (Bit 7)                                       */
+ #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)   /*!< P001GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)      /*!< P001ENAMP (Bit 6)                                     */
+ #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)   /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)      /*!< P001SEL1 (Bit 5)                                      */
+ #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)   /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)      /*!< P001SEL0 (Bit 4)                                      */
+ #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)   /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)      /*!< P000GEN (Bit 3)                                       */
+ #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)    /*!< P000GEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)      /*!< P000ENAMP (Bit 2)                                     */
+ #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)    /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)      /*!< P000SEL1 (Bit 1)                                      */
+ #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)    /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
+ #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)      /*!< P000SEL0 (Bit 0)                                      */
+ #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)    /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  ADRD  ========================================================== */
+ #define R_ADC0_ADRD_AD_Pos                 (0UL)      /*!< AD (Bit 0)                                            */
+ #define R_ADC0_ADRD_AD_Msk                 (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff)                            */
+/* =========================================================  ADRST  ========================================================= */
+ #define R_ADC0_ADRST_DIAGST_Pos            (0UL)      /*!< DIAGST (Bit 0)                                        */
+ #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)    /*!< DIAGST (Bitfield-Mask: 0x03)                          */
+/* ======================================================  VREFAMPCNT  ======================================================= */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)      /*!< VREFADCG (Bit 1)                                      */
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)    /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)      /*!< VREFADCEN (Bit 3)                                     */
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)    /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)      /*!< ADSLP (Bit 7)                                         */
+ #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)   /*!< ADSLP (Bitfield-Mask: 0x01)                           */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)      /*!< OLDETEN (Bit 0)                                       */
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)    /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)      /*!< BGREN (Bit 4)                                         */
+ #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)   /*!< BGREN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  ADCALEXE  ======================================================== */
+ #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)      /*!< CALEXE (Bit 7)                                        */
+ #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)   /*!< CALEXE (Bitfield-Mask: 0x01)                          */
+ #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)      /*!< CALMON (Bit 6)                                        */
+ #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)   /*!< CALMON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ADANIM  ========================================================= */
+ #define R_ADC0_ADANIM_ANIM_Pos             (0UL)      /*!< ANIM (Bit 0)                                          */
+ #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)    /*!< ANIM (Bitfield-Mask: 0x01)                            */
+/* =======================================================  ADPGAGS0  ======================================================== */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)      /*!< P002GAIN (Bit 8)                                      */
+ #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)  /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)      /*!< P001GAIN (Bit 4)                                      */
+ #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)   /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)      /*!< P000GAIN (Bit 0)                                      */
+ #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)    /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
+/* =======================================================  ADPGADCR0  ======================================================= */
+ #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)     /*!< P003DG (Bit 12)                                       */
+ #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)     /*!< P002DEN (Bit 11)                                      */
+ #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)  /*!< P002DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)      /*!< P002DG (Bit 8)                                        */
+ #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)  /*!< P002DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)      /*!< P001DEN (Bit 7)                                       */
+ #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)   /*!< P001DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)      /*!< P001DG (Bit 4)                                        */
+ #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)   /*!< P001DG (Bitfield-Mask: 0x03)                          */
+ #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)      /*!< P000DEN (Bit 3)                                       */
+ #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)    /*!< P000DEN (Bitfield-Mask: 0x01)                         */
+ #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)      /*!< P000DG (Bit 0)                                        */
+ #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)    /*!< P000DG (Bitfield-Mask: 0x03)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_AGT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  AGT  ========================================================== */
+ #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
+ #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  AGTCMA  ========================================================= */
+ #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
+ #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  AGTCMB  ========================================================= */
+ #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
+ #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  AGTCR  ========================================================= */
+ #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
+ #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
+ #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
+ #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
+ #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
+ #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
+ #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
+ #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AGTMR1  ========================================================= */
+ #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
+ #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
+ #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
+ #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
+ #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
+ #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
+/* ========================================================  AGTMR2  ========================================================= */
+ #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
+ #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
+ #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
+/* ========================================================  AGTIOC  ========================================================= */
+ #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
+ #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
+ #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
+ #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
+ #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
+ #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
+ #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
+ #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
+/* ========================================================  AGTISR  ========================================================= */
+ #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
+ #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AGTCMSR  ======================================================== */
+ #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
+ #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
+ #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
+ #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
+ #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
+ #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
+ #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
+ #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
+ #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
+ #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
+ #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
+ #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
+/* =======================================================  AGTIOSEL  ======================================================== */
+ #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
+ #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_BUS                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CSRECEN  ======================================================== */
+ #define R_BUS_CSRECEN_RCVENM_Pos    (8UL)     /*!< RCVENM (Bit 8)                                        */
+ #define R_BUS_CSRECEN_RCVENM_Msk    (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01)                          */
+ #define R_BUS_CSRECEN_RCVEN_Pos     (0UL)     /*!< RCVEN (Bit 0)                                         */
+ #define R_BUS_CSRECEN_RCVEN_Msk     (0x1UL)   /*!< RCVEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  CACR0  ========================================================= */
+ #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
+ #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CACR1  ========================================================= */
+ #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
+ #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
+ #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
+ #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
+ #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
+ #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CACR2  ========================================================= */
+ #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
+ #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
+ #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
+ #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
+ #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
+ #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
+ #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
+ #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CAICR  ========================================================= */
+ #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
+ #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
+ #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
+ #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
+ #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
+ #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
+ #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
+ #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
+ #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CASTR  ========================================================= */
+ #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
+ #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
+ #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
+ #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
+ #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
+ #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CAULVR  ========================================================= */
+ #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
+ #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CALLVR  ========================================================= */
+ #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
+ #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CACNTBR  ======================================================== */
+ #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
+ #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CAN0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  MKR  ========================================================== */
+ #define R_CAN0_MKR_SID_Pos              (18UL)         /*!< SID (Bit 18)                                          */
+ #define R_CAN0_MKR_SID_Msk              (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
+ #define R_CAN0_MKR_EID_Pos              (0UL)          /*!< EID (Bit 0)                                           */
+ #define R_CAN0_MKR_EID_Msk              (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
+/* =========================================================  FIDCR  ========================================================= */
+ #define R_CAN0_FIDCR_IDE_Pos            (31UL)         /*!< IDE (Bit 31)                                          */
+ #define R_CAN0_FIDCR_IDE_Msk            (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_FIDCR_RTR_Pos            (30UL)         /*!< RTR (Bit 30)                                          */
+ #define R_CAN0_FIDCR_RTR_Msk            (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_FIDCR_SID_Pos            (18UL)         /*!< SID (Bit 18)                                          */
+ #define R_CAN0_FIDCR_SID_Msk            (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
+ #define R_CAN0_FIDCR_EID_Pos            (0UL)          /*!< EID (Bit 0)                                           */
+ #define R_CAN0_FIDCR_EID_Msk            (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
+/* ========================================================  MKIVLR  ========================================================= */
+ #define R_CAN0_MKIVLR_MB31_Pos          (31UL)         /*!< MB31 (Bit 31)                                         */
+ #define R_CAN0_MKIVLR_MB31_Msk          (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB30_Pos          (30UL)         /*!< MB30 (Bit 30)                                         */
+ #define R_CAN0_MKIVLR_MB30_Msk          (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB29_Pos          (29UL)         /*!< MB29 (Bit 29)                                         */
+ #define R_CAN0_MKIVLR_MB29_Msk          (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB28_Pos          (28UL)         /*!< MB28 (Bit 28)                                         */
+ #define R_CAN0_MKIVLR_MB28_Msk          (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB27_Pos          (27UL)         /*!< MB27 (Bit 27)                                         */
+ #define R_CAN0_MKIVLR_MB27_Msk          (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB26_Pos          (26UL)         /*!< MB26 (Bit 26)                                         */
+ #define R_CAN0_MKIVLR_MB26_Msk          (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB25_Pos          (25UL)         /*!< MB25 (Bit 25)                                         */
+ #define R_CAN0_MKIVLR_MB25_Msk          (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB24_Pos          (24UL)         /*!< MB24 (Bit 24)                                         */
+ #define R_CAN0_MKIVLR_MB24_Msk          (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB23_Pos          (23UL)         /*!< MB23 (Bit 23)                                         */
+ #define R_CAN0_MKIVLR_MB23_Msk          (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB22_Pos          (22UL)         /*!< MB22 (Bit 22)                                         */
+ #define R_CAN0_MKIVLR_MB22_Msk          (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB21_Pos          (21UL)         /*!< MB21 (Bit 21)                                         */
+ #define R_CAN0_MKIVLR_MB21_Msk          (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB20_Pos          (20UL)         /*!< MB20 (Bit 20)                                         */
+ #define R_CAN0_MKIVLR_MB20_Msk          (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB19_Pos          (19UL)         /*!< MB19 (Bit 19)                                         */
+ #define R_CAN0_MKIVLR_MB19_Msk          (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB18_Pos          (18UL)         /*!< MB18 (Bit 18)                                         */
+ #define R_CAN0_MKIVLR_MB18_Msk          (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB17_Pos          (17UL)         /*!< MB17 (Bit 17)                                         */
+ #define R_CAN0_MKIVLR_MB17_Msk          (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB16_Pos          (16UL)         /*!< MB16 (Bit 16)                                         */
+ #define R_CAN0_MKIVLR_MB16_Msk          (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB15_Pos          (15UL)         /*!< MB15 (Bit 15)                                         */
+ #define R_CAN0_MKIVLR_MB15_Msk          (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB14_Pos          (14UL)         /*!< MB14 (Bit 14)                                         */
+ #define R_CAN0_MKIVLR_MB14_Msk          (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB13_Pos          (13UL)         /*!< MB13 (Bit 13)                                         */
+ #define R_CAN0_MKIVLR_MB13_Msk          (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB12_Pos          (12UL)         /*!< MB12 (Bit 12)                                         */
+ #define R_CAN0_MKIVLR_MB12_Msk          (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB11_Pos          (11UL)         /*!< MB11 (Bit 11)                                         */
+ #define R_CAN0_MKIVLR_MB11_Msk          (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB10_Pos          (10UL)         /*!< MB10 (Bit 10)                                         */
+ #define R_CAN0_MKIVLR_MB10_Msk          (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MKIVLR_MB9_Pos           (9UL)          /*!< MB9 (Bit 9)                                           */
+ #define R_CAN0_MKIVLR_MB9_Msk           (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB8_Pos           (8UL)          /*!< MB8 (Bit 8)                                           */
+ #define R_CAN0_MKIVLR_MB8_Msk           (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB7_Pos           (7UL)          /*!< MB7 (Bit 7)                                           */
+ #define R_CAN0_MKIVLR_MB7_Msk           (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB6_Pos           (6UL)          /*!< MB6 (Bit 6)                                           */
+ #define R_CAN0_MKIVLR_MB6_Msk           (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB5_Pos           (5UL)          /*!< MB5 (Bit 5)                                           */
+ #define R_CAN0_MKIVLR_MB5_Msk           (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB4_Pos           (4UL)          /*!< MB4 (Bit 4)                                           */
+ #define R_CAN0_MKIVLR_MB4_Msk           (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB3_Pos           (3UL)          /*!< MB3 (Bit 3)                                           */
+ #define R_CAN0_MKIVLR_MB3_Msk           (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB2_Pos           (2UL)          /*!< MB2 (Bit 2)                                           */
+ #define R_CAN0_MKIVLR_MB2_Msk           (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB1_Pos           (1UL)          /*!< MB1 (Bit 1)                                           */
+ #define R_CAN0_MKIVLR_MB1_Msk           (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MKIVLR_MB0_Pos           (0UL)          /*!< MB0 (Bit 0)                                           */
+ #define R_CAN0_MKIVLR_MB0_Msk           (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
+/* =========================================================  MIER  ========================================================== */
+ #define R_CAN0_MIER_MB31_Pos            (31UL)         /*!< MB31 (Bit 31)                                         */
+ #define R_CAN0_MIER_MB31_Msk            (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB30_Pos            (30UL)         /*!< MB30 (Bit 30)                                         */
+ #define R_CAN0_MIER_MB30_Msk            (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB29_Pos            (29UL)         /*!< MB29 (Bit 29)                                         */
+ #define R_CAN0_MIER_MB29_Msk            (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB28_Pos            (28UL)         /*!< MB28 (Bit 28)                                         */
+ #define R_CAN0_MIER_MB28_Msk            (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB27_Pos            (27UL)         /*!< MB27 (Bit 27)                                         */
+ #define R_CAN0_MIER_MB27_Msk            (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB26_Pos            (26UL)         /*!< MB26 (Bit 26)                                         */
+ #define R_CAN0_MIER_MB26_Msk            (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB25_Pos            (25UL)         /*!< MB25 (Bit 25)                                         */
+ #define R_CAN0_MIER_MB25_Msk            (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB24_Pos            (24UL)         /*!< MB24 (Bit 24)                                         */
+ #define R_CAN0_MIER_MB24_Msk            (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB23_Pos            (23UL)         /*!< MB23 (Bit 23)                                         */
+ #define R_CAN0_MIER_MB23_Msk            (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB22_Pos            (22UL)         /*!< MB22 (Bit 22)                                         */
+ #define R_CAN0_MIER_MB22_Msk            (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB21_Pos            (21UL)         /*!< MB21 (Bit 21)                                         */
+ #define R_CAN0_MIER_MB21_Msk            (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB20_Pos            (20UL)         /*!< MB20 (Bit 20)                                         */
+ #define R_CAN0_MIER_MB20_Msk            (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB19_Pos            (19UL)         /*!< MB19 (Bit 19)                                         */
+ #define R_CAN0_MIER_MB19_Msk            (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB18_Pos            (18UL)         /*!< MB18 (Bit 18)                                         */
+ #define R_CAN0_MIER_MB18_Msk            (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB17_Pos            (17UL)         /*!< MB17 (Bit 17)                                         */
+ #define R_CAN0_MIER_MB17_Msk            (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB16_Pos            (16UL)         /*!< MB16 (Bit 16)                                         */
+ #define R_CAN0_MIER_MB16_Msk            (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB15_Pos            (15UL)         /*!< MB15 (Bit 15)                                         */
+ #define R_CAN0_MIER_MB15_Msk            (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB14_Pos            (14UL)         /*!< MB14 (Bit 14)                                         */
+ #define R_CAN0_MIER_MB14_Msk            (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB13_Pos            (13UL)         /*!< MB13 (Bit 13)                                         */
+ #define R_CAN0_MIER_MB13_Msk            (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB12_Pos            (12UL)         /*!< MB12 (Bit 12)                                         */
+ #define R_CAN0_MIER_MB12_Msk            (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB11_Pos            (11UL)         /*!< MB11 (Bit 11)                                         */
+ #define R_CAN0_MIER_MB11_Msk            (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB10_Pos            (10UL)         /*!< MB10 (Bit 10)                                         */
+ #define R_CAN0_MIER_MB10_Msk            (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_MB9_Pos             (9UL)          /*!< MB9 (Bit 9)                                           */
+ #define R_CAN0_MIER_MB9_Msk             (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB8_Pos             (8UL)          /*!< MB8 (Bit 8)                                           */
+ #define R_CAN0_MIER_MB8_Msk             (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB7_Pos             (7UL)          /*!< MB7 (Bit 7)                                           */
+ #define R_CAN0_MIER_MB7_Msk             (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB6_Pos             (6UL)          /*!< MB6 (Bit 6)                                           */
+ #define R_CAN0_MIER_MB6_Msk             (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB5_Pos             (5UL)          /*!< MB5 (Bit 5)                                           */
+ #define R_CAN0_MIER_MB5_Msk             (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB4_Pos             (4UL)          /*!< MB4 (Bit 4)                                           */
+ #define R_CAN0_MIER_MB4_Msk             (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB3_Pos             (3UL)          /*!< MB3 (Bit 3)                                           */
+ #define R_CAN0_MIER_MB3_Msk             (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB2_Pos             (2UL)          /*!< MB2 (Bit 2)                                           */
+ #define R_CAN0_MIER_MB2_Msk             (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB1_Pos             (1UL)          /*!< MB1 (Bit 1)                                           */
+ #define R_CAN0_MIER_MB1_Msk             (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_MB0_Pos             (0UL)          /*!< MB0 (Bit 0)                                           */
+ #define R_CAN0_MIER_MB0_Msk             (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
+/* =======================================================  MIER_FIFO  ======================================================= */
+ #define R_CAN0_MIER_FIFO_MB29_Pos       (29UL)         /*!< MB29 (Bit 29)                                         */
+ #define R_CAN0_MIER_FIFO_MB29_Msk       (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB28_Pos       (28UL)         /*!< MB28 (Bit 28)                                         */
+ #define R_CAN0_MIER_FIFO_MB28_Msk       (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB25_Pos       (25UL)         /*!< MB25 (Bit 25)                                         */
+ #define R_CAN0_MIER_FIFO_MB25_Msk       (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB24_Pos       (24UL)         /*!< MB24 (Bit 24)                                         */
+ #define R_CAN0_MIER_FIFO_MB24_Msk       (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB23_Pos       (23UL)         /*!< MB23 (Bit 23)                                         */
+ #define R_CAN0_MIER_FIFO_MB23_Msk       (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB22_Pos       (22UL)         /*!< MB22 (Bit 22)                                         */
+ #define R_CAN0_MIER_FIFO_MB22_Msk       (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB21_Pos       (21UL)         /*!< MB21 (Bit 21)                                         */
+ #define R_CAN0_MIER_FIFO_MB21_Msk       (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB20_Pos       (20UL)         /*!< MB20 (Bit 20)                                         */
+ #define R_CAN0_MIER_FIFO_MB20_Msk       (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB19_Pos       (19UL)         /*!< MB19 (Bit 19)                                         */
+ #define R_CAN0_MIER_FIFO_MB19_Msk       (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB18_Pos       (18UL)         /*!< MB18 (Bit 18)                                         */
+ #define R_CAN0_MIER_FIFO_MB18_Msk       (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB17_Pos       (17UL)         /*!< MB17 (Bit 17)                                         */
+ #define R_CAN0_MIER_FIFO_MB17_Msk       (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB16_Pos       (16UL)         /*!< MB16 (Bit 16)                                         */
+ #define R_CAN0_MIER_FIFO_MB16_Msk       (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB15_Pos       (15UL)         /*!< MB15 (Bit 15)                                         */
+ #define R_CAN0_MIER_FIFO_MB15_Msk       (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB14_Pos       (14UL)         /*!< MB14 (Bit 14)                                         */
+ #define R_CAN0_MIER_FIFO_MB14_Msk       (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB13_Pos       (13UL)         /*!< MB13 (Bit 13)                                         */
+ #define R_CAN0_MIER_FIFO_MB13_Msk       (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB12_Pos       (12UL)         /*!< MB12 (Bit 12)                                         */
+ #define R_CAN0_MIER_FIFO_MB12_Msk       (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB11_Pos       (11UL)         /*!< MB11 (Bit 11)                                         */
+ #define R_CAN0_MIER_FIFO_MB11_Msk       (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB10_Pos       (10UL)         /*!< MB10 (Bit 10)                                         */
+ #define R_CAN0_MIER_FIFO_MB10_Msk       (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MIER_FIFO_MB9_Pos        (9UL)          /*!< MB9 (Bit 9)                                           */
+ #define R_CAN0_MIER_FIFO_MB9_Msk        (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB8_Pos        (8UL)          /*!< MB8 (Bit 8)                                           */
+ #define R_CAN0_MIER_FIFO_MB8_Msk        (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB7_Pos        (7UL)          /*!< MB7 (Bit 7)                                           */
+ #define R_CAN0_MIER_FIFO_MB7_Msk        (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB6_Pos        (6UL)          /*!< MB6 (Bit 6)                                           */
+ #define R_CAN0_MIER_FIFO_MB6_Msk        (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB5_Pos        (5UL)          /*!< MB5 (Bit 5)                                           */
+ #define R_CAN0_MIER_FIFO_MB5_Msk        (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB4_Pos        (4UL)          /*!< MB4 (Bit 4)                                           */
+ #define R_CAN0_MIER_FIFO_MB4_Msk        (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB3_Pos        (3UL)          /*!< MB3 (Bit 3)                                           */
+ #define R_CAN0_MIER_FIFO_MB3_Msk        (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB2_Pos        (2UL)          /*!< MB2 (Bit 2)                                           */
+ #define R_CAN0_MIER_FIFO_MB2_Msk        (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB1_Pos        (1UL)          /*!< MB1 (Bit 1)                                           */
+ #define R_CAN0_MIER_FIFO_MB1_Msk        (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_MIER_FIFO_MB0_Pos        (0UL)          /*!< MB0 (Bit 0)                                           */
+ #define R_CAN0_MIER_FIFO_MB0_Msk        (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
+/* ========================================================  MCTL_TX  ======================================================== */
+ #define R_CAN0_MCTL_TX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
+ #define R_CAN0_MCTL_TX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
+ #define R_CAN0_MCTL_TX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
+ #define R_CAN0_MCTL_TX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
+ #define R_CAN0_MCTL_TX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
+ #define R_CAN0_MCTL_TX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
+ #define R_CAN0_MCTL_TX_TRMABT_Pos       (2UL)          /*!< TRMABT (Bit 2)                                        */
+ #define R_CAN0_MCTL_TX_TRMABT_Msk       (0x4UL)        /*!< TRMABT (Bitfield-Mask: 0x01)                          */
+ #define R_CAN0_MCTL_TX_TRMACTIVE_Pos    (1UL)          /*!< TRMACTIVE (Bit 1)                                     */
+ #define R_CAN0_MCTL_TX_TRMACTIVE_Msk    (0x2UL)        /*!< TRMACTIVE (Bitfield-Mask: 0x01)                       */
+ #define R_CAN0_MCTL_TX_SENTDATA_Pos     (0UL)          /*!< SENTDATA (Bit 0)                                      */
+ #define R_CAN0_MCTL_TX_SENTDATA_Msk     (0x1UL)        /*!< SENTDATA (Bitfield-Mask: 0x01)                        */
+/* ========================================================  MCTL_RX  ======================================================== */
+ #define R_CAN0_MCTL_RX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
+ #define R_CAN0_MCTL_RX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
+ #define R_CAN0_MCTL_RX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
+ #define R_CAN0_MCTL_RX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
+ #define R_CAN0_MCTL_RX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
+ #define R_CAN0_MCTL_RX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
+ #define R_CAN0_MCTL_RX_MSGLOST_Pos      (2UL)          /*!< MSGLOST (Bit 2)                                       */
+ #define R_CAN0_MCTL_RX_MSGLOST_Msk      (0x4UL)        /*!< MSGLOST (Bitfield-Mask: 0x01)                         */
+ #define R_CAN0_MCTL_RX_INVALDATA_Pos    (1UL)          /*!< INVALDATA (Bit 1)                                     */
+ #define R_CAN0_MCTL_RX_INVALDATA_Msk    (0x2UL)        /*!< INVALDATA (Bitfield-Mask: 0x01)                       */
+ #define R_CAN0_MCTL_RX_NEWDATA_Pos      (0UL)          /*!< NEWDATA (Bit 0)                                       */
+ #define R_CAN0_MCTL_RX_NEWDATA_Msk      (0x1UL)        /*!< NEWDATA (Bitfield-Mask: 0x01)                         */
+/* =========================================================  CTLR  ========================================================== */
+ #define R_CAN0_CTLR_RBOC_Pos            (13UL)         /*!< RBOC (Bit 13)                                         */
+ #define R_CAN0_CTLR_RBOC_Msk            (0x2000UL)     /*!< RBOC (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_CTLR_BOM_Pos             (11UL)         /*!< BOM (Bit 11)                                          */
+ #define R_CAN0_CTLR_BOM_Msk             (0x1800UL)     /*!< BOM (Bitfield-Mask: 0x03)                             */
+ #define R_CAN0_CTLR_SLPM_Pos            (10UL)         /*!< SLPM (Bit 10)                                         */
+ #define R_CAN0_CTLR_SLPM_Msk            (0x400UL)      /*!< SLPM (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_CTLR_CANM_Pos            (8UL)          /*!< CANM (Bit 8)                                          */
+ #define R_CAN0_CTLR_CANM_Msk            (0x300UL)      /*!< CANM (Bitfield-Mask: 0x03)                            */
+ #define R_CAN0_CTLR_TSPS_Pos            (6UL)          /*!< TSPS (Bit 6)                                          */
+ #define R_CAN0_CTLR_TSPS_Msk            (0xc0UL)       /*!< TSPS (Bitfield-Mask: 0x03)                            */
+ #define R_CAN0_CTLR_TSRC_Pos            (5UL)          /*!< TSRC (Bit 5)                                          */
+ #define R_CAN0_CTLR_TSRC_Msk            (0x20UL)       /*!< TSRC (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_CTLR_TPM_Pos             (4UL)          /*!< TPM (Bit 4)                                           */
+ #define R_CAN0_CTLR_TPM_Msk             (0x10UL)       /*!< TPM (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_CTLR_MLM_Pos             (3UL)          /*!< MLM (Bit 3)                                           */
+ #define R_CAN0_CTLR_MLM_Msk             (0x8UL)        /*!< MLM (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_CTLR_IDFM_Pos            (1UL)          /*!< IDFM (Bit 1)                                          */
+ #define R_CAN0_CTLR_IDFM_Msk            (0x6UL)        /*!< IDFM (Bitfield-Mask: 0x03)                            */
+ #define R_CAN0_CTLR_MBM_Pos             (0UL)          /*!< MBM (Bit 0)                                           */
+ #define R_CAN0_CTLR_MBM_Msk             (0x1UL)        /*!< MBM (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  STR  ========================================================== */
+ #define R_CAN0_STR_RECST_Pos            (14UL)         /*!< RECST (Bit 14)                                        */
+ #define R_CAN0_STR_RECST_Msk            (0x4000UL)     /*!< RECST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_TRMST_Pos            (13UL)         /*!< TRMST (Bit 13)                                        */
+ #define R_CAN0_STR_TRMST_Msk            (0x2000UL)     /*!< TRMST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_BOST_Pos             (12UL)         /*!< BOST (Bit 12)                                         */
+ #define R_CAN0_STR_BOST_Msk             (0x1000UL)     /*!< BOST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_STR_EPST_Pos             (11UL)         /*!< EPST (Bit 11)                                         */
+ #define R_CAN0_STR_EPST_Msk             (0x800UL)      /*!< EPST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_STR_SLPST_Pos            (10UL)         /*!< SLPST (Bit 10)                                        */
+ #define R_CAN0_STR_SLPST_Msk            (0x400UL)      /*!< SLPST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_HLTST_Pos            (9UL)          /*!< HLTST (Bit 9)                                         */
+ #define R_CAN0_STR_HLTST_Msk            (0x200UL)      /*!< HLTST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_RSTST_Pos            (8UL)          /*!< RSTST (Bit 8)                                         */
+ #define R_CAN0_STR_RSTST_Msk            (0x100UL)      /*!< RSTST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_EST_Pos              (7UL)          /*!< EST (Bit 7)                                           */
+ #define R_CAN0_STR_EST_Msk              (0x80UL)       /*!< EST (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_STR_TABST_Pos            (6UL)          /*!< TABST (Bit 6)                                         */
+ #define R_CAN0_STR_TABST_Msk            (0x40UL)       /*!< TABST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_FMLST_Pos            (5UL)          /*!< FMLST (Bit 5)                                         */
+ #define R_CAN0_STR_FMLST_Msk            (0x20UL)       /*!< FMLST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_NMLST_Pos            (4UL)          /*!< NMLST (Bit 4)                                         */
+ #define R_CAN0_STR_NMLST_Msk            (0x10UL)       /*!< NMLST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_STR_TFST_Pos             (3UL)          /*!< TFST (Bit 3)                                          */
+ #define R_CAN0_STR_TFST_Msk             (0x8UL)        /*!< TFST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_STR_RFST_Pos             (2UL)          /*!< RFST (Bit 2)                                          */
+ #define R_CAN0_STR_RFST_Msk             (0x4UL)        /*!< RFST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_STR_SDST_Pos             (1UL)          /*!< SDST (Bit 1)                                          */
+ #define R_CAN0_STR_SDST_Msk             (0x2UL)        /*!< SDST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_STR_NDST_Pos             (0UL)          /*!< NDST (Bit 0)                                          */
+ #define R_CAN0_STR_NDST_Msk             (0x1UL)        /*!< NDST (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  BCR  ========================================================== */
+ #define R_CAN0_BCR_TSEG1_Pos            (28UL)         /*!< TSEG1 (Bit 28)                                        */
+ #define R_CAN0_BCR_TSEG1_Msk            (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
+ #define R_CAN0_BCR_BRP_Pos              (16UL)         /*!< BRP (Bit 16)                                          */
+ #define R_CAN0_BCR_BRP_Msk              (0x3ff0000UL)  /*!< BRP (Bitfield-Mask: 0x3ff)                            */
+ #define R_CAN0_BCR_SJW_Pos              (12UL)         /*!< SJW (Bit 12)                                          */
+ #define R_CAN0_BCR_SJW_Msk              (0x3000UL)     /*!< SJW (Bitfield-Mask: 0x03)                             */
+ #define R_CAN0_BCR_TSEG2_Pos            (8UL)          /*!< TSEG2 (Bit 8)                                         */
+ #define R_CAN0_BCR_TSEG2_Msk            (0x700UL)      /*!< TSEG2 (Bitfield-Mask: 0x07)                           */
+ #define R_CAN0_BCR_CCLKS_Pos            (0UL)          /*!< CCLKS (Bit 0)                                         */
+ #define R_CAN0_BCR_CCLKS_Msk            (0x1UL)        /*!< CCLKS (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RFCR  ========================================================== */
+ #define R_CAN0_RFCR_RFEST_Pos           (7UL)          /*!< RFEST (Bit 7)                                         */
+ #define R_CAN0_RFCR_RFEST_Msk           (0x80UL)       /*!< RFEST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_RFCR_RFWST_Pos           (6UL)          /*!< RFWST (Bit 6)                                         */
+ #define R_CAN0_RFCR_RFWST_Msk           (0x40UL)       /*!< RFWST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_RFCR_RFFST_Pos           (5UL)          /*!< RFFST (Bit 5)                                         */
+ #define R_CAN0_RFCR_RFFST_Msk           (0x20UL)       /*!< RFFST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_RFCR_RFMLF_Pos           (4UL)          /*!< RFMLF (Bit 4)                                         */
+ #define R_CAN0_RFCR_RFMLF_Msk           (0x10UL)       /*!< RFMLF (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_RFCR_RFUST_Pos           (1UL)          /*!< RFUST (Bit 1)                                         */
+ #define R_CAN0_RFCR_RFUST_Msk           (0xeUL)        /*!< RFUST (Bitfield-Mask: 0x07)                           */
+ #define R_CAN0_RFCR_RFE_Pos             (0UL)          /*!< RFE (Bit 0)                                           */
+ #define R_CAN0_RFCR_RFE_Msk             (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RFPCR  ========================================================= */
+ #define R_CAN0_RFPCR_RFPCR_Pos          (0UL)          /*!< RFPCR (Bit 0)                                         */
+ #define R_CAN0_RFPCR_RFPCR_Msk          (0xffUL)       /*!< RFPCR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  TFCR  ========================================================== */
+ #define R_CAN0_TFCR_TFEST_Pos           (7UL)          /*!< TFEST (Bit 7)                                         */
+ #define R_CAN0_TFCR_TFEST_Msk           (0x80UL)       /*!< TFEST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_TFCR_TFFST_Pos           (6UL)          /*!< TFFST (Bit 6)                                         */
+ #define R_CAN0_TFCR_TFFST_Msk           (0x40UL)       /*!< TFFST (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_TFCR_TFUST_Pos           (1UL)          /*!< TFUST (Bit 1)                                         */
+ #define R_CAN0_TFCR_TFUST_Msk           (0xeUL)        /*!< TFUST (Bitfield-Mask: 0x07)                           */
+ #define R_CAN0_TFCR_TFE_Pos             (0UL)          /*!< TFE (Bit 0)                                           */
+ #define R_CAN0_TFCR_TFE_Msk             (0x1UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TFPCR  ========================================================= */
+ #define R_CAN0_TFPCR_TFPCR_Pos          (0UL)          /*!< TFPCR (Bit 0)                                         */
+ #define R_CAN0_TFPCR_TFPCR_Msk          (0xffUL)       /*!< TFPCR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  EIER  ========================================================== */
+ #define R_CAN0_EIER_BLIE_Pos            (7UL)          /*!< BLIE (Bit 7)                                          */
+ #define R_CAN0_EIER_BLIE_Msk            (0x80UL)       /*!< BLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIER_OLIE_Pos            (6UL)          /*!< OLIE (Bit 6)                                          */
+ #define R_CAN0_EIER_OLIE_Msk            (0x40UL)       /*!< OLIE (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIER_ORIE_Pos            (5UL)          /*!< ORIE (Bit 5)                                          */
+ #define R_CAN0_EIER_ORIE_Msk            (0x20UL)       /*!< ORIE (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIER_BORIE_Pos           (4UL)          /*!< BORIE (Bit 4)                                         */
+ #define R_CAN0_EIER_BORIE_Msk           (0x10UL)       /*!< BORIE (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_EIER_BOEIE_Pos           (3UL)          /*!< BOEIE (Bit 3)                                         */
+ #define R_CAN0_EIER_BOEIE_Msk           (0x8UL)        /*!< BOEIE (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_EIER_EPIE_Pos            (2UL)          /*!< EPIE (Bit 2)                                          */
+ #define R_CAN0_EIER_EPIE_Msk            (0x4UL)        /*!< EPIE (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIER_EWIE_Pos            (1UL)          /*!< EWIE (Bit 1)                                          */
+ #define R_CAN0_EIER_EWIE_Msk            (0x2UL)        /*!< EWIE (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIER_BEIE_Pos            (0UL)          /*!< BEIE (Bit 0)                                          */
+ #define R_CAN0_EIER_BEIE_Msk            (0x1UL)        /*!< BEIE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EIFR  ========================================================== */
+ #define R_CAN0_EIFR_BLIF_Pos            (7UL)          /*!< BLIF (Bit 7)                                          */
+ #define R_CAN0_EIFR_BLIF_Msk            (0x80UL)       /*!< BLIF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIFR_OLIF_Pos            (6UL)          /*!< OLIF (Bit 6)                                          */
+ #define R_CAN0_EIFR_OLIF_Msk            (0x40UL)       /*!< OLIF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIFR_ORIF_Pos            (5UL)          /*!< ORIF (Bit 5)                                          */
+ #define R_CAN0_EIFR_ORIF_Msk            (0x20UL)       /*!< ORIF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIFR_BORIF_Pos           (4UL)          /*!< BORIF (Bit 4)                                         */
+ #define R_CAN0_EIFR_BORIF_Msk           (0x10UL)       /*!< BORIF (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_EIFR_BOEIF_Pos           (3UL)          /*!< BOEIF (Bit 3)                                         */
+ #define R_CAN0_EIFR_BOEIF_Msk           (0x8UL)        /*!< BOEIF (Bitfield-Mask: 0x01)                           */
+ #define R_CAN0_EIFR_EPIF_Pos            (2UL)          /*!< EPIF (Bit 2)                                          */
+ #define R_CAN0_EIFR_EPIF_Msk            (0x4UL)        /*!< EPIF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIFR_EWIF_Pos            (1UL)          /*!< EWIF (Bit 1)                                          */
+ #define R_CAN0_EIFR_EWIF_Msk            (0x2UL)        /*!< EWIF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_EIFR_BEIF_Pos            (0UL)          /*!< BEIF (Bit 0)                                          */
+ #define R_CAN0_EIFR_BEIF_Msk            (0x1UL)        /*!< BEIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  RECR  ========================================================== */
+ #define R_CAN0_RECR_RECR_Pos            (0UL)          /*!< RECR (Bit 0)                                          */
+ #define R_CAN0_RECR_RECR_Msk            (0xffUL)       /*!< RECR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  TECR  ========================================================== */
+ #define R_CAN0_TECR_TECR_Pos            (0UL)          /*!< TECR (Bit 0)                                          */
+ #define R_CAN0_TECR_TECR_Msk            (0xffUL)       /*!< TECR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  ECSR  ========================================================== */
+ #define R_CAN0_ECSR_EDPM_Pos            (7UL)          /*!< EDPM (Bit 7)                                          */
+ #define R_CAN0_ECSR_EDPM_Msk            (0x80UL)       /*!< EDPM (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_ECSR_ADEF_Pos            (6UL)          /*!< ADEF (Bit 6)                                          */
+ #define R_CAN0_ECSR_ADEF_Msk            (0x40UL)       /*!< ADEF (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_ECSR_BE0F_Pos            (5UL)          /*!< BE0F (Bit 5)                                          */
+ #define R_CAN0_ECSR_BE0F_Msk            (0x20UL)       /*!< BE0F (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_ECSR_BE1F_Pos            (4UL)          /*!< BE1F (Bit 4)                                          */
+ #define R_CAN0_ECSR_BE1F_Msk            (0x10UL)       /*!< BE1F (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_ECSR_CEF_Pos             (3UL)          /*!< CEF (Bit 3)                                           */
+ #define R_CAN0_ECSR_CEF_Msk             (0x8UL)        /*!< CEF (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_ECSR_AEF_Pos             (2UL)          /*!< AEF (Bit 2)                                           */
+ #define R_CAN0_ECSR_AEF_Msk             (0x4UL)        /*!< AEF (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_ECSR_FEF_Pos             (1UL)          /*!< FEF (Bit 1)                                           */
+ #define R_CAN0_ECSR_FEF_Msk             (0x2UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
+ #define R_CAN0_ECSR_SEF_Pos             (0UL)          /*!< SEF (Bit 0)                                           */
+ #define R_CAN0_ECSR_SEF_Msk             (0x1UL)        /*!< SEF (Bitfield-Mask: 0x01)                             */
+/* =========================================================  CSSR  ========================================================== */
+ #define R_CAN0_CSSR_CSSR_Pos            (0UL)          /*!< CSSR (Bit 0)                                          */
+ #define R_CAN0_CSSR_CSSR_Msk            (0xffUL)       /*!< CSSR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  MSSR  ========================================================== */
+ #define R_CAN0_MSSR_SEST_Pos            (7UL)          /*!< SEST (Bit 7)                                          */
+ #define R_CAN0_MSSR_SEST_Msk            (0x80UL)       /*!< SEST (Bitfield-Mask: 0x01)                            */
+ #define R_CAN0_MSSR_MBNST_Pos           (0UL)          /*!< MBNST (Bit 0)                                         */
+ #define R_CAN0_MSSR_MBNST_Msk           (0x1fUL)       /*!< MBNST (Bitfield-Mask: 0x1f)                           */
+/* =========================================================  MSMR  ========================================================== */
+ #define R_CAN0_MSMR_MBSM_Pos            (0UL)          /*!< MBSM (Bit 0)                                          */
+ #define R_CAN0_MSMR_MBSM_Msk            (0x3UL)        /*!< MBSM (Bitfield-Mask: 0x03)                            */
+/* ==========================================================  TSR  ========================================================== */
+ #define R_CAN0_TSR_TSR_Pos              (0UL)          /*!< TSR (Bit 0)                                           */
+ #define R_CAN0_TSR_TSR_Msk              (0xffffUL)     /*!< TSR (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  AFSR  ========================================================== */
+ #define R_CAN0_AFSR_AFSR_Pos            (0UL)          /*!< AFSR (Bit 0)                                          */
+ #define R_CAN0_AFSR_AFSR_Msk            (0xffffUL)     /*!< AFSR (Bitfield-Mask: 0xffff)                          */
+/* ==========================================================  TCR  ========================================================== */
+ #define R_CAN0_TCR_TSTM_Pos             (1UL)          /*!< TSTM (Bit 1)                                          */
+ #define R_CAN0_TCR_TSTM_Msk             (0x6UL)        /*!< TSTM (Bitfield-Mask: 0x03)                            */
+ #define R_CAN0_TCR_TSTE_Pos             (0UL)          /*!< TSTE (Bit 0)                                          */
+ #define R_CAN0_TCR_TSTE_Msk             (0x1UL)        /*!< TSTE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_CRC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CRCCR0  ========================================================= */
+ #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
+ #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
+ #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
+ #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
+ #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
+/* ========================================================  CRCCR1  ========================================================= */
+ #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
+ #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
+ #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
+ #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
+/* ========================================================  CRCDIR  ========================================================= */
+ #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
+ #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDIR_BY  ======================================================= */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCDOR  ========================================================= */
+ #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
+ #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  CRCDOR_HA  ======================================================= */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
+/* =======================================================  CRCDOR_BY  ======================================================= */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CRCSAR  ========================================================= */
+ #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
+ #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CTSU                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CTSUCR0  ======================================================== */
+ #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos       (7UL)      /*!< CTSUTXVSEL (Bit 7)                                    */
+ #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk       (0x80UL)   /*!< CTSUTXVSEL (Bitfield-Mask: 0x01)                      */
+ #define R_CTSU_CTSUCR0_CTSUINIT_Pos         (4UL)      /*!< CTSUINIT (Bit 4)                                      */
+ #define R_CTSU_CTSUCR0_CTSUINIT_Msk         (0x10UL)   /*!< CTSUINIT (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU_CTSUCR0_CTSUIOC_Pos          (3UL)      /*!< CTSUIOC (Bit 3)                                       */
+ #define R_CTSU_CTSUCR0_CTSUIOC_Msk          (0x8UL)    /*!< CTSUIOC (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU_CTSUCR0_CTSUSNZ_Pos          (2UL)      /*!< CTSUSNZ (Bit 2)                                       */
+ #define R_CTSU_CTSUCR0_CTSUSNZ_Msk          (0x4UL)    /*!< CTSUSNZ (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU_CTSUCR0_CTSUCAP_Pos          (1UL)      /*!< CTSUCAP (Bit 1)                                       */
+ #define R_CTSU_CTSUCR0_CTSUCAP_Msk          (0x2UL)    /*!< CTSUCAP (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU_CTSUCR0_CTSUSTRT_Pos         (0UL)      /*!< CTSUSTRT (Bit 0)                                      */
+ #define R_CTSU_CTSUCR0_CTSUSTRT_Msk         (0x1UL)    /*!< CTSUSTRT (Bitfield-Mask: 0x01)                        */
+/* ========================================================  CTSUCR1  ======================================================== */
+ #define R_CTSU_CTSUCR1_CTSUMD_Pos           (6UL)      /*!< CTSUMD (Bit 6)                                        */
+ #define R_CTSU_CTSUCR1_CTSUMD_Msk           (0xc0UL)   /*!< CTSUMD (Bitfield-Mask: 0x03)                          */
+ #define R_CTSU_CTSUCR1_CTSUCLK_Pos          (4UL)      /*!< CTSUCLK (Bit 4)                                       */
+ #define R_CTSU_CTSUCR1_CTSUCLK_Msk          (0x30UL)   /*!< CTSUCLK (Bitfield-Mask: 0x03)                         */
+ #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos       (3UL)      /*!< CTSUATUNE1 (Bit 3)                                    */
+ #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk       (0x8UL)    /*!< CTSUATUNE1 (Bitfield-Mask: 0x01)                      */
+ #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos       (2UL)      /*!< CTSUATUNE0 (Bit 2)                                    */
+ #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk       (0x4UL)    /*!< CTSUATUNE0 (Bitfield-Mask: 0x01)                      */
+ #define R_CTSU_CTSUCR1_CTSUCSW_Pos          (1UL)      /*!< CTSUCSW (Bit 1)                                       */
+ #define R_CTSU_CTSUCR1_CTSUCSW_Msk          (0x2UL)    /*!< CTSUCSW (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU_CTSUCR1_CTSUPON_Pos          (0UL)      /*!< CTSUPON (Bit 0)                                       */
+ #define R_CTSU_CTSUCR1_CTSUPON_Msk          (0x1UL)    /*!< CTSUPON (Bitfield-Mask: 0x01)                         */
+/* =======================================================  CTSUSDPRS  ======================================================= */
+ #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos       (6UL)      /*!< CTSUSOFF (Bit 6)                                      */
+ #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk       (0x40UL)   /*!< CTSUSOFF (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos     (4UL)      /*!< CTSUPRMODE (Bit 4)                                    */
+ #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk     (0x30UL)   /*!< CTSUPRMODE (Bitfield-Mask: 0x03)                      */
+ #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos    (0UL)      /*!< CTSUPRRATIO (Bit 0)                                   */
+ #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk    (0xfUL)    /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f)                     */
+/* ========================================================  CTSUSST  ======================================================== */
+ #define R_CTSU_CTSUSST_CTSUSST_Pos          (0UL)      /*!< CTSUSST (Bit 0)                                       */
+ #define R_CTSU_CTSUSST_CTSUSST_Msk          (0xffUL)   /*!< CTSUSST (Bitfield-Mask: 0xff)                         */
+/* =======================================================  CTSUMCH0  ======================================================== */
+ #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos        (0UL)      /*!< CTSUMCH0 (Bit 0)                                      */
+ #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk        (0x3fUL)   /*!< CTSUMCH0 (Bitfield-Mask: 0x3f)                        */
+/* =======================================================  CTSUMCH1  ======================================================== */
+ #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos        (0UL)      /*!< CTSUMCH1 (Bit 0)                                      */
+ #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk        (0x3fUL)   /*!< CTSUMCH1 (Bitfield-Mask: 0x3f)                        */
+/* =======================================================  CTSUCHAC  ======================================================== */
+ #define R_CTSU_CTSUCHAC_TS_Pos              (0UL)      /*!< TS (Bit 0)                                            */
+ #define R_CTSU_CTSUCHAC_TS_Msk              (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
+/* =======================================================  CTSUCHTRC  ======================================================= */
+ #define R_CTSU_CTSUCHTRC_TS_Pos             (0UL)      /*!< TS (Bit 0)                                            */
+ #define R_CTSU_CTSUCHTRC_TS_Msk             (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
+/* =======================================================  CTSUDCLKC  ======================================================= */
+ #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos      (4UL)      /*!< CTSUSSCNT (Bit 4)                                     */
+ #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk      (0x30UL)   /*!< CTSUSSCNT (Bitfield-Mask: 0x03)                       */
+ #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos      (0UL)      /*!< CTSUSSMOD (Bit 0)                                     */
+ #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk      (0x3UL)    /*!< CTSUSSMOD (Bitfield-Mask: 0x03)                       */
+/* ========================================================  CTSUST  ========================================================= */
+ #define R_CTSU_CTSUST_CTSUPS_Pos            (7UL)      /*!< CTSUPS (Bit 7)                                        */
+ #define R_CTSU_CTSUST_CTSUPS_Msk            (0x80UL)   /*!< CTSUPS (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU_CTSUST_CTSUROVF_Pos          (6UL)      /*!< CTSUROVF (Bit 6)                                      */
+ #define R_CTSU_CTSUST_CTSUROVF_Msk          (0x40UL)   /*!< CTSUROVF (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU_CTSUST_CTSUSOVF_Pos          (5UL)      /*!< CTSUSOVF (Bit 5)                                      */
+ #define R_CTSU_CTSUST_CTSUSOVF_Msk          (0x20UL)   /*!< CTSUSOVF (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU_CTSUST_CTSUDTSR_Pos          (4UL)      /*!< CTSUDTSR (Bit 4)                                      */
+ #define R_CTSU_CTSUST_CTSUDTSR_Msk          (0x10UL)   /*!< CTSUDTSR (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU_CTSUST_CTSUSTC_Pos           (0UL)      /*!< CTSUSTC (Bit 0)                                       */
+ #define R_CTSU_CTSUST_CTSUSTC_Msk           (0x7UL)    /*!< CTSUSTC (Bitfield-Mask: 0x07)                         */
+/* ========================================================  CTSUSSC  ======================================================== */
+ #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos        (8UL)      /*!< CTSUSSDIV (Bit 8)                                     */
+ #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk        (0xf00UL)  /*!< CTSUSSDIV (Bitfield-Mask: 0x0f)                       */
+/* ========================================================  CTSUSO0  ======================================================== */
+ #define R_CTSU_CTSUSO0_CTSUSNUM_Pos         (10UL)     /*!< CTSUSNUM (Bit 10)                                     */
+ #define R_CTSU_CTSUSO0_CTSUSNUM_Msk         (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f)                        */
+ #define R_CTSU_CTSUSO0_CTSUSO_Pos           (0UL)      /*!< CTSUSO (Bit 0)                                        */
+ #define R_CTSU_CTSUSO0_CTSUSO_Msk           (0x3ffUL)  /*!< CTSUSO (Bitfield-Mask: 0x3ff)                         */
+/* ========================================================  CTSUSO1  ======================================================== */
+ #define R_CTSU_CTSUSO1_CTSUICOG_Pos         (13UL)     /*!< CTSUICOG (Bit 13)                                     */
+ #define R_CTSU_CTSUSO1_CTSUICOG_Msk         (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03)                        */
+ #define R_CTSU_CTSUSO1_CTSUSDPA_Pos         (8UL)      /*!< CTSUSDPA (Bit 8)                                      */
+ #define R_CTSU_CTSUSO1_CTSUSDPA_Msk         (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f)                        */
+ #define R_CTSU_CTSUSO1_CTSURICOA_Pos        (0UL)      /*!< CTSURICOA (Bit 0)                                     */
+ #define R_CTSU_CTSUSO1_CTSURICOA_Msk        (0xffUL)   /*!< CTSURICOA (Bitfield-Mask: 0xff)                       */
+/* ========================================================  CTSUSC  ========================================================= */
+ #define R_CTSU_CTSUSC_CTSUSC_Pos            (0UL)      /*!< CTSUSC (Bit 0)                                        */
+ #define R_CTSU_CTSUSC_CTSUSC_Msk            (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  CTSURC  ========================================================= */
+ #define R_CTSU_CTSURC_CTSURC_Pos            (0UL)      /*!< CTSURC (Bit 0)                                        */
+ #define R_CTSU_CTSURC_CTSURC_Msk            (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  CTSUERRS  ======================================================== */
+ #define R_CTSU_CTSUERRS_CTSUICOMP_Pos       (15UL)     /*!< CTSUICOMP (Bit 15)                                    */
+ #define R_CTSU_CTSUERRS_CTSUICOMP_Msk       (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01)                       */
+
+/* =========================================================================================================================== */
+/* ================                                          R_CTSU2                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CTSUCRA  ======================================================== */
+ #define R_CTSU2_CTSUCRA_STRT_Pos      (0UL)          /*!< STRT (Bit 0)                                          */
+ #define R_CTSU2_CTSUCRA_STRT_Msk      (0x1UL)        /*!< STRT (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUCRA_CAP_Pos       (1UL)          /*!< CAP (Bit 1)                                           */
+ #define R_CTSU2_CTSUCRA_CAP_Msk       (0x2UL)        /*!< CAP (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_SNZ_Pos       (2UL)          /*!< SNZ (Bit 2)                                           */
+ #define R_CTSU2_CTSUCRA_SNZ_Msk       (0x4UL)        /*!< SNZ (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_CFCON_Pos     (3UL)          /*!< CFCON (Bit 3)                                         */
+ #define R_CTSU2_CTSUCRA_CFCON_Msk     (0x8UL)        /*!< CFCON (Bitfield-Mask: 0x01)                           */
+ #define R_CTSU2_CTSUCRA_INIT_Pos      (4UL)          /*!< INIT (Bit 4)                                          */
+ #define R_CTSU2_CTSUCRA_INIT_Msk      (0x10UL)       /*!< INIT (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUCRA_PUMPON_Pos    (5UL)          /*!< PUMPON (Bit 5)                                        */
+ #define R_CTSU2_CTSUCRA_PUMPON_Msk    (0x20UL)       /*!< PUMPON (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_TXVSEL_Pos    (6UL)          /*!< TXVSEL (Bit 6)                                        */
+ #define R_CTSU2_CTSUCRA_TXVSEL_Msk    (0xc0UL)       /*!< TXVSEL (Bitfield-Mask: 0x03)                          */
+ #define R_CTSU2_CTSUCRA_PON_Pos       (8UL)          /*!< PON (Bit 8)                                           */
+ #define R_CTSU2_CTSUCRA_PON_Msk       (0x100UL)      /*!< PON (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_CSW_Pos       (9UL)          /*!< CSW (Bit 9)                                           */
+ #define R_CTSU2_CTSUCRA_CSW_Msk       (0x200UL)      /*!< CSW (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_ATUNE0_Pos    (10UL)         /*!< ATUNE0 (Bit 10)                                       */
+ #define R_CTSU2_CTSUCRA_ATUNE0_Msk    (0x400UL)      /*!< ATUNE0 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_ATUNE1_Pos    (11UL)         /*!< ATUNE1 (Bit 11)                                       */
+ #define R_CTSU2_CTSUCRA_ATUNE1_Msk    (0x800UL)      /*!< ATUNE1 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_CLK_Pos       (12UL)         /*!< CLK (Bit 12)                                          */
+ #define R_CTSU2_CTSUCRA_CLK_Msk       (0x3000UL)     /*!< CLK (Bitfield-Mask: 0x03)                             */
+ #define R_CTSU2_CTSUCRA_MD0_Pos       (14UL)         /*!< MD0 (Bit 14)                                          */
+ #define R_CTSU2_CTSUCRA_MD0_Msk       (0x4000UL)     /*!< MD0 (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_MD1_Pos       (15UL)         /*!< MD1 (Bit 15)                                          */
+ #define R_CTSU2_CTSUCRA_MD1_Msk       (0x8000UL)     /*!< MD1 (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_MD2_Pos       (16UL)         /*!< MD2 (Bit 16)                                          */
+ #define R_CTSU2_CTSUCRA_MD2_Msk       (0x10000UL)    /*!< MD2 (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCRA_ATUNE2_Pos    (17UL)         /*!< ATUNE2 (Bit 17)                                       */
+ #define R_CTSU2_CTSUCRA_ATUNE2_Msk    (0x20000UL)    /*!< ATUNE2 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_LOAD_Pos      (18UL)         /*!< LOAD (Bit 18)                                         */
+ #define R_CTSU2_CTSUCRA_LOAD_Msk      (0xc0000UL)    /*!< LOAD (Bitfield-Mask: 0x03)                            */
+ #define R_CTSU2_CTSUCRA_POSEL_Pos     (20UL)         /*!< POSEL (Bit 20)                                        */
+ #define R_CTSU2_CTSUCRA_POSEL_Msk     (0x300000UL)   /*!< POSEL (Bitfield-Mask: 0x03)                           */
+ #define R_CTSU2_CTSUCRA_SDPSEL_Pos    (22UL)         /*!< SDPSEL (Bit 22)                                       */
+ #define R_CTSU2_CTSUCRA_SDPSEL_Msk    (0x400000UL)   /*!< SDPSEL (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_FCMODE_Pos    (23UL)         /*!< FCMODE (Bit 23)                                       */
+ #define R_CTSU2_CTSUCRA_FCMODE_Msk    (0x800000UL)   /*!< FCMODE (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_STCLK_Pos     (24UL)         /*!< STCLK (Bit 24)                                        */
+ #define R_CTSU2_CTSUCRA_STCLK_Msk     (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f)                           */
+ #define R_CTSU2_CTSUCRA_DCMODE_Pos    (30UL)         /*!< DCMODE (Bit 30)                                       */
+ #define R_CTSU2_CTSUCRA_DCMODE_Msk    (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCRA_DCBACK_Pos    (31UL)         /*!< DCBACK (Bit 31)                                       */
+ #define R_CTSU2_CTSUCRA_DCBACK_Msk    (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01)                          */
+/* =======================================================  CTSUCRAL  ======================================================== */
+/* ========================================================  CTSUCR0  ======================================================== */
+/* ========================================================  CTSUCR1  ======================================================== */
+/* ========================================================  CTSUCR2  ======================================================== */
+/* ========================================================  CTSUCR3  ======================================================== */
+/* ========================================================  CTSUCRB  ======================================================== */
+ #define R_CTSU2_CTSUCRB_PRRATIO_Pos    (0UL)          /*!< PRRATIO (Bit 0)                                       */
+ #define R_CTSU2_CTSUCRB_PRRATIO_Msk    (0xfUL)        /*!< PRRATIO (Bitfield-Mask: 0x0f)                         */
+ #define R_CTSU2_CTSUCRB_PRMODE_Pos     (4UL)          /*!< PRMODE (Bit 4)                                        */
+ #define R_CTSU2_CTSUCRB_PRMODE_Msk     (0x30UL)       /*!< PRMODE (Bitfield-Mask: 0x03)                          */
+ #define R_CTSU2_CTSUCRB_SOFF_Pos       (6UL)          /*!< SOFF (Bit 6)                                          */
+ #define R_CTSU2_CTSUCRB_SOFF_Msk       (0x40UL)       /*!< SOFF (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUCRB_PROFF_Pos      (7UL)          /*!< PROFF (Bit 7)                                         */
+ #define R_CTSU2_CTSUCRB_PROFF_Msk      (0x80UL)       /*!< PROFF (Bitfield-Mask: 0x01)                           */
+ #define R_CTSU2_CTSUCRB_SST_Pos        (8UL)          /*!< SST (Bit 8)                                           */
+ #define R_CTSU2_CTSUCRB_SST_Msk        (0xff00UL)     /*!< SST (Bitfield-Mask: 0xff)                             */
+ #define R_CTSU2_CTSUCRB_SSMOD_Pos      (24UL)         /*!< SSMOD (Bit 24)                                        */
+ #define R_CTSU2_CTSUCRB_SSMOD_Msk      (0x7000000UL)  /*!< SSMOD (Bitfield-Mask: 0x07)                           */
+ #define R_CTSU2_CTSUCRB_SSCNT_Pos      (28UL)         /*!< SSCNT (Bit 28)                                        */
+ #define R_CTSU2_CTSUCRB_SSCNT_Msk      (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03)                           */
+/* =======================================================  CTSUCRBL  ======================================================== */
+/* =======================================================  CTSUSDPRS  ======================================================= */
+/* ========================================================  CTSUSST  ======================================================== */
+/* =======================================================  CTSUCRBH  ======================================================== */
+/* =======================================================  CTSUDCLKC  ======================================================= */
+/* ========================================================  CTSUMCH  ======================================================== */
+ #define R_CTSU2_CTSUMCH_MCH0_Pos    (0UL)       /*!< MCH0 (Bit 0)                                          */
+ #define R_CTSU2_CTSUMCH_MCH0_Msk    (0x3fUL)    /*!< MCH0 (Bitfield-Mask: 0x3f)                            */
+ #define R_CTSU2_CTSUMCH_MCH1_Pos    (8UL)       /*!< MCH1 (Bit 8)                                          */
+ #define R_CTSU2_CTSUMCH_MCH1_Msk    (0x3f00UL)  /*!< MCH1 (Bitfield-Mask: 0x3f)                            */
+ #define R_CTSU2_CTSUMCH_MCA0_Pos    (16UL)      /*!< MCA0 (Bit 16)                                         */
+ #define R_CTSU2_CTSUMCH_MCA0_Msk    (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUMCH_MCA1_Pos    (17UL)      /*!< MCA1 (Bit 17)                                         */
+ #define R_CTSU2_CTSUMCH_MCA1_Msk    (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUMCH_MCA2_Pos    (18UL)      /*!< MCA2 (Bit 18)                                         */
+ #define R_CTSU2_CTSUMCH_MCA2_Msk    (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUMCH_MCA3_Pos    (19UL)      /*!< MCA3 (Bit 19)                                         */
+ #define R_CTSU2_CTSUMCH_MCA3_Msk    (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  CTSUMCHL  ======================================================== */
+/* =======================================================  CTSUMCH0  ======================================================== */
+/* =======================================================  CTSUMCH1  ======================================================== */
+/* =======================================================  CTSUMCHH  ======================================================== */
+/* =======================================================  CTSUMFAF  ======================================================== */
+/* =======================================================  CTSUCHACA  ======================================================= */
+ #define R_CTSU2_CTSUCHACA_CHAC00_Pos    (0UL)          /*!< CHAC00 (Bit 0)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC00_Msk    (0x1UL)        /*!< CHAC00 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC02_Pos    (2UL)          /*!< CHAC02 (Bit 2)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC02_Msk    (0x4UL)        /*!< CHAC02 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC04_Pos    (4UL)          /*!< CHAC04 (Bit 4)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC04_Msk    (0x10UL)       /*!< CHAC04 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC05_Pos    (5UL)          /*!< CHAC05 (Bit 5)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC05_Msk    (0x20UL)       /*!< CHAC05 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC06_Pos    (6UL)          /*!< CHAC06 (Bit 6)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC06_Msk    (0x40UL)       /*!< CHAC06 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC07_Pos    (7UL)          /*!< CHAC07 (Bit 7)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC07_Msk    (0x80UL)       /*!< CHAC07 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC08_Pos    (8UL)          /*!< CHAC08 (Bit 8)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC08_Msk    (0x100UL)      /*!< CHAC08 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC09_Pos    (9UL)          /*!< CHAC09 (Bit 9)                                        */
+ #define R_CTSU2_CTSUCHACA_CHAC09_Msk    (0x200UL)      /*!< CHAC09 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC10_Pos    (10UL)         /*!< CHAC10 (Bit 10)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC10_Msk    (0x400UL)      /*!< CHAC10 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC11_Pos    (11UL)         /*!< CHAC11 (Bit 11)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC11_Msk    (0x800UL)      /*!< CHAC11 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC12_Pos    (12UL)         /*!< CHAC12 (Bit 12)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC12_Msk    (0x1000UL)     /*!< CHAC12 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC13_Pos    (13UL)         /*!< CHAC13 (Bit 13)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC13_Msk    (0x2000UL)     /*!< CHAC13 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC14_Pos    (14UL)         /*!< CHAC14 (Bit 14)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC14_Msk    (0x4000UL)     /*!< CHAC14 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC15_Pos    (15UL)         /*!< CHAC15 (Bit 15)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC15_Msk    (0x8000UL)     /*!< CHAC15 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC16_Pos    (16UL)         /*!< CHAC16 (Bit 16)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC16_Msk    (0x10000UL)    /*!< CHAC16 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC17_Pos    (17UL)         /*!< CHAC17 (Bit 17)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC17_Msk    (0x20000UL)    /*!< CHAC17 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC18_Pos    (18UL)         /*!< CHAC18 (Bit 18)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC18_Msk    (0x40000UL)    /*!< CHAC18 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC21_Pos    (21UL)         /*!< CHAC21 (Bit 21)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC21_Msk    (0x200000UL)   /*!< CHAC21 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC22_Pos    (22UL)         /*!< CHAC22 (Bit 22)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC22_Msk    (0x400000UL)   /*!< CHAC22 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC23_Pos    (23UL)         /*!< CHAC23 (Bit 23)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC23_Msk    (0x800000UL)   /*!< CHAC23 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC24_Pos    (24UL)         /*!< CHAC24 (Bit 24)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC24_Msk    (0x1000000UL)  /*!< CHAC24 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC25_Pos    (25UL)         /*!< CHAC25 (Bit 25)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC25_Msk    (0x2000000UL)  /*!< CHAC25 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC26_Pos    (26UL)         /*!< CHAC26 (Bit 26)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC26_Msk    (0x4000000UL)  /*!< CHAC26 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC27_Pos    (27UL)         /*!< CHAC27 (Bit 27)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC27_Msk    (0x8000000UL)  /*!< CHAC27 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC28_Pos    (28UL)         /*!< CHAC28 (Bit 28)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC28_Msk    (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC29_Pos    (29UL)         /*!< CHAC29 (Bit 29)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC29_Msk    (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC30_Pos    (30UL)         /*!< CHAC30 (Bit 30)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC30_Msk    (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACA_CHAC31_Pos    (31UL)         /*!< CHAC31 (Bit 31)                                       */
+ #define R_CTSU2_CTSUCHACA_CHAC31_Msk    (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CTSUCHACAL  ======================================================= */
+/* =======================================================  CTSUCHAC0  ======================================================= */
+/* =======================================================  CTSUCHAC1  ======================================================= */
+/* ======================================================  CTSUCHACAH  ======================================================= */
+/* =======================================================  CTSUCHAC2  ======================================================= */
+/* =======================================================  CTSUCHAC3  ======================================================= */
+/* =======================================================  CTSUCHACB  ======================================================= */
+ #define R_CTSU2_CTSUCHACB_CHAC32_Pos      (0UL)          /*!< CHAC32 (Bit 0)                                        */
+ #define R_CTSU2_CTSUCHACB_CHAC32_Msk      (0x1UL)        /*!< CHAC32 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACB_CHAC33_Pos      (1UL)          /*!< CHAC33 (Bit 1)                                        */
+ #define R_CTSU2_CTSUCHACB_CHAC33_Msk      (0x2UL)        /*!< CHAC33 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACB_CHAC34_Pos      (2UL)          /*!< CHAC34 (Bit 2)                                        */
+ #define R_CTSU2_CTSUCHACB_CHAC34_Msk      (0x4UL)        /*!< CHAC34 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCHACB_CHAC35_Pos      (3UL)          /*!< CHAC35 (Bit 3)                                        */
+ #define R_CTSU2_CTSUCHACB_CHAC35_Msk      (0x8UL)        /*!< CHAC35 (Bitfield-Mask: 0x01)                          */
+/* ======================================================  CTSUCHACBL  ======================================================= */
+/* =======================================================  CTSUCHAC4  ======================================================= */
+/* ======================================================  CTSUCHTRCA  ======================================================= */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos      (0UL)          /*!< CHTRC (Bit 0)                                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk      (0x1UL)        /*!< CHTRC (Bitfield-Mask: 0x01)                           */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos    (2UL)          /*!< CHTRC02 (Bit 2)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk    (0x4UL)        /*!< CHTRC02 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos    (4UL)          /*!< CHTRC04 (Bit 4)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk    (0x10UL)       /*!< CHTRC04 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos    (5UL)          /*!< CHTRC05 (Bit 5)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk    (0x20UL)       /*!< CHTRC05 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos    (6UL)          /*!< CHTRC06 (Bit 6)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk    (0x40UL)       /*!< CHTRC06 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos    (7UL)          /*!< CHTRC07 (Bit 7)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk    (0x80UL)       /*!< CHTRC07 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos    (8UL)          /*!< CHTRC08 (Bit 8)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk    (0x100UL)      /*!< CHTRC08 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos    (9UL)          /*!< CHTRC09 (Bit 9)                                       */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk    (0x200UL)      /*!< CHTRC09 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos    (10UL)         /*!< CHTRC10 (Bit 10)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk    (0x400UL)      /*!< CHTRC10 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos    (11UL)         /*!< CHTRC11 (Bit 11)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk    (0x800UL)      /*!< CHTRC11 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos    (12UL)         /*!< CHTRC12 (Bit 12)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk    (0x1000UL)     /*!< CHTRC12 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos    (13UL)         /*!< CHTRC13 (Bit 13)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk    (0x2000UL)     /*!< CHTRC13 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos    (14UL)         /*!< CHTRC14 (Bit 14)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk    (0x4000UL)     /*!< CHTRC14 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos    (15UL)         /*!< CHTRC15 (Bit 15)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk    (0x8000UL)     /*!< CHTRC15 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos    (16UL)         /*!< CHTRC16 (Bit 16)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk    (0x10000UL)    /*!< CHTRC16 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos    (17UL)         /*!< CHTRC17 (Bit 17)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk    (0x20000UL)    /*!< CHTRC17 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos    (18UL)         /*!< CHTRC18 (Bit 18)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk    (0x40000UL)    /*!< CHTRC18 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos    (21UL)         /*!< CHTRC21 (Bit 21)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk    (0x200000UL)   /*!< CHTRC21 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos    (22UL)         /*!< CHTRC22 (Bit 22)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk    (0x400000UL)   /*!< CHTRC22 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos    (23UL)         /*!< CHTRC23 (Bit 23)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk    (0x800000UL)   /*!< CHTRC23 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos    (24UL)         /*!< CHTRC24 (Bit 24)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk    (0x1000000UL)  /*!< CHTRC24 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos    (25UL)         /*!< CHTRC25 (Bit 25)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk    (0x2000000UL)  /*!< CHTRC25 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos    (26UL)         /*!< CHTRC26 (Bit 26)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk    (0x4000000UL)  /*!< CHTRC26 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos    (27UL)         /*!< CHTRC27 (Bit 27)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk    (0x8000000UL)  /*!< CHTRC27 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos    (28UL)         /*!< CHTRC28 (Bit 28)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk    (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos    (29UL)         /*!< CHTRC29 (Bit 29)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk    (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos    (30UL)         /*!< CHTRC30 (Bit 30)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk    (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos    (31UL)         /*!< CHTRC31 (Bit 31)                                      */
+ #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk    (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CTSUCHTRCAL  ====================================================== */
+/* ======================================================  CTSUCHTRC0  ======================================================= */
+/* ======================================================  CTSUCHTRC1  ======================================================= */
+/* ======================================================  CTSUCHTRCAH  ====================================================== */
+/* ======================================================  CTSUCHTRC2  ======================================================= */
+/* ======================================================  CTSUCHTRC3  ======================================================= */
+/* ======================================================  CTSUCHTRCB  ======================================================= */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos    (0UL)        /*!< CHTRC32 (Bit 0)                                       */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk    (0x1UL)      /*!< CHTRC32 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos    (1UL)        /*!< CHTRC33 (Bit 1)                                       */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk    (0x2UL)      /*!< CHTRC33 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos    (2UL)        /*!< CHTRC34 (Bit 2)                                       */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk    (0x4UL)      /*!< CHTRC34 (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos    (3UL)        /*!< CHTRC35 (Bit 3)                                       */
+ #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk    (0x8UL)      /*!< CHTRC35 (Bitfield-Mask: 0x01)                         */
+/* ======================================================  CTSUCHTRCBL  ====================================================== */
+/* ======================================================  CTSUCHTRC4  ======================================================= */
+/* ========================================================  CTSUSR  ========================================================= */
+ #define R_CTSU2_CTSUSR_MFC_Pos            (0UL)        /*!< MFC (Bit 0)                                           */
+ #define R_CTSU2_CTSUSR_MFC_Msk            (0x3UL)      /*!< MFC (Bitfield-Mask: 0x03)                             */
+ #define R_CTSU2_CTSUSR_ICOMPRST_Pos       (5UL)        /*!< ICOMPRST (Bit 5)                                      */
+ #define R_CTSU2_CTSUSR_ICOMPRST_Msk       (0x20UL)     /*!< ICOMPRST (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU2_CTSUSR_ICOMP1_Pos         (6UL)        /*!< ICOMP1 (Bit 6)                                        */
+ #define R_CTSU2_CTSUSR_ICOMP1_Msk         (0x40UL)     /*!< ICOMP1 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUSR_ICOMP0_Pos         (7UL)        /*!< ICOMP0 (Bit 7)                                        */
+ #define R_CTSU2_CTSUSR_ICOMP0_Msk         (0x80UL)     /*!< ICOMP0 (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUSR_STC_Pos            (8UL)        /*!< STC (Bit 8)                                           */
+ #define R_CTSU2_CTSUSR_STC_Msk            (0x700UL)    /*!< STC (Bitfield-Mask: 0x07)                             */
+ #define R_CTSU2_CTSUSR_DTSR_Pos           (12UL)       /*!< DTSR (Bit 12)                                         */
+ #define R_CTSU2_CTSUSR_DTSR_Msk           (0x1000UL)   /*!< DTSR (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUSR_SENSOVF_Pos        (13UL)       /*!< SENSOVF (Bit 13)                                      */
+ #define R_CTSU2_CTSUSR_SENSOVF_Msk        (0x2000UL)   /*!< SENSOVF (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUSR_PS_Pos             (15UL)       /*!< PS (Bit 15)                                           */
+ #define R_CTSU2_CTSUSR_PS_Msk             (0x8000UL)   /*!< PS (Bitfield-Mask: 0x01)                              */
+ #define R_CTSU2_CTSUSR_CFCRDCH_Pos        (16UL)       /*!< CFCRDCH (Bit 16)                                      */
+ #define R_CTSU2_CTSUSR_CFCRDCH_Msk        (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f)                         */
+/* ========================================================  CTSUSRL  ======================================================== */
+/* ========================================================  CTSUSR0  ======================================================== */
+/* ========================================================  CTSUST  ========================================================= */
+/* ========================================================  CTSUSRH  ======================================================== */
+/* ========================================================  CTSUSR2  ======================================================== */
+/* ========================================================  CTSUSO  ========================================================= */
+ #define R_CTSU2_CTSUSO_SO_Pos             (0UL)          /*!< SO (Bit 0)                                            */
+ #define R_CTSU2_CTSUSO_SO_Msk             (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
+ #define R_CTSU2_CTSUSO_SNUM_Pos           (10UL)         /*!< SNUM (Bit 10)                                         */
+ #define R_CTSU2_CTSUSO_SNUM_Msk           (0x3fc00UL)    /*!< SNUM (Bitfield-Mask: 0xff)                            */
+ #define R_CTSU2_CTSUSO_SSDIV_Pos          (20UL)         /*!< SSDIV (Bit 20)                                        */
+ #define R_CTSU2_CTSUSO_SSDIV_Msk          (0xf00000UL)   /*!< SSDIV (Bitfield-Mask: 0x0f)                           */
+ #define R_CTSU2_CTSUSO_SDPA_Pos           (24UL)         /*!< SDPA (Bit 24)                                         */
+ #define R_CTSU2_CTSUSO_SDPA_Msk           (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff)                            */
+/* ========================================================  CTSUSO0  ======================================================== */
+/* ========================================================  CTSUSO1  ======================================================== */
+/* =======================================================  CTSUSCNT  ======================================================== */
+ #define R_CTSU2_CTSUSCNT_SENSCNT_Pos      (0UL)          /*!< SENSCNT (Bit 0)                                       */
+ #define R_CTSU2_CTSUSCNT_SENSCNT_Msk      (0xffffUL)     /*!< SENSCNT (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  CTSUSC  ========================================================= */
+/* =======================================================  CTSUCALIB  ======================================================= */
+ #define R_CTSU2_CTSUCALIB_TSOD_Pos        (2UL)          /*!< TSOD (Bit 2)                                          */
+ #define R_CTSU2_CTSUCALIB_TSOD_Msk        (0x4UL)        /*!< TSOD (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUCALIB_DRV_Pos         (3UL)          /*!< DRV (Bit 3)                                           */
+ #define R_CTSU2_CTSUCALIB_DRV_Msk         (0x8UL)        /*!< DRV (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos     (6UL)          /*!< SUCLKEN (Bit 6)                                       */
+ #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk     (0x40UL)       /*!< SUCLKEN (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCALIB_TSOC_Pos        (7UL)          /*!< TSOC (Bit 7)                                          */
+ #define R_CTSU2_CTSUCALIB_TSOC_Msk        (0x80UL)       /*!< TSOC (Bitfield-Mask: 0x01)                            */
+ #define R_CTSU2_CTSUCALIB_IOC_Pos         (9UL)          /*!< IOC (Bit 9)                                           */
+ #define R_CTSU2_CTSUCALIB_IOC_Msk         (0x200UL)      /*!< IOC (Bitfield-Mask: 0x01)                             */
+ #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos     (10UL)         /*!< CFCRDMD (Bit 10)                                      */
+ #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk     (0x400UL)      /*!< CFCRDMD (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCALIB_DCOFF_Pos       (11UL)         /*!< DCOFF (Bit 11)                                        */
+ #define R_CTSU2_CTSUCALIB_DCOFF_Msk       (0x800UL)      /*!< DCOFF (Bitfield-Mask: 0x01)                           */
+ #define R_CTSU2_CTSUCALIB_CFCMODE_Pos     (22UL)         /*!< CFCMODE (Bit 22)                                      */
+ #define R_CTSU2_CTSUCALIB_CFCMODE_Msk     (0x400000UL)   /*!< CFCMODE (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCALIB_DACCARRY_Pos    (25UL)         /*!< DACCARRY (Bit 25)                                     */
+ #define R_CTSU2_CTSUCALIB_DACCARRY_Msk    (0x2000000UL)  /*!< DACCARRY (Bitfield-Mask: 0x01)                        */
+ #define R_CTSU2_CTSUCALIB_SUCARRY_Pos     (27UL)         /*!< SUCARRY (Bit 27)                                      */
+ #define R_CTSU2_CTSUCALIB_SUCARRY_Msk     (0x8000000UL)  /*!< SUCARRY (Bitfield-Mask: 0x01)                         */
+ #define R_CTSU2_CTSUCALIB_DACCLK_Pos      (28UL)         /*!< DACCLK (Bit 28)                                       */
+ #define R_CTSU2_CTSUCALIB_DACCLK_Msk      (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCALIB_CCOCLK_Pos      (29UL)         /*!< CCOCLK (Bit 29)                                       */
+ #define R_CTSU2_CTSUCALIB_CCOCLK_Msk      (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01)                          */
+ #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos    (30UL)         /*!< CCOCALIB (Bit 30)                                     */
+ #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk    (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01)                        */
+/* =======================================================  CTSUDBGR0  ======================================================= */
+/* =======================================================  CTSUDBGR1  ======================================================= */
+/* ======================================================  CTSUSUCLKA  ======================================================= */
+/* ======================================================  CTSUSUCLK0  ======================================================= */
+/* ======================================================  CTSUSUCLK1  ======================================================= */
+/* ======================================================  CTSUSUCLKB  ======================================================= */
+ #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos      (0UL)          /*!< SUADJ2 (Bit 0)                                        */
+ #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk      (0xffUL)       /*!< SUADJ2 (Bitfield-Mask: 0xff)                          */
+ #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos    (8UL)          /*!< SUMULTI2 (Bit 8)                                      */
+ #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk    (0xff00UL)     /*!< SUMULTI2 (Bitfield-Mask: 0xff)                        */
+ #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos      (16UL)         /*!< SUADJ3 (Bit 16)                                       */
+ #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk      (0xff0000UL)   /*!< SUADJ3 (Bitfield-Mask: 0xff)                          */
+ #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos    (24UL)         /*!< SUMULTI3 (Bit 24)                                     */
+ #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk    (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff)                        */
+/* ======================================================  CTSUSUCLK2  ======================================================= */
+/* ======================================================  CTSUSUCLK3  ======================================================= */
+/* ======================================================  CTSUCFCCNT  ======================================================= */
+ #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos      (0UL)          /*!< CFCCNT (Bit 0)                                        */
+ #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk      (0xffffUL)     /*!< CFCCNT (Bitfield-Mask: 0xffff)                        */
+/* ======================================================  CTSUCFCCNTL  ====================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DAC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DACR  ========================================================== */
+ #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
+ #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
+ #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
+ #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  DADR  ========================================================== */
+ #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
+ #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  DADPR  ========================================================= */
+ #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
+ #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAADSCR  ======================================================== */
+ #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
+ #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DAVREFCR  ======================================================== */
+ #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
+ #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
+/* =========================================================  DAPC  ========================================================== */
+ #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
+ #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAAMPCR  ======================================================== */
+ #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
+ #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DAASWCR  ======================================================== */
+ #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
+ #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
+ #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
+ #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DAADUSR  ======================================================== */
+ #define R_DAC_DAADUSR_AMADSEL1_Pos    (6UL)      /*!< AMADSEL1 (Bit 6)                                      */
+ #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x40UL)   /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DAC8                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  DAM  ========================================================== */
+ #define R_DAC8_DAM_DACE1_Pos           (5UL)    /*!< DACE1 (Bit 5)                                         */
+ #define R_DAC8_DAM_DACE1_Msk           (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01)                           */
+ #define R_DAC8_DAM_DACE0_Pos           (4UL)    /*!< DACE0 (Bit 4)                                         */
+ #define R_DAC8_DAM_DACE0_Msk           (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01)                           */
+ #define R_DAC8_DAM_DAMD1_Pos           (1UL)    /*!< DAMD1 (Bit 1)                                         */
+ #define R_DAC8_DAM_DAMD1_Msk           (0x2UL)  /*!< DAMD1 (Bitfield-Mask: 0x01)                           */
+ #define R_DAC8_DAM_DAMD0_Pos           (0UL)    /*!< DAMD0 (Bit 0)                                         */
+ #define R_DAC8_DAM_DAMD0_Msk           (0x1UL)  /*!< DAMD0 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DACS  ========================================================== */
+ #define R_DAC8_DACS_DACS_Pos           (0UL)    /*!< DACS (Bit 0)                                          */
+ #define R_DAC8_DACS_DACS_Msk           (0xffUL) /*!< DACS (Bitfield-Mask: 0xff)                            */
+/* =======================================================  DACADSCR  ======================================================== */
+ #define R_DAC8_DACADSCR_DACADST_Pos    (0UL)    /*!< DACADST (Bit 0)                                       */
+ #define R_DAC8_DACADSCR_DACADST_Msk    (0x1UL)  /*!< DACADST (Bitfield-Mask: 0x01)                         */
+/* =========================================================  DACPC  ========================================================= */
+ #define R_DAC8_DACPC_PUMPEN_Pos        (0UL)    /*!< PUMPEN (Bit 0)                                        */
+ #define R_DAC8_DACPC_PUMPEN_Msk        (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DALI0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  BTVTHR1  ======================================================== */
+ #define R_DALI0_BTVTHR1_BTV2_Pos     (8UL)      /*!< BTV2 (Bit 8)                                          */
+ #define R_DALI0_BTVTHR1_BTV2_Msk     (0xff00UL) /*!< BTV2 (Bitfield-Mask: 0xff)                            */
+ #define R_DALI0_BTVTHR1_BTV1_Pos     (0UL)      /*!< BTV1 (Bit 0)                                          */
+ #define R_DALI0_BTVTHR1_BTV1_Msk     (0x7fUL)   /*!< BTV1 (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  BTVTHR2  ======================================================== */
+ #define R_DALI0_BTVTHR2_BTV4_Pos     (8UL)      /*!< BTV4 (Bit 8)                                          */
+ #define R_DALI0_BTVTHR2_BTV4_Msk     (0xff00UL) /*!< BTV4 (Bitfield-Mask: 0xff)                            */
+ #define R_DALI0_BTVTHR2_BTV3_Pos     (0UL)      /*!< BTV3 (Bit 0)                                          */
+ #define R_DALI0_BTVTHR2_BTV3_Msk     (0xffUL)   /*!< BTV3 (Bitfield-Mask: 0xff)                            */
+/* ========================================================  BTVTHR3  ======================================================== */
+ #define R_DALI0_BTVTHR3_BTV5_Pos     (0UL)      /*!< BTV5 (Bit 0)                                          */
+ #define R_DALI0_BTVTHR3_BTV5_Msk     (0xffUL)   /*!< BTV5 (Bitfield-Mask: 0xff)                            */
+/* ========================================================  BTVTHR4  ======================================================== */
+ #define R_DALI0_BTVTHR4_BTV6_Pos     (0UL)      /*!< BTV6 (Bit 0)                                          */
+ #define R_DALI0_BTVTHR4_BTV6_Msk     (0x1ffUL)  /*!< BTV6 (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  COLTHR1  ======================================================== */
+ #define R_DALI0_COLTHR1_COL2_Pos     (8UL)      /*!< COL2 (Bit 8)                                          */
+ #define R_DALI0_COLTHR1_COL2_Msk     (0x3f00UL) /*!< COL2 (Bitfield-Mask: 0x3f)                            */
+ #define R_DALI0_COLTHR1_COL1_Pos     (0UL)      /*!< COL1 (Bit 0)                                          */
+ #define R_DALI0_COLTHR1_COL1_Msk     (0x3fUL)   /*!< COL1 (Bitfield-Mask: 0x3f)                            */
+/* ========================================================  COLTHR2  ======================================================== */
+ #define R_DALI0_COLTHR2_COL4_Pos     (8UL)      /*!< COL4 (Bit 8)                                          */
+ #define R_DALI0_COLTHR2_COL4_Msk     (0x7f00UL) /*!< COL4 (Bitfield-Mask: 0x7f)                            */
+ #define R_DALI0_COLTHR2_COL3_Pos     (0UL)      /*!< COL3 (Bit 0)                                          */
+ #define R_DALI0_COLTHR2_COL3_Msk     (0x7fUL)   /*!< COL3 (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  COLTHR3  ======================================================== */
+ #define R_DALI0_COLTHR3_COL6_Pos     (8UL)      /*!< COL6 (Bit 8)                                          */
+ #define R_DALI0_COLTHR3_COL6_Msk     (0x7f00UL) /*!< COL6 (Bitfield-Mask: 0x7f)                            */
+ #define R_DALI0_COLTHR3_COL5_Pos     (0UL)      /*!< COL5 (Bit 0)                                          */
+ #define R_DALI0_COLTHR3_COL5_Msk     (0x7fUL)   /*!< COL5 (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  COLTHR4  ======================================================== */
+ #define R_DALI0_COLTHR4_COL8_Pos     (8UL)      /*!< COL8 (Bit 8)                                          */
+ #define R_DALI0_COLTHR4_COL8_Msk     (0xff00UL) /*!< COL8 (Bitfield-Mask: 0xff)                            */
+ #define R_DALI0_COLTHR4_COL7_Pos     (0UL)      /*!< COL7 (Bit 0)                                          */
+ #define R_DALI0_COLTHR4_COL7_Msk     (0xffUL)   /*!< COL7 (Bitfield-Mask: 0xff)                            */
+/* ========================================================  COLTHR5  ======================================================== */
+ #define R_DALI0_COLTHR5_COL9_Pos     (0UL)      /*!< COL9 (Bit 0)                                          */
+ #define R_DALI0_COLTHR5_COL9_Msk     (0xffUL)   /*!< COL9 (Bitfield-Mask: 0xff)                            */
+/* =========================================================  CNFR1  ========================================================= */
+ #define R_DALI0_CNFR1_CHL_Pos        (12UL)     /*!< CHL (Bit 12)                                          */
+ #define R_DALI0_CNFR1_CHL_Msk        (0x7000UL) /*!< CHL (Bitfield-Mask: 0x07)                             */
+ #define R_DALI0_CNFR1_CKS_Pos        (8UL)      /*!< CKS (Bit 8)                                           */
+ #define R_DALI0_CNFR1_CKS_Msk        (0x300UL)  /*!< CKS (Bitfield-Mask: 0x03)                             */
+ #define R_DALI0_CNFR1_BR_Pos         (0UL)      /*!< BR (Bit 0)                                            */
+ #define R_DALI0_CNFR1_BR_Msk         (0xffUL)   /*!< BR (Bitfield-Mask: 0xff)                              */
+/* =========================================================  CNFR2  ========================================================= */
+ #define R_DALI0_CNFR2_CDM0_Pos       (5UL)      /*!< CDM0 (Bit 5)                                          */
+ #define R_DALI0_CNFR2_CDM0_Msk       (0x20UL)   /*!< CDM0 (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CNFR2_CDE_Pos        (4UL)      /*!< CDE (Bit 4)                                           */
+ #define R_DALI0_CNFR2_CDE_Msk        (0x10UL)   /*!< CDE (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_CNFR2_TXWE_Pos       (3UL)      /*!< TXWE (Bit 3)                                          */
+ #define R_DALI0_CNFR2_TXWE_Msk       (0x8UL)    /*!< TXWE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CNFR2_SGA_Pos        (2UL)      /*!< SGA (Bit 2)                                           */
+ #define R_DALI0_CNFR2_SGA_Msk        (0x4UL)    /*!< SGA (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_CNFR2_BTVM_Pos       (1UL)      /*!< BTVM (Bit 1)                                          */
+ #define R_DALI0_CNFR2_BTVM_Msk       (0x2UL)    /*!< BTVM (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CNFR2_BTVE_Pos       (0UL)      /*!< BTVE (Bit 0)                                          */
+ #define R_DALI0_CNFR2_BTVE_Msk       (0x1UL)    /*!< BTVE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  TXWR1  ========================================================= */
+ #define R_DALI0_TXWR1_TXLW_Pos       (0UL)      /*!< TXLW (Bit 0)                                          */
+ #define R_DALI0_TXWR1_TXLW_Msk       (0x7fUL)   /*!< TXLW (Bitfield-Mask: 0x7f)                            */
+/* =========================================================  TDR1H  ========================================================= */
+ #define R_DALI0_TDR1H_DTDR_Pos       (0UL)      /*!< DTDR (Bit 0)                                          */
+ #define R_DALI0_TDR1H_DTDR_Msk       (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  TDR1L  ========================================================= */
+ #define R_DALI0_TDR1L_DTDR_Pos       (0UL)      /*!< DTDR (Bit 0)                                          */
+ #define R_DALI0_TDR1L_DTDR_Msk       (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  TRSTR1  ========================================================= */
+ #define R_DALI0_TRSTR1_TRST_Pos      (0UL)      /*!< TRST (Bit 0)                                          */
+ #define R_DALI0_TRSTR1_TRST_Msk      (0x1UL)    /*!< TRST (Bitfield-Mask: 0x01)                            */
+/* =========================================================  CTR1  ========================================================== */
+ #define R_DALI0_CTR1_FEIE_Pos        (12UL)     /*!< FEIE (Bit 12)                                         */
+ #define R_DALI0_CTR1_FEIE_Msk        (0x1000UL) /*!< FEIE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CTR1_BPIE_Pos        (11UL)     /*!< BPIE (Bit 11)                                         */
+ #define R_DALI0_CTR1_BPIE_Msk        (0x800UL)  /*!< BPIE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CTR1_CLIE_Pos        (10UL)     /*!< CLIE (Bit 10)                                         */
+ #define R_DALI0_CTR1_CLIE_Msk        (0x400UL)  /*!< CLIE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CTR1_DEIE_Pos        (9UL)      /*!< DEIE (Bit 9)                                          */
+ #define R_DALI0_CTR1_DEIE_Msk        (0x200UL)  /*!< DEIE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CTR1_SDIE_Pos        (8UL)      /*!< SDIE (Bit 8)                                          */
+ #define R_DALI0_CTR1_SDIE_Msk        (0x100UL)  /*!< SDIE (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_CTR1_RE_Pos          (1UL)      /*!< RE (Bit 1)                                            */
+ #define R_DALI0_CTR1_RE_Msk          (0x2UL)    /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_DALI0_CTR1_TE_Pos          (0UL)      /*!< TE (Bit 0)                                            */
+ #define R_DALI0_CTR1_TE_Msk          (0x1UL)    /*!< TE (Bitfield-Mask: 0x01)                              */
+/* ========================================================  TXDCTR1  ======================================================== */
+ #define R_DALI0_TXDCTR1_TXASE_Pos    (1UL)      /*!< TXASE (Bit 1)                                         */
+ #define R_DALI0_TXDCTR1_TXASE_Msk    (0x2UL)    /*!< TXASE (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_TXDCTR1_TXAS_Pos     (0UL)      /*!< TXAS (Bit 0)                                          */
+ #define R_DALI0_TXDCTR1_TXAS_Msk     (0x1UL)    /*!< TXAS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  RDR1H  ========================================================= */
+ #define R_DALI0_RDR1H_DRDR_Pos       (0UL)      /*!< DRDR (Bit 0)                                          */
+ #define R_DALI0_RDR1H_DRDR_Msk       (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  RDR1L  ========================================================= */
+ #define R_DALI0_RDR1L_DRDR_Pos       (0UL)      /*!< DRDR (Bit 0)                                          */
+ #define R_DALI0_RDR1L_DRDR_Msk       (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  STR1  ========================================================== */
+ #define R_DALI0_STR1_RDBL_Pos        (10UL)     /*!< RDBL (Bit 10)                                         */
+ #define R_DALI0_STR1_RDBL_Msk        (0xfc00UL) /*!< RDBL (Bitfield-Mask: 0x3f)                            */
+ #define R_DALI0_STR1_DAF_Pos         (9UL)      /*!< DAF (Bit 9)                                           */
+ #define R_DALI0_STR1_DAF_Msk         (0x200UL)  /*!< DAF (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_STR1_CDF_Pos         (8UL)      /*!< CDF (Bit 8)                                           */
+ #define R_DALI0_STR1_CDF_Msk         (0x100UL)  /*!< CDF (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_STR1_O32F_Pos        (7UL)      /*!< O32F (Bit 7)                                          */
+ #define R_DALI0_STR1_O32F_Msk        (0x80UL)   /*!< O32F (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_STR1_BPDF_Pos        (6UL)      /*!< BPDF (Bit 6)                                          */
+ #define R_DALI0_STR1_BPDF_Msk        (0x40UL)   /*!< BPDF (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_STR1_BBF_Pos         (5UL)      /*!< BBF (Bit 5)                                           */
+ #define R_DALI0_STR1_BBF_Msk         (0x20UL)   /*!< BBF (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_STR1_TENDF_Pos       (4UL)      /*!< TENDF (Bit 4)                                         */
+ #define R_DALI0_STR1_TENDF_Msk       (0x10UL)   /*!< TENDF (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_STR1_RDRF_Pos        (3UL)      /*!< RDRF (Bit 3)                                          */
+ #define R_DALI0_STR1_RDRF_Msk        (0x8UL)    /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_STR1_BTVF_Pos        (2UL)      /*!< BTVF (Bit 2)                                          */
+ #define R_DALI0_STR1_BTVF_Msk        (0x4UL)    /*!< BTVF (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_STR1_OVF_Pos         (1UL)      /*!< OVF (Bit 1)                                           */
+ #define R_DALI0_STR1_OVF_Msk         (0x2UL)    /*!< OVF (Bitfield-Mask: 0x01)                             */
+ #define R_DALI0_STR1_MFEF_Pos        (0UL)      /*!< MFEF (Bit 0)                                          */
+ #define R_DALI0_STR1_MFEF_Msk        (0x1UL)    /*!< MFEF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  COLR1  ========================================================= */
+ #define R_DALI0_COLR1_TXDCV_Pos      (13UL)     /*!< TXDCV (Bit 13)                                        */
+ #define R_DALI0_COLR1_TXDCV_Msk      (0x2000UL) /*!< TXDCV (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_COLR1_RXDCEG_Pos     (12UL)     /*!< RXDCEG (Bit 12)                                       */
+ #define R_DALI0_COLR1_RXDCEG_Msk     (0x1000UL) /*!< RXDCEG (Bitfield-Mask: 0x01)                          */
+ #define R_DALI0_COLR1_RXDMON_Pos     (11UL)     /*!< RXDMON (Bit 11)                                       */
+ #define R_DALI0_COLR1_RXDMON_Msk     (0x800UL)  /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+ #define R_DALI0_COLR1_CLDAF_Pos      (10UL)     /*!< CLDAF (Bit 10)                                        */
+ #define R_DALI0_COLR1_CLDAF_Msk      (0x400UL)  /*!< CLDAF (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_COLR1_CDTF1_Pos      (4UL)      /*!< CDTF1 (Bit 4)                                         */
+ #define R_DALI0_COLR1_CDTF1_Msk      (0x10UL)   /*!< CDTF1 (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_COLR1_CFTF2_Pos      (0UL)      /*!< CFTF2 (Bit 0)                                         */
+ #define R_DALI0_COLR1_CFTF2_Msk      (0xfUL)    /*!< CFTF2 (Bitfield-Mask: 0x0f)                           */
+/* =========================================================  FECR1  ========================================================= */
+ #define R_DALI0_FECR1_DAFC_Pos       (9UL)      /*!< DAFC (Bit 9)                                          */
+ #define R_DALI0_FECR1_DAFC_Msk       (0x200UL)  /*!< DAFC (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_FECR1_CDFC_Pos       (8UL)      /*!< CDFC (Bit 8)                                          */
+ #define R_DALI0_FECR1_CDFC_Msk       (0x100UL)  /*!< CDFC (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_FECR1_O32FC_Pos      (7UL)      /*!< O32FC (Bit 7)                                         */
+ #define R_DALI0_FECR1_O32FC_Msk      (0x80UL)   /*!< O32FC (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_FECR1_BPDFC_Pos      (6UL)      /*!< BPDFC (Bit 6)                                         */
+ #define R_DALI0_FECR1_BPDFC_Msk      (0x40UL)   /*!< BPDFC (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_FECR1_BBFC_Pos       (5UL)      /*!< BBFC (Bit 5)                                          */
+ #define R_DALI0_FECR1_BBFC_Msk       (0x20UL)   /*!< BBFC (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_FECR1_TENDFC_Pos     (4UL)      /*!< TENDFC (Bit 4)                                        */
+ #define R_DALI0_FECR1_TENDFC_Msk     (0x10UL)   /*!< TENDFC (Bitfield-Mask: 0x01)                          */
+ #define R_DALI0_FECR1_RDRFC_Pos      (3UL)      /*!< RDRFC (Bit 3)                                         */
+ #define R_DALI0_FECR1_RDRFC_Msk      (0x8UL)    /*!< RDRFC (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_FECR1_BTVFC_Pos      (2UL)      /*!< BTVFC (Bit 2)                                         */
+ #define R_DALI0_FECR1_BTVFC_Msk      (0x4UL)    /*!< BTVFC (Bitfield-Mask: 0x01)                           */
+ #define R_DALI0_FECR1_OVFC_Pos       (1UL)      /*!< OVFC (Bit 1)                                          */
+ #define R_DALI0_FECR1_OVFC_Msk       (0x2UL)    /*!< OVFC (Bitfield-Mask: 0x01)                            */
+ #define R_DALI0_FECR1_MFEFC_Pos      (0UL)      /*!< MFEFC (Bit 0)                                         */
+ #define R_DALI0_FECR1_MFEFC_Msk      (0x1UL)    /*!< MFEFC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SWRR1  ========================================================= */
+ #define R_DALI0_SWRR1_SWR_Pos        (0UL)      /*!< SWR (Bit 0)                                           */
+ #define R_DALI0_SWRR1_SWR_Msk        (0x1UL)    /*!< SWR (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DEBUG                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DBGSTR  ========================================================= */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
+/* =======================================================  DBGSTOPCR  ======================================================= */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DMA                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMAST  ========================================================= */
+ #define R_DMA_DMAST_DMST_Pos    (0UL)   /*!< DMST (Bit 0)                                          */
+ #define R_DMA_DMAST_DMST_Msk    (0x1UL) /*!< DMST (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_DMAC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DMSAR  ========================================================= */
+ #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
+ #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMDAR  ========================================================= */
+ #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
+ #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCRA  ========================================================= */
+ #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
+ #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
+ #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
+ #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
+/* =========================================================  DMCRB  ========================================================= */
+ #define R_DMAC0_DMCRB_DMCRB_Pos     (0UL)          /*!< DMCRB (Bit 0)                                         */
+ #define R_DMAC0_DMCRB_DMCRB_Msk     (0xffffUL)     /*!< DMCRB (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DMTMD  ========================================================= */
+ #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
+ #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
+ #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
+ #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
+ #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
+ #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
+/* =========================================================  DMINT  ========================================================= */
+ #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
+ #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
+ #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
+ #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
+ #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
+ #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
+ #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMAMD  ========================================================= */
+ #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
+ #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
+ #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
+ #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
+ #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
+ #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
+ #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
+/* =========================================================  DMOFR  ========================================================= */
+ #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
+ #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  DMCNT  ========================================================= */
+ #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
+ #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  DMREQ  ========================================================= */
+ #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
+ #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
+ #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
+/* =========================================================  DMSTS  ========================================================= */
+ #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
+ #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
+ #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
+ #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
+ #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DOC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DOCR  ========================================================== */
+ #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
+ #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
+ #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
+ #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
+ #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
+ #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
+ #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
+/* =========================================================  DODIR  ========================================================= */
+ #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
+ #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  DODSR  ========================================================= */
+ #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
+ #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DRW                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  CONTROL  ======================================================== */
+ #define R_DRW_CONTROL_SPANSTORE_Pos           (23UL)         /*!< SPANSTORE (Bit 23)                                    */
+ #define R_DRW_CONTROL_SPANSTORE_Msk           (0x800000UL)   /*!< SPANSTORE (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_CONTROL_SPANABORT_Pos           (22UL)         /*!< SPANABORT (Bit 22)                                    */
+ #define R_DRW_CONTROL_SPANABORT_Msk           (0x400000UL)   /*!< SPANABORT (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_CONTROL_UNIONCD_Pos             (21UL)         /*!< UNIONCD (Bit 21)                                      */
+ #define R_DRW_CONTROL_UNIONCD_Msk             (0x200000UL)   /*!< UNIONCD (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_CONTROL_UNIONAB_Pos             (20UL)         /*!< UNIONAB (Bit 20)                                      */
+ #define R_DRW_CONTROL_UNIONAB_Msk             (0x100000UL)   /*!< UNIONAB (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_CONTROL_UNION56_Pos             (19UL)         /*!< UNION56 (Bit 19)                                      */
+ #define R_DRW_CONTROL_UNION56_Msk             (0x80000UL)    /*!< UNION56 (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_CONTROL_UNION34_Pos             (18UL)         /*!< UNION34 (Bit 18)                                      */
+ #define R_DRW_CONTROL_UNION34_Msk             (0x40000UL)    /*!< UNION34 (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_CONTROL_UNION12_Pos             (17UL)         /*!< UNION12 (Bit 17)                                      */
+ #define R_DRW_CONTROL_UNION12_Msk             (0x20000UL)    /*!< UNION12 (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_CONTROL_BAND2ENABLE_Pos         (16UL)         /*!< BAND2ENABLE (Bit 16)                                  */
+ #define R_DRW_CONTROL_BAND2ENABLE_Msk         (0x10000UL)    /*!< BAND2ENABLE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_CONTROL_BAND1ENABLE_Pos         (15UL)         /*!< BAND1ENABLE (Bit 15)                                  */
+ #define R_DRW_CONTROL_BAND1ENABLE_Msk         (0x8000UL)     /*!< BAND1ENABLE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_CONTROL_LIM6THRESHOLD_Pos       (14UL)         /*!< LIM6THRESHOLD (Bit 14)                                */
+ #define R_DRW_CONTROL_LIM6THRESHOLD_Msk       (0x4000UL)     /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_LIM5THRESHOLD_Pos       (13UL)         /*!< LIM5THRESHOLD (Bit 13)                                */
+ #define R_DRW_CONTROL_LIM5THRESHOLD_Msk       (0x2000UL)     /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_LIM4THRESHOLD_Pos       (12UL)         /*!< LIM4THRESHOLD (Bit 12)                                */
+ #define R_DRW_CONTROL_LIM4THRESHOLD_Msk       (0x1000UL)     /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_LIM3THRESHOLD_Pos       (11UL)         /*!< LIM3THRESHOLD (Bit 11)                                */
+ #define R_DRW_CONTROL_LIM3THRESHOLD_Msk       (0x800UL)      /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_LIM2THRESHOLD_Pos       (10UL)         /*!< LIM2THRESHOLD (Bit 10)                                */
+ #define R_DRW_CONTROL_LIM2THRESHOLD_Msk       (0x400UL)      /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_LIM1THRESHOLD_Pos       (9UL)          /*!< LIM1THRESHOLD (Bit 9)                                 */
+ #define R_DRW_CONTROL_LIM1THRESHOLD_Msk       (0x200UL)      /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL_QUAD3ENABLE_Pos         (8UL)          /*!< QUAD3ENABLE (Bit 8)                                   */
+ #define R_DRW_CONTROL_QUAD3ENABLE_Msk         (0x100UL)      /*!< QUAD3ENABLE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_CONTROL_QUAD2ENABLE_Pos         (7UL)          /*!< QUAD2ENABLE (Bit 7)                                   */
+ #define R_DRW_CONTROL_QUAD2ENABLE_Msk         (0x80UL)       /*!< QUAD2ENABLE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_CONTROL_QUAD1ENABLE_Pos         (6UL)          /*!< QUAD1ENABLE (Bit 6)                                   */
+ #define R_DRW_CONTROL_QUAD1ENABLE_Msk         (0x40UL)       /*!< QUAD1ENABLE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_CONTROL_LIM6ENABLE_Pos          (5UL)          /*!< LIM6ENABLE (Bit 5)                                    */
+ #define R_DRW_CONTROL_LIM6ENABLE_Msk          (0x20UL)       /*!< LIM6ENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL_LIM5ENABLE_Pos          (4UL)          /*!< LIM5ENABLE (Bit 4)                                    */
+ #define R_DRW_CONTROL_LIM5ENABLE_Msk          (0x10UL)       /*!< LIM5ENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL_LIM4ENABLE_Pos          (3UL)          /*!< LIM4ENABLE (Bit 3)                                    */
+ #define R_DRW_CONTROL_LIM4ENABLE_Msk          (0x8UL)        /*!< LIM4ENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL_LIM3ENABLE_Pos          (2UL)          /*!< LIM3ENABLE (Bit 2)                                    */
+ #define R_DRW_CONTROL_LIM3ENABLE_Msk          (0x4UL)        /*!< LIM3ENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL_LIM2ENABLE_Pos          (1UL)          /*!< LIM2ENABLE (Bit 1)                                    */
+ #define R_DRW_CONTROL_LIM2ENABLE_Msk          (0x2UL)        /*!< LIM2ENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL_LIM1ENABLE_Pos          (0UL)          /*!< LIM1ENABLE (Bit 0)                                    */
+ #define R_DRW_CONTROL_LIM1ENABLE_Msk          (0x1UL)        /*!< LIM1ENABLE (Bitfield-Mask: 0x01)                      */
+/* =======================================================  CONTROL2  ======================================================== */
+ #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos      (30UL)         /*!< RLEPIXELWIDTH (Bit 30)                                */
+ #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk      (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03)                   */
+ #define R_DRW_CONTROL2_BDIA_Pos               (29UL)         /*!< BDIA (Bit 29)                                         */
+ #define R_DRW_CONTROL2_BDIA_Msk               (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01)                            */
+ #define R_DRW_CONTROL2_BSIA_Pos               (28UL)         /*!< BSIA (Bit 28)                                         */
+ #define R_DRW_CONTROL2_BSIA_Msk               (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01)                            */
+ #define R_DRW_CONTROL2_CLUTFORMAT_Pos         (27UL)         /*!< CLUTFORMAT (Bit 27)                                   */
+ #define R_DRW_CONTROL2_CLUTFORMAT_Msk         (0x8000000UL)  /*!< CLUTFORMAT (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL2_COLKEYENABLE_Pos       (26UL)         /*!< COLKEYENABLE (Bit 26)                                 */
+ #define R_DRW_CONTROL2_COLKEYENABLE_Msk       (0x4000000UL)  /*!< COLKEYENABLE (Bitfield-Mask: 0x01)                    */
+ #define R_DRW_CONTROL2_CLUTENABLE_Pos         (25UL)         /*!< CLUTENABLE (Bit 25)                                   */
+ #define R_DRW_CONTROL2_CLUTENABLE_Msk         (0x2000000UL)  /*!< CLUTENABLE (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_CONTROL2_RLEENABLE_Pos          (24UL)         /*!< RLEENABLE (Bit 24)                                    */
+ #define R_DRW_CONTROL2_RLEENABLE_Msk          (0x1000000UL)  /*!< RLEENABLE (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_CONTROL2_WRITEALPHA_Pos         (22UL)         /*!< WRITEALPHA (Bit 22)                                   */
+ #define R_DRW_CONTROL2_WRITEALPHA_Msk         (0xc00000UL)   /*!< WRITEALPHA (Bitfield-Mask: 0x03)                      */
+ #define R_DRW_CONTROL2_WRITEFORMAT10_Pos      (20UL)         /*!< WRITEFORMAT10 (Bit 20)                                */
+ #define R_DRW_CONTROL2_WRITEFORMAT10_Msk      (0x300000UL)   /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03)                   */
+ #define R_DRW_CONTROL2_READFORMAT10_Pos       (18UL)         /*!< READFORMAT10 (Bit 18)                                 */
+ #define R_DRW_CONTROL2_READFORMAT10_Msk       (0xc0000UL)    /*!< READFORMAT10 (Bitfield-Mask: 0x03)                    */
+ #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos     (17UL)         /*!< TEXTUREFILTERY (Bit 17)                               */
+ #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk     (0x20000UL)    /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01)                  */
+ #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos     (16UL)         /*!< TEXTUREFILTERX (Bit 16)                               */
+ #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk     (0x10000UL)    /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01)                  */
+ #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos      (15UL)         /*!< TEXTURECLAMPY (Bit 15)                                */
+ #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk      (0x8000UL)     /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos      (14UL)         /*!< TEXTURECLAMPX (Bit 14)                                */
+ #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk      (0x4000UL)     /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL2_BC2_Pos                (13UL)         /*!< BC2 (Bit 13)                                          */
+ #define R_DRW_CONTROL2_BC2_Msk                (0x2000UL)     /*!< BC2 (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_CONTROL2_BDI_Pos                (12UL)         /*!< BDI (Bit 12)                                          */
+ #define R_DRW_CONTROL2_BDI_Msk                (0x1000UL)     /*!< BDI (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_CONTROL2_BSI_Pos                (11UL)         /*!< BSI (Bit 11)                                          */
+ #define R_DRW_CONTROL2_BSI_Msk                (0x800UL)      /*!< BSI (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_CONTROL2_BDF_Pos                (10UL)         /*!< BDF (Bit 10)                                          */
+ #define R_DRW_CONTROL2_BDF_Msk                (0x400UL)      /*!< BDF (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_CONTROL2_BSF_Pos                (9UL)          /*!< BSF (Bit 9)                                           */
+ #define R_DRW_CONTROL2_BSF_Msk                (0x200UL)      /*!< BSF (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_CONTROL2_WRITEFORMAT2_Pos       (8UL)          /*!< WRITEFORMAT2 (Bit 8)                                  */
+ #define R_DRW_CONTROL2_WRITEFORMAT2_Msk       (0x100UL)      /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01)                    */
+ #define R_DRW_CONTROL2_BDFA_Pos               (7UL)          /*!< BDFA (Bit 7)                                          */
+ #define R_DRW_CONTROL2_BDFA_Msk               (0x80UL)       /*!< BDFA (Bitfield-Mask: 0x01)                            */
+ #define R_DRW_CONTROL2_BSFA_Pos               (6UL)          /*!< BSFA (Bit 6)                                          */
+ #define R_DRW_CONTROL2_BSFA_Msk               (0x40UL)       /*!< BSFA (Bitfield-Mask: 0x01)                            */
+ #define R_DRW_CONTROL2_READFORMAT32_Pos       (4UL)          /*!< READFORMAT32 (Bit 4)                                  */
+ #define R_DRW_CONTROL2_READFORMAT32_Msk       (0x30UL)       /*!< READFORMAT32 (Bitfield-Mask: 0x03)                    */
+ #define R_DRW_CONTROL2_USEACB_Pos             (3UL)          /*!< USEACB (Bit 3)                                        */
+ #define R_DRW_CONTROL2_USEACB_Msk             (0x8UL)        /*!< USEACB (Bitfield-Mask: 0x01)                          */
+ #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos    (2UL)          /*!< PATTERNSOURCEL5 (Bit 2)                               */
+ #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk    (0x4UL)        /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01)                 */
+ #define R_DRW_CONTROL2_TEXTUREENABLE_Pos      (1UL)          /*!< TEXTUREENABLE (Bit 1)                                 */
+ #define R_DRW_CONTROL2_TEXTUREENABLE_Msk      (0x2UL)        /*!< TEXTUREENABLE (Bitfield-Mask: 0x01)                   */
+ #define R_DRW_CONTROL2_PATTERNENABLE_Pos      (0UL)          /*!< PATTERNENABLE (Bit 0)                                 */
+ #define R_DRW_CONTROL2_PATTERNENABLE_Msk      (0x1UL)        /*!< PATTERNENABLE (Bitfield-Mask: 0x01)                   */
+/* ========================================================  IRQCTL  ========================================================= */
+ #define R_DRW_IRQCTL_BUSIRQCLR_Pos            (5UL)          /*!< BUSIRQCLR (Bit 5)                                     */
+ #define R_DRW_IRQCTL_BUSIRQCLR_Msk            (0x20UL)       /*!< BUSIRQCLR (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_IRQCTL_BUSIRQEN_Pos             (4UL)          /*!< BUSIRQEN (Bit 4)                                      */
+ #define R_DRW_IRQCTL_BUSIRQEN_Msk             (0x10UL)       /*!< BUSIRQEN (Bitfield-Mask: 0x01)                        */
+ #define R_DRW_IRQCTL_DLISTIRQCLR_Pos          (3UL)          /*!< DLISTIRQCLR (Bit 3)                                   */
+ #define R_DRW_IRQCTL_DLISTIRQCLR_Msk          (0x8UL)        /*!< DLISTIRQCLR (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_IRQCTL_ENUMIRQCLR_Pos           (2UL)          /*!< ENUMIRQCLR (Bit 2)                                    */
+ #define R_DRW_IRQCTL_ENUMIRQCLR_Msk           (0x4UL)        /*!< ENUMIRQCLR (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_IRQCTL_DLISTIRQEN_Pos           (1UL)          /*!< DLISTIRQEN (Bit 1)                                    */
+ #define R_DRW_IRQCTL_DLISTIRQEN_Msk           (0x2UL)        /*!< DLISTIRQEN (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_IRQCTL_ENUMIRQEN_Pos            (0UL)          /*!< ENUMIRQEN (Bit 0)                                     */
+ #define R_DRW_IRQCTL_ENUMIRQEN_Msk            (0x1UL)        /*!< ENUMIRQEN (Bitfield-Mask: 0x01)                       */
+/* =======================================================  CACHECTL  ======================================================== */
+ #define R_DRW_CACHECTL_CFLUSHTX_Pos           (3UL)          /*!< CFLUSHTX (Bit 3)                                      */
+ #define R_DRW_CACHECTL_CFLUSHTX_Msk           (0x8UL)        /*!< CFLUSHTX (Bitfield-Mask: 0x01)                        */
+ #define R_DRW_CACHECTL_CENABLETX_Pos          (2UL)          /*!< CENABLETX (Bit 2)                                     */
+ #define R_DRW_CACHECTL_CENABLETX_Msk          (0x4UL)        /*!< CENABLETX (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_CACHECTL_CFLUSHFX_Pos           (1UL)          /*!< CFLUSHFX (Bit 1)                                      */
+ #define R_DRW_CACHECTL_CFLUSHFX_Msk           (0x2UL)        /*!< CFLUSHFX (Bitfield-Mask: 0x01)                        */
+ #define R_DRW_CACHECTL_CENABLEFX_Pos          (0UL)          /*!< CENABLEFX (Bit 0)                                     */
+ #define R_DRW_CACHECTL_CENABLEFX_Msk          (0x1UL)        /*!< CENABLEFX (Bitfield-Mask: 0x01)                       */
+/* ========================================================  STATUS  ========================================================= */
+ #define R_DRW_STATUS_BUSERRMDL_Pos            (10UL)         /*!< BUSERRMDL (Bit 10)                                    */
+ #define R_DRW_STATUS_BUSERRMDL_Msk            (0x400UL)      /*!< BUSERRMDL (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_STATUS_BUSERRMTXMRL_Pos         (9UL)          /*!< BUSERRMTXMRL (Bit 9)                                  */
+ #define R_DRW_STATUS_BUSERRMTXMRL_Msk         (0x200UL)      /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01)                    */
+ #define R_DRW_STATUS_BUSERRMFB_Pos            (8UL)          /*!< BUSERRMFB (Bit 8)                                     */
+ #define R_DRW_STATUS_BUSERRMFB_Msk            (0x100UL)      /*!< BUSERRMFB (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_STATUS_BUSIRQ_Pos               (6UL)          /*!< BUSIRQ (Bit 6)                                        */
+ #define R_DRW_STATUS_BUSIRQ_Msk               (0x40UL)       /*!< BUSIRQ (Bitfield-Mask: 0x01)                          */
+ #define R_DRW_STATUS_DLISTIRQ_Pos             (5UL)          /*!< DLISTIRQ (Bit 5)                                      */
+ #define R_DRW_STATUS_DLISTIRQ_Msk             (0x20UL)       /*!< DLISTIRQ (Bitfield-Mask: 0x01)                        */
+ #define R_DRW_STATUS_ENUMIRQ_Pos              (4UL)          /*!< ENUMIRQ (Bit 4)                                       */
+ #define R_DRW_STATUS_ENUMIRQ_Msk              (0x10UL)       /*!< ENUMIRQ (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_STATUS_DLISTACTIVE_Pos          (3UL)          /*!< DLISTACTIVE (Bit 3)                                   */
+ #define R_DRW_STATUS_DLISTACTIVE_Msk          (0x8UL)        /*!< DLISTACTIVE (Bitfield-Mask: 0x01)                     */
+ #define R_DRW_STATUS_CACHEDIRTY_Pos           (2UL)          /*!< CACHEDIRTY (Bit 2)                                    */
+ #define R_DRW_STATUS_CACHEDIRTY_Msk           (0x4UL)        /*!< CACHEDIRTY (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_STATUS_BUSYWRITE_Pos            (1UL)          /*!< BUSYWRITE (Bit 1)                                     */
+ #define R_DRW_STATUS_BUSYWRITE_Msk            (0x2UL)        /*!< BUSYWRITE (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_STATUS_BUSYENUM_Pos             (0UL)          /*!< BUSYENUM (Bit 0)                                      */
+ #define R_DRW_STATUS_BUSYENUM_Msk             (0x1UL)        /*!< BUSYENUM (Bitfield-Mask: 0x01)                        */
+/* ======================================================  HWREVISION  ======================================================= */
+ #define R_DRW_HWREVISION_ACBLEND_Pos          (27UL)         /*!< ACBLEND (Bit 27)                                      */
+ #define R_DRW_HWREVISION_ACBLEND_Msk          (0x8000000UL)  /*!< ACBLEND (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_HWREVISION_COLORKEY_Pos         (25UL)         /*!< COLORKEY (Bit 25)                                     */
+ #define R_DRW_HWREVISION_COLORKEY_Msk         (0x2000000UL)  /*!< COLORKEY (Bitfield-Mask: 0x01)                        */
+ #define R_DRW_HWREVISION_TEXCLUT256_Pos       (24UL)         /*!< TEXCLUT256 (Bit 24)                                   */
+ #define R_DRW_HWREVISION_TEXCLUT256_Msk       (0x1000000UL)  /*!< TEXCLUT256 (Bitfield-Mask: 0x01)                      */
+ #define R_DRW_HWREVISION_RLEUNIT_Pos          (23UL)         /*!< RLEUNIT (Bit 23)                                      */
+ #define R_DRW_HWREVISION_RLEUNIT_Msk          (0x800000UL)   /*!< RLEUNIT (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_HWREVISION_TEXCLU_Pos           (21UL)         /*!< TEXCLU (Bit 21)                                       */
+ #define R_DRW_HWREVISION_TEXCLU_Msk           (0x200000UL)   /*!< TEXCLU (Bitfield-Mask: 0x01)                          */
+ #define R_DRW_HWREVISION_PERFCOUNT_Pos        (20UL)         /*!< PERFCOUNT (Bit 20)                                    */
+ #define R_DRW_HWREVISION_PERFCOUNT_Msk        (0x100000UL)   /*!< PERFCOUNT (Bitfield-Mask: 0x01)                       */
+ #define R_DRW_HWREVISION_TXCACHE_Pos          (19UL)         /*!< TXCACHE (Bit 19)                                      */
+ #define R_DRW_HWREVISION_TXCACHE_Msk          (0x80000UL)    /*!< TXCACHE (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_HWREVISION_FBCACHE_Pos          (18UL)         /*!< FBCACHE (Bit 18)                                      */
+ #define R_DRW_HWREVISION_FBCACHE_Msk          (0x40000UL)    /*!< FBCACHE (Bitfield-Mask: 0x01)                         */
+ #define R_DRW_HWREVISION_DLR_Pos              (17UL)         /*!< DLR (Bit 17)                                          */
+ #define R_DRW_HWREVISION_DLR_Msk              (0x20000UL)    /*!< DLR (Bitfield-Mask: 0x01)                             */
+ #define R_DRW_HWREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
+ #define R_DRW_HWREVISION_REV_Msk              (0xfffUL)      /*!< REV (Bitfield-Mask: 0xfff)                            */
+/* ========================================================  COLOR1  ========================================================= */
+ #define R_DRW_COLOR1_COLOR1A_Pos              (24UL)         /*!< COLOR1A (Bit 24)                                      */
+ #define R_DRW_COLOR1_COLOR1A_Msk              (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR1_COLOR1R_Pos              (16UL)         /*!< COLOR1R (Bit 16)                                      */
+ #define R_DRW_COLOR1_COLOR1R_Msk              (0xff0000UL)   /*!< COLOR1R (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR1_COLOR1G_Pos              (8UL)          /*!< COLOR1G (Bit 8)                                       */
+ #define R_DRW_COLOR1_COLOR1G_Msk              (0xff00UL)     /*!< COLOR1G (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR1_COLOR1B_Pos              (0UL)          /*!< COLOR1B (Bit 0)                                       */
+ #define R_DRW_COLOR1_COLOR1B_Msk              (0xffUL)       /*!< COLOR1B (Bitfield-Mask: 0xff)                         */
+/* ========================================================  COLOR2  ========================================================= */
+ #define R_DRW_COLOR2_COLOR2A_Pos              (24UL)         /*!< COLOR2A (Bit 24)                                      */
+ #define R_DRW_COLOR2_COLOR2A_Msk              (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR2_COLOR2R_Pos              (16UL)         /*!< COLOR2R (Bit 16)                                      */
+ #define R_DRW_COLOR2_COLOR2R_Msk              (0xff0000UL)   /*!< COLOR2R (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR2_COLOR2G_Pos              (8UL)          /*!< COLOR2G (Bit 8)                                       */
+ #define R_DRW_COLOR2_COLOR2G_Msk              (0xff00UL)     /*!< COLOR2G (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLOR2_COLOR2B_Pos              (0UL)          /*!< COLOR2B (Bit 0)                                       */
+ #define R_DRW_COLOR2_COLOR2B_Msk              (0xffUL)       /*!< COLOR2B (Bitfield-Mask: 0xff)                         */
+/* ========================================================  PATTERN  ======================================================== */
+ #define R_DRW_PATTERN_PATTERN_Pos             (0UL)          /*!< PATTERN (Bit 0)                                       */
+ #define R_DRW_PATTERN_PATTERN_Msk             (0xffUL)       /*!< PATTERN (Bitfield-Mask: 0xff)                         */
+/* ========================================================  L1START  ======================================================== */
+ #define R_DRW_L1START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L1START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L2START  ======================================================== */
+ #define R_DRW_L2START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L2START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L3START  ======================================================== */
+ #define R_DRW_L3START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L3START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L4START  ======================================================== */
+ #define R_DRW_L4START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L4START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L5START  ======================================================== */
+ #define R_DRW_L5START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L5START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L6START  ======================================================== */
+ #define R_DRW_L6START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
+ #define R_DRW_L6START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  L1XADD  ========================================================= */
+ #define R_DRW_L1XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L1XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L2XADD  ========================================================= */
+ #define R_DRW_L2XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L2XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L3XADD  ========================================================= */
+ #define R_DRW_L3XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L3XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L4XADD  ========================================================= */
+ #define R_DRW_L4XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L4XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L5XADD  ========================================================= */
+ #define R_DRW_L5XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L5XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L6XADD  ========================================================= */
+ #define R_DRW_L6XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
+ #define R_DRW_L6XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L1YADD  ========================================================= */
+ #define R_DRW_L1YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L1YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L2YADD  ========================================================= */
+ #define R_DRW_L2YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L2YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L3YADD  ========================================================= */
+ #define R_DRW_L3YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L3YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L4YADD  ========================================================= */
+ #define R_DRW_L4YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L4YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L5YADD  ========================================================= */
+ #define R_DRW_L5YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L5YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L6YADD  ========================================================= */
+ #define R_DRW_L6YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
+ #define R_DRW_L6YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L1BAND  ========================================================= */
+ #define R_DRW_L1BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
+ #define R_DRW_L1BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  L2BAND  ========================================================= */
+ #define R_DRW_L2BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
+ #define R_DRW_L2BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  TEXORIGIN  ======================================================= */
+ #define R_DRW_TEXORIGIN_TEXORIGIN_Pos         (0UL)          /*!< TEXORIGIN (Bit 0)                                     */
+ #define R_DRW_TEXORIGIN_TEXORIGIN_Msk         (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  TEXPITCH  ======================================================== */
+ #define R_DRW_TEXPITCH_TEXPITCH_Pos           (0UL)          /*!< TEXPITCH (Bit 0)                                      */
+ #define R_DRW_TEXPITCH_TEXPITCH_Msk           (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  TEXMASK  ======================================================== */
+ #define R_DRW_TEXMASK_TEXVMASK_Pos            (11UL)         /*!< TEXVMASK (Bit 11)                                     */
+ #define R_DRW_TEXMASK_TEXVMASK_Msk            (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff)                    */
+ #define R_DRW_TEXMASK_TEXUMASK_Pos            (0UL)          /*!< TEXUMASK (Bit 0)                                      */
+ #define R_DRW_TEXMASK_TEXUMASK_Msk            (0x7ffUL)      /*!< TEXUMASK (Bitfield-Mask: 0x7ff)                       */
+/* ========================================================  LUSTART  ======================================================== */
+ #define R_DRW_LUSTART_LUSTART_Pos             (0UL)          /*!< LUSTART (Bit 0)                                       */
+ #define R_DRW_LUSTART_LUSTART_Msk             (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  LUXADD  ========================================================= */
+ #define R_DRW_LUXADD_LUXADD_Pos               (0UL)          /*!< LUXADD (Bit 0)                                        */
+ #define R_DRW_LUXADD_LUXADD_Msk               (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  LUYADD  ========================================================= */
+ #define R_DRW_LUYADD_LUYADD_Pos               (0UL)          /*!< LUYADD (Bit 0)                                        */
+ #define R_DRW_LUYADD_LUYADD_Msk               (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  LVSTARTI  ======================================================== */
+ #define R_DRW_LVSTARTI_LVSTARTI_Pos           (0UL)          /*!< LVSTARTI (Bit 0)                                      */
+ #define R_DRW_LVSTARTI_LVSTARTI_Msk           (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  LVSTARTF  ======================================================== */
+ #define R_DRW_LVSTARTF_LVSTARTF_Pos           (0UL)          /*!< LVSTARTF (Bit 0)                                      */
+ #define R_DRW_LVSTARTF_LVSTARTF_Msk           (0xffffUL)     /*!< LVSTARTF (Bitfield-Mask: 0xffff)                      */
+/* ========================================================  LVXADDI  ======================================================== */
+ #define R_DRW_LVXADDI_LVXADDI_Pos             (0UL)          /*!< LVXADDI (Bit 0)                                       */
+ #define R_DRW_LVXADDI_LVXADDI_Msk             (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  LVYADDI  ======================================================== */
+ #define R_DRW_LVYADDI_LVYADDI_Pos             (0UL)          /*!< LVYADDI (Bit 0)                                       */
+ #define R_DRW_LVYADDI_LVYADDI_Msk             (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  LVYXADDF  ======================================================== */
+ #define R_DRW_LVYXADDF_LVYADDF_Pos            (16UL)         /*!< LVYADDF (Bit 16)                                      */
+ #define R_DRW_LVYXADDF_LVYADDF_Msk            (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff)                       */
+ #define R_DRW_LVYXADDF_LVXADDF_Pos            (0UL)          /*!< LVXADDF (Bit 0)                                       */
+ #define R_DRW_LVYXADDF_LVXADDF_Msk            (0xffffUL)     /*!< LVXADDF (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  TEXCLADDR  ======================================================= */
+ #define R_DRW_TEXCLADDR_CLADDR_Pos            (0UL)          /*!< CLADDR (Bit 0)                                        */
+ #define R_DRW_TEXCLADDR_CLADDR_Msk            (0xffUL)       /*!< CLADDR (Bitfield-Mask: 0xff)                          */
+/* =======================================================  TEXCLDATA  ======================================================= */
+ #define R_DRW_TEXCLDATA_CLDATA_Pos            (0UL)          /*!< CLDATA (Bit 0)                                        */
+ #define R_DRW_TEXCLDATA_CLDATA_Msk            (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  TEXCLOFFSET  ====================================================== */
+ #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos        (0UL)          /*!< CLOFFSET (Bit 0)                                      */
+ #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk        (0xffUL)       /*!< CLOFFSET (Bitfield-Mask: 0xff)                        */
+/* ========================================================  COLKEY  ========================================================= */
+ #define R_DRW_COLKEY_COLKEYR_Pos              (16UL)         /*!< COLKEYR (Bit 16)                                      */
+ #define R_DRW_COLKEY_COLKEYR_Msk              (0xff0000UL)   /*!< COLKEYR (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLKEY_COLKEYG_Pos              (8UL)          /*!< COLKEYG (Bit 8)                                       */
+ #define R_DRW_COLKEY_COLKEYG_Msk              (0xff00UL)     /*!< COLKEYG (Bitfield-Mask: 0xff)                         */
+ #define R_DRW_COLKEY_COLKEYB_Pos              (0UL)          /*!< COLKEYB (Bit 0)                                       */
+ #define R_DRW_COLKEY_COLKEYB_Msk              (0xffUL)       /*!< COLKEYB (Bitfield-Mask: 0xff)                         */
+/* =========================================================  SIZE  ========================================================== */
+ #define R_DRW_SIZE_SIZEY_Pos                  (16UL)         /*!< SIZEY (Bit 16)                                        */
+ #define R_DRW_SIZE_SIZEY_Msk                  (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff)                         */
+ #define R_DRW_SIZE_SIZEX_Pos                  (0UL)          /*!< SIZEX (Bit 0)                                         */
+ #define R_DRW_SIZE_SIZEX_Msk                  (0xffffUL)     /*!< SIZEX (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  PITCH  ========================================================= */
+ #define R_DRW_PITCH_SSD_Pos                   (16UL)         /*!< SSD (Bit 16)                                          */
+ #define R_DRW_PITCH_SSD_Msk                   (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff)                           */
+ #define R_DRW_PITCH_PITCH_Pos                 (0UL)          /*!< PITCH (Bit 0)                                         */
+ #define R_DRW_PITCH_PITCH_Msk                 (0xffffUL)     /*!< PITCH (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  ORIGIN  ========================================================= */
+ #define R_DRW_ORIGIN_ORIGIN_Pos               (0UL)          /*!< ORIGIN (Bit 0)                                        */
+ #define R_DRW_ORIGIN_ORIGIN_Msk               (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff)                    */
+/* ======================================================  DLISTSTART  ======================================================= */
+ #define R_DRW_DLISTSTART_DLISTSTART_Pos       (0UL)          /*!< DLISTSTART (Bit 0)                                    */
+ #define R_DRW_DLISTSTART_DLISTSTART_Msk       (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff)                */
+/* ======================================================  PERFTRIGGER  ====================================================== */
+ #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos    (16UL)         /*!< PERFTRIGGER2 (Bit 16)                                 */
+ #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk    (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff)                  */
+ #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos    (0UL)          /*!< PERFTRIGGER1 (Bit 0)                                  */
+ #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk    (0xffffUL)     /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff)                  */
+/* ======================================================  PERFCOUNT1  ======================================================= */
+ #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
+ #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
+/* ======================================================  PERFCOUNT2  ======================================================= */
+ #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
+ #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
+
+/* =========================================================================================================================== */
+/* ================                                           R_DTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  DTCCR  ========================================================= */
+ #define R_DTC_DTCCR_RRS_Pos        (4UL)          /*!< RRS (Bit 4)                                           */
+ #define R_DTC_DTCCR_RRS_Msk        (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DTCVBR  ========================================================= */
+ #define R_DTC_DTCVBR_DTCVBR_Pos    (0UL)          /*!< DTCVBR (Bit 0)                                        */
+ #define R_DTC_DTCVBR_DTCVBR_Msk    (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  DTCST  ========================================================= */
+ #define R_DTC_DTCST_DTCST_Pos      (0UL)          /*!< DTCST (Bit 0)                                         */
+ #define R_DTC_DTCST_DTCST_Msk      (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DTCSTS  ========================================================= */
+ #define R_DTC_DTCSTS_ACT_Pos       (15UL)         /*!< ACT (Bit 15)                                          */
+ #define R_DTC_DTCSTS_ACT_Msk       (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
+ #define R_DTC_DTCSTS_VECN_Pos      (0UL)          /*!< VECN (Bit 0)                                          */
+ #define R_DTC_DTCSTS_VECN_Msk      (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ELC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ELCR  ========================================================== */
+ #define R_ELC_ELCR_ELCON_Pos    (7UL)    /*!< ELCON (Bit 7)                                         */
+ #define R_ELC_ELCR_ELCON_Msk    (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_ETHERC0                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ECMR  ========================================================== */
+ #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
+ #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
+ #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
+ #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
+ #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
+ #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
+ #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
+ #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
+ #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
+ #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
+ #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
+ #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
+ #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
+ #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RFLR  ========================================================== */
+ #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
+ #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
+/* =========================================================  ECSR  ========================================================== */
+ #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
+ #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
+ #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
+ #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
+ #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
+ #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
+/* ========================================================  ECSIPR  ========================================================= */
+ #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
+ #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
+ #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
+ #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
+/* ==========================================================  PIR  ========================================================== */
+ #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
+ #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
+ #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
+ #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
+ #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
+/* ==========================================================  PSR  ========================================================== */
+ #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
+ #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
+/* =========================================================  RDMLR  ========================================================= */
+ #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
+ #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
+/* =========================================================  IPGR  ========================================================== */
+ #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
+ #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
+/* ==========================================================  APR  ========================================================== */
+ #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
+ #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
+/* ==========================================================  MPR  ========================================================== */
+ #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
+ #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
+/* =========================================================  RFCF  ========================================================== */
+ #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
+ #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
+/* ========================================================  TPAUSER  ======================================================== */
+ #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
+ #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
+/* =======================================================  TPAUSECR  ======================================================== */
+/* =========================================================  BCFRR  ========================================================= */
+ #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
+ #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  MAHR  ========================================================== */
+ #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
+ #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  MALR  ========================================================== */
+ #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
+ #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  TROCR  ========================================================= */
+ #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
+ #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  CDCR  ========================================================== */
+/* =========================================================  LCCR  ========================================================== */
+ #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
+ #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  CNDCR  ========================================================= */
+ #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
+ #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  CEFCR  ========================================================= */
+ #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
+ #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  FRECR  ========================================================= */
+ #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
+ #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  TSFRCR  ========================================================= */
+ #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
+ #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  TLFRCR  ========================================================= */
+ #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
+ #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  RFCR  ========================================================== */
+ #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
+ #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  MAFCR  ========================================================= */
+ #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
+ #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                      R_ETHERC_EDMAC                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  EDMR  ========================================================== */
+ #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
+ #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
+ #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
+ #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
+/* =========================================================  EDTRR  ========================================================= */
+ #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
+ #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
+/* =========================================================  EDRRR  ========================================================= */
+ #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
+ #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
+/* =========================================================  TDLAR  ========================================================= */
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  RDLAR  ========================================================= */
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  EESR  ========================================================== */
+ #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
+ #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
+ #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
+ #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
+ #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
+ #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
+ #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
+ #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
+ #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
+ #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
+ #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
+ #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
+ #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
+ #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
+ #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
+ #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
+ #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
+ #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
+ #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
+ #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
+ #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
+ #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
+ #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  EESIPR  ========================================================= */
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  TRSCER  ========================================================= */
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RMFCR  ========================================================= */
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  TFTR  ========================================================== */
+ #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
+/* ==========================================================  FDR  ========================================================== */
+ #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
+ #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
+ #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  RMCR  ========================================================== */
+ #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TFUCR  ========================================================= */
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  RFOCR  ========================================================= */
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  IOSR  ========================================================== */
+ #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
+/* =========================================================  FCFTR  ========================================================= */
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
+/* ========================================================  RPADIR  ========================================================= */
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
+/* =========================================================  TRIMD  ========================================================= */
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RBWAR  ========================================================= */
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  RDFAR  ========================================================= */
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  TBRAR  ========================================================= */
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  TDFAR  ========================================================= */
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
+
+/* =========================================================================================================================== */
+/* ================                                      R_ETHERC_EPTPC                                       ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SYSR  ========================================================== */
+ #define R_ETHERC_EPTPC_SYSR_GENDN_Pos             (17UL)         /*!< GENDN (Bit 17)                                        */
+ #define R_ETHERC_EPTPC_SYSR_GENDN_Msk             (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYSR_RESDN_Pos             (16UL)         /*!< RESDN (Bit 16)                                        */
+ #define R_ETHERC_EPTPC_SYSR_RESDN_Msk             (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYSR_INFABT_Pos            (14UL)         /*!< INFABT (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_SYSR_INFABT_Msk            (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYSR_RECLP_Pos             (12UL)         /*!< RECLP (Bit 12)                                        */
+ #define R_ETHERC_EPTPC_SYSR_RECLP_Msk             (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos            (6UL)          /*!< DRQOVR (Bit 6)                                        */
+ #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk            (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos            (5UL)          /*!< INTDEV (Bit 5)                                        */
+ #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk            (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos             (4UL)          /*!< DRPTO (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk             (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos             (2UL)          /*!< MPDUD (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk             (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos            (1UL)          /*!< INTCHG (Bit 1)                                        */
+ #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk            (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos             (0UL)          /*!< OFMUD (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk             (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SYIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos            (17UL)         /*!< GENDN (Bit 17)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk            (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos            (16UL)         /*!< RESDN (Bit 16)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk            (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos           (14UL)         /*!< INFABT (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk           (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos            (12UL)         /*!< RECLP (Bit 12)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk            (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos           (6UL)          /*!< DRQOVR (Bit 6)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk           (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos           (5UL)          /*!< INTDEV (Bit 5)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk           (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos            (4UL)          /*!< DRPTO (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk            (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos            (2UL)          /*!< MPDUD (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk            (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos           (1UL)          /*!< INTCHG (Bit 1)                                        */
+ #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk           (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos            (0UL)          /*!< OFMUD (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk            (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SYMACRU  ======================================================== */
+ #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos        (0UL)          /*!< SYMACRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk        (0xffffffUL)   /*!< SYMACRU (Bitfield-Mask: 0xffffff)                     */
+/* ========================================================  SYMACRL  ======================================================== */
+ #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos        (0UL)          /*!< SYMACRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk        (0xffffffUL)   /*!< SYMACRL (Bitfield-Mask: 0xffffff)                     */
+/* =======================================================  SYLLCCTLR  ======================================================= */
+ #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos          (0UL)          /*!< CTL (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk          (0xffUL)       /*!< CTL (Bitfield-Mask: 0xff)                             */
+/* =======================================================  SYIPADDRR  ======================================================= */
+ #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos    (0UL)          /*!< SYIPADDRR (Bit 0)                                     */
+ #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk    (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  SYSPVRR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos           (4UL)          /*!< TRSP (Bit 4)                                          */
+ #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk           (0xf0UL)       /*!< TRSP (Bitfield-Mask: 0x0f)                            */
+ #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk            (0xfUL)        /*!< VER (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  SYDOMR  ========================================================= */
+ #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos            (0UL)          /*!< DNUM (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk            (0xffUL)       /*!< DNUM (Bitfield-Mask: 0xff)                            */
+/* =========================================================  ANFR  ========================================================== */
+ #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos            (14UL)         /*!< FLAG14 (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk            (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos            (13UL)         /*!< FLAG13 (Bit 13)                                       */
+ #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk            (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos            (10UL)         /*!< FLAG10 (Bit 10)                                       */
+ #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk            (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos             (8UL)          /*!< FLAG8 (Bit 8)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk             (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos             (5UL)          /*!< FLAG5 (Bit 5)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk             (0x20UL)       /*!< FLAG5 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos             (4UL)          /*!< FLAG4 (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk             (0x10UL)       /*!< FLAG4 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos             (3UL)          /*!< FLAG3 (Bit 3)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk             (0x8UL)        /*!< FLAG3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos             (2UL)          /*!< FLAG2 (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk             (0x4UL)        /*!< FLAG2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos             (1UL)          /*!< FLAG1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk             (0x2UL)        /*!< FLAG1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos             (0UL)          /*!< FLAG0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk             (0x1UL)        /*!< FLAG0 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SYNFR  ========================================================= */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos           (14UL)         /*!< FLAG14 (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk           (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos           (13UL)         /*!< FLAG13 (Bit 13)                                       */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk           (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos           (10UL)         /*!< FLAG10 (Bit 10)                                       */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk           (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos            (9UL)          /*!< FLAG9 (Bit 9)                                         */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk            (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos            (8UL)          /*!< FLAG8 (Bit 8)                                         */
+ #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk            (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DYRQFR  ========================================================= */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
+ #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  DYRPFR  ========================================================= */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos           (9UL)          /*!< FLAG9 (Bit 9)                                         */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk           (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos           (8UL)          /*!< FLAG8 (Bit 8)                                         */
+ #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk           (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SYCIDRU  ======================================================== */
+ #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos        (0UL)          /*!< SYCIDRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk        (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  SYCIDRL  ======================================================== */
+ #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos        (0UL)          /*!< SYCIDRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk        (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  SYPNUMR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos           (0UL)          /*!< PNUM (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk           (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  SYRVLDR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos           (2UL)          /*!< ANUP (Bit 2)                                          */
+ #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk           (0x4UL)        /*!< ANUP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos           (1UL)          /*!< STUP (Bit 1)                                          */
+ #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk           (0x2UL)        /*!< STUP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos           (0UL)          /*!< BMUP (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk           (0x1UL)        /*!< BMUP (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SYRFL1R  ======================================================== */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos         (30UL)         /*!< PDFUP2 (Bit 30)                                       */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk         (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos         (29UL)         /*!< PDFUP1 (Bit 29)                                       */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk         (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos         (28UL)         /*!< PDFUP0 (Bit 28)                                       */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk         (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos          (26UL)         /*!< PDRP2 (Bit 26)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk          (0x4000000UL)  /*!< PDRP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos          (25UL)         /*!< PDRP1 (Bit 25)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk          (0x2000000UL)  /*!< PDRP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos          (24UL)         /*!< PDRP0 (Bit 24)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk          (0x1000000UL)  /*!< PDRP0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos          (22UL)         /*!< PDRQ2 (Bit 22)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk          (0x400000UL)   /*!< PDRQ2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos          (21UL)         /*!< PDRQ1 (Bit 21)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk          (0x200000UL)   /*!< PDRQ1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos          (20UL)         /*!< PDRQ0 (Bit 20)                                        */
+ #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk          (0x100000UL)   /*!< PDRQ0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos           (18UL)         /*!< DRP2 (Bit 18)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk           (0x40000UL)    /*!< DRP2 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos           (17UL)         /*!< DRP1 (Bit 17)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk           (0x20000UL)    /*!< DRP1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos           (16UL)         /*!< DRP0 (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk           (0x10000UL)    /*!< DRP0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos           (14UL)         /*!< DRQ2 (Bit 14)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk           (0x4000UL)     /*!< DRQ2 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos           (13UL)         /*!< DRQ1 (Bit 13)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk           (0x2000UL)     /*!< DRQ1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos           (12UL)         /*!< DRQ0 (Bit 12)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk           (0x1000UL)     /*!< DRQ0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos           (10UL)         /*!< FUP2 (Bit 10)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk           (0x400UL)      /*!< FUP2 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos           (9UL)          /*!< FUP1 (Bit 9)                                          */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk           (0x200UL)      /*!< FUP1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos           (8UL)          /*!< FUP0 (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk           (0x100UL)      /*!< FUP0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos          (6UL)          /*!< SYNC2 (Bit 6)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk          (0x40UL)       /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos          (5UL)          /*!< SYNC1 (Bit 5)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk          (0x20UL)       /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos          (4UL)          /*!< SYNC0 (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk          (0x10UL)       /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos          (1UL)          /*!< ANCE1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk          (0x2UL)        /*!< ANCE1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos          (0UL)          /*!< ANCE0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk          (0x1UL)        /*!< ANCE0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SYRFL2R  ======================================================== */
+ #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos           (29UL)         /*!< ILL1 (Bit 29)                                         */
+ #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk           (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos           (28UL)         /*!< ILL0 (Bit 28)                                         */
+ #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk           (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos           (5UL)          /*!< SIG1 (Bit 5)                                          */
+ #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk           (0x20UL)       /*!< SIG1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos           (4UL)          /*!< SIG0 (Bit 4)                                          */
+ #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk           (0x10UL)       /*!< SIG0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos           (1UL)          /*!< MAN1 (Bit 1)                                          */
+ #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk           (0x2UL)        /*!< MAN1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos           (0UL)          /*!< MAN0 (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk           (0x1UL)        /*!< MAN0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SYTRENR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos           (12UL)         /*!< PDRQ (Bit 12)                                         */
+ #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk           (0x1000UL)     /*!< PDRQ (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos            (8UL)          /*!< DRQ (Bit 8)                                           */
+ #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk            (0x100UL)      /*!< DRQ (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos           (4UL)          /*!< SYNC (Bit 4)                                          */
+ #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk           (0x10UL)       /*!< SYNC (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos           (0UL)          /*!< ANCE (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk           (0x1UL)        /*!< ANCE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  MTCIDU  ========================================================= */
+ #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos          (0UL)          /*!< MTCIDU (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk          (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MTCIDL  ========================================================= */
+ #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos          (0UL)          /*!< MTCIDL (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk          (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff)                    */
+/* =========================================================  MTPID  ========================================================= */
+ #define R_ETHERC_EPTPC_MTPID_PNUM_Pos             (0UL)          /*!< PNUM (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_MTPID_PNUM_Msk             (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  SYTLIR  ========================================================= */
+ #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos            (16UL)         /*!< DREQ (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk            (0xff0000UL)   /*!< DREQ (Bitfield-Mask: 0xff)                            */
+ #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
+ #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
+/* ========================================================  SYRLIR  ========================================================= */
+ #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos           (16UL)         /*!< DRESP (Bit 16)                                        */
+ #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk           (0xff0000UL)   /*!< DRESP (Bitfield-Mask: 0xff)                           */
+ #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
+ #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
+/* =========================================================  OFMRU  ========================================================= */
+ #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos            (0UL)          /*!< OFMRU (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk            (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  OFMRL  ========================================================= */
+ #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos            (0UL)          /*!< OFMRL (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk            (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  MPDRU  ========================================================= */
+ #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos            (0UL)          /*!< MPDRU (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk            (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  MPDRL  ========================================================= */
+ #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos            (0UL)          /*!< MPDRL (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk            (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GMPR  ========================================================== */
+ #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos             (16UL)         /*!< GMPR1 (Bit 16)                                        */
+ #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk             (0xff0000UL)   /*!< GMPR1 (Bitfield-Mask: 0xff)                           */
+ #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos             (0UL)          /*!< GMPR2 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk             (0xffUL)       /*!< GMPR2 (Bitfield-Mask: 0xff)                           */
+/* =========================================================  GMCQR  ========================================================= */
+ #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos            (0UL)          /*!< GMCQR (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk            (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  GMIDRU  ========================================================= */
+ #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos          (0UL)          /*!< GMIDRU (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk          (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  GMIDRL  ========================================================= */
+ #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos          (0UL)          /*!< GMIDRL (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk          (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  CUOTSR  ========================================================= */
+ #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos            (16UL)         /*!< CUTO (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk            (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos            (0UL)          /*!< TSRC (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk            (0xffUL)       /*!< TSRC (Bitfield-Mask: 0xff)                            */
+/* ==========================================================  SRR  ========================================================== */
+ #define R_ETHERC_EPTPC_SRR_SRMV_Pos               (0UL)          /*!< SRMV (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SRR_SRMV_Msk               (0xffffUL)     /*!< SRMV (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  PPMACRU  ======================================================== */
+ #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos        (0UL)          /*!< PPMACRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk        (0xffffffUL)   /*!< PPMACRU (Bitfield-Mask: 0xffffff)                     */
+/* ========================================================  PPMACRL  ======================================================== */
+ #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos        (0UL)          /*!< PPMACRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk        (0xffffffUL)   /*!< PPMACRL (Bitfield-Mask: 0xffffff)                     */
+/* ========================================================  PDMACRU  ======================================================== */
+ #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos        (0UL)          /*!< PDMACRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk        (0xffffffUL)   /*!< PDMACRU (Bitfield-Mask: 0xffffff)                     */
+/* ========================================================  PDMACRL  ======================================================== */
+ #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos        (0UL)          /*!< PDMACRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk        (0xffffffUL)   /*!< PDMACRL (Bitfield-Mask: 0xffffff)                     */
+/* ========================================================  PETYPER  ======================================================== */
+ #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos           (0UL)          /*!< TYPE (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk           (0xffffUL)     /*!< TYPE (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  PPIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos            (0UL)          /*!< PPIPR (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk            (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  PDIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos            (0UL)          /*!< PDIPR (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk            (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  PETOSR  ========================================================= */
+ #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos            (0UL)          /*!< EVTO (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk            (0xffUL)       /*!< EVTO (Bitfield-Mask: 0xff)                            */
+/* ========================================================  PGTOSR  ========================================================= */
+ #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos            (0UL)          /*!< GETO (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk            (0xffUL)       /*!< GETO (Bitfield-Mask: 0xff)                            */
+/* ========================================================  PPTTLR  ========================================================= */
+ #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos            (0UL)          /*!< PRTL (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk            (0xffUL)       /*!< PRTL (Bitfield-Mask: 0xff)                            */
+/* ========================================================  PDTTLR  ========================================================= */
+ #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos            (0UL)          /*!< PDTL (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk            (0xffUL)       /*!< PDTL (Bitfield-Mask: 0xff)                            */
+/* ========================================================  PEUDPR  ========================================================= */
+ #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos           (0UL)          /*!< EVUPT (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk           (0xffffUL)     /*!< EVUPT (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  PGUDPR  ========================================================= */
+ #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos           (0UL)          /*!< GEUPT (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk           (0xffffUL)     /*!< GEUPT (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  FFLTR  ========================================================= */
+ #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos           (16UL)         /*!< EXTPRM (Bit 16)                                       */
+ #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk           (0x10000UL)    /*!< EXTPRM (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_FFLTR_ENB_Pos              (2UL)          /*!< ENB (Bit 2)                                           */
+ #define R_ETHERC_EPTPC_FFLTR_ENB_Msk              (0x4UL)        /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_FFLTR_PRT_Pos              (1UL)          /*!< PRT (Bit 1)                                           */
+ #define R_ETHERC_EPTPC_FFLTR_PRT_Msk              (0x2UL)        /*!< PRT (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_FFLTR_SEL_Pos              (0UL)          /*!< SEL (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_FFLTR_SEL_Msk              (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DASYMRU  ======================================================== */
+ #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos        (0UL)          /*!< DASYMRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk        (0xffffUL)     /*!< DASYMRU (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DASYMRL  ======================================================== */
+ #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos        (0UL)          /*!< DASYMRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk        (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  TSLATR  ========================================================= */
+ #define R_ETHERC_EPTPC_TSLATR_INGP_Pos            (16UL)         /*!< INGP (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_TSLATR_INGP_Msk            (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff)                          */
+ #define R_ETHERC_EPTPC_TSLATR_EGP_Pos             (0UL)          /*!< EGP (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_TSLATR_EGP_Msk             (0xffffUL)     /*!< EGP (Bitfield-Mask: 0xffff)                           */
+/* ========================================================  SYCONFR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos          (20UL)         /*!< TCMOD (Bit 20)                                        */
+ #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk          (0x100000UL)   /*!< TCMOD (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos         (16UL)         /*!< FILDIS (Bit 16)                                       */
+ #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk         (0x10000UL)    /*!< FILDIS (Bitfield-Mask: 0x01)                          */
+ #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos          (12UL)         /*!< SBDIS (Bit 12)                                        */
+ #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk          (0x1000UL)     /*!< SBDIS (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos           (0UL)          /*!< TCYC (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk           (0xffUL)       /*!< TCYC (Bitfield-Mask: 0xff)                            */
+/* ========================================================  SYFORMR  ======================================================== */
+ #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos          (1UL)          /*!< FORM1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk          (0x2UL)        /*!< FORM1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos          (0UL)          /*!< FORM0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk          (0x1UL)        /*!< FORM0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  RSTOUTR  ======================================================== */
+ #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos        (0UL)          /*!< RSTOUTR (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk        (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff)                   */
+
+/* =========================================================================================================================== */
+/* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PTRSTR  ========================================================= */
+ #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos       (0UL)       /*!< RESET (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk       (0x1UL)     /*!< RESET (Bitfield-Mask: 0x01)                           */
+/* ========================================================  STCSELR  ======================================================== */
+ #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos    (8UL)       /*!< SCLKSEL (Bit 8)                                       */
+ #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk    (0x700UL)   /*!< SCLKSEL (Bitfield-Mask: 0x07)                         */
+ #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos    (0UL)       /*!< SCLKDIV (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk    (0x7UL)     /*!< SCLKDIV (Bitfield-Mask: 0x07)                         */
+/* ========================================================  BYPASS  ========================================================= */
+ #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos     (16UL)      /*!< BYPASS1 (Bit 16)                                      */
+ #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk     (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos     (0UL)       /*!< BYPASS0 (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk     (0x1UL)     /*!< BYPASS0 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  MIESR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos           (21UL)         /*!< CYC5 (Bit 21)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk           (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos           (20UL)         /*!< CYC4 (Bit 20)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk           (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos           (19UL)         /*!< CYC3 (Bit 19)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk           (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos           (18UL)         /*!< CYC2 (Bit 18)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk           (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos           (17UL)         /*!< CYC1 (Bit 17)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk           (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos           (16UL)         /*!< CYC0 (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk           (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos            (3UL)          /*!< PRC (Bit 3)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk            (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos            (2UL)          /*!< SY1 (Bit 2)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk            (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos            (1UL)          /*!< SY0 (Bit 1)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk            (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos             (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk             (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+/* ========================================================  MIEIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos          (21UL)         /*!< CYC5 (Bit 21)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk          (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos          (20UL)         /*!< CYC4 (Bit 20)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk          (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos          (19UL)         /*!< CYC3 (Bit 19)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk          (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos          (18UL)         /*!< CYC2 (Bit 18)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk          (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos          (17UL)         /*!< CYC1 (Bit 17)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk          (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos          (16UL)         /*!< CYC0 (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk          (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos           (3UL)          /*!< PRC (Bit 3)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk           (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos           (2UL)          /*!< SY1 (Bit 2)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk           (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos           (1UL)          /*!< SY0 (Bit 1)                                           */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk           (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos            (0UL)          /*!< ST (Bit 0)                                            */
+ #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk            (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
+/* ========================================================  ELIPPR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos          (24UL)         /*!< PLSN (Bit 24)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk          (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos          (16UL)         /*!< PLSP (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk          (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos         (13UL)         /*!< CYCN5 (Bit 13)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk         (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos         (12UL)         /*!< CYCN4 (Bit 12)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk         (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos         (11UL)         /*!< CYCN3 (Bit 11)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk         (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos         (10UL)         /*!< CYCN2 (Bit 10)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk         (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos         (9UL)          /*!< CYCN1 (Bit 9)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk         (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos         (8UL)          /*!< CYCN0 (Bit 8)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk         (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos         (5UL)          /*!< CYCP5 (Bit 5)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk         (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos         (4UL)          /*!< CYCP4 (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk         (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos         (3UL)          /*!< CYCP3 (Bit 3)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk         (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos         (2UL)          /*!< CYCP2 (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk         (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos         (1UL)          /*!< CYCP1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk         (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos         (0UL)          /*!< CYCP0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk         (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ELIPACR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos         (24UL)         /*!< PLSN (Bit 24)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk         (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos         (16UL)         /*!< PLSP (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk         (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos        (13UL)         /*!< CYCN5 (Bit 13)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk        (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos        (12UL)         /*!< CYCN4 (Bit 12)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk        (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos        (11UL)         /*!< CYCN3 (Bit 11)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk        (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos        (10UL)         /*!< CYCN2 (Bit 10)                                        */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk        (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos        (9UL)          /*!< CYCN1 (Bit 9)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk        (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos        (8UL)          /*!< CYCN0 (Bit 8)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk        (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos        (5UL)          /*!< CYCP5 (Bit 5)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk        (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos        (4UL)          /*!< CYCP4 (Bit 4)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk        (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos        (3UL)          /*!< CYCP3 (Bit 3)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk        (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos        (2UL)          /*!< CYCP2 (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk        (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos        (1UL)          /*!< CYCP1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk        (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos        (0UL)          /*!< CYCP0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk        (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  STSR  ========================================================== */
+ #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos            (4UL)          /*!< W10D (Bit 4)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk            (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos         (3UL)          /*!< SYNTOUT (Bit 3)                                       */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk         (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos         (1UL)          /*!< SYNCOUT (Bit 1)                                       */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk         (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos            (0UL)          /*!< SYNC (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk            (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos           (4UL)          /*!< W10D (Bit 4)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk           (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos        (3UL)          /*!< SYNTOUT (Bit 3)                                       */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk        (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos        (1UL)          /*!< SYNCOUT (Bit 1)                                       */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk        (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos           (0UL)          /*!< SYNC (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk           (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
+/* =========================================================  STCFR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos           (0UL)          /*!< STCF (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk           (0x3UL)        /*!< STCF (Bitfield-Mask: 0x03)                            */
+/* =========================================================  STMR  ========================================================== */
+ #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos           (29UL)         /*!< ALEN1 (Bit 29)                                        */
+ #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk           (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos           (28UL)         /*!< ALEN0 (Bit 28)                                        */
+ #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk           (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos            (20UL)         /*!< DVTH (Bit 20)                                         */
+ #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk            (0xf00000UL)   /*!< DVTH (Bitfield-Mask: 0x0f)                            */
+ #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos            (16UL)         /*!< SYTH (Bit 16)                                         */
+ #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk            (0xf0000UL)    /*!< SYTH (Bitfield-Mask: 0x0f)                            */
+ #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos            (15UL)         /*!< W10S (Bit 15)                                         */
+ #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk            (0x8000UL)     /*!< W10S (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos            (13UL)         /*!< CMOD (Bit 13)                                         */
+ #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk            (0x2000UL)     /*!< CMOD (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos            (0UL)          /*!< WINT (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk            (0xffUL)       /*!< WINT (Bitfield-Mask: 0xff)                            */
+/* ========================================================  SYNTOR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos        (0UL)          /*!< SYNTOR (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk        (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  IPTSELR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos      (5UL)          /*!< IPTSEL5 (Bit 5)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk      (0x20UL)       /*!< IPTSEL5 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos      (4UL)          /*!< IPTSEL4 (Bit 4)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk      (0x10UL)       /*!< IPTSEL4 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos      (3UL)          /*!< IPTSEL3 (Bit 3)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk      (0x8UL)        /*!< IPTSEL3 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos      (2UL)          /*!< IPTSEL2 (Bit 2)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk      (0x4UL)        /*!< IPTSEL2 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos      (1UL)          /*!< IPTSEL1 (Bit 1)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk      (0x2UL)        /*!< IPTSEL1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos      (0UL)          /*!< IPTSEL0 (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk      (0x1UL)        /*!< IPTSEL0 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MITSELR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos      (5UL)          /*!< MINTEN5 (Bit 5)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk      (0x20UL)       /*!< MINTEN5 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos      (4UL)          /*!< MINTEN4 (Bit 4)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk      (0x10UL)       /*!< MINTEN4 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos      (3UL)          /*!< MINTEN3 (Bit 3)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk      (0x8UL)        /*!< MINTEN3 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos      (2UL)          /*!< MINTEN2 (Bit 2)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk      (0x4UL)        /*!< MINTEN2 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos      (1UL)          /*!< MINTEN1 (Bit 1)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk      (0x2UL)        /*!< MINTEN1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos      (0UL)          /*!< MINTEN0 (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk      (0x1UL)        /*!< MINTEN0 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ELTSELR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos      (5UL)          /*!< ELTDIS5 (Bit 5)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk      (0x20UL)       /*!< ELTDIS5 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos      (4UL)          /*!< ELTDIS4 (Bit 4)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk      (0x10UL)       /*!< ELTDIS4 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos      (3UL)          /*!< ELTDIS3 (Bit 3)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk      (0x8UL)        /*!< ELTDIS3 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos      (2UL)          /*!< ELTDIS2 (Bit 2)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk      (0x4UL)        /*!< ELTDIS2 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos      (1UL)          /*!< ELTDIS1 (Bit 1)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk      (0x2UL)        /*!< ELTDIS1 (Bitfield-Mask: 0x01)                         */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos      (0UL)          /*!< ELTDIS0 (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk      (0x1UL)        /*!< ELTDIS0 (Bitfield-Mask: 0x01)                         */
+/* =======================================================  STCHSELR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos       (0UL)          /*!< SYSEL (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk       (0x1UL)        /*!< SYSEL (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SYNSTARTR  ======================================================= */
+ #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos        (0UL)          /*!< STR (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk        (0x1UL)        /*!< STR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LCIVLDR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos         (0UL)          /*!< LOAD (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk         (0x1UL)        /*!< LOAD (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SYNTDARU  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos    (0UL)          /*!< SYNTDARU (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk    (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  SYNTDARL  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos    (0UL)          /*!< SYNTDARL (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk    (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  SYNTDBRU  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos    (0UL)          /*!< SYNTDBRU (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk    (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  SYNTDBRL  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos    (0UL)          /*!< SYNTDBRL (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk    (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  LCIVRU  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos        (0UL)          /*!< LCIVRU (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk        (0xffffUL)     /*!< LCIVRU (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  LCIVRM  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos        (0UL)          /*!< LCIVRM (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk        (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  LCIVRL  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos        (0UL)          /*!< LCIVRL (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk        (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  GETW10R  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos         (0UL)          /*!< GW10 (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk         (0x1UL)        /*!< GW10 (Bitfield-Mask: 0x01)                            */
+/* =======================================================  PLIMITRU  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos    (0UL)          /*!< PLIMITRU (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk    (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
+/* =======================================================  PLIMITRM  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos    (0UL)          /*!< PLIMITRM (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk    (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  PLIMITRL  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos    (0UL)          /*!< PLIMITRL (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk    (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  MLIMITRU  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos    (0UL)          /*!< MLIMITRU (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk    (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
+/* =======================================================  MLIMITRM  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos    (0UL)          /*!< MLIMITRM (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk    (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  MLIMITRL  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos    (0UL)          /*!< MLIMITRL (Bit 0)                                      */
+ #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk    (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GETINFOR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos        (0UL)          /*!< INFO (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk        (0x1UL)        /*!< INFO (Bitfield-Mask: 0x01)                            */
+/* ========================================================  LCCVRU  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos        (0UL)          /*!< LCCVRU (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk        (0xffffUL)     /*!< LCCVRU (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  LCCVRM  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos        (0UL)          /*!< LCCVRM (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk        (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  LCCVRL  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos        (0UL)          /*!< LCCVRL (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk        (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  PW10VRU  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos      (0UL)          /*!< PW10VRU (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk      (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  PW10VRM  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos      (0UL)          /*!< PW10VRM (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk      (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  PW10VRL  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos      (0UL)          /*!< PW10VRL (Bit 0)                                       */
+ #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk      (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  MW10RU  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos        (0UL)          /*!< MW10RU (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk        (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MW10RM  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos        (0UL)          /*!< MW10RM (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk        (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  MW10RL  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos        (0UL)          /*!< MW10RL (Bit 0)                                        */
+ #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk        (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  TMSTARTR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos         (5UL)          /*!< EN5 (Bit 5)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk         (0x20UL)       /*!< EN5 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos         (4UL)          /*!< EN4 (Bit 4)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk         (0x10UL)       /*!< EN4 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos         (3UL)          /*!< EN3 (Bit 3)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk         (0x8UL)        /*!< EN3 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos         (2UL)          /*!< EN2 (Bit 2)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk         (0x4UL)        /*!< EN2 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos         (1UL)          /*!< EN1 (Bit 1)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk         (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos         (0UL)          /*!< EN0 (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk         (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PRSR  ========================================================== */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos            (29UL)         /*!< URE1 (Bit 29)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk            (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos            (28UL)         /*!< URE0 (Bit 28)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk            (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos            (8UL)          /*!< MACE (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk            (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos           (3UL)          /*!< OVRE3 (Bit 3)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk           (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos           (2UL)          /*!< OVRE2 (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk           (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos           (1UL)          /*!< OVRE1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk           (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos           (0UL)          /*!< OVRE0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk           (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  PRIPR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos           (29UL)         /*!< URE1 (Bit 29)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk           (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos           (28UL)         /*!< URE0 (Bit 28)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk           (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos           (8UL)          /*!< MACE (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk           (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos          (3UL)          /*!< OVRE3 (Bit 3)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk          (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos          (2UL)          /*!< OVRE2 (Bit 2)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk          (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos          (1UL)          /*!< OVRE1 (Bit 1)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk          (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos          (0UL)          /*!< OVRE0 (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk          (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
+/* ========================================================  TRNDISR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos         (0UL)          /*!< TDIS (Bit 0)                                          */
+ #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk         (0x3UL)        /*!< TDIS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  TRNMR  ========================================================= */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos           (9UL)          /*!< FWD1 (Bit 9)                                          */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk           (0x200UL)      /*!< FWD1 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos           (8UL)          /*!< FWD0 (Bit 8)                                          */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk           (0x100UL)      /*!< FWD0 (Bitfield-Mask: 0x01)                            */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos            (0UL)          /*!< MOD (Bit 0)                                           */
+ #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk            (0x1UL)        /*!< MOD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  TRNCTTDR  ======================================================== */
+ #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos       (0UL)          /*!< THVAL (Bit 0)                                         */
+ #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk       (0x7ffUL)      /*!< THVAL (Bitfield-Mask: 0x7ff)                          */
+
+/* =========================================================================================================================== */
+/* ================                                       R_FACI_HP_CMD                                       ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================  FACI_CMD16  ======================================================= */
+/* =======================================================  FACI_CMD8  ======================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_HP                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FASTAT  ========================================================= */
+ #define R_FACI_HP_FASTAT_CFAE_Pos        (7UL)          /*!< CFAE (Bit 7)                                          */
+ #define R_FACI_HP_FASTAT_CFAE_Msk        (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FASTAT_CMDLK_Pos       (4UL)          /*!< CMDLK (Bit 4)                                         */
+ #define R_FACI_HP_FASTAT_CMDLK_Msk       (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FASTAT_DFAE_Pos        (3UL)          /*!< DFAE (Bit 3)                                          */
+ #define R_FACI_HP_FASTAT_DFAE_Msk        (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FASTAT_ECRCT_Pos       (0UL)          /*!< ECRCT (Bit 0)                                         */
+ #define R_FACI_HP_FASTAT_ECRCT_Msk       (0x1UL)        /*!< ECRCT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FAEINT  ========================================================= */
+ #define R_FACI_HP_FAEINT_CFAEIE_Pos      (7UL)          /*!< CFAEIE (Bit 7)                                        */
+ #define R_FACI_HP_FAEINT_CFAEIE_Msk      (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Pos     (4UL)          /*!< CMDLKIE (Bit 4)                                       */
+ #define R_FACI_HP_FAEINT_CMDLKIE_Msk     (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FAEINT_DFAEIE_Pos      (3UL)          /*!< DFAEIE (Bit 3)                                        */
+ #define R_FACI_HP_FAEINT_DFAEIE_Msk      (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FAEINT_ECRCTIE_Pos     (0UL)          /*!< ECRCTIE (Bit 0)                                       */
+ #define R_FACI_HP_FAEINT_ECRCTIE_Msk     (0x1UL)        /*!< ECRCTIE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FRDYIE  ========================================================= */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Pos      (0UL)          /*!< FRDYIE (Bit 0)                                        */
+ #define R_FACI_HP_FRDYIE_FRDYIE_Msk      (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FSADDR  ========================================================= */
+ #define R_FACI_HP_FSADDR_FSA_Pos         (0UL)          /*!< FSA (Bit 0)                                           */
+ #define R_FACI_HP_FSADDR_FSA_Msk         (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FEADDR  ========================================================= */
+ #define R_FACI_HP_FEADDR_FEA_Pos         (0UL)          /*!< FEA (Bit 0)                                           */
+ #define R_FACI_HP_FEADDR_FEA_Msk         (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  FSTATR  ========================================================= */
+ #define R_FACI_HP_FSTATR_EBFULL_Pos      (18UL)         /*!< EBFULL (Bit 18)                                       */
+ #define R_FACI_HP_FSTATR_EBFULL_Msk      (0x40000UL)    /*!< EBFULL (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_OTPDTCT_Pos     (17UL)         /*!< OTPDTCT (Bit 17)                                      */
+ #define R_FACI_HP_FSTATR_OTPDTCT_Msk     (0x20000UL)    /*!< OTPDTCT (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_OTPCRCT_Pos     (16UL)         /*!< OTPCRCT (Bit 16)                                      */
+ #define R_FACI_HP_FSTATR_OTPCRCT_Msk     (0x10000UL)    /*!< OTPCRCT (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_FRDY_Pos        (15UL)         /*!< FRDY (Bit 15)                                         */
+ #define R_FACI_HP_FSTATR_FRDY_Msk        (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FSTATR_ILGLERR_Pos     (14UL)         /*!< ILGLERR (Bit 14)                                      */
+ #define R_FACI_HP_FSTATR_ILGLERR_Msk     (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_ERSERR_Pos      (13UL)         /*!< ERSERR (Bit 13)                                       */
+ #define R_FACI_HP_FSTATR_ERSERR_Msk      (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGERR_Pos      (12UL)         /*!< PRGERR (Bit 12)                                       */
+ #define R_FACI_HP_FSTATR_PRGERR_Msk      (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_SUSRDY_Pos      (11UL)         /*!< SUSRDY (Bit 11)                                       */
+ #define R_FACI_HP_FSTATR_SUSRDY_Msk      (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_DBFULL_Pos      (10UL)         /*!< DBFULL (Bit 10)                                       */
+ #define R_FACI_HP_FSTATR_DBFULL_Msk      (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_ERSSPD_Pos      (9UL)          /*!< ERSSPD (Bit 9)                                        */
+ #define R_FACI_HP_FSTATR_ERSSPD_Msk      (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_PRGSPD_Pos      (8UL)          /*!< PRGSPD (Bit 8)                                        */
+ #define R_FACI_HP_FSTATR_PRGSPD_Msk      (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_FCUERR_Pos      (7UL)          /*!< FCUERR (Bit 7)                                        */
+ #define R_FACI_HP_FSTATR_FCUERR_Msk      (0x80UL)       /*!< FCUERR (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_HP_FSTATR_FHVEERR_Pos     (6UL)          /*!< FHVEERR (Bit 6)                                       */
+ #define R_FACI_HP_FSTATR_FHVEERR_Msk     (0x40UL)       /*!< FHVEERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_CFGDTCT_Pos     (5UL)          /*!< CFGDTCT (Bit 5)                                       */
+ #define R_FACI_HP_FSTATR_CFGDTCT_Msk     (0x20UL)       /*!< CFGDTCT (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_CFGCRCT_Pos     (4UL)          /*!< CFGCRCT (Bit 4)                                       */
+ #define R_FACI_HP_FSTATR_CFGCRCT_Msk     (0x10UL)       /*!< CFGCRCT (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_TBLDTCT_Pos     (3UL)          /*!< TBLDTCT (Bit 3)                                       */
+ #define R_FACI_HP_FSTATR_TBLDTCT_Msk     (0x8UL)        /*!< TBLDTCT (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FSTATR_TBLCRCT_Pos     (2UL)          /*!< TBLCRCT (Bit 2)                                       */
+ #define R_FACI_HP_FSTATR_TBLCRCT_Msk     (0x4UL)        /*!< TBLCRCT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FENTRYR  ======================================================== */
+ #define R_FACI_HP_FENTRYR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FENTRYR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Pos    (7UL)          /*!< FENTRYD (Bit 7)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYD_Msk    (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Pos    (0UL)          /*!< FENTRYC (Bit 0)                                       */
+ #define R_FACI_HP_FENTRYR_FENTRYC_Msk    (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
+/* =======================================================  FSUINITR  ======================================================== */
+ #define R_FACI_HP_FSUINITR_KEY_Pos       (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUINITR_KEY_Msk       (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUINITR_SUINIT_Pos    (0UL)          /*!< SUINIT (Bit 0)                                        */
+ #define R_FACI_HP_FSUINITR_SUINIT_Msk    (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FCMDR  ========================================================= */
+ #define R_FACI_HP_FCMDR_CMDR_Pos         (8UL)          /*!< CMDR (Bit 8)                                          */
+ #define R_FACI_HP_FCMDR_CMDR_Msk         (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
+ #define R_FACI_HP_FCMDR_PCMDR_Pos        (0UL)          /*!< PCMDR (Bit 0)                                         */
+ #define R_FACI_HP_FCMDR_PCMDR_Msk        (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
+/* ========================================================  FPESTAT  ======================================================== */
+ #define R_FACI_HP_FPESTAT_PEERRST_Pos    (0UL)          /*!< PEERRST (Bit 0)                                       */
+ #define R_FACI_HP_FPESTAT_PEERRST_Msk    (0xffUL)       /*!< PEERRST (Bitfield-Mask: 0xff)                         */
+/* ========================================================  FBCCNT  ========================================================= */
+ #define R_FACI_HP_FBCCNT_BCDIR_Pos       (0UL)          /*!< BCDIR (Bit 0)                                         */
+ #define R_FACI_HP_FBCCNT_BCDIR_Msk       (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FBCSTAT  ======================================================== */
+ #define R_FACI_HP_FBCSTAT_BCST_Pos       (0UL)          /*!< BCST (Bit 0)                                          */
+ #define R_FACI_HP_FBCSTAT_BCST_Msk       (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  FPSADDR  ======================================================== */
+ #define R_FACI_HP_FPSADDR_PSADR_Pos      (0UL)          /*!< PSADR (Bit 0)                                         */
+ #define R_FACI_HP_FPSADDR_PSADR_Msk      (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
+/* ========================================================  FAWMON  ========================================================= */
+ #define R_FACI_HP_FAWMON_BTFLG_Pos       (31UL)         /*!< BTFLG (Bit 31)                                        */
+ #define R_FACI_HP_FAWMON_BTFLG_Msk       (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_HP_FAWMON_FAWE_Pos        (16UL)         /*!< FAWE (Bit 16)                                         */
+ #define R_FACI_HP_FAWMON_FAWE_Msk        (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
+ #define R_FACI_HP_FAWMON_FSPR_Pos        (15UL)         /*!< FSPR (Bit 15)                                         */
+ #define R_FACI_HP_FAWMON_FSPR_Msk        (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_HP_FAWMON_FAWS_Pos        (0UL)          /*!< FAWS (Bit 0)                                          */
+ #define R_FACI_HP_FAWMON_FAWS_Msk        (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
+/* =========================================================  FCPSR  ========================================================= */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Pos      (0UL)          /*!< ESUSPMD (Bit 0)                                       */
+ #define R_FACI_HP_FCPSR_ESUSPMD_Msk      (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
+/* ========================================================  FPCKAR  ========================================================= */
+ #define R_FACI_HP_FPCKAR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FPCKAR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FPCKAR_PCKA_Pos        (0UL)          /*!< PCKA (Bit 0)                                          */
+ #define R_FACI_HP_FPCKAR_PCKA_Msk        (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
+/* ========================================================  FSUACR  ========================================================= */
+ #define R_FACI_HP_FSUACR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
+ #define R_FACI_HP_FSUACR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_FACI_HP_FSUACR_SAS_Pos         (0UL)          /*!< SAS (Bit 0)                                           */
+ #define R_FACI_HP_FSUACR_SAS_Msk         (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FACI_LP                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  DFLCTL  ========================================================= */
+/* =========================================================  FPMCR  ========================================================= */
+ #define R_FACI_LP_FPMCR_FMS2_Pos           (7UL)      /*!< FMS2 (Bit 7)                                          */
+ #define R_FACI_LP_FPMCR_FMS2_Msk           (0x80UL)   /*!< FMS2 (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FPMCR_VLPE_Pos           (6UL)      /*!< VLPE (Bit 6)                                          */
+ #define R_FACI_LP_FPMCR_VLPE_Msk           (0x40UL)   /*!< VLPE (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FPMCR_FMS1_Pos           (4UL)      /*!< FMS1 (Bit 4)                                          */
+ #define R_FACI_LP_FPMCR_FMS1_Msk           (0x10UL)   /*!< FMS1 (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FPMCR_RPDIS_Pos          (3UL)      /*!< RPDIS (Bit 3)                                         */
+ #define R_FACI_LP_FPMCR_RPDIS_Msk          (0x8UL)    /*!< RPDIS (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_LP_FPMCR_FMS0_Pos           (1UL)      /*!< FMS0 (Bit 1)                                          */
+ #define R_FACI_LP_FPMCR_FMS0_Msk           (0x2UL)    /*!< FMS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FASR  ========================================================== */
+ #define R_FACI_LP_FASR_EXS_Pos             (0UL)      /*!< EXS (Bit 0)                                           */
+ #define R_FACI_LP_FASR_EXS_Msk             (0x1UL)    /*!< EXS (Bitfield-Mask: 0x01)                             */
+/* =========================================================  FSARL  ========================================================= */
+ #define R_FACI_LP_FSARL_FSAR15_0_Pos       (0UL)      /*!< FSAR15_0 (Bit 0)                                      */
+ #define R_FACI_LP_FSARL_FSAR15_0_Msk       (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff)                      */
+/* =========================================================  FSARH  ========================================================= */
+ #define R_FACI_LP_FSARH_FSAR31_25_Pos      (9UL)      /*!< FSAR31_25 (Bit 9)                                     */
+ #define R_FACI_LP_FSARH_FSAR31_25_Msk      (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f)                       */
+ #define R_FACI_LP_FSARH_FSAR20_16_Pos      (0UL)      /*!< FSAR20_16 (Bit 0)                                     */
+ #define R_FACI_LP_FSARH_FSAR20_16_Msk      (0x1fUL)   /*!< FSAR20_16 (Bitfield-Mask: 0x1f)                       */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_FACI_LP_FCR_OPST_Pos             (7UL)      /*!< OPST (Bit 7)                                          */
+ #define R_FACI_LP_FCR_OPST_Msk             (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FCR_STOP_Pos             (6UL)      /*!< STOP (Bit 6)                                          */
+ #define R_FACI_LP_FCR_STOP_Msk             (0x40UL)   /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FCR_DRC_Pos              (4UL)      /*!< DRC (Bit 4)                                           */
+ #define R_FACI_LP_FCR_DRC_Msk              (0x10UL)   /*!< DRC (Bitfield-Mask: 0x01)                             */
+ #define R_FACI_LP_FCR_CMD_Pos              (0UL)      /*!< CMD (Bit 0)                                           */
+ #define R_FACI_LP_FCR_CMD_Msk              (0xfUL)    /*!< CMD (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  FEARL  ========================================================= */
+ #define R_FACI_LP_FEARL_FEAR15_0_Pos       (0UL)      /*!< FEAR15_0 (Bit 0)                                      */
+ #define R_FACI_LP_FEARL_FEAR15_0_Msk       (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff)                      */
+/* =========================================================  FEARH  ========================================================= */
+ #define R_FACI_LP_FEARH_FEAR31_25_Pos      (9UL)      /*!< FEAR31_25 (Bit 9)                                     */
+ #define R_FACI_LP_FEARH_FEAR31_25_Msk      (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f)                       */
+ #define R_FACI_LP_FEARH_FEAR20_16_Pos      (0UL)      /*!< FEAR20_16 (Bit 0)                                     */
+ #define R_FACI_LP_FEARH_FEAR20_16_Msk      (0x1fUL)   /*!< FEAR20_16 (Bitfield-Mask: 0x1f)                       */
+/* ========================================================  FRESETR  ======================================================== */
+ #define R_FACI_LP_FRESETR_FRESET_Pos       (0UL)      /*!< FRESET (Bit 0)                                        */
+ #define R_FACI_LP_FRESETR_FRESET_Msk       (0x1UL)    /*!< FRESET (Bitfield-Mask: 0x01)                          */
+/* =======================================================  FSTATR00  ======================================================== */
+ #define R_FACI_LP_FSTATR00_EILGLERR_Pos    (5UL)      /*!< EILGLERR (Bit 5)                                      */
+ #define R_FACI_LP_FSTATR00_EILGLERR_Msk    (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_LP_FSTATR00_ILGLERR_Pos     (4UL)      /*!< ILGLERR (Bit 4)                                       */
+ #define R_FACI_LP_FSTATR00_ILGLERR_Msk     (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_LP_FSTATR00_BCERR0_Pos      (3UL)      /*!< BCERR0 (Bit 3)                                        */
+ #define R_FACI_LP_FSTATR00_BCERR0_Msk      (0x8UL)    /*!< BCERR0 (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_LP_FSTATR00_PRGERR01_Pos    (2UL)      /*!< PRGERR01 (Bit 2)                                      */
+ #define R_FACI_LP_FSTATR00_PRGERR01_Msk    (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_LP_FSTATR00_PRGERR0_Pos     (1UL)      /*!< PRGERR0 (Bit 1)                                       */
+ #define R_FACI_LP_FSTATR00_PRGERR0_Msk     (0x2UL)    /*!< PRGERR0 (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_LP_FSTATR00_ERERR0_Pos      (0UL)      /*!< ERERR0 (Bit 0)                                        */
+ #define R_FACI_LP_FSTATR00_ERERR0_Msk      (0x1UL)    /*!< ERERR0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  FSTATR1  ======================================================== */
+ #define R_FACI_LP_FSTATR1_EXRDY_Pos        (7UL)      /*!< EXRDY (Bit 7)                                         */
+ #define R_FACI_LP_FSTATR1_EXRDY_Msk        (0x80UL)   /*!< EXRDY (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_LP_FSTATR1_FRDY_Pos         (6UL)      /*!< FRDY (Bit 6)                                          */
+ #define R_FACI_LP_FSTATR1_FRDY_Msk         (0x40UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FSTATR1_DRRDY_Pos        (1UL)      /*!< DRRDY (Bit 1)                                         */
+ #define R_FACI_LP_FSTATR1_DRRDY_Msk        (0x2UL)    /*!< DRRDY (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FWBL0  ========================================================= */
+ #define R_FACI_LP_FWBL0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
+ #define R_FACI_LP_FWBL0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  FWBH0  ========================================================= */
+ #define R_FACI_LP_FWBH0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
+ #define R_FACI_LP_FWBH0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
+/* =======================================================  FSTATR01  ======================================================== */
+ #define R_FACI_LP_FSTATR01_BCERR1_Pos      (3UL)      /*!< BCERR1 (Bit 3)                                        */
+ #define R_FACI_LP_FSTATR01_BCERR1_Msk      (0x8UL)    /*!< BCERR1 (Bitfield-Mask: 0x01)                          */
+ #define R_FACI_LP_FSTATR01_PRGERR1_Pos     (1UL)      /*!< PRGERR1 (Bit 1)                                       */
+ #define R_FACI_LP_FSTATR01_PRGERR1_Msk     (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_LP_FSTATR01_ERERR1_Pos      (0UL)      /*!< ERERR1 (Bit 0)                                        */
+ #define R_FACI_LP_FSTATR01_ERERR1_Msk      (0x1UL)    /*!< ERERR1 (Bitfield-Mask: 0x01)                          */
+/* =========================================================  FWBL1  ========================================================= */
+ #define R_FACI_LP_FWBL1_WDATA47_32_Pos     (0UL)      /*!< WDATA47_32 (Bit 0)                                    */
+ #define R_FACI_LP_FWBL1_WDATA47_32_Msk     (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff)                    */
+/* =========================================================  FWBH1  ========================================================= */
+ #define R_FACI_LP_FWBH1_WDATA63_48_Pos     (0UL)      /*!< WDATA63_48 (Bit 0)                                    */
+ #define R_FACI_LP_FWBH1_WDATA63_48_Msk     (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff)                    */
+/* =========================================================  FRBL1  ========================================================= */
+ #define R_FACI_LP_FRBL1_RDATA47_32_Pos     (0UL)      /*!< RDATA47_32 (Bit 0)                                    */
+ #define R_FACI_LP_FRBL1_RDATA47_32_Msk     (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff)                    */
+/* =========================================================  FRBH1  ========================================================= */
+ #define R_FACI_LP_FRBH1_RDATA63_48_Pos     (0UL)      /*!< RDATA63_48 (Bit 0)                                    */
+ #define R_FACI_LP_FRBH1_RDATA63_48_Msk     (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff)                    */
+/* ==========================================================  FPR  ========================================================== */
+ #define R_FACI_LP_FPR_FPR_Pos              (0UL)      /*!< FPR (Bit 0)                                           */
+ #define R_FACI_LP_FPR_FPR_Msk              (0xffUL)   /*!< FPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  FPSR  ========================================================== */
+ #define R_FACI_LP_FPSR_PERR_Pos            (0UL)      /*!< PERR (Bit 0)                                          */
+ #define R_FACI_LP_FPSR_PERR_Msk            (0x1UL)    /*!< PERR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  FRBL0  ========================================================= */
+ #define R_FACI_LP_FRBL0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
+ #define R_FACI_LP_FRBL0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  FRBH0  ========================================================= */
+ #define R_FACI_LP_FRBH0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
+ #define R_FACI_LP_FRBH0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
+/* =========================================================  FSCMR  ========================================================= */
+ #define R_FACI_LP_FSCMR_FSPR_Pos           (14UL)     /*!< FSPR (Bit 14)                                         */
+ #define R_FACI_LP_FSCMR_FSPR_Msk           (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FSCMR_SASMF_Pos          (8UL)      /*!< SASMF (Bit 8)                                         */
+ #define R_FACI_LP_FSCMR_SASMF_Msk          (0x100UL)  /*!< SASMF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FAWSMR  ========================================================= */
+ #define R_FACI_LP_FAWSMR_FAWS_Pos          (0UL)      /*!< FAWS (Bit 0)                                          */
+ #define R_FACI_LP_FAWSMR_FAWS_Msk          (0xfffUL)  /*!< FAWS (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  FAWEMR  ========================================================= */
+ #define R_FACI_LP_FAWEMR_FAWE_Pos          (0UL)      /*!< FAWE (Bit 0)                                          */
+ #define R_FACI_LP_FAWEMR_FAWE_Msk          (0xfffUL)  /*!< FAWE (Bitfield-Mask: 0xfff)                           */
+/* =========================================================  FISR  ========================================================== */
+ #define R_FACI_LP_FISR_SAS_Pos             (6UL)      /*!< SAS (Bit 6)                                           */
+ #define R_FACI_LP_FISR_SAS_Msk             (0xc0UL)   /*!< SAS (Bitfield-Mask: 0x03)                             */
+ #define R_FACI_LP_FISR_PCKA_Pos            (0UL)      /*!< PCKA (Bit 0)                                          */
+ #define R_FACI_LP_FISR_PCKA_Msk            (0x3fUL)   /*!< PCKA (Bitfield-Mask: 0x3f)                            */
+/* =========================================================  FEXCR  ========================================================= */
+ #define R_FACI_LP_FEXCR_OPST_Pos           (7UL)      /*!< OPST (Bit 7)                                          */
+ #define R_FACI_LP_FEXCR_OPST_Msk           (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
+ #define R_FACI_LP_FEXCR_CMD_Pos            (0UL)      /*!< CMD (Bit 0)                                           */
+ #define R_FACI_LP_FEXCR_CMD_Msk            (0x7UL)    /*!< CMD (Bitfield-Mask: 0x07)                             */
+/* =========================================================  FEAML  ========================================================= */
+ #define R_FACI_LP_FEAML_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
+ #define R_FACI_LP_FEAML_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  FEAMH  ========================================================= */
+ #define R_FACI_LP_FEAMH_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
+ #define R_FACI_LP_FEAMH_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
+/* ========================================================  FSTATR2  ======================================================== */
+ #define R_FACI_LP_FSTATR2_EILGLERR_Pos     (5UL)      /*!< EILGLERR (Bit 5)                                      */
+ #define R_FACI_LP_FSTATR2_EILGLERR_Msk     (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_LP_FSTATR2_ILGLERR_Pos      (4UL)      /*!< ILGLERR (Bit 4)                                       */
+ #define R_FACI_LP_FSTATR2_ILGLERR_Msk      (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_LP_FSTATR2_BCERR_Pos        (3UL)      /*!< BCERR (Bit 3)                                         */
+ #define R_FACI_LP_FSTATR2_BCERR_Msk        (0x8UL)    /*!< BCERR (Bitfield-Mask: 0x01)                           */
+ #define R_FACI_LP_FSTATR2_PRGERR01_Pos     (2UL)      /*!< PRGERR01 (Bit 2)                                      */
+ #define R_FACI_LP_FSTATR2_PRGERR01_Msk     (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
+ #define R_FACI_LP_FSTATR2_PRGERR1_Pos      (1UL)      /*!< PRGERR1 (Bit 1)                                       */
+ #define R_FACI_LP_FSTATR2_PRGERR1_Msk      (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
+ #define R_FACI_LP_FSTATR2_ERERR_Pos        (0UL)      /*!< ERERR (Bit 0)                                         */
+ #define R_FACI_LP_FSTATR2_ERERR_Msk        (0x1UL)    /*!< ERERR (Bitfield-Mask: 0x01)                           */
+/* ======================================================  FENTRYR_MF4  ====================================================== */
+/* ========================================================  FENTRYR  ======================================================== */
+/* ========================================================  FLWAITR  ======================================================== */
+/* =========================================================  PFBER  ========================================================= */
+
+/* =========================================================================================================================== */
+/* ================                                         R_FCACHE                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  FCACHEE  ======================================================== */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)   /*!< FCACHEEN (Bit 0)                                      */
+ #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  FCACHEIV  ======================================================== */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)   /*!< FCACHEIV (Bit 0)                                      */
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
+/* =========================================================  FLWT  ========================================================== */
+ #define R_FCACHE_FLWT_FLWT_Pos            (0UL)   /*!< FLWT (Bit 0)                                          */
+ #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GLCDC                                          ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  GR1_CLUT0  ======================================================= */
+ #define R_GLCDC_GR1_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
+ #define R_GLCDC_GR1_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
+ #define R_GLCDC_GR1_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
+ #define R_GLCDC_GR1_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
+ #define R_GLCDC_GR1_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
+/* =======================================================  GR1_CLUT1  ======================================================= */
+ #define R_GLCDC_GR1_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
+ #define R_GLCDC_GR1_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
+ #define R_GLCDC_GR1_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
+ #define R_GLCDC_GR1_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR1_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
+ #define R_GLCDC_GR1_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
+/* =======================================================  GR2_CLUT0  ======================================================= */
+ #define R_GLCDC_GR2_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
+ #define R_GLCDC_GR2_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
+ #define R_GLCDC_GR2_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
+ #define R_GLCDC_GR2_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
+ #define R_GLCDC_GR2_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
+/* =======================================================  GR2_CLUT1  ======================================================= */
+ #define R_GLCDC_GR2_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
+ #define R_GLCDC_GR2_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
+ #define R_GLCDC_GR2_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
+ #define R_GLCDC_GR2_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
+ #define R_GLCDC_GR2_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
+ #define R_GLCDC_GR2_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
+
+/* =========================================================================================================================== */
+/* ================                                          R_GPT0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  GTWP  ========================================================== */
+ #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
+ #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
+/* =========================================================  GTSTR  ========================================================= */
+ #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
+ #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTSTP  ========================================================= */
+ #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
+ #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  GTCLR  ========================================================= */
+ #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
+ #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTSSR  ========================================================= */
+ #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
+ #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
+ #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTPSR  ========================================================= */
+ #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
+ #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
+ #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCSR  ========================================================= */
+ #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
+ #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
+ #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTUPSR  ========================================================= */
+ #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
+ #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
+ #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
+ #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTDNSR  ========================================================= */
+ #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
+ #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICASR  ======================================================== */
+ #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
+ #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  GTICBSR  ======================================================== */
+ #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
+ #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
+ #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
+ #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
+ #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
+ #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
+ #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
+ #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  GTCR  ========================================================== */
+ #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
+ #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
+ #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
+ #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
+ #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
+ #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
+/* =======================================================  GTUDDTYC  ======================================================== */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
+ #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
+ #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
+ #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
+ #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
+ #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
+ #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
+/* =========================================================  GTIOR  ========================================================= */
+ #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
+ #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
+ #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
+ #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
+ #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
+ #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
+ #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
+ #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
+ #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
+ #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
+ #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
+ #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
+ #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
+ #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
+ #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
+ #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  GTINTAD  ======================================================== */
+ #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
+ #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
+ #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
+ #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+/* =========================================================  GTST  ========================================================== */
+ #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
+ #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
+ #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
+ #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
+ #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
+ #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
+ #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
+ #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
+ #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
+ #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
+ #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
+ #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
+ #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
+ #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
+ #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
+ #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
+ #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
+ #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
+ #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
+ #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
+ #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTBER  ========================================================= */
+ #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
+ #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
+ #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
+ #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
+ #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
+ #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
+ #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
+ #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
+ #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
+ #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
+ #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
+ #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
+ #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
+ #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
+ #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
+ #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
+ #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTITC  ========================================================= */
+ #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
+ #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
+ #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
+ #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
+ #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
+ #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
+ #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
+ #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
+ #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
+ #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
+ #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
+ #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
+ #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
+ #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
+/* =========================================================  GTCNT  ========================================================= */
+ #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
+ #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTCCR  ========================================================= */
+ #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
+ #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTPR  ========================================================== */
+ #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
+ #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
+/* =========================================================  GTPBR  ========================================================= */
+ #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
+ #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
+/* ========================================================  GTPDBR  ========================================================= */
+ #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
+ #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  GTADTRA  ======================================================== */
+ #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
+ #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
+/* ========================================================  GTADTRB  ======================================================== */
+ #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
+ #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  GTADTBRA  ======================================================== */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
+ #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTBRB  ======================================================== */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
+ #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
+/* =======================================================  GTADTDBRA  ======================================================= */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  GTADTDBRB  ======================================================= */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
+/* ========================================================  GTDTCR  ========================================================= */
+ #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
+ #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
+ #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
+ #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
+ #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  GTDVU  ========================================================= */
+ #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDVD  ========================================================= */
+ #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
+ #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBU  ========================================================= */
+ #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
+ #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTDBD  ========================================================= */
+ #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
+ #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  GTSOS  ========================================================= */
+ #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
+ #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
+/* ========================================================  GTSOTR  ========================================================= */
+ #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
+ #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_ODC                                         ================ */
+/* =========================================================================================================================== */
+
+/* =======================================================  GTDLYCR1  ======================================================== */
+ #define R_GPT_ODC_GTDLYCR1_DLLMOD_Pos     (8UL)      /*!< DLLMOD (Bit 8)                                        */
+ #define R_GPT_ODC_GTDLYCR1_DLLMOD_Msk     (0x100UL)  /*!< DLLMOD (Bitfield-Mask: 0x01)                          */
+ #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos     (1UL)      /*!< DLYRST (Bit 1)                                        */
+ #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk     (0x2UL)    /*!< DLYRST (Bitfield-Mask: 0x01)                          */
+ #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos      (0UL)      /*!< DLLEN (Bit 0)                                         */
+ #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk      (0x1UL)    /*!< DLLEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  GTDLYCR2  ======================================================== */
+ #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos    (12UL)     /*!< DLYDENB (Bit 12)                                      */
+ #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk    (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01)                         */
+ #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos      (8UL)      /*!< DLYEN (Bit 8)                                         */
+ #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk      (0x100UL)  /*!< DLYEN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos      (0UL)      /*!< DLYBS (Bit 0)                                         */
+ #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk      (0x1UL)    /*!< DLYBS (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                         R_GPT_OPS                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  OPSCR  ========================================================= */
+ #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
+ #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
+ #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
+ #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
+ #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
+ #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
+ #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
+ #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
+ #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
+ #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
+ #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
+ #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
+ #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
+ #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
+ #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
+ #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
+ #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
+ #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                        R_GPT_POEG0                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  POEGG  ========================================================= */
+ #define R_GPT_POEG0_POEGG_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
+ #define R_GPT_POEG0_POEGG_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
+ #define R_GPT_POEG0_POEGG_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
+ #define R_GPT_POEG0_POEGG_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
+ #define R_GPT_POEG0_POEGG_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
+ #define R_GPT_POEG0_POEGG_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
+ #define R_GPT_POEG0_POEGG_CDRE_Pos     (8UL)          /*!< CDRE (Bit 8)                                          */
+ #define R_GPT_POEG0_POEGG_CDRE_Msk     (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
+ #define R_GPT_POEG0_POEGG_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
+ #define R_GPT_POEG0_POEGG_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
+ #define R_GPT_POEG0_POEGG_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
+ #define R_GPT_POEG0_POEGG_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
+ #define R_GPT_POEG0_POEGG_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
+ #define R_GPT_POEG0_POEGG_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
+ #define R_GPT_POEG0_POEGG_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
+ #define R_GPT_POEG0_POEGG_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
+ #define R_GPT_POEG0_POEGG_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_ICU                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  IRQCR  ========================================================= */
+ #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
+ #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
+ #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
+ #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
+ #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
+/* =========================================================  NMISR  ========================================================= */
+ #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
+ #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
+ #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
+ #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
+ #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
+ #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
+ #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
+ #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
+ #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
+ #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
+ #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
+ #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
+ #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
+/* =========================================================  NMIER  ========================================================= */
+ #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
+ #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
+ #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
+ #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
+ #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
+ #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
+ #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
+ #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
+ #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
+ #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
+ #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
+ #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
+ #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
+ #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  NMICLR  ========================================================= */
+ #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
+ #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
+ #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
+ #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
+ #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
+ #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
+ #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
+ #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
+ #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
+ #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
+ #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
+ #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
+ #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
+ #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  NMICR  ========================================================= */
+ #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
+ #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
+ #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
+ #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
+ #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
+ #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
+/* =========================================================  IELSR  ========================================================= */
+ #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
+ #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
+ #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
+ #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  DELSR  ========================================================= */
+ #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
+ #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
+ #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
+ #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
+/* ========================================================  SELSR0  ========================================================= */
+ #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
+ #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  WUPEN  ========================================================= */
+ #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
+ #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
+ #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
+ #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
+ #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
+ #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
+ #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
+ #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
+ #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
+ #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
+ #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
+ #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
+ #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
+ #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
+ #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
+ #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
+ #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IIC0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  ICCR1  ========================================================= */
+ #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
+ #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
+ #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
+ #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
+ #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
+ #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
+ #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
+ #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
+ #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICCR2  ========================================================= */
+ #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
+ #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
+ #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
+ #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
+ #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
+ #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
+ #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
+/* =========================================================  ICMR1  ========================================================= */
+ #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
+ #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
+ #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
+ #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
+ #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
+ #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
+/* =========================================================  ICMR2  ========================================================= */
+ #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
+ #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
+ #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
+ #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
+ #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
+ #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
+ #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICMR3  ========================================================= */
+ #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
+ #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
+ #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
+ #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
+ #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
+ #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
+ #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
+ #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
+/* =========================================================  ICFER  ========================================================= */
+ #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
+ #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
+ #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
+ #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
+ #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
+ #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
+ #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
+ #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
+ #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSER  ========================================================= */
+ #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
+ #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
+ #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
+ #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
+ #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
+ #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
+ #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICIER  ========================================================= */
+ #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
+ #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
+ #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
+ #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
+ #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
+ #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
+ #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
+ #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
+ #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
+/* =========================================================  ICSR1  ========================================================= */
+ #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
+ #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
+ #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
+ #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
+ #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
+ #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
+ #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICSR2  ========================================================= */
+ #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
+ #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
+ #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
+ #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
+ #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
+ #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
+ #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
+ #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
+ #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
+ #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  ICBRL  ========================================================= */
+ #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
+ #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICBRH  ========================================================= */
+ #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
+ #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
+/* =========================================================  ICDRT  ========================================================= */
+ #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
+ #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICDRR  ========================================================= */
+ #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
+ #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  ICWUR  ========================================================= */
+ #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
+ #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
+ #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
+ #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
+ #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
+ #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
+ #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
+ #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
+/* ========================================================  ICWUR2  ========================================================= */
+ #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
+ #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
+ #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
+ #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
+ #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
+ #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IRDA                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  IRCR  ========================================================== */
+ #define R_IRDA_IRCR_IRE_Pos        (7UL)    /*!< IRE (Bit 7)                                           */
+ #define R_IRDA_IRCR_IRE_Msk        (0x80UL) /*!< IRE (Bitfield-Mask: 0x01)                             */
+ #define R_IRDA_IRCR_IRTXINV_Pos    (3UL)    /*!< IRTXINV (Bit 3)                                       */
+ #define R_IRDA_IRCR_IRTXINV_Msk    (0x8UL)  /*!< IRTXINV (Bitfield-Mask: 0x01)                         */
+ #define R_IRDA_IRCR_IRRXINV_Pos    (2UL)    /*!< IRRXINV (Bit 2)                                       */
+ #define R_IRDA_IRCR_IRRXINV_Msk    (0x4UL)  /*!< IRRXINV (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                          R_IWDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  IWDTRR  ========================================================= */
+ #define R_IWDT_IWDTRR_IWDTRR_Pos    (0UL)      /*!< IWDTRR (Bit 0)                                        */
+ #define R_IWDT_IWDTRR_IWDTRR_Msk    (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  IWDTSR  ========================================================= */
+ #define R_IWDT_IWDTSR_REFEF_Pos     (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_IWDT_IWDTSR_REFEF_Msk     (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_UNDFF_Pos     (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_IWDT_IWDTSR_UNDFF_Msk     (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_IWDT_IWDTSR_CNTVAL_Pos    (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_IWDT_IWDTSR_CNTVAL_Msk    (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+
+/* =========================================================================================================================== */
+/* ================                                          R_JPEG                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  JCMOD  ========================================================= */
+ #define R_JPEG_JCMOD_DSP_Pos           (3UL)          /*!< DSP (Bit 3)                                           */
+ #define R_JPEG_JCMOD_DSP_Msk           (0x8UL)        /*!< DSP (Bitfield-Mask: 0x01)                             */
+ #define R_JPEG_JCMOD_REDU_Pos          (0UL)          /*!< REDU (Bit 0)                                          */
+ #define R_JPEG_JCMOD_REDU_Msk          (0x7UL)        /*!< REDU (Bitfield-Mask: 0x07)                            */
+/* =========================================================  JCCMD  ========================================================= */
+ #define R_JPEG_JCCMD_BRST_Pos          (7UL)          /*!< BRST (Bit 7)                                          */
+ #define R_JPEG_JCCMD_BRST_Msk          (0x80UL)       /*!< BRST (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCCMD_JEND_Pos          (2UL)          /*!< JEND (Bit 2)                                          */
+ #define R_JPEG_JCCMD_JEND_Msk          (0x4UL)        /*!< JEND (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCCMD_JRST_Pos          (1UL)          /*!< JRST (Bit 1)                                          */
+ #define R_JPEG_JCCMD_JRST_Msk          (0x2UL)        /*!< JRST (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCCMD_JSRT_Pos          (0UL)          /*!< JSRT (Bit 0)                                          */
+ #define R_JPEG_JCCMD_JSRT_Msk          (0x1UL)        /*!< JSRT (Bitfield-Mask: 0x01)                            */
+/* =========================================================  JCQTN  ========================================================= */
+ #define R_JPEG_JCQTN_QT3_Pos           (4UL)          /*!< QT3 (Bit 4)                                           */
+ #define R_JPEG_JCQTN_QT3_Msk           (0x30UL)       /*!< QT3 (Bitfield-Mask: 0x03)                             */
+ #define R_JPEG_JCQTN_QT2_Pos           (2UL)          /*!< QT2 (Bit 2)                                           */
+ #define R_JPEG_JCQTN_QT2_Msk           (0xcUL)        /*!< QT2 (Bitfield-Mask: 0x03)                             */
+ #define R_JPEG_JCQTN_QT1_Pos           (0UL)          /*!< QT1 (Bit 0)                                           */
+ #define R_JPEG_JCQTN_QT1_Msk           (0x3UL)        /*!< QT1 (Bitfield-Mask: 0x03)                             */
+/* =========================================================  JCHTN  ========================================================= */
+ #define R_JPEG_JCHTN_HTA3_Pos          (5UL)          /*!< HTA3 (Bit 5)                                          */
+ #define R_JPEG_JCHTN_HTA3_Msk          (0x20UL)       /*!< HTA3 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCHTN_HTD3_Pos          (4UL)          /*!< HTD3 (Bit 4)                                          */
+ #define R_JPEG_JCHTN_HTD3_Msk          (0x10UL)       /*!< HTD3 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCHTN_HTA2_Pos          (3UL)          /*!< HTA2 (Bit 3)                                          */
+ #define R_JPEG_JCHTN_HTA2_Msk          (0x8UL)        /*!< HTA2 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCHTN_HTD2_Pos          (2UL)          /*!< HTD2 (Bit 2)                                          */
+ #define R_JPEG_JCHTN_HTD2_Msk          (0x4UL)        /*!< HTD2 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCHTN_HTA1_Pos          (1UL)          /*!< HTA1 (Bit 1)                                          */
+ #define R_JPEG_JCHTN_HTA1_Msk          (0x2UL)        /*!< HTA1 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JCHTN_HTD1_Pos          (0UL)          /*!< HTD1 (Bit 0)                                          */
+ #define R_JPEG_JCHTN_HTD1_Msk          (0x1UL)        /*!< HTD1 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  JCDRIU  ========================================================= */
+ #define R_JPEG_JCDRIU_DRIU_Pos         (0UL)          /*!< DRIU (Bit 0)                                          */
+ #define R_JPEG_JCDRIU_DRIU_Msk         (0xffUL)       /*!< DRIU (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCDRID  ========================================================= */
+ #define R_JPEG_JCDRID_DRID_Pos         (0UL)          /*!< DRID (Bit 0)                                          */
+ #define R_JPEG_JCDRID_DRID_Msk         (0xffUL)       /*!< DRID (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCVSZU  ========================================================= */
+ #define R_JPEG_JCVSZU_VSZU_Pos         (0UL)          /*!< VSZU (Bit 0)                                          */
+ #define R_JPEG_JCVSZU_VSZU_Msk         (0xffUL)       /*!< VSZU (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCVSZD  ========================================================= */
+ #define R_JPEG_JCVSZD_VSZD_Pos         (0UL)          /*!< VSZD (Bit 0)                                          */
+ #define R_JPEG_JCVSZD_VSZD_Msk         (0xffUL)       /*!< VSZD (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCHSZU  ========================================================= */
+ #define R_JPEG_JCHSZU_HSZU_Pos         (0UL)          /*!< HSZU (Bit 0)                                          */
+ #define R_JPEG_JCHSZU_HSZU_Msk         (0xffUL)       /*!< HSZU (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCHSZD  ========================================================= */
+ #define R_JPEG_JCHSZD_HSZD_Pos         (0UL)          /*!< HSZD (Bit 0)                                          */
+ #define R_JPEG_JCHSZD_HSZD_Msk         (0xffUL)       /*!< HSZD (Bitfield-Mask: 0xff)                            */
+/* ========================================================  JCDTCU  ========================================================= */
+ #define R_JPEG_JCDTCU_DCU_Pos          (0UL)          /*!< DCU (Bit 0)                                           */
+ #define R_JPEG_JCDTCU_DCU_Msk          (0xffUL)       /*!< DCU (Bitfield-Mask: 0xff)                             */
+/* ========================================================  JCDTCM  ========================================================= */
+ #define R_JPEG_JCDTCM_DCM_Pos          (0UL)          /*!< DCM (Bit 0)                                           */
+ #define R_JPEG_JCDTCM_DCM_Msk          (0xffUL)       /*!< DCM (Bitfield-Mask: 0xff)                             */
+/* ========================================================  JCDTCD  ========================================================= */
+ #define R_JPEG_JCDTCD_DCD_Pos          (0UL)          /*!< DCD (Bit 0)                                           */
+ #define R_JPEG_JCDTCD_DCD_Msk          (0xffUL)       /*!< DCD (Bitfield-Mask: 0xff)                             */
+/* ========================================================  JINTE0  ========================================================= */
+ #define R_JPEG_JINTE0_INT7_Pos         (7UL)          /*!< INT7 (Bit 7)                                          */
+ #define R_JPEG_JINTE0_INT7_Msk         (0x80UL)       /*!< INT7 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTE0_INT6_Pos         (6UL)          /*!< INT6 (Bit 6)                                          */
+ #define R_JPEG_JINTE0_INT6_Msk         (0x40UL)       /*!< INT6 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTE0_INT5_Pos         (5UL)          /*!< INT5 (Bit 5)                                          */
+ #define R_JPEG_JINTE0_INT5_Msk         (0x20UL)       /*!< INT5 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTE0_INT3_Pos         (3UL)          /*!< INT3 (Bit 3)                                          */
+ #define R_JPEG_JINTE0_INT3_Msk         (0x8UL)        /*!< INT3 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  JINTS0  ========================================================= */
+ #define R_JPEG_JINTS0_INS6_Pos         (6UL)          /*!< INS6 (Bit 6)                                          */
+ #define R_JPEG_JINTS0_INS6_Msk         (0x40UL)       /*!< INS6 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTS0_INS5_Pos         (5UL)          /*!< INS5 (Bit 5)                                          */
+ #define R_JPEG_JINTS0_INS5_Msk         (0x20UL)       /*!< INS5 (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTS0_INS3_Pos         (3UL)          /*!< INS3 (Bit 3)                                          */
+ #define R_JPEG_JINTS0_INS3_Msk         (0x8UL)        /*!< INS3 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  JCDERR  ========================================================= */
+ #define R_JPEG_JCDERR_ERR_Pos          (0UL)          /*!< ERR (Bit 0)                                           */
+ #define R_JPEG_JCDERR_ERR_Msk          (0xfUL)        /*!< ERR (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  JCRST  ========================================================= */
+ #define R_JPEG_JCRST_RST_Pos           (0UL)          /*!< RST (Bit 0)                                           */
+ #define R_JPEG_JCRST_RST_Msk           (0x1UL)        /*!< RST (Bitfield-Mask: 0x01)                             */
+/* ========================================================  JIFECNT  ======================================================== */
+ #define R_JPEG_JIFECNT_JOUTSWAP_Pos    (8UL)          /*!< JOUTSWAP (Bit 8)                                      */
+ #define R_JPEG_JIFECNT_JOUTSWAP_Msk    (0x700UL)      /*!< JOUTSWAP (Bitfield-Mask: 0x07)                        */
+ #define R_JPEG_JIFECNT_DINRINI_Pos     (6UL)          /*!< DINRINI (Bit 6)                                       */
+ #define R_JPEG_JIFECNT_DINRINI_Msk     (0x40UL)       /*!< DINRINI (Bitfield-Mask: 0x01)                         */
+ #define R_JPEG_JIFECNT_DINRCMD_Pos     (5UL)          /*!< DINRCMD (Bit 5)                                       */
+ #define R_JPEG_JIFECNT_DINRCMD_Msk     (0x20UL)       /*!< DINRCMD (Bitfield-Mask: 0x01)                         */
+ #define R_JPEG_JIFECNT_DINLC_Pos       (4UL)          /*!< DINLC (Bit 4)                                         */
+ #define R_JPEG_JIFECNT_DINLC_Msk       (0x10UL)       /*!< DINLC (Bitfield-Mask: 0x01)                           */
+ #define R_JPEG_JIFECNT_DINSWAP_Pos     (0UL)          /*!< DINSWAP (Bit 0)                                       */
+ #define R_JPEG_JIFECNT_DINSWAP_Msk     (0x7UL)        /*!< DINSWAP (Bitfield-Mask: 0x07)                         */
+/* ========================================================  JIFESA  ========================================================= */
+ #define R_JPEG_JIFESA_ESA_Pos          (0UL)          /*!< ESA (Bit 0)                                           */
+ #define R_JPEG_JIFESA_ESA_Msk          (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  JIFESOFST  ======================================================= */
+ #define R_JPEG_JIFESOFST_ESMW_Pos      (0UL)          /*!< ESMW (Bit 0)                                          */
+ #define R_JPEG_JIFESOFST_ESMW_Msk      (0x7fffUL)     /*!< ESMW (Bitfield-Mask: 0x7fff)                          */
+/* ========================================================  JIFEDA  ========================================================= */
+ #define R_JPEG_JIFEDA_EDA_Pos          (0UL)          /*!< EDA (Bit 0)                                           */
+ #define R_JPEG_JIFEDA_EDA_Msk          (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  JIFESLC  ======================================================== */
+ #define R_JPEG_JIFESLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
+ #define R_JPEG_JIFESLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  JIFDCNT  ======================================================== */
+ #define R_JPEG_JIFDCNT_VINTER_Pos      (28UL)         /*!< VINTER (Bit 28)                                       */
+ #define R_JPEG_JIFDCNT_VINTER_Msk      (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03)                          */
+ #define R_JPEG_JIFDCNT_HINTER_Pos      (26UL)         /*!< HINTER (Bit 26)                                       */
+ #define R_JPEG_JIFDCNT_HINTER_Msk      (0xc000000UL)  /*!< HINTER (Bitfield-Mask: 0x03)                          */
+ #define R_JPEG_JIFDCNT_OPF_Pos         (24UL)         /*!< OPF (Bit 24)                                          */
+ #define R_JPEG_JIFDCNT_OPF_Msk         (0x3000000UL)  /*!< OPF (Bitfield-Mask: 0x03)                             */
+ #define R_JPEG_JIFDCNT_JINRINI_Pos     (14UL)         /*!< JINRINI (Bit 14)                                      */
+ #define R_JPEG_JIFDCNT_JINRINI_Msk     (0x4000UL)     /*!< JINRINI (Bitfield-Mask: 0x01)                         */
+ #define R_JPEG_JIFDCNT_JINRCMD_Pos     (13UL)         /*!< JINRCMD (Bit 13)                                      */
+ #define R_JPEG_JIFDCNT_JINRCMD_Msk     (0x2000UL)     /*!< JINRCMD (Bitfield-Mask: 0x01)                         */
+ #define R_JPEG_JIFDCNT_JINC_Pos        (12UL)         /*!< JINC (Bit 12)                                         */
+ #define R_JPEG_JIFDCNT_JINC_Msk        (0x1000UL)     /*!< JINC (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JIFDCNT_JINSWAP_Pos     (8UL)          /*!< JINSWAP (Bit 8)                                       */
+ #define R_JPEG_JIFDCNT_JINSWAP_Msk     (0x700UL)      /*!< JINSWAP (Bitfield-Mask: 0x07)                         */
+ #define R_JPEG_JIFDCNT_DOUTRINI_Pos    (6UL)          /*!< DOUTRINI (Bit 6)                                      */
+ #define R_JPEG_JIFDCNT_DOUTRINI_Msk    (0x40UL)       /*!< DOUTRINI (Bitfield-Mask: 0x01)                        */
+ #define R_JPEG_JIFDCNT_DOUTRCMD_Pos    (5UL)          /*!< DOUTRCMD (Bit 5)                                      */
+ #define R_JPEG_JIFDCNT_DOUTRCMD_Msk    (0x20UL)       /*!< DOUTRCMD (Bitfield-Mask: 0x01)                        */
+ #define R_JPEG_JIFDCNT_DOUTLC_Pos      (4UL)          /*!< DOUTLC (Bit 4)                                        */
+ #define R_JPEG_JIFDCNT_DOUTLC_Msk      (0x10UL)       /*!< DOUTLC (Bitfield-Mask: 0x01)                          */
+ #define R_JPEG_JIFDCNT_DOUTSWAP_Pos    (0UL)          /*!< DOUTSWAP (Bit 0)                                      */
+ #define R_JPEG_JIFDCNT_DOUTSWAP_Msk    (0x7UL)        /*!< DOUTSWAP (Bitfield-Mask: 0x07)                        */
+/* ========================================================  JIFDSA  ========================================================= */
+ #define R_JPEG_JIFDSA_DSA_Pos          (0UL)          /*!< DSA (Bit 0)                                           */
+ #define R_JPEG_JIFDSA_DSA_Msk          (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff)                       */
+/* =======================================================  JIFDDOFST  ======================================================= */
+ #define R_JPEG_JIFDDOFST_DDMW_Pos      (0UL)          /*!< DDMW (Bit 0)                                          */
+ #define R_JPEG_JIFDDOFST_DDMW_Msk      (0x7fffUL)     /*!< DDMW (Bitfield-Mask: 0x7fff)                          */
+/* ========================================================  JIFDDA  ========================================================= */
+ #define R_JPEG_JIFDDA_DDA_Pos          (0UL)          /*!< DDA (Bit 0)                                           */
+ #define R_JPEG_JIFDDA_DDA_Msk          (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff)                       */
+/* ========================================================  JIFDSDC  ======================================================== */
+ #define R_JPEG_JIFDSDC_JDATAS_Pos      (0UL)          /*!< JDATAS (Bit 0)                                        */
+ #define R_JPEG_JIFDSDC_JDATAS_Msk      (0xffffUL)     /*!< JDATAS (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  JIFDDLC  ======================================================== */
+ #define R_JPEG_JIFDDLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
+ #define R_JPEG_JIFDDLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  JIFDADT  ======================================================== */
+ #define R_JPEG_JIFDADT_ALPHA_Pos       (0UL)          /*!< ALPHA (Bit 0)                                         */
+ #define R_JPEG_JIFDADT_ALPHA_Msk       (0xffUL)       /*!< ALPHA (Bitfield-Mask: 0xff)                           */
+/* ========================================================  JINTE1  ========================================================= */
+ #define R_JPEG_JINTE1_CBTEN_Pos        (6UL)          /*!< CBTEN (Bit 6)                                         */
+ #define R_JPEG_JINTE1_CBTEN_Msk        (0x40UL)       /*!< CBTEN (Bitfield-Mask: 0x01)                           */
+ #define R_JPEG_JINTE1_DINLEN_Pos       (5UL)          /*!< DINLEN (Bit 5)                                        */
+ #define R_JPEG_JINTE1_DINLEN_Msk       (0x20UL)       /*!< DINLEN (Bitfield-Mask: 0x01)                          */
+ #define R_JPEG_JINTE1_DBTEN_Pos        (2UL)          /*!< DBTEN (Bit 2)                                         */
+ #define R_JPEG_JINTE1_DBTEN_Msk        (0x4UL)        /*!< DBTEN (Bitfield-Mask: 0x01)                           */
+ #define R_JPEG_JINTE1_JINEN_Pos        (1UL)          /*!< JINEN (Bit 1)                                         */
+ #define R_JPEG_JINTE1_JINEN_Msk        (0x2UL)        /*!< JINEN (Bitfield-Mask: 0x01)                           */
+ #define R_JPEG_JINTE1_DOUTLEN_Pos      (0UL)          /*!< DOUTLEN (Bit 0)                                       */
+ #define R_JPEG_JINTE1_DOUTLEN_Msk      (0x1UL)        /*!< DOUTLEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  JINTS1  ========================================================= */
+ #define R_JPEG_JINTS1_CBTF_Pos         (6UL)          /*!< CBTF (Bit 6)                                          */
+ #define R_JPEG_JINTS1_CBTF_Msk         (0x40UL)       /*!< CBTF (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTS1_DINLF_Pos        (5UL)          /*!< DINLF (Bit 5)                                         */
+ #define R_JPEG_JINTS1_DINLF_Msk        (0x20UL)       /*!< DINLF (Bitfield-Mask: 0x01)                           */
+ #define R_JPEG_JINTS1_DBTF_Pos         (2UL)          /*!< DBTF (Bit 2)                                          */
+ #define R_JPEG_JINTS1_DBTF_Msk         (0x4UL)        /*!< DBTF (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTS1_JINF_Pos         (1UL)          /*!< JINF (Bit 1)                                          */
+ #define R_JPEG_JINTS1_JINF_Msk         (0x2UL)        /*!< JINF (Bitfield-Mask: 0x01)                            */
+ #define R_JPEG_JINTS1_DOUTLF_Pos       (0UL)          /*!< DOUTLF (Bit 0)                                        */
+ #define R_JPEG_JINTS1_DOUTLF_Msk       (0x1UL)        /*!< DOUTLF (Bitfield-Mask: 0x01)                          */
+/* ========================================================  JCQTBL0  ======================================================== */
+/* ========================================================  JCQTBL1  ======================================================== */
+/* ========================================================  JCQTBL2  ======================================================== */
+/* ========================================================  JCQTBL3  ======================================================== */
+/* ========================================================  JCHTBD0  ======================================================== */
+/* ========================================================  JCHTBD1  ======================================================== */
+/* ========================================================  JCHTBA0  ======================================================== */
+/* ========================================================  JCHTBA1  ======================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_KINT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  KRCTL  ========================================================= */
+ #define R_KINT_KRCTL_KRMD_Pos    (7UL)    /*!< KRMD (Bit 7)                                          */
+ #define R_KINT_KRCTL_KRMD_Msk    (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRCTL_KREG_Pos    (0UL)    /*!< KREG (Bit 0)                                          */
+ #define R_KINT_KRCTL_KREG_Msk    (0x1UL)  /*!< KREG (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  KRF  ========================================================== */
+ #define R_KINT_KRF_KRF7_Pos      (7UL)    /*!< KRF7 (Bit 7)                                          */
+ #define R_KINT_KRF_KRF7_Msk      (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF6_Pos      (6UL)    /*!< KRF6 (Bit 6)                                          */
+ #define R_KINT_KRF_KRF6_Msk      (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF5_Pos      (5UL)    /*!< KRF5 (Bit 5)                                          */
+ #define R_KINT_KRF_KRF5_Msk      (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF4_Pos      (4UL)    /*!< KRF4 (Bit 4)                                          */
+ #define R_KINT_KRF_KRF4_Msk      (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF3_Pos      (3UL)    /*!< KRF3 (Bit 3)                                          */
+ #define R_KINT_KRF_KRF3_Msk      (0x8UL)  /*!< KRF3 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF2_Pos      (2UL)    /*!< KRF2 (Bit 2)                                          */
+ #define R_KINT_KRF_KRF2_Msk      (0x4UL)  /*!< KRF2 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF1_Pos      (1UL)    /*!< KRF1 (Bit 1)                                          */
+ #define R_KINT_KRF_KRF1_Msk      (0x2UL)  /*!< KRF1 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRF_KRF0_Pos      (0UL)    /*!< KRF0 (Bit 0)                                          */
+ #define R_KINT_KRF_KRF0_Msk      (0x1UL)  /*!< KRF0 (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  KRM  ========================================================== */
+ #define R_KINT_KRM_KRM7_Pos      (7UL)    /*!< KRM7 (Bit 7)                                          */
+ #define R_KINT_KRM_KRM7_Msk      (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM6_Pos      (6UL)    /*!< KRM6 (Bit 6)                                          */
+ #define R_KINT_KRM_KRM6_Msk      (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM5_Pos      (5UL)    /*!< KRM5 (Bit 5)                                          */
+ #define R_KINT_KRM_KRM5_Msk      (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM4_Pos      (4UL)    /*!< KRM4 (Bit 4)                                          */
+ #define R_KINT_KRM_KRM4_Msk      (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM3_Pos      (3UL)    /*!< KRM3 (Bit 3)                                          */
+ #define R_KINT_KRM_KRM3_Msk      (0x8UL)  /*!< KRM3 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM2_Pos      (2UL)    /*!< KRM2 (Bit 2)                                          */
+ #define R_KINT_KRM_KRM2_Msk      (0x4UL)  /*!< KRM2 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM1_Pos      (1UL)    /*!< KRM1 (Bit 1)                                          */
+ #define R_KINT_KRM_KRM1_Msk      (0x2UL)  /*!< KRM1 (Bitfield-Mask: 0x01)                            */
+ #define R_KINT_KRM_KRM0_Pos      (0UL)    /*!< KRM0 (Bit 0)                                          */
+ #define R_KINT_KRM_KRM0_Msk      (0x1UL)  /*!< KRM0 (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_MMF                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  MMSFR  ========================================================= */
+ #define R_MMF_MMSFR_KEY_Pos           (24UL)         /*!< KEY (Bit 24)                                          */
+ #define R_MMF_MMSFR_KEY_Msk           (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MMF_MMSFR_MEMMIRADDR_Pos    (7UL)          /*!< MEMMIRADDR (Bit 7)                                    */
+ #define R_MMF_MMSFR_MEMMIRADDR_Msk    (0x7fff80UL)   /*!< MEMMIRADDR (Bitfield-Mask: 0xffff)                    */
+/* =========================================================  MMEN  ========================================================== */
+ #define R_MMF_MMEN_KEY_Pos            (24UL)         /*!< KEY (Bit 24)                                          */
+ #define R_MMF_MMEN_KEY_Msk            (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MMF_MMEN_EN_Pos             (0UL)          /*!< EN (Bit 0)                                            */
+ #define R_MMF_MMEN_EN_Msk             (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_MMPU                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SMPU                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SMPUCTL  ======================================================== */
+ #define R_MPU_SMPU_SMPUCTL_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
+ #define R_MPU_SMPU_SMPUCTL_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
+ #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos    (1UL)      /*!< PROTECT (Bit 1)                                       */
+ #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk    (0x2UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
+ #define R_MPU_SMPU_SMPUCTL_OAD_Pos        (0UL)      /*!< OAD (Bit 0)                                           */
+ #define R_MPU_SMPU_SMPUCTL_OAD_Msk        (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                        R_MPU_SPMON                                        ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_MSTP                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  MSTPCRB  ======================================================== */
+ #define R_MSTP_MSTPCRB_MSTPB31_Pos    (31UL)         /*!< MSTPB31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB31_Msk    (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB30_Pos    (30UL)         /*!< MSTPB30 (Bit 30)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB30_Msk    (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB29_Pos    (29UL)         /*!< MSTPB29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB29_Msk    (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB28_Pos    (28UL)         /*!< MSTPB28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB28_Msk    (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB27_Pos    (27UL)         /*!< MSTPB27 (Bit 27)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB27_Msk    (0x8000000UL)  /*!< MSTPB27 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB26_Pos    (26UL)         /*!< MSTPB26 (Bit 26)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB26_Msk    (0x4000000UL)  /*!< MSTPB26 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB25_Pos    (25UL)         /*!< MSTPB25 (Bit 25)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB25_Msk    (0x2000000UL)  /*!< MSTPB25 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB24_Pos    (24UL)         /*!< MSTPB24 (Bit 24)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB24_Msk    (0x1000000UL)  /*!< MSTPB24 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB23_Pos    (23UL)         /*!< MSTPB23 (Bit 23)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB23_Msk    (0x800000UL)   /*!< MSTPB23 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB22_Pos    (22UL)         /*!< MSTPB22 (Bit 22)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB22_Msk    (0x400000UL)   /*!< MSTPB22 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB19_Pos    (19UL)         /*!< MSTPB19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB19_Msk    (0x80000UL)    /*!< MSTPB19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB18_Pos    (18UL)         /*!< MSTPB18 (Bit 18)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB18_Msk    (0x40000UL)    /*!< MSTPB18 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB15_Pos    (15UL)         /*!< MSTPB15 (Bit 15)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB15_Msk    (0x8000UL)     /*!< MSTPB15 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB14_Pos    (14UL)         /*!< MSTPB14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB14_Msk    (0x4000UL)     /*!< MSTPB14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB13_Pos    (13UL)         /*!< MSTPB13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB13_Msk    (0x2000UL)     /*!< MSTPB13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB12_Pos    (12UL)         /*!< MSTPB12 (Bit 12)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB12_Msk    (0x1000UL)     /*!< MSTPB12 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB11_Pos    (11UL)         /*!< MSTPB11 (Bit 11)                                      */
+ #define R_MSTP_MSTPCRB_MSTPB11_Msk    (0x800UL)      /*!< MSTPB11 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRB_MSTPB9_Pos     (9UL)          /*!< MSTPB9 (Bit 9)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB9_Msk     (0x200UL)      /*!< MSTPB9 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB8_Pos     (8UL)          /*!< MSTPB8 (Bit 8)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB8_Msk     (0x100UL)      /*!< MSTPB8 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB7_Pos     (7UL)          /*!< MSTPB7 (Bit 7)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB7_Msk     (0x80UL)       /*!< MSTPB7 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB6_Pos     (6UL)          /*!< MSTPB6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB6_Msk     (0x40UL)       /*!< MSTPB6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB5_Pos     (5UL)          /*!< MSTPB5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB5_Msk     (0x20UL)       /*!< MSTPB5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB2_Pos     (2UL)          /*!< MSTPB2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB2_Msk     (0x4UL)        /*!< MSTPB2 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRB_MSTPB1_Pos     (1UL)          /*!< MSTPB1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRB_MSTPB1_Msk     (0x2UL)        /*!< MSTPB1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRC  ======================================================== */
+ #define R_MSTP_MSTPCRC_MSTPC31_Pos    (31UL)         /*!< MSTPC31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC31_Msk    (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC28_Pos    (28UL)         /*!< MSTPC28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC28_Msk    (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC14_Pos    (14UL)         /*!< MSTPC14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC14_Msk    (0x4000UL)     /*!< MSTPC14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC13_Pos    (13UL)         /*!< MSTPC13 (Bit 13)                                      */
+ #define R_MSTP_MSTPCRC_MSTPC13_Msk    (0x2000UL)     /*!< MSTPC13 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRC_MSTPC4_Pos     (4UL)          /*!< MSTPC4 (Bit 4)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC4_Msk     (0x10UL)       /*!< MSTPC4 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC3_Pos     (3UL)          /*!< MSTPC3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC3_Msk     (0x8UL)        /*!< MSTPC3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC1_Pos     (1UL)          /*!< MSTPC1 (Bit 1)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC1_Msk     (0x2UL)        /*!< MSTPC1 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRC_MSTPC0_Pos     (0UL)          /*!< MSTPC0 (Bit 0)                                        */
+ #define R_MSTP_MSTPCRC_MSTPC0_Msk     (0x1UL)        /*!< MSTPC0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  MSTPCRD  ======================================================== */
+ #define R_MSTP_MSTPCRD_MSTPD31_Pos    (31UL)         /*!< MSTPD31 (Bit 31)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD31_Msk    (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD29_Pos    (29UL)         /*!< MSTPD29 (Bit 29)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD29_Msk    (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD28_Pos    (28UL)         /*!< MSTPD28 (Bit 28)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD28_Msk    (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD20_Pos    (20UL)         /*!< MSTPD20 (Bit 20)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD20_Msk    (0x100000UL)   /*!< MSTPD20 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD19_Pos    (19UL)         /*!< MSTPD19 (Bit 19)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD19_Msk    (0x80000UL)    /*!< MSTPD19 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD17_Pos    (17UL)         /*!< MSTPD17 (Bit 17)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD17_Msk    (0x20000UL)    /*!< MSTPD17 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD16_Pos    (16UL)         /*!< MSTPD16 (Bit 16)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD16_Msk    (0x10000UL)    /*!< MSTPD16 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD14_Pos    (14UL)         /*!< MSTPD14 (Bit 14)                                      */
+ #define R_MSTP_MSTPCRD_MSTPD14_Msk    (0x4000UL)     /*!< MSTPD14 (Bitfield-Mask: 0x01)                         */
+ #define R_MSTP_MSTPCRD_MSTPD6_Pos     (6UL)          /*!< MSTPD6 (Bit 6)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD6_Msk     (0x40UL)       /*!< MSTPD6 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD5_Pos     (5UL)          /*!< MSTPD5 (Bit 5)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD5_Msk     (0x20UL)       /*!< MSTPD5 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD3_Pos     (3UL)          /*!< MSTPD3 (Bit 3)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD3_Msk     (0x8UL)        /*!< MSTPD3 (Bitfield-Mask: 0x01)                          */
+ #define R_MSTP_MSTPCRD_MSTPD2_Pos     (2UL)          /*!< MSTPD2 (Bit 2)                                        */
+ #define R_MSTP_MSTPCRD_MSTPD2_Msk     (0x4UL)        /*!< MSTPD2 (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                          R_OPAMP                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  AMPMC  ========================================================= */
+ #define R_OPAMP_AMPMC_AMPSP_Pos      (7UL)    /*!< AMPSP (Bit 7)                                         */
+ #define R_OPAMP_AMPMC_AMPSP_Msk      (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01)                           */
+ #define R_OPAMP_AMPMC_AMPPC_Pos      (0UL)    /*!< AMPPC (Bit 0)                                         */
+ #define R_OPAMP_AMPMC_AMPPC_Msk      (0x1UL)  /*!< AMPPC (Bitfield-Mask: 0x01)                           */
+/* ========================================================  AMPTRM  ========================================================= */
+ #define R_OPAMP_AMPTRM_AMPTRM_Pos    (0UL)    /*!< AMPTRM (Bit 0)                                        */
+ #define R_OPAMP_AMPTRM_AMPTRM_Msk    (0x3UL)  /*!< AMPTRM (Bitfield-Mask: 0x03)                          */
+/* ========================================================  AMPTRS  ========================================================= */
+ #define R_OPAMP_AMPTRS_AMPTRS_Pos    (0UL)    /*!< AMPTRS (Bit 0)                                        */
+ #define R_OPAMP_AMPTRS_AMPTRS_Msk    (0x3UL)  /*!< AMPTRS (Bitfield-Mask: 0x03)                          */
+/* =========================================================  AMPC  ========================================================== */
+ #define R_OPAMP_AMPC_IREFE_Pos       (7UL)    /*!< IREFE (Bit 7)                                         */
+ #define R_OPAMP_AMPC_IREFE_Msk       (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01)                           */
+ #define R_OPAMP_AMPC_AMPE_Pos        (0UL)    /*!< AMPE (Bit 0)                                          */
+ #define R_OPAMP_AMPC_AMPE_Msk        (0x1UL)  /*!< AMPE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  AMPMON  ========================================================= */
+ #define R_OPAMP_AMPMON_AMPMON_Pos    (0UL)    /*!< AMPMON (Bit 0)                                        */
+ #define R_OPAMP_AMPMON_AMPMON_Msk    (0x1UL)  /*!< AMPMON (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AMPCPC  ========================================================= */
+ #define R_OPAMP_AMPCPC_PUMPEN_Pos    (0UL)    /*!< PUMPEN (Bit 0)                                        */
+ #define R_OPAMP_AMPCPC_PUMPEN_Msk    (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
+/* ========================================================  AMPUOTE  ======================================================== */
+ #define R_OPAMP_AMPUOTE_AMPTE_Pos    (0UL)    /*!< AMPTE (Bit 0)                                         */
+ #define R_OPAMP_AMPUOTE_AMPTE_Msk    (0x1UL)  /*!< AMPTE (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PDC                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  PCCR0  ========================================================= */
+ #define R_PDC_PCCR0_EDS_Pos       (14UL)         /*!< EDS (Bit 14)                                          */
+ #define R_PDC_PCCR0_EDS_Msk       (0x4000UL)     /*!< EDS (Bitfield-Mask: 0x01)                             */
+ #define R_PDC_PCCR0_PCKDIV_Pos    (11UL)         /*!< PCKDIV (Bit 11)                                       */
+ #define R_PDC_PCCR0_PCKDIV_Msk    (0x3800UL)     /*!< PCKDIV (Bitfield-Mask: 0x07)                          */
+ #define R_PDC_PCCR0_PCKOE_Pos     (10UL)         /*!< PCKOE (Bit 10)                                        */
+ #define R_PDC_PCCR0_PCKOE_Msk     (0x400UL)      /*!< PCKOE (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCCR0_HERIE_Pos     (9UL)          /*!< HERIE (Bit 9)                                         */
+ #define R_PDC_PCCR0_HERIE_Msk     (0x200UL)      /*!< HERIE (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCCR0_VERIE_Pos     (8UL)          /*!< VERIE (Bit 8)                                         */
+ #define R_PDC_PCCR0_VERIE_Msk     (0x100UL)      /*!< VERIE (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCCR0_UDRIE_Pos     (7UL)          /*!< UDRIE (Bit 7)                                         */
+ #define R_PDC_PCCR0_UDRIE_Msk     (0x80UL)       /*!< UDRIE (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCCR0_OVIE_Pos      (6UL)          /*!< OVIE (Bit 6)                                          */
+ #define R_PDC_PCCR0_OVIE_Msk      (0x40UL)       /*!< OVIE (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCCR0_FEIE_Pos      (5UL)          /*!< FEIE (Bit 5)                                          */
+ #define R_PDC_PCCR0_FEIE_Msk      (0x20UL)       /*!< FEIE (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCCR0_DFIE_Pos      (4UL)          /*!< DFIE (Bit 4)                                          */
+ #define R_PDC_PCCR0_DFIE_Msk      (0x10UL)       /*!< DFIE (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCCR0_PRST_Pos      (3UL)          /*!< PRST (Bit 3)                                          */
+ #define R_PDC_PCCR0_PRST_Msk      (0x8UL)        /*!< PRST (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCCR0_HPS_Pos       (2UL)          /*!< HPS (Bit 2)                                           */
+ #define R_PDC_PCCR0_HPS_Msk       (0x4UL)        /*!< HPS (Bitfield-Mask: 0x01)                             */
+ #define R_PDC_PCCR0_VPS_Pos       (1UL)          /*!< VPS (Bit 1)                                           */
+ #define R_PDC_PCCR0_VPS_Msk       (0x2UL)        /*!< VPS (Bitfield-Mask: 0x01)                             */
+ #define R_PDC_PCCR0_PCKE_Pos      (0UL)          /*!< PCKE (Bit 0)                                          */
+ #define R_PDC_PCCR0_PCKE_Msk      (0x1UL)        /*!< PCKE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PCCR1  ========================================================= */
+ #define R_PDC_PCCR1_PCE_Pos       (0UL)          /*!< PCE (Bit 0)                                           */
+ #define R_PDC_PCCR1_PCE_Msk       (0x1UL)        /*!< PCE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PCSR  ========================================================== */
+ #define R_PDC_PCSR_HERF_Pos       (6UL)          /*!< HERF (Bit 6)                                          */
+ #define R_PDC_PCSR_HERF_Msk       (0x40UL)       /*!< HERF (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCSR_VERF_Pos       (5UL)          /*!< VERF (Bit 5)                                          */
+ #define R_PDC_PCSR_VERF_Msk       (0x20UL)       /*!< VERF (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCSR_UDRF_Pos       (4UL)          /*!< UDRF (Bit 4)                                          */
+ #define R_PDC_PCSR_UDRF_Msk       (0x10UL)       /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCSR_OVRF_Pos       (3UL)          /*!< OVRF (Bit 3)                                          */
+ #define R_PDC_PCSR_OVRF_Msk       (0x8UL)        /*!< OVRF (Bitfield-Mask: 0x01)                            */
+ #define R_PDC_PCSR_FEF_Pos        (2UL)          /*!< FEF (Bit 2)                                           */
+ #define R_PDC_PCSR_FEF_Msk        (0x4UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
+ #define R_PDC_PCSR_FEMPF_Pos      (1UL)          /*!< FEMPF (Bit 1)                                         */
+ #define R_PDC_PCSR_FEMPF_Msk      (0x2UL)        /*!< FEMPF (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCSR_FBSY_Pos       (0UL)          /*!< FBSY (Bit 0)                                          */
+ #define R_PDC_PCSR_FBSY_Msk       (0x1UL)        /*!< FBSY (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCMONR  ========================================================= */
+ #define R_PDC_PCMONR_HSYNC_Pos    (1UL)          /*!< HSYNC (Bit 1)                                         */
+ #define R_PDC_PCMONR_HSYNC_Msk    (0x2UL)        /*!< HSYNC (Bitfield-Mask: 0x01)                           */
+ #define R_PDC_PCMONR_VSYNC_Pos    (0UL)          /*!< VSYNC (Bit 0)                                         */
+ #define R_PDC_PCMONR_VSYNC_Msk    (0x1UL)        /*!< VSYNC (Bitfield-Mask: 0x01)                           */
+/* =========================================================  PCDR  ========================================================== */
+ #define R_PDC_PCDR_PCDR_Pos       (0UL)          /*!< PCDR (Bit 0)                                          */
+ #define R_PDC_PCDR_PCDR_Msk       (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff)                      */
+/* ==========================================================  VCR  ========================================================== */
+ #define R_PDC_VCR_VSZ_Pos         (16UL)         /*!< VSZ (Bit 16)                                          */
+ #define R_PDC_VCR_VSZ_Msk         (0xfff0000UL)  /*!< VSZ (Bitfield-Mask: 0xfff)                            */
+ #define R_PDC_VCR_VST_Pos         (0UL)          /*!< VST (Bit 0)                                           */
+ #define R_PDC_VCR_VST_Msk         (0xfffUL)      /*!< VST (Bitfield-Mask: 0xfff)                            */
+/* ==========================================================  HCR  ========================================================== */
+ #define R_PDC_HCR_HSZ_Pos         (16UL)         /*!< HSZ (Bit 16)                                          */
+ #define R_PDC_HCR_HSZ_Msk         (0xfff0000UL)  /*!< HSZ (Bitfield-Mask: 0xfff)                            */
+ #define R_PDC_HCR_HST_Pos         (0UL)          /*!< HST (Bit 0)                                           */
+ #define R_PDC_HCR_HST_Msk         (0xfffUL)      /*!< HST (Bitfield-Mask: 0xfff)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PORT0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PCNTR1  ========================================================= */
+ #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
+ #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  PODR  ========================================================== */
+ #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
+ #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  PDR  ========================================================== */
+ #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
+ #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  PCNTR2  ========================================================= */
+ #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
+ #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EIDR  ========================================================== */
+ #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
+ #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  PIDR  ========================================================== */
+ #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
+ #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR3  ========================================================= */
+ #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  PORR  ========================================================== */
+ #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
+ #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  POSR  ========================================================== */
+ #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
+ #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
+/* ========================================================  PCNTR4  ========================================================= */
+ #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
+ #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
+ #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
+/* =========================================================  EORR  ========================================================== */
+ #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
+ #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
+/* =========================================================  EOSR  ========================================================== */
+ #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
+ #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_PFS                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================================================================================== */
+/* ================                                          R_PMISC                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PFENET  ========================================================= */
+ #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
+ #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
+ #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
+ #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
+/* =========================================================  PWPR  ========================================================== */
+ #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
+ #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
+ #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
+ #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_QSPI                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SFMSMD  ========================================================= */
+ #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
+ #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
+ #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
+ #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
+ #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
+ #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
+ #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
+ #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
+ #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
+ #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
+ #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  SFMSSC  ========================================================= */
+ #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
+ #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
+ #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
+ #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SFMSKC  ========================================================= */
+ #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
+ #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
+ #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  SFMSST  ========================================================= */
+ #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
+ #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
+ #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
+ #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
+/* ========================================================  SFMCOM  ========================================================= */
+ #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
+ #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
+/* ========================================================  SFMCMD  ========================================================= */
+ #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
+ #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SFMCST  ========================================================= */
+ #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
+ #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
+ #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
+ #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SFMSIC  ========================================================= */
+ #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
+ #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
+/* ========================================================  SFMSAC  ========================================================= */
+ #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
+ #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
+ #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
+/* ========================================================  SFMSDC  ========================================================= */
+ #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
+ #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
+ #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
+ #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
+ #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
+ #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SFMSPC  ========================================================= */
+ #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
+ #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
+ #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
+ #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
+/* ========================================================  SFMPMD  ========================================================= */
+ #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
+ #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SFMCNT1  ======================================================== */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
+ #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
+
+/* =========================================================================================================================== */
+/* ================                                           R_RTC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  R64CNT  ========================================================= */
+ #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
+ #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
+ #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
+ #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
+ #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
+ #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
+ #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
+ #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
+/* ========================================================  RSECCNT  ======================================================== */
+ #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT0  ========================================================= */
+ #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
+ #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RMINCNT  ======================================================== */
+ #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* =========================================================  BCNT1  ========================================================= */
+ #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
+ #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RHRCNT  ========================================================= */
+ #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* =========================================================  BCNT2  ========================================================= */
+ #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
+ #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RWKCNT  ========================================================= */
+ #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* =========================================================  BCNT3  ========================================================= */
+ #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
+ #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
+/* ========================================================  RDAYCNT  ======================================================== */
+ #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  RMONCNT  ======================================================== */
+ #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  RYRCNT  ========================================================= */
+ #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  RSECAR  ========================================================= */
+ #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
+ #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
+ #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT0AR  ======================================================== */
+ #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
+ #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RMINAR  ========================================================= */
+ #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
+ #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
+ #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
+ #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  BCNT1AR  ======================================================== */
+ #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
+ #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RHRAR  ========================================================= */
+ #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
+ #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
+ #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
+ #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
+ #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
+/* ========================================================  BCNT2AR  ======================================================== */
+ #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
+ #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
+/* =========================================================  RWKAR  ========================================================= */
+ #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
+ #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
+/* ========================================================  BCNT3AR  ======================================================== */
+ #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
+ #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
+/* ========================================================  RDAYAR  ========================================================= */
+ #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
+ #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
+ #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
+ #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  BCNT0AER  ======================================================== */
+ #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RMONAR  ========================================================= */
+ #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
+ #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
+ #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  BCNT1AER  ======================================================== */
+ #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RYRAR  ========================================================= */
+ #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
+ #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
+ #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
+ #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
+/* =======================================================  BCNT2AER  ======================================================== */
+ #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* ========================================================  RYRAREN  ======================================================== */
+ #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
+ #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
+/* =======================================================  BCNT3AER  ======================================================== */
+ #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
+ #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
+/* =========================================================  RCR1  ========================================================== */
+ #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
+ #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
+ #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
+ #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
+ #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
+ #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
+ #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
+ #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  RCR2  ========================================================== */
+ #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
+ #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
+ #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
+ #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
+ #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
+ #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
+ #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
+ #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
+ #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
+ #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
+ #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RCR4  ========================================================== */
+ #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
+ #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
+ #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
+ #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
+/* =========================================================  RFRH  ========================================================== */
+ #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
+ #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
+/* =========================================================  RFRL  ========================================================== */
+ #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
+ #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
+/* =========================================================  RADJ  ========================================================== */
+ #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
+ #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
+ #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
+ #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SCI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================================================  SMR  ========================================================== */
+ #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
+ #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
+ #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
+ #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
+ #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SMR_SMCI  ======================================================== */
+ #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
+ #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
+ #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
+ #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
+ #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
+ #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
+ #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
+ #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  BRR  ========================================================== */
+ #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
+ #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SCR  ========================================================== */
+ #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* =======================================================  SCR_SMCI  ======================================================== */
+ #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
+ #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
+ #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
+ #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
+ #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
+ #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
+ #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
+ #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
+/* ==========================================================  TDR  ========================================================== */
+ #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
+ #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
+/* ==========================================================  SSR  ========================================================== */
+ #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* =======================================================  SSR_FIFO  ======================================================== */
+ #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
+ #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
+ #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+/* =======================================================  SSR_SMCI  ======================================================== */
+ #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
+ #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
+ #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
+ #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
+ #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
+ #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  RDR  ========================================================== */
+ #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
+ #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SCMR  ========================================================== */
+ #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
+ #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
+ #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
+ #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
+ #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
+ #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SEMR  ========================================================== */
+ #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
+ #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
+ #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
+ #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
+ #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
+ #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
+ #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SNFR  ========================================================== */
+ #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
+ #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
+/* =========================================================  SIMR1  ========================================================= */
+ #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
+ #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
+ #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
+ #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SIMR2  ========================================================= */
+ #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
+ #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
+ #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
+ #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SIMR3  ========================================================= */
+ #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
+ #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
+ #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
+ #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
+ #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
+ #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
+ #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
+ #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
+ #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
+ #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
+/* =========================================================  SISR  ========================================================== */
+ #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
+ #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
+/* =========================================================  SPMR  ========================================================== */
+ #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
+ #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
+ #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
+ #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
+ #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
+ #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
+ #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
+/* =========================================================  TDRHL  ========================================================= */
+ #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
+ #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FTDRHL  ========================================================= */
+ #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
+ #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
+ #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FTDRH  ========================================================= */
+ #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
+ #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
+ #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FTDRL  ========================================================= */
+ #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
+ #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  RDRHL  ========================================================= */
+ #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
+ #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
+/* ========================================================  FRDRHL  ========================================================= */
+ #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
+ #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
+ #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
+ #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
+ #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
+ #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
+ #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
+ #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  FRDRH  ========================================================= */
+ #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
+ #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
+ #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
+ #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
+ #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
+ #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
+ #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
+ #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
+ #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
+ #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
+/* =========================================================  FRDRL  ========================================================= */
+ #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
+ #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
+/* =========================================================  MDDR  ========================================================== */
+ #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
+ #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
+/* =========================================================  DCCR  ========================================================== */
+ #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
+ #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
+ #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
+ #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
+ #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
+ #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  FCR  ========================================================== */
+ #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
+ #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
+ #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
+ #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
+ #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
+ #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
+ #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
+ #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
+ #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
+ #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
+ #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
+/* ==========================================================  FDR  ========================================================== */
+ #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
+ #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
+ #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
+ #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
+/* ==========================================================  LSR  ========================================================== */
+ #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
+ #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
+ #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
+ #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
+ #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
+/* ==========================================================  CDR  ========================================================== */
+ #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
+ #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
+/* =========================================================  SPTR  ========================================================== */
+ #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
+ #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
+ #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
+ #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
+ #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SDADC0                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  STC1  ========================================================== */
+ #define R_SDADC0_STC1_VSBIAS_Pos     (8UL)          /*!< VSBIAS (Bit 8)                                        */
+ #define R_SDADC0_STC1_VSBIAS_Msk     (0xf00UL)      /*!< VSBIAS (Bitfield-Mask: 0x0f)                          */
+ #define R_SDADC0_STC1_CLKDIV_Pos     (0UL)          /*!< CLKDIV (Bit 0)                                        */
+ #define R_SDADC0_STC1_CLKDIV_Msk     (0xfUL)        /*!< CLKDIV (Bitfield-Mask: 0x0f)                          */
+ #define R_SDADC0_STC1_SDADLPM_Pos    (7UL)          /*!< SDADLPM (Bit 7)                                       */
+ #define R_SDADC0_STC1_SDADLPM_Msk    (0x80UL)       /*!< SDADLPM (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_STC1_VREFSEL_Pos    (15UL)         /*!< VREFSEL (Bit 15)                                      */
+ #define R_SDADC0_STC1_VREFSEL_Msk    (0x8000UL)     /*!< VREFSEL (Bitfield-Mask: 0x01)                         */
+/* =========================================================  STC2  ========================================================== */
+ #define R_SDADC0_STC2_BGRPON_Pos     (0UL)          /*!< BGRPON (Bit 0)                                        */
+ #define R_SDADC0_STC2_BGRPON_Msk     (0x1UL)        /*!< BGRPON (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_STC2_ADFPWDS_Pos    (2UL)          /*!< ADFPWDS (Bit 2)                                       */
+ #define R_SDADC0_STC2_ADFPWDS_Msk    (0x4UL)        /*!< ADFPWDS (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_STC2_ADCPON_Pos     (1UL)          /*!< ADCPON (Bit 1)                                        */
+ #define R_SDADC0_STC2_ADCPON_Msk     (0x2UL)        /*!< ADCPON (Bitfield-Mask: 0x01)                          */
+/* =========================================================  PGAC  ========================================================== */
+ #define R_SDADC0_PGAC_PGAASN_Pos     (31UL)         /*!< PGAASN (Bit 31)                                       */
+ #define R_SDADC0_PGAC_PGAASN_Msk     (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_PGAC_PGACVE_Pos     (30UL)         /*!< PGACVE (Bit 30)                                       */
+ #define R_SDADC0_PGAC_PGACVE_Msk     (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_PGAC_PGAREV_Pos     (28UL)         /*!< PGAREV (Bit 28)                                       */
+ #define R_SDADC0_PGAC_PGAREV_Msk     (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_PGAC_PGAAVE_Pos     (26UL)         /*!< PGAAVE (Bit 26)                                       */
+ #define R_SDADC0_PGAC_PGAAVE_Msk     (0xc000000UL)  /*!< PGAAVE (Bitfield-Mask: 0x03)                          */
+ #define R_SDADC0_PGAC_PGAAVN_Pos     (24UL)         /*!< PGAAVN (Bit 24)                                       */
+ #define R_SDADC0_PGAC_PGAAVN_Msk     (0x3000000UL)  /*!< PGAAVN (Bitfield-Mask: 0x03)                          */
+ #define R_SDADC0_PGAC_PGACTN_Pos     (21UL)         /*!< PGACTN (Bit 21)                                       */
+ #define R_SDADC0_PGAC_PGACTN_Msk     (0xe00000UL)   /*!< PGACTN (Bitfield-Mask: 0x07)                          */
+ #define R_SDADC0_PGAC_PGACTM_Pos     (16UL)         /*!< PGACTM (Bit 16)                                       */
+ #define R_SDADC0_PGAC_PGACTM_Msk     (0x1f0000UL)   /*!< PGACTM (Bitfield-Mask: 0x1f)                          */
+ #define R_SDADC0_PGAC_PGASEL_Pos     (15UL)         /*!< PGASEL (Bit 15)                                       */
+ #define R_SDADC0_PGAC_PGASEL_Msk     (0x8000UL)     /*!< PGASEL (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_PGAC_PGAPOL_Pos     (14UL)         /*!< PGAPOL (Bit 14)                                       */
+ #define R_SDADC0_PGAC_PGAPOL_Msk     (0x4000UL)     /*!< PGAPOL (Bitfield-Mask: 0x01)                          */
+ #define R_SDADC0_PGAC_PGAOFS_Pos     (8UL)          /*!< PGAOFS (Bit 8)                                        */
+ #define R_SDADC0_PGAC_PGAOFS_Msk     (0x1f00UL)     /*!< PGAOFS (Bitfield-Mask: 0x1f)                          */
+ #define R_SDADC0_PGAC_PGAOSR_Pos     (5UL)          /*!< PGAOSR (Bit 5)                                        */
+ #define R_SDADC0_PGAC_PGAOSR_Msk     (0xe0UL)       /*!< PGAOSR (Bitfield-Mask: 0x07)                          */
+ #define R_SDADC0_PGAC_PGAGC_Pos      (0UL)          /*!< PGAGC (Bit 0)                                         */
+ #define R_SDADC0_PGAC_PGAGC_Msk      (0x1fUL)       /*!< PGAGC (Bitfield-Mask: 0x1f)                           */
+/* =========================================================  ADC1  ========================================================== */
+ #define R_SDADC0_ADC1_PGASLFT_Pos    (20UL)         /*!< PGASLFT (Bit 20)                                      */
+ #define R_SDADC0_ADC1_PGASLFT_Msk    (0x100000UL)   /*!< PGASLFT (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADC1_PGADISC_Pos    (17UL)         /*!< PGADISC (Bit 17)                                      */
+ #define R_SDADC0_ADC1_PGADISC_Msk    (0x20000UL)    /*!< PGADISC (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADC1_PGADISA_Pos    (16UL)         /*!< PGADISA (Bit 16)                                      */
+ #define R_SDADC0_ADC1_PGADISA_Msk    (0x10000UL)    /*!< PGADISA (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADC1_SDADBMP_Pos    (8UL)          /*!< SDADBMP (Bit 8)                                       */
+ #define R_SDADC0_ADC1_SDADBMP_Msk    (0x1f00UL)     /*!< SDADBMP (Bitfield-Mask: 0x1f)                         */
+ #define R_SDADC0_ADC1_SDADTMD_Pos    (4UL)          /*!< SDADTMD (Bit 4)                                       */
+ #define R_SDADC0_ADC1_SDADTMD_Msk    (0x10UL)       /*!< SDADTMD (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADC1_SDADSCM_Pos    (0UL)          /*!< SDADSCM (Bit 0)                                       */
+ #define R_SDADC0_ADC1_SDADSCM_Msk    (0x1UL)        /*!< SDADSCM (Bitfield-Mask: 0x01)                         */
+/* =========================================================  ADC2  ========================================================== */
+ #define R_SDADC0_ADC2_SDADST_Pos     (0UL)          /*!< SDADST (Bit 0)                                        */
+ #define R_SDADC0_ADC2_SDADST_Msk     (0x1UL)        /*!< SDADST (Bitfield-Mask: 0x01)                          */
+/* =========================================================  ADCR  ========================================================== */
+ #define R_SDADC0_ADCR_SDADCRC_Pos    (25UL)         /*!< SDADCRC (Bit 25)                                      */
+ #define R_SDADC0_ADCR_SDADCRC_Msk    (0xe000000UL)  /*!< SDADCRC (Bitfield-Mask: 0x07)                         */
+ #define R_SDADC0_ADCR_SDADCRS_Pos    (24UL)         /*!< SDADCRS (Bit 24)                                      */
+ #define R_SDADC0_ADCR_SDADCRS_Msk    (0x1000000UL)  /*!< SDADCRS (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADCR_SDADCRD_Pos    (0UL)          /*!< SDADCRD (Bit 0)                                       */
+ #define R_SDADC0_ADCR_SDADCRD_Msk    (0xffffffUL)   /*!< SDADCRD (Bitfield-Mask: 0xffffff)                     */
+/* =========================================================  ADAR  ========================================================== */
+ #define R_SDADC0_ADAR_SDADMVC_Pos    (25UL)         /*!< SDADMVC (Bit 25)                                      */
+ #define R_SDADC0_ADAR_SDADMVC_Msk    (0xe000000UL)  /*!< SDADMVC (Bitfield-Mask: 0x07)                         */
+ #define R_SDADC0_ADAR_SDADMVS_Pos    (24UL)         /*!< SDADMVS (Bit 24)                                      */
+ #define R_SDADC0_ADAR_SDADMVS_Msk    (0x1000000UL)  /*!< SDADMVS (Bitfield-Mask: 0x01)                         */
+ #define R_SDADC0_ADAR_SDADMVD_Pos    (0UL)          /*!< SDADMVD (Bit 0)                                       */
+ #define R_SDADC0_ADAR_SDADMVD_Msk    (0xffffffUL)   /*!< SDADMVD (Bitfield-Mask: 0xffffff)                     */
+/* =========================================================  CLBC  ========================================================== */
+ #define R_SDADC0_CLBC_CLBMD_Pos      (0UL)          /*!< CLBMD (Bit 0)                                         */
+ #define R_SDADC0_CLBC_CLBMD_Msk      (0x3UL)        /*!< CLBMD (Bitfield-Mask: 0x03)                           */
+/* ========================================================  CLBSTR  ========================================================= */
+ #define R_SDADC0_CLBSTR_CLBST_Pos    (0UL)          /*!< CLBST (Bit 0)                                         */
+ #define R_SDADC0_CLBSTR_CLBST_Msk    (0x1UL)        /*!< CLBST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  CLBSSR  ========================================================= */
+ #define R_SDADC0_CLBSSR_CLBSS_Pos    (0UL)          /*!< CLBSS (Bit 0)                                         */
+ #define R_SDADC0_CLBSSR_CLBSS_Msk    (0x1UL)        /*!< CLBSS (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SDHI0                                          ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SD_CMD  ========================================================= */
+ #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
+ #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
+ #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
+ #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
+ #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
+ #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
+ #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
+ #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
+ #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
+ #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
+ #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
+/* ========================================================  SD_ARG  ========================================================= */
+ #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
+ #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
+/* ========================================================  SD_ARG1  ======================================================== */
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  SD_STOP  ======================================================== */
+ #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
+ #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
+ #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SD_SECCNT  ======================================================= */
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
+/* =======================================================  SD_RSP10  ======================================================== */
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  SD_RSP1  ======================================================== */
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  SD_RSP32  ======================================================== */
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  SD_RSP3  ======================================================== */
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  SD_RSP54  ======================================================== */
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
+/* ========================================================  SD_RSP5  ======================================================== */
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
+/* =======================================================  SD_RSP76  ======================================================== */
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
+/* ========================================================  SD_RSP7  ======================================================== */
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
+/* =======================================================  SD_INFO1  ======================================================== */
+ #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
+ #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
+ #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
+ #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
+ #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
+ #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
+ #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
+ #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
+ #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
+ #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SD_INFO2  ======================================================== */
+ #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
+ #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
+ #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
+ #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
+ #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
+ #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
+ #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
+ #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
+ #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
+ #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
+ #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
+ #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
+ #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
+ #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
+ #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
+/* =====================================================  SD_INFO1_MASK  ===================================================== */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
+/* =====================================================  SD_INFO2_MASK  ===================================================== */
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SD_CLK_CTRL  ====================================================== */
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
+/* ========================================================  SD_SIZE  ======================================================== */
+ #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
+ #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
+/* =======================================================  SD_OPTION  ======================================================= */
+ #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
+ #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
+ #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
+ #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
+ #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
+ #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
+/* ======================================================  SD_ERR_STS1  ====================================================== */
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SD_ERR_STS2  ====================================================== */
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  SD_BUF0  ======================================================== */
+ #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
+ #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
+/* =======================================================  SDIO_MODE  ======================================================= */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
+ #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
+ #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
+ #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
+ #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
+ #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
+/* ======================================================  SDIO_INFO1  ======================================================= */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
+ #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
+/* ====================================================  SDIO_INFO1_MASK  ==================================================== */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SD_DMAEN  ======================================================== */
+ #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
+ #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SOFT_RST  ======================================================== */
+ #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
+ #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SDIF_MODE  ======================================================= */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  EXT_SWAP  ======================================================== */
+ #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
+ #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
+ #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
+ #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SLCDC                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  LCDM0  ========================================================= */
+ #define R_SLCDC_LCDM0_MDSET_Pos     (6UL)    /*!< MDSET (Bit 6)                                         */
+ #define R_SLCDC_LCDM0_MDSET_Msk     (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03)                           */
+ #define R_SLCDC_LCDM0_LWAVE_Pos     (5UL)    /*!< LWAVE (Bit 5)                                         */
+ #define R_SLCDC_LCDM0_LWAVE_Msk     (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01)                           */
+ #define R_SLCDC_LCDM0_LDTY_Pos      (2UL)    /*!< LDTY (Bit 2)                                          */
+ #define R_SLCDC_LCDM0_LDTY_Msk      (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07)                            */
+ #define R_SLCDC_LCDM0_LBAS_Pos      (0UL)    /*!< LBAS (Bit 0)                                          */
+ #define R_SLCDC_LCDM0_LBAS_Msk      (0x3UL)  /*!< LBAS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  LCDM1  ========================================================= */
+ #define R_SLCDC_LCDM1_LCDON_Pos     (7UL)    /*!< LCDON (Bit 7)                                         */
+ #define R_SLCDC_LCDM1_LCDON_Msk     (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01)                           */
+ #define R_SLCDC_LCDM1_SCOC_Pos      (6UL)    /*!< SCOC (Bit 6)                                          */
+ #define R_SLCDC_LCDM1_SCOC_Msk      (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01)                            */
+ #define R_SLCDC_LCDM1_VLCON_Pos     (5UL)    /*!< VLCON (Bit 5)                                         */
+ #define R_SLCDC_LCDM1_VLCON_Msk     (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01)                           */
+ #define R_SLCDC_LCDM1_BLON_Pos      (4UL)    /*!< BLON (Bit 4)                                          */
+ #define R_SLCDC_LCDM1_BLON_Msk      (0x10UL) /*!< BLON (Bitfield-Mask: 0x01)                            */
+ #define R_SLCDC_LCDM1_LCDSEL_Pos    (3UL)    /*!< LCDSEL (Bit 3)                                        */
+ #define R_SLCDC_LCDM1_LCDSEL_Msk    (0x8UL)  /*!< LCDSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SLCDC_LCDM1_LCDVLM_Pos    (0UL)    /*!< LCDVLM (Bit 0)                                        */
+ #define R_SLCDC_LCDM1_LCDVLM_Msk    (0x1UL)  /*!< LCDVLM (Bitfield-Mask: 0x01)                          */
+/* =========================================================  LCDC0  ========================================================= */
+ #define R_SLCDC_LCDC0_LCDC_Pos      (0UL)    /*!< LCDC (Bit 0)                                          */
+ #define R_SLCDC_LCDC0_LCDC_Msk      (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f)                            */
+/* =========================================================  VLCD  ========================================================== */
+ #define R_SLCDC_VLCD_VLCD_Pos       (0UL)    /*!< VLCD (Bit 0)                                          */
+ #define R_SLCDC_VLCD_VLCD_Msk       (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f)                            */
+/* ==========================================================  SEG  ========================================================== */
+ #define R_SLCDC_SEG_A_Pos           (0UL)    /*!< A (Bit 0)                                             */
+ #define R_SLCDC_SEG_A_Msk           (0xfUL)  /*!< A (Bitfield-Mask: 0x0f)                               */
+ #define R_SLCDC_SEG_B_Pos           (4UL)    /*!< B (Bit 4)                                             */
+ #define R_SLCDC_SEG_B_Msk           (0xf0UL) /*!< B (Bitfield-Mask: 0x0f)                               */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SPI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SPCR  ========================================================== */
+ #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
+ #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
+ #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
+ #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
+ #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
+ #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
+ #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
+ #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
+ #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SSLP  ========================================================== */
+ #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
+ #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
+ #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
+ #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
+ #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SPPCR  ========================================================= */
+ #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
+ #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
+ #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
+ #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
+ #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPSR  ========================================================== */
+ #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
+ #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
+ #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
+ #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
+ #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
+ #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
+ #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
+ #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPDR  ========================================================== */
+/* ========================================================  SPDR_HA  ======================================================== */
+/* ========================================================  SPDR_BY  ======================================================== */
+/* =========================================================  SPSCR  ========================================================= */
+ #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
+ #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPBR  ========================================================== */
+ #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
+ #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
+/* =========================================================  SPDCR  ========================================================= */
+ #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
+ #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
+ #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
+ #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
+ #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  SPCKD  ========================================================= */
+ #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
+ #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SSLND  ========================================================= */
+ #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
+ #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPND  ========================================================== */
+ #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
+ #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
+/* =========================================================  SPCR2  ========================================================= */
+ #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
+ #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
+ #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
+ #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
+ #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
+ #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
+ #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
+/* =========================================================  SPCMD  ========================================================= */
+ #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
+ #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
+ #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
+ #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
+ #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
+ #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
+ #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
+ #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
+ #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
+ #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
+ #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
+ #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
+ #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
+ #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
+ #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
+ #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
+ #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SPDCR2  ========================================================= */
+ #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
+ #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SRAM                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  PARIOAD  ======================================================== */
+ #define R_SRAM_PARIOAD_OAD_Pos              (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_PARIOAD_OAD_Msk              (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+/* =======================================================  SRAMPRCR  ======================================================== */
+ #define R_SRAM_SRAMPRCR_KW_Pos              (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_SRAMPRCR_KW_Msk              (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos        (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
+ #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk        (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
+/* =======================================================  SRAMWTSC  ======================================================== */
+ #define R_SRAM_SRAMWTSC_SRAMHSWTEN_Pos      (4UL)    /*!< SRAMHSWTEN (Bit 4)                                    */
+ #define R_SRAM_SRAMWTSC_SRAMHSWTEN_Msk      (0x10UL) /*!< SRAMHSWTEN (Bitfield-Mask: 0x01)                      */
+ #define R_SRAM_SRAMWTSC_SRAM1WTEN_Pos       (3UL)    /*!< SRAM1WTEN (Bit 3)                                     */
+ #define R_SRAM_SRAMWTSC_SRAM1WTEN_Msk       (0x8UL)  /*!< SRAM1WTEN (Bitfield-Mask: 0x01)                       */
+ #define R_SRAM_SRAMWTSC_SRAM0WTEN_Pos       (2UL)    /*!< SRAM0WTEN (Bit 2)                                     */
+ #define R_SRAM_SRAMWTSC_SRAM0WTEN_Msk       (0x4UL)  /*!< SRAM0WTEN (Bitfield-Mask: 0x01)                       */
+ #define R_SRAM_SRAMWTSC_ECCRAMRDWTEN_Pos    (1UL)    /*!< ECCRAMRDWTEN (Bit 1)                                  */
+ #define R_SRAM_SRAMWTSC_ECCRAMRDWTEN_Msk    (0x2UL)  /*!< ECCRAMRDWTEN (Bitfield-Mask: 0x01)                    */
+ #define R_SRAM_SRAMWTSC_ECCRAMWRWTEN_Pos    (0UL)    /*!< ECCRAMWRWTEN (Bit 0)                                  */
+ #define R_SRAM_SRAMWTSC_ECCRAMWRWTEN_Msk    (0x1UL)  /*!< ECCRAMWRWTEN (Bitfield-Mask: 0x01)                    */
+/* ========================================================  ECCMODE  ======================================================== */
+ #define R_SRAM_ECCMODE_ECCMOD_Pos           (0UL)    /*!< ECCMOD (Bit 0)                                        */
+ #define R_SRAM_ECCMODE_ECCMOD_Msk           (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
+/* ========================================================  ECC2STS  ======================================================== */
+ #define R_SRAM_ECC2STS_ECC2ERR_Pos          (0UL)    /*!< ECC2ERR (Bit 0)                                       */
+ #define R_SRAM_ECC2STS_ECC2ERR_Msk          (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECC1STSEN  ======================================================= */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Pos        (0UL)    /*!< E1STSEN (Bit 0)                                       */
+ #define R_SRAM_ECC1STSEN_E1STSEN_Msk        (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECC1STS  ======================================================== */
+ #define R_SRAM_ECC1STS_ECC1ERR_Pos          (0UL)    /*!< ECC1ERR (Bit 0)                                       */
+ #define R_SRAM_ECC1STS_ECC1ERR_Msk          (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
+/* ========================================================  ECCPRCR  ======================================================== */
+ #define R_SRAM_ECCPRCR_KW_Pos               (1UL)    /*!< KW (Bit 1)                                            */
+ #define R_SRAM_ECCPRCR_KW_Msk               (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Pos          (0UL)    /*!< ECCPRCR (Bit 0)                                       */
+ #define R_SRAM_ECCPRCR_ECCPRCR_Msk          (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
+/* =======================================================  ECCPRCR2  ======================================================== */
+ #define R_SRAM_ECCPRCR2_KW2_Pos             (1UL)    /*!< KW2 (Bit 1)                                           */
+ #define R_SRAM_ECCPRCR2_KW2_Msk             (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos        (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
+ #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk        (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
+/* ========================================================  ECCETST  ======================================================== */
+ #define R_SRAM_ECCETST_TSTBYP_Pos           (0UL)    /*!< TSTBYP (Bit 0)                                        */
+ #define R_SRAM_ECCETST_TSTBYP_Msk           (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  ECCOAD  ========================================================= */
+ #define R_SRAM_ECCOAD_OAD_Pos               (0UL)    /*!< OAD (Bit 0)                                           */
+ #define R_SRAM_ECCOAD_OAD_Msk               (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
+
+/* =========================================================================================================================== */
+/* ================                                           R_SRC                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SRCFCTR  ======================================================== */
+ #define R_SRC_SRCFCTR_SRCFCOE_Pos    (0UL)          /*!< SRCFCOE (Bit 0)                                       */
+ #define R_SRC_SRCFCTR_SRCFCOE_Msk    (0x3fffffUL)   /*!< SRCFCOE (Bitfield-Mask: 0x3fffff)                     */
+/* =========================================================  SRCID  ========================================================= */
+ #define R_SRC_SRCID_SRCID_Pos        (0UL)          /*!< SRCID (Bit 0)                                         */
+ #define R_SRC_SRCID_SRCID_Msk        (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff)                     */
+/* =========================================================  SRCOD  ========================================================= */
+ #define R_SRC_SRCOD_SRCOD_Pos        (0UL)          /*!< SRCOD (Bit 0)                                         */
+ #define R_SRC_SRCOD_SRCOD_Msk        (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff)                     */
+/* =======================================================  SRCIDCTRL  ======================================================= */
+ #define R_SRC_SRCIDCTRL_IED_Pos      (9UL)          /*!< IED (Bit 9)                                           */
+ #define R_SRC_SRCIDCTRL_IED_Msk      (0x200UL)      /*!< IED (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCIDCTRL_IEN_Pos      (8UL)          /*!< IEN (Bit 8)                                           */
+ #define R_SRC_SRCIDCTRL_IEN_Msk      (0x100UL)      /*!< IEN (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCIDCTRL_IFTRG_Pos    (0UL)          /*!< IFTRG (Bit 0)                                         */
+ #define R_SRC_SRCIDCTRL_IFTRG_Msk    (0x3UL)        /*!< IFTRG (Bitfield-Mask: 0x03)                           */
+/* ========================================================  SRCCTRL  ======================================================== */
+ #define R_SRC_SRCCTRL_FICRAE_Pos     (15UL)         /*!< FICRAE (Bit 15)                                       */
+ #define R_SRC_SRCCTRL_FICRAE_Msk     (0x8000UL)     /*!< FICRAE (Bitfield-Mask: 0x01)                          */
+ #define R_SRC_SRCCTRL_CEEN_Pos       (13UL)         /*!< CEEN (Bit 13)                                         */
+ #define R_SRC_SRCCTRL_CEEN_Msk       (0x2000UL)     /*!< CEEN (Bitfield-Mask: 0x01)                            */
+ #define R_SRC_SRCCTRL_SRCEN_Pos      (12UL)         /*!< SRCEN (Bit 12)                                        */
+ #define R_SRC_SRCCTRL_SRCEN_Msk      (0x1000UL)     /*!< SRCEN (Bitfield-Mask: 0x01)                           */
+ #define R_SRC_SRCCTRL_UDEN_Pos       (11UL)         /*!< UDEN (Bit 11)                                         */
+ #define R_SRC_SRCCTRL_UDEN_Msk       (0x800UL)      /*!< UDEN (Bitfield-Mask: 0x01)                            */
+ #define R_SRC_SRCCTRL_OVEN_Pos       (10UL)         /*!< OVEN (Bit 10)                                         */
+ #define R_SRC_SRCCTRL_OVEN_Msk       (0x400UL)      /*!< OVEN (Bitfield-Mask: 0x01)                            */
+ #define R_SRC_SRCCTRL_FL_Pos         (9UL)          /*!< FL (Bit 9)                                            */
+ #define R_SRC_SRCCTRL_FL_Msk         (0x200UL)      /*!< FL (Bitfield-Mask: 0x01)                              */
+ #define R_SRC_SRCCTRL_CL_Pos         (8UL)          /*!< CL (Bit 8)                                            */
+ #define R_SRC_SRCCTRL_CL_Msk         (0x100UL)      /*!< CL (Bitfield-Mask: 0x01)                              */
+ #define R_SRC_SRCCTRL_IFS_Pos        (4UL)          /*!< IFS (Bit 4)                                           */
+ #define R_SRC_SRCCTRL_IFS_Msk        (0xf0UL)       /*!< IFS (Bitfield-Mask: 0x0f)                             */
+ #define R_SRC_SRCCTRL_OFS_Pos        (0UL)          /*!< OFS (Bit 0)                                           */
+ #define R_SRC_SRCCTRL_OFS_Msk        (0x7UL)        /*!< OFS (Bitfield-Mask: 0x07)                             */
+/* =======================================================  SRCODCTRL  ======================================================= */
+ #define R_SRC_SRCODCTRL_OCH_Pos      (10UL)         /*!< OCH (Bit 10)                                          */
+ #define R_SRC_SRCODCTRL_OCH_Msk      (0x400UL)      /*!< OCH (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCODCTRL_OED_Pos      (9UL)          /*!< OED (Bit 9)                                           */
+ #define R_SRC_SRCODCTRL_OED_Msk      (0x200UL)      /*!< OED (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCODCTRL_OEN_Pos      (8UL)          /*!< OEN (Bit 8)                                           */
+ #define R_SRC_SRCODCTRL_OEN_Msk      (0x100UL)      /*!< OEN (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCODCTRL_OFTRG_Pos    (0UL)          /*!< OFTRG (Bit 0)                                         */
+ #define R_SRC_SRCODCTRL_OFTRG_Msk    (0x3UL)        /*!< OFTRG (Bitfield-Mask: 0x03)                           */
+/* ========================================================  SRCSTAT  ======================================================== */
+ #define R_SRC_SRCSTAT_OFDN_Pos       (11UL)         /*!< OFDN (Bit 11)                                         */
+ #define R_SRC_SRCSTAT_OFDN_Msk       (0xf800UL)     /*!< OFDN (Bitfield-Mask: 0x1f)                            */
+ #define R_SRC_SRCSTAT_IFDN_Pos       (7UL)          /*!< IFDN (Bit 7)                                          */
+ #define R_SRC_SRCSTAT_IFDN_Msk       (0x780UL)      /*!< IFDN (Bitfield-Mask: 0x0f)                            */
+ #define R_SRC_SRCSTAT_CEF_Pos        (5UL)          /*!< CEF (Bit 5)                                           */
+ #define R_SRC_SRCSTAT_CEF_Msk        (0x20UL)       /*!< CEF (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCSTAT_FLF_Pos        (4UL)          /*!< FLF (Bit 4)                                           */
+ #define R_SRC_SRCSTAT_FLF_Msk        (0x10UL)       /*!< FLF (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCSTAT_UDF_Pos        (3UL)          /*!< UDF (Bit 3)                                           */
+ #define R_SRC_SRCSTAT_UDF_Msk        (0x8UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCSTAT_OVF_Pos        (2UL)          /*!< OVF (Bit 2)                                           */
+ #define R_SRC_SRCSTAT_OVF_Msk        (0x4UL)        /*!< OVF (Bitfield-Mask: 0x01)                             */
+ #define R_SRC_SRCSTAT_IINT_Pos       (1UL)          /*!< IINT (Bit 1)                                          */
+ #define R_SRC_SRCSTAT_IINT_Msk       (0x2UL)        /*!< IINT (Bitfield-Mask: 0x01)                            */
+ #define R_SRC_SRCSTAT_OINT_Pos       (0UL)          /*!< OINT (Bit 0)                                          */
+ #define R_SRC_SRCSTAT_OINT_Msk       (0x1UL)        /*!< OINT (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                          R_SSI0                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SSICR  ========================================================= */
+ #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
+ #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
+ #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
+ #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
+ #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
+ #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
+ #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
+ #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
+ #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
+ #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
+ #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
+ #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
+ #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
+ #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
+ #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
+ #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
+ #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
+ #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
+ #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
+ #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
+ #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
+ #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
+ #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
+ #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
+/* =========================================================  SSISR  ========================================================= */
+ #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
+ #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
+ #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
+ #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
+ #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
+ #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
+ #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
+ #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
+ #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
+ #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
+ #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
+ #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
+ #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
+/* ========================================================  SSIFCR  ========================================================= */
+ #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
+ #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
+ #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
+ #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
+ #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
+ #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
+ #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
+ #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
+ #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
+ #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
+ #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
+/* ========================================================  SSIFSR  ========================================================= */
+ #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
+ #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
+ #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
+ #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
+ #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
+ #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
+ #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
+/* ========================================================  SSIFTDR  ======================================================== */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
+ #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFTDR16  ======================================================= */
+/* =======================================================  SSIFTDR8  ======================================================== */
+/* ========================================================  SSIFRDR  ======================================================== */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
+ #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
+/* =======================================================  SSIFRDR16  ======================================================= */
+/* =======================================================  SSIFRDR8  ======================================================== */
+/* ========================================================  SSIOFR  ========================================================= */
+ #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
+ #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
+ #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
+ #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
+ #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
+ #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SSISCR  ========================================================= */
+ #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
+ #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
+ #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
+ #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_SYSTEM                                          ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  SBYCR  ========================================================= */
+ #define R_SYSTEM_SBYCR_SSBY_Pos                (15UL)         /*!< SSBY (Bit 15)                                         */
+ #define R_SYSTEM_SBYCR_SSBY_Msk                (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SBYCR_OPE_Pos                 (14UL)         /*!< OPE (Bit 14)                                          */
+ #define R_SYSTEM_SBYCR_OPE_Msk                 (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  MSTPCRA  ======================================================== */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Pos           (22UL)         /*!< MSTPA22 (Bit 22)                                      */
+ #define R_SYSTEM_MSTPCRA_MSTPA22_Msk           (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Pos            (7UL)          /*!< MSTPA7 (Bit 7)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA7_Msk            (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Pos            (6UL)          /*!< MSTPA6 (Bit 6)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA6_Msk            (0x40UL)       /*!< MSTPA6 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Pos            (5UL)          /*!< MSTPA5 (Bit 5)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA5_Msk            (0x20UL)       /*!< MSTPA5 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Pos            (1UL)          /*!< MSTPA1 (Bit 1)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA1_Msk            (0x2UL)        /*!< MSTPA1 (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Pos            (0UL)          /*!< MSTPA0 (Bit 0)                                        */
+ #define R_SYSTEM_MSTPCRA_MSTPA0_Msk            (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
+/* =======================================================  SCKDIVCR  ======================================================== */
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos              (28UL)         /*!< FCK (Bit 28)                                          */
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk              (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos              (24UL)         /*!< ICK (Bit 24)                                          */
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk              (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos              (16UL)         /*!< BCK (Bit 16)                                          */
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk              (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos             (12UL)         /*!< PCKA (Bit 12)                                         */
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk             (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos             (8UL)          /*!< PCKB (Bit 8)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk             (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos             (4UL)          /*!< PCKC (Bit 4)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk             (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos             (0UL)          /*!< PCKD (Bit 0)                                          */
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk             (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
+/* =======================================================  SCKDIVCR2  ======================================================= */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Pos             (4UL)          /*!< UCK (Bit 4)                                           */
+ #define R_SYSTEM_SCKDIVCR2_UCK_Msk             (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
+/* ========================================================  SCKSCR  ========================================================= */
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk              (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
+/* ========================================================  PLLCCR  ========================================================= */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos             (8UL)          /*!< PLLMUL (Bit 8)                                        */
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk             (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos           (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk           (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos             (0UL)          /*!< PLIDIV (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk             (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
+/* =========================================================  PLLCR  ========================================================= */
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos              (0UL)          /*!< PLLSTP (Bit 0)                                        */
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk              (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
+/* ========================================================  PLLCCR2  ======================================================== */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Pos            (6UL)          /*!< PLODIV (Bit 6)                                        */
+ #define R_SYSTEM_PLLCCR2_PLODIV_Msk            (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Pos            (0UL)          /*!< PLLMUL (Bit 0)                                        */
+ #define R_SYSTEM_PLLCCR2_PLLMUL_Msk            (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
+/* =========================================================  BCKCR  ========================================================= */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos             (0UL)          /*!< BCLKDIV (Bit 0)                                       */
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk             (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MEMWAIT  ======================================================== */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos           (0UL)          /*!< MEMWAIT (Bit 0)                                       */
+ #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk           (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
+/* ========================================================  MOSCCR  ========================================================= */
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos              (0UL)          /*!< MOSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk              (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  HOCOCR  ========================================================= */
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos              (0UL)          /*!< HCSTP (Bit 0)                                         */
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk              (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  MOCOCR  ========================================================= */
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos              (0UL)          /*!< MCSTP (Bit 0)                                         */
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk              (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR1  ========================================================= */
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos              (0UL)          /*!< FLLEN (Bit 0)                                         */
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk              (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
+/* ========================================================  FLLCR2  ========================================================= */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos            (0UL)          /*!< FLLCNTL (Bit 0)                                       */
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk            (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
+/* =========================================================  OSCSF  ========================================================= */
+ #define R_SYSTEM_OSCSF_PLLSF_Pos               (5UL)          /*!< PLLSF (Bit 5)                                         */
+ #define R_SYSTEM_OSCSF_PLLSF_Msk               (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos              (3UL)          /*!< MOSCSF (Bit 3)                                        */
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk              (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos              (0UL)          /*!< HOCOSF (Bit 0)                                        */
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk              (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
+/* =========================================================  CKOCR  ========================================================= */
+ #define R_SYSTEM_CKOCR_CKOEN_Pos               (7UL)          /*!< CKOEN (Bit 7)                                         */
+ #define R_SYSTEM_CKOCR_CKOEN_Msk               (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_CKOCR_CKODIV_Pos              (4UL)          /*!< CKODIV (Bit 4)                                        */
+ #define R_SYSTEM_CKOCR_CKODIV_Msk              (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
+ #define R_SYSTEM_CKOCR_CKOSEL_Pos              (0UL)          /*!< CKOSEL (Bit 0)                                        */
+ #define R_SYSTEM_CKOCR_CKOSEL_Msk              (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
+/* ========================================================  TRCKCR  ========================================================= */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos             (7UL)          /*!< TRCKEN (Bit 7)                                        */
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk             (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Pos               (0UL)          /*!< TRCK (Bit 0)                                          */
+ #define R_SYSTEM_TRCKCR_TRCK_Msk               (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  OSTDCR  ========================================================= */
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos              (7UL)          /*!< OSTDE (Bit 7)                                         */
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk              (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos             (0UL)          /*!< OSTDIE (Bit 0)                                        */
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk             (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
+/* ========================================================  OSTDSR  ========================================================= */
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos              (0UL)          /*!< OSTDF (Bit 0)                                         */
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk              (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
+/* =======================================================  SLCDSCKCR  ======================================================= */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos        (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk        (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos       (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
+ #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk       (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
+/* ========================================================  EBCKOCR  ======================================================== */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos           (0UL)          /*!< EBCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk           (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  SDCKOCR  ======================================================== */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos           (0UL)          /*!< SDCKOEN (Bit 0)                                       */
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk           (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
+/* =======================================================  MOCOUTCR  ======================================================== */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos         (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk         (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =======================================================  HOCOUTCR  ======================================================== */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos         (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk         (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* =========================================================  SNZCR  ========================================================= */
+ #define R_SYSTEM_SNZCR_SNZE_Pos                (7UL)          /*!< SNZE (Bit 7)                                          */
+ #define R_SYSTEM_SNZCR_SNZE_Msk                (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos            (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk            (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos            (0UL)          /*!< RXDREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk            (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SNZEDCR  ======================================================== */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos         (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk         (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos          (6UL)          /*!< AD1UMTED (Bit 6)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk          (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos          (5UL)          /*!< AD1MATED (Bit 5)                                      */
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk          (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos          (4UL)          /*!< AD0UMTED (Bit 4)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk          (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos          (3UL)          /*!< AD0MATED (Bit 3)                                      */
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk          (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos          (2UL)          /*!< DTCNZRED (Bit 2)                                      */
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk          (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos           (1UL)          /*!< DTCZRED (Bit 1)                                       */
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk           (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos         (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk         (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SNZREQCR  ======================================================== */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos       (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk       (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos       (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk       (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos       (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk       (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos       (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk       (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos       (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk       (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos       (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk       (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos       (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk       (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos       (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk       (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos         (0UL)          /*!< SNZREQEN (Bit 0)                                      */
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk         (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FLSTOP  ========================================================= */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Pos             (4UL)          /*!< FLSTPF (Bit 4)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTPF_Msk             (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Pos             (0UL)          /*!< FLSTOP (Bit 0)                                        */
+ #define R_SYSTEM_FLSTOP_FLSTOP_Msk             (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
+/* =========================================================  PSMCR  ========================================================= */
+ #define R_SYSTEM_PSMCR_PSMC_Pos                (0UL)          /*!< PSMC (Bit 0)                                          */
+ #define R_SYSTEM_PSMCR_PSMC_Msk                (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
+/* =========================================================  OPCCR  ========================================================= */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos             (4UL)          /*!< OPCMTSF (Bit 4)                                       */
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk             (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_OPCCR_OPCM_Pos                (0UL)          /*!< OPCM (Bit 0)                                          */
+ #define R_SYSTEM_OPCCR_OPCM_Msk                (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
+/* ========================================================  SOPCCR  ========================================================= */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos           (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk           (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos              (0UL)          /*!< SOPCM (Bit 0)                                         */
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk              (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
+/* =======================================================  MOSCWTCR  ======================================================== */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos             (0UL)          /*!< MSTS (Bit 0)                                          */
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk             (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
+/* =======================================================  HOCOWTCR  ======================================================== */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos             (0UL)          /*!< HSTS (Bit 0)                                          */
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk             (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
+/* ========================================================  RSTSR1  ========================================================= */
+ #define R_SYSTEM_RSTSR1_SPERF_Pos              (12UL)         /*!< SPERF (Bit 12)                                        */
+ #define R_SYSTEM_RSTSR1_SPERF_Msk              (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Pos             (11UL)         /*!< BUSMRF (Bit 11)                                       */
+ #define R_SYSTEM_RSTSR1_BUSMRF_Msk             (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Pos             (10UL)         /*!< BUSSRF (Bit 10)                                       */
+ #define R_SYSTEM_RSTSR1_BUSSRF_Msk             (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR1_REERF_Pos              (9UL)          /*!< REERF (Bit 9)                                         */
+ #define R_SYSTEM_RSTSR1_REERF_Msk              (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_RPERF_Pos              (8UL)          /*!< RPERF (Bit 8)                                         */
+ #define R_SYSTEM_RSTSR1_RPERF_Msk              (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_SWRF_Pos               (2UL)          /*!< SWRF (Bit 2)                                          */
+ #define R_SYSTEM_RSTSR1_SWRF_Msk               (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos              (1UL)          /*!< WDTRF (Bit 1)                                         */
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk              (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos             (0UL)          /*!< IWDTRF (Bit 0)                                        */
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk             (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
+/* ========================================================  STCONR  ========================================================= */
+ #define R_SYSTEM_STCONR_STCON_Pos              (0UL)          /*!< STCON (Bit 0)                                         */
+ #define R_SYSTEM_STCONR_STCON_Msk              (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LVD1CR1  ======================================================== */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos            (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk            (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos            (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk            (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  LVD2CR1  ======================================================== */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos            (2UL)          /*!< IRQSEL (Bit 2)                                        */
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk            (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos            (0UL)          /*!< IDTSEL (Bit 0)                                        */
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk            (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
+/* ========================================================  USBCKCR  ======================================================== */
+ #define R_SYSTEM_USBCKCR_USBCLKSEL_Pos         (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
+ #define R_SYSTEM_USBCKCR_USBCLKSEL_Msk         (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
+/* =======================================================  SDADCCKCR  ======================================================= */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos      (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk      (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos       (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
+ #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk       (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
+/* ========================================================  LVD1SR  ========================================================= */
+ #define R_SYSTEM_LVD1SR_MON_Pos                (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD1SR_MON_Msk                (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD1SR_DET_Pos                (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD1SR_DET_Msk                (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2SR  ========================================================= */
+ #define R_SYSTEM_LVD2SR_MON_Pos                (1UL)          /*!< MON (Bit 1)                                           */
+ #define R_SYSTEM_LVD2SR_MON_Msk                (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
+ #define R_SYSTEM_LVD2SR_DET_Pos                (0UL)          /*!< DET (Bit 0)                                           */
+ #define R_SYSTEM_LVD2SR_DET_Msk                (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
+/* =========================================================  PRCR  ========================================================== */
+ #define R_SYSTEM_PRCR_PRKEY_Pos                (8UL)          /*!< PRKEY (Bit 8)                                         */
+ #define R_SYSTEM_PRCR_PRKEY_Msk                (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
+ #define R_SYSTEM_PRCR_PRC3_Pos                 (3UL)          /*!< PRC3 (Bit 3)                                          */
+ #define R_SYSTEM_PRCR_PRC3_Msk                 (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC1_Pos                 (1UL)          /*!< PRC1 (Bit 1)                                          */
+ #define R_SYSTEM_PRCR_PRC1_Msk                 (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_PRCR_PRC0_Pos                 (0UL)          /*!< PRC0 (Bit 0)                                          */
+ #define R_SYSTEM_PRCR_PRC0_Msk                 (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
+/* ========================================================  DPSIER0  ======================================================== */
+ #define R_SYSTEM_DPSIER0_DIRQE_Pos             (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER0_DIRQE_Msk             (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER1  ======================================================== */
+ #define R_SYSTEM_DPSIER1_DIRQE_Pos             (0UL)          /*!< DIRQE (Bit 0)                                         */
+ #define R_SYSTEM_DPSIER1_DIRQE_Msk             (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIER2  ======================================================== */
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos             (4UL)          /*!< DNMIE (Bit 4)                                         */
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk             (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos           (3UL)          /*!< DRTCAIE (Bit 3)                                       */
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk           (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos          (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk          (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Pos           (1UL)          /*!< DLVD2IE (Bit 1)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD2IE_Msk           (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Pos           (0UL)          /*!< DLVD1IE (Bit 0)                                       */
+ #define R_SYSTEM_DPSIER2_DLVD1IE_Msk           (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIER3  ======================================================== */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Pos           (2UL)          /*!< DAGT1IE (Bit 2)                                       */
+ #define R_SYSTEM_DPSIER3_DAGT1IE_Msk           (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos          (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk          (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos          (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk          (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPSIFR0  ======================================================== */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Pos             (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR0_DIRQF_Msk             (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR1  ======================================================== */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Pos             (0UL)          /*!< DIRQF (Bit 0)                                         */
+ #define R_SYSTEM_DPSIFR1_DIRQF_Msk             (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPSIFR2  ======================================================== */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos             (4UL)          /*!< DNMIF (Bit 4)                                         */
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk             (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos           (3UL)          /*!< DRTCAIF (Bit 3)                                       */
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk           (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos          (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk          (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos           (1UL)          /*!< DLVD2IF (Bit 1)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk           (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos           (0UL)          /*!< DLVD1IF (Bit 0)                                       */
+ #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk           (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPSIFR3  ======================================================== */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos           (2UL)          /*!< DAGT1IF (Bit 2)                                       */
+ #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk           (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos          (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk          (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos          (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk          (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
+/* =======================================================  DPSIEGR0  ======================================================== */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos           (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk           (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR1  ======================================================== */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos           (0UL)          /*!< DIRQEG (Bit 0)                                        */
+ #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk           (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
+/* =======================================================  DPSIEGR2  ======================================================== */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos           (4UL)          /*!< DNMIEG (Bit 4)                                        */
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk           (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos         (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk         (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos         (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
+ #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk         (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
+/* ========================================================  DPSBYCR  ======================================================== */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos             (7UL)          /*!< DPSBY (Bit 7)                                         */
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk             (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos            (6UL)          /*!< IOKEEP (Bit 6)                                        */
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk            (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos           (0UL)          /*!< DEEPCUT (Bit 0)                                       */
+ #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk           (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
+/* ========================================================  SYOCDCR  ======================================================== */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos             (7UL)          /*!< DBGEN (Bit 7)                                         */
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk             (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos             (0UL)          /*!< DOCDF (Bit 0)                                         */
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk             (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
+/* =========================================================  MOMCR  ========================================================= */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Pos           (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
+ #define R_SYSTEM_MOMCR_AUTODRVEN_Msk           (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_MOMCR_MOSEL_Pos               (6UL)          /*!< MOSEL (Bit 6)                                         */
+ #define R_SYSTEM_MOMCR_MOSEL_Msk               (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_MOMCR_MODRV0_Pos              (4UL)          /*!< MODRV0 (Bit 4)                                        */
+ #define R_SYSTEM_MOMCR_MODRV0_Msk              (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
+ #define R_SYSTEM_MOMCR_MODRV1_Pos              (3UL)          /*!< MODRV1 (Bit 3)                                        */
+ #define R_SYSTEM_MOMCR_MODRV1_Msk              (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  RSTSR0  ========================================================= */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos            (7UL)          /*!< DPSRSTF (Bit 7)                                       */
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk            (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos             (3UL)          /*!< LVD2RF (Bit 3)                                        */
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk             (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos             (2UL)          /*!< LVD1RF (Bit 2)                                        */
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk             (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos             (1UL)          /*!< LVD0RF (Bit 1)                                        */
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk             (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_RSTSR0_PORF_Pos               (0UL)          /*!< PORF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR0_PORF_Msk               (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  RSTSR2  ========================================================= */
+ #define R_SYSTEM_RSTSR2_CWSF_Pos               (0UL)          /*!< CWSF (Bit 0)                                          */
+ #define R_SYSTEM_RSTSR2_CWSF_Msk               (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
+/* ========================================================  LVCMPCR  ======================================================== */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos             (6UL)          /*!< LVD2E (Bit 6)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk             (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos             (5UL)          /*!< LVD1E (Bit 5)                                         */
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk             (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  LVDLVLR  ======================================================== */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos           (5UL)          /*!< LVD2LVL (Bit 5)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk           (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos           (0UL)          /*!< LVD1LVL (Bit 0)                                       */
+ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk           (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
+/* ========================================================  LVD1CR0  ======================================================== */
+ #define R_SYSTEM_LVD1CR0_RN_Pos                (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD1CR0_RN_Msk                (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_RI_Pos                (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD1CR0_RI_Msk                (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos             (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk             (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos              (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk              (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos             (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk             (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Pos               (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD1CR0_RIE_Msk               (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  LVD2CR0  ======================================================== */
+ #define R_SYSTEM_LVD2CR0_RN_Pos                (7UL)          /*!< RN (Bit 7)                                            */
+ #define R_SYSTEM_LVD2CR0_RN_Msk                (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_RI_Pos                (6UL)          /*!< RI (Bit 6)                                            */
+ #define R_SYSTEM_LVD2CR0_RI_Msk                (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos             (4UL)          /*!< FSAMP (Bit 4)                                         */
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk             (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos              (2UL)          /*!< CMPE (Bit 2)                                          */
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk              (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos             (1UL)          /*!< DFDIS (Bit 1)                                         */
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk             (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Pos               (0UL)          /*!< RIE (Bit 0)                                           */
+ #define R_SYSTEM_LVD2CR0_RIE_Msk               (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
+/* ========================================================  VBTCR1  ========================================================= */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos           (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
+ #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk           (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  SOSCCR  ========================================================= */
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos              (0UL)          /*!< SOSTP (Bit 0)                                         */
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk              (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
+/* =========================================================  SOMCR  ========================================================= */
+ #define R_SYSTEM_SOMCR_SODRV_Pos               (0UL)          /*!< SODRV (Bit 0)                                         */
+ #define R_SYSTEM_SOMCR_SODRV_Msk               (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
+/* ========================================================  LOCOCR  ========================================================= */
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos              (0UL)          /*!< LCSTP (Bit 0)                                         */
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk              (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
+/* =======================================================  LOCOUTCR  ======================================================== */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos         (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk         (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
+/* ========================================================  VBTCR2  ========================================================= */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos          (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
+ #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk          (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos           (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
+ #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk           (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
+/* =========================================================  VBTSR  ========================================================= */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Pos             (4UL)          /*!< VBTRVLD (Bit 4)                                       */
+ #define R_SYSTEM_VBTSR_VBTRVLD_Msk             (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Pos             (1UL)          /*!< VBTBLDF (Bit 1)                                       */
+ #define R_SYSTEM_VBTSR_VBTBLDF_Msk             (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTSR_VBTRDF_Pos              (0UL)          /*!< VBTRDF (Bit 0)                                        */
+ #define R_SYSTEM_VBTSR_VBTRDF_Msk              (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
+/* =======================================================  VBTCMPCR  ======================================================== */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos          (0UL)          /*!< VBTCMPE (Bit 0)                                       */
+ #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk          (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  VBTLVDICR  ======================================================= */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos      (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk      (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos        (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
+ #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk        (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTWCTLR  ======================================================== */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Pos             (0UL)          /*!< VWEN (Bit 0)                                          */
+ #define R_SYSTEM_VBTWCTLR_VWEN_Msk             (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
+/* ======================================================  VBTWCH0OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos    (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk    (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos    (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk    (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos     (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk     (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos     (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk     (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos     (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk     (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH1OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos    (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk    (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos    (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk    (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos     (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk     (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos     (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk     (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos     (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk     (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
+/* ======================================================  VBTWCH2OTSR  ====================================================== */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos    (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk    (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos    (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk    (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos     (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk     (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos     (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk     (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos     (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
+ #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk     (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
+/* =======================================================  VBTICTLR  ======================================================== */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos         (2UL)          /*!< VCH2INEN (Bit 2)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk         (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos         (1UL)          /*!< VCH1INEN (Bit 1)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk         (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos         (0UL)          /*!< VCH0INEN (Bit 0)                                      */
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk         (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  VBTOCTLR  ======================================================== */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos        (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk        (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos        (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
+ #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk        (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos        (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
+ #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk        (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos          (2UL)          /*!< VCH2OEN (Bit 2)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk          (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos          (1UL)          /*!< VCH1OEN (Bit 1)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk          (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos          (0UL)          /*!< VCH0OEN (Bit 0)                                       */
+ #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk          (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
+/* ========================================================  VBTWTER  ======================================================== */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Pos            (5UL)          /*!< VAGTUE (Bit 5)                                        */
+ #define R_SYSTEM_VBTWTER_VAGTUE_Msk            (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Pos            (4UL)          /*!< VRTCAE (Bit 4)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCAE_Msk            (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Pos            (3UL)          /*!< VRTCIE (Bit 3)                                        */
+ #define R_SYSTEM_VBTWTER_VRTCIE_Msk            (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWTER_VCH2E_Pos             (2UL)          /*!< VCH2E (Bit 2)                                         */
+ #define R_SYSTEM_VBTWTER_VCH2E_Msk             (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH1E_Pos             (1UL)          /*!< VCH1E (Bit 1)                                         */
+ #define R_SYSTEM_VBTWTER_VCH1E_Msk             (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWTER_VCH0E_Pos             (0UL)          /*!< VCH0E (Bit 0)                                         */
+ #define R_SYSTEM_VBTWTER_VCH0E_Msk             (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTWEGR  ======================================================== */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Pos            (2UL)          /*!< VCH2EG (Bit 2)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH2EG_Msk            (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Pos            (1UL)          /*!< VCH1EG (Bit 1)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH1EG_Msk            (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Pos            (0UL)          /*!< VCH0EG (Bit 0)                                        */
+ #define R_SYSTEM_VBTWEGR_VCH0EG_Msk            (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
+/* ========================================================  VBTWFR  ========================================================= */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Pos             (5UL)          /*!< VAGTUF (Bit 5)                                        */
+ #define R_SYSTEM_VBTWFR_VAGTUF_Msk             (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Pos             (4UL)          /*!< VRTCAF (Bit 4)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCAF_Msk             (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Pos             (3UL)          /*!< VRTCIF (Bit 3)                                        */
+ #define R_SYSTEM_VBTWFR_VRTCIF_Msk             (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
+ #define R_SYSTEM_VBTWFR_VCH2F_Pos              (2UL)          /*!< VCH2F (Bit 2)                                         */
+ #define R_SYSTEM_VBTWFR_VCH2F_Msk              (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH1F_Pos              (1UL)          /*!< VCH1F (Bit 1)                                         */
+ #define R_SYSTEM_VBTWFR_VCH1F_Msk              (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
+ #define R_SYSTEM_VBTWFR_VCH0F_Pos              (0UL)          /*!< VCH0F (Bit 0)                                         */
+ #define R_SYSTEM_VBTWFR_VCH0F_Msk              (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
+/* ========================================================  VBTBKR  ========================================================= */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
+ #define R_SYSTEM_VBTBKR_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
+/* ========================================================  FWEPROR  ======================================================== */
+ #define R_SYSTEM_FWEPROR_FLWE_Pos              (0UL)          /*!< FLWE (Bit 0)                                          */
+ #define R_SYSTEM_FWEPROR_FLWE_Msk              (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
+
+/* =========================================================================================================================== */
+/* ================                                           R_TSN                                           ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  TSCDRH  ========================================================= */
+ #define R_TSN_TSCDRH_TSCDRH_Pos    (0UL)    /*!< TSCDRH (Bit 0)                                        */
+ #define R_TSN_TSCDRH_TSCDRH_Msk    (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff)                          */
+/* ========================================================  TSCDRL  ========================================================= */
+ #define R_TSN_TSCDRL_TSCDRL_Pos    (0UL)    /*!< TSCDRL (Bit 0)                                        */
+ #define R_TSN_TSCDRL_TSCDRL_Msk    (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff)                          */
+
+/* =========================================================================================================================== */
+/* ================                                        R_TSN_CTRL                                         ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  TSCR  ========================================================== */
+ #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
+ #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
+ #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
+ #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
+
+/* =========================================================================================================================== */
+/* ================                                         R_USB_FS0                                         ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================  SYSCFG  ========================================================= */
+ #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
+ #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
+ #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
+ #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
+ #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
+ #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
+ #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
+ #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
+/* ========================================================  BUSWAIT  ======================================================== */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
+ #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
+/* ========================================================  SYSSTS0  ======================================================== */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
+ #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
+ #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
+ #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
+ #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
+ #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
+/* ========================================================  PLLSTA  ========================================================= */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
+/* =======================================================  DVSTCTR0  ======================================================== */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
+ #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
+ #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
+ #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
+ #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
+ #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
+/* =======================================================  TESTMODE  ======================================================== */
+ #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
+ #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
+/* ========================================================  CFIFOL  ========================================================= */
+/* ========================================================  CFIFOLL  ======================================================== */
+/* =========================================================  CFIFO  ========================================================= */
+/* ========================================================  CFIFOH  ========================================================= */
+/* ========================================================  CFIFOHH  ======================================================== */
+/* ========================================================  D0FIFOL  ======================================================== */
+/* =======================================================  D0FIFOLL  ======================================================== */
+/* ========================================================  D0FIFO  ========================================================= */
+/* ========================================================  D0FIFOH  ======================================================== */
+/* =======================================================  D0FIFOHH  ======================================================== */
+/* ========================================================  D1FIFOL  ======================================================== */
+/* =======================================================  D1FIFOLL  ======================================================== */
+/* ========================================================  D1FIFO  ========================================================= */
+/* ========================================================  D1FIFOH  ======================================================== */
+/* =======================================================  D1FIFOHH  ======================================================== */
+/* =======================================================  CFIFOSEL  ======================================================== */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
+ #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  CFIFOCTR  ======================================================== */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D0FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D0FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* =======================================================  D1FIFOSEL  ======================================================= */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
+ #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
+ #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  D1FIFOCTR  ======================================================= */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
+/* ========================================================  INTENB0  ======================================================== */
+ #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
+ #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
+ #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
+ #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
+ #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
+ #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
+ #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
+ #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
+ #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTENB1  ======================================================== */
+ #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
+ #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
+ #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
+ #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
+ #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
+ #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
+ #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
+ #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
+/* ========================================================  BRDYENB  ======================================================== */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  NRDYENB  ======================================================== */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BEMPENB  ======================================================== */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
+/* ========================================================  SOFCFG  ========================================================= */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
+ #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
+ #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
+ #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSET  ========================================================= */
+ #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
+ #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
+ #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
+ #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
+ #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
+ #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
+ #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
+ #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
+ #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
+/* ========================================================  INTSTS0  ======================================================== */
+ #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
+ #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
+ #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
+ #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
+ #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
+ #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
+ #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
+ #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
+ #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
+ #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
+/* ========================================================  INTSTS1  ======================================================== */
+ #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
+ #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
+ #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
+ #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
+ #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
+ #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
+ #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
+ #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
+ #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
+/* ========================================================  BRDYSTS  ======================================================== */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  NRDYSTS  ======================================================== */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BEMPSTS  ======================================================== */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
+/* ========================================================  FRMNUM  ========================================================= */
+ #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
+ #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
+ #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
+ #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
+/* ========================================================  UFRMNUM  ======================================================== */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
+ #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
+ #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
+/* ========================================================  USBADDR  ======================================================== */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
+ #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
+ #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
+/* ========================================================  USBREQ  ========================================================= */
+ #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
+ #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
+/* ========================================================  USBVAL  ========================================================= */
+ #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
+ #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBINDX  ======================================================== */
+ #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
+ #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
+/* ========================================================  USBLENG  ======================================================== */
+ #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
+ #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
+/* ========================================================  DCPCFG  ========================================================= */
+ #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
+ #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+/* ========================================================  DCPMAXP  ======================================================== */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
+/* ========================================================  DCPCTR  ========================================================= */
+ #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
+ #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
+ #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  PIPESEL  ======================================================== */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
+ #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
+/* ========================================================  PIPECFG  ======================================================== */
+ #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
+ #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
+ #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
+ #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
+ #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
+ #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
+ #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
+ #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
+/* =======================================================  PIPEMAXP  ======================================================== */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
+ #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
+/* =======================================================  PIPEPERI  ======================================================== */
+ #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
+ #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
+ #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
+/* =======================================================  PIPE_CTR  ======================================================== */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
+ #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
+ #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
+ #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
+/* ========================================================  DEVADD  ========================================================= */
+ #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
+ #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
+ #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
+ #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
+ #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
+ #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
+/* ======================================================  USBBCCTRL0  ======================================================= */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
+/* ========================================================  UCKSEL  ========================================================= */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
+ #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
+/* =========================================================  USBMC  ========================================================= */
+ #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
+ #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
+ #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  PHYSLEW  ======================================================== */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
+/* ========================================================  LPCTRL  ========================================================= */
+ #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
+ #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
+/* =========================================================  LPSTS  ========================================================= */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
+ #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
+/* ========================================================  BCCTRL  ========================================================= */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
+ #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
+/* =======================================================  PL1CTRL1  ======================================================== */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
+/* =======================================================  PL1CTRL2  ======================================================== */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
+/* =======================================================  HL1CTRL1  ======================================================== */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
+/* =======================================================  HL1CTRL2  ======================================================== */
+ #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
+ #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
+ #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
+/* ========================================================  DPUSR0R  ======================================================== */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR1R  ======================================================== */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
+/* ========================================================  DPUSR2R  ======================================================== */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
+ #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
+ #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
+ #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
+ #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
+/* ========================================================  DPUSRCR  ======================================================== */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
+/* ======================================================  DPUSR0R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
+/* ======================================================  DPUSR1R_FS  ======================================================= */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
+
+/* =========================================================================================================================== */
+/* ================                                           R_WDT                                           ================ */
+/* =========================================================================================================================== */
+
+/* =========================================================  WDTRR  ========================================================= */
+ #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
+ #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
+/* =========================================================  WDTCR  ========================================================= */
+ #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
+ #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
+ #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
+ #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
+ #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
+ #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
+ #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
+/* =========================================================  WDTSR  ========================================================= */
+ #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
+ #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
+ #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
+ #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
+ #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
+/* ========================================================  WDTRCR  ========================================================= */
+ #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
+ #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
+/* =======================================================  WDTCSTPR  ======================================================== */
+ #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
+ #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* RA_H */
+
+/** @} */ /* End of group RA */
+
+/** @} */ /* End of group Renesas */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
new file mode 100644
index 0000000000..1f8d6c4398
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef SYSTEM_RENESAS_ARM_H
+ #define SYSTEM_RENESAS_ARM_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+ #include 
+
+extern uint32_t SystemCoreClock;       /** System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd
new file mode 100644
index 0000000000..231b936f36
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd
@@ -0,0 +1,75474 @@
+
+
+  Renesas
+  Renesas
+  RA
+  All Chips
+  x.xx
+  Renesas RA All MCU
+  8
+  32
+  
+    
+      R_ACMPHS0
+      High-Speed Analog Comparator
+      0x40085000
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000008
+        0x01
+        registers
+      
+      
+        0x0000000C
+        0x01
+        registers
+      
+      
+        0x00000010
+        0x01
+        registers
+      
+      
+        
+          CMPCTL
+          Comparator Control Register
+          0x000
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HCMPON
+              Comparator operation control
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Operation stopped (the comparator outputs a low-level signal)
+                  #0
+                
+                
+                  1
+                  Operation enabled (input to the comparator pins is enabled
+                  #1
+                
+              
+            
+            
+              CDFS
+              Noise filter selection
+              5
+              6
+              read-write
+              
+                
+                  00
+                  Noise filter not used.
+                  #00
+                
+                
+                  01
+                  Noise filter sampling frequency is 2^3/PCLKB.
+                  #01
+                
+                
+                  10
+                  Noise filter sampling frequency is 2^4/PCLKB. 
+                  #10
+                
+                
+                  11
+                  Noise filter sampling frequency is 2^5/PCLKB.
+                  #11
+                
+              
+            
+            
+              CEG
+              Selection of valid edge (Edge selector) 
+              3
+              4
+              read-write
+              
+                
+                  00
+                  No edge selection.
+                  #00
+                
+                
+                  01
+                  Rising edge selection.
+                  #01
+                
+                
+                  10
+                  Falling edge selection
+                  #10
+                
+                
+                  11
+                  Both-edge selection
+                  #11
+                
+              
+            
+            
+              CSTEN
+              Interrupt Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Output via the Edge selector
+                  #0
+                
+                
+                  1
+                  Direct output
+                  #1
+                
+              
+            
+            
+              COE
+              Comparator output enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Comparator output disabled (the output signal is low level).
+                  #0
+                
+                
+                  1
+                  Comparator output enabled
+                  #1
+                
+              
+            
+            
+              CINV
+              Comparator output polarity selection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Comparator output not inverted 
+                  #0
+                
+                
+                  1
+                  Comparator output inverted
+                  #1
+                
+              
+            
+          
+        
+        
+          CMPSEL0
+          Comparator Input Select Register 
+          0x004
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPSEL
+              Comparator Input Selection
+              [3:0]
+              read-write
+              
+                
+                  0000
+                  Do not input
+                  0
+                
+                
+                  0001
+                  Select IVCMP0
+                  1
+                
+                
+                  0010
+                  Select IVCMP1
+                  2
+                
+                
+                  0100
+                  Select IVCMP2
+                  4
+                
+                
+                  1000
+                  Select IVCMP3
+                  8
+                
+              
+            
+          
+        
+        
+          CMPSEL1
+          Comparator Reference Voltage Select Register 
+          0x008
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CRVS
+              Reference Voltage Selection
+              [5:0]
+              read-write
+              
+                
+                  0000
+                  Do not input
+                  0
+                
+                
+                  0001
+                  Select IVREF0
+                  1
+                
+                
+                  0010
+                  Select IVREF1
+                  2
+                
+                
+                  0100
+                  Select IVREF2
+                  4
+                
+                
+                  1000
+                  Select IVREF3
+                  8
+                  010000
+                  Select IVREF4
+                  16
+                  100000
+                  Select IVREF5
+                  32
+                
+              
+            
+          
+        
+        
+          CMPMON
+          Comparator Output Monitor Register 
+          0x00C
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              CMPMON
+              Comparator output monitor 
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Comparator output Low
+                  #0
+                
+                
+                  1
+                  Comparator output High
+                  #1
+                
+              
+            
+          
+        
+        
+          CPIOC
+          Comparator Output Control Register 
+          0x010
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VREFEN
+              Internal Vref enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Internal Vref disable
+                  #0
+                
+                
+                  1
+                  Internal Vref enable
+                  #1
+                
+              
+            
+            
+              CPOE
+              Comparator output selection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VCOUT pin output of the comparator is disabled (the output signal is low level).
+                  #0
+                
+                
+                  1
+                  VCOUT pin output of the comparator is enabled
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_ACMPHS1
+      0x40085100
+    
+    
+      R_ACMPHS2
+      0x40085200
+    
+    
+      R_ACMPHS3
+      0x40085300
+    
+    
+      R_ACMPHS4
+      0x40085400
+    
+    
+      R_ACMPHS5
+      0x40085500
+    
+    
+      R_ACMPLP
+      Low-Power Analog Comparator
+      0x40085E00
+      
+        0x00000000
+        0x003
+        registers
+      
+      
+        0x00000004
+        0x002
+        registers
+      
+      
+        
+          COMPMDR
+          ACMPLP Mode Setting Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              C1MON
+              ACMPLP1 Monitor Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  CMPIN1 < CMPREF1, CMPIN1 < internal reference voltage, or ACMPLP1 operation disabled.(When the window function is disabled)/CMPIN1 < VRFL, CMPIN1 > VRFH, or ACMPLP1 operation disabled.(When the window function is enabled)
+                  #0
+                
+                
+                  1
+                  CMPIN1 > CMPREF1, or CMPIN1 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN1 < VRFH.(When the window function is enabled)
+                  #1
+                
+              
+            
+            
+              C1VRF
+              ACMPLP1 Reference Voltage Selection
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Select CMPREF1 input as ACMPLP1 reference voltage.
+                  #0
+                
+                
+                  1
+                  Select internal reference voltage (Vref) as ACMPLP1 reference voltage.
+                  #1
+                
+              
+            
+            
+              C1WDE
+              ACMPLP1 Window Function Mode Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              C1ENB
+              ACMPLP1 Operation Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              C0MON
+              ACMPLP0 Monitor Flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  CMPIN0 < CMPREF0, CMPIN0 < internal reference voltage, or ACMPLP0 operation disabled.(When the window function is disabled)/CMPIN0 < VRFL, CMPIN0 > VRFH, or ACMPLP0 operation disabled.(When the window function is enabled)
+                  #0
+                
+                
+                  1
+                  CMPIN0 > CMPREF0, or CMPIN0 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN0 < VRFH.(When the window function is enabled)
+                  #1
+                
+              
+            
+            
+              C0WDE
+              ACMPLP0 Window Function Mode Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              C0VRF
+              ACMPLP0 Reference Voltage Selection
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Select CMPREF0 input as ACMPLP0 reference voltage.
+                  #0
+                
+                
+                  1
+                  Select internal reference voltage (Vref) as ACMPLP0 reference voltage.
+                  #1
+                
+              
+            
+            
+              C0ENB
+              ACMPLP0 Operation Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          COMPFIR
+          ACMPLP Filter Control Register
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              C1EDG
+              ACMPLP1 Edge Detection Selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Interrupt and ELC event request by one-edge detection
+                  #0
+                
+                
+                  1
+                  Interrupt and ELC event request by both-edge detection
+                  #1
+                
+              
+            
+            
+              C1EPO
+              ACMPLP1 Edge Polarity Switching
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Interrupt and ELC event request at rising edge
+                  #0
+                
+                
+                  1
+                  Interrupt and ELC event request at falling edge
+                  #1
+                
+              
+            
+            
+              C1FCK
+              ACMPLP1 Filter Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  No Sampling (bypass)
+                  #00
+                
+                
+                  01
+                  Sampling at PCLK
+                  #01
+                
+                
+                  10
+                  Sampling at PCLK/8
+                  #10
+                
+                
+                  11
+                  Sampling at PCLK/32
+                  #11
+                
+              
+            
+            
+              C0EDG
+              ACMPLP0 Edge Detection Selection
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Interrupt and ELC event request by one-edge detection
+                  #0
+                
+                
+                  1
+                  Interrupt and ELC event request by both-edge detection
+                  #1
+                
+              
+            
+            
+              C0EPO
+              ACMPLP0 Edge Polarity Switching
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Interrupt and ELC event request at rising edge
+                  #0
+                
+                
+                  1
+                  Interrupt and ELC event request at falling edge
+                  #1
+                
+              
+            
+            
+              C0FCK
+              ACMPLP0 Filter Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  No Sampling (bypass)
+                  #00
+                
+                
+                  01
+                  Sampling at PCLK
+                  #01
+                
+                
+                  10
+                  Sampling at PCLK/8
+                  #10
+                
+                
+                  11
+                  Sampling at PCLK/32
+                  #11
+                
+              
+            
+          
+        
+        
+          COMPOCR
+          ACMPLP Output Control Register
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SPDMD
+              ACMPLP0/ACMPLP1 Speed Selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Comparator low-speed mode
+                  #0
+                
+                
+                  1
+                  Comparator high-speed mode
+                  #1
+                
+              
+            
+            
+              C1OP
+              ACMPLP1 VCOUT Output Polarity Selection
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Non inverted
+                  #0
+                
+                
+                  1
+                  Inverted
+                  #1
+                
+              
+            
+            
+              C1OE
+              ACMPLP1 VCOUT Pin Output Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              C0OP
+              ACMPLP0 VCOUT Output Polarity Selection
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Non inverted
+                  #0
+                
+                
+                  1
+                  Inverted
+                  #1
+                
+              
+            
+            
+              C0OE
+              ACMPLP0 VCOUT Pin Output Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          COMPSEL0
+          Comparator Input Select Register
+          0x04
+          8
+          read-write
+          0x11
+          0xFF
+          
+            
+              IVCMP1
+              ACMPLP1 Input (IVCMP1) Selection
+              4
+              6
+              read-write
+              
+                
+                  00
+                  No input
+                  #00
+                
+                
+                  01
+                  CMPIN1 input selected
+                  #01
+                
+                
+                  10
+                  AMP1O output selected
+                  #10
+                
+              
+            
+            
+              IVCMP0
+              ACMPLP0 Input (IVCMP0) Selection
+              0
+              2
+              read-write
+              
+                
+                  00
+                  No input
+                  #00
+                
+                
+                  01
+                  CMPIN0 input selected
+                  #01
+                
+                
+                  10
+                  AMP0O output selected
+                  #10
+                
+              
+            
+          
+        
+        
+          COMPSEL1
+          Comparator Reference voltage Select Register
+          0x05
+          8
+          read-write
+          0x91
+          0xFF
+          
+            
+              C1VRF2
+              ACMPLP1 Reference Voltage Selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  IVREF0 selected
+                  #0
+                
+                
+                  1
+                  IVREF1 selected
+                  #1
+                
+              
+            
+            
+              IVREF1
+              ACMPLP1 Reference Voltage(IVREF1) Selection
+              4
+              6
+              read-write
+              
+                
+                  00
+                  No reference voltage
+                  #00
+                
+                
+                  01
+                  CMPREF1 selected
+                  #01
+                
+                
+                  10
+                  DA8_1 output selected
+                  #10
+                
+              
+            
+            
+              IVREF0
+              ACMPLP0 Reference Voltage (IVREF0) Selection
+              0
+              2
+              read-write
+              
+                
+                  00
+                  No reference voltage
+                  #00
+                
+                
+                  01
+                  CMPREF0 selected
+                  #01
+                
+                
+                  10
+                  DA8_0 output selected
+                  #10
+                
+              
+            
+          
+        
+      
+    
+    
+      R_ADC0
+      A/D Converter
+      0x4005C000
+      
+        0x00000000
+        0x02
+        registers
+      
+      
+        0x00000004
+        0x009
+        registers
+      
+      
+        0x0000000E
+        0x04A
+        registers
+      
+      
+        0x00000066
+        0x02
+        registers
+      
+      
+        0x0000007A
+        0x01
+        registers
+      
+      
+        0x0000007C
+        0x002
+        registers
+      
+      
+        0x00000080
+        0x02
+        registers
+      
+      
+        0x00000084
+        0x004
+        registers
+      
+      
+        0x0000008A
+        0x01
+        registers
+      
+      
+        0x0000008C
+        0x01
+        registers
+      
+      
+        0x00000090
+        0x015
+        registers
+      
+      
+        0x000000A6
+        0x01
+        registers
+      
+      
+        0x000000A8
+        0x005
+        registers
+      
+      
+        0x000000DD
+        0x016
+        registers
+      
+      
+        0x000000F4
+        0x01
+        registers
+      
+      
+        0x000000F8
+        0x003
+        registers
+      
+      
+        0x000001A0
+        0x004
+        registers
+      
+      
+        0x000001B0
+        0x02
+        registers
+      
+      
+        
+          ADCSR
+          A/D Control Register
+          0x000
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADST
+              A/D Conversion Start
+              15
+              15
+              read-write
+              modify
+              
+                
+                  0
+                  Stops A/D conversion process.
+                  #0
+                
+                
+                  1
+                  Starts A/D conversion process.
+                  #1
+                
+              
+            
+            
+              ADCS
+              Scan Mode Select
+              13
+              14
+              read-write
+              
+                
+                  00
+                  Single scan mode
+                  #00
+                
+                
+                  01
+                  Group scan mode
+                  #01
+                
+                
+                  10
+                  Continuous scan mode
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              ADHSC
+              A/D Conversion Operation Mode Select
+              10
+              10
+              read-write
+              
+                
+                  0
+                  High speed A/D conversion mode
+                  #0
+                
+                
+                  1
+                  Low current A/D conversion mode
+                  #1
+                
+              
+            
+            
+              TRGE
+              Trigger Start Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Disables A/D conversion to be started by the synchronous or asynchronous trigger.
+                  #0
+                
+                
+                  1
+                  Enables A/D conversion to be started by the synchronous or asynchronous trigger.
+                  #1
+                
+              
+            
+            
+              EXTRG
+              Trigger Select
+              8
+              8
+              read-write
+              
+                
+                  0
+                  A/D conversion is started by the synchronous trigger (ELC).
+                  #0
+                
+                
+                  1
+                  A/D conversion is started by the asynchronous trigger (ADTRG0#).
+                  #1
+                
+              
+            
+            
+              DBLE
+              Double Trigger Mode Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Double trigger mode non-selection
+                  #0
+                
+                
+                  1
+                  Double trigger mode selection
+                  #1
+                
+              
+            
+            
+              GBADIE
+              Group B Scan End Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disables S12GBADI0 interrupt generation upon group B scan completion.
+                  #0
+                
+                
+                  1
+                  Enables S12GBADI0 interrupt generation upon group B scan completion.
+                  #1
+                
+              
+            
+            
+              DBLANS
+              Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          2
+          0x2
+          ADANSA[%s]
+          A/D Channel Select Register 
+          0x004
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              ANSA%s
+              AN Input Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  AN Input is not subjected to conversion.
+                  #0
+                
+                
+                  1
+                  AN Input is subjected to conversion.
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          0x2
+          ADADS[%s]
+          A/D-Converted Value Addition/Average Channel Select Register
+          0x008
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              ADS%s
+              A/D-Converted Value Addition/Average Channel Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  AN Input is not selected.
+                  #0
+                
+                
+                  1
+                  AN Input is selected.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADADC
+          A/D-Converted Value Addition/Average Count Select Register
+          0x00C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ADC
+              Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b)
+              0
+              2
+              read-write
+              
+                
+                  000
+                  1-time conversion (no addition; same as normal conversion)
+                  #000
+                
+                
+                  001
+                  2-time conversion (addition once)
+                  #001
+                
+                
+                  010
+                  3-time conversion (addition twice)
+                  #010
+                
+                
+                  011
+                  4-time conversion (addition three times)
+                  #011
+                
+                
+                  101
+                  16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy.
+                  #101
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              AVEE
+              Average Mode Enable. NOTE:When average mode is deselected by setting the ADADC.AVEE bit to 0, set the addition count to 1, 2, 3, 4 or 16-time conversion. 16-time conversion can only be used with 12-bit accuracy selected. NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b)
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable average mode
+                  #0
+                
+                
+                  1
+                  Enable average mode
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCER
+          A/D Control Extended Register
+          0x00E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADRFMT
+              A/D Data Register Format Select
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Flush-right is selected for the A/D data register format.
+                  #0
+                
+                
+                  1
+                  Flush-left is selected for the A/D data register format.
+                  #1
+                
+              
+            
+            
+              ADINV
+              Single-Ended Input A/D Converted Data Inversion Select
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Data is stored in a range of -32768 to 0.
+                  #0
+                
+                
+                  1
+                  Data is stored in a range of 0 to 32767.
+                  #1
+                
+              
+            
+            
+              DIAGM
+              Self-Diagnosis Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Disables self-diagnosis of A/D converter.
+                  #0
+                
+                
+                  1
+                  Enables self-diagnosis of A/D converter.
+                  #1
+                
+              
+            
+            
+              DIAGLD
+              Self-Diagnosis Mode Select
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Rotation mode for self-diagnosis voltage
+                  #0
+                
+                
+                  1
+                  Fixed mode for self-diagnosis voltage
+                  #1
+                
+              
+            
+            
+              DIAGVAL
+              Self-Diagnosis Conversion Voltage Select
+              8
+              9
+              read-write
+              
+                
+                  00
+                  When the self-diagnosis fixation mode is selected, it set prohibits it. 
+                  #00
+                
+                
+                  01
+                  The self-diagnosis by using the voltage of  0V.
+                  #01
+                
+                
+                  10
+                  The self-diagnosis by using the voltage of reference supply x 1/2. 
+                  #10
+                
+                
+                  11
+                  The self-diagnosis by using the voltage of the reference supply. 
+                  #11
+                
+              
+            
+            
+              ACE
+              A/D Data Register Automatic Clearing Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing.
+                  #1
+                
+              
+            
+            
+              ADPRC
+              A/D Conversion Accuracy Specify
+              1
+              2
+              read-write
+              
+                
+                  00
+                  A/D conversion is performed with 12-bit accuracy.
+                  #00
+                
+                
+                  01
+                  A/D conversion is performed with 10-bit accuracy.
+                  #01
+                
+                
+                  10
+                  A/D conversion is performed with 8-bit accuracy.
+                  #10
+                
+                
+                  11
+                  A/D conversion is performed with 14-bit accuracy.
+                  #11
+                
+              
+            
+          
+        
+        
+          ADSTRGR
+          A/D Conversion Start Trigger Select Register
+          0x010
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              TRSA
+              A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected.
+              8
+              13
+              read-write
+            
+            
+              TRSB
+              A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode.
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ADEXICR
+          A/D Conversion Extended Input Control Register
+          0x012
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              OCSB
+              Internal Reference Voltage A/D Conversion Select for Group B in group scan mode.
+              11
+              11
+              read-write
+              
+                
+                  0
+                  The internal reference voltage is not selected for group B in group scan mode.
+                  #0
+                
+                
+                  1
+                  The internal reference voltage is selected for group B in group scan mode.
+                  #1
+                
+              
+            
+            
+              TSSB
+              Temperature Sensor Output A/D Conversion Select for Group B in group scan mode.
+              10
+              10
+              read-write
+              
+                
+                  0
+                  The temperature sensor output is not selected for group B in group scan mode.
+                  #0
+                
+                
+                  1
+                  The temperature sensor output is selected for group B in group scan mode.
+                  #1
+                
+              
+            
+            
+              OCSA
+              Internal Reference Voltage A/D Conversion Select
+              9
+              9
+              read-write
+              
+                
+                  0
+                  The internal reference voltage is not selected.
+                  #0
+                
+                
+                  1
+                  The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode.
+                  #1
+                
+              
+            
+            
+              TSSA
+              Temperature Sensor Output A/D Conversion Select
+              8
+              8
+              read-write
+              
+                
+                  0
+                  The temperature sensor output is not selected.
+                  #0
+                
+                
+                  1
+                  The temperature sensor output is selected.
+                  #1
+                
+              
+            
+            
+              OCSAD
+              Internal Reference Voltage A/D converted Value Addition/Average Mode Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Internal reference voltage A/D-converted value addition/average mode is not selected.
+                  #0
+                
+                
+                  1
+                  Internal reference voltage A/D-converted value addition/average mode is selected.
+                  #1
+                
+              
+            
+            
+              TSSAD
+              Temperature Sensor Output A/D converted Value Addition/Average Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Temperature sensor output A/D-converted value addition/average mode is not selected.
+                  #0
+                
+                
+                  1
+                  Temperature sensor output A/D-converted value addition/average mode is selected.
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          2
+          ADANSB[%s]
+          A/D Channel Select Register B
+          0x014
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              ANSB%s
+              AN Input Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Input is not subjected to conversion.
+                  #0
+                
+                
+                  1
+                  Input is subjected to conversion.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADDBLDR
+          A/D Data Duplication Register
+          0x018
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADDBLDR
+              This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADTSDR
+          A/D Temperature Sensor Data Register
+          0x01A
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADTSDR
+              This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADOCDR
+          A/D Internal Reference Voltage Data Register
+          0x01C
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADOCDR
+              This is a 16-bit read-only register for storing the A/D result of internal reference voltage.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADRD_RIGHT
+          A/D Self-Diagnosis Data Register Right Justified
+          0x01E
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              DIAGST
+              Self-Diagnosis Status
+              14
+              15
+              read-only
+              
+                
+                  00
+                  Self-diagnosis has never been executed since power-on.
+                  #00
+                
+                
+                  01
+                  Self-diagnosis using the voltage of 0 V has been executed.
+                  #01
+                
+                
+                  10
+                  Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed.
+                  #10
+                
+                
+                  11
+                  Self-diagnosis using the voltage of reference power supply(VREFH) has been executed.
+                  #11
+                
+              
+            
+            
+              AD
+              A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC.
+              0
+              13
+              read-only
+            
+          
+        
+        
+          ADRD_LEFT
+          A/D Self-Diagnosis Data Register Left Justified
+          ADRD_RIGHT
+          0x01E
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              AD
+              A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC.
+              2
+              15
+              read-only
+            
+            
+              DIAGST
+              Self-Diagnosis Status
+              0
+              1
+              read-only
+              
+                
+                  00
+                  Self-diagnosis has never been executed since power-on.
+                  #00
+                
+                
+                  01
+                  Self-diagnosis using the voltage of 0 V has been executed.
+                  #01
+                
+                
+                  10
+                  Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed.
+                  #10
+                
+                
+                  11
+                  Self-diagnosis using the voltage of reference power supply(VREFH) has been executed.
+                  #11
+                
+              
+            
+          
+        
+        
+          28
+          0x2
+          ADDR[%s]
+          A/D Data Register
+          0x020
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADDR
+              The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADSHCR
+          A/D Sample and Hold Circuit Control Register
+          0x066
+          16
+          read-write
+          0x0018
+          0xFFFF
+          
+            
+              SHANS2
+              AN002 sample-and-hold circuit Select
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Bypass the sample-and-hold circuit.
+                  #0
+                
+                
+                  1
+                  Use the sample-and-hold circuit.
+                  #1
+                
+              
+            
+            
+              SHANS1
+              AN001 sample-and-hold circuit Select
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Bypass the sample-and-hold circuit.
+                  #0
+                
+                
+                  1
+                  Use the sample-and-hold circuit.
+                  #1
+                
+              
+            
+            
+              SHANS0
+              AN000 sample-and-hold circuit Select
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Bypass the sample-and-hold circuit.
+                  #0
+                
+                
+                  1
+                  Use the sample-and-hold circuit.
+                  #1
+                
+              
+            
+            
+              SSTSH
+              Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting  Set the sampling time (4 to 255 states)
+              0
+              7
+              read-write
+              
+                
+                  0x04
+                  0xFF
+                
+              
+            
+          
+        
+        
+          ADDISCR
+          A/D Disconnection Detection Control Register
+          0x07A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CHARGE
+              Selection of Precharge or Discharge
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Discharge
+                  #0
+                
+                
+                  1
+                  Precharge
+                  #1
+                
+              
+            
+            
+              ADNDIS
+              The charging time
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  Disconnection detection is disabled
+                  #0000
+                
+                
+                  0001
+                  Setting prohibited
+                  #0001
+                
+                
+                  others
+                  ( 1 / ADCLK ) x ADNDIS  
+                  true
+                
+              
+            
+          
+        
+        
+          ADSHMSR
+          A/D Sample and Hold Operation Mode Select Register
+          0x07C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SHMD
+              Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Sampling by channel-dedicated sample-and-hold circuit is disable.
+                  #0
+                
+                
+                  1
+                  Sampling by channel-dedicated sample-and-hold circuit is enable.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADGSPCR
+          A/D Group Scan Priority Control Register
+          0x080
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              GBRP
+              Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit.
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Single scan for group B is not continuously activated.
+                  #0
+                
+                
+                  1
+                  Single scan for group B is continuously activated.
+                  #1
+                
+              
+            
+            
+              GBRSCN
+              Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.)
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Scanning for group B is not restarted after having been discontinued due to group A priority control.
+                  #0
+                
+                
+                  1
+                  Scanning for group B is restarted after having been discontinued due to group A priority control.
+                  #1
+                
+              
+            
+            
+              PGS
+              Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operation is without group A priority control
+                  #0
+                
+                
+                  1
+                  Operation is with group A priority control
+                  #1
+                
+              
+            
+          
+        
+        
+          ADICR
+          A/D Interrupt Control Register
+          0x7D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ADIC
+              A/D Interrupt Control
+              0
+              1
+              read-write
+              
+                
+                  00
+                  ADC_ADI is generated at end of A/D Scan
+                  #00
+                
+                
+                  11
+                  ADC_ADI is generated at end of calibration
+                  #11
+                
+              
+            
+          
+        
+        
+          ADDBLDRA
+          A/D Data Duplexing Register A
+          0x084
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADDBLDRA
+              This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADDBLDRB
+          A/D Data Duplexing Register B
+          0x086
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ADDBLDRB
+              This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADHVREFCNT
+          A/D High-Potential/Low-Potential Reference Voltage Control Register
+          0x08A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ADSLP
+              Sleep
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal operation
+                  #0
+                
+                
+                  1
+                  Standby state.
+                  #1
+                
+              
+            
+            
+              LVSEL
+              Low-Potential Reference Voltage Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  AVSS0 is selected as the low-potential reference voltage
+                  #0
+                
+                
+                  1
+                  VREFL0 is selected as the low-potential reference voltage.
+                  #1
+                
+              
+            
+            
+              HVSEL
+              High-Potential Reference Voltage Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  AVCC0 is selected as the high-potential reference voltage
+                  #00
+                
+                
+                  01
+                  VREFH0 is selected as the high-potential reference voltage
+                  #01
+                
+                
+                  10
+                  Internal reference voltage is selected as the high-potential reference voltage
+                  #10
+                
+                
+                  11
+                  Internal node discharge. No reference voltage pin is selected.
+                  #11
+                
+              
+            
+          
+        
+        
+          ADWINMON
+          A/D Compare Function Window A/B Status Monitor Register
+          0x08C
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              MONCMPB
+              Comparison Result Monitor B
+              5
+              5
+              read-only
+              
+                
+                  0
+                  Window B comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Window B comparison conditions are met.
+                  #1
+                
+              
+            
+            
+              MONCMPA
+              Comparison Result Monitor A
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Window A comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Window A comparison conditions are met.
+                  #1
+                
+              
+            
+            
+              MONCOMB
+              Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled.
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Window A / window B composite conditions are not met.
+                  #0
+                
+                
+                  1
+                  Window A / window B composite conditions are met.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCMPCR
+          A/D Compare Function Control Register
+          0x090
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CMPAIE
+              Compare A Interrupt Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  ADC_CMPAI interrupt is disabled when comparison conditions (window A) are met.
+                  #0
+                
+                
+                  1
+                  ADC_CMPAI interrupt is enabled when comparison conditions (window A) are met.
+                  #1
+                
+              
+            
+            
+              WCMPE
+              Window Function Setting
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result.
+                  #0
+                
+                
+                  1
+                  Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result.
+                  #1
+                
+              
+            
+            
+              CMPBIE
+              Compare B Interrupt Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  ADC_CMPAI interrupt is disabled when comparison conditions (window B) are met.
+                  #0
+                
+                
+                  1
+                  ADC_CMPAI interrupt is enabled when comparison conditions (window B) are met.
+                  #1
+                
+              
+            
+            
+              CMPAE
+              Compare Window A Operation Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Compare window A operation is disabled. ADC_WCMPM and ADC_WCMPUM outputs are disabled.
+                  #0
+                
+                
+                  1
+                  Compare window A operation is enabled.
+                  #1
+                
+              
+            
+            
+              CMPBE
+              Compare Window B Operation Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Compare window B operation is disabled. ADC_WCMPM and ADC_WCMPUM outputs are disabled.
+                  #0
+                
+                
+                  1
+                  Compare window B operation is enabled.
+                  #1
+                
+              
+            
+            
+              CMPAB
+              Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1).
+              0
+              1
+              read-write
+              
+                
+                  00
+                  ADC_WCMPM is output when window A comparison conditions are met OR window B comparison conditions are met. ADC_WCMPUM is output in other cases.
+                  #00
+                
+                
+                  01
+                  ADC_WCMPM is output when window A comparison conditions are met EXOR window B comparison conditions are met. ADC_WCMPUM is output in other cases.
+                  #01
+                
+                
+                  10
+                  ADC140_WCMPM is output when window A comparison conditions are met and window B comparison conditions are met. ADC140_WCMPUM is output in other cases.
+                  #10
+                
+                
+                  11
+                  Setting prohibited.
+                  #11
+                
+              
+            
+          
+        
+        
+          ADCMPANSER
+          A/D Compare Function Window A Extended Input Select Register
+          0x092
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPOCA
+              Internal reference voltage Compare selection bit.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Excludes the internal reference voltage from the compare window A target range.
+                  #0
+                
+                
+                  1
+                  Includes the internal reference voltage in the compare window A target range.
+                  #1
+                
+              
+            
+            
+              CMPTSA
+              Temperature sensor output Compare selection bit.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Excludes the temperature sensor output from the compare window A target range.
+                  #0
+                
+                
+                  1
+                  Includes the temperature sensor output in the compare window A target range.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCMPLER
+          A/D Compare Function Window A Extended Input Comparison Condition Setting Register
+          0x093
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPLOCA
+              Compare Window A Internal Reference Voltage ComparisonCondition Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1)
+                  #0
+                
+                
+                  1
+                  ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1)
+                  #1
+                
+              
+            
+            
+              CMPLTSA
+              Compare Window A Temperature Sensor Output Comparison Condition Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1).
+                  #0
+                
+                
+                  1
+                  ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1).
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          0x2
+          ADCMPANSR[%s]
+          A/D Compare Function Window A Channel Select Register
+          0x094
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              CMPCHA%s
+              AN Input Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Excludes Input from the compare window A target range.
+                  #0
+                
+                
+                  1
+                  Includes Input  from the compare window A target range.
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          0x2
+          ADCMPLR[%s]
+          A/D Compare Function Window A Comparison Condition Setting Register
+          0x098
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              CMPLCHA%s
+              Comparison condition of input
+              0
+              0
+              read-write
+              
+                
+                  0
+                  ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1)
+                  #0
+                
+                
+                  1
+                  ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1).
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCMPDR0
+          A/D Compare Function Window A Lower-Side Level Setting Register
+          0x09C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADCMPDR0
+              The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          ADCMPDR1
+          A/D Compare Function Window A Upper-Side Level Setting Register
+          0x09E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADCMPDR1
+              The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A..
+              0
+              15
+              read-write
+            
+          
+        
+        
+          2
+          0x2
+          ADCMPSR[%s]
+          A/D Compare Function Window A Channel Status Register
+          0x0A0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              CMPSTCHA%s
+              Compare window A flag of input
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Comparison conditions are met.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCMPSER
+          A/D Compare Function Window A Extended Input Channel Status Register
+          0x0A4
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPSTOCA
+              Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Comparison conditions are met.
+                  #1
+                
+              
+            
+            
+              CMPSTTSA
+              Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time.
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Comparison conditions are met.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCMPBNSR
+          A/D Compare Function Window B Channel Selection Register
+          0x0A6
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPLB
+              Compare window B Compare condition setting bit.
+              7
+              7
+              read-write
+              
+                
+                  0
+                  CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value  (ADCMPCR.WCMPE=1)
+                  #0
+                
+                
+                  1
+                  CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1)
+                  #1
+                
+              
+            
+            
+              CMPCHB
+              Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected.
+              0
+              5
+              read-write
+              
+                
+                  0x00
+                  AN000
+                  0x00
+                
+                
+                  0x01
+                  AN001
+                  0x01
+                
+                
+                  0x02
+                  AN002
+                  0x02
+                
+                
+                  0x03
+                  AN003
+                  0x03
+                
+                
+                  0x04
+                  AN004
+                  0x04
+                
+                
+                  0x05
+                  AN005
+                  0x05
+                
+                
+                  0x06
+                  AN006
+                  0x06
+                
+                
+                  0x07
+                  AN007
+                  0x07
+                
+                
+                  0x08
+                  AN008
+                  0x08
+                
+                
+                  0x09
+                  AN009
+                  0x09
+                
+                
+                  0x0A
+                  AN010
+                  0x0A
+                
+                
+                  0x0B
+                  AN011
+                  0x0B
+                
+                
+                  0x0C
+                  AN012
+                  0x0C
+                
+                
+                  0x0D
+                  AN013
+                  0x0D
+                
+                
+                  0x0E
+                  AN014
+                  0x0E
+                
+                
+                  0x0F
+                  AN015
+                  0x0F
+                
+                
+                  0x10
+                  AN016
+                  0x10
+                
+                
+                  0x11
+                  AN017
+                  0x11
+                
+                
+                  0x12
+                  AN018
+                  0x12
+                
+                
+                  0x13
+                  AN019
+                  0x13
+                
+                
+                  0x14
+                  AN020
+                  0x14
+                
+                
+                  0x15
+                  AN021
+                  0x15
+                
+                
+                  0x16
+                  AN022
+                  0x16
+                
+                
+                  0x17
+                  AN023
+                  0x17
+                
+                
+                  0x18
+                  AN024
+                  0x18
+                
+                
+                  0x19
+                  AN025
+                  0x19
+                
+                
+                  0x1A
+                  AN026
+                  0x1A
+                
+                
+                  0x1B
+                  AN027
+                  0x1B
+                
+                
+                  0x20
+                  Temperature sensor
+                  0x20
+                
+                
+                  0x21
+                  Internal reference voltage
+                  0x21
+                
+                
+                  0x3F
+                  No channel is selected
+                  0x3F
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          ADWINLLB
+          A/D Compare Function Window B Lower-Side Level Setting Register
+          0x0A8
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADWINLLB
+              This register is used to compare A window function is used to set the lower level of the window B.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          ADWINULB
+          A/D Compare Function Window B Upper-Side Level Setting Register
+          0x0AA
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ADWINULB
+              This register is used to compare A window function is used to set the higher level of the window B.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          ADCMPBSR
+          A/D Compare Function Window B Status Register
+          0x0AC
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CMPSTB
+              Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN027, temperature sensor, and internal reference voltage) made the object of window B relation condition.
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Comparison conditions are not met.
+                  #0
+                
+                
+                  1
+                  Comparison conditions are met.
+                  #1
+                
+              
+            
+          
+        
+        
+          ADSSTRL
+          A/D Sampling State Register L
+          0x0DD
+          8
+          read-write
+          0x0B
+          0xFF
+          
+            
+              SST
+              Sampling Time Setting (AN016-AN027)
+              0
+              7
+              read-write
+              
+                
+                  0x05
+                  0xFF
+                
+              
+            
+          
+        
+        
+          ADSSTRT
+          A/D Sampling State Register T
+          0x0DE
+          8
+          read-write
+          0x0B
+          0xFF
+          
+            
+              SST
+              Sampling Time Setting (temperature sensor output)
+              0
+              7
+              read-write
+              
+                
+                  0x05
+                  0xFF
+                
+              
+            
+          
+        
+        
+          ADSSTRO
+          A/D Sampling State Register O
+          0x0DF
+          8
+          read-write
+          0x0B
+          0xFF
+          
+            
+              SST
+              Sampling Time Setting (Internal reference voltage)
+              0
+              7
+              read-write
+              
+                
+                  0x05
+                  0xFF
+                
+              
+            
+          
+        
+        
+          16
+          0x1
+          ADSSTR[%s]
+          A/D Sampling State Registers
+          0x0E0
+          8
+          read-write
+          0x0B
+          0xFF
+          
+            
+              SST
+              Sampling time setting
+              0
+              7
+              read-write
+              
+                
+                  0x05
+                  0xFF
+                
+              
+            
+          
+        
+        
+          ADPGACR
+          A/D Programmable Gain Amplifier Control Register
+          0x1A0
+          16
+          read-write
+          0x9999
+          0xFFFF
+          
+            
+              P002GEN
+              PGA P002 gain setting and enable bit
+              11
+              11
+              read-write
+              
+                
+                  0
+                  The gain setting is invalidated (AIN is not input in PGA). 
+                  #0
+                
+                
+                  1
+                  The gain setting is effectively done (AIN is input in PGA).
+                  #1
+                
+              
+            
+            
+              P002ENAMP
+              Amplifier enable bit for PGA P002
+              10
+              10
+              read-write
+              
+                
+                  0
+                  The amplifier in PGA is not used. 
+                  #0
+                
+                
+                  1
+                  The amplifier in PGA is used. 
+                  #1
+                
+              
+            
+            
+              P002SEL1
+              The amplifier passing is enable for PGA P002
+              9
+              9
+              read-write
+              
+                
+                  0
+                  By way of the amplifier in PGA. 
+                  #0
+                
+                
+                  1
+                  Note 1 that by way of amplifier in PGA
+                  #1
+                
+              
+            
+            
+              P002SEL0
+              A through amplifier is enable for PGA P002
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Not through the PGA in amplifier
+                  #0
+                
+                
+                  1
+                  I will through in the PGA amplifier.
+                  #1
+                
+              
+            
+            
+              P001GEN
+              PGA P001 gain setting and enable bit
+              7
+              7
+            
+            
+              P001ENAMP
+              Amplifier enable bit for PGA P001
+              6
+              6
+            
+            
+              P001SEL1
+              The amplifier passing is enable for PGA P001
+              5
+              5
+            
+            
+              P001SEL0
+              A through amplifier is enable for PGA P001
+              4
+              4
+            
+            
+              P000GEN
+              PGA P000 gain setting and enable bit
+              3
+              3
+            
+            
+              P000ENAMP
+              Amplifier enable bit for PGA P000
+              2
+              2
+            
+            
+              P000SEL1
+              The amplifier passing is enable for PGA P000
+              1
+              1
+            
+            
+              P000SEL0
+              A through amplifier is enable for PGA P000
+              0
+              0
+            
+          
+        
+        
+          ADRD
+          A/D Self-Diagnosis Data Register
+          0xF8
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              AD
+              Converted Value 15 to 0
+              0
+              15
+              read-only
+            
+          
+        
+        
+          ADRST
+          A/D Self-Diagnostic Status Register
+          0xFA
+          8
+          read-only
+          
+            
+              DIAGST
+              Self-Diagnosis Status
+              0
+              1
+              
+                
+                  00
+                  Self-diagnosis has not been executed since power-on
+                  #00
+                
+                
+                  01
+                  Self-diagnosis was executed under a condition that the ideal value of the A/D conversion result was 8000h
+                  #01
+                
+                
+                  10
+                  Self-diagnosis was executed under a condition that an ideal value of the A/D conversion result was 0000h
+                  #10
+                
+                
+                  11
+                  Self-diagnosis was executed under a condition than an ideal value of the A/D conversion result is 7FFFh
+                  #11
+                
+              
+            
+          
+        
+        
+          VREFAMPCNT
+          A/D Dedicated Reference Voltage Circuit Control Register
+          0xF4
+          8
+          read-write
+          
+            
+              VREFADCG
+              VREFADC Output Voltage Control
+              1
+              2
+              
+                
+                  0x
+                  1.5 V
+                  #00
+                
+                
+                  10
+                  2.0 V
+                  #10
+                
+                
+                  11
+                  2.5 V
+                  #11
+                
+              
+            
+            
+              VREFADCEN
+              VREFADCG Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disable the VREFADC output
+                  #0
+                
+                
+                  1
+                  Enable the VREFADC output
+                  #1
+                
+              
+            
+            
+              ADSLP
+              Sleep
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal operation
+                  #0
+                
+                
+                  1
+                  Standby
+                  #1
+                
+              
+            
+            
+              OLDETEN
+              OLDET Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable the over current detection.
+                  #0
+                
+                
+                  1
+                  Enable the over current detection.
+                  true
+                
+              
+            
+            
+              BGREN
+              BGR Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Turn off power of BGR
+                  #0
+                
+                
+                  1
+                  Turn on power of BGR
+                  true
+                
+              
+            
+          
+        
+        
+          ADCALEXE
+          A/D Calibration Execution Register
+          0xF2
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CALEXE
+              Calibration Start
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Calibration does not start
+                  #0
+                
+                
+                  1
+                  Calibration starts
+                  #1
+                
+              
+            
+            
+              CALMON
+              Calibration Status Flag
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Calibration not in progress
+                  #0
+                
+                
+                  1
+                  Calibration in progress
+                  #1
+                
+              
+            
+          
+        
+        
+          ADANIM
+          A/D Channel Input Mode Select Register
+          0xF0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              4
+              1
+              ANIM%s
+              Analog Channel Input Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Single-end mode
+                  #0
+                
+                
+                  1
+                  Differential mode
+                  #1
+                
+              
+            
+          
+        
+        
+          ADPGAGS0
+          A/D Programmable Gain Amplifier Gain Setting Register 0
+          0x1A2
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              P002GAIN
+              PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b) when the shingle end is input and each PGA P002 is set. When the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P002DG 1:0.
+              8
+              11
+              read-write
+              
+                
+                  0000
+                  x 2.000 (ADPGADDCR0.P002DEN=0)
+                  #0000
+                
+                
+                  0001
+                  x 2.500 (ADPGADDCR0.P002DEN=0) /  x 1.500 (ADPGADDCR0.P002DEN=1)
+                  #0001
+                
+                
+                  0010
+                  x 2.667 (ADPGADDCR0.P002DEN=0)
+                  #0010
+                
+                
+                  0011
+                  x 2.857 (ADPGADDCR0.P002DEN=0)
+                  #0011
+                
+                
+                  0100
+                  x 3.077 (ADPGADDCR0.P002DEN=0)
+                  #0100
+                
+                
+                  0101
+                  x 3.333 (ADPGADDCR0.P002DEN=0) /  x 2.333 (ADPGADDCR0.P002DEN=1)
+                  #0101
+                
+                
+                  0110
+                  x 3.636 (ADPGADDCR0.P002DEN=0)
+                  #0110
+                
+                
+                  0111
+                  x 4.000 (ADPGADDCR0.P002DEN=0)
+                  #0111
+                
+                
+                  1000
+                  x 4.444 (ADPGADDCR0.P002DEN=0)
+                  #1000
+                
+                
+                  1001
+                  x 5.000 (ADPGADDCR0.P002DEN=0) /  x 4.00 (ADPGADDCR0.P002DEN=1)
+                  #1001
+                
+                
+                  1010
+                  x 5.714 (ADPGADDCR0.P002DEN=0)
+                  #1010
+                
+                
+                  1011
+                  x 6.667 (ADPGADDCR0.P002DEN=0) /  x 5.667 (ADPGADDCR0.P002DEN=1)
+                  #1011
+                
+                
+                  1100
+                  x 8.000 (ADPGADDCR0.P002DEN=0)
+                  #1100
+                
+                
+                  1101
+                  x 10.000 (ADPGADDCR0.P002DEN=0)
+                  #1101
+                
+                
+                  1110
+                  x 13.333 (ADPGADDCR0.P002DEN=0)
+                  #1110
+                
+                
+                  1111
+                  x 1.000 (for offset measurement) (ADPGADDCR0.P002DEN=0)
+                  #1111
+                
+              
+            
+            
+              P001GAIN
+              PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b) when the shingle end is input and each PGA P001 is set. When the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P001DG 1:0.
+              4
+              7
+            
+            
+              P000GAIN
+              PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b) when the shingle end is input and each PGA P000 is set. When the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P000DG 1:0.
+              0
+              3
+            
+          
+        
+        
+          ADPGADCR0
+          A/D Programmable Gain Amplifier Differential Input Control Register
+          0x1B0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              P003DG
+              P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b.
+              12
+              13
+              read-write
+              
+                
+                  00
+                  x 1.5 
+                  #00
+                
+                
+                  01
+                  x 2.333
+                  #01
+                
+                
+                  10
+                  x 4.0
+                  #10
+                
+                
+                  11
+                  x 5.667
+                  #11
+                
+              
+            
+            
+              P002DEN
+              P002 Differential Input Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Differential input is disabled.
+                  #0
+                
+                
+                  1
+                  Differential input is enabled.
+                  #1
+                
+              
+            
+            
+              P002DG
+              P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b.
+              8
+              9
+              read-write
+              
+                
+                  00
+                  x 1.5 
+                  #00
+                
+                
+                  01
+                  x 2.333
+                  #01
+                
+                
+                  10
+                  x 4.0
+                  #10
+                
+                
+                  11
+                  x 5.667
+                  #11
+                
+              
+            
+            
+              P001DEN
+              P001 Differential Input Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Differential input is disabled.
+                  #0
+                
+                
+                  1
+                  Differential input is enabled.
+                  #1
+                
+              
+            
+            
+              P001DG
+              P001 Differential Input Gain SettingNOTE: When these bits are used, set {P001DEN, P001GEN} to 11b.
+              4
+              5
+              read-write
+              
+                
+                  00
+                  x 1.5 
+                  #00
+                
+                
+                  01
+                  x 2.333
+                  #01
+                
+                
+                  10
+                  x 4.0
+                  #10
+                
+                
+                  11
+                  x 5.667
+                  #11
+                
+              
+            
+            
+              P000DEN
+              P000 Differential Input Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Differential input is disabled.
+                  #0
+                
+                
+                  1
+                  Differential input is enabled.
+                  #1
+                
+              
+            
+            
+              P000DG
+              P000 Differential Input Gain SettingNOTE: When these bits are used, set {P000DEN, P000GEN} to 11b.
+              0
+              1
+              read-write
+              
+                
+                  00
+                  x 1.5 
+                  #00
+                
+                
+                  01
+                  x 2.333
+                  #01
+                
+                
+                  10
+                  x 4.0
+                  #10
+                
+                
+                  11
+                  x 5.667
+                  #11
+                
+              
+            
+          
+        
+      
+    
+    
+      R_ADC1
+      0x4005C200
+    
+    
+      R_AGT0
+      Asynchronous General Purpose Timer
+      0x40084000
+      
+        0x00000000
+        0x006
+        registers
+      
+      
+        0x00000008
+        0x003
+        registers
+      
+      
+        0x0000000C
+        0x004
+        registers
+      
+      
+        
+          AGT
+          AGT Counter Register
+          0x00
+          16
+          read-write
+          0xFFFF
+          0xFFFF
+          
+            
+              AGT
+              16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          AGTCMA
+          AGT Compare Match A Register
+          0x02
+          16
+          read-write
+          0xFFFF
+          0xFFFF
+          
+            
+              AGTCMA
+              AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH
+              0
+              15
+              read-write
+            
+          
+        
+        
+          AGTCMB
+          AGT Compare Match B Register
+          0x04
+          16
+          read-write
+          0xFFFF
+          0xFFFF
+          
+            
+              AGTCMB
+              AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH
+              0
+              15
+              read-write
+            
+          
+        
+        
+          AGTCR
+          AGT Control Register
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TCMBF
+              Compare match B flag
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No match
+                  #0
+                
+                
+                  1
+                  Match.
+                  #1
+                
+              
+            
+            
+              TCMAF
+              Compare match A flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No match
+                  #0
+                
+                
+                  1
+                  Match.
+                  #1
+                
+              
+            
+            
+              TUNDF
+              Underflow flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No match
+                  #0
+                
+                
+                  1
+                  Match.
+                  #1
+                
+              
+            
+            
+              TEDGF
+              Active edge judgment flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No active edge received
+                  #0
+                
+                
+                  1
+                  Active edge received.
+                  #1
+                
+              
+            
+            
+              TSTOP
+              AGT count forced stop
+              2
+              2
+              write-only
+              
+                
+                  0
+                  Writing is invalid
+                  #0
+                
+                
+                  1
+                  The count is forcibly stopped.
+                  #1
+                
+              
+            
+            
+              TCSTF
+              AGT count status flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Count stops
+                  #0
+                
+                
+                  1
+                  Count in progress.
+                  #1
+                
+              
+            
+            
+              TSTART
+              AGT count start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Count stops
+                  #0
+                
+                
+                  1
+                  Count starts.
+                  #1
+                
+              
+            
+          
+        
+        
+          AGTMR1
+          AGT Mode Register 1
+          0x09
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TCK
+              Count source
+              4
+              6
+              read-write
+              
+                
+                  000
+                  PCLKB
+                  #000
+                
+                
+                  001
+                  PCLKB/8
+                  #001
+                
+                
+                  011
+                  PCLKB/2
+                  #011
+                
+                
+                  100
+                  Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register
+                  #100
+                
+                
+                  101
+                  Underflow event signal from AGT0*6
+                  #101
+                
+                
+                  110
+                  Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register.
+                  #110
+                
+                
+                  others
+                  settings are prohibited.
+                  true
+                
+              
+            
+            
+              TEDGPL
+              Edge polarity
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Single-edge
+                  #0
+                
+                
+                  1
+                  Both-edge.
+                  #1
+                
+              
+            
+            
+              TMOD
+              Operating mode
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Timer mode
+                  #000
+                
+                
+                  001
+                  Pulse output mode
+                  #001
+                
+                
+                  010
+                  Event counter mode
+                  #010
+                
+                
+                  011
+                  Pulse width measurement mode
+                  #011
+                
+                
+                  100
+                  Pulse period measurement mode.
+                  #100
+                
+                
+                  others
+                  settings are prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          AGTMR2
+          AGT Mode Register 2
+          0x0A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LPM
+              Low Power Mode
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Low Power mode
+                  #1
+                
+              
+            
+            
+              CKS
+              AGTLCLK/AGTSCLK count source clock frequency division ratio
+              0
+              2
+              read-write
+              
+                
+                  000
+                  1/1
+                  #000
+                
+                
+                  001
+                  1/2
+                  #001
+                
+                
+                  010
+                  1/4
+                  #010
+                
+                
+                  011
+                  1/8
+                  #011
+                
+                
+                  100
+                  1/16
+                  #100
+                
+                
+                  101
+                  1/32
+                  #101
+                
+                
+                  110
+                  1/64
+                  #110
+                
+                
+                  111
+                  1/128.
+                  #111
+                
+              
+            
+          
+        
+        
+          AGTIOC
+          AGT I/O Control Register
+          0x0C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TIOGT
+              Count control
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Event is always counted
+                  #00
+                
+                
+                  01
+                  Event is counted during polarity period specified for AGTEEn.
+                  #01
+                
+                
+                  others
+                  settings are prohibited.
+                  true
+                
+              
+            
+            
+              TIPF
+              Input filter
+              4
+              5
+              read-write
+              
+                
+                  00
+                  No filter
+                  #00
+                
+                
+                  01
+                  Filter sampled at PCLKB
+                  #01
+                
+                
+                  10
+                  Filter sampled at PCLKB/8
+                  #10
+                
+                
+                  11
+                  Filter sampled at PCLKB/32
+                  #11
+                
+              
+            
+            
+              TOE
+              AGTOn output enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  AGTOn output disabled
+                  #0
+                
+                
+                  1
+                  AGTOn output enabled.
+                  #1
+                
+              
+            
+            
+              TEDGSEL
+              I/O polarity switchFunction varies depending on the operating mode. 
+              0
+              0
+              read-write
+            
+          
+        
+        
+          AGTISR
+          AGT Event Pin Select Register
+          0x0D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              EEPS
+              AGTEE  polarty selection
+              2
+              2
+              read-write
+              
+                
+                  0
+                  An event is counted during the low-level period
+                  #0
+                
+                
+                  1
+                  An event is counted during the high-level period
+                  #1
+                
+              
+            
+          
+        
+        
+          AGTCMSR
+          AGT Compare Match Function Select Register
+          0x0E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TOPOLB
+              AGTOB polarity select
+              6
+              6
+              read-write
+              
+                
+                  0
+                  AGTOB Output is started at low
+                  #0
+                
+                
+                  1
+                  AGTOB Output is started at high
+                  #1
+                
+              
+            
+            
+              TOEB
+              AGTOB output enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  AGTOB output disabled (port)
+                  #0
+                
+                
+                  1
+                  AGTOB output enabled
+                  #1
+                
+              
+            
+            
+              TCMEB
+              Compare match B register enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disable compare match B register
+                  #0
+                
+                
+                  1
+                  Enable compare match B register
+                  #1
+                
+              
+            
+            
+              TOPOLA
+              AGTOA polarity select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  AGTOA Output is started at low
+                  #0
+                
+                
+                  1
+                  AGTOA Output is started at high
+                  #1
+                
+              
+            
+            
+              TOEA
+              AGTOA output enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  AGTOA output disabled (port)
+                  #0
+                
+                
+                  1
+                  AGTOA output enabled
+                  #1
+                
+              
+            
+            
+              TCMEA
+              Compare match A register enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable compare match A register
+                  #0
+                
+                
+                  1
+                  Enable compare match A register
+                  #1
+                
+              
+            
+          
+        
+        
+          AGTIOSEL
+          AGT Pin Select Register
+          0x0F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TIES
+              AGTIO input enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  External event input is disabled during Software Standby mode
+                  #0
+                
+                
+                  1
+                  External event input is enabled during Software Standby mode.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_AGT1
+      0x40084100
+    
+    
+      R_BUS
+      Bus Interface
+      0x40003000
+      
+        0x00000002
+        0x00A
+        registers
+      
+      
+        0x00000012
+        0x00A
+        registers
+      
+      
+        0x00000022
+        0x00A
+        registers
+      
+      
+        0x00000032
+        0x00A
+        registers
+      
+      
+        0x00000042
+        0x00A
+        registers
+      
+      
+        0x00000052
+        0x00A
+        registers
+      
+      
+        0x00000062
+        0x00A
+        registers
+      
+      
+        0x00000072
+        0x00A
+        registers
+      
+      
+        0x00000802
+        0x02
+        registers
+      
+      
+        0x0000080A
+        0x02
+        registers
+      
+      
+        0x00000812
+        0x02
+        registers
+      
+      
+        0x0000081A
+        0x02
+        registers
+      
+      
+        0x00000822
+        0x02
+        registers
+      
+      
+        0x0000082A
+        0x02
+        registers
+      
+      
+        0x00000832
+        0x02
+        registers
+      
+      
+        0x0000083A
+        0x02
+        registers
+      
+      
+        0x00000842
+        0x02
+        registers
+      
+      
+        0x0000084A
+        0x02
+        registers
+      
+      
+        0x00000852
+        0x02
+        registers
+      
+      
+        0x0000085A
+        0x02
+        registers
+      
+      
+        0x00000862
+        0x02
+        registers
+      
+      
+        0x0000086A
+        0x02
+        registers
+      
+      
+        0x00000872
+        0x02
+        registers
+      
+      
+        0x0000087A
+        0x02
+        registers
+      
+      
+        0x00000880
+        0x02
+        registers
+      
+      
+        0x00000C00
+        0x003
+        registers
+      
+      
+        0x00000C10
+        0x01
+        registers
+      
+      
+        0x00000C14
+        0x003
+        registers
+      
+      
+        0x00000C20
+        0x01
+        registers
+      
+      
+        0x00000C24
+        0x02
+        registers
+      
+      
+        0x00000C40
+        0x01
+        registers
+      
+      
+        0x00000C44
+        0x006
+        registers
+      
+      
+        0x00000C50
+        0x01
+        registers
+      
+      
+        0x00001000
+        0x02
+        registers
+      
+      
+        0x00001004
+        0x02
+        registers
+      
+      
+        0x00001008
+        0x02
+        registers
+      
+      
+        0x0000100C
+        0x02
+        registers
+      
+      
+        0x00001010
+        0x02
+        registers
+      
+      
+        0x00001014
+        0x02
+        registers
+      
+      
+        0x00001100
+        0x02
+        registers
+      
+      
+        0x00001104
+        0x02
+        registers
+      
+      
+        0x00001108
+        0x02
+        registers
+      
+      
+        0x0000110C
+        0x02
+        registers
+      
+      
+        0x00001110
+        0x02
+        registers
+      
+      
+        0x00001114
+        0x02
+        registers
+      
+      
+        0x00001118
+        0x02
+        registers
+      
+      
+        0x0000111C
+        0x02
+        registers
+      
+      
+        0x00001120
+        0x02
+        registers
+      
+      
+        0x00001124
+        0x02
+        registers
+      
+      
+        0x00001128
+        0x02
+        registers
+      
+      
+        0x0000112C
+        0x02
+        registers
+      
+      
+        0x00001130
+        0x02
+        registers
+      
+      
+        0x00001134
+        0x02
+        registers
+      
+      
+        0x00001138
+        0x02
+        registers
+      
+      
+        0x0000113C
+        0x02
+        registers
+      
+      
+        0x00001800
+        0x005
+        registers
+      
+      
+        0x00001810
+        0x005
+        registers
+      
+      
+        0x00001820
+        0x005
+        registers
+      
+      
+        0x00001830
+        0x005
+        registers
+      
+      
+        0x00001840
+        0x005
+        registers
+      
+      
+        0x00001850
+        0x005
+        registers
+      
+      
+        0x00001860
+        0x005
+        registers
+      
+      
+        0x00001870
+        0x005
+        registers
+      
+      
+        0x00001880
+        0x005
+        registers
+      
+      
+        0x00001890
+        0x005
+        registers
+      
+      
+        0x000018A0
+        0x005
+        registers
+      
+      
+        
+          8
+          0x10
+          CSa[%s]
+          CS Registers
+          0x0000
+          
+            MOD
+            Mode Register
+            0x0002
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                PRMOD
+                Page Read Access Mode Select
+                15
+                15
+                read-write
+                
+                  
+                    0
+                    Normal access compatible mode
+                    #0
+                  
+                  
+                    1
+                    External data read continuous assertion mode
+                    #1
+                  
+                
+              
+              
+                PWENB
+                Page Write Access Enable
+                9
+                9
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+              
+                PRENB
+                Page Read Access Enable
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+              
+                EWENB
+                External Wait Enable
+                3
+                3
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+              
+                WRMOD
+                Write Access Mode Select
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Byte strobe mode
+                    #0
+                  
+                  
+                    1
+                    Single write strobe mode
+                    #1
+                  
+                
+              
+            
+          
+          
+            WCR1
+            Wait Control Register 1
+            0x0004
+            32
+            read-write
+            0x07070707
+            0xFFFFFFFF
+            
+              
+                CSRWAIT
+                Normal Read Cycle Wait Select
+                24
+                28
+                read-write
+                
+                  
+                    0x00
+                    No wait is inserted.
+                    0x00
+                  
+                  
+                    others
+                    Wait with a length of CSRWAIT clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                CSWWAIT
+                Normal Write Cycle Wait Select
+                16
+                20
+                read-write
+                
+                  
+                    0x00
+                    No wait is inserted.
+                    0x00
+                  
+                  
+                    others
+                    Wait with a length of CSWWAIT clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                CSPRWAIT
+                Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
+                8
+                10
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of CSPRWAIT clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                CSPWWAIT
+                Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
+                0
+                2
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of CSPWWAIT clock cycle is inserted.
+                    true
+                  
+                
+              
+            
+          
+          
+            WCR2
+            Wait Control Register 2
+            0x0008
+            32
+            read-write
+            0x00000007
+            0xFFFFFFFF
+            
+              
+                CSON
+                CS Assert Wait Select
+                28
+                30
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of CSON clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                WDON
+                Write Data Output Wait Select
+                24
+                26
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of WDON clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                WRON
+                WR Assert Wait Select
+                20
+                22
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of WRON clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                RDON
+                RD Assert Wait Select
+                16
+                18
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of RDON clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                AWAIT
+                CS Assert Wait Select
+                12
+                13
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of AWAIT clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                WDOFF
+                Write Data Output Extension Cycle Select
+                8
+                10
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of WDOFF clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                CSWOFF
+                Write-Access CS Extension Cycle Select
+                4
+                6
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of CSWOFF clock cycle is inserted.
+                    true
+                  
+                
+              
+              
+                CSROFF
+                Read-Access CS Extension Cycle Select
+                0
+                2
+                read-write
+                
+                  
+                    0x0
+                    No wait is inserted.
+                    0x0
+                  
+                  
+                    others
+                    Wait with a length of CSROFF clock cycle is inserted.
+                    true
+                  
+                
+              
+            
+          
+        
+        
+          8
+          0x10
+          CSb[%s]
+          CS Registers
+          0x0800
+          
+            CR
+            Control Register
+            0x002
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                MPXEN
+                Address/Data Multiplexed I/O Interface Select
+                12
+                12
+                read-write
+                
+                  
+                    0
+                    Separate bus interface is selected for area n
+                    #0
+                  
+                  
+                    1
+                    Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)
+                    #1
+                  
+                
+              
+              
+                EMODE
+                Endian Mode
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    Little Endian
+                    #0
+                  
+                  
+                    1
+                    Big Endian
+                    #1
+                  
+                
+              
+              
+                BSIZE
+                External Bus Width Select
+                4
+                5
+                read-write
+                
+                  
+                    00
+                    A 16-bit bus space
+                    #00
+                  
+                  
+                    01
+                    Setting prohibited
+                    #01
+                  
+                  
+                    10
+                    An 8-bit bus space
+                    #10
+                  
+                  
+                    11
+                    Setting prohibited
+                    #11
+                  
+                
+              
+              
+                EXENB
+                Operation Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Disable operation
+                    #0
+                  
+                  
+                    1
+                    Enable operation
+                    #1
+                  
+                
+              
+            
+          
+          
+            REC
+            Recovery Cycle Register
+            0x00A
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                WRCV
+                Write Recovery
+                8
+                11
+                read-write
+                
+                  
+                    0x0
+                    No recovery cycle is inserted.
+                    0x0
+                  
+                  
+                    others
+                    WRCV recovery cycle is inserted.
+                    true
+                  
+                
+              
+              
+                RRCV
+                Read Recovery
+                0
+                3
+                read-write
+                
+                  
+                    0x0
+                    No recovery cycle is inserted.
+                    0x0
+                  
+                  
+                    others
+                    RRCV recovery cycle is inserted.
+                    true
+                  
+                
+              
+            
+          
+        
+        
+          SDRAM
+          SDRAM Registers
+          0x0C00
+          
+            SDCCR
+            SDC Control Register
+            0x00
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                BSIZE
+                SDRAM Bus Width Select
+                4
+                5
+                read-write
+                
+                  
+                    00
+                    A 16-bit bus space
+                    #00
+                  
+                  
+                    01
+                    Setting prohibited
+                    #01
+                  
+                  
+                    10
+                    An 8-bit bus space
+                    #10
+                  
+                  
+                    11
+                    Setting prohibited
+                    #11
+                  
+                
+              
+              
+                EXENB
+                Operation Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDCMOD
+            SDC Mode Register
+            0x01
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                EMODE
+                Endian Mode
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Endian order of SDRAM address space is the same as the endian order of the operating mode
+                    #0
+                  
+                  
+                    1
+                    Endian order of SDRAM address space is not the endian order of the operating mode.
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDAMOD
+            SDRAM Access Mode Register
+            0x02
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                BE
+                Continuous Access Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable.
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDSELF
+            SDRAM Self-Refresh Control Register
+            0x10
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                SFEN
+                SDRAM Self-Refresh Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDRFCR
+            SDRAM Refresh Control Register
+            0x14
+            16
+            read-write
+            0x0001
+            0xFFFF
+            
+              
+                REFW
+                Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) 
+                12
+                15
+                read-write
+              
+              
+                RFC
+                Auto-Refresh Request Interval Setting
+                0
+                11
+                read-write
+                
+                  
+                    0x0
+                    Setting prohibited
+                    0x0
+                  
+                  
+                    others
+                    RFC+1 cycles inserted
+                    true
+                  
+                
+              
+            
+          
+          
+            SDRFEN
+            SDRAM Auto-Refresh Control Register
+            0x16
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                RFEN
+                Auto-Refresh Operation Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Disable
+                    #0
+                  
+                  
+                    1
+                    Enable
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDICR
+            SDRAM Initialization Sequence Control Register
+            0x20
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                INIRQ
+                Initialization Sequence Start
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Invalid
+                    #0
+                  
+                  
+                    1
+                    Initialization sequence starts
+                    #1
+                  
+                
+              
+            
+          
+          
+            SDIR
+            SDRAM Initialization Register
+            0x24
+            16
+            read-write
+            0x0010
+            0xFFFF
+            
+              
+                PRC
+                Initialization Precharge Cycle Count   ( PRF+3 cycles )
+                8
+                10
+                read-write
+              
+              
+                ARFC
+                Initialization Auto-Refresh Count
+                4
+                7
+                read-write
+                
+                  
+                    0x0
+                    Setting prohibited
+                    0x0
+                  
+                  
+                    others
+                    ARFC+1 times
+                    true
+                  
+                
+              
+              
+                ARFI
+                Initialization Auto-Refresh Interval ( PRF+3 cycles )
+                0
+                3
+                read-write
+              
+            
+          
+          
+            SDADR
+            SDRAM Address Register
+            0x40
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                MXC
+                Address Multiplex Select
+                0
+                1
+                read-write
+                
+                  
+                    00
+                    8-bit shift
+                    #00
+                  
+                  
+                    01
+                    9-bit shift
+                    #01
+                  
+                  
+                    10
+                    10-bit shift
+                    #10
+                  
+                  
+                    11
+                    11-bit shift
+                    #11
+                  
+                
+              
+            
+          
+          
+            SDTR
+            SDRAM Timing Register
+            0x44
+            32
+            read-write
+            0x00000002
+            0xFFFFFFFF
+            
+              
+                RAS
+                Row Active Interval
+                16
+                18
+                read-write
+                
+                  
+                    000
+                    1 cycle
+                    #000
+                  
+                  
+                    001
+                    2 cycles
+                    #001
+                  
+                  
+                    010
+                    3 cycles
+                    #010
+                  
+                  
+                    011
+                    4 cycles
+                    #011
+                  
+                  
+                    100
+                    5 cycles
+                    #100
+                  
+                  
+                    101
+                    6 cycles
+                    #101
+                  
+                  
+                    110
+                    7 cycles
+                    #110
+                  
+                  
+                    111
+                    Setting prohibited
+                    #111
+                  
+                
+              
+              
+                RCD
+                Row Column Latency ( RCD+1  cycles )
+                12
+                13
+                read-write
+              
+              
+                RP
+                Row Precharge Interval ( RP+1  cycles )
+                9
+                11
+                read-write
+              
+              
+                WR
+                Write Recovery Interval
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    1 cycle
+                    #0
+                  
+                  
+                    1
+                    2 cycles
+                    #1
+                  
+                
+              
+              
+                CL
+                SDRAMC Column Latency
+                0
+                2
+                read-write
+                
+                  
+                    001
+                    1 cycle
+                    #001
+                  
+                  
+                    010
+                    2 cycles
+                    #010
+                  
+                  
+                    011
+                    3 cycles
+                    #011
+                  
+                  
+                    others
+                    Setting prohibited
+                    true
+                  
+                
+              
+            
+          
+          
+            SDMOD
+            SDRAM Mode Register
+            0x48
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                MR
+                Mode Register SettingWriting to these bits: Mode register set command is issued.
+                0
+                14
+                read-write
+              
+            
+          
+          
+            SDSR
+            SDRAM Status Register
+            0x50
+            8
+            read-only
+            0x00
+            0xFF
+            
+              
+                SRFST
+                Self-Refresh Transition/Recovery Status
+                4
+                4
+                read-only
+                
+                  
+                    0
+                    Transition/recovery not in progress
+                    #0
+                  
+                  
+                    1
+                    Transition/recovery in progress
+                    #1
+                  
+                
+              
+              
+                INIST
+                Initialization Status
+                3
+                3
+                read-only
+                
+                  
+                    0
+                    Initialization sequence not in progress
+                    #0
+                  
+                  
+                    1
+                    Initialization sequence in progress
+                    #1
+                  
+                
+              
+              
+                MRSST
+                Mode Register Setting Status
+                0
+                0
+                read-only
+                
+                  
+                    0
+                    Mode register setting not in progress
+                    #0
+                  
+                  
+                    1
+                    Mode register setting in progress
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          11
+          0x10
+          
+            
+              BUS1
+              BUS1
+              0
+            
+            
+              BUS2
+              BUS2
+              1
+            
+            
+              BUS3
+              BUS3
+              2
+            
+            
+              BUS4
+              BUS4
+              3
+            
+            
+              BUS5
+              BUS5
+              4
+            
+            
+              BUS6
+              BUS6
+              5
+            
+            
+              BUS7
+              BUS7
+              6
+            
+            
+              BUS8
+              BUS8
+              7
+            
+            
+              BUS9
+              BUS9
+              8
+            
+            
+              BUS10
+              BUS10
+              9
+            
+            
+              BUS11
+              BUS11
+              10
+            
+          
+          BUSERR[%s]
+          Bus Error Registers
+          0x1800
+          
+            ADD
+            Bus Error Address Register
+            0x00
+            32
+            read-only
+            0x00000000
+            0x00000000
+            
+              
+                BERAD
+                Bus Error AddressWhen a bus error occurs, It stores an error address.
+                0
+                31
+                read-only
+              
+            
+          
+          
+            STAT
+            Bus Error Status Register
+            0x04
+            8
+            read-only
+            0x00
+            0xFE
+            
+              
+                ERRSTAT
+                Bus Error StatusWhen bus error assert, error flag occurs.
+                7
+                7
+                read-only
+                
+                  
+                    0
+                    No bus error occurred
+                    #0
+                  
+                  
+                    1
+                    Bus error occurred
+                    #1
+                  
+                
+              
+              
+                ACCSTAT
+                Error access statusThe status at the time of the error
+                0
+                0
+                read-only
+                
+                  
+                    0
+                    Read access
+                    #0
+                  
+                  
+                    1
+                    Write Access
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          6
+          0x4
+          
+            
+              M4I
+              M4I
+              0
+            
+            
+              M4D
+              M4D
+              1
+            
+            
+              SYS
+              SYS
+              2
+            
+            
+              DMA
+              DMA
+              3
+            
+            
+              EDM
+              EDM
+              4
+            
+            
+              GPX
+              GPX
+              5
+            
+          
+          BUSM[%s]
+          Master Bus Control Register Array
+          0x1000
+          
+            CNT
+            Master Bus Control Register 
+            0x0
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                IERES
+                Ignore Error Responses
+                15
+                15
+                read-write
+                
+                  
+                    0
+                    Bus error will be reported.
+                    #0
+                  
+                  
+                    1
+                    Bus error will not be reported.
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          16
+          0x4
+          
+            
+              FLI
+              FLI
+              0
+            
+            
+              RAMH
+              RAMH
+              1
+            
+            
+              MBIU
+              MBIU
+              2
+            
+            
+              RAM0
+              RAM0
+              3
+            
+            
+              RAM1
+              RAM1
+              4
+            
+            
+              P0B
+              P0B
+              5
+            
+            
+              P2B
+              P2B
+              6
+            
+            
+              P3B
+              P3B
+              7
+            
+            
+              P4B
+              P4B
+              8
+            
+            
+              PxB
+              PxB
+              9
+            
+            
+              P6B
+              P6B
+              10
+            
+            
+              P7B
+              P7B
+              11
+            
+            
+              FBU
+              FBU
+              12
+            
+            
+              EXT
+              EXT
+              13
+            
+            
+              EXT2
+              EXT2
+              14
+            
+            
+              GPX
+              GPX
+              15
+            
+          
+          BUSS[%s]
+          Slave Bus Control Register Array
+          0x1100
+          
+            CNT
+            Slave Bus Control Register
+            0x00
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                ARBMET
+                Arbitration MethodSpecify the priority between groups
+                4
+                5
+                read-write
+                
+                  
+                    00
+                    fixed priority
+                    #00
+                  
+                  
+                    01
+                    round-robin
+                    #01
+                  
+                  
+                    others
+                    Setting prohibited
+                    true
+                  
+                
+              
+            
+          
+        
+        
+          CSRECEN
+          CS Recovery Cycle Insertion Enable Register
+          0x0880
+          16
+          read-write
+          0x3E3E
+          0xFFFF
+          
+            
+              8
+              1
+              RCVENM%s
+              Multiplexed Bus Recovery Cycle Insertion Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Recovery cycle insertion is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery cycle insertion is enabled.
+                  #1
+                
+              
+            
+            
+              8
+              1
+              RCVEN%s
+              Separate Bus Recovery Cycle Insertion Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Recovery cycle insertion is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery cycle insertion is enabled.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_CAC
+      Clock Frequency Accuracy Measurement Circuit
+      0x40044600
+      
+        0x00000000
+        0x005
+        registers
+      
+      
+        0x00000006
+        0x006
+        registers
+      
+      
+        
+          CACR0
+          CAC Control Register 0 
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CFME
+              Clock Frequency Measurement Enable.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+          
+        
+        
+          CACR1
+          CAC Control Register 1
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              EDGES
+              Valid Edge Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Rising edge
+                  #00
+                
+                
+                  01
+                  Falling edge
+                  #01
+                
+                
+                  10
+                  Both rising and falling edges
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              TCSS
+              Measurement Target Clock Frequency Division Ratio Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  No division
+                  #00
+                
+                
+                  01
+                  x 1/4 clock
+                  #01
+                
+                
+                  10
+                  x 1/8 clock
+                  #10
+                
+                
+                  11
+                  x 1/32 clock
+                  #11
+                
+              
+            
+            
+              FMCS
+              Measurement Target Clock Select
+              1
+              3
+              read-write
+              
+                
+                  000
+                  Main clock
+                  #000
+                
+                
+                  001
+                  Sub-clock
+                  #001
+                
+                
+                  010
+                  HOCO clock
+                  #010
+                
+                
+                  011
+                  MOCO clock
+                  #011
+                
+                
+                  100
+                  LOCO clock
+                  #100
+                
+                
+                  101
+                  Peripheral module clock(PCLKB)
+                  #101
+                
+                
+                  110
+                  IWDTCLK clock
+                  #110
+                
+                
+                  111
+                  Setting prohibited
+                  #111
+                
+              
+            
+            
+              CACREFE
+              CACREF Pin Input Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+          
+        
+        
+          CACR2
+          CAC Control Register 2 
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DFS
+              Digital Filter Selection
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Digital filtering is disabled.
+                  #00
+                
+                
+                  01
+                  The sampling clock for the digital filter is the frequency measuring clock.
+                  #01
+                
+                
+                  10
+                  The sampling clock for the digital filter is the frequency measuring clock divided by 4.
+                  #10
+                
+                
+                  11
+                  The sampling clock for the digital filter is the frequency measuring clock divided by 16.
+                  #11
+                
+              
+            
+            
+              RCDS
+              Measurement Reference Clock Frequency Division Ratio Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  1/32 clock
+                  #00
+                
+                
+                  01
+                  1/128 clock
+                  #01
+                
+                
+                  10
+                  1/1024 clock
+                  #10
+                
+                
+                  11
+                  1/8192 clock
+                  #11
+                
+              
+            
+            
+              RSCS
+              Measurement Reference Clock Select
+              1
+              3
+              read-write
+              
+                
+                  000
+                  Main clock
+                  #000
+                
+                
+                  001
+                  Sub-clock
+                  #001
+                
+                
+                  010
+                  HOCO clock
+                  #010
+                
+                
+                  011
+                  MOCO clock
+                  #011
+                
+                
+                  100
+                  LOCO clock
+                  #100
+                
+                
+                  101
+                  Peripheral module clock(PCLKB)
+                  #101
+                
+                
+                  110
+                  IWDTCLK clock
+                  #110
+                
+                
+                  111
+                  Setting prohibited
+                  #111
+                
+              
+            
+            
+              RPS
+              Reference Signal Select 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  CACREF pin input
+                  #0
+                
+                
+                  1
+                  Internal clock (internally generated signal)
+                  #1
+                
+              
+            
+          
+        
+        
+          CAICR
+          CAC Interrupt Control Register 
+          0x03
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OVFFCL
+              OVFF Clear 
+              6
+              6
+              write-only
+              
+                
+                  0
+                  No effect on operations
+                  #0
+                
+                
+                  1
+                  Clears the OVFF flag
+                  #1
+                
+              
+            
+            
+              MENDFCL
+              MENDF Clear 
+              5
+              5
+              write-only
+              
+                
+                  0
+                  No effect on operations
+                  #0
+                
+                
+                  1
+                  Clears the MENDF flag
+                  #1
+                
+              
+            
+            
+              FERRFCL
+              FERRF Clear
+              4
+              4
+              write-only
+              
+                
+                  0
+                  No effect on operations
+                  #0
+                
+                
+                  1
+                  Clears the FERRF flag
+                  #1
+                
+              
+            
+            
+              OVFIE
+              Overflow Interrupt Request  Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+            
+              MENDIE
+              Measurement End Interrupt Request Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+            
+              FERRIE
+              Frequency Error Interrupt Request Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+          
+        
+        
+          CASTR
+          CAC Status Register 
+          0x04
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              OVFF
+              Counter Overflow Flag 
+              2
+              2
+              read-only
+              
+                
+                  0
+                  The counter has not overflowed.
+                  #0
+                
+                
+                  1
+                  The counter has overflowed.
+                  #1
+                
+              
+            
+            
+              MENDF
+              Measurement End Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Measurement is in progress.
+                  #0
+                
+                
+                  1
+                  Measurement has ended.
+                  #1
+                
+              
+            
+            
+              FERRF
+              Frequency Error Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  The clock frequency is within the range corresponding to the settings.
+                  #0
+                
+                
+                  1
+                  The clock frequency has deviated beyond the range corresponding to the settings (frequency error).
+                  #1
+                
+              
+            
+          
+        
+        
+          CAULVR
+          CAC Upper-Limit Value Setting Register 
+          0x06
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CAULVR
+              CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          CALLVR
+          CAC Lower-Limit Value Setting Register 
+          0x08
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CALLVR
+              CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          CACNTBR
+          CAC Counter Buffer Register
+          0x0A
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              CACNTBR
+              CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input
+              0
+              15
+              read-only
+            
+          
+        
+      
+    
+    
+      R_CAN0
+      Controller Area Network (CAN) Module
+      0x40050000
+      
+        0x00000200
+        0x230
+        registers
+      
+      
+        0x00000820
+        0x039
+        registers
+      
+      
+        
+          32
+          0x10
+          MB[%s]
+          Mailbox
+          0x200
+          
+            ID
+            Mailbox ID Register 
+            0x0
+            32
+            read-write
+            0x00000000
+            0x00000000
+            
+              
+                IDE
+                ID Extension
+                31
+                31
+                read-write
+                
+                  
+                    0
+                    Standard ID
+                    #0
+                  
+                  
+                    1
+                    Extended ID
+                    #1
+                  
+                
+              
+              
+                RTR
+                Remote Transmission Request
+                30
+                30
+                read-write
+                
+                  
+                    0
+                    Data frame
+                    #0
+                  
+                  
+                    1
+                    Remote frame
+                    #1
+                  
+                
+              
+              
+                SID
+                Standard ID 
+                18
+                28
+                read-write
+              
+              
+                EID
+                Extended ID
+                0
+                17
+                read-write
+              
+            
+          
+          
+            DL
+            Mailbox DLC Register 
+            0x4
+            16
+            read-write
+            0x0000
+            0x0000
+            
+              
+                DLC
+                Data Length Code
+                0
+                3
+                read-write
+                
+                  
+                    0000
+                    Data length = 0 byte
+                    #0000
+                  
+                  
+                    0001
+                    Data length = 1 byte
+                    #0001
+                  
+                  
+                    0010
+                    Data length = 2 bytes
+                    #0010
+                  
+                  
+                    0011
+                    Data length = 3 bytes
+                    #0011
+                  
+                  
+                    0100
+                    Data length = 4 bytes
+                    #0100
+                  
+                  
+                    0101
+                    Data length = 5 bytes
+                    #0101
+                  
+                  
+                    0110
+                    Data length = 6 bytes
+                    #0110
+                  
+                  
+                    0111
+                    Data length = 7 bytes
+                    #0111
+                  
+                  
+                    others
+                    Data length = 8 bytes
+                    true
+                  
+                
+              
+            
+          
+          
+            8
+            0x01
+            D[%s]
+            Mailbox Data Register 
+            0x6
+            8
+            read-write
+            0x00
+            0x00
+            
+              
+                DATA
+                DATA0 to DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB-first, and transmission or reception starts from bit 7
+                0
+                7
+                read-write
+              
+            
+          
+          
+            TS
+            Mailbox Timestamp Register 
+            0xE
+            16
+            read-write
+            0x0000
+            0x0000
+            
+              
+                TSH
+                Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
+                8
+                15
+                read-write
+              
+              
+                TSL
+                Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox.
+                0
+                7
+                read-write
+              
+            
+          
+        
+        
+          8
+          0x4
+          MKR[%s]
+          Mask Register 
+          0x400
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              SID
+              Standard ID 
+              18
+              28
+              read-write
+            
+            
+              EID
+              Extended ID
+              0
+              17
+              read-write
+            
+          
+        
+        
+          2
+          0x4
+          FIDCR[%s]
+          FIFO Received ID Compare Registers 
+          0x420
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              IDE
+              ID Extension
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Standard ID
+                  #0
+                
+                
+                  1
+                  Extended ID
+                  #1
+                
+              
+            
+            
+              RTR
+              Remote Transmission Request
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Data frame
+                  #0
+                
+                
+                  1
+                  Remote frame
+                  #1
+                
+              
+            
+            
+              SID
+              Standard ID 
+              18
+              28
+              read-write
+            
+            
+              EID
+              Extended ID
+              0
+              17
+              read-write
+            
+          
+        
+        
+          MKIVLR
+          Mask Invalid Register 
+          0x428
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              MB31
+              mailbox 31 Mask Invalid 
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB30
+              mailbox 30 Mask Invalid 
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB29
+              mailbox 29 Mask Invalid
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB28
+              mailbox 28 Mask Invalid
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB27
+              mailbox 27 Mask Invalid
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB26
+              mailbox 26 Mask Invalid 
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB25
+              mailbox 25 Mask Invalid 
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB24
+              mailbox 24 Mask Invalid 
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB23
+              mailbox 23 Mask Invalid 
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB22
+              mailbox 22 Mask Invalid 
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB21
+              mailbox 21 Mask Invalid 
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB20
+              mailbox 20 Mask Invalid 
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB19
+              mailbox 19 Mask Invalid 
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB18
+              mailbox 18 Mask Invalid 
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB17
+              mailbox 17 Mask Invalid 
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB16
+              mailbox 16 Mask Invalid 
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB15
+              mailbox 15 Mask Invalid 
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB14
+              mailbox 14 Mask Invalid 
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB13
+              mailbox 13 Mask Invalid 
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB12
+              mailbox 12 Mask Invalid  
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB11
+              mailbox 11 Mask Invalid 
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB10
+              mailbox 10 Mask Invalid 
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB9
+              mailbox 9 Mask Invalid 
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB8
+              mailbox 8 Mask Invalid 
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB7
+              mailbox 7 Mask Invalid 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB6
+              mailbox 6 Mask Invalid 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB5
+              mailbox 5 Mask Invalid 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB4
+              mailbox 4 Mask Invalid 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB3
+              mailbox 3 Mask Invalid 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB2
+              mailbox 2 Mask Invalid 
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB1
+              mailbox 1 Mask Invalid 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+            
+              MB0
+              mailbox 0 Mask Invalid  
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Mask valid
+                  #0
+                
+                
+                  1
+                  Mask invalid
+                  #1
+                
+              
+            
+          
+        
+        
+          MIER
+          Mailbox Interrupt Enable Register
+          0x42C
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              MB31
+              mailbox 31 Interrupt Enable 
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB30
+              mailbox 30 Interrupt Enable 
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB29
+              mailbox 29 Interrupt Enable 
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB28
+              mailbox 28 Interrupt Enable 
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB27
+              mailbox 27 Interrupt Enable 
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB26
+              mailbox 26 Interrupt Enable 
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB25
+              mailbox 25 Interrupt Enable 
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB24
+              mailbox 24 Interrupt Enable 
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB23
+              mailbox 23 Interrupt Enable 
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB22
+              mailbox 22 Interrupt Enable 
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB21
+              mailbox 21 Interrupt Enable 
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB20
+              mailbox 20 Interrupt Enable 
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB19
+              mailbox 19 Interrupt Enable 
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB18
+              mailbox 18 Interrupt Enable 
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB17
+              mailbox 17 Interrupt Enable 
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB16
+              mailbox 16 Interrupt Enable 
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB15
+              mailbox 15 Interrupt Enable 
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB14
+              mailbox 14 Interrupt Enable 
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB13
+              mailbox 13 Interrupt Enable 
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB12
+              mailbox 12 Interrupt Enable 
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB11
+              mailbox 11 Interrupt Enable 
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB10
+              mailbox 10 Interrupt Enable 
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB9
+              mailbox 9 Interrupt Enable 
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB8
+              mailbox 8 Interrupt Enable 
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB7
+              mailbox 7 Interrupt Enable 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB6
+              mailbox 6 Interrupt Enable 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB5
+              mailbox 5 Interrupt Enable 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB4
+              mailbox 4 Interrupt Enable 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB3
+              mailbox 3 Interrupt Enable 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB2
+              mailbox 2 Interrupt Enable 
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB1
+              mailbox 1 Interrupt Enable 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB0
+              mailbox 0 Interrupt Enable 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          MIER_FIFO
+          Mailbox Interrupt Enable Register for FIFO Mailbox Mode
+          MIER
+          0x42C
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              MB29
+              Receive FIFO Interrupt Generation Timing Control
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Every time reception is completed
+                  #0
+                
+                
+                  1
+                  When the receive FIFO becomes buffer warning by completion of reception
+                  #1
+                
+              
+            
+            
+              MB28
+              Receive FIFO Interrupt Enable 
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB25
+              Transmit FIFO Interrupt Generation Timing Control
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Every time transmission is completed
+                  #0
+                
+                
+                  1
+                  When the transmit FIFO becomes empty due to completion of transmission
+                  #1
+                
+              
+            
+            
+              MB24
+              Transmit FIFO Interrupt Enable 
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB23
+              mailbox 23 Interrupt Enable 
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB22
+              mailbox 22 Interrupt Enable 
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB21
+              mailbox 21 Interrupt Enable 
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB20
+              mailbox 20 Interrupt Enable 
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB19
+              mailbox 19 Interrupt Enable 
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB18
+              mailbox 18 Interrupt Enable 
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB17
+              mailbox 17 Interrupt Enable 
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB16
+              mailbox 16 Interrupt Enable 
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB15
+              mailbox 15 Interrupt Enable 
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB14
+              mailbox 14 Interrupt Enable 
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB13
+              mailbox 13 Interrupt Enable 
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB12
+              mailbox 12 Interrupt Enable 
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB11
+              mailbox 11 Interrupt Enable 
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB10
+              mailbox 10 Interrupt Enable 
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB9
+              mailbox 9 Interrupt Enable 
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB8
+              mailbox 8 Interrupt Enable 
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB7
+              mailbox 7 Interrupt Enable 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB6
+              mailbox 6 Interrupt Enable 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB5
+              mailbox 5 Interrupt Enable 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB4
+              mailbox 4 Interrupt Enable 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB3
+              mailbox 3 Interrupt Enable 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB2
+              mailbox 2 Interrupt Enable 
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB1
+              mailbox 1 Interrupt Enable 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+            
+              MB0
+              mailbox 0 Interrupt Enable 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt disabled
+                  #0
+                
+                
+                  1
+                  Interrupt enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          32
+          0x1
+          MCTL_TX[%s]
+          Message Control Register for Transmit
+          0x820
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TRMREQ
+              Transmit Mailbox Request
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Not configured for transmission
+                  #0
+                
+                
+                  1
+                  Configured for transmission
+                  #1
+                
+              
+            
+            
+              RECREQ
+              Receive Mailbox Request 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Not configured for reception
+                  #0
+                
+                
+                  1
+                  Configured for reception
+                  #1
+                
+              
+            
+            
+              ONESHOT
+              One-Shot Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  One-shot reception or one-shot transmission disabled
+                  #0
+                
+                
+                  1
+                  One-shot reception or one-shot transmission enabled
+                  #1
+                
+              
+            
+            
+              TRMABT
+              Transmission Abort Complete Flag (Transmit mailbox setting enabled)
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested
+                  #0
+                
+                
+                  1
+                  Transmission abort is completed 
+                  #1
+                
+              
+            
+            
+              TRMACTIVE
+              Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Transmission is pending or transmission is not requested
+                  #0
+                
+                
+                  1
+                  From acceptance of transmission request to completion of transmission, or error/arbitration-lost
+                  #1
+                
+              
+            
+            
+              SENTDATA
+              Transmission Complete Flag
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Transmission is not completed
+                  #0
+                
+                
+                  1
+                  Transmission is completed
+                  #1
+                
+              
+            
+          
+        
+        
+          32
+          0x1
+          MCTL_RX[%s]
+          Message Control Register for Receive
+          MCTL_TX[%s]
+          0x820
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TRMREQ
+              Transmit Mailbox Request
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Not configured for transmission
+                  #0
+                
+                
+                  1
+                  Configured for transmission
+                  #1
+                
+              
+            
+            
+              RECREQ
+              Receive Mailbox Request 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Not configured for reception
+                  #0
+                
+                
+                  1
+                  Configured for reception
+                  #1
+                
+              
+            
+            
+              ONESHOT
+              One-Shot Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  One-shot reception or one-shot transmission disabled
+                  #0
+                
+                
+                  1
+                  One-shot reception or one-shot transmission enabled
+                  #1
+                
+              
+            
+            
+              MSGLOST
+              Message Lost Flag(Receive mailbox setting enabled)
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Message is not overwritten or overrun
+                  #0
+                
+                
+                  1
+                  Message is overwritten or overrun
+                  #1
+                
+              
+            
+            
+              INVALDATA
+              Reception-in-Progress Status Flag (Receive mailbox setting enabled)
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Message valid
+                  #0
+                
+                
+                  1
+                  Message being updated
+                  #1
+                
+              
+            
+            
+              NEWDATA
+              Reception Complete Flag
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No data has been received or 0 is written to the NEWDATA bit
+                  #0
+                
+                
+                  1
+                  A new message is being stored or has been stored to the mailbox
+                  #1
+                
+              
+            
+          
+        
+        
+          CTLR
+          Control Register 
+          0x840
+          16
+          read-write
+          0x0500
+          0xFFFF
+          
+            
+              RBOC
+              Forcible Return From Bus-Off
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Nothing occurred
+                  #0
+                
+                
+                  1
+                  Forcible return from bus-off
+                  #1
+                
+              
+            
+            
+              BOM
+              Bus-Off Recovery Mode by a program request
+              11
+              12
+              read-write
+              
+                
+                  00
+                  Normal mode (ISO11898-1 compliant)
+                  #00
+                
+                
+                  01
+                  Entry to CAN halt mode automatically at bus-off entry
+                  #01
+                
+                
+                  10
+                  Entry to CAN halt mode automatically at bus-off end
+                  #10
+                
+                
+                  11
+                  Entry to CAN halt mode (during bus-off recovery period) 
+                  #11
+                
+              
+            
+            
+              SLPM
+              CAN Sleep Mode
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Other than CAN sleep mode
+                  #0
+                
+                
+                  1
+                  CAN sleep mode
+                  #1
+                
+              
+            
+            
+              CANM
+              CAN Operating Mode Select
+              8
+              9
+              read-write
+              
+                
+                  00
+                  CAN operation mode
+                  #00
+                
+                
+                  01
+                  CAN reset mode
+                  #01
+                
+                
+                  10
+                  CAN halt mode
+                  #10
+                
+                
+                  11
+                  CAN reset mode (forcible transition)
+                  #11
+                
+              
+            
+            
+              TSPS
+              Time Stamp Prescaler Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Every bit time
+                  #00
+                
+                
+                  01
+                  Every 2-bit time
+                  #01
+                
+                
+                  10
+                  Every 4-bit time
+                  #10
+                
+                
+                  11
+                  Every 8-bit time
+                  #11
+                
+              
+            
+            
+              TSRC
+              Time Stamp Counter Reset Command
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Nothing occurred
+                  #0
+                
+                
+                  1
+                  Reset
+                  #1
+                
+              
+            
+            
+              TPM
+              Transmission Priority Mode Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  ID priority transmit mode
+                  #0
+                
+                
+                  1
+                  Mailbox number priority transmit mode
+                  #1
+                
+              
+            
+            
+              MLM
+              Message Lost Mode Select
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Overwrite mode
+                  #0
+                
+                
+                  1
+                  Overrun mode
+                  #1
+                
+              
+            
+            
+              IDFM
+              ID Format Mode Select
+              1
+              2
+              read-write
+              
+                
+                  00
+                  Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids.
+                  #00
+                
+                
+                  01
+                  Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. 
+                  #01
+                
+                
+                  10
+                  Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO.
+                  #10
+                
+                
+                  11
+                  Do not use this combination
+                  #11
+                
+              
+            
+            
+              MBM
+              CAN Mailbox Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Normal mailbox mode
+                  #0
+                
+                
+                  1
+                  FIFO mailbox mode
+                  #1
+                
+              
+            
+          
+        
+        
+          STR
+          Status Register 
+          0x842
+          16
+          read-only
+          0x0500
+          0xFFFF
+          
+            
+              RECST
+              Receive Status Flag (receiver) 
+              14
+              14
+              read-only
+              
+                
+                  0
+                  Bus idle or transmission in progress 
+                  #0
+                
+                
+                  1
+                  Reception in progress
+                  #1
+                
+              
+            
+            
+              TRMST
+              Transmit Status Flag (transmitter)
+              13
+              13
+              read-only
+              
+                
+                  0
+                  Bus idle or reception in progress 
+                  #0
+                
+                
+                  1
+                  Transmission in progress or in bus-off state
+                  #1
+                
+              
+            
+            
+              BOST
+              Bus-Off Status Flag 
+              12
+              12
+              read-only
+              
+                
+                  0
+                  Not in bus-off state 
+                  #0
+                
+                
+                  1
+                  In bus-off state
+                  #1
+                
+              
+            
+            
+              EPST
+              Error-Passive Status Flag
+              11
+              11
+              read-only
+              
+                
+                  0
+                  Not in error-passive state 
+                  #0
+                
+                
+                  1
+                  In error-passive state
+                  #1
+                
+              
+            
+            
+              SLPST
+              CAN Sleep Status Flag 
+              10
+              10
+              read-only
+              
+                
+                  0
+                  Not in CAN sleep mode 
+                  #0
+                
+                
+                  1
+                  In CAN sleep mode
+                  #1
+                
+              
+            
+            
+              HLTST
+              CAN Halt Status Flag 
+              9
+              9
+              read-only
+              
+                
+                  0
+                  Not in CAN halt mode 
+                  #0
+                
+                
+                  1
+                  In CAN halt mode
+                  #1
+                
+              
+            
+            
+              RSTST
+              CAN Reset Status Flag 
+              8
+              8
+              read-only
+              
+                
+                  0
+                  Not in CAN reset mode
+                  #0
+                
+                
+                  1
+                  In CAN reset mode
+                  #1
+                
+              
+            
+            
+              EST
+              Error Status Flag 
+              7
+              7
+              read-only
+              
+                
+                  0
+                  No error occurred
+                  #0
+                
+                
+                  1
+                  Error occurred
+                  #1
+                
+              
+            
+            
+              TABST
+              Transmission Abort Status Flag 
+              6
+              6
+              read-only
+              
+                
+                  0
+                  No mailbox with TRMABT bit = 1
+                  #0
+                
+                
+                  1
+                  Mailbox(es) with TRMABT bit = 1
+                  #1
+                
+              
+            
+            
+              FMLST
+              FIFO Mailbox Message Lost Status Flag
+              5
+              5
+              read-only
+              
+                
+                  0
+                  RFMLF bit = 0
+                  #0
+                
+                
+                  1
+                  RFMLF bit = 1
+                  #1
+                
+              
+            
+            
+              NMLST
+              Normal Mailbox Message Lost Status Flag 
+              4
+              4
+              read-only
+              
+                
+                  0
+                  No mailbox with MSGLOST bit = 1
+                  #0
+                
+                
+                  1
+                  Mailbox(es) with MSGLOST bit = 1
+                  #1
+                
+              
+            
+            
+              TFST
+              Transmit FIFO Status Flag 
+              3
+              3
+              read-only
+              
+                
+                  0
+                  Transmit FIFO is full
+                  #0
+                
+                
+                  1
+                  Transmit FIFO is not full
+                  #1
+                
+              
+            
+            
+              RFST
+              Receive FIFO Status Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  No message in receive FIFO (empty)
+                  #0
+                
+                
+                  1
+                  Message in receive FIFO
+                  #1
+                
+              
+            
+            
+              SDST
+              SENTDATA Status Flag 
+              1
+              1
+              read-only
+              
+                
+                  0
+                  No mailbox with SENTDATA bit = 1
+                  #0
+                
+                
+                  1
+                  Mailbox(es) with SENTDATA bit = 1
+                  #1
+                
+              
+            
+            
+              NDST
+              NEWDATA Status Flag 
+              0
+              0
+              read-only
+              
+                
+                  0
+                  No mailbox with NEWDATA bit = 1
+                  #0
+                
+                
+                  1
+                  Mailbox(es) with NEWDATA bit = 1
+                  #1
+                
+              
+            
+          
+        
+        
+          BCR
+          Bit Configuration Register 
+          0x844
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TSEG1
+              Time Segment 1 Control  
+              28
+              31
+              read-write
+              
+                
+                  0000
+                  Setting prohibited
+                  #0000
+                
+                
+                  0001
+                  Setting prohibited
+                  #0001
+                
+                
+                  0010
+                  Setting prohibited
+                  #0010
+                
+                
+                  0011
+                  4 Tq
+                  #0011
+                
+                
+                  0100
+                  5 Tq
+                  #0100
+                
+                
+                  0101
+                  6 Tq
+                  #0101
+                
+                
+                  0110
+                  7 Tq
+                  #0110
+                
+                
+                  0111
+                  8 Tq
+                  #0111
+                
+                
+                  1000
+                  9 Tq
+                  #1000
+                
+                
+                  1001
+                  10 Tq
+                  #1001
+                
+                
+                  1010
+                  11 Tq
+                  #1010
+                
+                
+                  1011
+                  12 Tq
+                  #1011
+                
+                
+                  1100
+                  13 Tq
+                  #1100
+                
+                
+                  1101
+                  14 Tq
+                  #1101
+                
+                
+                  1110
+                  15 Tq
+                  #1110
+                
+                
+                  1111
+                  16 Tq
+                  #1111
+                
+              
+            
+            
+              BRP
+              Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK).
+              16
+              25
+              read-write
+            
+            
+              SJW
+              Resynchronization Jump Width Control 
+              12
+              13
+              read-write
+              
+                
+                  00
+                  1 Tq
+                  #00
+                
+                
+                  01
+                  2 Tq
+                  #01
+                
+                
+                  10
+                  3 Tq
+                  #10
+                
+                
+                  11
+                  4 Tq
+                  #11
+                
+              
+            
+            
+              TSEG2
+              Time Segment 2 Control
+              8
+              10
+              read-write
+              
+                
+                  000
+                  Setting prohibited
+                  #000
+                
+                
+                  001
+                  2 Tq
+                  #001
+                
+                
+                  010
+                  3 Tq
+                  #010
+                
+                
+                  011
+                  4 Tq
+                  #011
+                
+                
+                  100
+                  5 Tq
+                  #100
+                
+                
+                  101
+                  6 Tq
+                  #101
+                
+                
+                  110
+                  7 Tq
+                  #110
+                
+                
+                  111
+                  8 Tq
+                  #111
+                
+              
+            
+            
+              CCLKS
+              CAN Clock Source Selection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  PCLK (generated by the PLL clock)
+                  #0
+                
+                
+                  1
+                  CANMCLK (generated by the main clock)
+                  #1
+                
+              
+            
+          
+        
+        
+          RFCR
+          Receive FIFO Control Register
+          0x848
+          8
+          read-write
+          0x80
+          0xFF
+          
+            
+              RFEST
+              Receive FIFO Empty Status Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Unread message in receive FIFO
+                  #0
+                
+                
+                  1
+                  No unread message in receive FIFO
+                  #1
+                
+              
+            
+            
+              RFWST
+              Receive FIFO Buffer Warning Status Flag 
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Receive FIFO is not buffer warning
+                  #0
+                
+                
+                  1
+                  Receive FIFO is buffer warning (3 unread messages)
+                  #1
+                
+              
+            
+            
+              RFFST
+              Receive FIFO Full Status Flag
+              5
+              5
+              read-only
+              
+                
+                  0
+                  Receive FIFO is not full
+                  #0
+                
+                
+                  1
+                  Receive FIFO is full (4 unread messages)
+                  #1
+                
+              
+            
+            
+              RFMLF
+              Receive FIFO Message Lost Flag 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  No receive FIFO message lost has occurred
+                  #0
+                
+                
+                  1
+                  Receive FIFO message lost has occurred
+                  #1
+                
+              
+            
+            
+              RFUST
+              Receive FIFO Unread Message Number Status 
+              1
+              3
+              read-only
+              
+                
+                  000
+                  No unread message
+                  #000
+                
+                
+                  001
+                  1 unread message
+                  #001
+                
+                
+                  010
+                  2 unread messages
+                  #010
+                
+                
+                  011
+                  3 unread messages
+                  #011
+                
+                
+                  100
+                  4 unread messages
+                  #100
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              RFE
+              Receive FIFO Enable 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Receive FIFO disabled
+                  #0
+                
+                
+                  1
+                  Receive FIFO enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          RFPCR
+          Receive FIFO Pointer Control Register 
+          0x849
+          8
+          write-only
+          0x00
+          0x00
+          
+            
+              RFPCR
+              The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR.
+              0
+              7
+              write-only
+            
+          
+        
+        
+          TFCR
+          Transmit FIFO Control Register 
+          0x84A
+          8
+          read-write
+          0x80
+          0xFF
+          
+            
+              TFEST
+              Transmit FIFO Empty Status
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Unsent message in transmit FIFO
+                  #0
+                
+                
+                  1
+                  No unsent message in transmit FIFO
+                  #1
+                
+              
+            
+            
+              TFFST
+              Transmit FIFO Full Status 
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Transmit FIFO is not full
+                  #0
+                
+                
+                  1
+                  Transmit FIFO is full (4 unsent messages)
+                  #1
+                
+              
+            
+            
+              TFUST
+              Transmit FIFO Unsent Message Number Status 
+              1
+              3
+              read-only
+              
+                
+                  000
+                  No unsent message
+                  #000
+                
+                
+                  001
+                  1 unsent message
+                  #001
+                
+                
+                  010
+                  2 unsent messages
+                  #010
+                
+                
+                  011
+                  3 unsent messages
+                  #011
+                
+                
+                  100
+                  4 unsent messages
+                  #100
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              TFE
+              Transmit FIFO Enable 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Transmit FIFO disabled
+                  #0
+                
+                
+                  1
+                  Transmit FIFO enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          TFPCR
+          Transmit FIFO Pointer Control Register 
+          0x84B
+          8
+          write-only
+          0x00
+          0x00
+          
+            
+              TFPCR
+              The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR.
+              0
+              7
+              write-only
+            
+          
+        
+        
+          EIER
+          Error Interrupt Enable Register 
+          0x84C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BLIE
+              Bus Lock Interrupt Enable 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Bus lock interrupt disabled
+                  #0
+                
+                
+                  1
+                  Bus lock interrupt enabled
+                  #1
+                
+              
+            
+            
+              OLIE
+              Overload Frame Transmit Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Overload frame transmit interrupt disabled
+                  #0
+                
+                
+                  1
+                  Overload frame transmit interrupt enabled
+                  #1
+                
+              
+            
+            
+              ORIE
+              Overrun Interrupt Enable 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Receive overrun interrupt disabled
+                  #0
+                
+                
+                  1
+                  Receive overrun interrupt enabled
+                  #1
+                
+              
+            
+            
+              BORIE
+              Bus-Off Recovery Interrupt Enable 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Bus-off recovery interrupt disabled
+                  #0
+                
+                
+                  1
+                  Bus-off recovery interrupt enabled
+                  #1
+                
+              
+            
+            
+              BOEIE
+              Bus-Off Entry Interrupt Enable 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Bus-off entry interrupt disabled
+                  #0
+                
+                
+                  1
+                  Bus-off entry interrupt enabled
+                  #1
+                
+              
+            
+            
+              EPIE
+              Error-Passive Interrupt Enable 
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Error-passive interrupt disabled
+                  #0
+                
+                
+                  1
+                  Error-passive interrupt enabled
+                  #1
+                
+              
+            
+            
+              EWIE
+              Error-Warning Interrupt Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Error-warning interrupt disabled
+                  #0
+                
+                
+                  1
+                  Error-warning interrupt enabled
+                  #1
+                
+              
+            
+            
+              BEIE
+              Bus Error Interrupt Enable 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Bus error interrupt disabled
+                  #0
+                
+                
+                  1
+                  Bus error interrupt enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          EIFR
+          Error Interrupt Factor Judge Register 
+          0x84D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BLIF
+              Bus Lock Detect Flag 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  No bus lock detected
+                  #0
+                
+                
+                  1
+                  Bus lock detected
+                  #1
+                
+              
+            
+            
+              OLIF
+              Overload Frame Transmission Detect Flag 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No overload frame transmission detected
+                  #0
+                
+                
+                  1
+                  Overload frame transmission detected
+                  #1
+                
+              
+            
+            
+              ORIF
+              Receive Overrun Detect Flag 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  No receive overrun detected
+                  #0
+                
+                
+                  1
+                  Receive overrun detected
+                  #1
+                
+              
+            
+            
+              BORIF
+              Bus-Off Recovery Detect Flag 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  No bus-off recovery detected
+                  #0
+                
+                
+                  1
+                  Bus-off recovery detected
+                  #1
+                
+              
+            
+            
+              BOEIF
+              Bus-Off Entry Detect Flag 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  No bus-off entry detected
+                  #0
+                
+                
+                  1
+                  Bus-off entry detected
+                  #1
+                
+              
+            
+            
+              EPIF
+              Error-Passive Detect Flag
+              2
+              2
+              read-write
+              
+                
+                  0
+                  No error-passive detected
+                  #0
+                
+                
+                  1
+                  Error-passive detected
+                  #1
+                
+              
+            
+            
+              EWIF
+              Error-Warning Detect Flag 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  No error-warning detected
+                  #0
+                
+                
+                  1
+                  Error-warning detected
+                  #1
+                
+              
+            
+            
+              BEIF
+              Bus Error Detect Flag
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No bus error detected
+                  #0
+                
+                
+                  1
+                  Bus error detected
+                  #1
+                
+              
+            
+          
+        
+        
+          RECR
+          Receive Error Count Register 
+          0x84E
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              RECR
+              Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          TECR
+          Transmit Error Count Register 
+          0x84F
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              TECR
+              Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          ECSR
+          Error Code Store Register 
+          0x850
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              EDPM
+              Error Display Mode Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Output of first detected error code
+                  #0
+                
+                
+                  1
+                  Output of accumulated error code
+                  #1
+                
+              
+            
+            
+              ADEF
+              ACK Delimiter Error Flag
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No ACK delimiter error detected
+                  #0
+                
+                
+                  1
+                  ACK delimiter error detected
+                  #1
+                
+              
+            
+            
+              BE0F
+              Bit Error (dominant) Flag
+              5
+              5
+              read-write
+              
+                
+                  0
+                  No bit error (dominant) detected
+                  #0
+                
+                
+                  1
+                  Bit error (dominant) detected
+                  #1
+                
+              
+            
+            
+              BE1F
+              Bit Error (recessive) Flag
+              4
+              4
+              read-write
+              
+                
+                  0
+                  No bit error (recessive) detected
+                  #0
+                
+                
+                  1
+                  Bit error (recessive) detected
+                  #1
+                
+              
+            
+            
+              CEF
+              CRC Error Flag
+              3
+              3
+              read-write
+              
+                
+                  0
+                  No CRC error detected
+                  #0
+                
+                
+                  1
+                  CRC error detected
+                  #1
+                
+              
+            
+            
+              AEF
+              ACK Error Flag
+              2
+              2
+              read-write
+              
+                
+                  0
+                  No ACK error detected
+                  #0
+                
+                
+                  1
+                  ACK error detected
+                  #1
+                
+              
+            
+            
+              FEF
+              Form Error Flag
+              1
+              1
+              read-write
+              
+                
+                  0
+                  No form error detected
+                  #0
+                
+                
+                  1
+                  Form error detected
+                  #1
+                
+              
+            
+            
+              SEF
+              Stuff Error Flag
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No stuff error detected
+                  #0
+                
+                
+                  1
+                  Stuff error detected
+                  #1
+                
+              
+            
+          
+        
+        
+          CSSR
+          Channel Search Support Register 
+          0x851
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              CSSR
+              When the value for the channel search is input, the channel number is output to MSSR.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          MSSR
+          Mailbox Search Status Register 
+          0x852
+          8
+          read-only
+          0x80
+          0xFF
+          
+            
+              SEST
+              Search Result Status
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Search result found
+                  #0
+                
+                
+                  1
+                  No search result
+                  #1
+                
+              
+            
+            
+              MBNST
+              Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR.
+              0
+              4
+              read-only
+            
+          
+        
+        
+          MSMR
+          Mailbox Search Mode Register 
+          0x853
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MBSM
+              Mailbox Search Mode Select 
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Receive mailbox search mode
+                  #00
+                
+                
+                  01
+                  Transmit mailbox search mode
+                  #01
+                
+                
+                  10
+                  Message lost search mode
+                  #10
+                
+                
+                  11
+                  Channel search mode
+                  #11
+                
+              
+            
+          
+        
+        
+          TSR
+          Time Stamp Register 
+          0x854
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              TSR
+              Free-running counter value for the time stamp function
+              0
+              15
+              read-only
+            
+          
+        
+        
+          AFSR
+          Acceptance Filter Support Register 
+          0x856
+          16
+          read-write
+          0x0000
+          0x0000
+          
+            
+              AFSR
+              After the standard ID of a received message is written, the value converted for data table search can be read.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          TCR
+          Test Control Register 
+          0x858
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TSTM
+              CAN Test Mode Select 
+              1
+              2
+              read-write
+              
+                
+                  00
+                  Other than CAN test mode
+                  #00
+                
+                
+                  01
+                  Listen-only mode
+                  #01
+                
+                
+                  10
+                  Self-test mode 0 (external loopback)
+                  #10
+                
+                
+                  11
+                  Self-test mode 1 (internal loopback)
+                  #11
+                
+              
+            
+            
+              TSTE
+              CAN Test Mode Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  CAN test mode disabled
+                  #0
+                
+                
+                  1
+                  CAN test mode enabled
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_CAN1
+      0x40051000
+    
+    
+      R_CRC
+      Cyclic Redundancy Check (CRC) Calculator
+      0x40074000
+      
+        0x00000000
+        0x002
+        registers
+      
+      
+        0x00000004
+        0x00A
+        registers
+      
+      
+        
+          CRCCR0
+          CRC Control Register0
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DORCLR
+              CRCDOR Register Clear
+              7
+              7
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clears the CRCDOR register.
+                  #1
+                
+              
+            
+            
+              LMS
+              CRC Calculation Switching
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Generates CRC for LSB first communication.
+                  #0
+                
+                
+                  1
+                  Generates CRC for MSB first communication.
+                  #1
+                
+              
+            
+            
+              GPS
+              CRC Generating Polynomial Switching
+              0
+              2
+              read-write
+              
+                
+                  000
+                  No calculation is executed.
+                  #000
+                
+                
+                  001
+                  8-bit CRC-8 (X8 + X2 + X + 1)
+                  #001
+                
+                
+                  010
+                  16-bit CRC-16 (X16 + X15 + X2 + 1)
+                  #010
+                
+                
+                  011
+                  16-bit CRC-CCITT (X16 + X12 + X5 + 1)
+                  #011
+                
+                
+                  100
+                  32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1)
+                  #100
+                
+                
+                  101
+                  32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1)
+                  #101
+                
+                
+                  others
+                  No calculation is executed.
+                  true
+                
+              
+            
+          
+        
+        
+          CRCCR1
+          CRC Control Register1
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CRCSEN
+              Snoop enable bit
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              CRCSWR
+              Snoop-on-write/read switch bit
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Snoop-on-read
+                  #0
+                
+                
+                  1
+                  Snoop-on-write
+                  #1
+                
+              
+            
+          
+        
+        
+          CRCDIR
+          CRC Data Input Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CRCDIR
+              Calculation input Data (Case of CRC-32, CRC-32C )
+              0
+              31
+              read-write
+            
+          
+        
+        
+          CRCDIR_BY
+          CRC Data Input Register (byte access)
+          CRCDIR
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CRCDIR_BY
+              Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT )
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CRCDOR
+          CRC Data Output Register
+          0x08
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CRCDOR
+              Calculation output Data (Case of CRC-32, CRC-32C )
+              0
+              31
+              read-write
+            
+          
+        
+        
+          CRCDOR_HA
+          CRC Data Output Register (halfword access)
+          CRCDOR
+          0x08
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CRCDOR_HA
+              Calculation output Data (Case of CRC-16 or CRC-CCITT )
+              0
+              15
+              read-write
+            
+          
+        
+        
+          CRCDOR_BY
+          CRC Data Output Register(byte access)
+          CRCDOR
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CRCDOR_BY
+              Calculation output Data (Case of CRC-8 )
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CRCSAR
+          Snoop Address Register
+          0x0C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CRCSA
+              snoop address bitSet the I/O register address to snoop
+              0
+              13
+              read-write
+              
+                
+                  0x0003
+                  SCI0.TDR
+                  0x0003
+                
+                
+                  0x0005
+                  SCI0.RDR
+                  0x0005
+                
+                
+                  0x0023
+                  SCI1.TDR
+                  0x0023
+                
+                
+                  0x0025
+                  SCI1.RDR
+                  0x0025
+                
+                
+                  0x0043
+                  SCI2.TDR
+                  0x0043
+                
+                
+                  0x0045
+                  SCI2.RDR
+                  0x0045
+                
+                
+                  0x0063
+                  SCI3.TDR
+                  0x0063
+                
+                
+                  0x0065
+                  SCI3.RDR
+                  0x0065
+                
+                
+                  0x0083
+                  SCI4.TDR
+                  0x0083
+                
+                
+                  0x0085
+                  SCI4.RDR
+                  0x0085
+                
+                
+                  0x00A3
+                  SCI5.TDR
+                  0x00A3
+                
+                
+                  0x00A5
+                  SCI5.RDR
+                  0x00A5
+                
+                
+                  0x00C3
+                  SCI6.TDR
+                  0x00C3
+                
+                
+                  0x00C5
+                  SCI6.RDR
+                  0x00C5
+                
+                
+                  0x00E3
+                  SCI7.TDR
+                  0x00E3
+                
+                
+                  0x00E5
+                  SCI7.RDR
+                  0x00E5
+                
+                
+                  0x0103
+                  SCI8.TDR
+                  0x0103
+                
+                
+                  0x0105
+                  SCI8.RDR
+                  0x0105
+                
+                
+                  0x0123
+                  SCI9.TDR
+                  0x0123
+                
+                
+                  0x0125
+                  SCI9.RDR
+                  0x0125
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+      
+    
+    
+      R_CTSU
+      Capacitive Touch Sensing Unit
+      0x40081000
+      
+        0x00000000
+        0x01E
+        registers
+      
+      
+        
+          CTSUCR0
+          CTSU Control Register 0
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUTXVSEL
+              CTSU Transmission power supply selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Select Vcc
+                  #0
+                
+                
+                  1
+                  Select internal logic power supply
+                  #1
+                
+              
+            
+            
+              CTSUINIT
+              CTSU Control Block Initialization
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Writing a 0 has no effect, this bit is read as 0.
+                  #0
+                
+                
+                  1
+                  initializes the CTSU control block and registers.
+                  #1
+                
+              
+            
+            
+              CTSUIOC
+              CTSU Transmit Pin Control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Low-level output from transmit channel non-measurement pin.
+                  #0
+                
+                
+                  1
+                  High-level output from transmit channel non-measurement pin.
+                  #1
+                
+              
+            
+            
+              CTSUSNZ
+              CTSU Wait State Power-Saving Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Power-saving function during wait state is disabled.
+                  #0
+                
+                
+                  1
+                  Power-saving function during wait state is enabled.
+                  #1
+                
+              
+            
+            
+              CTSUCAP
+              CTSU Measurement Operation Start Trigger Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Software trigger.
+                  #0
+                
+                
+                  1
+                  External trigger.
+                  #1
+                
+              
+            
+            
+              CTSUSTRT
+              CTSU Measurement Operation Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Measurement operation stops.
+                  #0
+                
+                
+                  1
+                  Measurement operation starts.
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCR1
+          CTSU Control Register 1
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUMD
+              CTSU Measurement Mode Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Self-capacitance single scan mode
+                  #00
+                
+                
+                  01
+                  Self-capacitance multi-scan mode
+                  #01
+                
+                
+                  10
+                  Mutual capacitance simple scan mode
+                  #10
+                
+                
+                  11
+                  Mutual capacitance full scan mode
+                  #11
+                
+              
+            
+            
+              CTSUCLK
+              CTSU Operating Clock Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  PCLK
+                  #00
+                
+                
+                  01
+                  PCLK/2 (PCLK divided by 2)
+                  #01
+                
+                
+                  10
+                  PCLK/2 (PCLK divided by 4)
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              CTSUATUNE1
+              CTSU Power Supply Capacity Adjustment 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Normal output
+                  #0
+                
+                
+                  1
+                  High-current output
+                  #1
+                
+              
+            
+            
+              CTSUATUNE0
+              CTSU Power Supply Operating Mode Setting
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Normal operating mode
+                  #0
+                
+                
+                  1
+                  Low-voltage operating mode
+                  #1
+                
+              
+            
+            
+              CTSUCSW
+              CTSU LPF Capacitance Charging Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Turned off capacitance switch
+                  #0
+                
+                
+                  1
+                  Turned on capacitance switch
+                  #1
+                
+              
+            
+            
+              CTSUPON
+              CTSU Power Supply Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Powered off the CTSU
+                  #0
+                
+                
+                  1
+                  Powered on the CTSU
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUSDPRS
+          CTSU Synchronous Noise Reduction Setting Register
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUSOFF
+              CTSU High-Pass Noise Reduction Function Off Setting
+              6
+              6
+              read-write
+              
+                
+                  0
+                  High-pass noise reduction function turned on
+                  #0
+                
+                
+                  1
+                  High-pass noise reduction function turned off
+                  #1
+                
+              
+            
+            
+              CTSUPRMODE
+              CTSU Base Period and Pulse Count Setting
+              4
+              5
+              read-write
+              
+                
+                  00
+                  510 pulses
+                  #00
+                
+                
+                  01
+                  126 pulses
+                  #01
+                
+                
+                  10
+                  62 pulses (recommended setting value)
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              CTSUPRRATIO
+              CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b)
+              0
+              3
+              read-write
+            
+          
+        
+        
+          CTSUSST
+          CTSU Sensor Stabilization Wait Control Register 
+          0x03
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUSST
+              CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CTSUMCH0
+          CTSU Measurement Channel Register 0
+          0x04
+          8
+          read-write
+          0x3F
+          0xFF
+          
+            
+              CTSUMCH0
+              CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If  the value of CTSUMCH0 was set to b'111111 in  mode other than self-capacitor single scan mode, the measurement is stopped.
+              0
+              5
+              read-write
+              
+                
+                  TS0
+                  measured TS0
+                  0
+                
+                
+                  TS1
+                  measured TS1
+                  1
+                
+                
+                  TS2
+                  measured TS2
+                  2
+                
+                
+                  TS3
+                  measured TS3
+                  3
+                
+                
+                  TS4
+                  measured TS4
+                  4
+                
+                
+                  TS5
+                  measured TS5
+                  5
+                
+                
+                  TS6
+                  measured TS6
+                  6
+                
+                
+                  TS7
+                  measured TS7
+                  7
+                
+                
+                  TS8
+                  measured TS8
+                  8
+                
+                
+                  TS9
+                  measured TS9
+                  9
+                
+                
+                  TS10
+                  measured TS10
+                  10
+                
+                
+                  TS11
+                  measured TS11
+                  11
+                
+                
+                  TS12
+                  measured TS12
+                  12
+                
+                
+                  TS13
+                  measured TS13
+                  13
+                
+                
+                  TS14
+                  measured TS14
+                  14
+                
+                
+                  TS15
+                  measured TS15
+                  15
+                
+                
+                  TS16
+                  measured TS16
+                  16
+                
+                
+                  TS17
+                  measured TS17
+                  17
+                
+                
+                  TS18
+                  measured TS18
+                  18
+                
+                
+                  TS19
+                  measured TS19
+                  19
+                
+                
+                  TS20
+                  measured TS20
+                  20
+                
+                
+                  TS21
+                  measured TS21
+                  21
+                
+                
+                  TS22
+                  measured TS22
+                  22
+                
+                
+                  TS23
+                  measured TS23
+                  23
+                
+                
+                  TS24
+                  measured TS24
+                  24
+                
+                
+                  TS25
+                  measured TS25
+                  25
+                
+                
+                  TS26
+                  measured TS26
+                  26
+                
+                
+                  TS27
+                  measured TS27
+                  27
+                
+                
+                  TS28
+                  measured TS28
+                  28
+                
+                
+                  TS29
+                  measured TS29
+                  29
+                
+                
+                  TS30
+                  measured TS30
+                  30
+                
+                
+                  TS31
+                  measured TS31
+                  31
+                
+                
+                  TS32
+                  measured TS32
+                  32
+                
+                
+                  TS33
+                  measured TS33
+                  33
+                
+                
+                  TS34
+                  measured TS34
+                  34
+                
+                
+                  TS35
+                  measured TS35
+                  35
+                
+                
+                  STOP
+                  Conversion Stopped
+                  #111111
+                
+              
+            
+          
+        
+        
+          CTSUMCH1
+          CTSU Measurement Channel Register 1
+          0x05
+          8
+          read-write
+          0x3F
+          0xFF
+          
+            
+              CTSUMCH1
+              CTSU Measurement Channel 1Note1: If  the value of CTSUMCH1 was set to b'111111, the measurement is stopped.
+              0
+              5
+              read-only
+              
+                
+                  TS0
+                  measured TS0
+                  0
+                
+                
+                  TS1
+                  measured TS1
+                  1
+                
+                
+                  TS2
+                  measured TS2
+                  2
+                
+                
+                  TS3
+                  measured TS3
+                  3
+                
+                
+                  TS4
+                  measured TS4
+                  4
+                
+                
+                  TS5
+                  measured TS5
+                  5
+                
+                
+                  TS6
+                  measured TS6
+                  6
+                
+                
+                  TS7
+                  measured TS7
+                  7
+                
+                
+                  TS8
+                  measured TS8
+                  8
+                
+                
+                  TS9
+                  measured TS9
+                  9
+                
+                
+                  TS10
+                  measured TS10
+                  10
+                
+                
+                  TS11
+                  measured TS11
+                  11
+                
+                
+                  TS12
+                  measured TS12
+                  12
+                
+                
+                  TS13
+                  measured TS13
+                  13
+                
+                
+                  TS14
+                  measured TS14
+                  14
+                
+                
+                  TS15
+                  measured TS15
+                  15
+                
+                
+                  TS16
+                  measured TS16
+                  16
+                
+                
+                  TS17
+                  measured TS17
+                  17
+                
+                
+                  TS18
+                  measured TS18
+                  18
+                
+                
+                  TS19
+                  measured TS19
+                  19
+                
+                
+                  TS20
+                  measured TS20
+                  20
+                
+                
+                  TS21
+                  measured TS21
+                  21
+                
+                
+                  TS22
+                  measured TS22
+                  22
+                
+                
+                  TS23
+                  measured TS23
+                  23
+                
+                
+                  TS24
+                  measured TS24
+                  24
+                
+                
+                  TS25
+                  measured TS25
+                  25
+                
+                
+                  TS26
+                  measured TS26
+                  26
+                
+                
+                  TS27
+                  measured TS27
+                  27
+                
+                
+                  TS28
+                  measured TS28
+                  28
+                
+                
+                  TS29
+                  measured TS29
+                  29
+                
+                
+                  TS30
+                  measured TS30
+                  30
+                
+                
+                  TS31
+                  measured TS31
+                  31
+                
+                
+                  TS32
+                  measured TS32
+                  32
+                
+                
+                  TS33
+                  measured TS33
+                  33
+                
+                
+                  TS34
+                  measured TS34
+                  34
+                
+                
+                  TS35
+                  measured TS35
+                  35
+                
+                
+                  STOP
+                  Conversion Stopped
+                  #111111
+                
+              
+            
+          
+        
+        
+          5
+          1
+          CTSUCHAC[%s]
+          CTSU Channel Enable Control Register
+          0x06
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              TS%s
+              CTSU Channel Enable Control 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not measure
+                  0
+                
+                
+                  1
+                  Measure
+                  1
+                
+              
+            
+          
+        
+        
+          5
+          1
+          CTSUCHTRC[%s]
+          CTSU Channel Transmit/Receive Control Register
+          0x0B
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              TS%s
+              CTSU Channel Transmit/Receive Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUDCLKC
+          CTSU High-Pass Noise Reduction Control Register
+          0x10
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUSSCNT
+              CTSU Diffusion Clock Mode ControlNOTE: This bit  should be set to 11b.
+              4
+              5
+              read-write
+            
+            
+              CTSUSSMOD
+              CTSU Diffusion Clock Mode SelectNOTE: This bit  should be set to 00b.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CTSUST
+          CTSU Status Register
+          0x11
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CTSUPS
+              CTSU Mutual Capacitance Status Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  First measurement
+                  #0
+                
+                
+                  1
+                  Second measurement
+                  #1
+                
+              
+            
+            
+              CTSUROVF
+              CTSU Reference Counter Overflow Flag
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No overflow
+                  #0
+                
+                
+                  1
+                  An overflow
+                  #1
+                
+              
+            
+            
+              CTSUSOVF
+              CTSU Sensor Counter Overflow Flag
+              5
+              5
+              read-write
+              
+                
+                  0
+                  No overflow
+                  #0
+                
+                
+                  1
+                  An overflow
+                  #1
+                
+              
+            
+            
+              CTSUDTSR
+              CTSU Data Transfer Status Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Measurement result has been read
+                  #0
+                
+                
+                  1
+                  Measurement result has not been read
+                  #1
+                
+              
+            
+            
+              CTSUSTC
+              CTSU Measurement Status Counter
+              0
+              2
+              read-only
+              
+                
+                  000
+                  Status 0
+                  #000
+                
+                
+                  001
+                  Status 1
+                  #001
+                
+                
+                  010
+                  Status 2
+                  #010
+                
+                
+                  011
+                  Status 3
+                  #011
+                
+                
+                  100
+                  Status 4
+                  #100
+                
+                
+                  101
+                  Status 5
+                  #101
+                
+              
+            
+          
+        
+        
+          CTSUSSC
+          CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 
+          0x12
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CTSUSSDIV
+              CTSU Spectrum Diffusion Frequency Division Setting
+              8
+              11
+              read-write
+              
+                
+                  0000
+                  4.00 <= fb
+                  #0000
+                
+                
+                  0001
+                  2.00 <= fb < 4.00
+                  #0001
+                
+                
+                  0010
+                  1.33 <= fb < 2.00
+                  #0010
+                
+                
+                  0011
+                  1.00 <= fb < 1.33
+                  #0011
+                
+                
+                  0100
+                  0.80 <= fb < 1.00
+                  #0100
+                
+                
+                  0101
+                  0.67 <= fb < 0.80
+                  #0101
+                
+                
+                  0110
+                  0.57 <= fb < 0.67
+                  #0110
+                
+                
+                  0111
+                  0.50 <= fb < 0.57
+                  #0111
+                
+                
+                  1000
+                  0.44 <= fb < 0.50
+                  #1000
+                
+                
+                  1001
+                  0.40 <= fb < 0.44
+                  #1001
+                
+                
+                  1010
+                  0.36 <= fb < 0.40
+                  #1010
+                
+                
+                  1011
+                  0.33 <= fb < 0.36
+                  #1011
+                
+                
+                  1100
+                  0.31 <= fb < 0.33
+                  #1100
+                
+                
+                  1101
+                  0.29 <= fb < 0.31
+                  #1101
+                
+                
+                  1110
+                  0.27 <= fb < 0.29
+                  #1110
+                
+                
+                  1111
+                  fb < 0.27
+                  #1111
+                
+              
+            
+          
+        
+        
+          CTSUSO0
+          CTSU Sensor Offset Register 0
+          0x14
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CTSUSNUM
+              CTSU Measurement Count Setting
+              10
+              15
+              read-write
+            
+            
+              CTSUSO
+              CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 )
+              0
+              9
+              read-write
+            
+          
+        
+        
+          CTSUSO1
+          CTSU Sensor Offset Register 1
+          0x16
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CTSUICOG
+              CTSU ICO Gain Adjustment
+              13
+              14
+              read-write
+              
+                
+                  00
+                  100 percent gain
+                  #00
+                
+                
+                  01
+                  66 percent gain
+                  #01
+                
+                
+                  10
+                  50 percent gain
+                  #10
+                
+                
+                  11
+                  40 percent gain
+                  #11
+                
+              
+            
+            
+              CTSUSDPA
+              CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2
+              8
+              12
+              read-write
+            
+            
+              CTSURICOA
+              CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 )
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CTSUSC
+          CTSU Sensor Counter
+          0x18
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              CTSUSC
+              CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          CTSURC
+          CTSU Reference Counter
+          0x1A
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              CTSURC
+              CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          CTSUERRS
+          CTSU Error Status Register 
+          0x1C
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              CTSUICOMP
+              TSCAP Voltage Error Monitor
+              15
+              15
+              read-only
+              
+                
+                  0
+                  Normal TSCAP voltage
+                  #0
+                
+                
+                  1
+                  Abnormal TSCAP voltage
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_CTSU2
+      Capacitive Touch Sensing Unit
+      0x40082000
+      
+        0x00
+        12
+        registers
+      
+      
+        0x0C
+        8
+        registers
+      
+      
+        0x14
+        8
+        registers
+      
+      
+        0x1C
+        4
+        registers
+      
+      
+        0x20
+        8
+        registers
+      
+      
+        0x28
+        16
+        registers
+      
+      
+        
+          CTSUCRA
+          CTSU Control Register A
+          0x00
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              STRT
+              CTSU Measurement Operation Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Stop measurement operation
+                  #0
+                
+                
+                  1
+                  Start measurement operation
+                  #1
+                
+              
+            
+            
+              CAP
+              CTSU Measurement Operation Start Trigger Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Software trigger
+                  #0
+                
+                
+                  1
+                  External trigger
+                  #1
+                
+              
+            
+            
+              SNZ
+              CTSU Wait State Power-Saving Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disable power-saving function during wait state
+                  #0
+                
+                
+                  1
+                  Enable power-saving function during wait state
+                  #1
+                
+              
+            
+            
+              CFCON
+              CTSU CFC Power on Control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  CFC power off
+                  #0
+                
+                
+                  1
+                  CFC power on
+                  #1
+                
+              
+            
+            
+              INIT
+              CTSU Control Block Initialization
+              4
+              4
+              write-only
+            
+            
+              PUMPON
+              CTSU Boost Circuit Control
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Boost circuit off
+                  #0
+                
+                
+                  1
+                  Boost circuit on
+                  #1
+                
+              
+            
+            
+              TXVSEL
+              CTSU Transmission Power Supply Selection
+              6
+              7
+              read-write
+              
+                
+                  00
+                  VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method.
+                  #00
+                
+                
+                  01
+                  VCC is selected as the power supply for the transmit pins in self-capacitance method.
+                  #01
+                
+                
+                  10
+                  VCL is selected as the power-supply voltage for the transmit pins.
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              PON
+              CTSU Power Supply Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Power off the CTSU
+                  #0
+                
+                
+                  1
+                  Power on the CTSU
+                  #1
+                
+              
+            
+            
+              CSW
+              CTSU LPF Capacitance Charging Control
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Turn off capacitance switch
+                  #0
+                
+                
+                  1
+                  Turn on capacitance switch
+                  #1
+                
+              
+            
+            
+              ATUNE0
+              CTSU Power Supply Operating Mode Setting
+              10
+              10
+              read-write
+              
+                
+                  0
+                  VCC ≥ 2.4 V: Normal operating mode
+  VCC < 2.4 V: Setting prohibited
+  
+                  #0
+                
+                
+                  1
+                  Low-voltage operating mode
+                  #1
+                
+              
+            
+            
+              ATUNE1
+              CTSU Current Range Adjustment
+              11
+              11
+              read-write
+              
+                
+                  0
+                  40 µA when CTSUATUNE2 = 0
+  20 µA when CTSUATUNE2 = 1
+  
+                  #0
+                
+                
+                  1
+                  80 µA when CTSUATUNE2 = 0
+  160 µA when CTSUATUNE2 = 1
+  
+                  #1
+                
+              
+            
+            
+              CLK
+              CTSU Operating Clock Select
+              12
+              13
+              read-write
+              
+                
+                  00
+                  PCLKB
+                  #00
+                
+                
+                  01
+                  PCLKB/2 (PCLKB divided by 2)
+                  #01
+                
+                
+                  10
+                  PCLKB/4 (PCLKB divided by 4)
+                  #10
+                
+                
+                  11
+                  PCLKB/8 (PCLKB divided by 8)
+                  #11
+                
+              
+            
+            
+              MD0
+              CTSU Measurement Mode Select 0
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Single scan mode
+                  #0
+                
+                
+                  1
+                  Multi-scan mode
+                  #1
+                
+              
+            
+            
+              MD1
+              CTSU Measurement Mode Select 1
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Single scan mode
+                  #0
+                
+                
+                  1
+                  Multi-scan mode
+                  #1
+                
+              
+            
+            
+              MD2
+              CTSU Measurement Mode Select 2
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Measure the current that flows through the switched capacitor.
+                  #0
+                
+                
+                  1
+                  Measure the transfer charge in CFC circuit (high speed measurement)
+                  #1
+                
+              
+            
+            
+              ATUNE2
+              CTSU Current Range Adjustment
+              17
+              17
+              read-write
+              
+                
+                  0
+                  40 µA when CTSUATUNE1 = 0
+  80 µA when CTSUATUNE2 = 1
+  
+                  #0
+                
+                
+                  1
+                  20 µA when CTSUATUNE1 = 0
+  160 µA when CTSUATUNE2 = 1
+  
+                  #1
+                
+              
+            
+            
+              LOAD
+              CTSU Measurement Load Control
+              18
+              19
+              read-write
+              
+                
+                  00
+                  Normal measurement mode
+                  #00
+                
+                
+                  01
+                  Load off mode
+                  #01
+                
+                
+                  10
+                  Current load mode
+                  #10
+                
+                
+                  11
+                  Resistance load mode
+                  #11
+                
+              
+            
+            
+              POSEL
+              CTSU Non-measured Channel Output Select
+              20
+              21
+              read-write
+              
+                
+                  00
+                  Output low through GPIO
+                  #00
+                
+                
+                  01
+                  Hi-Z
+                  #01
+                
+                
+                  10
+                  Output low through the power setting in the TXVSEL[1:0] bits
+                  #10
+                
+                
+                  11
+                  Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits
+                  #11
+                
+              
+            
+            
+              SDPSEL
+              CTSU Sensor Drive Pulse Select
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Random pulse mode
+                  #0
+                
+                
+                  1
+                  High resolution pulse mode
+                  #1
+                
+              
+            
+            
+              FCMODE
+              CTSU SUCLK Control
+              23
+              23
+              read-write
+              
+                
+                  0
+                  SUCLK is used as frequency diffusion clock
+                  #0
+                
+                
+                  1
+                  SUCLK is used as recovery clock for multi-clock measurement
+                  #1
+                
+              
+            
+            
+              STCLK
+              CTSU STCLK Select
+              24
+              29
+              read-write
+            
+            
+              DCMODE
+              CTSU Current Measurement Mode Select
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Current measurement mode
+                  #1
+                
+              
+            
+            
+              DCBACK
+              CTSU Current Measurement Feedback Select
+              31
+              31
+              read-write
+              
+                
+                  0
+                  TSCAP pin is selected
+                  #0
+                
+                
+                  1
+                  Measurement pin is selected
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCRAL
+          CTSU Control Register A
+          CTSUCRA
+          0x00
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCR0
+          CTSU Control Register A
+          CTSUCRA
+          0x00
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCR1
+          CTSU Control Register A
+          CTSUCRA
+          0x01
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCR2
+          CTSU Control Register A
+          CTSUCRAH
+          0x02
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCR3
+          CTSU Control Register A
+          CTSUCRA
+          0x03
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCRB
+          CTSU Control Register B
+          0x04
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              PRRATIO
+              CTSU Measurement Time and Pulse Count Adjustment
+              0
+              3
+              read-write
+            
+            
+              PRMODE
+              CTSU Base Period and Pulse Count Setting
+              4
+              5
+              read-write
+              
+                
+                  00
+                  510 pulses (512 pulses when PROFF bit is 1)
+                  #00
+                
+                
+                  01
+                  126 pulses (128 pulses when PROFF bit is 1)
+                  #01
+                
+                
+                  10
+                  62 pulses (recommended setting) (64 pulses when PROFF bit is 1)
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              SOFF
+              CTSU High-Pass Noise Reduction Function Off Setting
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Turn spectrum diffusion on.
+                  #0
+                
+                
+                  1
+                  Turn spectrum diffusion off.
+                  #1
+                
+              
+            
+            
+              PROFF
+              CTSU Random Number Off Control
+              7
+              7
+              read-write
+              
+                
+                  0
+                  There is random number control.
+                  #0
+                
+                
+                  1
+                  There is no random number control.
+                  #1
+                
+              
+            
+            
+              SST
+              CTSU Sensor Stabilization Wait Control
+              8
+              15
+              read-write
+            
+            
+              SSMOD
+              CTSU SUCLK Diffusion Mode Select
+              24
+              26
+              read-write
+            
+            
+              SSCNT
+              CTSU SUCLK Diffusion Control
+              28
+              29
+              read-write
+            
+          
+        
+        
+          CTSUCRBL
+          CTSU Control Register B
+          CTSUCRB
+          0x04
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSDPRS
+          CTSU Control Register B
+          CTSUCRB
+          0x04
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUSST
+          CTSU Control Register B
+          CTSUCRB
+          0x05
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCRBH
+          CTSU Control Register B
+          CTSUCRB
+          0x06
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUDCLKC
+          CTSU Control Register B
+          CTSUCRB
+          0x07
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUMCH
+          CTSU Measurement Channel Register
+          0x08
+          32
+          read-write
+          0x00003f3f
+          0xffffffff
+          
+            
+              MCH0
+              CTSU Measurement Channel 0
+              0
+              5
+              read-write
+              
+                
+                  0x00
+                  TS00
+                  0x00
+                
+                
+                  0x02
+                  TS02
+                  0x02
+                
+                
+                  0x04
+                  TS04
+                  0x04
+                
+                
+                  0x05
+                  TS05
+                  0x05
+                
+                
+                  0x06
+                  TS06
+                  0x06
+                
+                
+                  0x07
+                  TS07
+                  0x07
+                
+                
+                  0x08
+                  TS08
+                  0x08
+                
+                
+                  0x09
+                  TS09
+                  0x09
+                
+                
+                  0x0A
+                  TS10
+                  0x0a
+                
+                
+                  0x0B
+                  TS11
+                  0x0b
+                
+                
+                  0x0C
+                  TS12
+                  0x0c
+                
+                
+                  0x0D
+                  TS13
+                  0x0d
+                
+                
+                  0x0E
+                  TS14
+                  0x0e
+                
+                
+                  0x0F
+                  TS15
+                  0x0f
+                
+                
+                  0x10
+                  TS16
+                  0x10
+                
+                
+                  0x11
+                  TS17
+                  0x11
+                
+                
+                  0x12
+                  TS18
+                  0x12
+                
+                
+                  0x15
+                  TS21
+                  0x15
+                
+                
+                  0x16
+                  TS22
+                  0x16
+                
+                
+                  0x17
+                  TS23
+                  0x17
+                
+                
+                  0x18
+                  TS24
+                  0x18
+                
+                
+                  0x19
+                  TS25
+                  0x19
+                
+                
+                  0x1A
+                  TS26
+                  0x1a
+                
+                
+                  0x1B
+                  TS27
+                  0x1b
+                
+                
+                  0x1C
+                  TS28
+                  0x1c
+                
+                
+                  0x1D
+                  TS29
+                  0x1d
+                
+                
+                  0x1E
+                  TS30
+                  0x1e
+                
+                
+                  0x1F
+                  TS31
+                  0x1f
+                
+                
+                  0x20
+                  TS32
+                  0x20
+                
+                
+                  0x21
+                  TS33
+                  0x21
+                
+                
+                  0x22
+                  TS34
+                  0x22
+                
+                
+                  0x23
+                  TS35
+                  0x23
+                
+                
+                  0x3F
+                  Measurement is being stopped.
+                  0x3f
+                
+              
+            
+            
+              MCH1
+              CTSU Measurement Channel 1
+              8
+              13
+              read-write
+              
+                
+                  0x00
+                  TS00
+                  0x00
+                
+                
+                  0x02
+                  TS02
+                  0x02
+                
+                
+                  0x04
+                  TS04
+                  0x04
+                
+                
+                  0x05
+                  TS05
+                  0x05
+                
+                
+                  0x06
+                  TS06
+                  0x06
+                
+                
+                  0x07
+                  TS07
+                  0x07
+                
+                
+                  0x08
+                  TS08
+                  0x08
+                
+                
+                  0x09
+                  TS09
+                  0x09
+                
+                
+                  0x0A
+                  TS10
+                  0x0a
+                
+                
+                  0x0B
+                  TS11
+                  0x0b
+                
+                
+                  0x0C
+                  TS12
+                  0x0c
+                
+                
+                  0x0D
+                  TS13
+                  0x0d
+                
+                
+                  0x0E
+                  TS14
+                  0x0e
+                
+                
+                  0x0F
+                  TS15
+                  0x0f
+                
+                
+                  0x10
+                  TS16
+                  0x10
+                
+                
+                  0x11
+                  TS17
+                  0x11
+                
+                
+                  0x12
+                  TS18
+                  0x12
+                
+                
+                  0x15
+                  TS21
+                  0x15
+                
+                
+                  0x16
+                  TS22
+                  0x16
+                
+                
+                  0x17
+                  TS23
+                  0x17
+                
+                
+                  0x18
+                  TS24
+                  0x18
+                
+                
+                  0x19
+                  TS25
+                  0x19
+                
+                
+                  0x1A
+                  TS26
+                  0x1a
+                
+                
+                  0x1B
+                  TS27
+                  0x1b
+                
+                
+                  0x1C
+                  TS28
+                  0x1c
+                
+                
+                  0x1D
+                  TS29
+                  0x1d
+                
+                
+                  0x1E
+                  TS30
+                  0x1e
+                
+                
+                  0x1F
+                  TS31
+                  0x1f
+                
+                
+                  0x20
+                  TS32
+                  0x20
+                
+                
+                  0x21
+                  TS33
+                  0x21
+                
+                
+                  0x22
+                  TS34
+                  0x22
+                
+                
+                  0x23
+                  TS35
+                  0x23
+                
+                
+                  0x3F
+                  Measurement is being stopped.
+                  0x3f
+                
+              
+            
+            
+              MCA0
+              CTSU Multiple Valid Clock Control
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Valid
+                  #0
+                
+                
+                  1
+                  Invalid
+                  #1
+                
+              
+            
+            
+              MCA1
+              CTSU Multiple Valid Clock Control
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Valid
+                  #0
+                
+                
+                  1
+                  Invalid
+                  #1
+                
+              
+            
+            
+              MCA2
+              CTSU Multiple Valid Clock Control
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Valid
+                  #0
+                
+                
+                  1
+                  Invalid
+                  #1
+                
+              
+            
+            
+              MCA3
+              CTSU Multiple Valid Clock Control
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Valid
+                  #0
+                
+                
+                  1
+                  Invalid
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUMCHL
+          CTSU Measurement Channel Register
+          CTSUMCH
+          0x08
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUMCH0
+          CTSU Measurement Channel Register
+          CTSUMCH
+          0x08
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUMCH1
+          CTSU Measurement Channel Register
+          CTSUMCH
+          0x09
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUMCHH
+          CTSU Measurement Channel Register
+          CTSUMCH
+          0x0A
+          16
+          read-write
+          0x3f3f
+          0xffff
+        
+        
+          CTSUMFAF
+          CTSU Measurement Channel Register
+          CTSUMCHH
+          0x0A
+          8
+          read-write
+          0x3f
+          0xff
+        
+        
+          CTSUCHACA
+          CTSU Channel Enable Control Register A
+          0x0C
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              CHAC00
+              CTSU Channel Enable Control A
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC02
+              CTSU Channel Enable Control A
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC04
+              CTSU Channel Enable Control A
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC05
+              CTSU Channel Enable Control A
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC06
+              CTSU Channel Enable Control A
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC07
+              CTSU Channel Enable Control A
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC08
+              CTSU Channel Enable Control A
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC09
+              CTSU Channel Enable Control A
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC10
+              CTSU Channel Enable Control A
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC11
+              CTSU Channel Enable Control A
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC12
+              CTSU Channel Enable Control A
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC13
+              CTSU Channel Enable Control A
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC14
+              CTSU Channel Enable Control A
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC15
+              CTSU Channel Enable Control A
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC16
+              CTSU Channel Enable Control A
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC17
+              CTSU Channel Enable Control A
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC18
+              CTSU Channel Enable Control A
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC21
+              CTSU Channel Enable Control A
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC22
+              CTSU Channel Enable Control A
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC23
+              CTSU Channel Enable Control A
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC24
+              CTSU Channel Enable Control A
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC25
+              CTSU Channel Enable Control A
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC26
+              CTSU Channel Enable Control A
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC27
+              CTSU Channel Enable Control A
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC28
+              CTSU Channel Enable Control A
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC29
+              CTSU Channel Enable Control A
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC30
+              CTSU Channel Enable Control A
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC31
+              CTSU Channel Enable Control A
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCHACAL
+          CTSU Channel Enable Control Register A
+          CTSUCHACA
+          0x0C
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHAC0
+          CTSU Channel Enable Control Register A
+          CTSUCHACA
+          0x0C
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHAC1
+          CTSU Channel Enable Control Register A
+          CTSUCHACA
+          0x0D
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHACAH
+          CTSU Channel Enable Control Register A
+          CTSUCHACA
+          0x0E
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHAC2
+          CTSU Channel Enable Control Register A
+          CTSUCHACAH
+          0x0E
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHAC3
+          CTSU Channel Enable Control Register A
+          CTSUCHACA
+          0x0F
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHACB
+          CTSU Channel Enable Control Register B
+          0x10
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              CHAC32
+              CTSU Channel Enable Control B
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC33
+              CTSU Channel Enable Control B
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC34
+              CTSU Channel Enable Control B
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+            
+              CHAC35
+              CTSU Channel Enable Control B
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Do not measure.
+                  #0
+                
+                
+                  1
+                  Measure.
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCHACBL
+          CTSU Channel Enable Control Register B
+          CTSUCHACB
+          0x10
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHAC4
+          CTSU Channel Enable Control Register B
+          CTSUCHACB
+          0x10
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHTRCA
+          CTSU Channel Transmit/Receive Control Register A
+          0x14
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              CHTRC
+              CTSU Channel Transmit/Receive Control A
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC02
+              CTSU Channel Transmit/Receive Control A
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC04
+              CTSU Channel Transmit/Receive Control A
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC05
+              CTSU Channel Transmit/Receive Control A
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC06
+              CTSU Channel Transmit/Receive Control A
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC07
+              CTSU Channel Transmit/Receive Control A
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC08
+              CTSU Channel Transmit/Receive Control A
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC09
+              CTSU Channel Transmit/Receive Control A
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC10
+              CTSU Channel Transmit/Receive Control A
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC11
+              CTSU Channel Transmit/Receive Control A
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC12
+              CTSU Channel Transmit/Receive Control A
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC13
+              CTSU Channel Transmit/Receive Control A
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC14
+              CTSU Channel Transmit/Receive Control A
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC15
+              CTSU Channel Transmit/Receive Control A
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC16
+              CTSU Channel Transmit/Receive Control A
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC17
+              CTSU Channel Transmit/Receive Control A
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC18
+              CTSU Channel Transmit/Receive Control A
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC21
+              CTSU Channel Transmit/Receive Control A
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC22
+              CTSU Channel Transmit/Receive Control A
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC23
+              CTSU Channel Transmit/Receive Control A
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC24
+              CTSU Channel Transmit/Receive Control A
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC25
+              CTSU Channel Transmit/Receive Control A
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC26
+              CTSU Channel Transmit/Receive Control A
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC27
+              CTSU Channel Transmit/Receive Control A
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC28
+              CTSU Channel Transmit/Receive Control A
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC29
+              CTSU Channel Transmit/Receive Control A
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC30
+              CTSU Channel Transmit/Receive Control A
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC31
+              CTSU Channel Transmit/Receive Control A
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCHTRCAL
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCA
+          0x14
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHTRC0
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCA
+          0x14
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHTRC1
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCA
+          0x15
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHTRCAH
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCA
+          0x16
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHTRC2
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCAH
+          0x16
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHTRC3
+          CTSU Channel Transmit/Receive Control Register A
+          CTSUCHTRCA
+          0x17
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUCHTRCB
+          CTSU Channel Transmit/Receive Control Register B
+          0x18
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              CHTRC32
+              CTSU Channel Transmit/Receive Control B
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC33
+              CTSU Channel Transmit/Receive Control B
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC34
+              CTSU Channel Transmit/Receive Control B
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+            
+              CHTRC35
+              CTSU Channel Transmit/Receive Control B
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Reception
+                  #0
+                
+                
+                  1
+                  Transmission
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUCHTRCBL
+          CTSU Channel Transmit/Receive Control Register B
+          CTSUCHTRCB
+          0x18
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCHTRC4
+          CTSU Channel Transmit/Receive Control Register B
+          CTSUCHTRCB
+          0x18
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUSR
+          CTSU Status Register
+          0x1C
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              MFC
+              CTSU Multi-clock Counter
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Multi-clock 0
+                  #00
+                
+                
+                  01
+                  Multi-clock 1
+                  #01
+                
+                
+                  10
+                  Multi-clock 2
+                  #10
+                
+                
+                  11
+                  Multi-clock 3
+                  #11
+                
+              
+            
+            
+              ICOMPRST
+              CTSU CTSUICOMP1 Flag Reset
+              5
+              5
+              write-only
+            
+            
+              ICOMP1
+              CTSU Sense Current Error Monitor
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Normal sensor current
+                  #0
+                
+                
+                  1
+                  Abnormal sensor current
+                  #1
+                
+              
+            
+            
+              ICOMP0
+              TSCAP Voltage Error Monitor
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Normal TSCAP voltage
+                  #0
+                
+                
+                  1
+                  Abnormal TSCAP voltage
+                  #1
+                
+              
+            
+            
+              STC
+              CTSU Measurement Status Counter
+              8
+              10
+              read-only
+              
+                
+                  000
+                  Status 0
+                  #000
+                
+                
+                  001
+                  Status 1
+                  #001
+                
+                
+                  010
+                  Status 2
+                  #010
+                
+                
+                  011
+                  Status 3
+                  #011
+                
+                
+                  100
+                  Status 4
+                  #100
+                
+                
+                  101
+                  Status 5
+                  #101
+                
+              
+            
+            
+              DTSR
+              CTSU Data Transfer Status Flag
+              12
+              12
+              read-only
+              
+                
+                  0
+                  Read
+                  #0
+                
+                
+                  1
+                  Not read
+                  #1
+                
+              
+            
+            
+              SENSOVF
+              CTSU Sensor Counter Overflow Flag
+              13
+              13
+              read-write
+              
+                
+                  0
+                  No overflow occurred
+                  #0
+                
+                
+                  1
+                  Overflow occurred
+                  #1
+                
+              
+            
+            
+              PS
+              CTSU Mutual Capacitance Status Flag
+              15
+              15
+              read-only
+              
+                
+                  0
+                  First measurement
+                  #0
+                
+                
+                  1
+                  Second measurement
+                  #1
+                
+              
+            
+            
+              CFCRDCH
+              CTSU CFC Read Channel Select
+              16
+              21
+              read-write
+              
+                
+                  0x00
+                  TS00
+                  0x00
+                
+                
+                  0x02
+                  TS02 (CFC)
+                  0x02
+                
+                
+                  0x04
+                  TS04
+                  0x04
+                
+                
+                  0x05
+                  TS05
+                  0x05
+                
+                
+                  0x06
+                  TS06
+                  0x06
+                
+                
+                  0x07
+                  TS07
+                  0x07
+                
+                
+                  0x08
+                  TS08 (CFC)
+                  0x08
+                
+                
+                  0x09
+                  TS09 (CFC)
+                  0x09
+                
+                
+                  0x0A
+                  TS10 (CFC)
+                  0x0a
+                
+                
+                  0x0B
+                  TS11 (CFC)
+                  0x0b
+                
+                
+                  0x0C
+                  TS12 (CFC)
+                  0x0c
+                
+                
+                  0x0D
+                  TS13 (CFC)
+                  0x0d
+                
+                
+                  0x0E
+                  TS14 (CFC)
+                  0x0e
+                
+                
+                  0x0F
+                  TS15 (CFC)
+                  0x0f
+                
+                
+                  0x10
+                  TS16 (CFC)
+                  0x10
+                
+                
+                  0x11
+                  TS17
+                  0x11
+                
+                
+                  0x12
+                  TS18
+                  0x12
+                
+                
+                  0x15
+                  TS21
+                  0x15
+                
+                
+                  0x16
+                  TS22
+                  0x16
+                
+                
+                  0x17
+                  TS23
+                  0x17
+                
+                
+                  0x18
+                  TS24
+                  0x18
+                
+                
+                  0x19
+                  TS25
+                  0x19
+                
+                
+                  0x1A
+                  TS26 (CFC)
+                  0x1a
+                
+                
+                  0x1B
+                  TS27 (CFC)
+                  0x1b
+                
+                
+                  0x1C
+                  TS28 (CFC)
+                  0x1c
+                
+                
+                  0x1D
+                  TS29 (CFC)
+                  0x1d
+                
+                
+                  0x1E
+                  TS30 (CFC)
+                  0x1e
+                
+                
+                  0x1F
+                  TS31 (CFC)
+                  0x1f
+                
+                
+                  0x20
+                  TS32 (CFC)
+                  0x20
+                
+                
+                  0x21
+                  TS33 (CFC)
+                  0x21
+                
+                
+                  0x22
+                  TS34 (CFC)
+                  0x22
+                
+                
+                  0x23
+                  TS35 (CFC)
+                  0x23
+                
+              
+            
+          
+        
+        
+          CTSUSRL
+          CTSU Status Register
+          CTSUSR
+          0x1C
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSR0
+          CTSU Status Register
+          CTSUSR
+          0x1C
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUST
+          CTSU Status Register
+          CTSUSR
+          0x1D
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUSRH
+          CTSU Status Register
+          CTSUSR
+          0x1E
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSR2
+          CTSU Status Register
+          CTSUSRH
+          0x1E
+          8
+          read-write
+          0x00
+          0xff
+        
+        
+          CTSUSO
+          CTSU Sensor Offset Register
+          0x20
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              SO
+              CTSU Sensor Offset Adjustment
+              0
+              9
+              read-write
+            
+            
+              SNUM
+              CTSU Measurement Count Setting
+              10
+              17
+              read-write
+            
+            
+              SSDIV
+              CTSU Spectrum Diffusion Frequency Division Setting
+              20
+              23
+              read-write
+            
+            
+              SDPA
+              CTSU Base Clock Setting
+              24
+              31
+              read-write
+            
+          
+        
+        
+          CTSUSO0
+          CTSU Sensor Offset Register
+          CTSUSO
+          0x20
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSO1
+          CTSU Sensor Offset Register
+          CTSUSO
+          0x22
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSCNT
+          CTSU Sensor Counter Register
+          0x24
+          32
+          read-only
+          0x00000000
+          0xffffffff
+          
+            
+              SENSCNT
+              CTSU Sensor Counter
+              0
+              15
+              read-only
+            
+          
+        
+        
+          CTSUSC
+          CTSU Sensor Counter Register
+          CTSUSCNT
+          0x24
+          16
+          read-only
+          0x0000
+          0xffff
+        
+        
+          CTSUCALIB
+          CTSU Calibration Register
+          0x28
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              TSOD
+              CTSU TS Pins Fixed Output Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Electrostatic capacitance measurement mode
+                  #0
+                
+                
+                  1
+                  TS pins fix output (High output/Low output).
+                  #1
+                
+              
+            
+            
+              DRV
+              CTSU Calibration Setting Bit 1
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Electrostatic capacitance measurement mode
+                  #0
+                
+                
+                  1
+                  Calibration setting 1
+                  #1
+                
+              
+            
+            
+              SUCLKEN
+              CTSU SUCLK Enable Control
+              6
+              6
+              read-write
+              
+                
+                  0
+                  SUCLK operation is disabled.
+                  #0
+                
+                
+                  1
+                  SUCLK operation is enabled.
+                  #1
+                
+              
+            
+            
+              TSOC
+              CTSU Calibration Setting Bit 2
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Electrostatic capacitance measurement mode
+                  #0
+                
+                
+                  1
+                  Calibration setting 2
+                  #1
+                
+              
+            
+            
+              IOC
+              CTSU Transfer Pins Control
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Low level
+                  #0
+                
+                
+                  1
+                  High level
+                  #1
+                
+              
+            
+            
+              CFCRDMD
+              CTSU CFC Counter Read Mode Select
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Read by DTC
+                  #0
+                
+                
+                  1
+                  Read by CPU
+                  #1
+                
+              
+            
+            
+              DCOFF
+              CTSU Down Converter Control
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Normal operation mode
+                  #0
+                
+                
+                  1
+                  The down converter is off.
+                  #1
+                
+              
+            
+            
+              CFCMODE
+              CTSU CFC Current Source Switching
+              22
+              22
+              read-write
+              
+                
+                  0
+                  CFC current measurement (normal mode)
+                  #0
+                
+                
+                  1
+                  External current measurement for calibration
+                  #1
+                
+              
+            
+            
+              DACCARRY
+              CTSU DAC Upper Current Source Carry Control
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Do not carry
+                  #0
+                
+                
+                  1
+                  Carry
+                  #1
+                
+              
+            
+            
+              SUCARRY
+              CTSU CCO Carry Control
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Do not carry
+                  #0
+                
+                
+                  1
+                  Carry
+                  #1
+                
+              
+            
+            
+              DACCLK
+              CTSU DAC Modulation Circuit Clock Select
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Divided PCLK specified by CTSUCRA.CLK[1:0] bits
+                  #0
+                
+                
+                  1
+                  SUCLK
+                  #1
+                
+              
+            
+            
+              CCOCLK
+              CTSU CCO Modulation Circuit Clock Select
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Divided PCLK specified by CTSUCRA.CLK[1:0] bits
+                  #0
+                
+                
+                  1
+                  SUCLK
+                  #1
+                
+              
+            
+            
+              CCOCALIB
+              CTSU CCO Calibration Mode Select
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Oscillator calibration mode
+                  #1
+                
+              
+            
+          
+        
+        
+          CTSUDBGR0
+          CTSU Calibration Register
+          CTSUCALIB
+          0x28
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUDBGR1
+          CTSU Calibration Register
+          CTSUCALIB
+          0x2A
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSUCLKA
+          CTSU Sensor Unit Clock Control Register A
+          0x2C
+          32
+          read-write
+          0x00000000
+          0xffffffff
+        
+        
+          CTSUSUCLK0
+          CTSU Sensor Unit Clock Control Register A
+          CTSUSUCLKA
+          0x2C
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSUCLK1
+          CTSU Sensor Unit Clock Control Register A
+          CTSUSUCLKA
+          0x2E
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSUCLKB
+          CTSU Sensor Unit Clock Control Register B
+          0x30
+          32
+          read-write
+          0x00000000
+          0xffffffff
+          
+            
+              SUADJ2
+              CTSU SUCLK Frequency Adjustment
+              0
+              7
+              read-write
+            
+            
+              SUMULTI2
+              CTSU SUCLK Multiplier Rate Setting
+              8
+              15
+              read-write
+            
+            
+              SUADJ3
+              CTSU SUCLK Frequency Adjustment
+              16
+              23
+              read-write
+            
+            
+              SUMULTI3
+              CTSU SUCLK Multiplier Rate Setting
+              24
+              31
+              read-write
+            
+          
+        
+        
+          CTSUSUCLK2
+          CTSU Sensor Unit Clock Control Register B
+          CTSUSUCLKB
+          0x30
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUSUCLK3
+          CTSU Sensor Unit Clock Control Register B
+          CTSUSUCLKB
+          0x32
+          16
+          read-write
+          0x0000
+          0xffff
+        
+        
+          CTSUCFCCNT
+          CTSU CFC Counter Register
+          0x34
+          32
+          read-only
+          0x00000000
+          0xffffffff
+          
+            
+              CFCCNT
+              CTSU CFC Counter
+              0
+              15
+              read-only
+            
+          
+        
+        
+          CTSUCFCCNTL
+          CTSU CFC Counter Register
+          CTSUCFCCNT
+          0x34
+          16
+          read-only
+          0x0000
+          0xffff
+        
+      
+    
+    
+      R_DAC
+      D/A Converter
+      0x4005E000
+      
+        0x00000000
+        0x00A
+        registers
+      
+      
+        
+          DACR
+          D/A Control Register 
+          0x04
+          8
+          read-write
+          0x1F
+          0xFF
+          
+            
+              DAE
+              D/A Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Control D/A conversion of channels 0 and 1 individually
+                  #0
+                
+              
+            
+            
+              2
+              1
+              DAOE%s
+              D/A Output Enable 0
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Analog output of channel 0 (DA0) is disabled.
+                  #0
+                
+                
+                  1
+                  D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          2
+          DADR[%s]
+          D/A Data Register
+          0x00
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DADR
+              D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          DADPR
+          DADR0 Format Select Register
+          0x05
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DPSEL
+              DADRm Format Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Right justified format.
+                  #0
+                
+                
+                  1
+                  Left justified format.
+                  #1
+                
+              
+            
+          
+        
+        
+          DAADSCR
+          D/A-A/D Synchronous Start Control Register 
+          0x06
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DAADST
+              D/A-A/D Synchronous Conversion
+              7
+              7
+              read-write
+              
+                
+                  0
+                  D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled).
+                  #0
+                
+                
+                  1
+                  D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled).
+                  #1
+                
+              
+            
+          
+        
+        
+          DAVREFCR
+          D/A VREF Control Register 
+          0x07
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              REF
+              D/A Reference Voltage Select
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Not selected
+                  #000
+                
+                
+                  001
+                  AVCC0/AVSS0
+                  #001
+                
+                
+                  011
+                  Internal reference voltage/AVSS0
+                  #011
+                
+                
+                  110
+                  VREFH/VREFL
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          DAPC
+          D/A Switch Charge Pump Control Register
+          0x09
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              PUMPEN
+              Charge Pump Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Charge pump disabled
+                  #0
+                
+                
+                  1
+                  Charge pump enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DAAMPCR
+          D/A Output Amplifier Control Register
+          0x08
+          8
+          read-write
+          0x1F
+          0xFF
+          
+            
+              2
+              1
+              DAAMP%s
+              Amplifier Control
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Do not use channel output amplifier
+                  #0
+                
+              
+            
+          
+        
+        
+          DAASWCR
+          D/A Amplifier Stabilization Wait Control Register
+          0x1C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DAASW1
+              Set the DAASW1 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 1. When DAASW1 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 1. When the DAASW1 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 1 is output through the output amplifier.
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Amplifier stabilization wait off (output) for channel 1
+                  #0
+                
+                
+                  1
+                  Amplifier stabilization wait on (high-Z) for channel 1
+                  #1
+                
+              
+            
+            
+              DAASW0
+              Set the DAASW0 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 0. When DAASW0 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 0. When the DAASW0 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 0 is output through the output amplifier.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Amplifier stabilization wait off (output) for channel 0
+                  #0
+                
+                
+                  1
+                  Amplifier stabilization wait on (high-Z) for channel 0
+                  #1
+                
+              
+            
+          
+        
+        
+          DAADUSR
+          D/A A/D Synchronous Unit Select Register
+          0x10C0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              AMADSEL1
+              The DAADUSR register selects the target ADC12 unit for D/A and A/D synchronous conversions. Set bit [1] to 1 to select unit 1 as the target synchronous unit for the MCU. When setting the DAADSCR.DAADST bit to 1 for synchronous conversions, select the target unit in this register in advance. Only set the DAADUSR register while the ADCSR.ADST bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit is set to 0.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Do not select unit 1
+                  #0
+                
+                
+                  1
+                  Select unit 1
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_DAC8
+      8-Bit D/A Converter
+      0x4009E000
+      
+        0x00000000
+        0x002
+        registers
+      
+      
+        0x00000003
+        0x01
+        registers
+      
+      
+        0x00000006
+        0x002
+        registers
+      
+      
+        
+          DAM
+          D/A Converter Mode Register
+          0x03
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DACE1
+              D/A operation enable 1
+              5
+              5
+              read-write
+              
+                
+                  0
+                  D/A conversion disabled for channel 1
+                  #0
+                
+                
+                  1
+                  D/A conversion enabled for channel 1
+                  #1
+                
+              
+            
+            
+              DACE0
+              D/A operation enable 0
+              4
+              4
+              read-write
+              
+                
+                  0
+                  D/A conversion disabled for channel 0
+                  #0
+                
+                
+                  1
+                  D/A conversion enabled for channel 0
+                  #1
+                
+              
+            
+            
+              DAMD1
+              D/A operation mode select 1
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Channel 1 for normal operation mode
+                  #0
+                
+                
+                  1
+                  Channel 1 for real-time output mode(event link)
+                  #1
+                
+              
+            
+            
+              DAMD0
+              D/A operation mode select 0
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Channel 0 for normal operation mode
+                  #0
+                
+                
+                  1
+                  Channel 0 for real-time output mode(event link)
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          0x01
+          DACS[%s]
+          D/A Conversion Value Setting Register %s
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DACS
+              DACS D/A conversion store data 
+              0
+              7
+              read-write
+            
+          
+        
+        
+          DACADSCR
+          D/A A/D Synchronous Start Control Register
+          0x06
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DACADST
+              D/A A/D Synchronous Conversion
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not synchronize DAC8 with ADC16 operation (disable interference reduction between D/A and A/D conversion)
+                  #0
+                
+                
+                  1
+                  Synchronize DAC8 with ADC16 operation (enable interference reduction between D/A and A/D conversion).
+                  #1
+                
+              
+            
+          
+        
+        
+          DACPC
+          D/A SW Charge Pump Control Register
+          0x07
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              PUMPEN
+              Charge pump enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Charge pump disable
+                  #0
+                
+                
+                  1
+                  Charge pump enable
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_DALI0
+      Digital Addressable Lighting Interface
+      0x4008F000
+      
+        0x00000000
+        0x018
+        registers
+      
+      
+        0x0000001E
+        0x006
+        registers
+      
+      
+        0x00000026
+        0x004
+        registers
+      
+      
+        0x0000002E
+        0x006
+        registers
+      
+      
+        0x00000036
+        0x02
+        registers
+      
+      
+        0x0000003A
+        0x004
+        registers
+      
+      
+        
+          BTVTHR1
+          DALI Bit Timing Violation Threshold Register 1
+          0x000
+          16
+          read-write
+          0x4F00
+          0xFFFF
+          
+            
+              BTV2
+              Bit Timing Violation Threshold 2Specifies the bit timing violation threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              15
+              read-write
+            
+            
+              BTV1
+              Bit Timing Violation Threshold 1Specifies the bit timing violation threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          BTVTHR2
+          DALI Bit Timing Violation Threshold Register 2
+          0x002
+          16
+          read-write
+          0x654F
+          0xFFFF
+          
+            
+              BTV4
+              Bit Timing Violation Threshold 4Specifies the bit timing violation threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              15
+              read-write
+            
+            
+              BTV3
+              Bit Timing Violation Threshold 3Specifies the bit timing violation threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          BTVTHR3
+          DALI Bit Timing Violation Threshold Register 3
+          0x004
+          16
+          read-write
+          0x009D
+          0xFFFF
+          
+            
+              BTV5
+              Bit Timing Violation Threshold 5Specifies the bit timing violation threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          BTVTHR4
+          DALI Bit Timing Violation Threshold Register 4
+          0x006
+          16
+          read-write
+          0x00DB
+          0xFFFF
+          
+            
+              BTV6
+              Bit Timing Violation Threshold 6Specifies the bit timing violation threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          COLTHR1
+          DALI Collision Threshold Register 1
+          0x008
+          16
+          read-write
+          0x380F
+          0xFFFF
+          
+            
+              COL2
+              Collision Threshold 2Specifies the collision threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              13
+              read-write
+            
+            
+              COL1
+              Collision Threshold 1Specifies the collision threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              5
+              read-write
+            
+          
+        
+        
+          COLTHR2
+          DALI Collision Threshold Register 2
+          0x00A
+          16
+          read-write
+          0x443C
+          0xFFFF
+          
+            
+              COL4
+              Collision Threshold 4Specifies the collision threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              14
+              read-write
+            
+            
+              COL3
+              Collision Threshold 3Specifies the collision threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          COLTHR3
+          DALI Collision Threshold Register 3
+          0x00C
+          16
+          read-write
+          0x7148
+          0xFFFF
+          
+            
+              COL6
+              Collision Threshold 6Specifies the collision threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              14
+              read-write
+            
+            
+              COL5
+              Collision Threshold 5Specifies the collision threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          COLTHR4
+          DALI Collision Threshold Register 4
+          0x00E
+          16
+          read-write
+          0x8879
+          0xFFFF
+          
+            
+              COL8
+              Collision Threshold 8Specifies the collision threshold value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              8
+              15
+              read-write
+            
+            
+              COL7
+              Collision Threshold 7Specifies the collision threshold value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          COLTHR5
+          DALI Collision Threshold Register 5
+          0x010
+          16
+          read-write
+          0x008E
+          0xFFFF
+          
+            
+              COL9
+              Collision Threshold 9Specifies the collision threshold value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CNFR1
+          DALI Configuration Register 1
+          0x012
+          16
+          read-write
+          0x00FF
+          0xFFFF
+          
+            
+              CHL
+              Character Length
+              12
+              14
+              read-write
+              
+                
+                  000
+                  8 bits
+                  #000
+                
+                
+                  001
+                  16 bits
+                  #001
+                
+                
+                  010
+                  24 bits
+                  #010
+                
+                
+                  011
+                  32 bits
+                  #011
+                
+                
+                  100
+                  20 bits
+                  #100
+                
+                
+                  101
+                  17 bits
+                  #101
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              CKS
+              Clock Select
+              8
+              9
+              read-write
+              
+                
+                  00
+                  PCLK clock (x = 0)
+                  #00
+                
+                
+                  01
+                  PCLK/4 clock (x = 1)
+                  #01
+                
+                
+                  10
+                  PCLK/16 clock (x = 2)
+                  #10
+                
+                
+                  11
+                  PCLK/64 clock (x = 3)
+                  #11
+                
+              
+            
+            
+              BR
+              Clock SelectBit rate setting example is shown in Table
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CNFR2
+          DALI Configuration Register 2
+          0x014
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CDM0
+              Collision Detect ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Destroy area
+                  #0
+                
+                
+                  1
+                  Destroy area and avoidance area (edge)
+                  #1
+                
+              
+            
+            
+              CDE
+              Collision Detect EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Collision detection is disabled.
+                  #0
+                
+                
+                  1
+                  Collision detection is enabled.
+                  #1
+                
+              
+            
+            
+              TXWE
+              DTX Width Modulation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  The width of DTX0 waveform is not modulated.
+                  #0
+                
+                
+                  1
+                  The width of DTX0 waveform is modulated.
+                  #1
+                
+              
+            
+            
+              SGA
+              Save an Edge of Gray Area ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  The edge allowable area of the DRX0 input signal is the default.
+                  #0
+                
+                
+                  1
+                  The edge allowable area of the DRX0 input signal is extended.
+                  #1
+                
+              
+            
+            
+              BTVM
+              Bit Timing Violation ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Edge in gray area between half bit and 2-half bit is not detected as bit timing violation.
+                  #0
+                
+                
+                  1
+                  Edge in gray area between half bit and 2-half bit is detected as bit timing violation.
+                  #1
+                
+              
+            
+            
+              BTVE
+              Bit Timing Violation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Bit timing violation function is disabled.
+                  #0
+                
+                
+                  1
+                  Bit timing violation function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          TXWR1
+          DALI DTX Width Register 1
+          0x016
+          16
+          read-write
+          0x003F
+          0xFFFF
+          
+            
+              TXLW
+              DTX Low WidthDTX0 pin low level width
+              0
+              6
+              read-write
+            
+          
+        
+        
+          TDR1H
+          DALI Transmit Data Register 1H
+          0x01E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DTDR
+              Upper 16-bit DALI transmit data
+              0
+              15
+              read-write
+            
+          
+        
+        
+          TDR1L
+          DALI Transmit Data Register 1L
+          0x020
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DTDR
+              Lower 16-bit DALI transmit data
+              0
+              15
+              read-write
+            
+          
+        
+        
+          TRSTR1
+          DALI Transmit Control Register 1
+          SPDR
+          0x022
+          16
+          write-only
+          0x0000
+          0xFFFF
+          
+            
+              TRST
+              Transmission Start Trigger
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No effect 
+                  #0
+                
+                
+                  1
+                  Transmission Start
+                  #1
+                
+              
+            
+          
+        
+        
+          CTR1
+          DALI Control Register 1
+          0x026
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FEIE
+              DALI_FEI Output Enabling
+              12
+              12
+              read-write
+              
+                
+                  0
+                  DALI_FEI output is disabled.
+                  #0
+                
+                
+                  1
+                  DALI_FEI output is enabled.
+                  #1
+                
+              
+            
+            
+              BPIE
+              DALI_BPI Output Enabling
+              11
+              11
+              read-write
+              
+                
+                  0
+                  DALI_BPI output is disabled.
+                  #0
+                
+                
+                  1
+                  DALI_BPI output is enabled.
+                  #1
+                
+              
+            
+            
+              CLIE
+              DALI_CLI Output Enabling
+              10
+              10
+              read-write
+              
+                
+                  0
+                  DALI_CLI output is disabled.
+                  #0
+                
+                
+                  1
+                  DALI_CLI output is enabled.
+                  #1
+                
+              
+            
+            
+              DEIE
+              DALI_DEI Output Enabling
+              9
+              9
+              read-write
+              
+                
+                  0
+                  DALI_DEI output is disabled.
+                  #0
+                
+                
+                  1
+                  DALI_DEI output is enabled.
+                  #1
+                
+              
+            
+            
+              SDIE
+              DALI_SDI Output Enabling
+              8
+              8
+              read-write
+              
+                
+                  0
+                  DALI_SDI output is disabled.
+                  #0
+                
+                
+                  1
+                  DALI_SDI output is enabled.
+                  #1
+                
+              
+            
+            
+              RE
+              Receive Enabling
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Storing received data is disabled.
+                  #0
+                
+                
+                  1
+                  Storing received data is enabled.
+                  #1
+                
+              
+            
+            
+              TE
+              Transmit Enabling
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Transmit operation is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit operation is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          TXDCTR1
+          DALI DTX Control Register 1
+          0x028
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              TXASE
+              DTX Assert EnablingNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  An internal transmit data is output to the DTX0 pin.
+                  #0
+                
+                
+                  1
+                  The level specified by TXAS bit is output to the DTX0 pin.
+                  #1
+                
+              
+            
+            
+              TXAS
+              DTX Assert LevelNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  The DTX0 pin is driven low.
+                  #0
+                
+                
+                  1
+                  The DTX0 pin is driven high.
+                  #1
+                
+              
+            
+          
+        
+        
+          RDR1H
+          DALI Reception Data Register 1H
+          0x02E
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              DRDR
+              Upper 16-bit of DALI receive data
+              0
+              15
+              read-only
+            
+          
+        
+        
+          RDR1L
+          DALI Reception Data Register 1L
+          0x030
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              DRDR
+              Lower 16-bit of DALI receive data
+              0
+              15
+              read-only
+            
+          
+        
+        
+          STR1
+          DALI Status Register 1
+          0x032
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              RDBL
+              Receive Data Bit LengthThese bits store the bit length for data received successfully
+              10
+              15
+              read-only
+            
+            
+              DAF
+              Destroy Area Flag
+              9
+              9
+              read-only
+              
+                
+                  0
+                  The collision did not occur in the destroy area or 1 was written to the DALI0.FECR1.DAFC bit.
+                  #0
+                
+                
+                  1
+                  The collision occurred in the destroy area.
+                  #1
+                
+              
+            
+            
+              CDF
+              Collision Detect Flag
+              8
+              8
+              read-only
+              
+                
+                  0
+                  No collision occurred or 1 was written to the DALI0.FECR1.CDFC bit.
+                  #0
+                
+                
+                  1
+                  A collision occurred.
+                  #1
+                
+              
+            
+            
+              O32F
+              Over 32-Bit Data Reception Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Receive data is 32 bits or less, or 1 was written to the DALI0.FECR1.O32FC bit.
+                  #0
+                
+                
+                  1
+                  Receive data is 33 bits or more.
+                  #1
+                
+              
+            
+            
+              BPDF
+              Bus Power Down Flag
+              6
+              6
+              read-only
+              
+                
+                  0
+                  No effected
+                  #0
+                
+                
+                  1
+                  Bus power down detected
+                  #1
+                
+              
+            
+            
+              BBF
+              Bus BUSY Flag
+              5
+              5
+              read-only
+              
+                
+                  0
+                  DALI bus is IDLE
+                  #0
+                
+                
+                  1
+                  DALI bus is BUSY
+                  #1
+                
+              
+            
+            
+              TENDF
+              Transmit End Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  1 was written to the DALI0.FECR1.TENDFC bit.
+                  #0
+                
+                
+                  1
+                  Frame transmission has been completed.
+                  #1
+                
+              
+            
+            
+              RDRF
+              Receive Data Register Full Flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  The DALI0.RDR1L register was read or 1 was written to the DALI0.FECR1.RDRFC.
+                  #0
+                
+                
+                  1
+                  Receive data is stored in the DALI0.RDR1L or DALI0.RDR1H register.
+                  #1
+                
+              
+            
+            
+              BTVF
+              Bit Timing Violation Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  No bit timing violation occurred or 1 was written to the DALI0.FECR1.BTVFC bit.
+                  #0
+                
+                
+                  1
+                  Bit timing violation occurred
+                  #1
+                
+              
+            
+            
+              OVF
+              Overrun Error Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  No overrun error occurred or 1 was written to the DALI0.FECR1.OVFC bit.
+                  #0
+                
+                
+                  1
+                  An overrun error occurred.
+                  #1
+                
+              
+            
+            
+              MFEF
+              Manchester Flaming Error Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  No MFE occurred or 1 was written to the DALI0.FECR1.MFEFC bit.
+                  #0
+                
+                
+                  1
+                  An MFE occurred.
+                  #1
+                
+              
+            
+          
+        
+        
+          COLR1
+          DALI Collision Register 1
+          0x036
+          16
+          read-only
+          0x0800
+          0xFFFF
+          
+            
+              TXDCV
+              DTX Collision Value
+              13
+              13
+              read-only
+              
+                
+                  0
+                  Low
+                  #0
+                
+                
+                  1
+                  High
+                  #1
+                
+              
+            
+            
+              RXDCEG
+              DRX Collision Edge
+              12
+              12
+              read-only
+              
+                
+                  0
+                  Falling edge
+                  #0
+                
+                
+                  1
+                  Rising edge
+                  #1
+                
+              
+            
+            
+              RXDMON
+              DRX MonitorThis bit monitors the DRX0 pin value after the DRX0 pin is synchronized
+              11
+              11
+              read-only
+            
+            
+              CLDAF
+              Collision Last Destroy Area Flag
+              10
+              10
+              read-only
+              
+                
+                  0
+                  Collision detected is caused by a DRX0 edge occurrence.
+                  #0
+                
+                
+                  1
+                  Collision detected is not caused by a DRX0 edge occurrence. (Last destroy area)
+                  #1
+                
+              
+            
+            
+              CDTF1
+              Collision Detect Timing Flag 1
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Collision detection started at the edge on a bit period boundary.
+                  #0
+                
+                
+                  1
+                  Collision detection started at the edge in the middle of a bit period. 
+                  #1
+                
+              
+            
+            
+              CFTF2
+              Collision Detect Timing Flag 2
+              0
+              3
+              read-only
+              
+                
+                  0000
+                  After reset is released
+                  #0000
+                
+                
+                  0001
+                  Collision detection timing 1
+                  #0001
+                
+                
+                  0010
+                  Collision detection timing 2
+                  #0010
+                
+                
+                  0011
+                  Collision detection timing 3
+                  #0011
+                
+                
+                  0100
+                  Collision detection timing 4
+                  #0100
+                
+                
+                  0101
+                  Collision detection timing 5
+                  #0101
+                
+                
+                  0110
+                  Collision detection timing 6
+                  #0110
+                
+                
+                  0111
+                  Collision detection timing 7 *1
+                  #0111
+                
+                
+                  1000
+                  Collision detection timing 8 *1
+                  #1000
+                
+                
+                  1001
+                  Collision detection timing 9 *1
+                  #1001
+                
+                
+                  1010
+                  Collision detection timing 10 *1
+                  #1010
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          FECR1
+          DALI Flag Error Clear Register 1
+          0x03A
+          16
+          write-only
+          0x0000
+          0xFFFF
+          
+            
+              DAFC
+              Destroy Area Flag Clear
+              9
+              9
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.DAF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.DAF bit is cleared.
+                  #1
+                
+              
+            
+            
+              CDFC
+              Collision Detect Flag Clear
+              8
+              8
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.CDF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.CDF bit is cleared.
+                  #1
+                
+              
+            
+            
+              O32FC
+              Over 32-Bit Data Reception Flag Clear
+              7
+              7
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.O32F bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.O32F bit is cleared
+                  #1
+                
+              
+            
+            
+              BPDFC
+              Bus Power Down Flag Clear
+              6
+              6
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.BPDF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.BPDF bit is cleared.
+                  #1
+                
+              
+            
+            
+              BBFC
+              Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1.
+              5
+              5
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.BBF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.BBF bit is cleared
+                  #1
+                
+              
+            
+            
+              TENDFC
+              Transmit End Flag Clear
+              4
+              4
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.TENDF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.TENDF bit is cleared
+                  #1
+                
+              
+            
+            
+              RDRFC
+              Receive Data Register Full Flag Clear
+              3
+              3
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.RDRF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.RDRF bit is cleared.
+                  #1
+                
+              
+            
+            
+              BTVFC
+              Bit Timing Violation Flag Clear
+              2
+              2
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.BTVF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.BTVF bit is cleared.
+                  #1
+                
+              
+            
+            
+              OVFC
+              Overrun Error Flag Clear
+              1
+              1
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.OVF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.OVF bit is cleared
+                  #1
+                
+              
+            
+            
+              MFEFC
+              Manchester Flaming Error Flag Clear
+              0
+              0
+              write-only
+              
+                
+                  0
+                  DALI0.STR1.MFEF bit is not cleared.
+                  #0
+                
+                
+                  1
+                  DALI0.STR1.MFEF bit is cleared
+                  #1
+                
+              
+            
+          
+        
+        
+          SWRR1
+          DALI Software Reset Register 1
+          0x03C
+          16
+          write-only
+          0x0000
+          0xFFFF
+          
+            
+              SWR
+              Software ResetWriting 1 to this bit causes a software reset.
+              0
+              0
+              write-only
+            
+          
+        
+      
+    
+    
+      R_DEBUG
+      Debug Function
+      0x4001B000
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        0x00000010
+        0x04
+        registers
+      
+      
+        
+          DBGSTR
+          Debug Status Register
+          0
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CDBGPWRUPREQ
+              Debug power-up request
+              28
+              28
+              read-only
+              
+                
+                  0
+                  0: OCD is not requesting debug power up
+                  #0
+                
+                
+                  1
+                  0: OCD is requesting debug power up
+                  #1
+                
+              
+            
+            
+              CDBGPWRUPACK
+              Debug power-up acknowledge
+              29
+              29
+              
+                
+                  0
+                  Debug power-up request is not acknowledged
+                  #0
+                
+                
+                  1
+                  Debug power-up request is acknowledged
+                  #1
+                
+              
+            
+          
+        
+        
+          DBGSTOPCR
+          Debug Stop Control Register
+          0x10
+          32
+          read-write
+          0x00000003
+          0xFFFFFFFF
+          
+            
+              DBGSTOP_RPER
+              Mask bit for SRAM parity error
+              24
+              24
+            
+            
+              3
+              1
+              DBGSTOP_LVD%s
+              Mask bit for LVD reset/interupt
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Enable reset/interupt on corresponding LVD
+                  #0
+                
+                
+                  1
+                  Mask reset/interupt on corresponding LVD
+                  #1
+                
+              
+            
+            
+              DBGSTOP_RECCR
+              Mask bit for SRAM ECC error
+              25
+              25
+            
+            
+              DBGSTOP_IWDT
+              Mask bit for IWDT reset/interrupt
+              0
+              0
+            
+            
+              DBGSTOP_WDT
+              Mask bit for WDT reset/interrupt 
+              1
+              1
+            
+          
+        
+      
+    
+    
+      R_DMA
+      DMA Controller Common
+      0x40005200
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        
+          DMAST
+          DMAC Module Activation Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DMST
+              DMAC Operation Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled.
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_DMAC0
+      DMA Controller
+      0x40005000
+      
+        0x00000000
+        0x00E
+        registers
+      
+      
+        0x00000010
+        0x02
+        registers
+      
+      
+        0x00000013
+        0x003
+        registers
+      
+      
+        0x00000018
+        0x007
+        registers
+      
+      
+        
+          DMSAR
+          DMA Source Address Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DMSAR
+              Specifies the transfer source start address.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          DMDAR
+          DMA Destination Address Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DMDAR
+              Specifies the transfer destination start address.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          DMCRA
+          DMA Transfer Count Register
+          0x08
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DMCRAH
+              Upper bits of transfer count
+              16
+              25
+              read-write
+            
+            
+              DMCRAL
+              Lower bits of transfer count
+              0
+              15
+              read-write
+            
+          
+        
+        
+          DMCRB
+          DMA Block Transfer Count Register
+          0x0C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DMCRB
+              Specifies the number of block transfer operations or repeat transfer operations.
+              0
+              15
+              read-write
+              
+                
+                  0000
+                  65,536 blocks
+                  #0000
+                
+                
+                  others
+                  DMCRB blocks
+                  true
+                
+              
+            
+          
+        
+        
+          DMTMD
+          DMA Transfer Mode Register
+          0x10
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              MD
+              Transfer Mode Select
+              14
+              15
+              read-write
+              
+                
+                  00
+                  Normal transfer
+                  #00
+                
+                
+                  01
+                  Repeat transfer
+                  #01
+                
+                
+                  10
+                  Block transfer
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              DTS
+              Repeat Area Select
+              12
+              13
+              read-write
+              
+                
+                  00
+                  The destination is specified as the repeat area or block area.
+                  #00
+                
+                
+                  01
+                  The source is specified as the repeat area or block area.
+                  #01
+                
+                
+                  10
+                  The repeat area or block area is not specified.
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              SZ
+              Transfer Data Size Select
+              8
+              9
+              read-write
+              
+                
+                  00
+                  8 bits
+                  #00
+                
+                
+                  01
+                  16 bits
+                  #01
+                
+                
+                  10
+                  32 bits
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              DCTG
+              Transfer Request Source Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Software
+                  #00
+                
+                
+                  01
+                  Interrupts*1 from peripheral modules or external interrupt input pins
+                  #01
+                
+                
+                  10
+                  Setting prohibited
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          DMINT
+          DMA Interrupt Setting Register
+          0x13
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DTIE
+              Transfer End Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              ESIE
+              Transfer Escape End Interrupt Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              RPTIE
+              Repeat Size End Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              SARIE
+              Source Address Extended Repeat Area Overflow Interrupt Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              DARIE
+              Destination Address Extended Repeat Area Overflow Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DMAMD
+          DMA Address Mode Register
+          0x14
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              SM
+              Source Address Update Mode
+              14
+              15
+              read-write
+              
+                
+                  00
+                  Fixed address
+                  #00
+                
+                
+                  01
+                  Offset addition
+                  #01
+                
+                
+                  10
+                  Incremented address
+                  #10
+                
+                
+                  11
+                  Decremented address.
+                  #11
+                
+              
+            
+            
+              SARA
+              Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings.
+              8
+              12
+              read-write
+            
+            
+              DM
+              Destination Address Update Mode
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Fixed address
+                  #00
+                
+                
+                  01
+                  Offset addition
+                  #01
+                
+                
+                  10
+                  Incremented address
+                  #10
+                
+                
+                  11
+                  Decremented address.
+                  #11
+                
+              
+            
+            
+              DARA
+              Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          DMOFR
+          DMA Offset Register
+          0x18
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DMOFR
+              Specifies the offset when offset addition is selected as the address update mode for transfer source or destination.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          DMCNT
+          DMA Transfer Enable Register
+          0x1C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DTE
+              DMA Transfer Enable
+              0
+              0
+              read-write
+              modify
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          DMREQ
+          DMA Software Start Register
+          0x1D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CLRS
+              DMA Software Start Bit Auto Clear Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  SWREQ bit is cleared after DMA transfer is started by software.
+                  #0
+                
+                
+                  1
+                  SWREQ bit is not cleared after DMA transfer is started by software.
+                  #1
+                
+              
+            
+            
+              SWREQ
+              DMA Software Start
+              0
+              0
+              read-write
+              modify
+              
+                
+                  0
+                  DMA transfer is not requested.
+                  #0
+                
+                
+                  1
+                  DMA transfer is requested.
+                  #1
+                
+              
+            
+          
+        
+        
+          DMSTS
+          DMA Status Register
+          0x1E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ACT
+              DMA Active Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  DMAC operation suspended
+                  #0
+                
+                
+                  1
+                  DMAC operating.
+                  #1
+                
+              
+            
+            
+              DTIF
+              Transfer End Interrupt Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt
+                  #0
+                
+                
+                  1
+                  Interrupt occurred.
+                  #1
+                
+              
+            
+            
+              ESIF
+              Transfer Escape End Interrupt Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt
+                  #0
+                
+                
+                  1
+                  Interrupt occurred.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_DMAC1
+      0x40005040
+    
+    
+      R_DMAC2
+      0x40005080
+    
+    
+      R_DMAC3
+      0x400050C0
+    
+    
+      R_DMAC4
+      0x40005100
+    
+    
+      R_DMAC5
+      0x40005140
+    
+    
+      R_DMAC6
+      0x40005180
+    
+    
+      R_DMAC7
+      0x400051C0
+    
+    
+      R_DOC
+      Data Operation Circuit
+      0x40054100
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000002
+        0x004
+        registers
+      
+      
+        
+          DOCR
+          DOC Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DOPCFCL
+              DOPCF Clear
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Maintains the DOPCF flag state.
+                  #0
+                
+                
+                  1
+                  Clears the DOPCF flag.
+                  #1
+                
+              
+            
+            
+              DOPCF
+              Data Operation Circuit Flag
+              5
+              5
+              read-only
+            
+            
+              DCSEL
+              Detection Condition Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  DOPCF is set when data mismatch is detected.
+                  #0
+                
+                
+                  1
+                  DOPCF is set when data match is detected.
+                  #1
+                
+              
+            
+            
+              OMS
+              Operating Mode Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Data comparison mode
+                  #00
+                
+                
+                  01
+                  Data addition mode
+                  #01
+                
+                
+                  10
+                  Data subtraction mode
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          DODIR
+          DOC Data Input Register
+          0x02
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DODIR
+              16-bit read-write register in which 16-bit data for use in the operations are stored.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          DODSR
+          DOC Data Setting Register
+          0x04
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DODSR
+              This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes.
+              0
+              15
+              read-write
+            
+          
+        
+      
+    
+    
+      R_DRW
+      2D Drawing Engine
+      0x400E4000
+      
+        0x00000000
+        0x008
+        registers
+      
+      
+        0x00000010
+        0x050
+        registers
+      
+      
+        0x00000064
+        0x008
+        registers
+      
+      
+        0x00000074
+        0x010
+        registers
+      
+      
+        0x00000090
+        0x020
+        registers
+      
+      
+        0x000000B4
+        0x024
+        registers
+      
+      
+        0x000000DC
+        0x010
+        registers
+      
+      
+        
+          CONTROL
+          Geometry Control Register
+          0x00
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SPANSTORE
+              Nextline span start is always equal or left to current-line span start
+              23
+              23
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              SPANABORT
+              Shape is horizontally convex, only a single span per scanline
+              22
+              22
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              UNIONCD
+              Combine outputs C & D as union (output is final)
+              21
+              21
+              write-only
+              
+                
+                  0
+                  minimum/intersect
+                  #0
+                
+                
+                  1
+                  maximum/union
+                  #1
+                
+              
+            
+            
+              UNIONAB
+              Combine outputs A & B as union (output is called C)
+              20
+              20
+              write-only
+              
+                
+                  0
+                  minimum/intersect
+                  #0
+                
+                
+                  1
+                  maximum/union
+                  #1
+                
+              
+            
+            
+              UNION56
+              Combine limter 5 & 6 as union (output is called D)
+              19
+              19
+              write-only
+              
+                
+                  0
+                  minimum/intersect
+                  #0
+                
+                
+                  1
+                  maximum/union
+                  #1
+                
+              
+            
+            
+              UNION34
+              Combine limter 3 & 4 as union (output is called B)
+              18
+              18
+              write-only
+              
+                
+                  0
+                  minimum/intersect
+                  #0
+                
+                
+                  1
+                  maximum/union
+                  #1
+                
+              
+            
+            
+              UNION12
+              Combine limter 1 & 2 as union (output is called A)
+              17
+              17
+              write-only
+              
+                
+                  0
+                  minimum/intersect
+                  #0
+                
+                
+                  1
+                  maximum/union
+                  #1
+                
+              
+            
+            
+              BAND2ENABLE
+              Enable band postprocess for limiter 1 (see L1BAND)
+              16
+              16
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              BAND1ENABLE
+              Enable band postprocess for limiter 1 (see L1BAND)
+              15
+              15
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM6THRESHOLD
+              Enable limiter 6 threshold mode
+              14
+              14
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM5THRESHOLD
+              Enable limiter 5 threshold mode
+              13
+              13
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM4THRESHOLD
+              Enable limiter 4 threshold mode
+              12
+              12
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM3THRESHOLD
+              Enable limiter 3 threshold mode
+              11
+              11
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM2THRESHOLD
+              Enable limiter 2 threshold mode
+              10
+              10
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM1THRESHOLD
+              Enable limiter 1 threshold mode
+              9
+              9
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              QUAD3ENABLE
+              Enable quadratic coupling of limiters 5 and 6
+              8
+              8
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              QUAD2ENABLE
+              Enable quadratic coupling of limiters 3 and 4
+              7
+              7
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              QUAD1ENABLE
+              Enable quadratic coupling of limiters 1 and 2
+              6
+              6
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM6ENABLE
+              Enable limiter 6
+              5
+              5
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM5ENABLE
+              Enable limiter 5
+              4
+              4
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM4ENABLE
+              Enable limiter 4
+              3
+              3
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM3ENABLE
+              Enable limiter 3 
+              2
+              2
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM2ENABLE
+              Enable limiter 2 
+              1
+              1
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+            
+              LIM1ENABLE
+              Enable limiter 1 
+              0
+              0
+              write-only
+              
+                
+                  0
+                  disabled
+                  #0
+                
+                
+                  1
+                  enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          CONTROL2
+          Surface Control Register 
+          0x04
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RLEPIXELWIDTH
+              Texel width for RLE unit
+              30
+              31
+              write-only
+              
+                
+                  00
+                  1 byte per texel
+                  #00
+                
+                
+                  01
+                  2 byte per texel
+                  #01
+                
+                
+                  10
+                  3 byte per texel
+                  #10
+                
+                
+                  11
+                  4 byte per texel
+                  #11
+                
+              
+            
+            
+              BDIA
+              Blend destination factor inverted in alpha channel (USEACB = 1)
+              29
+              29
+              write-only
+              
+                
+                  0
+                  use blend factor as specified through BDFA
+                  #0
+                
+                
+                  1
+                  invert blend destination factor (1-x)
+                  #1
+                
+              
+            
+            
+              BSIA
+              Blend source factor inverted in alpha channel (USEACB = 1)
+              28
+              28
+              write-only
+              
+                
+                  0
+                  use blend factor as specified through BSFA
+                  #0
+                
+                
+                  1
+                  invert blend source factor (1-x)
+                  #1
+                
+              
+            
+            
+              CLUTFORMAT
+              Format of the CLUT
+              27
+              27
+              write-only
+              
+                
+                  0
+                  aRGB(8888)
+                  #0
+                
+                
+                  1
+                  RGB(565)
+                  #1
+                
+              
+            
+            
+              COLKEYENABLE
+              color keying enable
+              26
+              26
+              write-only
+              
+                
+                  0
+                  color keying disabled
+                  #0
+                
+                
+                  1
+                  color keying enabled
+                  #1
+                
+              
+            
+            
+              CLUTENABLE
+              CLUT enable
+              25
+              25
+              write-only
+              
+                
+                  0
+                  CLUT disabled
+                  #0
+                
+                
+                  1
+                  CLUT enabled
+                  #1
+                
+              
+            
+            
+              RLEENABLE
+              RLE enable
+              24
+              24
+              write-only
+              
+                
+                  0
+                  RLE disabled
+                  #0
+                
+                
+                  1
+                  RLE enabled
+                  #1
+                
+              
+            
+            
+              WRITEALPHA
+              Writeback alpha source for framebufferSet the 'alpha source' for the framebuffer(USEACB = 0)Blend alpha in color 2 instead of framebuffer alpha((USEACB = 1))In not alpha channel blending mode (USEACB = 0):Set the 'alpha source' for the framebuffer.In alpha channel blending mode (USEACB = 1):Blend alpha in color 2 instead of framebuffer alpha00B:  BC2A = 1: use alpha from framebuffer as destination (DST_A)else: BC2A = 0: use alpha in color 2 as destination (DST_A)
+              22
+              23
+              write-only
+              
+                
+                  00
+                  use alpha from color 2
+                  #00
+                
+                
+                  01
+                  use source alpha (pixel coverage)
+                  #01
+                
+                
+                  10
+                  use 0.0 as alpha
+                  #10
+                
+                
+                  11
+                  use alpha from framebuffer   
+                  #11
+                
+              
+            
+            
+              WRITEFORMAT10
+              Pixel format of the framebuffer
+              20
+              21
+              write-only
+              
+                
+                  00
+                  8bpp a(8)0
+                  #00
+                
+                
+                  01
+                  16bpp RGB(565) 
+                  #01
+                
+                
+                  10
+                  32bpp aRGB(8888)
+                  #10
+                
+                
+                  11
+                  16bpp aRGB(4444) 
+                  #11
+                
+              
+            
+            
+              READFORMAT10
+              Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance
+              18
+              19
+              write-only
+              
+                
+                  00
+                  8 bpp a(8) (READFORMAT32=00) / 16 bpp aRGB(1555)  (READFORMAT32=01) / 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance  (READFORMAT32=11)
+                  #00
+                
+                
+                  01
+                  16 bpp RGB(565)  (READFORMAT32=00) / 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color  (READFORMAT32=01) / 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance  (READFORMAT32=10) 
+                  #01
+                
+                
+                  10
+                  32 bpp aRGB(8888) (READFORMAT32=00)  / 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance (READFORMAT32=10) 
+                  #10
+                
+                
+                  11
+                  16 bpp aRGB(4444)  (READFORMAT32=00) / 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance  (READFORMAT32=10) 
+                  #11
+                
+              
+            
+            
+              TEXTUREFILTERY
+              Linear filtering on texture V axis
+              17
+              17
+              write-only
+              
+                
+                  0
+                  no filtering on texture V axis
+                  #0
+                
+                
+                  1
+                  linear filtering on texture V axis
+                  #1
+                
+              
+            
+            
+              TEXTUREFILTERX
+              Linear filtering on texture U axis
+              16
+              16
+              write-only
+              
+                
+                  0
+                  no filtering on texture U axis
+                  #0
+                
+                
+                  1
+                  linear filtering on texture U axis
+                  #1
+                
+              
+            
+            
+              TEXTURECLAMPY
+              Calculating V limiter outside use textureThe bit describes what happens if the V limiter (y direction in texture space) calculates a V value outside of the used texture
+              15
+              15
+              write-only
+              
+                
+                  0
+                  Texture wrap mode:    The integer part of the calculated value from the v limiter is anded with TEXVMASK. This results  in a  repetition of the texture in y/v direction.
+                  #0
+                
+                
+                  1
+                  Texture clamp mode:    The texture color at the border of the texture is taken. This results in a repetition of the texture  border  color in y/v direction.
+                  #1
+                
+              
+            
+            
+              TEXTURECLAMPX
+              Calculating U limiter outside use textureThe bit describes what happens if the U limiter (x direction in texture space) calculates a U value outside of the used texture
+              14
+              14
+              write-only
+              
+                
+                  0
+                  Texture wrap mode: The integer part of the calculated value from the u limiter is anded with      TEXUMASK. This results in a repetition of the texture in x/u direction.
+                  #0
+                
+                
+                  1
+                  Texture clamp mode: The texture color at the border of the texture is taken. This results in a     repetition of the texture border color in x/u direction.
+                  #1
+                
+              
+            
+            
+              BC2
+              Blend color 2 instead of framebuffer pixel
+              13
+              13
+              write-only
+              
+                
+                  0
+                  use pixel from framebuffer as destination (DST)
+                  #0
+                
+                
+                  1
+                  use color 2 as destination (DST)
+                  #1
+                
+              
+            
+            
+              BDI
+              Blend destination factor is inverteddst factor will be inverted (meaning 1-a or 1-1 depending on BDF)
+              12
+              12
+              write-only
+              
+                
+                  0
+                  use blend factor as specified through BDF
+                  #0
+                
+                
+                  1
+                  invert blend destinationfactor (1-x)
+                  #1
+                
+              
+            
+            
+              BSI
+              Blend source factor is invertedsrc factor will be inverted (meaning 1-a or 1-1 depending on BSF)
+              11
+              11
+              write-only
+              
+                
+                  0
+                  use blend factor as specified through BSF
+                  #0
+                
+                
+                  1
+                  invert blend source factor (1-x)
+                  #1
+                
+              
+            
+            
+              BDF
+              Blend destination factordst factor is alpha (factor is 1 per default)
+              10
+              10
+              write-only
+              
+                
+                  0
+                  use 1.0 as blend destination factor
+                  #0
+                
+                
+                  1
+                  use alpha as blend destination factor
+                  #1
+                
+              
+            
+            
+              BSF
+              Blend source factorsrc factor is alpha (factor is 1 per default)
+              9
+              9
+              write-only
+              
+                
+                  0
+                  use 1.0 as blend source factor
+                  #0
+                
+                
+                  1
+                  use alpha as blend source factor
+                  #1
+                
+              
+            
+            
+              WRITEFORMAT2
+              Bit 3 of framebuffer pixel formatSee WRITEFORMAT above description.
+              8
+              8
+              write-only
+            
+            
+              BDFA
+              Blend destinetion factor  for alpha channel in alpha channel blending mode (USEACB = 1)
+              7
+              7
+              write-only
+              
+                
+                  0
+                  use 1.0 as blend destination factor for alpha channel
+                  #0
+                
+                
+                  1
+                  use alpha as blend destination factor for alpha channel
+                  #1
+                
+              
+            
+            
+              BSFA
+              Blend source factor  for alpha channel in alpha channel blending mode (USEACB = 1)
+              6
+              6
+              write-only
+              
+                
+                  0
+                  use 1.0 as blend source factor for alpha channel
+                  #0
+                
+                
+                  1
+                  use alpha as blend source factor for alpha channel
+                  #1
+                
+              
+            
+            
+              READFORMAT32
+              Bit 4 and 3 of the texture buffer format.See READFORMAT above for description
+              4
+              5
+              write-only
+            
+            
+              USEACB
+              Alpha blend mode
+              3
+              3
+              write-only
+              
+                
+                  0
+                  use WRITEALPHA[1:0] mode
+                  #0
+                
+                
+                  1
+                  use full alpha channel blending mode
+                  #1
+                
+              
+            
+            
+              PATTERNSOURCEL5
+              Limiter 5 is used as pattern index instead of the default U limiter.Limiter 5 can be combined with limiter 6 to form a quadratic limiter which can be used to make quadratic pattern functions to draw radial patterns.
+              2
+              2
+              write-only
+            
+            
+              TEXTUREENABLE
+              Pixel source is read from texture and used as an alpha to blend between COLOR1 and COLOR2
+              1
+              1
+              write-only
+              
+                
+                  0
+                  disabled texture
+                  #0
+                
+                
+                  1
+                  enabled texture
+                  #1
+                
+              
+            
+            
+              PATTERNENABLE
+              Pixel source is a pattern color (blend of COLOR1 and COLOR2 depending on PATTERN and pattern index)
+              0
+              0
+              write-only
+              
+                
+                  0
+                  disabled pattern
+                  #0
+                
+                
+                  1
+                  enabled pattern
+                  #1
+                
+              
+            
+          
+        
+        
+          IRQCTL
+          Interrupt Control Register
+          0xC0
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BUSIRQCLR
+              Clear bus error interrupt BUSIRQ
+              5
+              5
+              write-only
+              
+                
+                  0
+                  no BUSIRQCLR clear
+                  #0
+                
+                
+                  1
+                  clear BUSIRQCLR
+                  #1
+                
+              
+            
+            
+              BUSIRQEN
+              BUSIRQ interrupt mask enable
+              4
+              4
+              write-only
+              
+                
+                  0
+                  disable (mask) BUSIRQ
+                  #0
+                
+                
+                  1
+                  enable (unmask) BUSIRQ
+                  #1
+                
+              
+            
+            
+              DLISTIRQCLR
+              Clear display list interrupt DLISTIRQ
+              3
+              3
+              write-only
+              
+                
+                  0
+                  no DLISTRQCLR clear
+                  #0
+                
+                
+                  1
+                  clear DLISTRQCLR
+                  #1
+                
+              
+            
+            
+              ENUMIRQCLR
+              Clear enumeration interrupt ENUMIRQ
+              2
+              2
+              write-only
+              
+                
+                  0
+                  no ENUMIRQCLR clear
+                  #0
+                
+                
+                  1
+                  clear ENUMIRQCLR
+                  #1
+                
+              
+            
+            
+              DLISTIRQEN
+              DLISTIRQ interrupt mask enable
+              1
+              1
+              write-only
+              
+                
+                  0
+                  disable (mask) DLISTIRQ
+                  #0
+                
+                
+                  1
+                  enable (unmask) DLISTIRQ
+                  #1
+                
+              
+            
+            
+              ENUMIRQEN
+              ENUMIRQ interrupt mask enable
+              0
+              0
+              write-only
+              
+                
+                  0
+                  disable (mask) ENUMIRQ
+                  #0
+                
+                
+                  1
+                  enable (unmask) ENUMIRQ
+                  #1
+                
+              
+            
+          
+        
+        
+          CACHECTL
+          Cache Control Register
+          0xC4
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CFLUSHTX
+              Flush texture cache
+              3
+              3
+              write-only
+              
+                
+                  0
+                  do not flush the texture cache
+                  #0
+                
+                
+                  1
+                  flush the texture cache
+                  #1
+                
+              
+            
+            
+              CENABLETX
+              Texture cache enable
+              2
+              2
+              write-only
+              
+                
+                  0
+                  disable the texture cache
+                  #0
+                
+                
+                  1
+                  enable the texture cache
+                  #1
+                
+              
+            
+            
+              CFLUSHFX
+              Flush framebuffer cache
+              1
+              1
+              write-only
+              
+                
+                  0
+                  do not flush the framebuffer cache
+                  #0
+                
+                
+                  1
+                  flush the framebuffer cache
+                  #1
+                
+              
+            
+            
+              CENABLEFX
+              Framebuffer cache enable
+              0
+              0
+              write-only
+              
+                
+                  0
+                  disable the framebuffer cache
+                  #0
+                
+                
+                  1
+                  enable the framebuffer cache
+                  #1
+                
+              
+            
+          
+        
+        
+          STATUS
+          Status Control Register
+          CONTROL
+          0x00
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BUSERRMDL
+              display list bus error interrupt triggered
+              10
+              10
+              read-only
+              
+                
+                  0
+                  no display list bus error occurred or interrupt disabled
+                  #0
+                
+                
+                  1
+                  display list bus error interrupt triggered
+                  #1
+                
+              
+            
+            
+              BUSERRMTXMRL
+              texture bus error interrupt triggered
+              9
+              9
+              read-only
+              
+                
+                  0
+                  no texture bus error occurred or interrupt disabled
+                  #0
+                
+                
+                  1
+                  texture bus error interrupt triggered
+                  #1
+                
+              
+            
+            
+              BUSERRMFB
+              framebuffer bus error interrupt triggered
+              8
+              8
+              read-only
+              
+                
+                  0
+                  no framebuffer bus error occured or interrupt disabled
+                  #0
+                
+                
+                  1
+                  framebuffer bus error interrupt triggered
+                  #1
+                
+              
+            
+            
+              BUSIRQ
+              bus error interrupt triggered
+              6
+              6
+              read-only
+              
+                
+                  0
+                  no bus error occurred or interrupt disabled
+                  #0
+                
+                
+                  1
+                  bus error interrupt triggered
+                  #1
+                
+              
+            
+            
+              DLISTIRQ
+              display list finished interrupt triggered
+              5
+              5
+              read-only
+              
+                
+                  0
+                  display list not finished or interrupt disabled
+                  #0
+                
+                
+                  1
+                  display list finished interrupt triggered
+                  #1
+                
+              
+            
+            
+              ENUMIRQ
+              enumeration finished interrupt triggered
+              4
+              4
+              read-only
+              
+                
+                  0
+                  enumeration not finished or interrupt disabled
+                  #0
+                
+                
+                  1
+                  enumeration finished interrupt triggered
+                  #1
+                
+              
+            
+            
+              DLISTACTIVE
+              Display list reader status
+              3
+              3
+              read-only
+              
+                
+                  0
+                  display list reader is idle
+                  #0
+                
+                
+                  1
+                  display list reader busy, no direct write access to registers allowed
+                  #1
+                
+              
+            
+            
+              CACHEDIRTY
+              Framebuffer cache status
+              2
+              2
+              read-only
+              
+                
+                  0
+                  framebuffer cache is not dirty
+                  #0
+                
+                
+                  1
+                  framebuffer cache is dirty, frame should not be flipped
+                  #1
+                
+              
+            
+            
+              BUSYWRITE
+              Framebuffer writeback status
+              1
+              1
+              read-only
+              
+                
+                  0
+                  framebuffer writeback finished
+                  #0
+                
+                
+                  1
+                  framebuffer writeback busy, framebuffer type can not be changed
+                  #1
+                
+              
+            
+            
+              BUSYENUM
+              Enumeration unit status
+              0
+              0
+              read-only
+              
+                
+                  0
+                  enumeration unit idle
+                  #0
+                
+                
+                  1
+                  enumeration unit busy, new primitive can not be started
+                  #1
+                
+              
+            
+          
+        
+        
+          HWREVISION
+          Hardware Version and Feature Set ID Register
+          CONTROL2
+          0x04
+          32
+          read-only
+          0x0FBE0107
+          0xFFFFFFFF
+          
+            
+              ACBLEND
+              Alpha channel blending feature 
+              27
+              27
+              read-only
+              
+                
+                  0
+                  Alpha channel blending unavailable
+                  #0
+                
+                
+                  1
+                  Alpha channel blending available
+                  #1
+                
+              
+            
+            
+              COLORKEY
+              Colorkey feature 
+              25
+              25
+              read-only
+              
+                
+                  0
+                  Colorkey unavailable
+                  #0
+                
+                
+                  1
+                  Colorkey available
+                  #1
+                
+              
+            
+            
+              TEXCLUT256
+              Texture CLUT feature 
+              24
+              24
+              read-only
+              
+                
+                  0
+                  Texture CLUT unavailable
+                  #0
+                
+                
+                  1
+                  Texture CLUT available
+                  #1
+                
+              
+            
+            
+              RLEUNIT
+              RLE unit feature 
+              23
+              23
+              read-only
+              
+                
+                  0
+                  RLE unit unavailable
+                  #0
+                
+                
+                  1
+                  RLE unit available
+                  #1
+                
+              
+            
+            
+              TEXCLU
+              Texture CLUT with 16 or 256 entries feature 
+              21
+              21
+              read-only
+              
+                
+                  0
+                  Texture CLUT with 16 or 256 entries unavailable
+                  #0
+                
+                
+                  1
+                  Texture CLUT with 16 or 256 entries available
+                  #1
+                
+              
+            
+            
+              PERFCOUNT
+              Two performance counter feature
+              20
+              20
+              read-only
+              
+                
+                  0
+                  Two performance counter unavailable
+                  #0
+                
+                
+                  1
+                  Two performance counter available
+                  #1
+                
+              
+            
+            
+              TXCACHE
+              Texture cache feature
+              19
+              19
+              read-only
+              
+                
+                  0
+                  Texture cache unavailable
+                  #0
+                
+                
+                  1
+                  Texture cache available
+                  #1
+                
+              
+            
+            
+              FBCACHE
+              Framebuffer cache feature
+              18
+              18
+              read-only
+              
+                
+                  0
+                  Framebuffer cache unavailable
+                  #0
+                
+                
+                  1
+                  Framebuffer cache available
+                  #1
+                
+              
+            
+            
+              DLR
+              Display list reader feature
+              17
+              17
+              read-only
+              
+                
+                  0
+                  Display list reader unavailable
+                  #0
+                
+                
+                  1
+                  Display list reader available
+                  #1
+                
+              
+            
+            
+              REV
+              Revision number
+              0
+              11
+              read-only
+            
+          
+        
+        
+          COLOR1
+          Base Color Register
+          0x64
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              COLOR1A
+              Alpha channel of color 1(0x00: transparent. . .  0xFF: opaque)
+              24
+              31
+              write-only
+            
+            
+              COLOR1R
+              Red channel of color 1
+              16
+              23
+              write-only
+            
+            
+              COLOR1G
+              Green channel of color 1
+              8
+              15
+              write-only
+            
+            
+              COLOR1B
+              Blue channel of color 1
+              0
+              7
+              write-only
+            
+          
+        
+        
+          COLOR2
+          Secondary Color Register
+          0x68
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              COLOR2A
+              Alpha channel of color 2(0x00: transparent. . .   0xFF: opaque)
+              24
+              31
+              write-only
+            
+            
+              COLOR2R
+              Red channel of color 2
+              16
+              23
+              write-only
+            
+            
+              COLOR2G
+              Green channel of color 2
+              8
+              15
+              write-only
+            
+            
+              COLOR2B
+              Blue channel of color 2
+              0
+              7
+              write-only
+            
+          
+        
+        
+          PATTERN
+          Pattern Register
+          0x74
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PATTERN
+              Bitmap of the pattern
+              0
+              7
+              write-only
+            
+          
+        
+        
+          6
+          0x4
+          1-6
+          L%sSTART
+          Limiter %s Start Value Register
+          0x10
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LSTART
+              Start value of the n'th limiter(n=1-6)
+              0
+              31
+              write-only
+            
+          
+        
+        
+          6
+          0x4
+          1-6
+          L%sXADD
+          Limiter %s X-Axis Increment Register
+          0x28
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LXADD
+              X-axis increment
+              0
+              31
+              write-only
+            
+          
+        
+        
+          6
+          0x4
+          1-6
+          L%sYADD
+          Limiter %s Y-Axis Increment Register
+          0x40
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LYADD
+              Y-axis increment
+              0
+              31
+              write-only
+            
+          
+        
+        
+          2
+          0x4
+          1,2
+          L%sBAND
+          Limiter %s Band Width Parameter Register
+          0x58
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LBAND
+              Limiter m band width parameter
+              0
+              31
+              write-only
+            
+          
+        
+        
+          TEXORIGIN
+          Texture Base Address Register 
+          0xBC
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TEXORIGIN
+              Texture base address
+              0
+              31
+              write-only
+            
+          
+        
+        
+          TEXPITCH
+          Texels Per Texture Line Register
+          0xB4
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TEXPITCH
+              Texels per texture linevalid range: 0 to 2048
+              0
+              31
+              write-only
+            
+          
+        
+        
+          TEXMASK
+          Texture Size or Texture Address Mask Register
+          0xB8
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TEXVMASK
+              V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = 0): texture_height must be a power of 2In texture clamping mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 are allowed.
+              11
+              31
+              write-only
+            
+            
+              TEXUMASK
+              U maskSet TEXUMASK[10:0] = texture_width -1In texture wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX = 1):all widths up to 2048 are allowed.
+              0
+              10
+              write-only
+            
+          
+        
+        
+          LUSTART
+          U Limiter Start Value Register 
+          0x90
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LUSTART
+              U limiter start value
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LUXADD
+          U Limiter X-Axis Increment Register
+          0x94
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LUXADD
+              U limiter x-axis increment
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LUYADD
+          U Limiter Y-Axis Increment Register
+          0x98
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LUYADD
+              U limiter y-axis increment
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LVSTARTI
+          V Limiter Start Value Integer Part Register
+          0x9C
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LVSTARTI
+              V limiter start value integer part
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LVSTARTF
+          V Limiter Start Value Fractional Part Register
+          0xA0
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LVSTARTF
+              V limiter start value fractional part
+              0
+              15
+              write-only
+            
+          
+        
+        
+          LVXADDI
+          V Limiter X-Axis Increment Integer Part Register
+          0xA4
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LVXADDI
+              V limiter x-axis increment integer part
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LVYADDI
+          V Limiter Y-Axis Increment Integer Part Register
+          0xA8
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LVYADDI
+              V limiter y-axis increment integer part
+              0
+              31
+              write-only
+            
+          
+        
+        
+          LVYXADDF
+          V Limiter Increment Fractional Parts Register
+          0xAC
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LVYADDF
+              V y limiter increment fractional part
+              16
+              31
+              write-only
+            
+            
+              LVXADDF
+              V xlimiter increment fractional part
+              0
+              15
+              write-only
+            
+          
+        
+        
+          TEXCLADDR
+          CLUT Start Address Register
+          0xDC
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CLADDR
+              Texture CLUT start address for indexed texture format
+              0
+              7
+              write-only
+            
+          
+        
+        
+          TEXCLDATA
+          CLUT Data Register
+          0xE0
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CLDATA
+              Texture CLUT data for Indexed texture format
+              0
+              31
+              write-only
+            
+          
+        
+        
+          TEXCLOFFSET
+          CLUT Offset Register
+          0xE4
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CLOFFSET
+              Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] is or'ed with the original index
+              0
+              7
+              write-only
+            
+          
+        
+        
+          COLKEY
+          Color Key Register
+          0xE8
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              COLKEYR
+              Red channel of color key
+              16
+              23
+              write-only
+            
+            
+              COLKEYG
+              Green channel of color key
+              8
+              15
+              write-only
+            
+            
+              COLKEYB
+              Blue channel of color key
+              0
+              7
+              write-only
+            
+          
+        
+        
+          SIZE
+          Bounding Box Dimension Register
+          0x78
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SIZEY
+              Height of the bounding box in pixelsvalid range: 0 to 1024
+              16
+              31
+              write-only
+            
+            
+              SIZEX
+               Width of the bounding box in pixelsvalid range: 0 to 1024
+              0
+              15
+              write-only
+            
+          
+        
+        
+          PITCH
+          Framebuffer Pitch And Spanstore Delay Register
+          0x7C
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SSD
+              Spanstore delay
+              16
+              31
+              write-only
+            
+            
+              PITCH
+              pitch of the framebuffer. A negative width can be used to render bottom-up instead of top-down
+              0
+              15
+              write-only
+            
+          
+        
+        
+          ORIGIN
+          Framebuffer Base Address Register
+          0x80
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ORIGIN
+              Address of the first pixel in framebuffer
+              0
+              31
+              write-only
+            
+          
+        
+        
+          DLISTSTART
+          Display List Start Address Register
+          0xC8
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DLISTSTART
+              Display list start address
+              0
+              31
+              write-only
+            
+          
+        
+        
+          PERFTRIGGER
+          Performance Counters Control Register
+          0xD4
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PERFTRIGGER2
+              Selects the internal event that will increment PERFCOUNT2 register
+              16
+              31
+              write-only
+              
+                
+                  0x00
+                  disable performance counter 
+                  0x00
+                
+                
+                  0x01
+                  2D Drawing Engine active cycles 
+                  0x01
+                
+                
+                  0x02
+                  framebuffer read access 
+                  0x02
+                
+                
+                  0x03
+                  framebuffer write access 
+                  0x03
+                
+                
+                  0x04
+                  texture read access 
+                  0x04
+                
+                
+                  0x05
+                  invisible pixels (enumerated but selected with alpha 0percent) 
+                  0x05
+                
+                
+                  0x06
+                  invisible pixels while internal FIFO is empty (lost cycles) 
+                  0x06
+                
+                
+                  0x07
+                  display list reader active cycles 
+                  0x07
+                
+                
+                  0x08
+                  framebuffer read hits
+                  0x08
+                
+                
+                  0x09
+                  framebuffer read misses
+                  0x09
+                
+                
+                  0x0A
+                  framebuffer write hits 
+                  0x0A
+                
+                
+                  0x0B
+                  framebuffer write misses 
+                  0x0B
+                
+                
+                  0x0C
+                  texture read hits 
+                  0x0C
+                
+                
+                  0x0D
+                  texture read misses 
+                  0x0D
+                
+                
+                  0x1F
+                  every clock cycle (for use as timer) 
+                  0x1F
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PERFTRIGGER1
+              Selects the internal event that will increment PERFCOUNT1 register.
+              0
+              15
+              write-only
+              
+                
+                  0x00
+                  disable performance counter 
+                  0x00
+                
+                
+                  0x01
+                  2D Drawing Engine active cycles 
+                  0x01
+                
+                
+                  0x02
+                  framebuffer read access 
+                  0x02
+                
+                
+                  0x03
+                  framebuffer write access 
+                  0x03
+                
+                
+                  0x04
+                  texture read access 
+                  0x04
+                
+                
+                  0x05
+                  invisible pixels (enumerated but selected with alpha 0percent) 
+                  0x05
+                
+                
+                  0x06
+                  invisible pixels while internal FIFO is empty (lost cycles) 
+                  0x06
+                
+                
+                  0x07
+                  display list reader active cycles 
+                  0x07
+                
+                
+                  0x08
+                  framebuffer read hits
+                  0x08
+                
+                
+                  0x09
+                  framebuffer read misses
+                  0x09
+                
+                
+                  0x0A
+                  framebuffer write hits 
+                  0x0A
+                
+                
+                  0x0B
+                  framebuffer write misses 
+                  0x0B
+                
+                
+                  0x0C
+                  texture read hits 
+                  0x0C
+                
+                
+                  0x0D
+                  texture read misses 
+                  0x0D
+                
+                
+                  0x1F
+                  every clock cycle (for use as timer) 
+                  0x1F
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          2
+          0x4
+          1,2
+          PERFCOUNT%s
+          Performance Counter %s
+          0xCC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PERFCOUNT
+              Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H.
+              0
+              31
+              read-write
+            
+          
+        
+      
+    
+    
+      R_DTC
+      Data Transfer Controller
+      0x40005400
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x04
+        registers
+      
+      
+        0x0000000C
+        0x01
+        registers
+      
+      
+        0x0000000E
+        0x02
+        registers
+      
+      
+        
+          DTCCR
+          DTC Control Register
+          0x00
+          8
+          read-write
+          0x08
+          0xFF
+          
+            
+              RRS
+              DTC Transfer Information Read Skip Enable.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Do not skip transfer information read
+                  #0
+                
+                
+                  1
+                  Skip transfer information read when vector numbers match
+                  #1
+                
+              
+            
+          
+        
+        
+          DTCVBR
+          DTC Vector Base Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DTCVBR
+              DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          DTCST
+          DTC Module Start Register
+          0x0C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DTCST
+              DTC Module Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  DTC module stop
+                  #0
+                
+                
+                  1
+                  DTC module start
+                  #1
+                
+              
+            
+          
+        
+        
+          DTCSTS
+          DTC Status Register
+          0x0E
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              ACT
+              DTC Active Flag
+              15
+              15
+              read-only
+              
+                
+                  0
+                  DTC transfer operation is not in progress.
+                  #0
+                
+                
+                  1
+                  DTC transfer operation is in progress.
+                  #1
+                
+              
+            
+            
+              VECN
+              DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1)
+              0
+              7
+              read-only
+            
+          
+        
+      
+    
+    
+      R_ELC
+      Event Link Controller
+      0x40041000
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000002
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000010
+        0x02
+        registers
+      
+      
+        0x00000014
+        0x02
+        registers
+      
+      
+        0x00000018
+        0x02
+        registers
+      
+      
+        0x0000001C
+        0x02
+        registers
+      
+      
+        0x00000020
+        0x02
+        registers
+      
+      
+        0x00000024
+        0x02
+        registers
+      
+      
+        0x00000028
+        0x02
+        registers
+      
+      
+        0x0000002C
+        0x02
+        registers
+      
+      
+        0x00000030
+        0x02
+        registers
+      
+      
+        0x00000034
+        0x02
+        registers
+      
+      
+        0x00000038
+        0x02
+        registers
+      
+      
+        0x0000003C
+        0x02
+        registers
+      
+      
+        0x00000040
+        0x02
+        registers
+      
+      
+        0x00000044
+        0x02
+        registers
+      
+      
+        0x00000048
+        0x02
+        registers
+      
+      
+        0x0000004C
+        0x02
+        registers
+      
+      
+        0x00000050
+        0x02
+        registers
+      
+      
+        0x00000054
+        0x02
+        registers
+      
+      
+        0x00000058
+        0x02
+        registers
+      
+      
+        0x0000005C
+        0x02
+        registers
+      
+      
+        0x00000060
+        0x02
+        registers
+      
+      
+        0x00000064
+        0x02
+        registers
+      
+      
+        0x00000068
+        0x02
+        registers
+      
+      
+        
+          2
+          0x2
+          ELSEGR[%s]
+          Event Link Software Event Generation Register
+          0x02
+          
+            BY
+            Event Link Software Event Generation Register
+            0x00
+            8
+            read-write
+            0x80
+            0xFF
+            
+              
+                WI
+                ELSEGR Register Write Disable
+                7
+                7
+                write-only
+                
+                  
+                    0
+                    Write to ELSEGR register is enabled.
+                    #0
+                  
+                  
+                    1
+                    Write to ELSEGR register is disabled.
+                    #1
+                  
+                
+              
+              
+                WE
+                SEG Bit Write Enable
+                6
+                6
+                read-write
+                
+                  
+                    0
+                    Write to SEG bit is disabled.
+                    #0
+                  
+                  
+                    1
+                    Write to SEG bit is enabled.
+                    #1
+                  
+                
+              
+              
+                SEG
+                Software Event Generation
+                0
+                0
+                write-only
+                
+                  
+                    0
+                    Normal operation
+                    #0
+                  
+                  
+                    1
+                    Software event is generated.
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          23
+          0x4
+          
+            
+              GPTA
+              GPTA
+              0
+            
+            
+              GPTB
+              GPTB
+              1
+            
+            
+              GPTC
+              GPTC
+              2
+            
+            
+              GPTD
+              GPTD
+              3
+            
+            
+              GPTE
+              GPTE
+              4
+            
+            
+              GPTF
+              GPTF
+              5
+            
+            
+              GPTG
+              GPTG
+              6
+            
+            
+              GPTH
+              GPTH
+              7
+            
+            
+              ADCA0
+              ADCA0
+              8
+            
+            
+              ADCB0
+              ADCB0
+              9
+            
+            
+              ADCA1
+              ADCA1
+              10
+            
+            
+              ADCB1
+              ADCB1
+              11
+            
+            
+              DA0
+              DA0
+              12
+            
+            
+              DA1
+              DA1
+              13
+            
+            
+              PORT1
+              PORT1
+              14
+            
+            
+              PORT2
+              PORT2
+              15
+            
+            
+              PORT3
+              PORT3
+              16
+            
+            
+              PORT4
+              PORT4
+              17
+            
+            
+              CTSU
+              CTSU
+              18
+            
+            
+              DA80
+              DA80
+              19
+            
+            
+              DA81
+              DA81
+              20
+            
+            
+              DA82
+              DA82
+              21
+            
+            
+              SDADC0
+              SDADC0
+              22
+            
+          
+          ELSR[%s]
+          Event Link Setting Register %s
+          0x10
+          
+            HA
+            Event Link Setting Register
+            0x00
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                ELS
+                Event Link Select
+                0
+                8
+                read-write
+                
+                  
+                    0x000
+                    Event output to the corresponding peripheral module is disabled.
+                    0x000
+                  
+                  
+                    others
+                    Set the number for the event signal to be linked.
+                    true
+                  
+                
+              
+            
+          
+        
+        
+          ELCR
+          Event Link Controller Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ELCON
+              All Event Link Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  ELC function is disabled.
+                  #0
+                
+                
+                  1
+                  ELC function is  enabled.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_ETHERC0
+      Ethernet MAC Controller
+      0x40064100
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        0x00000008
+        0x04
+        registers
+      
+      
+        0x00000010
+        0x04
+        registers
+      
+      
+        0x00000018
+        0x04
+        registers
+      
+      
+        0x00000020
+        0x04
+        registers
+      
+      
+        0x00000028
+        0x04
+        registers
+      
+      
+        0x00000040
+        0x04
+        registers
+      
+      
+        0x00000050
+        0x00C
+        registers
+      
+      
+        0x00000060
+        0x010
+        registers
+      
+      
+        0x000000C0
+        0x04
+        registers
+      
+      
+        0x000000C8
+        0x04
+        registers
+      
+      
+        0x000000D0
+        0x010
+        registers
+      
+      
+        0x000000E4
+        0x018
+        registers
+      
+      
+        
+          ECMR
+          ETHERC Mode Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TPC
+              PAUSE Frame Transmit
+              20
+              20
+              read-write
+              
+                
+                  0
+                  PAUSE frame is transmitted even during a PAUSE period.
+                  #0
+                
+                
+                  1
+                  PAUSE frame is not transmitted during a PAUSE period.
+                  #1
+                
+              
+            
+            
+              ZPF
+              0 Time PAUSE Frame Enable
+              19
+              19
+              read-write
+              
+                
+                  0
+                  PAUSE frame that contains the pause_time parameter of 0 is not used.
+                  #0
+                
+                
+                  1
+                  PAUSE frame that contains the pause_time parameter of 0 is used.
+                  #1
+                
+              
+            
+            
+              PFR
+              PAUSE Frame Receive Mode
+              18
+              18
+              read-write
+              
+                
+                  0
+                  PAUSE frame is not transferred to the EDMAC.
+                  #0
+                
+                
+                  1
+                  PAUSE frame is transferred to the EDMAC.
+                  #1
+                
+              
+            
+            
+              RXF
+              Receive Flow Control Operating Mode
+              17
+              17
+              read-write
+              
+                
+                  0
+                  PAUSE frame detection is disabled.
+                  #0
+                
+                
+                  1
+                  PAUSE frame detection is enabled.
+                  #1
+                
+              
+            
+            
+              TXF
+              Transmit Flow Control Operating Mode
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.)
+                  #0
+                
+                
+                  1
+                  Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.)
+                  #1
+                
+              
+            
+            
+              PRCEF
+              CRC Error Frame Receive Mode
+              12
+              12
+              read-write
+              
+                
+                  0
+                  EDMAC is notified of a CRC error.
+                  #0
+                
+                
+                  1
+                  EDMAC is not notified of a CRC error.
+                  #1
+                
+              
+            
+            
+              MPDE
+              Magic Packet Detection Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Magic Packet detection is disabled.
+                  #0
+                
+                
+                  1
+                  Magic Packet detection is enabled.
+                  #1
+                
+              
+            
+            
+              RE
+              Reception Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Receive function is disabled.
+                  #0
+                
+                
+                  1
+                  Receive function is enabled.
+                  #1
+                
+              
+            
+            
+              TE
+              Transmission Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Transmit function is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit function is enabled.
+                  #1
+                
+              
+            
+            
+              ILB
+              Internal Loopback Mode
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Normal data transmission or reception is performed.
+                  #0
+                
+                
+                  1
+                  Data is looped back in the ETHERC when full-duplex mode is selected.
+                  #1
+                
+              
+            
+            
+              RTM
+              Bit Rate
+              2
+              2
+              read-write
+              
+                
+                  0
+                  10 Mbps
+                  #0
+                
+                
+                  1
+                  100 Mbps
+                  #1
+                
+              
+            
+            
+              DM
+              Duplex Mode
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Half-duplex mode
+                  #0
+                
+                
+                  1
+                  Full-duplex mode
+                  #1
+                
+              
+            
+            
+              PRM
+              Promiscuous Mode
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Promiscuous mode is disabled.
+                  #0
+                
+                
+                  1
+                  Promiscuous mode is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          RFLR
+          Receive Frame Maximum Length Register
+          0x08
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RFL
+              Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes.
+              0
+              11
+              read-write
+            
+          
+        
+        
+          ECSR
+          ETHERC Status Register
+          0x10
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BFR
+              Continuous Broadcast Frame Reception Flag
+              5
+              5
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Continuous reception of broadcast frames has not been detected.
+                  #0
+                
+                
+                  1
+                  Continuous reception of broadcast frames has been detected.
+                  #1
+                
+              
+            
+            
+              PSRTO
+              PAUSE Frame Retransmit Over Flag
+              4
+              4
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  PAUSE frame retransmit count has not reached the upper limit.
+                  #0
+                
+                
+                  1
+                  PAUSE frame retransmit count has reached the upper limit.
+                  #1
+                
+              
+            
+            
+              LCHNG
+              LCHNG Link Signal Change Flag
+              2
+              2
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Change in the ETn_LINKSTA signal has not been detected.
+                  #0
+                
+                
+                  1
+                  Change in the ETn_LINKSTA signal has been detected (high to low, or low to high).
+                  #1
+                
+              
+            
+            
+              MPD
+              Magic Packet Detect Flag
+              1
+              1
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Magic Packet has not been detected.
+                  #0
+                
+                
+                  1
+                  Magic Packet has been detected.
+                  #1
+                
+              
+            
+            
+              ICD
+              False Carrier Detect Flag
+              0
+              0
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  PHY-LSI has not detected a false carrier on the line.
+                  #0
+                
+                
+                  1
+                  PHY-LSI has detected a false carrier on the line.
+                  #1
+                
+              
+            
+          
+        
+        
+          ECSIPR
+          ETHERC Interrupt Enable Register
+          0x18
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BFSIPR
+              Continuous Broadcast Frame Reception Interrupt Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Notification of continuous broadcast frame reception interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Notification of continuous broadcast frame reception interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              PSRTOIP
+              PAUSE Frame Retransmit Over Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Notification of PAUSE frame retransmit over interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Notification of PAUSE frame retransmit over interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              LCHNGIP
+              LINK Signal Change Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Notification of ETn_LINKSTA signal change interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Notification of ETn_LINKSTA signal change interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              MPDIP
+              Magic Packet Detect Interrupt Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Notification of the Magic Packet detect interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Notification of the Magic Packet detect interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              ICDIP
+              False Carrier Detect Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Notification of the false carrier detect interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Notification of the false carrier detect interrupt is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          PIR
+          PHY Interface Register
+          0x20
+          32
+          read-write
+          0x00000000
+          0xFFFFFFF7
+          
+            
+              MDI
+              MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0.
+              3
+              3
+              read-only
+            
+            
+              MDO
+              MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read).
+              2
+              2
+              read-write
+            
+            
+              MMD
+              MII/RMII Management Mode
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Read
+                  #0
+                
+                
+                  1
+                  Write
+                  #1
+                
+              
+            
+            
+              MDC
+              MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII.
+              0
+              0
+              read-write
+            
+          
+        
+        
+          PSR
+          PHY Status Register
+          0x28
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFE
+          
+            
+              LMON
+              ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI.
+              0
+              0
+              read-only
+            
+          
+        
+        
+          RDMLR
+          Random Number Generation Counter Upper Limit Setting Register
+          0x40
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RMD
+              Random Number Generation Counter
+              0
+              19
+              read-write
+              
+                
+                  00000h
+                  Normal operation
+                  0x00000
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          IPGR
+          IPG Register
+          0x50
+          32
+          read-write
+          0x00000014
+          0xFFFFFFFF
+          
+            
+              IPG
+              Interpacket Gap  Range:"16bit time(0x00)"-"140bit time(0x1F)" 
+              0
+              4
+              read-write
+              
+                
+                  14h
+                  96 bit time (initial value)
+                  0x14
+                
+                
+                  others
+                  (IPGx4+16) bit time
+                  true
+                
+              
+            
+          
+        
+        
+          APR
+          Automatic PAUSE Frame Register
+          0x54
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              AP
+              Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          MPR
+          Manual PAUSE Frame Register
+          0x58
+          32
+          write-only
+          0x00000000
+          0xFFFF0000
+          
+            
+              MP
+              Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined.
+              0
+              15
+              write-only
+            
+          
+        
+        
+          RFCF
+          Received PAUSE Frame Counter
+          0x60
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RPAUSE
+              Received PAUSE Frame CountNumber of received PAUSE frames
+              0
+              7
+              read-only
+            
+          
+        
+        
+          TPAUSER
+          PAUSE Frame Retransmit Count Setting Register
+          0x64
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TPAUSE
+              Automatic PAUSE Frame Retransmit Setting
+              0
+              15
+              read-write
+              
+                
+                  0x0000
+                  Number of retransmissions is unlimited
+                  0x0000
+                
+                
+                  others
+                  Maximum number of retransmissions is (TPAUSE)
+                  true
+                
+              
+            
+          
+        
+        
+          TPAUSECR
+          PAUSE Frame Retransmit Counter
+          0x68
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+        
+        
+          BCFRR
+          Broadcast Frame Receive Count Setting Register
+          0x6C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BCF
+              Broadcast Frame Continuous Receive Count Setting
+              0
+              15
+              read-write
+              
+                
+                  0000h
+                  Number of receptions is unlimited.
+                  0x0000
+                
+                
+                  others
+                  Receive (BFC) frame.
+                  true
+                
+              
+            
+          
+        
+        
+          MAHR
+          MAC Address Upper Bit Register
+          0xC0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MAHR
+              MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          MALR
+          MAC Address Lower Bit Register
+          0xC8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MALR
+              MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          TROCR
+          Transmit Retry Over Counter Register
+          0xD0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TROCR
+              Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          CDCR
+          Late Collision Detect Counter Register
+          0xD4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+        
+        
+          LCCR
+          Lost Carrier Counter Register
+          0xD8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCCR
+              Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          CNDCR
+          Carrier Not Detect Counter Register
+          0xDC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CNDCR
+              Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          CEFCR
+          CRC Error Frame Receive Counter Register
+          0xE4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CEFCR
+              CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          FRECR
+          Frame Receive Error Counter Register
+          0xE8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FRECR
+              Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          TSFRCR
+          Too-Short Frame Receive Counter Register
+          0xEC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TSFRCR
+              Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          TLFRCR
+          Too-Long Frame Receive Counter Register
+          0xF0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TLFRCR
+              Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          RFCR
+          Received Alignment Error Frame Counter Register
+          0xF4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RFCR
+              Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets).
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+        
+          MAFCR
+          Multicast Address Frame Receive Counter Register
+          0xF8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MAFCR
+              Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received.
+              0
+              31
+              read-write
+              clear
+            
+          
+        
+      
+    
+    
+      R_ETHERC_EDMAC
+      Ethernet DMA Controller
+      0x40064000
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        0x00000008
+        0x04
+        registers
+      
+      
+        0x00000010
+        0x04
+        registers
+      
+      
+        0x00000018
+        0x04
+        registers
+      
+      
+        0x00000020
+        0x04
+        registers
+      
+      
+        0x00000028
+        0x04
+        registers
+      
+      
+        0x00000030
+        0x04
+        registers
+      
+      
+        0x00000038
+        0x04
+        registers
+      
+      
+        0x00000040
+        0x04
+        registers
+      
+      
+        0x00000048
+        0x04
+        registers
+      
+      
+        0x00000050
+        0x04
+        registers
+      
+      
+        0x00000058
+        0x04
+        registers
+      
+      
+        0x00000064
+        0x010
+        registers
+      
+      
+        0x00000078
+        0x008
+        registers
+      
+      
+        0x000000C8
+        0x008
+        registers
+      
+      
+        0x000000D4
+        0x008
+        registers
+      
+      
+        
+          EDMR
+          EDMAC Mode Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DE
+              Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Big endian mode
+                  #0
+                
+                
+                  1
+                  Little endian mode
+                  #1
+                
+              
+            
+            
+              DL
+              Transmit/Receive DescriptorLength
+              4
+              5
+              read-write
+              
+                
+                  00
+                  16 bytes
+                  #00
+                
+                
+                  01
+                  32 bytes
+                  #01
+                
+                
+                  10
+                  64 bytes
+                  #10
+                
+                
+                  11
+                  16 bytes
+                  #11
+                
+              
+            
+            
+              SWR
+              Software Reset
+              0
+              0
+              write-only
+              
+                
+                  0
+                  no effect.
+                  #0
+                
+                
+                  1
+                  the corresponding channels of the EDMAC and ETHERC are reset.  Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset.
+                  #1
+                
+              
+            
+          
+        
+        
+          EDTRR
+          EDMAC Transmit Request Register
+          0x08
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TR
+              Transmit Request
+              0
+              0
+              write-only
+              
+                
+                  0
+                  no effect.
+                  #0
+                
+                
+                  1
+                  When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. 
+                  #1
+                
+              
+            
+          
+        
+        
+          EDRRR
+          EDMAC Receive Request Register
+          0x10
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RR
+              Receive Request
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Receive function is disabled.
+                  #0
+                
+                
+                  1
+                  Receive descriptor is read, and the receive function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          TDLAR
+          Transmit Descriptor List Start Address Register
+          0x18
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TDLAR
+              The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b
+              0
+              31
+              read-write
+            
+          
+        
+        
+          RDLAR
+          Receive Descriptor List Start Address Register
+          0x20
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDLAR
+              The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b
+              0
+              31
+              read-write
+            
+          
+        
+        
+          EESR
+          ETHERC/EDMAC Status Register
+          0x28
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TWB
+              Write-Back Complete Flag
+              30
+              30
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Write-back has not been completed, or no transmission has been requested.
+                  #0
+                
+                
+                  1
+                  Write-back to the transmit descriptor has been completed.
+                  #1
+                
+              
+            
+            
+              TABT
+              Transmit Abort Detect Flag
+              26
+              26
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Frame transmission has not been aborted or no transmission has been requested.
+                  #0
+                
+                
+                  1
+                  Frame transmission has been aborted.
+                  #1
+                
+              
+            
+            
+              RABT
+              Receive Abort Detect Flag
+              25
+              25
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Frame reception has not been aborted or no reception has been requested.
+                  #0
+                
+                
+                  1
+                  Frame reception has been aborted.
+                  #1
+                
+              
+            
+            
+              RFCOF
+              Receive Frame Counter Overflow Flag
+              24
+              24
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Receive frame counter has not overflowed.
+                  #0
+                
+                
+                  1
+                  Receive frame counter has overflowed.
+                  #1
+                
+              
+            
+            
+              ADE
+              Address Error Flag
+              23
+              23
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Invalid memory address has not been detected (normal operation).
+                  #0
+                
+                
+                  1
+                  Invalid memory address has been detected. 
+                  #1
+                
+              
+            
+            
+              ECI
+              ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared.
+              22
+              22
+              read-only
+              
+                
+                  0
+                  ETHERC status interrupt source has not been detected.
+                  #0
+                
+                
+                  1
+                  ETHERC status interrupt source has been detected.
+                  #1
+                
+              
+            
+            
+              TC
+              Frame Transfer Complete Flag
+              21
+              21
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Transfer have not been completed, or no transfer has been requested.
+                  #0
+                
+                
+                  1
+                  All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO.
+                  #1
+                
+              
+            
+            
+              TDE
+              Transmit Descriptor Empty Flag
+              20
+              20
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1.
+                  #0
+                
+                
+                  1
+                  The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0.
+                  #1
+                
+              
+            
+            
+              TFUF
+              Transmit FIFO Underflow Flag
+              19
+              19
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Underflow has not occurred.
+                  #0
+                
+                
+                  1
+                  Underflow has occurred.
+                  #1
+                
+              
+            
+            
+              FR
+              Frame Receive Flag
+              18
+              18
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Frame has not been received.
+                  #0
+                
+                
+                  1
+                  Frame has been received. Update of the receive descriptor is complete.
+                  #1
+                
+              
+            
+            
+              RDE
+              Receive Descriptor Empty Flag
+              17
+              17
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1.
+                  #0
+                
+                
+                  1
+                  The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0.
+                  #1
+                
+              
+            
+            
+              RFOF
+              Receive FIFO Overflow Flag
+              16
+              16
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Overflow has not occurred.
+                  #0
+                
+                
+                  1
+                  Overflow has occurred.
+                  #1
+                
+              
+            
+            
+              CND
+              Carrier Not Detect Flag
+              11
+              11
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A carrier has been detected when transmission starts.
+                  #0
+                
+                
+                  1
+                  A carrier has not been detected during preamble transmission.
+                  #1
+                
+              
+            
+            
+              DLC
+              Loss of Carrier Detect Flag
+              10
+              10
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Loss of carrier has not been detected.
+                  #0
+                
+                
+                  1
+                  Loss of carrier has been detected during frame transmission.
+                  #1
+                
+              
+            
+            
+              CD
+              Late Collision Detect Flag
+              9
+              9
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Late collision has not been detected.
+                  #0
+                
+                
+                  1
+                  Late collision has been detected during frame transmission.
+                  #1
+                
+              
+            
+            
+              TRO
+              Transmit Retry Over Flag
+              8
+              8
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Transmit retry-over condition has not been detected.
+                  #0
+                
+                
+                  1
+                  Transmit retry-over condition has been detected.
+                  #1
+                
+              
+            
+            
+              RMAF
+              Multicast Address Frame Receive Flag
+              7
+              7
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Multicast address frame has not been received.
+                  #0
+                
+                
+                  1
+                  Multicast address frame has been received.
+                  #1
+                
+              
+            
+            
+              RRF
+              Alignment Error Flag
+              4
+              4
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Alignment error has not been detected.
+                  #0
+                
+                
+                  1
+                  Alignment error has been detected.
+                  #1
+                
+              
+            
+            
+              RTLF
+              Frame-Too-Long Error Flag
+              3
+              3
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Frame-too-long error has not been detected.
+                  #0
+                
+                
+                  1
+                  Frame-too-long error has been detected.
+                  #1
+                
+              
+            
+            
+              RTSF
+              Frame-Too-Short Error Flag
+              2
+              2
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Frame-too-short error has not been detected.
+                  #0
+                
+                
+                  1
+                  Frame-too-short error has been detected.
+                  #1
+                
+              
+            
+            
+              PRE
+              PHY-LSI Receive Error Flag
+              1
+              1
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  PHY-LSI receive error has not been detected.
+                  #0
+                
+                
+                  1
+                  PHY-LSI receive error has been detected.
+                  #1
+                
+              
+            
+            
+              CERF
+              CRC Error Flag
+              0
+              0
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  CRC error has not been detected.
+                  #0
+                
+                
+                  1
+                  CRC error has been detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          EESIPR
+          ETHERC/EDMAC Status Interrupt Enable Register
+          0x30
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TWBIP
+              Write-Back Complete Interrupt Request Enable
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Write-back complete interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Write-back complete interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              TABTIP
+              Transmit Abort Detect Interrupt Request Enable
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Transmit abort detect interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit abort detect interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RABTIP
+              Receive Abort Detect Interrupt Request Enable
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Receive abort detect interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Receive abort detect interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RFCOFIP
+              Receive Frame Counter Overflow Interrupt Request Enable
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Receive frame counter overflow interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Receive frame counter overflow interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              ADEIP
+              Address Error Interrupt Request Enable
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Address error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Address error interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              ECIIP
+              ETHERC Status Register Source Interrupt Request Enable
+              22
+              22
+              read-write
+              
+                
+                  0
+                  ETHERC status interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  ETHERC status interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              TCIP
+              Frame Transfer Complete Interrupt Request Enable
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Frame transmission complete interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Frame transmission complete interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              TDEIP
+              Transmit Descriptor Empty Interrupt Request Enable
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Transmit descriptor empty interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit descriptor empty interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              TFUFIP
+              Transmit FIFO Underflow Interrupt Request Enable
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Underflow interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Underflow interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              FRIP
+              Frame Receive Interrupt Request Enable
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Frame reception interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Frame reception interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RDEIP
+              Receive Descriptor Empty Interrupt Request Enable
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Receive descriptor empty interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Receive descriptor empty interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RFOFIP
+              Receive FIFO Overflow Interrupt Request Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Overflow interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Overflow interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              CNDIP
+              Carrier Not Detect Interrupt Request Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Carrier not detect interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Carrier not detect interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              DLCIP
+              Loss of Carrier Detect Interrupt Request Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Loss of carrier detect interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Loss of carrier detect interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              CDIP
+              Late Collision Detect Interrupt Request Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Late collision detect interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Late collision detect interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              TROIP
+              Transmit Retry Over Interrupt Request Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Transmit retry over interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit retry over interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RMAFIP
+              Multicast Address Frame Receive Interrupt Request Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Multicast address frame receive interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Multicast address frame receive interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RRFIP
+              Alignment Error Interrupt Request Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Alignment error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Alignment error interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RTLFIP
+              Frame-Too-Long Error Interrupt Request Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Frame-too-long error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Frame-too-long error interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              RTSFIP
+              Frame-Too-Short Error Interrupt Request Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Frame-too-short error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  Frame-too-short error interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              PREIP
+              PHY-LSI Receive Error Interrupt Request Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  PHY-LSI receive error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  PHY-LSI receive error interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              CERFIP
+              CRC Error Interrupt Request Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  CRC error interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  CRC error interrupt request is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          TRSCER
+          ETHERC/EDMAC Transmit/Receive Status Copy Enable Register
+          0x38
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RMAFCE
+              RMAF Flag Copy Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor.
+                  #0
+                
+                
+                  1
+                  The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor.
+                  #1
+                
+              
+            
+            
+              RRFCE
+              RRF Flag Copy Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor.
+                  #0
+                
+                
+                  1
+                  The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor.
+                  #1
+                
+              
+            
+          
+        
+        
+          RMFCR
+          Missed-Frame Counter Register
+          0x40
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MFC
+              Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception.
+              0
+              15
+              read-write
+              clear
+            
+          
+        
+        
+          TFTR
+          Transmit FIFO Threshold Register
+          0x48
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TFT
+              Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4.  Example:     00Dh: 52 bytes     040h: 256 bytes     100h: 1024 bytes     200h: 2048 bytes
+              0
+              10
+              read-write
+              
+                
+                  0x000
+                  0x200
+                
+              
+              
+                
+                  0x000
+                  Store and forward mode
+                  0x000
+                
+                
+                  others
+                  The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited)
+                  true
+                
+              
+            
+          
+        
+        
+          FDR
+          Transmit FIFO Threshold Register
+          0x50
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TFD
+              Receive FIFO Depth
+              8
+              12
+              read-write
+              
+                
+                  01111
+                  4096 bytes
+                  #01111
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+            
+              RFD
+              Transmit FIFO Depth
+              0
+              4
+              read-write
+              
+                
+                  00111
+                  2048 bytes
+                  #00111
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          RMCR
+          Receive Method Control Register
+          0x58
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RNR
+              Receive Request Reset
+              0
+              0
+              read-write
+              
+                
+                  0
+                  EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received.
+                  #0
+                
+                
+                  1
+                  EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received.
+                  #1
+                
+              
+            
+          
+        
+        
+          TFUCR
+          Transmit FIFO Underflow Counter
+          0x64
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              UNDER
+              Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          RFOCR
+          Receive FIFO Overflow Counter
+          0x68
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              OVER
+              Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          IOSR
+          Independent Output Signal Setting Register
+          0x6C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ELB
+              External Loopback Mode
+              0
+              0
+              read-write
+              
+                
+                  0
+                  The ETn_EXOUT pin outputs low.
+                  #0
+                
+                
+                  1
+                  The ETn_EXOUT pin outputs high.
+                  #1
+                
+              
+            
+          
+        
+        
+          FCFTR
+          Flow Control Start FIFO Threshold Setting Register
+          0x70
+          32
+          read-write
+          0x00070007
+          0xFFFFFFFF
+          
+            
+              RFFO
+              Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.)
+              16
+              18
+              read-write
+              
+                
+                  000
+                  When 2 receive frames have been stored in the receive FIFO.
+                  #000
+                
+                
+                  001
+                  When 4 receive frames have been stored in the receive FIFO.
+                  #001
+                
+                
+                  010
+                  When 6 receive frames have been stored in the receive FIFO.
+                  #010
+                
+                
+                  011
+                  When 8 receive frames have been stored in the receive FIFO.
+                  #011
+                
+                
+                  100
+                  When 10 receive frames have been stored in the receive FIFO.
+                  #100
+                
+                
+                  101
+                  When 12 receive frames have been stored in the receive FIFO.
+                  #101
+                
+                
+                  110
+                  When 14 receive frames have been stored in the receive FIFO.
+                  #110
+                
+                
+                  111
+                  When 16 receive frames have been stored in the receive FIFO.
+                  #111
+                
+              
+            
+            
+              RFDO
+              Receive FIFO Data PAUSE Output Threshold(When  (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.)
+              0
+              2
+              read-write
+              
+                
+                  000
+                  When  224 ( 256 - 32) bytes of data is stored in the receive FIFO.
+                  #000
+                
+                
+                  001
+                  When  480 ( 512 - 32) bytes of data is stored in the receive FIFO.
+                  #001
+                
+                
+                  010
+                  When  736 ( 768 - 32) bytes of data is stored in the receive FIFO.
+                  #010
+                
+                
+                  011
+                  When  992 (1024 - 32) bytes of data is stored in the receive FIFO.
+                  #011
+                
+                
+                  100
+                  When 1248 (1280 - 32) bytes of data is stored in the receive FIFO.
+                  #100
+                
+                
+                  101
+                  When 1504 (1536 - 32) bytes of data is stored in the receive FIFO.
+                  #101
+                
+                
+                  110
+                  When 1760 (1792 - 32) bytes of data is stored in the receive FIFO.
+                  #110
+                
+                
+                  111
+                  When 2016 (2048 - 32) bytes of data is stored in the receive FIFO.
+                  #111
+                
+              
+            
+          
+        
+        
+          RPADIR
+          Receive Data Padding Insert Register
+          0x78
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PADS
+              Padding Size
+              16
+              17
+              read-write
+              
+                
+                  00
+                  No padding is inserted.
+                  #00
+                
+                
+                  01
+                  1 byte is inserted.
+                  #01
+                
+                
+                  10
+                  2 bytes are inserted.
+                  #10
+                
+                
+                  11
+                  3 bytes are inserted.
+                  #11
+                
+              
+            
+            
+              PADR
+              Padding Slot
+              0
+              5
+              read-write
+              
+                
+                  00h
+                  Padding is inserted at the head of received data.
+                  0x00
+                
+                
+                  others
+                  Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data.
+                  true
+                
+              
+            
+          
+        
+        
+          TRIMD
+          Transmit Interrupt Setting Register
+          0x07C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TIM
+              Transmit Interrupt Mode
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. 
+                  #0
+                
+                
+                  1
+                  Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed.
+                  #1
+                
+              
+            
+            
+              TIS
+              Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Transmit Interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit Interrupt is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          RBWAR
+          Receive Buffer Write Address Register
+          0xC8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RBWAR
+              Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          RDFAR
+          Receive Descriptor Fetch Address Register
+          0xCC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDFAR
+              Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          TBRAR
+          Transmit Buffer Read Address Register
+          0x0D4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TBRAR
+              Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          TDFAR
+          Transmit Descriptor Fetch Address Register
+          0xD8
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TDFAR
+              Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register.
+              0
+              31
+              read-only
+            
+          
+        
+      
+    
+    
+      R_ETHERC_EPTPC
+      Ethernet PTP Controller
+      0x40065800
+      
+        0x00000000
+        0x008
+        registers
+      
+      
+        0x00000010
+        0x010
+        registers
+      
+      
+        0x00000040
+        0x008
+        registers
+      
+      
+        0x00000050
+        0x01C
+        registers
+      
+      
+        0x00000080
+        0x04
+        registers
+      
+      
+        0x00000090
+        0x00C
+        registers
+      
+      
+        0x000000A0
+        0x00C
+        registers
+      
+      
+        0x000000C0
+        0x018
+        registers
+      
+      
+        0x000000E0
+        0x018
+        registers
+      
+      
+        0x00000100
+        0x014
+        registers
+      
+      
+        0x00000120
+        0x024
+        registers
+      
+      
+        0x00000160
+        0x018
+        registers
+      
+      
+        0x000001C0
+        0x018
+        registers
+      
+      
+        
+          2
+          0x8
+          F[%s]
+          Frame Reception Filter Setting Registers
+          0x160
+          
+            2
+            0x8
+            0-1
+            MACRU
+            Frame Reception Filter MAC Address Setting Registers
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                FMACRU
+                These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames.
+                0
+                23
+                read-write
+              
+            
+          
+          
+            2
+            0x8
+            0-1
+            MACRL
+            Frame Reception Filter MAC Address Setting Registers
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                FMACRL
+                These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames.
+                0
+                23
+                read-write
+              
+            
+          
+        
+        
+          SYSR
+          SYNFP Status Register
+          0x000
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GENDN
+              Generation Stop Completion Detection Flag
+              17
+              17
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Stopping generation has not been completed.
+                  #0
+                
+                
+                  1
+                  Stopping generation has been completed.
+                  #1
+                
+              
+            
+            
+              RESDN
+              Response Stop Completion Detection Flag
+              16
+              16
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  Stopping responses has not been completed.
+                  #0
+                
+                
+                  1
+                  Stopping responses has been completed.
+                  #1
+                
+              
+            
+            
+              INFABT
+              Control Information Abnormality Detection Flag
+              14
+              14
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No abnormality in control information
+                  #0
+                
+                
+                  1
+                  Abnormality in control information
+                  #1
+                
+              
+            
+            
+              RECLP
+              Loop Reception Detection Flag
+              12
+              12
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A received message has not returned through a loop.
+                  #0
+                
+                
+                  1
+                  A received message has returned through a loop.
+                  #1
+                
+              
+            
+            
+              DRQOVR
+              Delay_Req Reception FIFO Overflow Detection Flag
+              6
+              6
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The received Delay_Req has not caused the reception FIFO to overflow.
+                  #0
+                
+                
+                  1
+                  The received Delay_Req has caused the reception FIFO to overflow.
+                  #1
+                
+              
+            
+            
+              INTDEV
+              Receive logMessageInterval Value Out-of-Range Flag
+              5
+              5
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The received logMessageInterval value is within the range.
+                  #0
+                
+                
+                  1
+                  The received logMessageInterval value is out of the range.
+                  #1
+                
+              
+            
+            
+              DRPTO
+              Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag
+              4
+              4
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A Delay_Resp/Pdelay_Resp timeout has not occurred.
+                  #0
+                
+                
+                  1
+                  A Delay_Resp/Pdelay_Resp timeout has occurred.
+                  #1
+                
+              
+            
+            
+              MPDUD
+              meanPathDelay Value Update Flag
+              2
+              2
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The meanPathDelay value has not been updated.
+                  #0
+                
+                
+                  1
+                  The meanPathDelay value has been updated.
+                  #1
+                
+              
+            
+            
+              INTCHG
+              Receive logMessageInterval Value Change Detection Flag
+              1
+              1
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No change in the received logMessageInterval value.
+                  #0
+                
+                
+                  1
+                  A change in the received logMessageInterval value.
+                  #1
+                
+              
+            
+            
+              OFMUD
+              offsetFromMaster Value Update Flag
+              0
+              0
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  The offsetFromMaster value has not been updated.
+                  #0
+                
+                
+                  1
+                  The offsetFromMaster value has been updated.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYIPR
+          SYNFP Status Notification Permission Register
+          0x004
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GENDN
+              SYSR.GENDN Status Notification Permission
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.GENDN.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.GENDN.
+                  #1
+                
+              
+            
+            
+              RESDN
+              SYSR.RESDN Status Notification Permission
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.RESDN.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.RESDN.
+                  #1
+                
+              
+            
+            
+              INFABT
+              SYSR.INFABT Status Notification Permission
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.INFABT.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.INFABT.
+                  #1
+                
+              
+            
+            
+              RECLP
+              SYSR.RECLP Status Notification Permission
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.RECLP.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.RECLP.
+                  #1
+                
+              
+            
+            
+              DRQOVR
+              SYSR.DRQOVR Status Notification Permission
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.DRQOVR.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.DRQOVR.
+                  #1
+                
+              
+            
+            
+              INTDEV
+              SYSR.INTDEV Status Notification Permission
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.INTDEV.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.INTDEV.
+                  #1
+                
+              
+            
+            
+              DRPTO
+              SYSR.DRPTO Status Notification Permission
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.DRPTO.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.DRPTO.
+                  #1
+                
+              
+            
+            
+              MPDUD
+              SYSR.MPDUD Status Notification Permission
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.MPDUD.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.MPDUD.
+                  #1
+                
+              
+            
+            
+              INTCHG
+              SYSR.INTCHG Status Notification Permission
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.INTCHG.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.INTCHG.
+                  #1
+                
+              
+            
+            
+              OFMUD
+              SYSR.OFMUD Status Notification Permission
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of SYSR.OFMUD.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of SYSR.OFMUD.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYMACRU
+          SYNFP MAC Address Registers
+          0x010
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYMACRU
+              These bits hold the setting for the higher-order 24 bits of the local MAC address.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          SYMACRL
+          SYNFP MAC Address Registers
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYMACRL
+              These bits hold the setting for the lower-order 24 bits of the local MAC address.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          SYLLCCTLR
+          SYNFP LLC-CTL Value Register
+          0x018
+          32
+          read-write
+          0x00000003
+          0xFFFFFFFF
+          
+            
+              CTL
+              LLC-CTL FieldThese bits specify the value used for the control field in the LLC sublayer when generating IEEE802.3 frames.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SYIPADDRR
+          SYNFP Local IP Address Register
+          0x01C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYIPADDRR
+              These bits hold the setting for the local IP address.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYSPVRR
+          SYNFP Specification Version Setting Register
+          0x040
+          32
+          read-write
+          0x00000002
+          0xFFFFFFFF
+          
+            
+              TRSP
+              transportSpecific Field ValueThese bits are used to set the transportSpecific field value of the PTP v2 header.When a message is received, this value is compared with the transportSpecific field of the received frame.In generating messages, the value is used for the transportSpecific field of the frame for transmission.Set these bits to 0000b (IEEE 1588).
+              4
+              7
+              read-write
+            
+            
+              VER
+              versionPTP Field ValueThese bits are used to set the versionPTP field value of the PTP v2 header.When a message is received, this value is compared with the versionPTP field of the received frame.In generating messages, the value is used for the versionPTP field of the frame for transmission.Set these bits to 0010b (PTP v2).
+              0
+              3
+              read-write
+            
+          
+        
+        
+          SYDOMR
+          SYNFP Domain Number Setting Register
+          0x044
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DNUM
+              domainNumber Field Value SettingThese bits are used to set the domainNumber field value of the PTP v2 header.When a message is received, this value is compared with the domainNumber field of the received frame as a condition for PTP reception processing.In generating messages, the value is used for the domainNumber field of the frame for transmission.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          ANFR
+          Announce Message Flag Field Setting Register
+          0x050
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FLAG14
+              PTP profile Specific 2
+              14
+              14
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 2 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 2 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG13
+              PTP profile Specific 1
+              13
+              13
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 1 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 1 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG10
+              unicastFlag
+              10
+              10
+              read-write
+              
+                
+                  0
+                  unicastFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  unicastFlag is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG8
+              alternateMasterFlag
+              8
+              8
+              read-write
+              
+                
+                  0
+                  alternateMasterFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  alternateMasterFlag is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG5
+              frequencyTraceableThis bit is used to set the logical value of the frequencyTraceable member of timePropertiesDS.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  frequencyTraceable is set to FALSE.
+                  #0
+                
+                
+                  1
+                  frequencyTraceable is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG4
+              timeTraceableThis bit is used to set the logical value of the timeTraceable member of timePropertiesDS.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  timeTraceable is set to FALSE.
+                  #0
+                
+                
+                  1
+                  timeTraceable is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG3
+              ptpTimescaleThis bit is used to set the logical value of the ptpTimescale member of timePropertiesDS.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  ptpTimescale is set to FALSE.
+                  #0
+                
+                
+                  1
+                  ptpTimescale is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG2
+              currentUtcOffsetValidThis bit is used to set the logical value of the currentUtcOffsetValid member of timePropertiesDS.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  currentUtcOffsetValid is set to FALSE.
+                  #0
+                
+                
+                  1
+                  currentUtcOffsetValid is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG1
+              leap59This bit is used to set the logical value of the leap59 member of timePropertiesDS.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  leap59 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  leap59 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG0
+              leap61This bit is used to set the logical value of the leap61 member of timePropertiesDS.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  leap61 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  leap61 is set to TRUE.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYNFR
+          Sync Message Flag Field Setting Register
+          0x054
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FLAG14
+              PTP profile Specific 2
+              14
+              14
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 2 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 2 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG13
+              PTP profile Specific 1
+              13
+              13
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 1 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 1 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG10
+              unicastFlag
+              10
+              10
+              read-write
+              
+                
+                  0
+                  unicastFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  unicastFlag is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG9
+              twoStepFlag
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Set this bit to 0 (FALSE).
+                  #0
+                
+                
+                  1
+                  Setting prohibited
+                  #1
+                
+              
+            
+            
+              FLAG8
+              alternateMasterFlag
+              8
+              8
+              read-write
+              
+                
+                  0
+                  alternateMasterFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  alternateMasterFlag is set to TRUE.
+                  #1
+                
+              
+            
+          
+        
+        
+          DYRQFR
+          Delay_Req Message Flag Field Setting Register
+          0x058
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FLAG14
+              PTP profile Specific 2
+              14
+              14
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 2 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 2 is set to TRULE.
+                  #1
+                
+              
+            
+            
+              FLAG13
+              PTP profile Specific 1
+              13
+              13
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 1 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 1 is set to TRULE.
+                  #1
+                
+              
+            
+            
+              FLAG10
+              unicastFlag
+              10
+              10
+              read-write
+              
+                
+                  0
+                  unicastFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  unicastFlag is set to TRULE.
+                  #1
+                
+              
+            
+          
+        
+        
+          DYRPFR
+          Delay_Resp Message Flag Field Setting Register
+          0x05C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FLAG14
+              PTP profile Specific 2
+              14
+              14
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 2 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 2 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG13
+              PTP profile Specific 1
+              13
+              13
+              read-write
+              
+                
+                  0
+                  PTP profile Specific 1 is set to FALSE.
+                  #0
+                
+                
+                  1
+                  PTP profile Specific 1 is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG10
+              unicastFlag
+              10
+              10
+              read-write
+              
+                
+                  0
+                  unicastFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  unicastFlag is set to TRUE.
+                  #1
+                
+              
+            
+            
+              FLAG9
+              woStepFlag
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Set this bit to 0 (FALSE).
+                  #0
+                
+                
+                  1
+                  Setting prohibited
+                  #1
+                
+              
+            
+            
+              FLAG8
+              alternateMasterFlag
+              8
+              8
+              read-write
+              
+                
+                  0
+                  alternateMasterFlag is set to FALSE.
+                  #0
+                
+                
+                  1
+                  alternateMasterFlag is set to TRUE.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYCIDRU
+          SYNFP Local Clock ID Registers
+          0x060
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYCIDRU
+              These bits hold the setting for the higher-order 32 bits of the clock-ID of your port.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYCIDRL
+          SYNFP Local Clock ID Registers
+          0x064
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYCIDRL
+              These bits hold the setting for the lower-order 32 bits of the clock-ID of your port.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYPNUMR
+          SYNFP Local Port Number Register
+          0x068
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PNUM
+              Local Port Number SettingThese bits hold the setting for the port number of the local port.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          SYRVLDR
+          SYNFP Register Value Load Directive Register
+          0x080
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ANUP
+              Announce Message Generation Information Update
+              2
+              2
+              write-only
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages.
+                  #1
+                
+              
+            
+            
+              STUP
+              State Update
+              1
+              1
+              write-only
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages.
+                  #1
+                
+              
+            
+            
+              BMUP
+              BMC Update
+              0
+              0
+              write-only
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYRFL1R
+          SYNFP Reception Filter Register 1
+          0x090
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PDFUP2
+              Pdelay_Resp_Follow_Up Message Processing
+              30
+              30
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP does not process messages.
+                  #1
+                
+              
+            
+            
+              PDFUP1
+              Pdelay_Resp_Follow_Up Message Processing
+              29
+              29
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              PDFUP0
+              Pdelay_Resp_Follow_Up Message Processing
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              PDRP2
+              Pdelay_Resp Message Processing
+              26
+              26
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              PDRP1
+              Pdelay_Resp Message Processing
+              25
+              25
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              PDRP0
+              Pdelay_Resp Message Processing
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              PDRQ2
+              Pdelay_Req Message Processing
+              22
+              22
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              PDRQ1
+              Pdelay_Req Message Processing
+              21
+              21
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              PDRQ0
+              Pdelay_Req Message Processing
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              DRP2
+              Delay_Resp Message Processing
+              18
+              18
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              DRP1
+              Delay_Resp Message Processing
+              17
+              17
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              DRP0
+              Delay_Resp Message Processing
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              DRQ2
+              Delay_Req Message Processing
+              14
+              14
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              DRQ1
+              Delay_Req Message Processing
+              13
+              13
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              DRQ0
+              Delay_Req Message Processing
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              FUP2
+              Follow_Up Message Processing
+              10
+              10
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              FUP1
+              Follow_Up Message Processing
+              9
+              9
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              FUP0
+              Follow_Up Message Processing
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              SYNC2
+              Sync Message Processing
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The SYNFP does not process messages.
+                  #0
+                
+                
+                  1
+                  The SYNFP processes messages.
+                  #1
+                
+              
+            
+            
+              SYNC1
+              Sync Message Processing
+              5
+              5
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              SYNC0
+              Sync Message Processing
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              ANCE1
+              Announce Message Processing
+              1
+              1
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              ANCE0
+              Announce Message Processing
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYRFL2R
+          SYNFP Reception Filter Register 2
+          0x094
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ILL1
+              Illegal Message Processing Setting
+              29
+              29
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              ILL0
+              Illegal Message Processing Setting
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              SIG1
+              Signaling Message Processing Setting
+              5
+              5
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              SIG0
+              Signaling Message Processing Setting
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              MAN1
+              Management Message Processing Setting
+              1
+              1
+              read-write
+              
+                
+                  0
+                  The PRC-TC does not relay messages between ports 0 and 1.
+                  #0
+                
+                
+                  1
+                  The PRC-TC relays messages between ports 0 and 1.
+                  #1
+                
+              
+            
+            
+              MAN0
+              Management Message Processing Setting
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Messages are not transferred to the PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  Messages are transferred to the PTPEDMAC.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYTRENR
+          SYNFP Transmission Enable Register
+          0x098
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PDRQ
+              Pdelay_Req Message Transmission Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Pdelay_Req messages are not transmitted.
+                  #0
+                
+                
+                  1
+                  Pdelay_Req messages are transmitted.
+                  #1
+                
+              
+            
+            
+              DRQ
+              Delay_Req Message Transmission Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Delay_Req messages are not transmitted.
+                  #0
+                
+                
+                  1
+                  Delay_Req messages are transmitted.
+                  #1
+                
+              
+            
+            
+              SYNC
+              Sync Message Transmission Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Sync messages are not transmitted.
+                  #0
+                
+                
+                  1
+                  Sync messages are transmitted.
+                  #1
+                
+              
+            
+            
+              ANCE
+              Announce Message Transmission Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Announce messages are not transmitted.
+                  #0
+                
+                
+                  1
+                  Announce messages are transmitted.
+                  #1
+                
+              
+            
+          
+        
+        
+          MTCIDU
+          Master Clock ID Registers
+          0x0A0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MTCIDU
+              These bits hold the setting for the higher-order 32 bits of the clock-ID of the master clock.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          MTCIDL
+          Master Clock ID Registers
+          0x0A4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MTCIDL
+              These bits hold the setting for the lower-order 32 bits of the clock-ID of the master clock.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          MTPID
+          Master clock port number register
+          0x0A8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PNUM
+              Master Clock Port Number SettingThese bits hold the setting for the port number of the master clock.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          SYTLIR
+          SYNFP Transmission Interval Setting Register
+          0x0C0
+          32
+          read-write
+          0x00000001
+          0xFFFFFFFF
+          
+            
+              DREQ
+              Delay_Req Transmission Interval Average Value/ Pdelay_Req Transmission Interval SettingThe bits set the average interval for the transmission of Delay_Req messages and the interval for the transmission of Pdelay_Req messages.The setting is also placed in the logMessageInterval field of Delay_Resp messages.
+              16
+              23
+              read-write
+            
+            
+              SYNC
+              Sync Message Transmission Interval SettingThese bits set the interval for the transmission of Sync messages. The setting is also placed in the logMessageInterval field of transmitted Sync messages.
+              8
+              15
+              read-write
+            
+            
+              ANCE
+              Announce Message Transmission Interval SettingThese bits set the interval for the transmission of Announce messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SYRLIR
+          SYNFP Received logMessageInterval Value Indication Register
+          0x0C4
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DRESP
+              Delay_Resp Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Delay_Resp message.
+              16
+              23
+              read-only
+            
+            
+              SYNC
+              Sync Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Sync message.
+              8
+              15
+              read-only
+            
+            
+              ANCE
+              Announce Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Announce message.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          OFMRU
+          offsetFromMaster Value Registers
+          0x0C8
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              OFMRU
+              These bits indicate the higher-order 32 bits of the calculated offsetFromMaster value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          OFMRL
+          offsetFromMaster Value Registers
+          0x0CC
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              OFMRL
+              These bits indicate the lower-order 32 bits of the calculated offsetFromMaster value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          MPDRU
+          meanPathDelay Value Registers
+          0x0D0
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MPDRU
+              These bits indicate the higher-order 32 bits of the calculated meanPathDelay value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          MPDRL
+          meanPathDelay Value Registers
+          0x0D4
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MPDRL
+              These bits indicate the lower-order 32 bits of the calculated meanPathDelay value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          GMPR
+          grandmasterPriority Field Setting Register
+          0x0E0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GMPR1
+              grandmasterPriority1 Field Value SettingThese bits are used to set the value of the grandmasterPriority1 fields of Announce messages.
+              16
+              23
+              read-write
+            
+            
+              GMPR2
+              grandmasterPriority2 Field Value SettingThese bits are used to set the value of the grandmasterPriority2 fields of Announce messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          GMCQR
+          grandmasterClockQuality Field Setting Register
+          0x0E4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GMCQR
+              These bits are used to set the value of the grandmasterClockQuality fields of Announce messages. The correspondence between bits and the grandmasterClockQuality fields is as listed below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 to b0: offsetScaledLogVariance
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GMIDRU
+          grandmasterIdentity Field Setting Registers
+          0x0E8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GMIDRU
+              These bits hold the setting for the higher-order 32 bits of the value of the grandmasterIdentity fields of Announce messages.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GMIDRL
+          grandmasterIdentity Field Setting Registers
+          0x0EC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GMIDRL
+              These bits hold the setting for the lower-order 32 bits of the value of the grandmasterIdentity fields of Announce messages.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          CUOTSR
+          currentUtcOffset/timeSource Field Setting Register
+          0x0F0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CUTO
+              currentUtcOffset Field SettingThese bits set the value of the currentUtcOffset fields of Announce messages.
+              16
+              31
+              read-write
+            
+            
+              TSRC
+              timeSource Field SettingThese bits set the value of the timeSource fields of Announce messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SRR
+          stepsRemoved Field Setting Register
+          0x0F4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SRMV
+              stepsRemoved Field Value SettingThese bits set the value of the stepsRemoved fields of Announce messages.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          PPMACRU
+          PTP-primary Message Destination MAC Address Setting Registers
+          0x100
+          32
+          read-write
+          0x00011B19
+          0xFFFFFFFF
+          
+            
+              PPMACRU
+              These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-primary messages.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          PPMACRL
+          PTP-primary Message Destination MAC Address Setting Registers
+          0x104
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PPMACRL
+              These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-primary messages.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          PDMACRU
+          PTP-pdelay Message MAC Address Setting Registers
+          0x108
+          32
+          read-write
+          0x000180C2
+          0xFFFFFFFF
+          
+            
+              PDMACRU
+              These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-pdelay messages.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          PDMACRL
+          PTP-pdelay Message MAC Address Setting Registers
+          0x10C
+          32
+          read-write
+          0x0000000E
+          0xFFFFFFFF
+          
+            
+              PDMACRL
+              These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          PETYPER
+          PTP Message EtherType Setting Register
+          0x110
+          32
+          read-write
+          0x000088F7
+          0xFFFFFFFF
+          
+            
+              TYPE
+              PTP Message EtherType Value SettingThese bits hold the setting for the EtherType field value for frames in the Ethernet II format.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          PPIPR
+          PTP-primary Message Destination IP Address Setting Register
+          0x120
+          32
+          read-write
+          0xE0000181
+          0xFFFFFFFF
+          
+            
+              PPIPR
+              These bits hold the setting for the destination IP address for PTPprimary messages.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          PDIPR
+          PTP-pdelay Message Destination IP Address Setting Register
+          0x124
+          32
+          read-write
+          0xE000006B
+          0xFFFFFFFF
+          
+            
+              PDIPR
+              These bits hold the setting for the destination IP address for PTPpdelay messages.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          PETOSR
+          PTP Event Message TOS Setting Register
+          0x128
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EVTO
+              PTP Event Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP event messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          PGTOSR
+          PTP general Message TOS Setting Register
+          0x12C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GETO
+              PTP general Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP general messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          PPTTLR
+          PTP-primary Message TTL Setting Register
+          0x130
+          32
+          read-write
+          0x00000080
+          0xFFFFFFFF
+          
+            
+              PRTL
+              PTP-primary Message TTL Field Value SettingThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-primary messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          PDTTLR
+          PTP-pdelay Message TTL Setting Register
+          0x134
+          32
+          read-write
+          0x00000001
+          0xFFFFFFFF
+          
+            
+              PDTL
+              PTP-pdelay Message TTL Field ValueThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-pdelay messages.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          PEUDPR
+          PTP Event Message UDP Destination Port Number Setting Register
+          0x138
+          32
+          read-write
+          0x0000013F
+          0xFFFFFFFF
+          
+            
+              EVUPT
+              PTP Event Message Destination Port Number SettingThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP event messages.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          PGUDPR
+          PTP general Message UDP Destination Port Number Setting Register
+          0x13C
+          32
+          read-write
+          0x00000140
+          0xFFFFFFFF
+          
+            
+              GEUPT
+              PTP general Message Destination Port NumberThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP general messages.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          FFLTR
+          Frame Reception Filter Setting Register
+          0x140
+          32
+          read-write
+          0x00010000
+          0xFFFFFFFF
+          
+            
+              EXTPRM
+              Extended Promiscuous ModeSetting
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Normal operation (unicast frames addressed to the EPTPC are received, filtering of PTP frames is applied, multicast filtering is applied, and all broadcast frames are received).
+                  #0
+                
+                
+                  1
+                  Extended promiscuous mode (all frames are received)
+                  #1
+                
+              
+            
+            
+              ENB
+              Reception Filter EnableNOTE: The setting of these bits is only effective when EXTPRM=0.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Filtering is disabled (all multicast frames are received).
+                  #0
+                
+                
+                  1
+                  See PRT and SEL bit.
+                  #1
+                
+              
+            
+            
+              PRT
+              Frame Reception EnableNOTE: The setting of these bits is only effective when EXTPRM=0 and ENB=1.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Do not receive multicast frames.
+                  #0
+                
+                
+                  1
+                  See SEL bit.
+                  #1
+                
+              
+            
+            
+              SEL
+              Receive MAC Address SelectNOTE: The setting of these bits is only effective when EXTPRM=0, ENB=1and RPT=1.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Only receive multicast frames matching the MAC address setting in FMAC0R(U/L).
+                  #0
+                
+                
+                  1
+                  Only receive multicast frames matching the MAC address setting in FMAC1R(U/L).
+                  #1
+                
+              
+            
+          
+        
+        
+          DASYMRU
+          Asymmetric Delay Setting Registers
+          0x1C0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DASYMRU
+              These bits hold the setting for the higher-order 16 bits of the asymmetric delay value.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          DASYMRL
+          Asymmetric Delay Setting Registers
+          0x1C4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DASYMRL
+              These bits hold the setting for the lower-order 32 bits of the asymmetric delay value.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          TSLATR
+          Timestamp Latency Setting Register
+          0x1C8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              INGP
+              Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports.
+              16
+              31
+              read-write
+            
+            
+              EGP
+              Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          SYCONFR
+          SYNFP Operation Setting Register
+          0x1CC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TCMOD
+              TC Mode Setting
+              20
+              20
+              read-write
+              
+                
+                  0
+                  E2E TC
+                  #0
+                
+                
+                  1
+                  P2P TC
+                  #1
+                
+              
+            
+            
+              FILDIS
+              Receive Message domainNumber Filter Disable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Filtering conditions for the reception of PTP messages include comparison with the domainNumber field.
+                  #0
+                
+                
+                  1
+                  Filtering conditions for the reception of PTP messages do not include comparison with the domainNumber field.
+                  #1
+                
+              
+            
+            
+              SBDIS
+              Sync Message Transmission Bandwidth Securing Disable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Securing of the bandwidth for the transmission of SYNC messages is enabled (transfer by the EDMAC is given lower priority).
+                  #0
+                
+                
+                  1
+                  Securing of the bandwidth for the transmission of SYNC messages is disabled (transfer by the EDMAC is given higher priority).
+                  #1
+                
+              
+            
+            
+              TCYC
+              PTP Message Transmission Interval SettingThese bits are used to set the time from the completion of one transmission to the start of the next in cycles of the transmission clock. A value n in these bits means that a transmission interval of n cycles will be secured.No interval is secured if the setting is 00h.We recommend the setting 28h (40 cycles).
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SYFORMR
+          SYNFP Frame Format Setting Register
+          0x1D0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FORM1
+              Ethernet Frame Format Setting
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Set this bit to 0 (Ethernet II frame format).
+                  #0
+                
+                
+                  1
+                  Setting prohibited
+                  #1
+                
+              
+            
+            
+              FORM0
+              Ethernet/UDP Encapsulation
+              0
+              0
+              read-write
+              
+                
+                  0
+                  PTP directly over Ethernet
+                  #0
+                
+                
+                  1
+                  PTP over UDP/IPv4
+                  #1
+                
+              
+            
+          
+        
+        
+          RSTOUTR
+          Response Message Reception Timeout Register
+          0x1D4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RSTOUTR
+              Response Message Reception Timeout Time SettingA response message not being received within n x 1024 (ns), where n is the setting, is judged to represent a timeout.
+              0
+              31
+              read-write
+            
+          
+        
+      
+    
+    
+      R_ETHERC_EPTPC1
+      0x40065C00
+    
+    
+      R_ETHERC_EPTPC_CFG
+      Ethernet PTP Configuration
+      0x40064500
+      
+        0x00000000
+        0x00C
+        registers
+      
+      
+        
+          PTRSTR
+          EPTPC Reset Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RESET
+              EPTPC Software Reset
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not reset the EPTPC
+                  #0
+                
+                
+                  1
+                  Reset the EPTPC. Do not access the EPTPC-related registers other than this register while a software reset is being issued.
+                  #1
+                
+              
+            
+          
+        
+        
+          STCSELR
+          STCA Clock Select Register
+          0x04
+          32
+          read-write
+          0x00000006
+          0xFFFFFFFF
+          
+            
+              SCLKSEL
+              STCA Clock Select
+              8
+              10
+              read-write
+              
+                
+                  000
+                  PCLKA clock divided by 1 to 6
+                  #000
+                
+                
+                  010
+                  Input clock from the REF50CK0 pin
+                  #010
+                
+                
+                  011
+                  Input clock from the REF50CK1 pin
+                  #011
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+            
+              SCLKDIV
+              PCLKA Clock Frequency Division
+              0
+              2
+              read-write
+              
+                
+                  001
+                  1
+                  #001
+                
+                
+                  010
+                  1/2
+                  #010
+                
+                
+                  011
+                  1/3
+                  #011
+                
+                
+                  100
+                  1/4
+                  #100
+                
+                
+                  101
+                  1/5
+                  #101
+                
+                
+                  110
+                  1/6
+                  #110
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          BYPASS
+          Bypass 1588 module Register
+          0x08
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BYPASS1
+              Bypass 1588 module for Ether 1ch
+              16
+              16
+              read-write
+              
+                
+                  0
+                  to use 1588 module for Ether 1ch
+                  #0
+                
+                
+                  1
+                  to bypass 1588 module for Ether 1ch
+                  #1
+                
+              
+            
+            
+              BYPASS0
+              Bypass 1588 module for Ether 0ch 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  to use 1588 module for Ether 0ch
+                  #0
+                
+                
+                  1
+                  to bypass 1588 module for Ether 0ch
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_ETHERC_EPTPC_COMMON
+      Ethernet PTP Controller Common
+      0x40065000
+      
+        0x00000000
+        0x008
+        registers
+      
+      
+        0x00000010
+        0x008
+        registers
+      
+      
+        0x00000040
+        0x008
+        registers
+      
+      
+        0x00000050
+        0x00C
+        registers
+      
+      
+        0x00000060
+        0x010
+        registers
+      
+      
+        0x00000080
+        0x008
+        registers
+      
+      
+        0x00000090
+        0x010
+        registers
+      
+      
+        0x000000B0
+        0x00C
+        registers
+      
+      
+        0x00000124
+        0x020
+        registers
+      
+      
+        0x00000170
+        0x00C
+        registers
+      
+      
+        0x00000210
+        0x00C
+        registers
+      
+      
+        0x000002D0
+        0x00C
+        registers
+      
+      
+        0x00000300
+        0x060
+        registers
+      
+      
+        0x0000037C
+        0x04
+        registers
+      
+      
+        0x00000400
+        0x008
+        registers
+      
+      
+        0x00000410
+        0x014
+        registers
+      
+      
+        0x00000430
+        0x008
+        registers
+      
+      
+        
+          6
+          0x10
+          TM[%s]
+          Timer Setting Registers
+          0x300
+          
+            STTRU
+            Timer Start Time Setting Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                TMSTTRU
+                These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds.
+                0
+                31
+                read-write
+              
+            
+          
+          
+            STTRL
+            Timer Start Time Setting Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                TMSTTRL
+                These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds.
+                0
+                31
+                read-write
+              
+            
+          
+          
+            CYCR
+            Timer Cycle Setting Registers
+            0x08
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                TMCYCR
+                These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock.
+                0
+                29
+                read-write
+              
+            
+          
+          
+            PLSR
+            Timer Pulse Width Setting Register
+            0x0C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                TMPLSR
+                These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock.
+                0
+                28
+                read-write
+              
+            
+          
+        
+        
+          2
+          0x8
+          PR[%s]
+          Local MAC Address Registers
+          0x410
+          
+            MACRU
+            Channel Local MAC Address Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                PRMACRU
+                These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
+                0
+                23
+                read-write
+              
+            
+          
+          
+            MACRL
+            Channel Local MAC Address Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                PRMACRL
+                These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0.
+                0
+                23
+                read-write
+              
+            
+          
+        
+        
+          MIESR
+          MINT Interrupt Source Status Register
+          0x000
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CYC5
+              Pulse Output Timer 5 Rising Edge Detection Flag
+              21
+              21
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 5 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 5 is detected.
+                  #1
+                
+              
+            
+            
+              CYC4
+              Pulse Output Timer 4 Rising Edge Detection Flag
+              20
+              20
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 4 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 4 is detected.
+                  #1
+                
+              
+            
+            
+              CYC3
+              Pulse Output Timer 3 Rising Edge Detection Flag
+              19
+              19
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 3 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 3 is detected.
+                  #1
+                
+              
+            
+            
+              CYC2
+              Pulse Output Timer 2 Rising Edge Detection Flag
+              18
+              18
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 2 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 2 is detected.
+                  #1
+                
+              
+            
+            
+              CYC1
+              Pulse Output Timer 1 Rising Edge Detection Flag
+              17
+              17
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 1 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 1 is detected.
+                  #1
+                
+              
+            
+            
+              CYC0
+              Pulse Output Timer 0 Rising Edge Detection Flag
+              16
+              16
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A rising edge in the periodic pulse signal from pulse output timer 0 is not detected.
+                  #0
+                
+                
+                  1
+                  A rising edge in the periodic pulse signal from pulse output timer 0 is detected.
+                  #1
+                
+              
+            
+            
+              PRC
+              PRC-TC Status Flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  No change in the state of the PRC-TC module
+                  #0
+                
+                
+                  1
+                  A change in the state of the PRC-TC module
+                  #1
+                
+              
+            
+            
+              SY1
+              SYNFP1 Status Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  No change in the state of the SYNFP1 module
+                  #0
+                
+                
+                  1
+                  A change in the state of the SYNFP1 module
+                  #1
+                
+              
+            
+            
+              SY0
+              SYNFP0 Status Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  No change in the state of the SYNFP0 module
+                  #0
+                
+                
+                  1
+                  A change in the state of the SYNFP0 module
+                  #1
+                
+              
+            
+            
+              ST
+              STCA Status Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  No change in the state of the STCA module
+                  #0
+                
+                
+                  1
+                  A change in the state of the STCA module
+                  #1
+                
+              
+            
+          
+        
+        
+          MIEIPR
+          MINT Interrupt Request Permission Register
+          0x004
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CYC5
+              Pulse Output Timer 5 Rising Edge Detection Interrupt Request Permission
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5.
+                  #1
+                
+              
+            
+            
+              CYC4
+              Pulse Output Timer 4 Rising Edge Detection Interrupt Request Permission
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4.
+                  #1
+                
+              
+            
+            
+              CYC3
+              Pulse Output Timer 3 Rising Edge Detection Interrupt Request Permission
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3.
+                  #1
+                
+              
+            
+            
+              CYC2
+              Pulse Output Timer 2 Rising Edge Detection Interrupt Request Permission
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2.
+                  #1
+                
+              
+            
+            
+              CYC1
+              Pulse Output Timer 1 Rising Edge Detection Interrupt Request Permission
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1.
+                  #1
+                
+              
+            
+            
+              CYC0
+              Pulse Output Timer 0 Rising Edge Detection Interrupt Request Permission
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0.
+                  #1
+                
+              
+            
+            
+              PRC
+              PRC-TC Status Interrupt Request Permission
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests by the PRC-TC status flag.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests by the PRCTC status flag.
+                  #1
+                
+              
+            
+            
+              SY1
+              SYNFP1 Status Interrupt Request Permission
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests by the SYNFP1 status flag.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests by the SYNFP1 status flag.
+                  #1
+                
+              
+            
+            
+              SY0
+              SYNFP0 Status Interrupt Request Permission
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests by the SYNFP0 status flag.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests by the SYNFP0 status flag.
+                  #1
+                
+              
+            
+            
+              ST
+              STCA Status Interrupt Request Permission
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Prohibits the generation of MINT interrupt requests by the STCA status flag.
+                  #0
+                
+                
+                  1
+                  Permits the generation of MINT interrupt requests by the STCA status flag.
+                  #1
+                
+              
+            
+          
+        
+        
+          ELIPPR
+          ELC Output/ETHER_IPLS Interrupt Request Permission Register
+          0x010
+          32
+          read-write
+          0x00003F3F
+          0xFFFFFFFF
+          
+            
+              PLSN
+              Pulse Output Timer Falling Edge Detection IPLS Interrupt Request Permission
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Prohibits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer.
+                  #0
+                
+                
+                  1
+                  Permits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer.
+                  #1
+                
+              
+            
+            
+              PLSP
+              Pulse Output Timer Rising Edge Detection IPLS Interrupt Request Permission
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Prohibits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer.
+                  #0
+                
+                
+                  1
+                  Permits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer.
+                  #1
+                
+              
+            
+            
+              CYCN5
+              Pulse Output Timer 5 Falling Edge Detection Event Output Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCN4
+              Pulse Output Timer 4 Falling Edge Detection Event Output Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCN3
+              Pulse Output Timer 3 Falling Edge Detection Event Output Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCN2
+              Pulse Output Timer 2 Falling Edge Detection Event Output Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCN1
+              Pulse Output Timer 1 Falling Edge Detection Event Output Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCN0
+              Pulse Output Timer 0 Falling Edge Detection Event Output Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Falling edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Falling edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP5
+              Pulse Output Timer 5 Rising Edge Detection Event Output Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP4
+              Pulse Output Timer 4 Rising Edge Detection Event Output Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP3
+              Pulse Output Timer 3 Rising Edge Detection Event Output Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP2
+              Pulse Output Timer 2 Rising Edge Detection Event Output Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP1
+              Pulse Output Timer 1 Rising Edge Detection Event Output Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+            
+              CYCP0
+              Pulse Output Timer 0 Rising Edge Detection Event  Output Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Rising edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals.
+                  #0
+                
+                
+                  1
+                  Rising edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals.
+                  #1
+                
+              
+            
+          
+        
+        
+          ELIPACR
+          ELC Output/IPLS Interrupt Permission Automatic Clearing Register
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PLSN
+              ELIPPR.PLSN Bit Automatic Clearing
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
+                  #1
+                
+              
+            
+            
+              PLSP
+              ELIPPR.PLSP Bit Automatic Clearing
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer.
+                  #1
+                
+              
+            
+            
+              CYCN5
+              ELIPPR.CYCN5 Bit Automatic Clearing
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5.
+                  #1
+                
+              
+            
+            
+              CYCN4
+              ELIPPR.CYCN4 Bit Automatic Clearing
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4.
+                  #1
+                
+              
+            
+            
+              CYCN3
+              ELIPPR.CYCN3 Bit Automatic Clearing
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3.
+                  #1
+                
+              
+            
+            
+              CYCN2
+              ELIPPR.CYCN2 Bit Automatic Clearing
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2.
+                  #1
+                
+              
+            
+            
+              CYCN1
+              ELIPPR.CYCN1 Bit Automatic Clearing
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1.
+                  #1
+                
+              
+            
+            
+              CYCN0
+              ELIPPR.CYCN0 Bit Automatic Clearing
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0.
+                  #1
+                
+              
+            
+            
+              CYCP5
+              ELIPPR.CYCP5 Bit Automatic Clearing
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5.
+                  #1
+                
+              
+            
+            
+              CYCP4
+              ELIPPR.CYCP4 Bit Automatic Clearing
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4.
+                  #1
+                
+              
+            
+            
+              CYCP3
+              ELIPPR.CYCP3 Bit Automatic Clearing
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3.
+                  #1
+                
+              
+            
+            
+              CYCP2
+              ELIPPR.CYCP2 Bit Automatic Clearing
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2.
+                  #1
+                
+              
+            
+            
+              CYCP1
+              ELIPPR.CYCP1 Bit Automatic Clearing
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1.
+                  #1
+                
+              
+            
+            
+              CYCP0
+              ELIPPR.CYCP0 Bit Automatic Clearing
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0.
+                  #0
+                
+                
+                  1
+                  Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0.
+                  #1
+                
+              
+            
+          
+        
+        
+          STSR
+          STCA Status Register
+          0x040
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              W10D
+              Worst 10 Acquisition Completion Flag
+              4
+              4
+              read-write
+              oneToClear
+              
+                
+                  0
+                  Ten worst values not acquired yet
+                  #0
+                
+                
+                  1
+                  Ten worst values acquired
+                  #1
+                
+              
+            
+            
+              SYNTOUT
+              Sync Message Reception Timeout Detection Flag
+              3
+              3
+              read-write
+              oneToClear
+              
+                
+                  0
+                  Sync message reception timeout not detected
+                  #0
+                
+                
+                  1
+                  Sync message reception timeout detected
+                  #1
+                
+              
+            
+            
+              SYNCOUT
+              Synchronization Loss Detection Flag
+              1
+              1
+              read-write
+              oneToClear
+              
+                
+                  0
+                  Loss of synchronization not detected
+                  #0
+                
+                
+                  1
+                  Loss of synchronization detected
+                  #1
+                
+              
+            
+            
+              SYNC
+              Synchronized State Detection Flag
+              0
+              0
+              read-write
+              oneToClear
+              
+                
+                  0
+                  Synchronization not detected
+                  #0
+                
+                
+                  1
+                  Synchronization detected
+                  #1
+                
+              
+            
+          
+        
+        
+          STIPR
+          STCA Status Notification Permission Register
+          0x044
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              W10D
+              W10D Status Notification Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disable notification of the STSR.W10D state
+                  #0
+                
+                
+                  1
+                  Enable notification of the STSR.W10D state
+                  #1
+                
+              
+            
+            
+              SYNTOUT
+              SYNTOUT Status Notification Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disable notification of the STSR.SYNTOUT state
+                  #0
+                
+                
+                  1
+                  Enable notification of the STSR.SYNTOUT state
+                  #1
+                
+              
+            
+            
+              SYNCOUT
+              SYNCOUT Status Notification Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disable notification of the STSR.SYNCOUT state
+                  #0
+                
+                
+                  1
+                  Enable notification of the STSR.SYNCOUT state
+                  #1
+                
+              
+            
+            
+              SYNC
+              SYNC Status Notification Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable notification of the STSR.SYNC state
+                  #0
+                
+                
+                  1
+                  Enable notification of the STSR.SYNC state
+                  #1
+                
+              
+            
+          
+        
+        
+          STCFR
+          STCA Clock Frequency Setting Register
+          0x050
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              STCF
+              STCA Clock Frequency
+              0
+              1
+              read-write
+              
+                
+                  00
+                  20MHz
+                  #00
+                
+                
+                  01
+                  25MHz
+                  #01
+                
+                
+                  10
+                  50MHz
+                  #10
+                
+                
+                  11
+                  100 MHz
+                  #11
+                
+              
+            
+          
+        
+        
+          STMR
+          STCA Operating Mode Register
+          0x054
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ALEN1
+              Alarm Detection Enable 1
+              29
+              29
+              read-write
+              
+                
+                  0
+                  The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt.
+                  #0
+                
+                
+                  1
+                  The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt.
+                  #1
+                
+              
+            
+            
+              ALEN0
+              Alarm Detection Enable 0
+              28
+              28
+              read-write
+              
+                
+                  0
+                  The STSR.SYNC or SYNCOUT flag is not set to 1 on detection of synchronization or loss of synchronization.
+                  #0
+                
+                
+                  1
+                  The STSR.SYNC or SYNCOUT flag is set to 1 on detection of synchronization or loss of synchronization.
+                  #1
+                
+              
+            
+            
+              DVTH
+              Synchronization Loss Detection Threshold Setting
+              20
+              23
+              read-write
+              
+                
+                  0x0
+                  None
+                  0x0
+                
+                
+                  others
+                  (DVTH) time
+                  true
+                
+              
+            
+            
+              SYTH
+              Synchronized State Detection Threshold Setting
+              16
+              19
+              read-write
+              
+                
+                  0x0
+                  None
+                  0x0
+                
+                
+                  others
+                  (SYTH) time
+                  true
+                
+              
+            
+            
+              W10S
+              Worst 10 Acquisition Control Select
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Measurement is started by hardware and the value acquired in the PW10VR or MW10R register is used as the limit for filtering.
+                  #0
+                
+                
+                  1
+                  Measurement is started by the GETW10R.GW10 bit. Also, the value set in the PLIMITR or MLIMITR register is used as the limit for filtering.
+                  #1
+                
+              
+            
+            
+              CMOD
+              Time Synchronization Correction Mode
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Mode 1
+                  #0
+                
+                
+                  1
+                  Mode 2
+                  #1
+                
+              
+            
+            
+              WINT
+              Worst 10 Acquisition Time
+              0
+              7
+              read-write
+              
+                
+                  0x00
+                  The worst 10 values are not acquired.
+                  0x00
+                
+                
+                  others
+                  Sync message reception: (WINT) time
+                  true
+                
+              
+            
+          
+        
+        
+          SYNTOR
+          Sync Message Reception Timeout Register
+          0x058
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYNTOR
+              A Sync message not being received within 1024 x n (ns), where n is the setting, leads to a timeout for reception of Sync messages, leading to the STSR.SYNTOUT flag being set to 1.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          IPTSELR
+          IPLS Interrupt Request Timer Select Register
+          0x060
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              IPTSEL5
+              Pulse Output Timer 5 Select
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Pulse output timer 5 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 5 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+            
+              IPTSEL4
+              Pulse Output Timer 4 Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Pulse output timer 4 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 4 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+            
+              IPTSEL3
+              Pulse Output Timer 3 Select
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Pulse output timer 3 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 3 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+            
+              IPTSEL2
+              Pulse Output Timer 2 Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Pulse output timer 2 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 2 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+            
+              IPTSEL1
+              Pulse Output Timer 1 Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Pulse output timer 1 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 1 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+            
+              IPTSEL0
+              Pulse Output Timer 0 Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Pulse output timer 0 is not selected as a source of IPLS interrupt requests.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 0 is selected as a source of IPLS interrupt requests.
+                  #1
+                
+              
+            
+          
+        
+        
+          MITSELR
+          MINT Interrupt Request Timer Select Register
+          0x064
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MINTEN5
+              Pulse Output Timer 5 MINT Interrupt Output Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+            
+              MINTEN4
+              Pulse Output Timer 4 MINT Interrupt Output Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+            
+              MINTEN3
+              Pulse Output Timer 3 MINT Interrupt Output Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+            
+              MINTEN2
+              Pulse Output Timer 2 MINT Interrupt Output Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+            
+              MINTEN1
+              Pulse Output Timer 1 MINT Interrupt Output Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+            
+              MINTEN0
+              Pulse Output Timer 0 MINT Interrupt Output Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source.
+                  #0
+                
+                
+                  1
+                  Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source.
+                  #1
+                
+              
+            
+          
+        
+        
+          ELTSELR
+          ELC Output Timer Select Register
+          0x068
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ELTDIS5
+              Pulse Output Timer 5 Event Generation Disable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Pulse output timer 5 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 5 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+            
+              ELTDIS4
+              Pulse Output Timer 4 Event Generation Disable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Pulse output timer 4 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 4 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+            
+              ELTDIS3
+              Pulse Output Timer 3 Event Generation Disable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Pulse output timer 3 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 3 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+            
+              ELTDIS2
+              Pulse Output Timer 2 Event Generation Disable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Pulse output timer 2 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 2 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+            
+              ELTDIS1
+              Pulse Output Timer 1 Event Generation Disable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Pulse output timer 1 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 1 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+            
+              ELTDIS0
+              Pulse Output Timer 0 Event Generation Disable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Pulse output timer 0 is used for the generation of event signals for the ELC.
+                  #0
+                
+                
+                  1
+                  Pulse output timer 0 is not used for the generation of event signals for the ELC.
+                  #1
+                
+              
+            
+          
+        
+        
+          STCHSELR
+          Time Synchronization Channel Select Register
+          0x06C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYSEL
+              Timer Information Input SelectNOTE: Do not change the value of this bit while the SYNSTARTR.STR bit is 1.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Time information from synchronization from the SYNFP0 module is used.
+                  #0
+                
+                
+                  1
+                  Time information from synchronization from the SYNFP1 module is used.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYNSTARTR
+          Slave Time Synchronization Start Register
+          0x080
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              STR
+              Slave Time Synchronization Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Slave time synchronization is stopped.
+                  #0
+                
+                
+                  1
+                  Slave time synchronization is started.
+                  #1
+                
+              
+            
+          
+        
+        
+          LCIVLDR
+          Local Time Counter Initial Value Load Directive Register
+          0x084
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LOAD
+              Local Time Counter Initial Value Load Directive
+              0
+              0
+              write-only
+              
+                
+                  0
+                  The initial value is not loaded into the local time counter.
+                  #0
+                
+                
+                  1
+                  The initial value is loaded into the local time counter.
+                  #1
+                
+              
+            
+          
+        
+        
+          SYNTDARU
+          Synchronization Loss Detection Threshold Registers
+          0x090
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYNTDARU
+              These bits hold the setting for the higher-order 32 bits of the threshold for detection of loss of synchronization.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYNTDARL
+          Synchronization Loss Detection Threshold Registers
+          0x094
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYNTDARL
+              These bits hold the setting for the lower-order 32 bits of the threshold for detection of loss of synchronization.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYNTDBRU
+          Synchronization Detection Threshold Registers
+          0x098
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYNTDBRU
+              These bits hold the setting for the higher-order 32 bits of the threshold for detection of synchronization.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SYNTDBRL
+          Synchronization Detection Threshold Registers
+          0x09C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SYNTDBRL
+              These bits hold the setting for the lower-order 32 bits of the threshold for detection of synchronization.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          LCIVRU
+          Local Time Counter Initial Value Registers
+          0x0B0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCIVRU
+              These bits hold the setting for the higher-order 16 bits of the integer portion of the initial value for the local timer counter.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          LCIVRM
+          Local Time Counter Initial Value Registers
+          0x0B4
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCIVRM
+              These bits hold the setting for the lower-order 32 bits of the integer portion of the initial value for the local timer counter.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          LCIVRL
+          Local Time Counter Initial Value Registers
+          0x0B8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCIVRL
+              These bits hold the setting for the fractional portion of the initial value of the local timer counter in nanoseconds.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GETW10R
+          Worst 10 Acquisition Directive Register
+          0x124
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GW10
+              Worst 10 Acquisition Directive
+              0
+              0
+              read-write
+              
+                
+                  0
+                  The worst-10 values are not acquired.
+                  #0
+                
+                
+                  1
+                  Starts acquisition of the worst-10 values.
+                  #1
+                
+              
+            
+          
+        
+        
+          PLIMITRU
+          Positive Gradient Limit Registers
+          0x128
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PLIMITRU
+              These bits hold the setting for the higher-order 31 bits of the limit for the positive gradient.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          PLIMITRM
+          Positive Gradient Limit Registers
+          0x12C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PLIMITRM
+              These bits hold the setting for the middle-order 32 bits of the limit for the positive gradient.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          PLIMITRL
+          Positive Gradient Limit Registers
+          0x130
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PLIMITRL
+              These bits hold the setting for the lower-order 32 bits of the limit for the positive gradient.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          MLIMITRU
+          Negative Gradient Limit Registers
+          0x134
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MLIMITRU
+              These bits hold the setting for the higher-order 31 bits of the limit for the negative gradient.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          MLIMITRM
+          Negative Gradient Limit Registers
+          0x138
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MLIMITRM
+              These bits hold the setting for the middle-order 32 bits of the limit for the negative gradient.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          MLIMITRL
+          Negative Gradient Limit Registers
+          0x13C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MLIMITRL
+              These bits hold the setting for the lower-order 32 bits of the limit for the negative gradient.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GETINFOR
+          Statistical Information Retention Control Register
+          0x140
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              INFO
+              Information Retention ControlNOTE: Once information fetching is directed, values of various statistical information read before completion of information fetching are not guaranteed.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Has no effects.(write) / Information retention is completed.(read)
+                  #0
+                
+                
+                  1
+                  Information is retained.(write) / Processing for information retention is in progress.(read)
+                  #1
+                
+              
+            
+          
+        
+        
+          LCCVRU
+          Local Time Counters
+          0x170
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCCVRU
+              These bits are for reading the higher-order 16 bits of the integer portion of the local timer counter's value.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          LCCVRM
+          Local Time Counters
+          0x174
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCCVRM
+              These bits are for reading the lower-order 32 bits of the integer portion of the local timer counter's value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          LCCVRL
+          Local Time Counters
+          0x178
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              LCCVRL
+              These bits are for reading the fractional portion of the local timer counter's value (in nanoseconds).
+              0
+              31
+              read-only
+            
+          
+        
+        
+          PW10VRU
+          Positive Gradient Worst 10 Value Registers
+          0x210
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PW10VRU
+              These bits are for reading the higher-order 32 bits of the positive gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          PW10VRM
+          Positive Gradient Worst 10 Value Registers
+          0x214
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PW10VRM
+              These bits are for reading the middle-order 32 bits of the positive gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          PW10VRL
+          Positive Gradient Worst 10 Value Registers
+          0x218
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PW10VRL
+              These bits are for reading the lower-order 32 bits of the positive gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          MW10RU
+          Negative Gradient Worst 10 Value Registers
+          0x2D0
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MW10RU
+              These bits are for reading the higher-order 32 bits of the negative gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          MW10RM
+          Negative Gradient Worst 10 Value Registers
+          0x2D4
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MW10RM
+              These bits are for reading the middle-order 32 bits of the negative gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          MW10RL
+          Negative Gradient Worst 10 Value Registers
+          0x2D8
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              MW10RL
+              These bits are for reading the lower-order 32 bits of the negative gradient value.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          TMSTARTR
+          Timer Start Register
+          0x37C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EN5
+              Pulse Output Timer 5 Start
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 5.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 5.
+                  #1
+                
+              
+            
+            
+              EN4
+              Pulse Output Timer 4 Start
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 4.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 4.
+                  #1
+                
+              
+            
+            
+              EN3
+              Pulse Output Timer 3 Start
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 3.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 3.
+                  #1
+                
+              
+            
+            
+              EN2
+              Pulse Output Timer 2 Start
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 2.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 2.
+                  #1
+                
+              
+            
+            
+              EN1
+              Pulse Output Timer 1 Start
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 1.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 1.
+                  #1
+                
+              
+            
+            
+              EN0
+              Pulse Output Timer 0 Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Stops pulse output timer 0.
+                  #0
+                
+                
+                  1
+                  Starts pulse output timer 0.
+                  #1
+                
+              
+            
+          
+        
+        
+          PRSR
+          PRC-TC Status Register
+          0x400
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              URE1
+              Relay Packet Underflow Detection Flag 1
+              29
+              29
+              read-write
+              oneToClear
+              
+                
+                  0
+                  No underflow in transfer of data from SYNFP0 to SYNFP1.
+                  #0
+                
+                
+                  1
+                  An underflow has been detected in transfer of data from SYNFP0 to SYNFP1.
+                  #1
+                
+              
+            
+            
+              URE0
+              Relay Packet Underflow Detection Flag 0
+              28
+              28
+              read-write
+              oneToClear
+              
+                
+                  0
+                  No underflow in transfer of data from SYNFP1 to SYNFP0.
+                  #0
+                
+                
+                  1
+                  An underflow has been detected in transfer of data from SYNFP1 to SYNFP0.
+                  #1
+                
+              
+            
+            
+              MACE
+              Originating MAC Address Mismatch Detection Flag
+              8
+              8
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  A MAC address mismatch has not been detected.
+                  #0
+                
+                
+                  1
+                  A MAC address mismatch has been detected.
+                  #1
+                
+              
+            
+            
+              OVRE3
+              Relay Packet Overflow Detection Flag 3
+              3
+              3
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No overflow in transfer of data from SYNFP0 to SYNFP1.
+                  #0
+                
+                
+                  1
+                  An overflow has been detected in transfer of data from SYNFP0 to SYNFP1.
+                  #1
+                
+              
+            
+            
+              OVRE2
+              Relay Packet Overflow Detection Flag 2
+              2
+              2
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No overflow in transfer of data from SYNFP1 to SYNFP0.
+                  #0
+                
+                
+                  1
+                  An overflow has been detected in transfer of data from SYNFP1 to SYNFP0.
+                  #1
+                
+              
+            
+            
+              OVRE1
+              Relay Packet Overflow Detection Flag 1
+              1
+              1
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No overflow in transfer of data from SYNFP0 to PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  An overflow has been detected in transfer of data from SYNFP0 to PTPEDMAC.
+                  #1
+                
+              
+            
+            
+              OVRE0
+              Relay Packet Overflow Detection Flag 0
+              0
+              0
+              read-write
+              oneToClear
+              modify
+              
+                
+                  0
+                  No overflow in transfer of data from SYNFP1 to PTPEDMAC.
+                  #0
+                
+                
+                  1
+                  An overflow has been detected in transfer of data from SYNFP1 to PTPEDMAC.
+                  #1
+                
+              
+            
+          
+        
+        
+          PRIPR
+          PRC-TC Status Notification Permission Register
+          0x404
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              URE1
+              PRSR.URE1 Status Notification Permission
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.URE1.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.URE1.
+                  #1
+                
+              
+            
+            
+              URE0
+              PRSR.URE0 Status Notification Permission
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.URE0.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.URE0.
+                  #1
+                
+              
+            
+            
+              MACE
+              PRSR.MACE Status Notification Permission
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.MACE
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.MACE
+                  #1
+                
+              
+            
+            
+              OVRE3
+              PRSR.OVRE3 Status Notification Permission
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.OVRE3.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.OVRE3.
+                  #1
+                
+              
+            
+            
+              OVRE2
+              PRSR.OVRE2 Status Notification Permission
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.OVRE2.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.OVRE2.
+                  #1
+                
+              
+            
+            
+              OVRE1
+              PRSR.OVRE1 Status Notification Permission
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.OVRE1.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.OVRE1.
+                  #1
+                
+              
+            
+            
+              OVRE0
+              PRSR.OVRE0 Status Notification Permission
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Prohibits notification of the state of PRSR.OVRE0.
+                  #0
+                
+                
+                  1
+                  Permits notification of the state of PRSR.OVRE0.
+                  #1
+                
+              
+            
+          
+        
+        
+          TRNDISR
+          Packet Transmission Control Register
+          0x420
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TDIS
+              Packet Transmission Control
+              0
+              1
+              read-write
+              
+                
+                  00
+                  PTP packets are transmitted through both Ethernet port 0 and Ethernet port 1.
+                  #00
+                
+                
+                  01
+                  PTP packets are only transmitted through Ethernet port 0.
+                  #01
+                
+                
+                  10
+                  PTP packets are only transmitted through Ethernet port 1.
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          TRNMR
+          Relay Mode Register
+          0x430
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FWD1
+              Channel 1 Relay Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 1 to port 0.
+                  #0
+                
+                
+                  1
+                  Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 1 to port 0.
+                  #1
+                
+              
+            
+            
+              FWD0
+              Channel 0 Relay Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 0 to port 1.
+                  #0
+                
+                
+                  1
+                  Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 0 to port 1.
+                  #1
+                
+              
+            
+            
+              MOD
+              Cut-Through Mode
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Store-and-forward
+                  #0
+                
+                
+                  1
+                  Cut-through
+                  #1
+                
+              
+            
+          
+        
+        
+          TRNCTTDR
+          Cut-Through Transfer Start Threshold Register
+          0x434
+          32
+          read-write
+          0x00000060
+          0xFFFFFFFF
+          
+            
+              THVAL
+              FIFO Read Start ThresholdThreshold for starting to read data from the relay FIFO in cut-through mode (specified as the number of bytes)NOTE1: A value cannot be set in the lower-order 2 bits. These bits are fixed to 0.NOTE2: A value of less than 96 bytes cannot be set.
+              0
+              10
+              read-write
+            
+          
+        
+      
+    
+    
+      R_FACI_HP_CMD
+      Flash Application Command Interface Command-Issuing Area
+      0x407E0000
+      
+        0x00000000
+        4
+        registers
+      
+      
+        
+          FACI_CMD16
+          FACI Command Issuing Area (halfword access)
+          0
+          16
+          read-write
+          0x0000
+          0xFFFF
+        
+        
+          FACI_CMD8
+          FACI Command Issuing Area (halfword access)
+          FACI_CMD16
+          0
+          8
+          read-write
+          0x00
+          0xFF
+        
+      
+    
+    
+      R_FACI_HP
+      Flash Application Command Interface
+      0x407FE000
+      
+        0x00000000
+        0x100
+        registers
+      
+      
+        
+          FASTAT
+          Flash Access Status
+          0x0010
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CFAE
+              Code Flash Access Error
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No code flash access error has occurred.
+                  #0
+                
+                
+                  1
+                  Code flash access error has occurred.
+                  #1
+                
+              
+            
+            
+              CMDLK
+              Command Lock
+              4
+              4
+              read-only
+            
+            
+              DFAE
+              Data Flash Access Error
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+            
+            
+              ECRCT
+              0
+              0
+              read-only
+            
+          
+        
+        
+          FAEINT
+          Flash Access Error Interrupt Enable
+          0x0014
+          8
+          read-write
+          0x99
+          0xFF
+          
+            
+              CFAEIE
+              Code Flash Access Error Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Does not generate "intflerr" interrupt request when CFAE = "1".
+                  #0
+                
+                
+                  1
+                  Generates "intflerr" interrupt request when CFAE = "1".
+                  #1
+                
+              
+            
+            
+              CMDLKIE
+              Command Lock Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Does not generate "intflerr" interrupt request when CMDLK = "1".
+                  #0
+                
+                
+                  1
+                  Generates "intflerr" interrupt request when CMDLK = "1".
+                  #1
+                
+              
+            
+            
+              DFAEIE
+              Data Flash Access Error Interrupt Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Does not generate "intflerr" interrupt request when DFAE = "1".
+                  #0
+                
+                
+                  1
+                  Generates "intflerr" interrupt request when DFAE = "1".
+                  #1
+                
+              
+            
+            
+              ECRCTIE
+              Error Correct Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Does not generate "intflerr" interrupt request when ECRCT = "1".
+                  #0
+                
+                
+                  1
+                  Generates "intflerr" interrupt request when ECRCT = "1".
+                  #1
+                
+              
+            
+          
+        
+        
+          FRDYIE
+          Flash Ready Interrupt Enable
+          0x0018
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              FRDYIE
+              FRDY Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Does not generate "intflend" interrupt request when FRDY is changed from "0" to "1".
+                  #0
+                
+                
+                  1
+                  Generates "intflend" interrupt request when FRDY is changed from "0" to "1".
+                  #1
+                
+              
+            
+          
+        
+        
+          FSADDR
+          Flash Start Address
+          0x0030
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FSA
+              Start Address of Flash Sequencer Command Target Area
+  These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored.
+              0
+              31
+              read-write
+              
+                
+                  others
+                  Specifies start address for each command processing.
+                  true
+                
+              
+            
+          
+        
+        
+          FEADDR
+          Flash End Address
+          0x0034
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FEA
+              End Address of Flash Sequencer Command Target Area
+  Specifies end address of target area in "Blank Check" command.
+  These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          FSTATR
+          Flash Status
+          0x0080
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EBFULL
+              FDMYECC Buffer Full
+              18
+              18
+              read-only
+              
+                
+                  0
+                  ECC Buffer is not full
+                  #0
+                
+                
+                  1
+                  ECC Buffer is full
+                  #1
+                
+              
+            
+            
+              OTPDTCT
+              OTP Bit ECC 2-Bit Error Detection Monitoring Bit
+              17
+              17
+              read-only
+              
+                
+                  0
+                  No error has been detected.
+                  #0
+                
+                
+                  1
+                  An error has been detected.
+                  #1
+                
+              
+            
+            
+              OTPCRCT
+              OTP Bit ECC 1-Bit Error Correction Monitoring Bit
+              16
+              16
+              read-only
+              
+                
+                  0
+                  No error has been corrected.
+                  #0
+                
+                
+                  1
+                  An error has been corrected.
+                  #1
+                
+              
+            
+            
+              FRDY
+              Flash Ready
+              15
+              15
+              read-only
+              
+                
+                  0
+                  "Program", "DMA Program", "Erase", "Program" or "Erase" command suspension, "Forced Stop", "Blank Check", "Config Program", "Config Clear", "Lock Bit Program", "Lock Bit Read", or "OTP Program" is processing.
+                  #0
+                
+                
+                  1
+                  None of the above is in progress.
+                  #1
+                
+              
+            
+            
+              ILGLERR
+              Illegal Command Error
+              14
+              14
+              read-only
+              
+                
+                  0
+                  Flash sequencer has not detected any illegal command or illegal flash memory access.
+                  #0
+                
+                
+                  1
+                  Flash sequencer has detected an illegal command or illegal flash memory access
+                  #1
+                
+              
+            
+            
+              ERSERR
+              Erasure Error
+              13
+              13
+              read-only
+              
+                
+                  0
+                  Erasure processing has been completed successfully
+                  #0
+                
+                
+                  1
+                  An error has occurred during erasure
+                  #1
+                
+              
+            
+            
+              PRGERR
+              Programming Error
+              12
+              12
+              read-only
+              
+                
+                  0
+                  Programming has been completed successfully
+                  #0
+                
+                
+                  1
+                  An error has occurred during programming
+                  #1
+                
+              
+            
+            
+              SUSRDY
+              Suspend Ready
+              11
+              11
+              read-only
+              
+                
+                  0
+                  Flash sequencer cannot accept "Program/Erase Suspend" command.
+                  #0
+                
+                
+                  1
+                  Flash sequencer can accept "Program/Erase Suspend" command.
+                  #1
+                
+              
+            
+            
+              DBFULL
+              Data Buffer Full
+              10
+              10
+              read-only
+              
+                
+                  0
+                  Data Buffer is not full
+                  #0
+                
+              
+            
+            
+              ERSSPD
+              Erasure-Suspended Status
+              9
+              9
+              read-only
+              
+                
+                  0
+                  Flash sequencer is in status other than the below mentioned.
+                  #0
+                
+                
+                  1
+                  Flash sequencer is in erasure suspension process or erasure-suspended status.
+                  #1
+                
+              
+            
+            
+              PRGSPD
+              Programming-Suspended Status
+              8
+              8
+              read-only
+              
+                
+                  0
+                  Flash sequencer is in status other than the below mentioned.
+                  #0
+                
+                
+                  1
+                  Flash sequencer is in programming suspension process or programming-suspended status.
+                  #1
+                
+              
+            
+            
+              FCUERR
+              FCU Error
+              7
+              7
+              read-only
+              
+                
+                  0
+                  No error has occurred during FPCC processing.
+                  #0
+                
+                
+                  1
+                  An error has occurred during FPCC processing.
+                  #1
+                
+              
+            
+            
+              FHVEERR
+              "fhve" Error
+              6
+              6
+              read-only
+              
+                
+                  0
+                  No error has been detected.
+                  #0
+                
+                
+                  1
+                  An error has been detected.
+                  #1
+                
+              
+            
+            
+              CFGDTCT
+              Config Area ECC 2-Bit Error Detection Monitoring Bit
+              5
+              5
+              read-only
+              
+                
+                  0
+                  No error has been detected.
+                  #0
+                
+                
+                  1
+                  An error has been detected.
+                  #1
+                
+              
+            
+            
+              CFGCRCT
+              Config Area ECC 1-Bit Error Correction Monitoring Bit
+              4
+              4
+              read-only
+              
+                
+                  0
+                  No error has been corrected.
+                  #0
+                
+                
+                  1
+                  An error has been corrected.
+                  #1
+                
+              
+            
+            
+              TBLDTCT
+              Table Area ECC 2-Bit Error Detection Monitoring Bit
+              3
+              3
+              read-only
+              
+                
+                  0
+                  No error has been detected.
+                  #0
+                
+                
+                  1
+                  An error has been detected.
+                  #1
+                
+              
+            
+            
+              TBLCRCT
+              Table Area ECC 1-Bit Error Correction Monitoring Bit
+              2
+              2
+              read-only
+              
+                
+                  0
+                  No error has been corrected.
+                  #0
+                
+                
+                  1
+                  An error has been corrected.
+                  #1
+                
+              
+            
+          
+        
+        
+          FENTRYR
+          Program/Erase Mode Entry
+          0x0084
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              KEY
+              KEY Code
+              8
+              15
+              write-only
+              
+                
+                  0xAA
+                  Writing to the other bits in this register is enabled.
+                  0xAA
+                
+                
+                  others
+                  Writing to the other bits in this register is disabled.
+                  true
+                
+              
+            
+            
+              FENTRYD
+              Data Flash P/E Mode Entry
+  These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored.
+  Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits.
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Data flash is in "Read Mode"
+                  #0
+                
+                
+                  1
+                  Data flash is in "P/E Mode"
+                  #1
+                
+              
+            
+            
+              FENTRYC
+              Code Flash P/E Mode Entry
+  These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored.
+  Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Code flash is in "Read Mode"
+                  #0
+                
+                
+                  1
+                  Code flash is in "P/E Mode"
+                  #1
+                
+              
+            
+          
+        
+        
+          FSUINITR
+          Flash Sequencer Set-up Initialize
+          0x008C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              KEY
+              KEY Code
+              8
+              15
+              write-only
+              
+                
+                  0x2D
+                  Writing to the other bits in this register is enabled.
+                  0x2D
+                
+                
+                  others
+                  Writing to the other bits in this register is disabled.
+                  true
+                
+              
+            
+            
+              SUINIT
+              Set-up Initialization
+  This bit can be written when FRDY bit of FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored.
+  Writing to these bits is enabled only when this register is accessed in 16-bit size and H'2D is written to KEY bits.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Set-up registers keep its' value.
+                  #0
+                
+                
+                  1
+                  Set-up registers are initialized.
+                  #1
+                
+              
+            
+          
+        
+        
+          FCMDR
+          Flash Sequencer Command
+          0x00A0
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              CMDR
+              Command Register
+              8
+              15
+              read-only
+              
+                
+                  others
+                  These bits store the latest command accepted by FACI.
+                  true
+                
+              
+            
+            
+              PCMDR
+              Previous Command Register
+              0
+              7
+              read-only
+              
+                
+                  others
+                  These bits store previous command accepted by FACI.
+                  true
+                
+              
+            
+          
+        
+        
+          FPESTAT
+          Program/Erase Error Status
+          0x00C0
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              PEERRST
+              P/E Error Status
+              0
+              7
+              read-only
+              
+                
+                  0x01
+                  A write attempt made to an area protected by the lock bits
+                  0x01
+                
+                
+                  0x02
+                  A write error caused by other source than the above
+                  0x02
+                
+                
+                  0x11
+                  An erase attempt made to an area protected by the lock bits
+                  0x11
+                
+                
+                  0x12
+                  An erase error caused by other source than the above
+                  0x12
+                
+                
+                  others
+                  Reserved
+                  true
+                
+              
+            
+          
+        
+        
+          FBCCNT
+          Blank Check Control
+          0x00D0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BCDIR
+              Blank Check Direction
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Blank check is executed from smaller address to larger address. (Incremental mode)
+                  #0
+                
+                
+                  1
+                  Blank check is executed from larger address to smaller address. (Decremental mode)
+                  #1
+                
+              
+            
+          
+        
+        
+          FBCSTAT
+          Blank Check Status
+          0x00D4
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              BCST
+              Blank Check Status Bit
+              0
+              0
+              read-only
+              
+                
+                  0
+                  The target area is erased (blank).
+                  #0
+                
+                
+                  1
+                  The target area is filled with 0s and/or 1s.
+                  #1
+                
+              
+            
+          
+        
+        
+          FPSADDR
+          Programmed Area Start Address
+          0x00D8
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PSADR
+              Programmed Area Start Address
+  NOTE: Indicates address of the first programmed data which is found in "Blank Check" command execution.
+              0
+              18
+              read-only
+            
+          
+        
+        
+          FAWMON
+          Flash Access Window Monitor
+          0x0DC
+          32
+          read-only
+          0x00000000
+          0x00000000
+          
+            
+              BTFLG
+              Flag of Start-Up area select for Boot Swap
+              31
+              31
+              read-only
+              
+                
+                  0
+                  The start-up area is the alternate area (sector 1)
+                  #0
+                
+                
+                  1
+                  The start-up area is the default area (sector 0)
+                  #1
+                
+              
+            
+            
+              FAWE
+              End Sector Address for Access Window
+  NOTE: These bits indicate the end sector address for setting the access window that is located in the configuration area.
+              16
+              26
+              read-only
+            
+            
+              FSPR
+              Protection Flag of programming the Access Window, Boot Flag and Temporary Boot Swap Control and "Config Clear" command execution
+              15
+              15
+              read-only
+              
+                
+                  0
+                  Protected state
+                  #0
+                
+                
+                  1
+                  Non-protected state
+                  #1
+                
+              
+            
+            
+              FAWS
+              Start Sector Address for Access Window
+  NOTE: These bits indicate the start sector address for setting the access window that is located in the configuration area. 
+              0
+              10
+              read-only
+            
+          
+        
+        
+          FCPSR
+          FCU Process Switch
+          0x00E0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              ESUSPMD
+              Erasure-Suspended Mode
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Suspension-priority mode
+                  #0
+                
+                
+                  1
+                  Erasure-priority mode
+                  #1
+                
+              
+            
+          
+        
+        
+          FPCKAR
+          Flash Sequencer Processing Clock Frequency Notification
+          0x00E4
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              KEY
+              KEY Code
+              8
+              15
+              write-only
+              
+                
+                  0x1E
+                  Writing to the other bits in this register is enabled.
+                  0x1E
+                
+                
+                  others
+                  Writing to the other bits in this register is disabled.
+                  true
+                
+              
+            
+            
+              PCKA
+              Flash Sequencer Processing Clock Frequency
+  These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored.
+  Writing to these bits is enabled only when this register is accessed in 16-bit size and H'1E is written to KEY bits.
+              0
+              7
+              read-write
+              
+                
+                  others
+                  Notifies operating frequency of clkf.
+                  true
+                
+              
+            
+          
+        
+        
+          FSUACR
+          Flash Start-Up Area Control Register
+          0x00E8
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              KEY
+              KEY Code
+              8
+              15
+              write-only
+              
+                
+                  0x66
+                  Writing to the other bits in this register is enabled.
+                  0x66
+                
+                
+                  others
+                  Writing to the other bits in this register is disabled.
+                  true
+                
+              
+            
+            
+              SAS
+              Start Up Area Select
+  These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored.
+  Writing to these bits is enabled only when this register is accessed in 16-bit size and H'66 is written to KEY bits.
+              0
+              1
+              read-write
+              
+                
+                  10
+                  The start-up area is temporarily switched to the default area (sector 0) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit.
+                  #10
+                
+                
+                  11
+                  The start-up area is temporarily switched to the alternate area (sector 1) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit.
+                  #11
+                
+                
+                  others
+                  The start-up area is selected according to the start-up area setting of the configuration area (BTFLG bit).
+                  true
+                
+              
+            
+          
+        
+      
+    
+    
+      R_FACI_LP
+      Flash Application Command Interface
+      0x407EC000
+      
+        0x00000000
+        0x400
+        registers
+      
+      
+        
+          DFLCTL
+          Flash P/E Mode Control Register
+          0x090
+          8
+          read-write
+          0x00
+          0xFF
+        
+        
+          FPMCR
+          Flash P/E Mode Control Register
+          0x100
+          8
+          read-write
+          0x08
+          0xFF
+          
+            
+              FMS2
+              Flash Operating Mode Select 2.
+Refer to the description of the FMS0 bit.
+              7
+              7
+              read-write
+            
+            
+              VLPE
+              Low-Voltage P/E Mode Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Low-voltage programming is disabled
+                  #0
+                
+                
+                  1
+                  Low-voltage programming is enabled
+                  #1
+                
+              
+            
+            
+              FMS1
+              The bit to make data flash a programming mode
+Refer to the description of the FMS0 bit.
+              4
+              4
+              read-write
+            
+            
+              RPDIS
+              Code Flash P/E Disable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  The programming of the code flash is enabled
+                  #0
+                
+                
+                  1
+                  The programming of the code flash is disabled
+                  #1
+                
+              
+            
+            
+              FMS0
+              Flash Operating Mode Select 0
+FMS2,1,0:
+     000: Read mode
+     011: Discharge mode 1
+     111: Discharge mode 2
+     101: Code Flash P/E mode
+     010: Data flash P/E mode
+     Others: Setting prohibited.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          FASR
+          Flash Area Select Register
+          0x104
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              EXS
+              Extra area select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  User area or data area
+                  #0
+                
+                
+                  1
+                  Extra area
+                  #1
+                
+              
+            
+          
+        
+        
+          FSARL
+          Flash Processing Start Address Register L
+          0x108
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FSAR15_0
+              Start address
+              0
+              15
+              read-write
+            
+          
+        
+        
+          FSARH
+          Flash Processing Start Address Register H
+          0x110
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FSAR31_25
+              Start address
+              9
+              15
+              read-write
+            
+            
+              FSAR20_16
+              Start address
+              0
+              4
+              read-write
+            
+          
+        
+        
+          FCR
+          Flash Control Register
+          0x114
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OPST
+              Processing Start
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Processing stops.
+                  #0
+                
+                
+                  1
+                  Processing starts.
+                  #1
+                
+              
+            
+            
+              STOP
+              Forced Processing Stop
+              6
+              6
+              read-write
+            
+            
+              DRC
+              Data Read Completion
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Data is not read or next data is requested.
+                  #0
+                
+                
+                  1
+                  Data reading is completed.
+                  #1
+                
+              
+            
+            
+              CMD
+              Software Command Setting
+              0
+              3
+              read-write
+              
+                
+                  0001
+                  Program
+                  #0001
+                
+                
+                  0011
+                  Blank check 
+                  #0011
+                
+                
+                  0100
+                  Block erase 
+                  #0100
+                
+                
+                  0101
+                  Consecutive read
+                  #0101
+                
+                
+                  0111
+                  Chip erase
+                  #0111
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          FEARL
+          Flash Processing End Address Register L
+          0x118
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FEAR15_0
+              End address
+              0
+              15
+              read-write
+            
+          
+        
+        
+          FEARH
+          Flash Processing End Address Register H
+          0x120
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FEAR31_25
+              End address
+              9
+              15
+              read-write
+            
+            
+              FEAR20_16
+              End address
+              0
+              4
+              read-write
+            
+          
+        
+        
+          FRESETR
+          Flash Reset Register
+          0x124
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FRESET
+              Software Reset of the registers
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No effect
+                  #0
+                
+                
+                  1
+                  The registers relates to the flash programming are reset.
+                  #1
+                
+              
+            
+          
+        
+        
+          FSTATR00
+          Flash Status Register00
+          0x128
+          32
+          read-only
+          0x00000000
+          0xFFFFFFEF
+          
+            
+              EILGLERR
+              Extra Area Illegal Command Error Flag
+              5
+              5
+              read-only
+              
+                
+                  0
+                  No illegal command or illegal access to the extra area is detected.
+                  #0
+                
+                
+                  1
+                  An illegal command or illegal access to the extra area is detected.
+                  #1
+                
+              
+            
+            
+              ILGLERR
+              Illegal Command Error Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  No illegal software command or illegal access is detected.
+                  #0
+                
+                
+                  1
+                  An illegal command or illegal access is detected.
+                  #1
+                
+              
+            
+            
+              BCERR0
+              Blank Check Error Flag0
+              3
+              3
+              read-only
+              
+                
+                  0
+                  Blank checking terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during blank checking.
+                  #1
+                
+              
+            
+            
+              PRGERR01
+              Program Error Flag 01
+              2
+              2
+              read-only
+              
+                
+                  0
+                  Programming by the FEXCR register terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during programming.
+                  #1
+                
+              
+            
+            
+              PRGERR0
+              Program Error Flag0
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Programming terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during programming.
+                  #1
+                
+              
+            
+            
+              ERERR0
+              Erase Error Flag0
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Erasure terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during erasure.
+                  #1
+                
+              
+            
+          
+        
+        
+          FSTATR1
+          Flash Status Register1
+          0x12C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFB
+          
+            
+              EXRDY
+              End status signal of a Extra programming sequencer
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Other than below
+                  #0
+                
+                
+                  1
+                  The software command of the FEXCR register is terminated.
+                  #1
+                
+              
+            
+            
+              FRDY
+              End status signal of a sequencer
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Other than below
+                  #0
+                
+                
+                  1
+                  The software command of the FCR register is terminated.
+                  #1
+                
+              
+            
+            
+              DRRDY
+              Data read request
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Other than below
+                  #0
+                
+                
+                  1
+                  The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers.
+                  #1
+                
+              
+            
+          
+        
+        
+          FWBL0
+          Flash Write Buffer Register L0
+          0x130
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              WDATA
+              Program data of the program command
+              0
+              15
+              read-write
+            
+          
+        
+        
+          FWBH0
+          Flash Write Buffer Register H0
+          0x138
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              WDATA
+              Program data of the program command
+              0
+              15
+            
+          
+        
+        
+          FSTATR01
+          Flash Status Register01
+          0x13C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BCERR1
+              Blank Check Error Flag1
+              3
+              3
+              
+                
+                  0
+                  Blank checking terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during blank checking.
+                  #1
+                
+              
+            
+            
+              PRGERR1
+              Program Error Flag1
+              1
+              1
+              
+                
+                  0
+                  Programming terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during programming.
+                  #1
+                
+              
+            
+            
+              ERERR1
+              Erase Error Flag1
+              0
+              0
+              
+                
+                  0
+                  Erasure terminates normally.
+                  #0
+                
+                
+                  1
+                  An error occurs during erasure.
+                  #1
+                
+              
+            
+          
+        
+        
+          FWBL1
+          Flash Write Buffer Register L1
+          0x140
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              WDATA47_32
+              Program data of the program command
+              0
+              15
+              read-write
+            
+          
+        
+        
+          FWBH1
+          Flash Write Buffer Register H1
+          0x144
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              WDATA63_48
+              Program data of the program command
+              0
+              15
+            
+          
+        
+        
+          FRBL1
+          Flash Read Buffer Register L1
+          0x148
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDATA47_32
+              Read data of the consecutive read command
+              0
+              15
+              read-only
+            
+          
+        
+        
+          FRBH1
+          Flash Read Buffer Register H1
+          0x14C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDATA63_48
+              Read data of the consecutive read command
+              0
+              15
+              read-only
+            
+          
+        
+        
+          FPR
+          Protection Unlock Register
+          0x180
+          32
+          write-only
+          0x00000000
+          0xFFFFFF00
+          
+            
+              FPR
+              Protection Unlock Register
+              0
+              7
+              write-only
+            
+          
+        
+        
+          FPSR
+          Protection Unlock Status Register
+          0x184
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PERR
+              Protect Error Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  No error
+                  #0
+                
+                
+                  1
+                  An error occurs.
+                  #1
+                
+              
+            
+          
+        
+        
+          FRBL0
+          Flash Read Buffer Register L0
+          0x188
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDATA
+              Read data of the consecutive read command
+              0
+              15
+            
+          
+        
+        
+          FRBH0
+          Flash Read Buffer Register H0
+          0x190
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              RDATA
+              Read data of the consecutive read command
+              0
+              15
+            
+          
+        
+        
+          FSCMR
+          Flash Start-Up Setting Monitor Register
+          0x1C0
+          32
+          read-only
+          0x00000000
+          0xFFFFBEFF
+          
+            
+              FSPR
+              Access Window Protection Flag
+              14
+              14
+              read-only
+            
+            
+              SASMF
+              Start-up Area Setting Monitor Flag
+              8
+              8
+              read-only
+            
+          
+        
+        
+          FAWSMR
+          Flash Access Window Start Address Monitor Register 
+          0x1C8
+          32
+          read-only
+          0x00000000
+          0xFFFFF000
+          
+            
+              FAWS
+              Flash Access Window Start Address
+              0
+              11
+              read-only
+            
+          
+        
+        
+          FAWEMR
+          Flash Access Window End Address Monitor Register
+          0x1D0
+          32
+          read-only
+          0x00000000
+          0xFFFFF000
+          
+            
+              FAWE
+              Flash Access Window End Address
+              0
+              11
+              read-only
+            
+          
+        
+        
+          FISR
+          Flash Initial Setting Register
+          0x1D8
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SAS
+              Temporary boot swap mode
+              6
+              7
+              
+                
+                  10
+                  The start-up area is switched to the default area temporarily.
+                  #10
+                
+                
+                  11
+                  The start-up area is switched to the alternate area temporarily.
+                  #11
+                
+                
+                  others
+                  The start-up area is selected according to the start-up area settings of the extra area.
+                  true
+                
+              
+            
+            
+              PCKA
+              Peripheral Clock Notification
+              0
+              5
+            
+          
+        
+        
+          FEXCR
+          Flash Extra Area Control Register
+          0x1DC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              OPST
+              Software Command Setting
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Processing stops.
+                  #0
+                
+                
+                  1
+                  Processing starts.
+                  #1
+                
+              
+            
+            
+              CMD
+              Processing Start)
+              0
+              2
+              read-write
+              
+                
+                  001
+                  Start-up area selection and security setting
+                  #001
+                
+                
+                  010
+                  Access window information program
+                  #010
+                
+                
+                  011
+                  OCDID1 program
+                  #011
+                
+                
+                  100
+                  OCDID2 program
+                  #100
+                
+                
+                  101
+                  OCDID3 program
+                  #101
+                
+                
+                  110
+                  OCDID4 program
+                  #110
+                
+                
+                  111
+                  Extra area clear
+                  #111
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          FEAML
+          Flash Error Address Monitor Register L
+          0x1E0
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FEAM
+              Flash Error Address Monitor Register
+              0
+              15
+            
+          
+        
+        
+          FEAMH
+          Flash Error Address Monitor Register H
+          0x1E8
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              FEAM
+              Flash Error Address Monitor Register
+              0
+              15
+            
+          
+        
+        
+          FSTATR2
+          Flash Status Register2
+          0x1F0
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EILGLERR
+              Extra Area Illegal Command Error Flag
+              5
+              5
+              read-only
+            
+            
+              ILGLERR
+              Illegal Command Error Flag
+              4
+              4
+              read-only
+            
+            
+              BCERR
+              Blank Check Error Flag
+              3
+              3
+              read-only
+            
+            
+              PRGERR01
+              Program Error Flag 01
+              2
+              2
+              read-write
+            
+            
+              PRGERR1
+              Program Error Flag
+              1
+              1
+              read-only
+            
+            
+              ERERR
+              Erase Error Flag
+              0
+              0
+              read-only
+            
+          
+        
+        
+          FENTRYR_MF4
+          Flash P/E Mode Entry Register for MF4
+          0x3FB0
+          16
+          read-write
+          0x0000
+          0xFFFF
+        
+        
+          FENTRYR
+          Flash P/E Mode Entry Register
+          0x3FB2
+          16
+          read-write
+          0x0000
+          0xFFFF
+        
+        
+          FLWAITR
+          Flash Wait Cycle Register
+          0x3FC0
+          8
+          read-write
+          0x00
+          0xFF
+        
+        
+          PFBER
+          Prefetch Buffer Enable Register
+          0x3FC8
+          8
+          read-write
+          0x00
+          0xFF
+        
+      
+    
+    
+      R_FCACHE
+      Flash Memory Cache
+      0x4001C000
+      
+        0x00000100
+        0x02
+        registers
+      
+      
+        0x00000104
+        0x02
+        registers
+      
+      
+        0x0000011C
+        0x01
+        registers
+      
+      
+        
+          FCACHEE
+          Flash Cache Enable Register
+          0x100
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FCACHEEN
+              FCACHE Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable FCACHE
+                  #0
+                
+                
+                  1
+                  Enable FCACHE
+                  #1
+                
+              
+            
+          
+        
+        
+          FCACHEIV
+          Flash Cache Invalidate Register
+          0x104
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FCACHEIV
+              Flash Cache Invalidate Register 
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not invalidate reads, setting ignored on writes
+                  #0
+                
+                
+                  1
+                  Invalidate on reads and writes.
+                  #1
+                
+              
+            
+          
+        
+        
+          FLWT
+          Flash Wait Cycle Register
+          0x11C
+          8
+          read-write
+          
+            
+              FLWT
+              Flash Wait Cycle
+              0
+              2
+              read-write
+              
+                
+                  000
+                  0 waits (ICLK <= 80 MHz)
+                  #000
+                
+                
+                  001
+                  1 wait (80 MHz < ICLK <= 160 MHz)
+                  #001
+                
+                
+                  010
+                  2 waits (160 MHz < ICLK <= 240 MHz).
+                  #010
+                
+              
+            
+          
+        
+      
+    
+    
+      R_GLCDC
+      Graphics LCD Controller
+      0x400E0000
+      
+        0x00000000
+        0x101C
+        registers
+      
+      
+        0x00001100
+        0x014
+        registers
+      
+      
+        0x00001118
+        0x02C
+        registers
+      
+      
+        0x0000114C
+        0x00C
+        registers
+      
+      
+        0x00001200
+        0x014
+        registers
+      
+      
+        0x00001218
+        0x02C
+        registers
+      
+      
+        0x0000124C
+        0x00C
+        registers
+      
+      
+        0x00001300
+        0x03C
+        registers
+      
+      
+        0x00001340
+        0x03C
+        registers
+      
+      
+        0x00001380
+        0x03C
+        registers
+      
+      
+        0x000013C0
+        0x018
+        registers
+      
+      
+        0x000013E4
+        0x04
+        registers
+      
+      
+        0x00001404
+        0x028
+        registers
+      
+      
+        0x00001440
+        0x014
+        registers
+      
+      
+        
+          BG
+          Background Registers
+          0x1000
+          
+            EN
+            Background Plane Setting Operation Control Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                SWRST
+                Entire module SW reset control
+                16
+                16
+                read-write
+                
+                  
+                    1
+                    Releases the entire module from the SW reset state.
+                    #1
+                  
+                  
+                    0
+                    Places the entire module in the SW reset state.
+                    #0
+                  
+                
+              
+              
+                VEN
+                Control of LCDC internal register value reflection to internal operations
+                8
+                8
+                read-write
+                oneToSet
+                modify
+                
+                  
+                    1
+                    Enables
+                    #1
+                  
+                  
+                    0
+                    Disables(Cleared to 0 by an internal source)
+                    #0
+                  
+                
+              
+              
+                EN
+                Background plane generation module operation enable
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Enables operation.
+                    #1
+                  
+                  
+                    0
+                    Disables operation.
+                    #0
+                  
+                
+              
+            
+          
+          
+            PERI
+            Background Plane Setting Free-Running Period Register
+            0x04
+            32
+            read-write
+            0x00170017
+            0xFFFFFFFF
+            
+              
+                FV
+                Background plane vertical synchronization signal period on the basis of line.
+                16
+                26
+                read-write
+                
+                  
+                    0x013
+                    0x3FF
+                  
+                
+                
+                  
+                    FV
+                    FV lines.The valid range is 0x013 to 0x3FF.
+                    true
+                  
+                
+              
+              
+                FH
+                Background plane horizontal synchronization signal period on the basis of pixel clock (PXCLK).
+                0
+                10
+                read-write
+                
+                  
+                    0x017
+                    0x3FF
+                  
+                
+                
+                  
+                    FH
+                    FH lines. The valid range is 0x017 to 0x3FF. 
+                    true
+                  
+                
+              
+            
+          
+          
+            SYNC
+            Background Plane Setting Synchronization Position Register
+            0x08
+            32
+            read-write
+            0x00010001
+            0xFFFFFFFF
+            
+              
+                VP
+                Background plane vertical synchronization signal assertion position on the basis of line.
+                16
+                19
+                read-write
+                
+                  
+                    0x0
+                    Setting prohibited
+                    0x0
+                  
+                  
+                    others
+                    (VP)th line
+                    true
+                  
+                
+              
+              
+                HP
+                Background plane horizontal synchronization signal assertion position on the basis of pixel clock (PXCLK).
+                0
+                3
+                read-write
+                
+                  
+                    0x0
+                    Setting prohibited
+                    0x0
+                  
+                  
+                    others
+                    (HP)th line (pixels)
+                    true
+                  
+                
+              
+            
+          
+          
+            VSIZE
+            Background Plane Setting Full Image Vertical Size Register
+            0x0C
+            32
+            read-write
+            0x00070010
+            0xFFFFFFFF
+            
+              
+                VP
+                Background plane vertical valid pixel start position on the basis of line
+                16
+                26
+                read-write
+                
+                  
+                    0x0003
+                    0x3EF
+                  
+                
+                
+                  
+                    VP
+                    VP lines. The valid range is 0x003 to 0x3EF. 
+                    true
+                  
+                
+              
+              
+                VW
+                Background plane vertical valid pixel width on the basis of line 
+                0
+                10
+                read-write
+                
+                  
+                    0x0010
+                    0x03FC
+                  
+                
+                
+                  
+                    VW
+                    VW lines. The valid range is 0x010 to 0x3F0. 
+                    true
+                  
+                
+              
+            
+          
+          
+            HSIZE
+            Background Plane Setting Full Image Horizontal Size Register
+            0x10
+            32
+            read-write
+            0x00060010
+            0xFFFFFFFF
+            
+              
+                HP
+                Background plane horizontal valid pixel start position on the basis of pixel clock (PXCLK).
+                16
+                26
+                read-write
+                
+                  
+                    0x006
+                    0x3EE
+                  
+                
+                
+                  
+                    HP
+                    HP cycle(pixel). The valid range is 0x006 to 0x3EE. 
+                    true
+                  
+                
+              
+              
+                HW
+                
+									Background plane horizontall valid pixel width on the basis of pixel clock (PXCLK)
+									Note: When serial RGB is selected as the output format for the output control block, add two to the horizontal enable signal width and set the resulting value to this field.
+								
+                0
+                10
+                read-write
+                
+                  
+                    0x010
+                    0x3F8
+                  
+                
+                
+                  
+                    HW
+                    HW cycles. The valid range is 0x010 to 0x3F8. 
+                    true
+                  
+                
+              
+            
+          
+          
+            BGC
+            Background Plane Setting Background Color Register
+            0x14
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                R
+                
+									R value for background plane valid pixel area.
+									Unsigned; 8-bit integer.
+								
+                16
+                23
+                read-write
+              
+              
+                G
+                
+									G value for background plane valid pixel area
+									Unsigned; 8-bit integer
+								
+                8
+                15
+                read-write
+              
+              
+                B
+                
+									B value for background plane valid pixel area
+									Unsigned; 8-bit integer
+								
+                0
+                7
+                read-write
+              
+            
+          
+          
+            MON
+            Background Plane Setting Status Monitor Register
+            0x18
+            32
+            read-only
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                SWRST
+                Entire module SW reset state monitor.
+                16
+                16
+                read-only
+                
+                  
+                    1
+                    The entire module is released from the SW reset state.
+                    #1
+                  
+                  
+                    0
+                    The entire module is in the SW reset state.
+                    #0
+                  
+                
+              
+              
+                VEN
+                
+									Entire module internal operation reflection control signal monitor.
+									The signal  state for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal.
+								
+                8
+                8
+                read-only
+                
+                  
+                    1
+                    The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is asserted.
+                    #1
+                  
+                  
+                    0
+                    The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is negated.
+                    #0
+                  
+                
+              
+              
+                EN
+                Background plane generation module operation state monitor.
+                0
+                0
+                read-only
+                
+                  
+                    1
+                    Operation is in progress.
+                    #1
+                  
+                  
+                    0
+                    Operation is stopped.
+                    #0
+                  
+                
+              
+            
+          
+        
+        
+          2
+          0x100
+          GR[%s]
+          Layer Registers
+          0x1100
+          
+            VEN
+            Graphics Register Update Control Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                PVEN
+                
+									Control of graphics n module register value reflection to internal operations.
+									Reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).
+								
+                0
+                0
+                read-write
+                zeroToClear
+                modify
+                
+                  
+                    1
+                    Enables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).
+                    #1
+                  
+                  
+                    0
+                    Disables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS).
+                    #0
+                  
+                
+              
+            
+          
+          
+            FLMRD
+            Graphics Frame Buffer Read Control Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                RENB
+                Graphics data (frame buffer data) read enable.
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Enables reading.
+                    #1
+                  
+                  
+                    0
+                    Disables reading.
+                    #0
+                  
+                
+              
+            
+          
+          
+            FLM1
+            Graphics Frame Buffer Control Register 1
+            0x08
+            32
+            read-only
+            0x00000003
+            0xFFFFFFFF
+            
+              
+                BSTMD
+                
+									Burst transfer control for graphics data (frame buffer data)
+									access
+								
+                0
+                1
+                read-only
+                
+                  
+                    11
+                    16-beat increment burst transfer (64-byte boundary)
+                    #11
+                  
+                  
+                    others
+                    Setting prohibited.
+                    true
+                  
+                
+              
+            
+          
+          
+            FLM2
+            Graphics Frame Buffer Control Register 2
+            0x0C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                BASE
+                
+									Base address for accessing graphics data (frame buffer data)
+									Set the head address in the frame buffer where graphics data is to be stored. GRn_FLM2.BASE[5:0] should be fixed to 0 during 64-byte burst transfer.
+								
+                0
+                31
+                read-write
+              
+            
+          
+          
+            FLM3
+            Graphics Frame Buffer Control Register 3
+            0x10
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                LNOFF
+                
+									Macro line offset address for accessing graphics data
+									(frame buffer data)
+									Signed; 16-bit integer
+								
+                16
+                31
+                read-write
+              
+            
+          
+          
+            FLM5
+            Graphics Frame Buffer Control Register 5
+            0x18
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                LNNUM
+                Number of lines per frame for accessing graphics data (frame buffer data).
+                16
+                26
+                read-write
+                
+                  
+                    0x00F
+                    0x3FF
+                  
+                
+                
+                  
+                    LNNUM
+                    LNNUM lines.  The valid range is 0x00F to 0x3FF. 
+                    true
+                  
+                
+              
+              
+                DATANUM
+                Number of data transfer times per line for accessing graphics data (frame buffer data), where one transfer is defined as 16-beat burst access (64-byte boundary)
+                0
+                15
+                read-write
+                
+                  
+                    DATAUM
+                    DATAUM+1 times.
+                    true
+                  
+                
+              
+            
+          
+          
+            FLM6
+            Graphics Frame Buffer Control Register 6
+            0x1C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                FORMAT
+                Data format for accessing graphics data (frame buffer data).
+                28
+                30
+                read-write
+                
+                  
+                    111
+                    CLUT11bit/pix)
+                    #111
+                  
+                  
+                    110
+                    CLUT4 (4 bits/pix)
+                    #110
+                  
+                  
+                    101
+                    CLUT8 (8 bits/pix)
+                    #101
+                  
+                  
+                    100
+                    ARGB8888 (32 bits/pix)
+                    #100
+                  
+                  
+                    011
+                    ARGB4444 (16 bits/pix)
+                    #011
+                  
+                  
+                    010
+                    ARGB1555 (16 bits/pix, 1 bit of A is LUT data)
+                    #010
+                  
+                  
+                    001
+                    RGB888 (32 bits/pix, 8 bits on the MSB side are invalid)
+                    #001
+                  
+                  
+                    000
+                    RGB565 (16 bits/pix)
+                    #000
+                  
+                  
+                    others
+                    Setting prohibited.
+                    true
+                  
+                
+              
+            
+          
+          
+            AB1
+            Graphics Alpha Blending Control Register 1
+            0x20
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                ARCON
+                Rectangular area alpha blending control.
+                12
+                12
+                read-write
+                
+                  
+                    1
+                    On
+                    #1
+                  
+                  
+                    0
+                    Off
+                    #0
+                  
+                
+              
+              
+                ARCDISPON
+                Image area border display control for rectangular area alpha blending.
+                8
+                8
+                read-write
+                
+                  
+                    1
+                    Display on
+                    #1
+                  
+                  
+                    0
+                    Display off
+                    #0
+                  
+                
+              
+              
+                GRCDISPON
+                Graphics image area border display control.
+                4
+                4
+                read-write
+                
+                  
+                    1
+                    Display on
+                    #1
+                  
+                  
+                    0
+                    Display off
+                    #0
+                  
+                
+              
+              
+                DISPSEL
+                Graphics display plane control.
+                0
+                1
+                read-write
+                
+                  
+                    11
+                    Blended display of lower-layer graphics (input image from the previous stage) and current graphics (graphics data read from the AHB bus)
+                    #11
+                  
+                  
+                    10
+                    Current graphics display
+                    #10
+                  
+                  
+                    01
+                    Lower-layer graphics display
+                    #01
+                  
+                  
+                    00
+                    Background color display (value set by the GRn_BASE register).
+                    #00
+                  
+                
+              
+            
+          
+          
+            AB2
+            Graphics Alpha Blending Control Register 2
+            0x24
+            32
+            read-write
+            0x00060010
+            0xFFFFFFFF
+            
+              
+                GRCVS
+                Vertical start position of graphics image area.
+                16
+                26
+                read-write
+                
+                  
+                    0x002
+                    0x3EE
+                  
+                
+                
+                  
+                    GRCVS
+                    GRCVS lines. The valid range is 0x002 to 0x3EE. 
+                    true
+                  
+                
+              
+              
+                GRCVW
+                Vertical width of graphics image area.
+                0
+                10
+                read-write
+                
+                  
+                    0x010
+                    0x3FC
+                  
+                
+                
+                  
+                    GRCVW
+                    GRCVW lines.  The valid range is 0x010 to 0x3F0. 
+                    true
+                  
+                
+              
+            
+          
+          
+            AB3
+            Graphics Alpha Blending Control Register 3
+            0x28
+            32
+            read-write
+            0x00050010
+            0xFFFFFFFF
+            
+              
+                GRCHS
+                Horizontal start position of graphics image area.
+                16
+                26
+                read-write
+                
+                  
+                    0x005
+                    0x3ED
+                  
+                
+                
+                  
+                    GRCHS
+                    GRCHS lines. The valid range is 0x005 to 0x3ED. 
+                    true
+                  
+                
+              
+              
+                GRCHW
+                Horizontal width of graphics image area.
+                0
+                10
+                read-write
+                
+                  
+                    0x010
+                    0x3F0
+                  
+                
+                
+                  
+                    GRCHW
+                    GRCHW pixels. The valid range is 0x010 to 0x3F0. 
+                    true
+                  
+                
+              
+            
+          
+          
+            AB4
+            Graphics Alpha Blending Control Register 4
+            0x2C
+            32
+            read-write
+            0x00060010
+            0xFFFFFFFF
+            
+              
+                ARCVS
+                Vertical start position of rectangular area alpha blending image area
+                16
+                26
+                read-write
+                
+                  
+                    0x002
+                    0x3EE
+                  
+                
+                
+                  
+                    ARCVS
+                    ARCVS linels. The valid range is 0x002 to 0x3EE. 
+                    true
+                  
+                
+              
+              
+                ARCVW
+                Vertical width of rectangular area alpha blending image area.
+                0
+                10
+                read-write
+                
+                  
+                    0x001
+                    0x3FC
+                  
+                
+                
+                  
+                    ARCVW
+                    ARCVW linels. The valid range is 0x001 to 0x3F0. 
+                    true
+                  
+                
+              
+            
+          
+          
+            AB5
+            Graphics Alpha Blending Control Register 5
+            0x30
+            32
+            read-write
+            0x00050010
+            0xFFFFFFFF
+            
+              
+                ARCHS
+                Horizontal start position of rectangular area alpha blending image area.
+                16
+                26
+                read-write
+                
+                  
+                    0x005
+                    0x3ED
+                  
+                
+                
+                  
+                    ARCHS
+                    ARCHS pixel. The valid range is 0x005 to 0x3ED. 
+                    true
+                  
+                
+              
+              
+                ARCHW
+                Horizontal width of rectangular area alpha blending image area.
+                0
+                10
+                read-write
+                
+                  
+                    0x001
+                    0x3F8
+                  
+                
+                
+                  
+                    ARCHW
+                    ARCHW pixels. The valid range is 0x001 to 0x3F0. 
+                    true
+                  
+                
+              
+            
+          
+          
+            AB6
+            Graphics Alpha Blending Control Register 6
+            0x34
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                ARCCOEF
+                
+									Alpha coefficient for alpha blending in rectangular area (-255 to 255).
+									[8]: Sign (0: addition, 1: subtraction)
+									[7:0]: Variation (absolute value)
+								
+                16
+                24
+                read-write
+              
+              
+                ARCRATE
+                Frame rate for alpha blending in rectangular area.
+                0
+                7
+                read-write
+                
+                  
+                    ARCRATE
+                    ARCRATE+1 frames
+                    true
+                  
+                
+              
+            
+          
+          
+            AB7
+            Graphics Alpha Blending Control Register 7
+            0x38
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                ARCDEF
+                Initial alpha value for alpha blending in rectangular area.
+                16
+                23
+                read-write
+              
+              
+                CKON
+                RGB-index chroma-key processing control.
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Enables chroma-key processing
+                    #1
+                  
+                  
+                    0
+                    Disables chroma-key processing
+                    #0
+                  
+                
+              
+            
+          
+          
+            AB8
+            Graphics Alpha Blending Control Register 8
+            0x3C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                CKKG
+                
+									G signal for RGB-index chroma-key processing
+									Unsigned; 8 bits.
+								
+                16
+                23
+                read-write
+              
+              
+                CKKB
+                
+									B signal for RGB-index chroma-key processing
+									Unsigned; 8 bits.
+								
+                8
+                15
+                read-write
+              
+              
+                CKKR
+                
+									R signal for RGB-index chroma-key processing
+									Unsigned; 8 bits.
+								
+                0
+                7
+                read-write
+              
+            
+          
+          
+            AB9
+            Graphics Alpha Blending Control Register 9
+            0x40
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                CKA
+                A value after RGB-index chroma-key processing replacement.
+                24
+                31
+                read-write
+              
+              
+                CKG
+                
+									G value after RGB-index chroma-key processing replacement
+									Unsigned; 8 bits.
+								
+                16
+                23
+                read-write
+              
+              
+                CKB
+                
+									B value after RGB-index chroma-key processing replacement
+									Unsigned; 8 bits.
+								
+                8
+                15
+                read-write
+              
+              
+                CKR
+                
+									R value after RGB-index chroma-key processing replacement
+									Unsigned; 8 bits.
+								
+                0
+                7
+                read-write
+              
+            
+          
+          
+            BASE
+            Graphics Background Color Control Register
+            0x4C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                G
+                
+									Background color G value
+									Unsigned; 8 bits
+								
+                16
+                23
+                read-write
+              
+              
+                B
+                
+									Background color B value
+									Unsigned; 8 bits
+								
+                8
+                15
+                read-write
+              
+              
+                R
+                
+									Background color R value
+									Unsigned; 8 bits
+								
+                0
+                7
+                read-write
+              
+            
+          
+          
+            CLUTINT
+            Graphics CLUT Table Interrupt Control Register
+            0x50
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                SEL
+                CLUT table control
+                16
+                16
+                read-write
+                
+                  
+                    1
+                    Uses CLUT1 plane for internal operations.
+                    #1
+                  
+                  
+                    0
+                    Uses CLUT0 plane for internal operations.
+                    #0
+                  
+                  
+                    others
+                    Setting prohibited
+                    true
+                  
+                
+              
+              
+                LINE
+                Number of detection lines
+                0
+                10
+                read-write
+                
+                  
+                    0x000
+                    0x400
+                  
+                
+                
+                  
+                    LINE
+                    LINE+1 lines. The valid range is 0x000 to 0x400. 
+                    true
+                  
+                
+              
+            
+          
+          
+            MON
+            Graphics Status Monitor Register
+            0x54
+            32
+            read-only
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                UNDFLST
+                Status monitor for underflow
+                16
+                16
+                read-only
+                
+                  
+                    1
+                    An underflow occurs in internal operations.
+                    #1
+                  
+                  
+                    0
+                    No underflow occurs in internal operations.
+                    #0
+                  
+                
+              
+              
+                ARCST
+                Status monitor for alpha blending in rectangular area
+                0
+                0
+                read-only
+                
+                  
+                    1
+                    Fade-in/fade-out is in progress.
+                    #1
+                  
+                  
+                    0
+                    Fade-in/fade-out is not in progress.
+                    #0
+                  
+                
+              
+            
+          
+        
+        
+          3
+          0x40
+          GAM[%s]
+          Gamma Settings
+          0x1300
+          
+            LATCH
+            Gamma Register Update Control Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                VEN
+                
+									Control of gamma correction x module register value reflection to internal operations.
+									The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+								
+                0
+                0
+                read-write
+                zeroToClear
+                modify
+                
+                  
+                    1
+                    Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+                    #1
+                  
+                  
+                    0
+                    Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+                    #0
+                  
+                
+              
+            
+          
+          
+            GAM_SW
+            Gamma Correction Block Function Switch Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                GAMON
+                Gamma correction on/off control
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Turns on gamma correction.
+                    #1
+                  
+                  
+                    0
+                    Turns off gamma correction.
+                    #0
+                  
+                
+              
+            
+          
+          
+            8
+            0x04
+            LUT[%s]
+            Gamma Correction Block Table Setting Register 
+            0x08
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                2
+                16
+                HIGH,LOW
+                _%s
+                
+									Gain value of area 0.
+									Unsigned 11-bit fixed point.
+								
+                0
+                10
+                read-write
+                
+                  
+                    GAIN00
+                    GAIN00/1024
+                    true
+                  
+                
+              
+            
+          
+          
+            5
+            0x04
+            AREA[%s]
+            Gamma Correction Block Area Setting Register 
+            0x28
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                3
+                10
+                HIGH,MID,LOW
+                _%s
+                
+									Start threshold of area 1
+									Unsigned 10-bit integer
+								
+                0
+                9
+                read-write
+              
+            
+          
+        
+        
+          OUT
+          Output Control Registers
+          0x13C0
+          
+            VLATCH
+            Output Control Block Register Update Control Register
+            0x0
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                VEN
+                
+									Control of output control module register value reflection to internal operations.
+									The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+								
+                0
+                0
+                read-write
+                zeroToClear
+                modify
+                
+                  
+                    1
+                    Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+                    #1
+                  
+                  
+                    0
+                    Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS).
+                    #0
+                  
+                
+              
+            
+          
+          
+            SET
+            Output Control Block Output Interface Register
+            0x4
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                ENDIANON
+                Bit endian change control
+                28
+                28
+                read-write
+                
+                  
+                    1
+                    Ascending order (big endian)
+                    #1
+                  
+                  
+                    0
+                    Descending order (little endian)
+                    #0
+                  
+                
+              
+              
+                SWAPON
+                Pixel order control
+                24
+                24
+                read-write
+                
+                  
+                    1
+                    In the order of BGR
+                    #1
+                  
+                  
+                    0
+                    In the order of RGB
+                    #0
+                  
+                
+              
+              
+                FORMAT
+                Output format select
+                12
+                13
+                read-write
+                
+                  
+                    11
+                    Serial RGB; select RGB888 as dither output format.
+                    #11
+                  
+                  
+                    10
+                    RGB565; select RGB565 as dither output format.
+                    #10
+                  
+                  
+                    01
+                    RGB666; select RGB666 as dither output format.
+                    #01
+                  
+                  
+                    00
+                    RGB888; select RGB888 as dither output format.
+                    #00
+                  
+                
+              
+              
+                FRQSEL
+                Clock frequency division control
+                8
+                9
+                read-write
+                
+                  
+                    11
+                    Setting prohibited
+                    #11
+                  
+                  
+                    10
+                    Quarter frequency (serial RGB)
+                    #10
+                  
+                  
+                    01
+                    Setting prohibited
+                    #01
+                  
+                  
+                    00
+                    No frequency division, parallel RGB
+                    #00
+                  
+                
+              
+              
+                DIRSEL
+                Invalid data position control in serial RGB format
+                4
+                4
+                read-write
+                
+                  
+                    1
+                    Invalid data is output prior to valid (RGB) data.
+                    #1
+                  
+                  
+                    0
+                    Invalid data is output following valid (RGB) data.
+                    #0
+                  
+                
+              
+              
+                PHASE
+                Data delay in serial RGB format (based on OUTCLK)
+                0
+                1
+                read-write
+                
+                  
+                    11
+                    3 cycles
+                    #11
+                  
+                  
+                    10
+                    2 cycles
+                    #10
+                  
+                  
+                    01
+                    1 cycle
+                    #01
+                  
+                  
+                    00
+                    0 cycle
+                    #00
+                  
+                
+              
+            
+          
+          
+            BRIGHT1
+            Output Control Block Brightness Correction Register 1
+            0x8
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                BRTG
+                
+									Brightness (DC) adjustment of G signal
+									Unsigned; 10 bits; +512 with offset; integer
+								
+                0
+                9
+                read-write
+              
+            
+          
+          
+            BRIGHT2
+            Output Control Block Brightness Correction Register 2
+            0xC
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                BRTB
+                
+									Brightness (DC) adjustment of B signal
+									Unsigned; 10 bits; +512 with offset; integer
+								
+                16
+                25
+                read-write
+              
+              
+                BRTR
+                
+									Brightness (DC) adjustment of R signal
+									Unsigned; 10 bits; +512 with offset; integer
+								
+                0
+                9
+                read-write
+              
+            
+          
+          
+            CONTRAST
+            Output Control Block Contrast Correction Register
+            0x10
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                CONTG
+                
+									Contrast (GAIN) adjustment of G signal
+									Unsigned; 8 bits fixed point.
+								
+                16
+                23
+                read-write
+                
+                  
+                    CONTG
+                    CONTG/128
+                    true
+                  
+                
+              
+              
+                CONTB
+                
+									Contrast (GAIN) adjustment of B signal
+									Unsigned; 8 bits fixed point
+								
+                8
+                15
+                read-write
+                
+                  
+                    CONTB
+                    CONTB/128
+                    true
+                  
+                
+              
+              
+                CONTR
+                
+									Contrast (GAIN) adjustment of R signal
+									Unsigned; 8 bits fixed point
+								
+                0
+                7
+                read-write
+                
+                  
+                    CONTR
+                    CONTR/128
+                    true
+                  
+                
+              
+            
+          
+          
+            PDTHA
+            Output Control Block Panel Dither Correction Register
+            0x14
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                SEL
+                Operation mode
+                20
+                21
+                read-write
+                
+                  
+                    11
+                    Setting prohibited
+                    #11
+                  
+                  
+                    10
+                    2x2 pattern dither
+                    #10
+                  
+                  
+                    01
+                    Round-off
+                    #01
+                  
+                  
+                    00
+                    Truncate
+                    #00
+                  
+                
+              
+              
+                FORM
+                Output format select
+                16
+                17
+                read-write
+                
+                  
+                    11
+                    Setting prohibited
+                    #11
+                  
+                  
+                    10
+                    RGB565; select RGB565 as output interface format.
+                    #10
+                  
+                  
+                    01
+                    RGB666; select RGB666 as output interface format.
+                    #01
+                  
+                  
+                    00
+                    RGB888; select RGB888 or serial RGB as output interface format.
+                    #00
+                  
+                
+              
+              
+                PA
+                
+									Pattern value (A) of 2 x 2 pattern dither
+									Unsigned 2-bit integer
+								
+                12
+                13
+                read-write
+              
+              
+                PB
+                
+									Pattern value (B) of 2 x 2 pattern dither
+									Unsigned 2-bit integer
+								
+                8
+                9
+                read-write
+              
+              
+                PC
+                
+									Pattern value (C) of 2 x 2 pattern dither
+									Unsigned 2-bit integer
+								
+                4
+                5
+                read-write
+              
+              
+                PD
+                
+									Pattern value (D) of 2 x 2 pattern dither
+									Unsigned 2-bit integer
+								
+                0
+                1
+                read-write
+              
+            
+          
+          
+            CLKPHASE
+            Output Control Block Output Phase Control Register
+            0x24
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                FRONTGAM
+                Correction control
+                12
+                12
+                read-write
+                
+                  
+                    1
+                    Gamma correction is followed by brightness/contrast correction.
+                    #1
+                  
+                  
+                    0
+                    Brightness/contrast correction is followed by gamma correction.
+                    #0
+                  
+                
+              
+              
+                LCDEDGE
+                LCD_DATA Output Phase Control
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    In synchronization with the rising edge of LCD_CLK.
+                    #0
+                  
+                  
+                    1
+                    In synchronization with the falling edge of LCD_CLK
+                    #1
+                  
+                
+              
+              
+                TCON0EDGE
+                LCD_TCON0 Output Phase Control
+                6
+                6
+                read-write
+                
+                  
+                    1
+                    In synchronization with the falling edge of LCD_CLK.
+                    #1
+                  
+                  
+                    0
+                    In synchronization with the rising edge of LCD_CLK.
+                    #0
+                  
+                
+              
+              
+                TCON1EDGE
+                LCD_TCON1 Output Phase Control
+                5
+                5
+                read-write
+                
+                  
+                    1
+                    In synchronization with the falling edge of LCD_CLK.
+                    #1
+                  
+                  
+                    0
+                    In synchronization with the rising edge of LCD_CLK.
+                    #0
+                  
+                
+              
+              
+                TCON2EDGE
+                LCD_TCON2 Output Phase Control
+                4
+                4
+                read-write
+                
+                  
+                    1
+                    In synchronization with the falling edge of LCD_CLK.
+                    #1
+                  
+                  
+                    0
+                    In synchronization with the rising edge of LCD_CLK.
+                    #0
+                  
+                
+              
+              
+                TCON3EDGE
+                LCD_TCON3 Output Phase Control
+                3
+                3
+                read-write
+                
+                  
+                    1
+                    In synchronization with the falling edge of LCD_CLK.
+                    #1
+                  
+                  
+                    0
+                    In synchronization with the rising edge of LCD_CLK.
+                    #0
+                  
+                
+              
+            
+          
+        
+        
+          TCON
+          Timing Control Registers
+          0x1400
+          
+            TIM
+            TCON Reference Timing Setting Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                HALF
+                
+									Vertical synchronization signal generation change timing
+									Sets the delay from the assertion of the internal horizontal synchronization signal in terms of pixels.
+								
+                16
+                26
+                read-write
+                
+                  
+                    0x000
+                    0x3FF
+                  
+                
+                
+                  
+                    HALF
+                    HALF pixels. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+              
+                OFFSET
+                
+									Horizontal synchronization signal generation reference timing
+									Sets the offset from the assertion of the internal horizontal synchronization signal in terms of pixels.
+								
+                0
+                10
+                read-write
+                
+                  
+                    0x000
+                    0x3FF
+                  
+                
+                
+                  
+                    OFFSET
+                    OFFSET+1 pixels. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+            
+          
+          
+            2
+            0x8
+            A,B
+            STV%s1
+            TCON Vertical Timing Setting Register %s1
+            0x08
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                VS
+                STVx1 first change timing
+                16
+                26
+                read-write
+                
+                  
+                    0x000
+                    0x7FF
+                  
+                
+                
+                  
+                    VS
+                    VS pixels. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+              
+                VW
+                
+									STVx1 second change timing
+									Sets the signal assertion width.
+								
+                0
+                10
+                read-write
+                
+                  
+                    0x000
+                    0x7FF
+                  
+                
+                
+                  
+                    VW
+                    VW pixels. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+            
+          
+          
+            2
+            0x8
+            A,B
+            STV%s2
+            TCON Vertical Timing Setting Register %s2
+            0x0C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                INV
+                STVx signal polarity inversion control 
+                4
+                4
+                read-write
+                
+                  
+                    1
+                    Inverted
+                    #1
+                  
+                  
+                    0
+                    Not inverted
+                    #0
+                  
+                
+              
+              
+                SEL
+                Output signal select control for VSOUT (controlled by TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 register) pin
+                0
+                2
+                read-write
+                
+                  
+                    111
+                    DE
+                    #111
+                  
+                  
+                    110
+                    Setting prohibited
+                    #110
+                  
+                  
+                    101
+                    Setting prohibited
+                    #101
+                  
+                  
+                    100
+                    Setting prohibited
+                    #100
+                  
+                  
+                    011
+                    STHB
+                    #011
+                  
+                  
+                    010
+                    STHA
+                    #010
+                  
+                  
+                    001
+                    STVB
+                    #001
+                  
+                  
+                    000
+                    STVA
+                    #000
+                  
+                
+              
+            
+          
+          
+            2
+            0x8
+            A,B
+            STH%s1
+            TCON Horizontal Timing Setting Register STH%s1
+            0x18
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                HS
+                STHx1 first change timing
+                16
+                26
+                read-write
+                
+                  
+                    0x000
+                    0x3FF
+                  
+                
+                
+                  
+                    HS
+                    HS lines. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+              
+                HW
+                
+									STHx1 second change timing.
+									Sets the signal assertion width.
+								
+                0
+                10
+                read-write
+                
+                  
+                    0x000
+                    0x3FF
+                  
+                
+                
+                  
+                    HW
+                    HW pixels. The valid range is 0x000 to 0x3FF. 
+                    true
+                  
+                
+              
+            
+          
+          
+            2
+            0x8
+            A,B
+            STH%s2
+            TCON Horizontal Timing Setting Register STH%s2
+            0x1C
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                HSSEL
+                STHx signal generation reference timing control.
+                8
+                8
+                read-write
+                
+                  
+                    1
+                    Reference timing is the offset set with the TCON_TIM.OFFSET[10:0] (horizontal synchronization generation reference timing) field
+                    #1
+                  
+                  
+                    0
+                    Reference timing is the input horizontal synchronization signal (HSIN)
+                    #0
+                  
+                
+              
+              
+                INV
+                STVx signal polarity inversion control.
+                4
+                4
+                read-write
+                
+                  
+                    1
+                    Inverted
+                    #1
+                  
+                  
+                    0
+                    Not inverted
+                    #0
+                  
+                
+              
+              
+                SEL
+                Output signal select control for LCD_TCON2 (controlled by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 register) pin.
+                0
+                2
+                read-write
+                
+                  
+                    111
+                    DE
+                    #111
+                  
+                  
+                    110
+                    Setting prohibited
+                    #110
+                  
+                  
+                    101
+                    Setting prohibited
+                    #101
+                  
+                  
+                    100
+                    Setting prohibited
+                    #100
+                  
+                  
+                    011
+                    STHB
+                    #011
+                  
+                  
+                    010
+                    STHA
+                    #010
+                  
+                  
+                    001
+                    STVB
+                    #001
+                  
+                  
+                    000
+                    STVA
+                    #000
+                  
+                
+              
+            
+          
+          
+            DE
+            TCON Data Enable Polarity Setting Register
+            0x28
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                INV
+                DE signal polarity inversion control.
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Inverted
+                    #1
+                  
+                  
+                    0
+                    Not inverted
+                    #0
+                  
+                
+              
+            
+          
+        
+        
+          SYSCNT
+          GLCDC System Control Registers
+          0x1440
+          
+            DTCTEN
+            System control block State Detection Control Register
+            0x00
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                L2UNDFDTC
+                Graphics 2 underflow detection control
+                2
+                2
+                read-write
+                
+                  
+                    1
+                    Enables detection.
+                    #1
+                  
+                  
+                    0
+                    Disables detection.
+                    #0
+                  
+                
+              
+              
+                L1UNDFDTC
+                Graphics 1 underflow detection control
+                1
+                1
+                read-write
+                
+                  
+                    1
+                    Enables detection.
+                    #1
+                  
+                  
+                    0
+                    Disables detection.
+                    #0
+                  
+                
+              
+              
+                VPOSDTC
+                Specified line detection control
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Enables detection.
+                    #1
+                  
+                  
+                    0
+                    Disables detection.
+                    #0
+                  
+                
+              
+            
+          
+          
+            INTEN
+            System control block Interrupt Request Enable Control Register
+            0x04
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                L2UNDFINTEN
+                Interrupt request signal GLCDC_L2UNDF enable control.
+                2
+                2
+                read-write
+                
+                  
+                    1
+                    Enables GLCDC_L2UNDF output
+                    #1
+                  
+                  
+                    0
+                    Disables GLCDC_L2UNDF output
+                    #0
+                  
+                
+              
+              
+                L1UNDFINTEN
+                Interrupt request signal GLCDC_L1UNDF enable control.
+                1
+                1
+                read-write
+                
+                  
+                    1
+                    Enables GLCDC_L1UNDF output
+                    #1
+                  
+                  
+                    0
+                    Disables GLCDC_L1UNDF output
+                    #0
+                  
+                
+              
+              
+                VPOSINTEN
+                Interrupt request signal GLCDC_VPOS enable control.
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Enables GLCDC_VPOS output
+                    #1
+                  
+                  
+                    0
+                    Disables GLCDC_VPOS output
+                    #0
+                  
+                
+              
+            
+          
+          
+            STCLR
+            System control block Status Clear Register
+            0x08
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                L2UNDFCLR
+                Graphics 2 underflow detection flag clear field
+                2
+                2
+                read-write
+                
+                  
+                    1
+                    Clears the graphics 2 underflow detection flag.
+                    #1
+                  
+                  
+                    0
+                    No operation
+                    #0
+                  
+                
+              
+              
+                L1UNDFCLR
+                Graphics 1 underflow detection flag clear field
+                1
+                1
+                read-write
+                
+                  
+                    1
+                    Clears the graphics 1 underflow detection flag.
+                    #1
+                  
+                  
+                    0
+                    No operation
+                    #0
+                  
+                
+              
+              
+                VPOSCLR
+                Graphics 2 specified line detection flag clear field
+                0
+                0
+                read-write
+                
+                  
+                    1
+                    Clears the specified line detection flag.
+                    #1
+                  
+                  
+                    0
+                    No operation
+                    #0
+                  
+                
+              
+            
+          
+          
+            STMON
+            System control block Status Monitor Register
+            0x0c
+            32
+            read-only
+            0x00000000
+            0xFFFFFFFF
+            
+              
+                L2UNDF
+                Graphics 2 underflow detection flag
+                2
+                2
+                read-only
+                
+                  
+                    1
+                    An underflow has been detected in graphics 2.
+                    #1
+                  
+                  
+                    0
+                    No underflow has been detected in graphics 2.
+                    #0
+                  
+                
+              
+              
+                L1UNDF
+                Graphics 1 underflow detection flag
+                1
+                1
+                read-only
+                
+                  
+                    1
+                    An underflow has been detected in graphics 1.
+                    #1
+                  
+                  
+                    0
+                    No underflow has been detected in graphics 1.
+                    #0
+                  
+                
+              
+              
+                VPOS
+                Graphics 2 specified line detection flag
+                0
+                0
+                read-only
+                
+                  
+                    1
+                    A specified line notification has been detected in graphics 2.
+                    #1
+                  
+                  
+                    0
+                    No specified line notification has been detected in graphics 2.
+                    #0
+                  
+                
+              
+            
+          
+          
+            PANEL_CLK
+            System control block Version and Panel Clock Control Register
+            0x10
+            32
+            read-write
+            0x01000000
+            0xFFFFFFFF
+            
+              
+                VER
+                
+									Version information
+									Version information of the GLCDC
+								
+                16
+                31
+                read-only
+              
+              
+                PIXSEL
+                
+									Pixel clock select control.
+									Must be set to the same value as OUT_SET.FRQSEL[1].
+								
+                12
+                12
+                read-write
+                
+                  
+                    0
+                    No frequency division, parallel RGB
+                    #0
+                  
+                  
+                    1
+                    Quarter frequency,serial RGB
+                    #1
+                  
+                
+              
+              
+                CLKSEL
+                Panel clock supply source select
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    External clock select
+                    #0
+                  
+                  
+                    1
+                    PLL output select
+                    #1
+                  
+                
+              
+              
+                CLKEN
+                
+									Panel clock output enable control
+									Note: Before changing the PIXSEL,CLKSEL or DCDR bit, this bit must be set to 0.
+								
+                6
+                6
+                read-write
+                
+                  
+                    0
+                    Disable panel clock output 
+                    #0
+                  
+                  
+                    1
+                    Enable panel clock output 
+                    #1
+                  
+                
+              
+              
+                DCDR
+                
+									Clock division ratio setting control
+									Refer toTable 2.7.1 for details about setting value.
+									Note: Settings that are not listed in table 2.7.1 are prohibited.
+								
+                0
+                5
+                read-write
+              
+            
+          
+        
+        
+          256
+          0x4
+          GR1_CLUT0[%s]
+          Color Palette 0 Plane for Graphics 1 Plane
+          0x0000
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              A
+              Alpha Blending Value of Color Palette n Plane for Graphics m Plane
+              24
+              31
+              read-write
+            
+            
+              R
+              R Value of Color Palette n Plane for Graphics m Plane
+              16
+              23
+              read-write
+            
+            
+              G
+              G Value of Color Palette n Plane for Graphics m Plane
+              8
+              15
+              read-write
+            
+            
+              B
+              B Value of Color Palette n Plane for Graphics m Plane
+              0
+              7
+              read-write
+            
+          
+        
+        
+          GR1_CLUT1[%s]
+          Color Palette 1 Plane for Graphics 1 Plane
+          0x0400
+          
+        
+        
+          GR2_CLUT0[%s]
+          Color Palette 0 Plane for Graphics 2 Plane
+          0x0800
+          
+        
+        
+          GR2_CLUT1[%s]
+          Color Palette 1 Plane for Graphics 2 Plane
+          0x0C00
+          
+        
+      
+    
+    
+      R_GPT0
+      General PWM Timer
+      0x40078000
+      
+        0x00000000
+        0x0A4
+        registers
+      
+      
+        
+          GTWP
+          General PWM Timer Write-Protection Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PRKEY
+              GTWP Key Code
+              8
+              15
+              write-only
+              
+                
+                  0xA5
+                  Written to these bits, the WP bits write is permitted. 
+                  0xA5
+                
+                
+                  others
+                  The WP bits write is not permitted. 
+                  true
+                
+              
+            
+            
+              WP
+              Register Write Disable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Write to the register is enabled
+                  #0
+                
+                
+                  1
+                  Write to the register is disabled
+                  #1
+                
+              
+            
+          
+        
+        
+          GTSTR
+          General PWM Timer Software Start Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              14
+              1
+              CSTRT%s
+              Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No effect (write) / counter stop (read)
+                  #0
+                
+                
+                  1
+                  GTCNT counter starts (write) / Counter running (read)
+                  #1
+                
+              
+            
+          
+        
+        
+          GTSTP
+          General PWM Timer Software Stop Register
+          0x08
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              14
+              1
+              CSTOP%s
+              Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No effect (write) / counter running (read)
+                  #0
+                
+                
+                  1
+                  GPT GTCNT counter stops (write) / Counter stop (read)
+                  #1
+                
+              
+            
+          
+        
+        
+          GTCLR
+          General PWM Timer Software Clear Register
+          0x0C
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              14
+              1
+              CCLR%s
+              Channel GTCNT Count Clear
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No effect
+                  #0
+                
+                
+                  1
+                  GPT GTCNT counter clears
+                  #1
+                
+              
+            
+          
+        
+        
+          GTSSR
+          General PWM Timer Start Source Select Register
+          0x10
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CSTRT
+              Software Source Counter Start Enable
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Counter start is disable by the GTSTR register
+                  #0
+                
+                
+                  1
+                  Counter start is enable by the GTSTR register
+                  #1
+                
+              
+            
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              SSELC%s
+              ELC_GPT Event Source Counter Start Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the ELC_GPT input
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the ELC_GPT input
+                  #1
+                
+              
+            
+            
+              SSCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              SSCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              SSCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              SSCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              SSCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              SSCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              SSCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              SSCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              SSGTRG%sF
+              GTETRG Pin Falling Input Source Counter Start Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              SSGTRG%sR
+              GTETRG Pin Rising Input Source Counter Start Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Counter start is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter start is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTPSR
+          General PWM Timer Stop Source Select Register
+          0x14
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CSTOP
+              Software Source Counter Stop Enable
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Counter stop is disable by the GTSTP register
+                  #0
+                
+                
+                  1
+                  Counter stop is enable by the GTSTP register
+                  #1
+                
+              
+            
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              PSELC%s
+              ELC_GPTA Event Source Counter Stop Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the ELC_GPTA input
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the ELC_GPTA input
+                  #1
+                
+              
+            
+            
+              PSCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              PSCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              PSCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              PSCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              PSCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              PSCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              PSCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              PSCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              PSGTRG%sF
+              GTETRG Pin Falling Input Source Counter Stop Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              PSGTRG%sR
+              GTETRG Pin Rising Input Source Counter Stop Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Counter stop is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter stop is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTCSR
+          General PWM Timer Clear Source Select Register
+          0x18
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CCLR
+              Software Source Counter Clear Enable
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Counter clear is disable by the GTCLR register
+                  #0
+                
+                
+                  1
+                  Counter clear is enable by the GTCLR register
+                  #1
+                
+              
+            
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              CSELC%s
+              ELC_GPTA Event Source Counter Clear Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the ELC_GPTA input
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the ELC_GPTA input
+                  #1
+                
+              
+            
+            
+              CSCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              CSCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              CSCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              CSCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              CSCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              CSCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              CSCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              CSCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              CSGTRG%sF
+              GTETRG Pin Falling Input Source Counter Clear Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              CSGTRG%sR
+              GTETRG Pin Rising Input Source Counter Clear Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Counter clear is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter clear is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTUPSR
+          General PWM Timer Up Count Source Select Register
+          0x1C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              USELC%s
+              ELC_GPT Event Source Counter Count Up Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the ELC_GPT input
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the ELC_GPT input
+                  #1
+                
+              
+            
+            
+              USCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              USCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              USCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              USCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              USCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              USCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              USCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              USCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              USGTRG%sF
+              GTETRG Pin Falling Input Source Counter Count Up Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              USGTRG%sR
+              GTETRG Pin Rising Input Source Counter Count Up Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Counter count up is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter count up is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTDNSR
+          General PWM Timer Down Count Source Select Register
+          0x20
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              DSELC%s
+              ELC_GPT Event Source Counter Count Down Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the ELC_GPT input
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the ELC_GPT input
+                  #1
+                
+              
+            
+            
+              DSCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              DSCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              DSCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              DSCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              DSCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              DSCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              DSCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              DSCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              DSGTRG%sF
+              GTETRG Pin Falling Input Source Counter Count Down Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              DSGTRG%sR
+              GTETRG Pin Rising Input Source Counter Count Down Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Counter count down is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  Counter count down is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTICASR
+          General PWM Timer Input Capture Source Select Register A
+          0x24
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              ASELC%s
+              ELC_GPT Event Source GTCCRA Input Capture Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the ELC_GPT input
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the ELC_GPT input
+                  #1
+                
+              
+            
+            
+              ASCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              ASCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              ASCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              ASCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              ASCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              ASCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              ASCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              ASCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              ASGTRG%sF
+              GTETRG Pin Falling Input Source GTCCRA Input Capture Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              ASGTRG%sR
+              GTETRG Pin Rising Input Source GTCCRA Input Capture Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  GTCCRA input capture is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  GTCCRA input capture is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTICBSR
+          General PWM Timer Input Capture Source Select Register B
+          0x28
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              8
+              1
+              A,B,C,D,E,F,G,H
+              BSELC%s
+              ELC_GPT Event Source GTCCRB Input Capture Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the ELC_GPT input
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the ELC_GPT input
+                  #1
+                
+              
+            
+            
+              BSCBFAH
+              GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              BSCBFAL
+              GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              BSCBRAH
+              GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1
+                  #1
+                
+              
+            
+            
+              BSCBRAL
+              GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0
+                  #1
+                
+              
+            
+            
+              BSCAFBH
+              GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              BSCAFBL
+              GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              BSCARBH
+              GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1
+                  #1
+                
+              
+            
+            
+              BSCARBL
+              GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              BSGTRG%sF
+              GTETRG Pin Falling Input Source GTCCRB Input Capture Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the falling edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the falling edge of GTETRG input
+                  #1
+                
+              
+            
+            
+              4
+              2
+              A,B,C,D
+              BSGTRG%sR
+              GTETRG Pin Rising Input Source GTCCRB Input Capture Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  GTCCRB input capture is disable at the rising edge of GTETRG input
+                  #0
+                
+                
+                  1
+                  GTCCRB input capture is enable at the rising edge of GTETRG input
+                  #1
+                
+              
+            
+          
+        
+        
+          GTCR
+          General PWM Timer Control Register
+          0x2C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TPCS
+              Timer Prescaler Select
+              24
+              26
+              read-write
+              
+                
+                  0000
+                  PCLK/1
+                  #0000
+                
+                
+                  0001
+                  PCLK/2
+                  #0001
+                
+                
+                  0010
+                  PCLK/4
+                  #0010
+                
+                
+                  0011
+                  PCLK/8
+                  #0011
+                
+                
+                  0100
+                  PCLK/16
+                  #0100
+                
+                
+                  0101
+                  PCLK/32
+                  #0101
+                
+                
+                  0110
+                  PCLK/64
+                  #0110
+                
+                
+                  1000
+                  PCLK/256
+                  #1000
+                
+                
+                  1010
+                  PCLK/1024
+                  #1010
+                
+                
+                  1100
+                  GTETRGA
+                  #1100
+                
+                
+                  1101
+                  GTETRGB
+                  #1101
+                
+                
+                  1110
+                  GTETRGC
+                  #1110
+                
+                
+                  1111
+                  GTETRGD
+                  #1111
+                
+                
+                  others
+                  Setting prohibied
+                  true
+                
+              
+            
+            
+              MD
+              Mode Select
+              16
+              18
+              read-write
+              
+                
+                  000
+                  Saw-wave PWM mode (single buffer or double buffer possible)
+                  #000
+                
+                
+                  001
+                  Saw-wave one-shot pulse mode (fixed buffer operation)
+                  #001
+                
+                
+                  010
+                  Setting prohibited
+                  #010
+                
+                
+                  011
+                  Setting prohibited
+                  #011
+                
+                
+                  100
+                  Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible)
+                  #100
+                
+                
+                  101
+                  Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible)
+                  #101
+                
+                
+                  110
+                  Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation)
+                  #110
+                
+                
+                  111
+                  Setting prohibited
+                  #111
+                
+              
+            
+            
+              CST
+              Count Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Count operation is stopped
+                  #0
+                
+                
+                  1
+                  Count operation is performed
+                  #1
+                
+              
+            
+          
+        
+        
+          GTUDDTYC
+          General PWM Timer Count Direction and Duty Setting Register
+          0x30
+          32
+          read-write
+          0x00000001
+          0xFFFFFFFF
+          
+            
+              OBDTYR
+              GTIOCB Output Value Selecting after Releasing  0 percent/100 percent Duty Setting
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting.
+                  #0
+                
+                
+                  1
+                  Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting.
+                  #1
+                
+              
+            
+            
+              OBDTYF
+              Forcible GTIOCB Output Duty Setting
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Not forcibly set
+                  #0
+                
+                
+                  1
+                  Forcibly set
+                  #1
+                
+              
+            
+            
+              OBDTY
+              GTIOCB Output Duty Setting
+              24
+              25
+              read-write
+              
+                
+                  00
+                  GTIOCB pin duty is depend on compare match
+                  #00
+                
+                
+                  01
+                  GTIOCB pin duty is depend on compare match
+                  #01
+                
+                
+                  10
+                  GTIOCB pin duty 0 percent
+                  #10
+                
+                
+                  11
+                  GTIOCB pin duty 100 percent
+                  #11
+                
+              
+            
+            
+              OADTYR
+              GTIOCA Output Value Selecting after Releasing  0 percent/100 percent Duty Setting
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.
+                  #0
+                
+                
+                  1
+                  Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting.
+                  #1
+                
+              
+            
+            
+              OADTYF
+              Forcible GTIOCA Output Duty Setting
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Not forcibly set
+                  #0
+                
+                
+                  1
+                  Forcibly set
+                  #1
+                
+              
+            
+            
+              OADTY
+              GTIOCA Output Duty Setting
+              16
+              17
+              read-write
+              
+                
+                  00
+                  GTIOCA pin duty is depend on compare match
+                  #00
+                
+                
+                  01
+                  GTIOCA pin duty is depend on compare match
+                  #01
+                
+                
+                  10
+                  GTIOCA pin duty 0 percent
+                  #10
+                
+                
+                  11
+                  GTIOCA pin duty 100 percent
+                  #11
+                
+              
+            
+            
+              UDF
+              Forcible Count Direction Setting
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Not forcibly set
+                  #0
+                
+                
+                  1
+                  Forcibly set
+                  #1
+                
+              
+            
+            
+              UD
+              Count Direction Setting
+              0
+              0
+              read-write
+              
+                
+                  0
+                  GTCNT counts down.
+                  #0
+                
+                
+                  1
+                  GTCNT counts up.
+                  #1
+                
+              
+            
+          
+        
+        
+          GTIOR
+          General PWM Timer I/O Control Register
+          0x34
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              NFCSB
+              Noise Filter B Sampling Clock Select
+              30
+              31
+              read-write
+              
+                
+                  00
+                  PCLK/1
+                  #00
+                
+                
+                  01
+                  PCLK/4
+                  #01
+                
+                
+                  10
+                  PCLK/16
+                  #10
+                
+                
+                  11
+                  PCLK/64
+                  #11
+                
+              
+            
+            
+              NFBEN
+              Noise Filter B Enable
+              29
+              29
+              read-write
+              
+                
+                  0
+                  The noise filter for the GTIOCB pin is disabled.
+                  #0
+                
+                
+                  1
+                  The noise filter for the GTIOCB pin is enabled.
+                  #1
+                
+              
+            
+            
+              OBDF
+              GTIOCB Pin Disable Value Setting
+              25
+              26
+              read-write
+              
+                
+                  00
+                  Output disable is prohibited.
+                  #00
+                
+                
+                  01
+                  GTIOCB pin is set to Hi-Z when output disable is performed.
+                  #01
+                
+                
+                  10
+                  GTIOCB pin is set to 0 when output disable is performed.
+                  #10
+                
+                
+                  11
+                  GTIOCB pin is set to 1 when output disable is performed.
+                  #11
+                
+              
+            
+            
+              OBE
+              GTIOCB Pin Output Enable
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Output is disabled
+                  #0
+                
+                
+                  1
+                  Output is enabled
+                  #1
+                
+              
+            
+            
+              OBHLD
+              GTIOCB Pin Output Setting at the Start/Stop Count
+              23
+              23
+              read-write
+              
+                
+                  0
+                  The GTIOCB pin output level at start/stop of counting depends on the register setting.
+                  #0
+                
+                
+                  1
+                  The GTIOCB pin output level is retained at start/stop of counting.
+                  #1
+                
+              
+            
+            
+              OBDFLT
+              GTIOCB Pin Output Value Setting at the Count Stop
+              22
+              22
+              read-write
+              
+                
+                  0
+                  The GTIOCB pin outputs low when counting is stopped.
+                  #0
+                
+                
+                  1
+                  The GTIOCB pin outputs high when counting is stopped.
+                  #1
+                
+              
+            
+            
+              GTIOB
+              GTIOCB Pin Function Select
+              16
+              20
+              read-write
+              
+                
+                  00000
+                  Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match.
+                  #00000
+                
+                
+                  00001
+                  Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match.
+                  #00001
+                
+                
+                  00010
+                  Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match.
+                  #00010
+                
+                
+                  00011
+                  Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match.
+                  #00011
+                
+                
+                  00100
+                  Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match.
+                  #00100
+                
+                
+                  00101
+                  Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match.
+                  #00101
+                
+                
+                  00110
+                  Initial output is Low. Low output at cycle end. High output at GTCCRB compare match.
+                  #00110
+                
+                
+                  00111
+                  Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match.
+                  #00111
+                
+                
+                  01000
+                  Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match.
+                  #01000
+                
+                
+                  01001
+                  Initial output is Low. High output at cycle end. Low output at GTCCRB compare match.
+                  #01001
+                
+                
+                  01010
+                  Initial output is Low. High output at cycle end. High output at GTCCRB compare match.
+                  #01010
+                
+                
+                  01011
+                  Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match.
+                  #01011
+                
+                
+                  01100
+                  Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match.
+                  #01100
+                
+                
+                  01101
+                  Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match.
+                  #01101
+                
+                
+                  01110
+                  Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match.
+                  #01110
+                
+                
+                  01111
+                  Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match.
+                  #01111
+                
+                
+                  10000
+                  Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match.
+                  #10000
+                
+                
+                  10001
+                  Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match.
+                  #10001
+                
+                
+                  10010
+                  Initial output is High. Output retained at cycle end. High output at GTCCRB compare match.
+                  #10010
+                
+                
+                  10011
+                  Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match.
+                  #10011
+                
+                
+                  10100
+                  Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match.
+                  #10100
+                
+                
+                  10101
+                  Initial output is High. Low output at cycle end. Low output at GTCCRB compare match.
+                  #10101
+                
+                
+                  10110
+                  Initial output is High. Low output at cycle end. High output at GTCCRB compare match.
+                  #10110
+                
+                
+                  10111
+                  Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match.
+                  #10111
+                
+                
+                  11000
+                  Initial output is High. High output at cycle end. Output retained at GTCCRB compare match.
+                  #11000
+                
+                
+                  11001
+                  Initial output is High. High output at cycle end. Low output at GTCCRB compare match.
+                  #11001
+                
+                
+                  11010
+                  Initial output is High. High output at cycle end. High output at GTCCRB compare match.
+                  #11010
+                
+                
+                  11011
+                  Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match.
+                  #11011
+                
+                
+                  11100
+                  Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match.
+                  #11100
+                
+                
+                  11101
+                  Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match.
+                  #11101
+                
+                
+                  11110
+                  Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match.
+                  #11110
+                
+                
+                  11111
+                  Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match.
+                  #11111
+                
+              
+            
+            
+              NFCSA
+              Noise Filter A Sampling Clock Select
+              14
+              15
+              read-write
+              
+                
+                  00
+                  PCLK/1
+                  #00
+                
+                
+                  01
+                  PCLK/4
+                  #01
+                
+                
+                  10
+                  PCLK/16
+                  #10
+                
+                
+                  11
+                  PCLK/64
+                  #11
+                
+              
+            
+            
+              NFAEN
+              Noise Filter A Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  The noise filter for the GTIOCA pin is disabled.
+                  #0
+                
+                
+                  1
+                  The noise filter for the GTIOCA pin is enabled.
+                  #1
+                
+              
+            
+            
+              OADF
+              GTIOCA Pin Disable Value Setting
+              9
+              10
+              read-write
+              
+                
+                  00
+                  Output disable is prohibited.
+                  #00
+                
+                
+                  01
+                  GTIOCA pin is set to Hi-Z when output disable is performed.
+                  #01
+                
+                
+                  10
+                  GTIOCA pin is set to 0 when output disable is performed.
+                  #10
+                
+                
+                  11
+                  GTIOCA pin is set to 1 when output disable is performed.
+                  #11
+                
+              
+            
+            
+              OAE
+              GTIOCA Pin Output Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Output is disabled
+                  #0
+                
+                
+                  1
+                  Output is enabled
+                  #1
+                
+              
+            
+            
+              OAHLD
+              GTIOCA Pin Output Setting at the Start/Stop Count
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The GTIOCA pin output level at start/stop of counting depends on the register setting.
+                  #0
+                
+                
+                  1
+                  The GTIOCA pin output level is retained at start/stop of counting.
+                  #1
+                
+              
+            
+            
+              OADFLT
+              GTIOCA Pin Output Value Setting at the Count Stop
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The GTIOCA pin outputs low when counting is stopped.
+                  #0
+                
+                
+                  1
+                  The GTIOCA pin outputs high when counting is stopped.
+                  #1
+                
+              
+            
+            
+              GTIOA
+              GTIOCA Pin Function Select
+              0
+              4
+              read-write
+              
+                
+                  00000
+                  Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match.
+                  #00000
+                
+                
+                  00001
+                  Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match.
+                  #00001
+                
+                
+                  00010
+                  Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match.
+                  #00010
+                
+                
+                  00011
+                  Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match.
+                  #00011
+                
+                
+                  00100
+                  Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match.
+                  #00100
+                
+                
+                  00101
+                  Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match.
+                  #00101
+                
+                
+                  00110
+                  Initial output is Low. Low output at cycle end. High output at GTCCRA compare match.
+                  #00110
+                
+                
+                  00111
+                  Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match.
+                  #00111
+                
+                
+                  01000
+                  Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match.
+                  #01000
+                
+                
+                  01001
+                  Initial output is Low. High output at cycle end. Low output at GTCCRA compare match.
+                  #01001
+                
+                
+                  01010
+                  Initial output is Low. High output at cycle end. High output at GTCCRA compare match.
+                  #01010
+                
+                
+                  01011
+                  Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match.
+                  #01011
+                
+                
+                  01100
+                  Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match.
+                  #01100
+                
+                
+                  01101
+                  Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match.
+                  #01101
+                
+                
+                  01110
+                  Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match.
+                  #01110
+                
+                
+                  01111
+                  Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match.
+                  #01111
+                
+                
+                  10000
+                  Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match.
+                  #10000
+                
+                
+                  10001
+                  Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match.
+                  #10001
+                
+                
+                  10010
+                  Initial output is High. Output retained at cycle end. High output at GTCCRA compare match.
+                  #10010
+                
+                
+                  10011
+                  Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match.
+                  #10011
+                
+                
+                  10100
+                  Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match.
+                  #10100
+                
+                
+                  10101
+                  Initial output is High. Low output at cycle end. Low output at GTCCRA compare match.
+                  #10101
+                
+                
+                  10110
+                  Initial output is High. Low output at cycle end. High output at GTCCRA compare match.
+                  #10110
+                
+                
+                  10111
+                  Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match.
+                  #10111
+                
+                
+                  11000
+                  Initial output is High. High output at cycle end. Output retained at GTCCRA compare match.
+                  #11000
+                
+                
+                  11001
+                  Initial output is High. High output at cycle end. Low output at GTCCRA compare match.
+                  #11001
+                
+                
+                  11010
+                  Initial output is High. High output at cycle end. High output at GTCCRA compare match.
+                  #11010
+                
+                
+                  11011
+                  Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match.
+                  #11011
+                
+                
+                  11100
+                  Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match.
+                  #11100
+                
+                
+                  11101
+                  Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match.
+                  #11101
+                
+                
+                  11110
+                  Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match.
+                  #11110
+                
+                
+                  11111
+                  Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match.
+                  #11111
+                
+              
+            
+          
+        
+        
+          GTINTAD
+          General PWM Timer Interrupt Output Setting Register
+          0x38
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GRPABL
+              Same Time Output Level Low Disable Request Enable
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Same time output level low disable request is disabled.
+                  #0
+                
+                
+                  1
+                  Same time output level low disable request is enabled.
+                  #1
+                
+              
+            
+            
+              GRPABH
+              Same Time Output Level High Disable Request Enable
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Same time output level high disable request is disabled.
+                  #0
+                
+                
+                  1
+                  Same time output level high disable request is enabled.
+                  #1
+                
+              
+            
+            
+              GRPDTE
+              Dead Time Error Output Disable Request Enable
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Disable dead time error output disable request
+                  #0
+                
+                
+                  1
+                  Enable dead time error output disable request
+                  #1
+                
+              
+            
+            
+              GRP
+              Output Disable Source Select
+              24
+              25
+              read-write
+              
+                
+                  00
+                  Group A output disable request
+                  #00
+                
+                
+                  01
+                  Group B output disable request
+                  #01
+                
+                
+                  10
+                  Group C output disable request
+                  #10
+                
+                
+                  11
+                  Group D output disable request
+                  #11
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          GTST
+          General PWM Timer Status Register
+          0x3C
+          32
+          read-write
+          0x00008000
+          0xFFFFFFFF
+          
+            
+              OABLF
+              Same Time Output Level Low Disable Request Enable
+              30
+              30
+              read-only
+              
+                
+                  0
+                  GTIOCA pin and GTIOCB pin don't output 0 at the same time.
+                  #0
+                
+                
+                  1
+                  GTIOCA pin and GTIOCB pin output 0 at the same time.
+                  #1
+                
+              
+            
+            
+              OABHF
+              Same Time Output Level High Disable Request Enable
+              29
+              29
+              read-only
+              
+                
+                  0
+                  GTIOCA pin and GTIOCB pin don't output 1 at the same time.
+                  #0
+                
+                
+                  1
+                  GTIOCA pin and GTIOCB pin output 1 at the same time.
+                  #1
+                
+              
+            
+            
+              DTEF
+              Dead Time Error Flag
+              28
+              28
+              read-only
+              
+                
+                  0
+                  No dead time error has occurred.
+                  #0
+                
+                
+                  1
+                  A dead time error has occurred.
+                  #1
+                
+              
+            
+            
+              ODF
+              Output Disable Flag
+              24
+              24
+              read-only
+              
+                
+                  0
+                  No output disable request is generated.
+                  #0
+                
+                
+                  1
+                  An output disable request is generated.
+                  #1
+                
+              
+            
+            
+              ADTRBDF
+              GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag
+              19
+              19
+              read-write
+              
+                
+                  0
+                  No compare match of GTADTRB at down-counting is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTADTRB at down-counting is generated.
+                  #1
+                
+              
+            
+            
+              ADTRBUF
+              GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag
+              18
+              18
+              read-write
+              
+                
+                  0
+                  No compare match of GTADTRB at up-counting is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTADTRB at up-counting is generated.
+                  #1
+                
+              
+            
+            
+              ADTRADF
+              GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag
+              17
+              17
+              read-write
+              
+                
+                  0
+                  No compare match of GTADTRA at down-counting is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTADTRA at down-counting is generated.
+                  #1
+                
+              
+            
+            
+              ADTRAUF
+              GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  No compare match of GTADTRA at up-counting is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTADTRA at up-counting is generated.
+                  #1
+                
+              
+            
+            
+              TUCF
+              Count Direction Flag
+              15
+              15
+              read-only
+              
+                
+                  0
+                  The GTCNT counter counts downward.
+                  #0
+                
+                
+                  1
+                  The GTCNT counter counts upward.
+                  #1
+                
+              
+            
+            
+              ITCNT
+              GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.)
+              8
+              10
+              read-only
+            
+            
+              TCFPU
+              Underflow Flag
+              7
+              7
+              read-write
+              
+                
+                  0
+                  No underflow (trough) has occurred.
+                  #0
+                
+                
+                  1
+                  An underflow (trough) has occurred.
+                  #1
+                
+              
+            
+            
+              TCFPO
+              Overflow Flag
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No overflow (crest) has occurred.
+                  #0
+                
+                
+                  1
+                  An overflow (crest) has occurred.
+                  #1
+                
+              
+            
+            
+              TCFF
+              Input Compare Match Flag F
+              5
+              5
+              read-write
+              
+                
+                  0
+                  No compare match of GTCCRF is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTCCRF is generated.
+                  #1
+                
+              
+            
+            
+              TCFE
+              Input Compare Match Flag E
+              4
+              4
+              read-write
+              
+                
+                  0
+                  No compare match of GTCCRE is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTCCRE is generated.
+                  #1
+                
+              
+            
+            
+              TCFD
+              Input Compare Match Flag D
+              3
+              3
+              read-write
+              
+                
+                  0
+                  No compare match of GTCCRD is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTCCRD is generated.
+                  #1
+                
+              
+            
+            
+              TCFC
+              Input Compare Match Flag C
+              2
+              2
+              read-write
+              
+                
+                  0
+                  No compare match of GTCCRC is generated.
+                  #0
+                
+                
+                  1
+                  A compare match of GTCCRC is generated.
+                  #1
+                
+              
+            
+            
+              TCFB
+              Input Capture/Compare Match Flag B
+              1
+              1
+              read-write
+              
+                
+                  0
+                  No input capture/compare match of GTCCRB is generated.
+                  #0
+                
+                
+                  1
+                  An input capture/compare match of GTCCRB is generated.
+                  #1
+                
+              
+            
+            
+              TCFA
+              Input Capture/Compare Match Flag A
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No input capture/compare match of GTCCRA is generated.
+                  #0
+                
+                
+                  1
+                  An input capture/compare match of GTCCRA is generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          GTBER
+          General PWM Timer Buffer Enable Register
+          0x40
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ADTDB
+              GTADTRB Double Buffer Operation
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Single buffer operation (GTADTBRB --> GTADTRB) 
+                  #0
+                
+                
+                  1
+                  Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB)
+                  #1
+                
+              
+            
+            
+              ADTTB
+              GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.
+              28
+              29
+              read-write
+              
+                
+                  00
+                  No transfer
+                  #00
+                
+                
+                  01
+                  Transfer at crest
+                  #01
+                
+                
+                  10
+                  Transfer at trough
+                  #10
+                
+                
+                  11
+                  Transfer at both crest and trough
+                  #11
+                
+              
+            
+            
+              ADTDA
+              GTADTRA Double Buffer Operation
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Single buffer operation (GTADTBRA --> GTADTRA)
+                  #0
+                
+                
+                  1
+                  Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA)
+                  #1
+                
+              
+            
+            
+              ADTTA
+              GTADTRA Buffer Transfer Timing Select  in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.
+              24
+              25
+              read-write
+              
+                
+                  00
+                  No transfer
+                  #00
+                
+                
+                  01
+                  Transfer at crest
+                  #01
+                
+                
+                  10
+                  Transfer at trough
+                  #10
+                
+                
+                  11
+                  Transfer at both crest and trough
+                  #11
+                
+              
+            
+            
+              CCRSWT
+              GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0.
+              22
+              22
+              write-only
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. 
+                  #1
+                
+              
+            
+            
+              PR
+              GTPR Buffer Operation
+              20
+              21
+              read-write
+              
+                
+                  00
+                  Buffer operation is not performed
+                  #00
+                
+                
+                  01
+                  Single buffer operation (GTPBR --> GTPR)
+                  #01
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              CCRB
+              GTCCRB Buffer Operation
+              18
+              19
+              read-write
+              
+                
+                  00
+                  Buffer operation is not performed
+                  #00
+                
+                
+                  01
+                  Single buffer operation (GTCCRB <--> GTCCRE)
+                  #01
+                
+                
+                  10
+                  Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)
+                  #10
+                
+                
+                  11
+                  Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF)
+                  #11
+                
+              
+            
+            
+              CCRA
+              GTCCRA Buffer Operation
+              16
+              17
+              read-write
+              
+                
+                  00
+                  Buffer operation is not performed
+                  #00
+                
+                
+                  01
+                  Single buffer operation (GTCCRA <--> GTCCRC)
+                  #01
+                
+                
+                  10
+                  Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)
+                  #10
+                
+                
+                  11
+                  Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD)
+                  #11
+                
+              
+            
+            
+              BD3
+              BD[3]: GTDV Buffer Operation DisableBD[2]
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Enable buffer operation
+                  #0
+                
+                
+                  1
+                  Disable buffer operation
+                  #1
+                
+              
+            
+            
+              BD2
+              BD[2]: GTADTR Buffer Operation DisableBD
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Enable buffer operation
+                  #0
+                
+                
+                  1
+                  Disable buffer operation
+                  #1
+                
+              
+            
+            
+              BD1
+              BD[1]: GTPR Buffer Operation Disable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Buffer operation is enabled
+                  #0
+                
+                
+                  1
+                  Buffer operation is disabled
+                  #1
+                
+              
+            
+            
+              BD0
+              BD[0]: GTCCR Buffer Operation Disable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Buffer operation is enabled
+                  #0
+                
+                
+                  1
+                  Buffer operation is disabled
+                  #1
+                
+              
+            
+          
+        
+        
+          GTITC
+          General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register
+          0x44
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ADTBL
+              GTADTRB A/D Converter Start Request Link
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ADTAL
+              GTADTRA A/D Converter Start Request Link
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #1
+                
+              
+            
+            
+              IVTT
+              GPT_OVF/GPT_UDF Interrupt Skipping Count Select
+              8
+              10
+              read-write
+              
+                
+                  000
+                  No skipping
+                  #000
+                
+                
+                  001
+                  Skipping count of 1
+                  #001
+                
+                
+                  010
+                  Skipping count of 2
+                  #010
+                
+                
+                  011
+                  Skipping count of 3
+                  #011
+                
+                
+                  100
+                  Skipping count of 4
+                  #100
+                
+                
+                  101
+                  Skipping count of 5
+                  #101
+                
+                
+                  110
+                  Skipping count of 6
+                  #110
+                
+                
+                  111
+                  Skipping count of 7.
+                  #111
+                
+              
+            
+            
+              IVTC
+              GPT_OVF/GPT_UDF Interrupt Skipping Function Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Do not perform skipping
+                  #00
+                
+                
+                  01
+                  Count and skip both overflow and underflow for saw waves and crest for triangle waves
+                  #01
+                
+                
+                  10
+                  Count and skip both overflow and underflow for saw waves and trough for triangle waves
+                  #10
+                
+                
+                  11
+                  Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves.
+                  #11
+                
+              
+            
+            
+              ITLF
+              GTCCRF Compare Match Interrupt Link
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ITLE
+              GTCCRE Compare Match Interrupt Link
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ITLD
+              GTCCRD Compare Match Interrupt Link
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ITLC
+              GTCCRC Compare Match Interrupt Link
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ITLB
+              GTCCRB Compare Match/Input Capture Interrupt Link
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+            
+              ITLA
+              GTCCRA Compare Match/Input Capture Interrupt Link
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function
+                  #0
+                
+                
+                  1
+                  Link with GPTn_OVF/GPTn_UDF interrupt skipping function.
+                  #1
+                
+              
+            
+          
+        
+        
+          GTCNT
+          General PWM Timer Counter
+          0x48
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              GTCNT
+              Counter 
+              0
+              31
+              read-write
+            
+          
+        
+        
+          6
+          4
+          
+            
+              A
+              A
+              0
+            
+            
+              B
+              B
+              1
+            
+            
+              C
+              C
+              2
+            
+            
+              E
+              E
+              3
+            
+            
+              D
+              D
+              4
+            
+            
+              F
+              F
+              5
+            
+          
+          GTCCR[%s]
+          General PWM Timer Compare Capture Register
+          0x4C
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTCCR
+              Compare Capture Register A
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTPR
+          General PWM Timer Cycle Setting Register
+          0x64
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTPR
+              Cycle Setting Register
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTPBR
+          General PWM Timer Cycle Setting Buffer Register
+          0x68
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTPBR
+              Cycle Setting Buffer Register
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTPDBR
+          General PWM Timer Cycle Setting Double-Buffer Register
+          0x6C
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTPDBR
+              Cycle Setting Double-Buffer Register
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTRA
+          A/D Converter Start Request Timing Register A
+          0x70
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTRA
+              A/D Converter Start Request Timing Register A
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTRB
+          A/D Converter Start Request Timing Register B
+          0x7C
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTRB
+              A/D Converter Start Request Timing Register B
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTBRA
+          A/D Converter Start Request Timing Buffer Register A
+          0x74
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTBRA
+              A/D Converter Start Request Timing Buffer Register A
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTBRB
+          A/D Converter Start Request Timing Buffer Register B
+          0x80
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTBRB
+              A/D Converter Start Request Timing Buffer Register B
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTDBRA
+          A/D Converter Start Request Timing Double-Buffer Register A
+          0x78
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTDBRA
+              A/D Converter Start Request Timing Double-Buffer Register A
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTADTDBRB
+          A/D Converter Start Request Timing Double-Buffer Register B
+          0x84
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTADTDBRB
+              A/D Converter Start Request Timing Double-Buffer Register B
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTDTCR
+          General PWM Timer Dead Time Control Register
+          0x88
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              TDFER
+              GTDVD Setting
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Set GTDVU and GTDVD separately
+                  #0
+                
+                
+                  1
+                  Automatically set the value written to GTDVU to GTDVD
+                  #1
+                
+              
+            
+            
+              TDBDE
+              GTDVD Buffer Operation Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disable GTDVD buffer operation
+                  #0
+                
+                
+                  1
+                  Enable GTDVD buffer operation
+                  #1
+                
+              
+            
+            
+              TDBUE
+              GTDVU Buffer Operation Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disable GTDVU buffer operation
+                  #0
+                
+                
+                  1
+                  Enable GTDVU buffer operation
+                  #1
+                
+              
+            
+            
+              TDE
+              Negative-Phase Waveform Setting
+              0
+              0
+              read-write
+              
+                
+                  0
+                  GTCCRB is set without using GTDVU and GTDVD.
+                  #0
+                
+                
+                  1
+                  GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB.
+                  #1
+                
+              
+            
+          
+        
+        
+          GTDVU
+          General PWM Timer Dead Time Value Register U
+          0x8C
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTDVU
+              Dead Time Value Register U
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTDVD
+          General PWM Timer Dead Time Value Register D
+          0x90
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTDVD
+              Dead Time Value Register D
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTDBU
+          General PWM Timer Dead Time Buffer Register U
+          0x94
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTDVU
+              Dead Time Buffer Register U
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTDBD
+          General PWM Timer Dead Time Buffer Register D
+          0x98
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              GTDBD
+              Dead Time Buffer Register D
+              0
+              31
+              read-write
+            
+          
+        
+        
+          GTSOS
+          General PWM Timer Output Protection Function Status Register
+          0x9C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SOS
+              Output Protection Function Status
+              0
+              1
+              read-only
+              
+                
+                  00
+                  Normal operation
+                  #00
+                
+                
+                  01
+                  Protected state (GTCCRA = 0 is set during transfer at trough or crest)
+                  #01
+                
+                
+                  10
+                  Protected state (GTCCRA >= GTPR is set during transfer at trough)
+                  #10
+                
+                
+                  11
+                  Protected state (GTCCRA >= GTPR is set during transfer at crest)
+                  #11
+                
+              
+            
+          
+        
+        
+          GTSOTR
+          General PWM Timer Output Protection Function Temporary Release Register
+          0xA0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SOTR
+              Output Protection Function Temporary Release
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not release protected state
+                  #0
+                
+                
+                  1
+                  Release protected state
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_GPT1
+      0x40078100
+    
+    
+      R_GPT2
+      0x40078200
+    
+    
+      R_GPT3
+      0x40078300
+    
+    
+      R_GPT4
+      0x40078400
+    
+    
+      R_GPT5
+      0x40078500
+    
+    
+      R_GPT6
+      0x40078600
+    
+    
+      R_GPT7
+      0x40078700
+    
+    
+      R_GPT8
+      0x40078800
+    
+    
+      R_GPT9
+      0x40078900
+    
+    
+      R_GPT10
+      0x40078A00
+    
+    
+      R_GPT11
+      0x40078B00
+    
+    
+      R_GPT12
+      0x40078C00
+    
+    
+      R_GPT13
+      0x40078D00
+    
+    
+      R_GPT_ODC
+      PWM Delay Generation Circuit
+      0x4007B000
+      
+        0x00000000
+        0x004
+        registers
+      
+      
+        0x00000018
+        0x020
+        registers
+      
+      
+        
+          4
+          4
+          GTDLYR[%s]
+          PWM DELAY RISING
+          0x18
+          
+            A
+            GTIOCA Output Delay Register
+            0
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                DLY
+                GTIOCnA Output Rising Edge Delay Setting
+                0
+                4
+                read-write
+                
+                  
+                    00000
+                    No delay on rising edges
+                    #00000
+                  
+                  
+                    others
+                    Delay of DLY/32 times the PCLKD period is applied.
+                    true
+                  
+                
+              
+            
+          
+          
+            B
+            GTIOCB Output Delay Register
+            2
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                DLY
+                GTIOCnA Output Rising Edge Delay Setting
+                0
+                4
+                read-write
+                
+                  
+                    00000
+                    No delay on rising edges
+                    #00000
+                  
+                  
+                    others
+                    Delay of DLY/32 times the PCLKD period is applied.
+                    true
+                  
+                
+              
+            
+          
+        
+        
+          GTDLYF[%s]
+          PWM DELAY FALLING
+          0x28
+        
+        
+          GTDLYCR1
+          PWM Output Delay Control Register1
+          0x00
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DLLMOD
+              DLL Mode Select
+              8
+              8
+              read-write
+              
+                
+                  0
+                  5 bit-mode
+                  #0
+                
+                
+                  1
+                  4 bit-mode
+                  #1
+                
+              
+            
+            
+              DLYRST
+              PWM Delay Generation Circuit Reset
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Normal operation
+                  #0
+                
+                
+                  1
+                  Reset
+                  #1
+                
+              
+            
+            
+              DLLEN
+              DLL Operation Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  DLL operation is disabled
+                  #0
+                
+                
+                  1
+                  DLL operation is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          GTDLYCR2
+          PWM Output Delay Control Register2
+          0x02
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              1
+              1
+              DLYDENB%s
+              PWM Delay Generation Circuit Disenable for GTIOCB
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Delay generation circuit of GTIOCB is based on DLYEN1.
+                  #0
+                
+                
+                  1
+                  Delay generation circuit of GTIOCB is disabled.
+                  #1
+                
+              
+            
+            
+              1
+              1
+              DLYEN%s
+              PWM Delay Generation Circuit enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Delay generation circuit of channel is enabled
+                  #0
+                
+                
+                  1
+                  Delay generation circuit of channel is disabled.
+                  #1
+                
+              
+            
+            
+              4
+              1
+              DLYBS%s
+              PWM Delay Generation Circuit bypass
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Delay generation circuit of channel is bypassed.
+                  #0
+                
+                
+                  1
+                  Delay generation circuit of channel is not bypassed.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_GPT_OPS
+      Output Phase Switching for GPT
+      0x40078FF0
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        
+          OPSCR
+          Output Phase Switching Control Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              NFCS
+              External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input.
+              30
+              31
+              read-write
+              
+                
+                  00
+                  PCLK/1 
+                  #00
+                
+                
+                  01
+                  PCLK/4 
+                  #01
+                
+                
+                  10
+                  PCLK/16
+                  #10
+                
+                
+                  11
+                  PCLK/64
+                  #11
+                
+              
+            
+            
+              NFEN
+              External Input Noise Filter Enable
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Do not use a noise filter to the external input.
+                  #0
+                
+                
+                  1
+                  Use a noise filter to the external input.
+                  #1
+                
+              
+            
+            
+              GODF
+              Group output disable function
+              26
+              26
+              read-write
+              
+                
+                  0
+                  This bit function is ignored.
+                  #0
+                
+                
+                  1
+                  Group disable will clear OPSCR.EN Bit.
+                  #1
+                
+              
+            
+            
+              GRP
+              Output disabled source selection
+              24
+              25
+              read-write
+              
+                
+                  00
+                  Select Group A output disable source
+                  #00
+                
+                
+                  01
+                  Select Group B output disable source
+                  #01
+                
+                
+                  10
+                  Select Group C output disable source
+                  #10
+                
+                
+                  11
+                  Select Group D output disable source
+                  #11
+                
+              
+            
+            
+              ALIGN
+              Input phase alignment
+              21
+              21
+              read-write
+              
+                
+                  0
+                  Input phase is aligned to PCLK.
+                  #0
+                
+                
+                  1
+                  Input phase is aligned PWM.
+                  #1
+                
+              
+            
+            
+              RV
+              Output phase rotation direction reversal
+              20
+              20
+              read-write
+              
+                
+                  0
+                  U/V/W-Phase output
+                  #0
+                
+                
+                  1
+                  Output to reverse the V / W-phase
+                  #1
+                
+              
+            
+            
+              INV
+              Invert-Phase Output Control
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Positive Logic (Active High)output
+                  #0
+                
+                
+                  1
+                  Negative Logic (Active Low)output
+                  #1
+                
+              
+            
+            
+              N
+              Negative-Phase Output (N) Control
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Level signal output
+                  #0
+                
+                
+                  1
+                  PWM signal output (PWM of GPT0)
+                  #1
+                
+              
+            
+            
+              P
+              Positive-Phase Output (P) Control
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Level signal output
+                  #0
+                
+                
+                  1
+                  PWM signal output (PWM of GPT0)
+                  #1
+                
+              
+            
+            
+              FB
+              External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. 
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Select the external input.
+                  #0
+                
+                
+                  1
+                  Select the soft setting(OPSCR.UF, VF, WF).
+                  #1
+                
+              
+            
+            
+              EN
+              Enable-Phase Output Control
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Not Output(Hi-Z external terminals).
+                  #0
+                
+                
+                  1
+                  Output
+                  #1
+                
+              
+            
+            
+              W
+              Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 
+              6
+              6
+              read-only
+            
+            
+              V
+              Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 
+              5
+              5
+              read-only
+            
+            
+              U
+              Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)
+              4
+              4
+              read-only
+            
+            
+              WF
+              Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 
+              2
+              2
+              read-write
+            
+            
+              VF
+              Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 
+              1
+              1
+              read-write
+            
+            
+              UF
+              Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 
+              0
+              0
+              read-write
+            
+          
+        
+      
+    
+    
+      R_GPT_POEG0
+      Port Output Enable for GPT
+      0x40042000
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        
+          POEGG
+          POEG Group Setting Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              NFCS
+              Noise Filter Clock Select
+              30
+              31
+              read-write
+              
+                
+                  00
+                  Sampling GTETRG pin input level for three times in every PCLKB. 
+                  #00
+                
+                
+                  01
+                  Sampling GTETRG pin input level for three times in every PCLKB /8.
+                  #01
+                
+                
+                  10
+                  Sampling GTETRG pin input level for three times in every PCLKB /32.
+                  #10
+                
+                
+                  11
+                  Sampling GTETRG pin input level for three times in every PCLKB /128. 
+                  #11
+                
+              
+            
+            
+              NFEN
+              Noise Filter Enable
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Filtering noise disabled
+                  #0
+                
+                
+                  1
+                  Filtering noise enabled 
+                  #1
+                
+              
+            
+            
+              INV
+              GTETRG Input Reverse
+              28
+              28
+              read-write
+              
+                
+                  0
+                  GTETRG Input
+                  #0
+                
+                
+                  1
+                  GTETRG Input Reversed.
+                  #1
+                
+              
+            
+            
+              ST
+              GTETRG Input Status Flag
+              16
+              16
+              read-only
+              
+                
+                  0
+                  GTETRG input after filtering is 0.
+                  #0
+                
+                
+                  1
+                  GTETRG input after filtering is 1. 
+                  #1
+                
+              
+            
+            
+              6
+              1
+              CDRE%s
+              Comparator Disable Request Enable. Note: Can be modified only once after a reset.
+              8
+              8
+              read-write
+              
+                
+                  0
+                  A disable request of comparator 0 disabled.
+                  #0
+                
+                
+                  1
+                  A disable request of comparator 0 enabled. 
+                  #1
+                
+              
+            
+            
+              OSTPE
+              Oscillation Stop Detection EnableNote: Can be modified only once after a reset.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  A output-disable request from the oscillation stop detection disabled. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from the oscillation stop detection enabled.   
+                  #1
+                
+              
+            
+            
+              IOCE
+              Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disable output-disable requests from GPT disable request
+                  #0
+                
+                
+                  1
+                  Enable output-disable requests from GPT disable request
+                  #1
+                
+              
+            
+            
+              PIDE
+              Port Input Detection EnableNote: Can be modified only once after a reset.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  A output-disable request from the GTETRG pins disabled. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from the GTETRG pins enabled. 
+                  #1
+                
+              
+            
+            
+              SSF
+              Software Stop Flag
+              3
+              3
+              read-write
+              
+                
+                  0
+                  A output-disable request from software has not been generated. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from software has been generated. 
+                  #1
+                
+              
+            
+            
+              OSTPF
+              Oscillation Stop Detection Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  A output-disable request from the oscillation stop detection has not been generated. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from the oscillation stop detection has been generated. 
+                  #1
+                
+              
+            
+            
+              IOCF
+              Real Time Overcurrent Detection Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  A output-disable request from GPT disable request or comparator interrupt has not been generated. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from GPT disable request or comparator interrupt has been generated.
+                  #1
+                
+              
+            
+            
+              PIDF
+              Port Input Detection Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  A output-disable request from the GTETRG pin has not been generated. 
+                  #0
+                
+                
+                  1
+                  A output-disable request from the GTETRG pin has been generated.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_GPT_POEG1
+      0x40042100
+    
+    
+      R_GPT_POEG2
+      0x40042200
+    
+    
+      R_GPT_POEG3
+      0x40042300
+    
+    
+      R_ICU
+      Interrupt Controller Unit
+      0x40006000
+      
+        0x00000000
+        0x010
+        registers
+      
+      
+        0x00000100
+        0x01
+        registers
+      
+      
+        0x00000120
+        0x02
+        registers
+      
+      
+        0x00000130
+        0x02
+        registers
+      
+      
+        0x00000140
+        0x02
+        registers
+      
+      
+        0x000001A0
+        0x04
+        registers
+      
+      
+        0x00000200
+        0x02
+        registers
+      
+      
+        0x00000280
+        0x020
+        registers
+      
+      
+        0x00000300
+        0x180
+        registers
+      
+      
+        
+          16
+          0x1
+          IRQCR[%s]
+          IRQ Control Register %s
+          0x000
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              FLTEN
+              IRQ Digital Filter Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Digital filter disabled.
+                  #0
+                
+                
+                  1
+                  Digital filter enabled.
+                  #1
+                
+              
+            
+            
+              FCLKSEL
+              IRQ Digital Filter Sampling Clock Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  PCLKB
+                  #00
+                
+                
+                  01
+                  PCLKB/8
+                  #01
+                
+                
+                  10
+                  PCLKB/32
+                  #10
+                
+                
+                  11
+                  PCLKB/64
+                  #11
+                
+              
+            
+            
+              IRQMD
+              IRQ Detection Sense Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Falling edge
+                  #00
+                
+                
+                  01
+                  Rising edge
+                  #01
+                
+                
+                  10
+                  Rising and falling edges
+                  #10
+                
+                
+                  11
+                  Low level
+                  #11
+                
+              
+            
+          
+        
+        
+          NMISR
+          Non-Maskable Interrupt Status Register
+          0x140
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              SPEST
+              CPU Stack pointer monitor  Interrupt Status Flag
+              12
+              12
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              BUSMST
+              MPU Bus Master Error Interrupt Status Flag
+              11
+              11
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              BUSSST
+              MPU Bus Slave Error Interrupt Status Flag
+              10
+              10
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              RECCST
+              RAM ECC Error Interrupt Status Flag
+              9
+              9
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              RPEST
+              RAM Parity Error Interrupt Status Flag
+              8
+              8
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              NMIST
+              NMI Status Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              OSTST
+              Oscillation Stop Detection Interrupt Status Flag
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Interrupt not requested for main oscillation stop
+                  #0
+                
+                
+                  1
+                  Interrupt requested for main oscillation stop.
+                  #1
+                
+              
+            
+            
+              VBATTST
+              VBATT monitor Interrupt Status Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              LVD2ST
+              Voltage-Monitoring 2 Interrupt Status Flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              LVD1ST
+              Voltage-Monitoring 1 Interrupt Status Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              WDTST
+              WDT Underflow/Refresh Error Status Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+            
+              IWDTST
+              IWDT Underflow/Refresh Error Status Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Interrupt not requested
+                  #0
+                
+                
+                  1
+                  Interrupt requested.
+                  #1
+                
+              
+            
+          
+        
+        
+          NMIER
+          Non-Maskable Interrupt Enable Register
+          0x120
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              SPEEN
+              CPU Stack pointer monitor Interrupt Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              BUSMEN
+              MPU Bus Master Error Interrupt Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              BUSSEN
+              MPU Bus Slave Error Interrupt Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              RECCEN
+              RAM ECC Error Interrupt Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              RPEEN
+              RAM Parity Error Interrupt Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              NMIEN
+              NMI Pin Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              OSTEN
+              Oscillation Stop Detection Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              VBATTEN
+              VBATT monitor Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              LVD2EN
+              Voltage-Monitoring 2 Interrupt Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              LVD1EN
+              Voltage-Monitoring 1 Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              WDTEN
+              WDT Underflow/Refresh Error Interrupt Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+            
+              IWDTEN
+              IWDT Underflow/Refresh Error Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          NMICLR
+          Non-Maskable Interrupt Status Clear Register
+          0x130
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              SPECLR
+              CPU Stack Pointer Monitor Interrupt Clear
+              12
+              12
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.SPEST flag. 
+                  #1
+                
+              
+            
+            
+              BUSMCLR
+              Bus Master Error Clear
+              11
+              11
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.BUSMST flag. 
+                  #1
+                
+              
+            
+            
+              BUSSCLR
+              Bus Slave Error Clear
+              10
+              10
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.BUSSST flag. 
+                  #1
+                
+              
+            
+            
+              RECCCLR
+              SRAM ECC Error Clear
+              9
+              9
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.RECCST flag. 
+                  #1
+                
+              
+            
+            
+              RPECLR
+              SRAM Parity Error Clear
+              8
+              8
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.RPEST flag. 
+                  #1
+                
+              
+            
+            
+              NMICLR
+              NMI Clear
+              7
+              7
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.NMIST flag. 
+                  #1
+                
+              
+            
+            
+              OSTCLR
+              OST Clear
+              6
+              6
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.OSTST flag. 
+                  #1
+                
+              
+            
+            
+              VBATTCLR
+              VBATT Clear
+              4
+              4
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.VBATTST flag. 
+                  #1
+                
+              
+            
+            
+              LVD2CLR
+              LVD2 Clear
+              3
+              3
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.LVD2ST flag. 
+                  #1
+                
+              
+            
+            
+              LVD1CLR
+              LVD1 Clear
+              2
+              2
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.LVD1ST flag. 
+                  #1
+                
+              
+            
+            
+              WDTCLR
+              WDT Clear
+              1
+              1
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.WDTST flag. 
+                  #1
+                
+              
+            
+            
+              IWDTCLR
+              IWDT Clear
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the NMISR.IWDTST flag. 
+                  #1
+                
+              
+            
+          
+        
+        
+          NMICR
+          NMI Pin Interrupt Control Register
+          0x100
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              NFLTEN
+              NMI Digital Filter Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Digital filter is disabled.
+                  #0
+                
+                
+                  1
+                  Digital filter is enabled.
+                  #1
+                
+              
+            
+            
+              NFCLKSEL
+              NMI Digital Filter Sampling Clock Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  PCLKB
+                  #00
+                
+                
+                  01
+                  PCLKB/8
+                  #01
+                
+                
+                  10
+                  PCLKB/32
+                  #10
+                
+                
+                  11
+                  PCLKB/64
+                  #11
+                
+              
+            
+            
+              NMIMD
+              NMI Detection Set
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Falling edge
+                  #0
+                
+                
+                  1
+                  Rising edge
+                  #1
+                
+              
+            
+          
+        
+        
+          96
+          0x4
+          IELSR[%s]
+          ICU Event Link Setting Register %s
+          0x300
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DTCE
+              DTC Activation Enable
+              24
+              24
+              read-write
+              
+                
+                  0
+                  DTC activation is disabled
+                  #0
+                
+                
+                  1
+                  DTC activation is enabled
+                  #1
+                
+              
+            
+            
+              IR
+              Interrupt Status Flag
+              16
+              16
+              read-write
+              
+                
+                  0
+                  No interrupt request is generated
+                  #0
+                
+                
+                  1
+                  An interrupt request is generated ( 1 write to the IR bit is prohibited. )
+                  #1
+                
+              
+            
+            
+              IELS
+              ICU Event selection to NVICSet the number for the event signal to be linked .
+              0
+              8
+              read-write
+              
+                
+                  0x000
+                  Nothing is selected
+                  0x000
+                
+                
+                  others
+                  See Event Table
+                  true
+                
+              
+            
+          
+        
+        
+          8
+          0x4
+          DELSR[%s]
+          DMAC Event Link Setting Register
+          0x280
+          32
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              IR
+              Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited.
+              16
+              16
+              read-write
+              
+                
+                  0x0
+                  No interrupt request is generated.
+                  #0
+                
+                
+                  0x1
+                  An interrupt request is generated.
+                  #1
+                
+              
+            
+            
+              DELS
+              Event selection to DMAC Start request
+              0
+              8
+              read-write
+              
+                
+                  0x000
+                  Nothing is selected.
+                  0x000
+                
+                
+                  others
+                  See Event Table
+                  true
+                
+              
+            
+          
+        
+        
+          SELSR0
+          Snooze Event Link Setting Register
+          0x200
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              SELS
+              SYS Event Link Select
+              0
+              8
+              read-write
+              
+                
+                  0x000
+                  Nothing is selected
+                  0x000
+                
+              
+            
+          
+        
+        
+          WUPEN
+          Wake Up Interrupt Enable Register
+          0x1A0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              IIC0WUPEN
+              IIC0 address match interrupt S/W standby returns enable
+              31
+              31
+              read-write
+              
+                
+                  0
+                  S/W standby returns by IIC0 address match interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by IIC0 address match interrupt is enabled
+                  #1
+                
+              
+            
+            
+              AGT1CBWUPEN
+              AGT1 compare match B interrupt S/W standby returns enable
+              30
+              30
+              read-write
+              
+                
+                  0
+                  S/W standby returns by AGT1 compare match B interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by AGT1 compare match B interrupt is enabled
+                  #1
+                
+              
+            
+            
+              AGT1CAWUPEN
+              AGT1 compare match A interrupt S/W standby returns enable 
+              29
+              29
+              read-write
+              
+                
+                  0
+                  S/W standby returns by AGT1 compare match A interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by AGT1 compare match A interrupt is enabled
+                  #1
+                
+              
+            
+            
+              AGT1UDWUPEN
+              AGT1 underflow interrupt S/W standby returns enable
+              28
+              28
+              read-write
+              
+                
+                  0
+                  S/W standby returns by AGT1 underflow interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by AGT1 underflow interrupt is enabled
+                  #1
+                
+              
+            
+            
+              USBFSWUPEN
+              USBFS interrupt S/W standby returns enable
+              27
+              27
+              read-write
+              
+                
+                  0
+                  S/W standby returns by USBFS interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by USBFS interrupt is enabled
+                  #1
+                
+              
+            
+            
+              USBHSWUPEN
+              USBHS interrupt S/W standby returns enable bit
+              26
+              26
+              read-write
+              
+                
+                  0
+                  S/W standby returns by USBHS interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by USBHS interrupt is enabled
+                  #1
+                
+              
+            
+            
+              RTCPRDWUPEN
+              RCT period interrupt S/W standby returns enable
+              25
+              25
+              read-write
+              
+                
+                  0
+                  S/W standby returns by RTC period interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by RTC period interrupt is enabled
+                  #1
+                
+              
+            
+            
+              RTCALMWUPEN
+              RTC alarm interrupt S/W standby returns enable
+              24
+              24
+              read-write
+              
+                
+                  0
+                  S/W standby returns by RTC alarm interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by RTC alarm interrupt is enabled
+                  #1
+                
+              
+            
+            
+              ACMPLP0WUPEN
+              ACMPLP0 interrupt S/W standby returns enable
+              23
+              23
+              read-write
+              
+                
+                  0
+                  S/W standby returns by ACMPLP0 interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by ACMPLP0 interrupt is enabled
+                  #1
+                
+              
+            
+            
+              ACMPHS0WUPEN
+              ACMPHS0 interrupt S/W standby returns enable bit
+              22
+              22
+              read-write
+              
+                
+                  0
+                  S/W standby returns by ACMPHS0 interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by ACMPHS0 interrupt is enabled
+                  #1
+                
+              
+            
+            
+              VBATTWUPEN
+              VBATT monitor interrupt S/W standby returns enable
+              20
+              20
+              read-write
+              
+                
+                  0
+                  S/W standby returns by VBATT monitor interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by VBATT monitor interrupt is enabled
+                  #1
+                
+              
+            
+            
+              LVD2WUPEN
+              LVD2 interrupt S/W standby returns enable
+              19
+              19
+              read-write
+              
+                
+                  0
+                  S/W standby returns by LVD2 interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by LVD2 interrupt is enabled
+                  #1
+                
+              
+            
+            
+              LVD1WUPEN
+              LVD1 interrupt S/W standby returns enable
+              18
+              18
+              read-write
+              
+                
+                  0
+                  S/W standby returns by LVD1 interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by LVD1 interrupt is enabled
+                  #1
+                
+              
+            
+            
+              KEYWUPEN
+              Key interrupt S/W standby returns enable
+              17
+              17
+              read-write
+              
+                
+                  0
+                  S/W standby returns by KEY interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by KEY interrupt is enabled
+                  #1
+                
+              
+            
+            
+              IWDTWUPEN
+              IWDT interrupt S/W standby returns enable
+              16
+              16
+              read-write
+              
+                
+                  0
+                  S/W standby returns by IWDT interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by IWDT interrupt is enabled
+                  #1
+                
+              
+            
+            
+              16
+              0x01
+              IRQWUPEN%s
+              IRQ interrupt S/W standby returns enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  S/W standby returns by IRQ interrupt is disabled
+                  #0
+                
+                
+                  1
+                  S/W standby returns by IRQ interrupt is enabled
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_IIC0
+      I2C Bus Interface
+      0x40053000
+      
+        0x00000000
+        0x014
+        registers
+      
+      
+        0x00000016
+        0x002
+        registers
+      
+      
+        
+          3
+          0x2
+          SAR[%s]
+          Slave Address Registers
+          0x0A
+          16
+          
+            L
+            Slave Address Register L
+            0x0
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                SVA
+                A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] }
+                0
+                7
+                read-write
+              
+            
+          
+          
+            U
+            Slave Address Register U
+            0x01
+            8
+            read-write
+            0x00
+            0xFF
+            
+              
+                SVA9
+                10-Bit Address(bit9)
+                2
+                2
+                read-write
+              
+              
+                SVA8
+                10-Bit Address(bit8)
+                1
+                1
+                read-write
+              
+              
+                FS
+                7-Bit/10-Bit Address Format Selection
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    The 7-bit address format is selected.
+                    #0
+                  
+                  
+                    1
+                    The 10-bit address format is selected.
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          ICCR1
+          I2C Bus Control Register 1 
+          0x00
+          8
+          read-write
+          0x1F
+          0xFF
+          
+            
+              ICE
+              I2C Bus Interface Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable (SCLn and SDAn pins in inactive state)
+                  #0
+                
+                
+                  1
+                  Enable (SCLn and SDAn pins in active state)
+                  #1
+                
+              
+            
+            
+              IICRST
+              I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Releases the RIIC reset or internal reset.
+                  #0
+                
+                
+                  1
+                  Initiates the RIIC reset or internal reset. 
+                  #1
+                
+              
+            
+            
+              CLO
+              Extra SCL Clock Cycle Output
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Does not output an extra SCL clock cycle.
+                  #0
+                
+                
+                  1
+                  Outputs an extra SCL clock cycle.
+                  #1
+                
+              
+            
+            
+              SOWP
+              SCLO/SDAO Write Protect
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Bits SCLO and SDAO can be written
+                  #0
+                
+                
+                  1
+                  Bits SCLO and SDAO are protected.
+                  #1
+                
+              
+            
+            
+              SCLO
+              SCL Output Control/Monitor
+              3
+              3
+              read-write
+              
+                
+                  0
+                  (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low.
+                  #0
+                
+                
+                  1
+                  (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin.
+                  #1
+                
+              
+            
+            
+              SDAO
+              SDA Output Control/Monitor
+              2
+              2
+              read-write
+              
+                
+                  0
+                  (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low.
+                  #0
+                
+                
+                  1
+                  (Read)The RIIC has released the SDAn pin./  (Write)The RIIC releases the SDAn pin.
+                  #1
+                
+              
+            
+            
+              SCLI
+              SCL Line Monitor
+              1
+              1
+              read-only
+              
+                
+                  0
+                  SCLn line is low.
+                  #0
+                
+                
+                  1
+                  SCLn line is high.
+                  #1
+                
+              
+            
+            
+              SDAI
+              SDA Line Monitor
+              0
+              0
+              read-only
+              
+                
+                  0
+                  SDAn line is low.
+                  #0
+                
+                
+                  1
+                  SDAn line is high.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICCR2
+          I2C Bus Control Register 2
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BBSY
+              Bus Busy Detection Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  The I2C bus is released (bus free state).
+                  #0
+                
+                
+                  1
+                  The I2C bus is occupied (bus busy state). 
+                  #1
+                
+              
+            
+            
+              MST
+              Master/Slave Mode
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Slave mode
+                  #0
+                
+                
+                  1
+                  Master mode
+                  #1
+                
+              
+            
+            
+              TRS
+              Transmit/Receive Mode 
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Receive mode
+                  #0
+                
+                
+                  1
+                  Transmit mode
+                  #1
+                
+              
+            
+            
+              SP
+              Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Does not request to issue a stop condition.
+                  #0
+                
+                
+                  1
+                  Requests to issue a stop condition.
+                  #1
+                
+              
+            
+            
+              RS
+              Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Does not request to issue a restart condition.
+                  #0
+                
+                
+                  1
+                  Requests to issue a restart condition.
+                  #1
+                
+              
+            
+            
+              ST
+              Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state).
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Does not request to issue a start condition.
+                  #0
+                
+                
+                  1
+                  Requests to issue a start condition.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICMR1
+          I2C Bus Mode Register 1
+          0x02
+          8
+          read-write
+          0x08
+          0xFF
+          
+            
+              MTWP
+              MST/TRS Write Protect
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disables writing to the MST and TRS bits in ICCR2.
+                  #0
+                
+                
+                  1
+                  Enables writing to the MST and TRS bits in ICCR2.
+                  #1
+                
+              
+            
+            
+              CKS
+              Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )
+              4
+              6
+              read-write
+              
+                
+                  000
+                  PCLKB/1 clock
+                  #000
+                
+                
+                  001
+                  PCLKB/2 clock
+                  #001
+                
+                
+                  010
+                  PCLKB/4 clock
+                  #010
+                
+                
+                  011
+                  PCLKB/8 clock
+                  #011
+                
+                
+                  100
+                  PCLKB/16 clock
+                  #100
+                
+                
+                  101
+                  PCLKB/32 clock
+                  #101
+                
+                
+                  110
+                  PCLKB/64 clock
+                  #110
+                
+                
+                  111
+                  PCLKB/128 clock
+                  #111
+                
+              
+            
+            
+              BCWP
+              BC Write Protect(This bit is read as 1.)
+              3
+              3
+              write-only
+              
+                
+                  0
+                  Enables a value to be written in the BC[2:0] bits.
+                  #0
+                
+                
+                  1
+                  Disables a value to be written in the BC[2:0] bits.
+                  #1
+                
+              
+            
+            
+              BC
+              Bit Counter
+              0
+              2
+              read-write
+              
+                
+                  000
+                  9 bits
+                  #000
+                
+                
+                  001
+                  2 bits
+                  #001
+                
+                
+                  010
+                  3 bits
+                  #010
+                
+                
+                  011
+                  4 bits
+                  #011
+                
+                
+                  100
+                  5 bits
+                  #100
+                
+                
+                  101
+                  6 bits
+                  #101
+                
+                
+                  110
+                  7 bits
+                  #110
+                
+                
+                  111
+                  8 bits
+                  #111
+                
+              
+            
+          
+        
+        
+          ICMR2
+          I2C Bus Mode Register 2
+          0x03
+          8
+          read-write
+          0x06
+          0xFF
+          
+            
+              DLCS
+              SDA Output Delay Clock Source Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter.
+                  #0
+                
+                
+                  1
+                  The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter.
+                  #1
+                
+              
+            
+            
+              SDDL
+              SDA Output Delay Counter
+              4
+              6
+              read-write
+              
+                
+                  000
+                  No output delay
+                  #000
+                
+                
+                  001
+                  1 fIIC cycle  (ICMR2.DLCS=0) / 1  or 2 fIIC cycles (ICMR2.DLCS=1)
+                  #001
+                
+                
+                  010
+                  2 fIIC cycles (ICMR2.DLCS=0) /  3 or 4 fIIC cycles (ICMR2.DLCS=1)
+                  #010
+                
+                
+                  011
+                  3 fIIC cycles (ICMR2.DLCS=0) /  5 or 6 fIIC cycles (ICMR2.DLCS=1)
+                  #011
+                
+                
+                  100
+                  4 fIIC cycles (ICMR2.DLCS=0) /  7 or 8 fIIC cycles (ICMR2.DLCS=1)
+                  #100
+                
+                
+                  101
+                  5 fIIC cycles (ICMR2.DLCS=0) /  9 or 10 fIIC cycles (ICMR2.DLCS=1)
+                  #101
+                
+                
+                  110
+                  6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)
+                  #110
+                
+                
+                  111
+                  7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)
+                  #111
+                
+              
+            
+            
+              TMOH
+              Timeout H Count Control
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Count is disabled while the SCLn line is at a high level.
+                  #0
+                
+                
+                  1
+                  Count is enabled while the SCLn line is at a high level.
+                  #1
+                
+              
+            
+            
+              TMOL
+              Timeout L Count Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Count is disabled while the SCLn line is at a low level.
+                  #0
+                
+                
+                  1
+                  Count is enabled while the SCLn line is at a low level.
+                  #1
+                
+              
+            
+            
+              TMOS
+              Timeout Detection Time Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Long mode is selected.
+                  #0
+                
+                
+                  1
+                  Short mode is selected.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICMR3
+          I2C Bus Mode Register 3
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SMBS
+              SMBus/I2C Bus Selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The I2C bus is selected.
+                  #0
+                
+                
+                  1
+                  The SMBus is selected.
+                  #1
+                
+              
+            
+            
+              WAIT
+              WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)
+                  #0
+                
+                
+                  1
+                  WAIT (The period between ninth clock cycle and first clock cycle is held low.)
+                  #1
+                
+              
+            
+            
+              RDRFS
+              RDRF Flag Set Timing Selection
+              5
+              5
+              read-write
+              
+                
+                  0
+                  The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)
+                  #0
+                
+                
+                  1
+                  The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)
+                  #1
+                
+              
+            
+            
+              ACKWP
+              ACKBT Write Protect
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Modification of the ACKBT bit is disabled.
+                  #0
+                
+                
+                  1
+                  Modification of the ACKBT bit is enabled.
+                  #1
+                
+              
+            
+            
+              ACKBT
+              Transmit Acknowledge
+              3
+              3
+              read-write
+              
+                
+                  0
+                  A 0 is sent as the acknowledge bit (ACK transmission).
+                  #0
+                
+                
+                  1
+                  A 1 is sent as the acknowledge bit (NACK transmission).
+                  #1
+                
+              
+            
+            
+              ACKBR
+              Receive Acknowledge
+              2
+              2
+              read-only
+              
+                
+                  0
+                  A 0 is received as the acknowledge bit (ACK reception).
+                  #0
+                
+                
+                  1
+                  A 1 is received as the acknowledge bit (NACK reception).
+                  #1
+                
+              
+            
+            
+              NF
+              Noise Filter Stage Selection
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Noise of up to one fIIC cycle is filtered out (single-stage filter).
+                  #00
+                
+                
+                  01
+                  Noise of up to two fIIC cycles is filtered out (2-stage filter).
+                  #01
+                
+                
+                  10
+                  Noise of up to three fIIC cycles is filtered out (3-stage filter).
+                  #10
+                
+                
+                  11
+                  Noise of up to four fIIC cycles is filtered out (4-stage filter)
+                  #11
+                
+              
+            
+          
+        
+        
+          ICFER
+          I2C Bus Function Enable Register 
+          0x05
+          8
+          read-write
+          0x72
+          0xFF
+          
+            
+              FMPE
+              Fast-mode Plus Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  No Fm+ slope control circuit is used for the SCLn pin and SDAn pin.
+                  #0
+                
+                
+                  1
+                  An Fm+ slope control circuit is used for the SCLn pin and SDAn pin.
+                  #1
+                
+              
+            
+            
+              SCLE
+              SCL Synchronous Circuit Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  No SCL synchronous circuit is used.
+                  #0
+                
+                
+                  1
+                  An SCL synchronous circuit is used.
+                  #1
+                
+              
+            
+            
+              NFE
+              Digital Noise Filter Circuit Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  No digital noise filter circuit is used.
+                  #0
+                
+                
+                  1
+                  A digital noise filter circuit is used.
+                  #1
+                
+              
+            
+            
+              NACKE
+              NACK Reception Transfer Suspension Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Transfer operation is not suspended during NACK reception (transfer suspension disabled).
+                  #0
+                
+                
+                  1
+                  Transfer operation is suspended during NACK reception (transfer suspension enabled).
+                  #1
+                
+              
+            
+            
+              SALE
+              Slave Arbitration-Lost Detection Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Slave arbitration-lost detection is disabled.
+                  #0
+                
+                
+                  1
+                  Slave arbitration-lost detection is enabled.
+                  #1
+                
+              
+            
+            
+              NALE
+              NACK Transmission Arbitration-Lost Detection Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  NACK transmission arbitration-lost detection is disabled.
+                  #0
+                
+                
+                  1
+                  NACK transmission arbitration-lost detection is enabled.
+                  #1
+                
+              
+            
+            
+              MALE
+              Master Arbitration-Lost Detection Enable 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Master arbitration-lost detection is disabled.
+                  #0
+                
+                
+                  1
+                  Master arbitration-lost detection is enabled.
+                  #1
+                
+              
+            
+            
+              TMOE
+              Timeout Function Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  The timeout function is disabled.
+                  #0
+                
+                
+                  1
+                  The timeout function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICSER
+          I2C Bus Status Enable Register
+          0x06
+          8
+          read-write
+          0x09
+          0xFF
+          
+            
+              HOAE
+              Host Address Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Host address detection is disabled.
+                  #0
+                
+                
+                  1
+                  Host address detection is enabled.
+                  #1
+                
+              
+            
+            
+              DIDE
+              Device-ID Address Detection Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Device-ID address detection is disabled.
+                  #0
+                
+                
+                  1
+                  Device-ID address detection is enabled.
+                  #1
+                
+              
+            
+            
+              GCAE
+              General Call Address Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  General call address detection is disabled.
+                  #0
+                
+                
+                  1
+                  General call address detection is enabled.
+                  #1
+                
+              
+            
+            
+              SAR2E
+              Slave Address Register 2 Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Slave address in SARL2 and SARU2 is disabled.
+                  #0
+                
+                
+                  1
+                  Slave address in SARL2 and SARU2 is enabled
+                  #1
+                
+              
+            
+            
+              SAR1E
+              Slave Address Register 1 Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Slave address in SARL1 and SARU1 is disabled.
+                  #0
+                
+                
+                  1
+                  Slave address in SARL1 and SARU1 is enabled.
+                  #1
+                
+              
+            
+            
+              SAR0E
+              Slave Address Register 0 Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Slave address in SARL0 and SARU0 is disabled.
+                  #0
+                
+                
+                  1
+                  Slave address in SARL0 and SARU0 is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICIER
+          I2C Bus Interrupt Enable Register
+          0x07
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TIE
+              Transmit Data Empty Interrupt Request Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Transmit data empty interrupt request (IIC_TXI) is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit data empty interrupt request (IIC_TXI) is enabled.
+                  #1
+                
+              
+            
+            
+              TEIE
+              Transmit End Interrupt Request  Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Transmit end interrupt request (IIC_TEI) is disabled.
+                  #0
+                
+                
+                  1
+                  Transmit end interrupt request (IIC_TEI) is enabled.
+                  #1
+                
+              
+            
+            
+              RIE
+              Receive Data Full Interrupt Request Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Receive data full interrupt request (IIC_RXI) is disabled.
+                  #0
+                
+                
+                  1
+                  Receive data full interrupt request (IIC_RXI) is enabled.
+                  #1
+                
+              
+            
+            
+              NAKIE
+              NACK Reception Interrupt Request Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  NACK reception interrupt request (NAKI) is disabled.
+                  #0
+                
+                
+                  1
+                  NACK reception interrupt request (NAKI) is enabled.
+                  #1
+                
+              
+            
+            
+              SPIE
+              Stop Condition Detection Interrupt Request Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Stop condition detection interrupt request (SPI) is disabled.
+                  #0
+                
+                
+                  1
+                  Stop condition detection interrupt request (SPI) is enabled.
+                  #1
+                
+              
+            
+            
+              STIE
+              Start Condition Detection Interrupt Request Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Start condition detection interrupt request (STI) is disabled.
+                  #0
+                
+                
+                  1
+                  Start condition detection interrupt request (STI) is enabled.
+                  #1
+                
+              
+            
+            
+              ALIE
+              Arbitration-Lost Interrupt Request Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Arbitration-lost interrupt request (ALI) is disabled.  
+                  #0
+                
+                
+                  1
+                  Arbitration-lost interrupt request (ALI) is enabled.
+                  #1
+                
+              
+            
+            
+              TMOIE
+              Timeout Interrupt Request Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Timeout interrupt request (TMOI) is disabled.  
+                  #0
+                
+                
+                  1
+                  Timeout interrupt request (TMOI) is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICSR1
+          I2C Bus Status Register 1
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HOA
+              Host Address Detection Flag 
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Host address is not detected.  
+                  #0
+                
+                
+                  1
+                  Host address is detected.
+                  #1
+                
+              
+            
+            
+              DID
+              Device-ID Address Detection Flag
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Device-ID command is not detected.
+                  #0
+                
+                
+                  1
+                  Device-ID command is detected.
+                  #1
+                
+              
+            
+            
+              GCA
+              General Call Address Detection Flag
+              3
+              3
+              read-write
+              
+                
+                  0
+                  General call address is not detected.
+                  #0
+                
+                
+                  1
+                  General call address is detected.
+                  #1
+                
+              
+            
+            
+              AAS2
+              Slave Address 2 Detection Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Slave address 2 is not detected.
+                  #0
+                
+                
+                  1
+                  Slave address 2 is detected
+                  #1
+                
+              
+            
+            
+              AAS1
+              Slave Address 1 Detection Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Slave address 1 is not detected.
+                  #0
+                
+                
+                  1
+                  Slave address 1 is detected.
+                  #1
+                
+              
+            
+            
+              AAS0
+              Slave Address 0 Detection Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Slave address 0 is not detected.
+                  #0
+                
+                
+                  1
+                  Slave address 0 is detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICSR2
+          I2C Bus Status Register 2
+          0x09
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TDRE
+              Transmit Data Empty Flag
+              7
+              7
+              read-only
+              
+                
+                  0
+                  ICDRT contains transmit data. 
+                  #0
+                
+                
+                  1
+                  ICDRT contains no transmit data.
+                  #1
+                
+              
+            
+            
+              TEND
+              Transmit End Flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Data is being transmitted.
+                  #0
+                
+                
+                  1
+                  Data has been transmitted.
+                  #1
+                
+              
+            
+            
+              RDRF
+              Receive Data Full Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  ICDRR contains no receive data.
+                  #0
+                
+                
+                  1
+                  ICDRR contains receive data.
+                  #1
+                
+              
+            
+            
+              NACKF
+              NACK Detection Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  NACK is not detected.
+                  #0
+                
+                
+                  1
+                  NACK is detected.
+                  #1
+                
+              
+            
+            
+              STOP
+              Stop Condition Detection Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Stop condition is not detected.
+                  #0
+                
+                
+                  1
+                  Stop condition is detected.
+                  #1
+                
+              
+            
+            
+              START
+              Start Condition Detection Flag 
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Start condition is not detected.
+                  #0
+                
+                
+                  1
+                  Start condition is detected.
+                  #1
+                
+              
+            
+            
+              AL
+              Arbitration-Lost Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Arbitration is not lost.
+                  #0
+                
+                
+                  1
+                  Arbitration is lost.
+                  #1
+                
+              
+            
+            
+              TMOF
+              Timeout Detection Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Timeout is not detected.
+                  #0
+                
+                
+                  1
+                  Timeout is detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICBRL
+          I2C Bus Bit Rate Low-Level Register
+          0x10
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              BRL
+              Bit Rate Low-Level Period(Low-level period of SCL clock)
+              0
+              4
+              read-write
+            
+          
+        
+        
+          ICBRH
+          I2C Bus Bit Rate High-Level Register 
+          0x11
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              BRH
+              Bit Rate High-Level Period(High-level period of SCL clock)
+              0
+              4
+              read-write
+            
+          
+        
+        
+          ICDRT
+          I2C Bus Transmit Data Register
+          0x12
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              ICDRT
+              8-bit read-write register that stores transmit data.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          ICDRR
+          I2C Bus Receive Data Register
+          0x13
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              ICDRR
+              8-bit register that stores the received data
+              0
+              7
+              read-only
+            
+          
+        
+        
+          ICWUR
+          I2C Bus Wake Up Unit Register
+          0x16
+          8
+          read-write
+          0x10
+          0xFF
+          
+            
+              WUE
+              Wakeup Function Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Wakeup function disabled
+                  #0
+                
+                
+                  1
+                  Wakeup function enabled.
+                  #1
+                
+              
+            
+            
+              WUIE
+              Wakeup Interrupt Request Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Wakeup Interrupt Request (IIC0_WUI) disabled
+                  #0
+                
+                
+                  1
+                  Wakeup Interrupt Request (IIC0_WUI) enabled.
+                  #1
+                
+              
+            
+            
+              WUF
+              Wakeup Event Occurrence Flag
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Slave address does not match during wakeup function
+                  #0
+                
+                
+                  1
+                  Slave address matches during wakeup function.
+                  #1
+                
+              
+            
+            
+              WUACK
+              ACK bit for Wakeup Mode
+              4
+              4
+              read-write
+              
+                
+                  0
+                  State of synchronous operation
+                  #0
+                
+                
+                  1
+                  State of asynchronous operation
+                  #1
+                
+              
+            
+            
+              WUAFA
+              Wakeup Analog Filter Additional Selection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Do not add the wakeup analog filter
+                  #0
+                
+                
+                  1
+                  Add the wakeup analog filter.
+                  #1
+                
+              
+            
+          
+        
+        
+          ICWUR2
+          I2C Bus Wake up Unit Register 2
+          0x17
+          8
+          read-write
+          0xFD
+          0xFF
+          
+            
+              WUSYF
+              Wake-up Function Synchronous Operation Status Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  IIC asynchronous circuit enable condition
+                  #0
+                
+                
+                  1
+                  IIC synchronous circuit enable condition.
+                  #1
+                
+              
+            
+            
+              WUASYF
+              Wake-up Function Asynchronous Operation Status Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  IIC synchronous circuit enable condition
+                  #0
+                
+                
+                  1
+                  IIC asynchronous circuit enable condition.
+                  #1
+                
+              
+            
+            
+              WUSEN
+              Wake-up Function Synchronous Enable
+              0
+              0
+              read-only
+              
+                
+                  0
+                  IIC asynchronous circuit enable
+                  #0
+                
+                
+                  1
+                  IIC synchronous circuit enable
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_IIC1
+      0x40053100
+    
+    
+      R_IIC2
+      0x40053200
+    
+    
+      R_IRDA
+      IrDA Interface
+      0x40070F00
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        
+          IRCR
+          IrDA Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              IRE
+              IrDA Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Serial I/O pins are used for normal serial communication.
+                  #0
+                
+                
+                  1
+                  Serial I/O pins are used for IrDA data communication.
+                  #1
+                
+              
+            
+            
+              IRTXINV
+              IRTXD Polarity Switching 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Data to be transmitted is output to IRTXD as is.
+                  #0
+                
+                
+                  1
+                  Data to be transmitted is output to IRTXD after the polarity is inverted.
+                  #1
+                
+              
+            
+            
+              IRRXINV
+              IRRXD Polarity Switching
+              2
+              2
+              read-write
+              
+                
+                  0
+                  IRRXD input is used as received data as is.
+                  #0
+                
+                
+                  1
+                  IRRXD input is used as received data after the polarity is inverted.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_IWDT
+      Independent Watchdog Timer
+      0x40044400
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x02
+        registers
+      
+      
+        
+          IWDTRR
+          IWDT Refresh Register
+          0x00
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              IWDTRR
+              The counter is refreshed by writing 0x00 and then writing 0xFF to this register.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          IWDTSR
+          IWDT Status Register
+          0x04
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              REFEF
+              Refresh Error Flag
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Refresh error not occurred
+                  #0
+                
+                
+                  1
+                  Refresh error occurred
+                  #1
+                
+              
+            
+            
+              UNDFF
+              Underflow Flag
+              14
+              14
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Underflow not occurred
+                  #0
+                
+                
+                  1
+                  Underflow occurred
+                  #1
+                
+              
+            
+            
+              CNTVAL
+              Counter ValueValue counted by the counter
+              0
+              13
+              read-only
+            
+          
+        
+      
+    
+    
+      R_JPEG
+      JPEG Codec
+      0x400E6000
+      
+        0x00000000
+        0x002
+        registers
+      
+      
+        0x00000003
+        0x00F
+        registers
+      
+      
+        0x00000040
+        0x014
+        registers
+      
+      
+        0x00000058
+        0x01C
+        registers
+      
+      
+        0x0000008C
+        0x008
+        registers
+      
+      
+        0x00000100
+        0x11C
+        registers
+      
+      
+        0x00000220
+        0x0B2
+        registers
+      
+      
+        0x00000300
+        0x01C
+        registers
+      
+      
+        0x00000320
+        0x0B2
+        registers
+      
+      
+        
+          JCMOD
+           JPEG Code Mode Register
+          0x000
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DSP
+              Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Compression process 
+                  #0
+                
+                
+                  1
+                  Decompression process
+                  #1
+                
+              
+            
+            
+              REDU
+              Pixel FormatNOTE: Read-only in Decompression.
+              0
+              2
+              read-write
+              
+                
+                  001
+                  YCbCr422(Compression) / YCbCr422(Decompression)
+                  #001
+                
+                
+                  000
+                  Setting prohibited(Compression) / YCbCr444(Decompression)
+                  #000
+                
+                
+                  110
+                  Setting prohibited(Compression) / YCbCr411/[Decompression] 
+                  #110
+                
+                
+                  010
+                  Setting prohibited(Compression) / YCbCr420/[Decompression] 
+                  #010
+                
+                
+                  others
+                  Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression])
+                  true
+                
+              
+            
+          
+        
+        
+          JCCMD
+          JPEG Code Command Register
+          0x001
+          8
+          write-only
+          0x00
+          0x00
+          
+            
+              BRST
+              Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued.
+              7
+              7
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers.
+                  #1
+                
+              
+            
+            
+              JEND
+              Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1
+              2
+              2
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear all bits in JINTE0.
+                  #1
+                
+              
+            
+            
+              JRST
+              JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1.
+              1
+              1
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0).
+                  #1
+                
+              
+            
+            
+              JSRT
+              JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation.
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No effect.
+                  #0
+                
+                
+                  1
+                  Start JPEG core processing
+                  #1
+                
+              
+            
+          
+        
+        
+          JCQTN
+          JPEG Code Quantization Table Number Register
+          0x003
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              QT3
+              Quantization table number for the third color component NOTE: Read-only in Decompression.
+              4
+              5
+              read-write
+              
+                
+                  00
+                  Use quantization table No.0 (JCQTBL0) as the third color component.
+                  #00
+                
+                
+                  01
+                  Use quantization table No.1 (JCQTBL1) as the third color component.
+                  #01
+                
+                
+                  10
+                  Use quantization table No.2 (JCQTBL2) as the third color component.
+                  #10
+                
+                
+                  11
+                  Use quantization table No.3 (JCQTBL3) as the third color component.
+                  #11
+                
+              
+            
+            
+              QT2
+              Quantization table number for the second color component NOTE: Read-only in Decompression.
+              2
+              3
+              read-write
+              
+                
+                  00
+                  Use quantization table No.0 (JCQTBL0) as the second color component.
+                  #00
+                
+                
+                  01
+                  Use quantization table No.1 (JCQTBL1) as the second color component.
+                  #01
+                
+                
+                  10
+                  Use quantization table No.2 (JCQTBL2) as the second color component.
+                  #10
+                
+                
+                  11
+                  Use quantization table No.3 (JCQTBL3) as the second color component.
+                  #11
+                
+              
+            
+            
+              QT1
+              Quantization table number for the first color componentNOTE: Read-only in Decompression.
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Use quantization table No.0 (JCQTBL0) as the first color component.
+                  #00
+                
+                
+                  01
+                  Use quantization table No.1 (JCQTBL1) as the first color component.
+                  #01
+                
+                
+                  10
+                  Use quantization table No.2 (JCQTBL2) as the first color component.
+                  #10
+                
+                
+                  11
+                  Use quantization table No.3 (JCQTBL3) as the first color component.
+                  #11
+                
+              
+            
+          
+        
+        
+          JCHTN
+          JPEG Code Huffman Table Number Register
+          0x004
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HTA3
+              Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1)
+                  #0
+                
+                
+                  1
+                  AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0)
+                  #1
+                
+              
+            
+            
+              HTD3
+              Huffman table number (DC) for the third color component NOTE: Read-only in Decompression.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1)
+                  #0
+                
+                
+                  1
+                  DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0)
+                  #1
+                
+              
+            
+            
+              HTA2
+              Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1)
+                  #0
+                
+                
+                  1
+                  AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0)
+                  #1
+                
+              
+            
+            
+              HTD2
+              Huffman table number (DC) for the second color component NOTE: Read-only in Decompression.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1)
+                  #0
+                
+                
+                  1
+                  DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0)
+                  #1
+                
+              
+            
+            
+              HTA1
+              Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1)
+                  #0
+                
+                
+                  1
+                  AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0)
+                  #1
+                
+              
+            
+            
+              HTD1
+              Huffman table number (DC) for the first color component NOTE: Read-only in Decompression.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1)
+                  #0
+                
+                
+                  1
+                  DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0)
+                  #1
+                
+              
+            
+          
+        
+        
+          JCDRIU
+          JPEG Code DRI Upper Register
+          0x005
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DRIU
+              Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCDRID
+          JPEG Code DRI Lower Register
+          0x006
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DRID
+              Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCVSZU
+          JPEG Code Vertical Size Upper Register
+          0x007
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VSZU
+              Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCVSZD
+          JPEG Code Vertical Size Lower Register
+          0x008
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VSZD
+              Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCHSZU
+          JPEG Code Horizontal Size Upper Register 
+          0x009
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HSZU
+              Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCHSZD
+          JPEG Coded Horizontal Size Lower Register
+          0x00A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HSZD
+              Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JCDTCU
+          JPEG Code Data Count Upper Register
+          0x00B
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              DCU
+              Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          JCDTCM
+          JPEG Code Data Count Middle Register
+          0x00C
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              DCM
+              Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          JCDTCD
+          JPEG Code Data Count Lower Register
+          0x00D
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              DCD
+               Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          JINTE0
+          JPEG Interrupt Enable Register 0
+          0x00E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              INT7
+              This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned.
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              INT6
+              This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              INT5
+              This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              INT3
+              This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          JINTS0
+          JPEG Interrupt Status Register 0 
+          0x00F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              INS6
+              This bit is set to 1 when this module completes compression process normally.
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+            
+            
+              INS5
+              This bit is set to 1 when a compressed data error occurs.
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+            
+            
+              INS3
+               This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. 
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+            
+          
+        
+        
+          JCDERR
+          JPEG Code Decode Error Register
+          0x010
+          8
+          read-write
+          0x0A
+          0xFF
+          
+            
+              ERR
+              Error Code  (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression.
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  Normal(Decompression error codes)/Normal(Segment error codes)
+                  #0000
+                
+                
+                  0001
+                  SOI not detected(Decompression error codes)
+                  #0001
+                
+                
+                  0010
+                  SOF1 to SOFF detected(Decompression error codes)
+                  #0010
+                
+                
+                  0011
+                  Unprovided pixel format detected(Decompression error codes)
+                  #0011
+                
+                
+                  0100
+                  SOF accuracy error(Decompression error codes)
+                  #0100
+                
+                
+                  0101
+                  DQT accuracy error(Decompression error codes)
+                  #0101
+                
+                
+                  0110
+                  Component error 1(Decompression error codes)
+                  #0110
+                
+                
+                  0111
+                  Component error 2(Decompression error codes)
+                  #0111
+                
+                
+                  1000
+                  SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes)
+                  #1000
+                
+                
+                  1001
+                  SOS not detected(Decompression error codes)
+                  #1001
+                
+                
+                  1010
+                  EOI not detected (default)(Decompression error codes)
+                  #1010
+                
+                
+                  1011
+                  Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes)
+                  #1011
+                
+                
+                  1100
+                  Image size error detected(Decompression error codes)/Image size error(Segment error codes)
+                  #1100
+                
+                
+                  1101
+                  Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes)
+                  #1101
+                
+                
+                  1110
+                  Block data number error detected(Decompression error codes)/Block data number error(Segment error codes)
+                  #1110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          JCRST
+          JPEG Code Reset Register
+          0x011
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              RST
+              Operating State
+              0
+              0
+              read-only
+              
+                
+                  0
+                  State other than below 
+                  #0
+                
+                
+                  1
+                  Suspended state caused by interrupt sources of JINTE0 
+                  #1
+                
+              
+            
+          
+        
+        
+          JIFECNT
+          JPEG Interface Compression Control Register
+          0x040
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              JOUTSWAP
+              Byte/Halfword/Word Swap Output coded data in compression is swapped.
+              8
+              10
+              read-write
+              
+                
+                  000
+                  (1) (2) (3) (4) (5) (6) (7) (8) 
+                  #000
+                
+                
+                  001
+                  (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 
+                  #001
+                
+                
+                  010
+                  (3) (4) (1) (2) (7) (8) (5) (6)  [Halfword swap] 
+                  #010
+                
+                
+                  011
+                  (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] 
+                  #011
+                
+                
+                  100
+                  (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] 
+                  #100
+                
+                
+                  101
+                  (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] 
+                  #101
+                
+                
+                  110
+                  (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] 
+                  #110
+                
+                
+                  111
+                  (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] 
+                  #111
+                
+              
+            
+            
+              DINRINI
+              Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The transfer address is not initialized when the input of image data lines is restarted
+                  #0
+                
+                
+                  1
+                  The transfer address is initialized when the input of image data lines is restarted
+                  #1
+                
+              
+            
+            
+              DINRCMD
+              Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. 
+              5
+              5
+              write-only
+            
+            
+              DINLC
+               Count Mode Setting for Stopping Input Image Data Lines 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Count mode for stopping the input of image data lines is off
+                  #0
+                
+                
+                  1
+                  Count mode for stopping the input of image data lines is on
+                  #1
+                
+              
+            
+            
+              DINSWAP
+               Byte/Halfword Swap 
+              0
+              2
+              read-write
+              
+                
+                  000
+                  (1) (2) (3) (4) (5) (6) (7) (8) 
+                  #000
+                
+                
+                  001
+                  (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 
+                  #001
+                
+                
+                  010
+                  (3) (4) (1) (2) (7) (8) (5) (6)  [Halfword swap] 
+                  #010
+                
+                
+                  011
+                  (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] 
+                  #011
+                
+                
+                  100
+                  (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] 
+                  #100
+                
+                
+                  101
+                  (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] 
+                  #101
+                
+                
+                  110
+                  (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] 
+                  #110
+                
+                
+                  111
+                  (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] 
+                  #111
+                
+              
+            
+          
+        
+        
+          JIFESA
+          JPEG Interface Compression Source Address Register
+          0x044
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ESA
+               Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          JIFESOFST
+          JPEG Interface Compression Line Offset Register
+          0x048
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ESMW
+              Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          JIFEDA
+          JPEG Interface Compression Destination Address Register
+          0x04C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EDA
+              Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          JIFESLC
+          JPEG Interface Compression Source Line Count Register
+          0x050
+          32
+          read-write
+          0xFFF8FFF8
+          0xFFFFFFFF
+          
+            
+              LINES
+              Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. 
+              0
+              15
+              read-write
+            
+          
+        
+        
+          JIFDCNT
+          JPEG Interface Decompression Control Register 
+          0x058
+          32
+          read-write
+          0x01000000
+          0xFFFFFFFF
+          
+            
+              VINTER
+              Vertical SubsamplingSubsamples vertical output image data. 
+              28
+              29
+              read-write
+              
+                
+                  00
+                  No subsampling 
+                  #00
+                
+                
+                  01
+                  Subsamples output data into 1/2. 
+                  #01
+                
+                
+                  10
+                  Subsamples output data into 1/4. 
+                  #10
+                
+                
+                  11
+                  Subsamples output data into 1/8.
+                  #11
+                
+              
+            
+            
+              HINTER
+              Horizontal Subsampling Subsamples horizontal output image data.
+              26
+              27
+              read-write
+              
+                
+                  00
+                  No subsampling 
+                  #00
+                
+                
+                  01
+                  Subsamples output data into 1/2. 
+                  #01
+                
+                
+                  10
+                  Subsamples output data into 1/4. 
+                  #10
+                
+                
+                  11
+                  Subsamples output data into 1/8.
+                  #11
+                
+              
+            
+            
+              OPF
+              Specifies output image data pixel format.
+              24
+              25
+              read-write
+              
+                
+                  01
+                  ARGB8888 
+                  #01
+                
+                
+                  10
+                  RGB565 
+                  #10
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              JINRINI
+              Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. 
+              14
+              14
+              read-write
+              
+                
+                  0
+                  The transfer address is not initialized when the input of coded data is restarted. 
+                  #0
+                
+                
+                  1
+                  The transfer address is initialized when the input of coded data is restarted.
+                  #1
+                
+              
+            
+            
+              JINRCMD
+              Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0.
+              13
+              13
+              write-only
+            
+            
+              JINC
+              Count Mode Setting for Stopping Input Coded Data 
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Count mode for stopping the input of coded data is off. 
+                  #0
+                
+                
+                  1
+                  Count mode for stopping the input of coded data is on
+                  #1
+                
+              
+            
+            
+              JINSWAP
+              Byte/Word/Longword Swap Input coded data in decompression is swapped. 
+              8
+              10
+              read-write
+              
+                
+                  000
+                  (1) (2) (3) (4) (5) (6) (7) (8) 
+                  #000
+                
+                
+                  001
+                  (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 
+                  #001
+                
+                
+                  010
+                  (3) (4) (1) (2) (7) (8) (5) (6)  [Halfword swap] 
+                  #010
+                
+                
+                  011
+                  (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] 
+                  #011
+                
+                
+                  100
+                  (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] 
+                  #100
+                
+                
+                  101
+                  (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] 
+                  #101
+                
+                
+                  110
+                  (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] 
+                  #110
+                
+                
+                  111
+                  (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap]
+                  #111
+                
+              
+            
+            
+              DOUTRINI
+              Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The transfer address is not initialized when the output of lines of image data is restarted. 
+                  #0
+                
+                
+                  1
+                  The transfer address is initialized when the output of lines of image data is restarted
+                  #1
+                
+              
+            
+            
+              DOUTRCMD
+              Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. 
+              5
+              5
+              write-only
+            
+            
+              DOUTLC
+              Count Mode for Stopping Output Image Data Lines
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Count mode for stopping the output of image data lines is off. 
+                  #0
+                
+                
+                  1
+                  Count mode for stopping the output of image data lines is on
+                  #1
+                
+              
+            
+            
+              DOUTSWAP
+              Byte/Word Swap Output image data in decompression is swapped. 
+              0
+              2
+              read-write
+              
+                
+                  000
+                  (1) (2) (3) (4) (5) (6) (7) (8) 
+                  #000
+                
+                
+                  001
+                  (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 
+                  #001
+                
+                
+                  010
+                  (3) (4) (1) (2) (7) (8) (5) (6)  [Halfword swap] 
+                  #010
+                
+                
+                  011
+                  (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] 
+                  #011
+                
+                
+                  100
+                  (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] 
+                  #100
+                
+                
+                  101
+                  (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] 
+                  #101
+                
+                
+                  110
+                  (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] 
+                  #110
+                
+                
+                  111
+                  (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] 
+                  #111
+                
+              
+            
+          
+        
+        
+          JIFDSA
+          JPEG Interface Decompression Source Address Register
+          0x05C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DSA
+              Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. 
+              0
+              31
+              read-write
+            
+          
+        
+        
+          JIFDDOFST
+          JPEG Interface Decompression Line Offset Register
+          0x060
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DDMW
+              Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. 
+              0
+              14
+              read-write
+            
+          
+        
+        
+          JIFDDA
+          JPEG Interface Decompression Destination Address Register
+          0x064
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DDA
+              Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. 
+              0
+              31
+              read-write
+            
+          
+        
+        
+          JIFDSDC
+          JPEG Interface Decompression Source Data Count Register
+          0x068
+          32
+          read-write
+          0xFFF8FFF8
+          0xFFFFFFFF
+          
+            
+              JDATAS
+               Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. 
+              0
+              15
+              read-write
+            
+          
+        
+        
+          JIFDDLC
+          JPEG Interface Decompression Destination Line Count Register
+          0x06C
+          32
+          read-write
+          0xFFF8FFF8
+          0xFFFFFFFF
+          
+            
+              LINES
+              Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          JIFDADT
+          JPEG Interface Decompression alpha Set Register 
+          0x070
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              ALPHA
+              Setting of the alpha value for output in ARGB8888 format.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          JINTE1
+          JPEG Interrupt Enable Register 1
+          0x08C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CBTEN
+               Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disables an interrupt request. 
+                  #0
+                
+                
+                  1
+                  Enables an interrupt request. 
+                  #1
+                
+              
+            
+            
+              DINLEN
+               Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disables an interrupt request. 
+                  #0
+                
+                
+                  1
+                  Enables an interrupt request. 
+                  #1
+                
+              
+            
+            
+              DBTEN
+              Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disables an interrupt request. 
+                  #0
+                
+                
+                  1
+                  Enables an interrupt request. 
+                  #1
+                
+              
+            
+            
+              JINEN
+              Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disables an interrupt request. 
+                  #0
+                
+                
+                  1
+                  Enables an interrupt request. 
+                  #1
+                
+              
+            
+            
+              DOUTLEN
+              Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disables an interrupt request. 
+                  #0
+                
+                
+                  1
+                  Enables an interrupt request.
+                  #1
+                
+              
+            
+          
+        
+        
+          JINTS1
+          JPEG Interrupt Status Register 1
+          0x090
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CBTF
+               This bit is set to 1 when the last output coded data is written in compression.
+              6
+              6
+              read-write
+              modify
+            
+            
+              DINLF
+              This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression.  This bit is valid only when the DINLC bit in JIFECNT is set to 1. 
+              5
+              5
+              read-write
+              modify
+            
+            
+              DBTF
+               This bit is set to 1 when the last output image data is written in decompression. 
+              2
+              2
+              read-write
+              modify
+            
+            
+              JINF
+               This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression.  This bit is valid only when the JINC bit in JIFDCNT is set to 1.
+              1
+              1
+              read-write
+              modify
+            
+            
+              DOUTLF
+              In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. 
+              0
+              0
+              read-write
+              modify
+            
+          
+        
+        
+          64
+          0x1
+          JCQTBL0[%s]
+          Quantization Table 0
+          0x0100
+          8
+          write-only
+          0x00
+          0x00
+        
+        
+          JCQTBL1[%s]
+          Quantization Table 1
+          0x0140
+        
+        
+          JCQTBL2[%s]
+          Quantization Table 2
+          0x0180
+        
+        
+          JCQTBL3[%s]
+          Quantization Table 3
+          0x01C0
+        
+        
+          28
+          0x1
+          JCHTBD0[%s]
+          DC Huffman Table 0
+          0x0200
+          8
+          read-write
+          0x00
+          0x00
+        
+        
+          JCHTBD1[%s]
+          DC Huffman Table 1
+          0x0300
+        
+        
+          178
+          0x1
+          JCHTBA0[%s]
+          AC Huffman Table 0
+          0x0220
+          8
+          read-write
+          0x00
+          0x00
+        
+        
+          JCHTBA1[%s]
+          DC Huffman Table 1
+          0x0320
+        
+      
+    
+    
+      R_KINT
+      Key Interrupt Function
+      0x40080000
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000008
+        0x01
+        registers
+      
+      
+        
+          KRCTL
+          KEY Return Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              KRMD
+              Usage of Key Interrupt Flags(KR0 to KR7)
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Do not use key interrupt flags
+                  #0
+                
+                
+                  1
+                  Use key interrupt flags.
+                  #1
+                
+              
+            
+            
+              KREG
+              Detection Edge Selection (KRF0 to KRF7)
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Falling edge
+                  #0
+                
+                
+                  1
+                  Rising edge
+                  #1
+                
+              
+            
+          
+        
+        
+          KRF
+          KEY Return Flag Register
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+          zeroToClear
+          modify
+          
+            
+              KRF7
+              Key interrupt flag 7
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF6
+              Key interrupt flag 6
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF5
+              Key interrupt flag 5
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF4
+              Key interrupt flag 4
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF3
+              Key interrupt flag 3
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF2
+              Key interrupt flag 2
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF1
+              Key interrupt flag 1
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+            
+              KRF0
+              Key interrupt flag 0
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No interrupt detected
+                  #0
+                
+                
+                  1
+                  Interrupt detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          KRM
+          KEY Return Mode Register
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              KRM7
+              Key interrupt mode control 7
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM6
+              Key interrupt mode control 6
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM5
+              Key interrupt mode control 5
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM4
+              Key interrupt mode control 4
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM3
+              Key interrupt mode control 3
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM2
+              Key interrupt mode control 2
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM1
+              Key interrupt mode control 1
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+            
+              KRM0
+              Key interrupt mode control 0
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Does not detect key interrupt signal
+                  #0
+                
+                
+                  1
+                  Detect key interrupt signal.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_MMF
+      Memory Mirror Function
+      0x40001000
+      
+        0x00000000
+        0x008
+        registers
+      
+      
+        
+          MMSFR
+          MemMirror Special Function Register
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              KEY
+              MMSFR Key Code
+              24
+              31
+              write-only
+              
+                
+                  0xDB
+                  Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB.
+                  0xDB
+                
+                
+                  others
+                  Writing to the MEMMIRADDR bits are invalid.
+                  true
+                
+              
+            
+            
+              MEMMIRADDR
+              Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0.
+              7
+              22
+              read-write
+            
+          
+        
+        
+          MMEN
+          MemMirror Enable Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              KEY
+              MMEN Key Code
+              24
+              31
+              write-only
+              
+                
+                  0xDB
+                  Writing to the EN bit is valid, when the KEY bits are written 0xDB.
+                  0xDB
+                
+                
+                  others
+                  Writing to the EN bit is invalid.
+                  true
+                
+              
+            
+            
+              EN
+              Memory Mirror Function Enable
+              0
+              0
+              read-write
+              
+                
+                  1
+                  Memory Mirror Function is enabled.
+                  #1
+                
+                
+                  0
+                  Memory Mirror Function is disabled.
+                  #0
+                
+              
+            
+          
+        
+      
+    
+    
+      R_MPU_MMPU
+      Bus Master MPU
+      0x40000000
+      
+        0x00000000
+        0x02
+        registers
+      
+      
+        0x00000102
+        0x02
+        registers
+      
+      
+        0x00000200
+        0x02
+        registers
+      
+      
+        0x00000204
+        0x008
+        registers
+      
+      
+        0x00000210
+        0x02
+        registers
+      
+      
+        0x00000214
+        0x008
+        registers
+      
+      
+        0x00000220
+        0x02
+        registers
+      
+      
+        0x00000224
+        0x008
+        registers
+      
+      
+        0x00000230
+        0x02
+        registers
+      
+      
+        0x00000234
+        0x008
+        registers
+      
+      
+        0x00000240
+        0x02
+        registers
+      
+      
+        0x00000244
+        0x008
+        registers
+      
+      
+        0x00000250
+        0x02
+        registers
+      
+      
+        0x00000254
+        0x008
+        registers
+      
+      
+        0x00000260
+        0x02
+        registers
+      
+      
+        0x00000264
+        0x008
+        registers
+      
+      
+        0x00000270
+        0x02
+        registers
+      
+      
+        0x00000274
+        0x008
+        registers
+      
+      
+        0x00000280
+        0x02
+        registers
+      
+      
+        0x00000284
+        0x008
+        registers
+      
+      
+        0x00000290
+        0x02
+        registers
+      
+      
+        0x00000294
+        0x008
+        registers
+      
+      
+        0x000002A0
+        0x02
+        registers
+      
+      
+        0x000002A4
+        0x008
+        registers
+      
+      
+        0x000002B0
+        0x02
+        registers
+      
+      
+        0x000002B4
+        0x008
+        registers
+      
+      
+        0x000002C0
+        0x02
+        registers
+      
+      
+        0x000002C4
+        0x008
+        registers
+      
+      
+        0x000002D0
+        0x02
+        registers
+      
+      
+        0x000002D4
+        0x008
+        registers
+      
+      
+        0x000002E0
+        0x02
+        registers
+      
+      
+        0x000002E4
+        0x008
+        registers
+      
+      
+        0x000002F0
+        0x02
+        registers
+      
+      
+        0x000002F4
+        0x008
+        registers
+      
+      
+        0x00000300
+        0x02
+        registers
+      
+      
+        0x00000304
+        0x008
+        registers
+      
+      
+        0x00000310
+        0x02
+        registers
+      
+      
+        0x00000314
+        0x008
+        registers
+      
+      
+        0x00000320
+        0x02
+        registers
+      
+      
+        0x00000324
+        0x008
+        registers
+      
+      
+        0x00000330
+        0x02
+        registers
+      
+      
+        0x00000334
+        0x008
+        registers
+      
+      
+        0x00000340
+        0x02
+        registers
+      
+      
+        0x00000344
+        0x008
+        registers
+      
+      
+        0x00000350
+        0x02
+        registers
+      
+      
+        0x00000354
+        0x008
+        registers
+      
+      
+        0x00000360
+        0x02
+        registers
+      
+      
+        0x00000364
+        0x008
+        registers
+      
+      
+        0x00000370
+        0x02
+        registers
+      
+      
+        0x00000374
+        0x008
+        registers
+      
+      
+        0x00000380
+        0x02
+        registers
+      
+      
+        0x00000384
+        0x008
+        registers
+      
+      
+        0x00000390
+        0x02
+        registers
+      
+      
+        0x00000394
+        0x008
+        registers
+      
+      
+        0x000003A0
+        0x02
+        registers
+      
+      
+        0x000003A4
+        0x008
+        registers
+      
+      
+        0x000003B0
+        0x02
+        registers
+      
+      
+        0x000003B4
+        0x008
+        registers
+      
+      
+        0x000003C0
+        0x02
+        registers
+      
+      
+        0x000003C4
+        0x008
+        registers
+      
+      
+        0x000003D0
+        0x02
+        registers
+      
+      
+        0x000003D4
+        0x008
+        registers
+      
+      
+        0x000003E0
+        0x02
+        registers
+      
+      
+        0x000003E4
+        0x008
+        registers
+      
+      
+        0x000003F0
+        0x02
+        registers
+      
+      
+        0x000003F4
+        0x008
+        registers
+      
+      
+        0x00000400
+        0x02
+        registers
+      
+      
+        0x00000502
+        0x02
+        registers
+      
+      
+        0x00000600
+        0x02
+        registers
+      
+      
+        0x00000604
+        0x008
+        registers
+      
+      
+        0x00000610
+        0x02
+        registers
+      
+      
+        0x00000614
+        0x008
+        registers
+      
+      
+        0x00000620
+        0x02
+        registers
+      
+      
+        0x00000624
+        0x008
+        registers
+      
+      
+        0x00000630
+        0x02
+        registers
+      
+      
+        0x00000634
+        0x008
+        registers
+      
+      
+        0x00000640
+        0x02
+        registers
+      
+      
+        0x00000644
+        0x008
+        registers
+      
+      
+        0x00000650
+        0x02
+        registers
+      
+      
+        0x00000654
+        0x008
+        registers
+      
+      
+        0x00000660
+        0x02
+        registers
+      
+      
+        0x00000664
+        0x008
+        registers
+      
+      
+        0x00000670
+        0x02
+        registers
+      
+      
+        0x00000674
+        0x008
+        registers
+      
+      
+        0x00000680
+        0x02
+        registers
+      
+      
+        0x00000684
+        0x008
+        registers
+      
+      
+        0x00000690
+        0x02
+        registers
+      
+      
+        0x00000694
+        0x008
+        registers
+      
+      
+        0x000006A0
+        0x02
+        registers
+      
+      
+        0x000006A4
+        0x008
+        registers
+      
+      
+        0x000006B0
+        0x02
+        registers
+      
+      
+        0x000006B4
+        0x008
+        registers
+      
+      
+        0x000006C0
+        0x02
+        registers
+      
+      
+        0x000006C4
+        0x008
+        registers
+      
+      
+        0x000006D0
+        0x02
+        registers
+      
+      
+        0x000006D4
+        0x008
+        registers
+      
+      
+        0x000006E0
+        0x02
+        registers
+      
+      
+        0x000006E4
+        0x008
+        registers
+      
+      
+        0x000006F0
+        0x02
+        registers
+      
+      
+        0x000006F4
+        0x008
+        registers
+      
+      
+        0x00000700
+        0x02
+        registers
+      
+      
+        0x00000704
+        0x008
+        registers
+      
+      
+        0x00000710
+        0x02
+        registers
+      
+      
+        0x00000714
+        0x008
+        registers
+      
+      
+        0x00000720
+        0x02
+        registers
+      
+      
+        0x00000724
+        0x008
+        registers
+      
+      
+        0x00000730
+        0x02
+        registers
+      
+      
+        0x00000734
+        0x008
+        registers
+      
+      
+        0x00000740
+        0x02
+        registers
+      
+      
+        0x00000744
+        0x008
+        registers
+      
+      
+        0x00000750
+        0x02
+        registers
+      
+      
+        0x00000754
+        0x008
+        registers
+      
+      
+        0x00000760
+        0x02
+        registers
+      
+      
+        0x00000764
+        0x008
+        registers
+      
+      
+        0x00000770
+        0x02
+        registers
+      
+      
+        0x00000774
+        0x008
+        registers
+      
+      
+        0x00000780
+        0x02
+        registers
+      
+      
+        0x00000784
+        0x008
+        registers
+      
+      
+        0x00000790
+        0x02
+        registers
+      
+      
+        0x00000794
+        0x008
+        registers
+      
+      
+        0x000007A0
+        0x02
+        registers
+      
+      
+        0x000007A4
+        0x008
+        registers
+      
+      
+        0x000007B0
+        0x02
+        registers
+      
+      
+        0x000007B4
+        0x008
+        registers
+      
+      
+        0x000007C0
+        0x02
+        registers
+      
+      
+        0x000007C4
+        0x008
+        registers
+      
+      
+        0x000007D0
+        0x02
+        registers
+      
+      
+        0x000007D4
+        0x008
+        registers
+      
+      
+        0x000007E0
+        0x02
+        registers
+      
+      
+        0x000007E4
+        0x008
+        registers
+      
+      
+        0x000007F0
+        0x02
+        registers
+      
+      
+        0x000007F4
+        0x008
+        registers
+      
+      
+        0x00000800
+        0x02
+        registers
+      
+      
+        0x00000902
+        0x02
+        registers
+      
+      
+        0x00000A00
+        0x02
+        registers
+      
+      
+        0x00000A04
+        0x008
+        registers
+      
+      
+        0x00000A10
+        0x02
+        registers
+      
+      
+        0x00000A14
+        0x008
+        registers
+      
+      
+        0x00000A20
+        0x02
+        registers
+      
+      
+        0x00000A24
+        0x008
+        registers
+      
+      
+        0x00000A30
+        0x02
+        registers
+      
+      
+        0x00000A34
+        0x008
+        registers
+      
+      
+        0x00000A40
+        0x02
+        registers
+      
+      
+        0x00000A44
+        0x008
+        registers
+      
+      
+        0x00000A50
+        0x02
+        registers
+      
+      
+        0x00000A54
+        0x008
+        registers
+      
+      
+        0x00000A60
+        0x02
+        registers
+      
+      
+        0x00000A64
+        0x008
+        registers
+      
+      
+        0x00000A70
+        0x02
+        registers
+      
+      
+        0x00000A74
+        0x008
+        registers
+      
+      
+        0x00000A80
+        0x02
+        registers
+      
+      
+        0x00000A84
+        0x008
+        registers
+      
+      
+        0x00000A90
+        0x02
+        registers
+      
+      
+        0x00000A94
+        0x008
+        registers
+      
+      
+        0x00000AA0
+        0x02
+        registers
+      
+      
+        0x00000AA4
+        0x008
+        registers
+      
+      
+        0x00000AB0
+        0x02
+        registers
+      
+      
+        0x00000AB4
+        0x008
+        registers
+      
+      
+        0x00000AC0
+        0x02
+        registers
+      
+      
+        0x00000AC4
+        0x008
+        registers
+      
+      
+        0x00000AD0
+        0x02
+        registers
+      
+      
+        0x00000AD4
+        0x008
+        registers
+      
+      
+        0x00000AE0
+        0x02
+        registers
+      
+      
+        0x00000AE4
+        0x008
+        registers
+      
+      
+        0x00000AF0
+        0x02
+        registers
+      
+      
+        0x00000AF4
+        0x008
+        registers
+      
+      
+        0x00000B00
+        0x02
+        registers
+      
+      
+        0x00000B04
+        0x008
+        registers
+      
+      
+        0x00000B10
+        0x02
+        registers
+      
+      
+        0x00000B14
+        0x008
+        registers
+      
+      
+        0x00000B20
+        0x02
+        registers
+      
+      
+        0x00000B24
+        0x008
+        registers
+      
+      
+        0x00000B30
+        0x02
+        registers
+      
+      
+        0x00000B34
+        0x008
+        registers
+      
+      
+        0x00000B40
+        0x02
+        registers
+      
+      
+        0x00000B44
+        0x008
+        registers
+      
+      
+        0x00000B50
+        0x02
+        registers
+      
+      
+        0x00000B54
+        0x008
+        registers
+      
+      
+        0x00000B60
+        0x02
+        registers
+      
+      
+        0x00000B64
+        0x008
+        registers
+      
+      
+        0x00000B70
+        0x02
+        registers
+      
+      
+        0x00000B74
+        0x008
+        registers
+      
+      
+        0x00000B80
+        0x02
+        registers
+      
+      
+        0x00000B84
+        0x008
+        registers
+      
+      
+        0x00000B90
+        0x02
+        registers
+      
+      
+        0x00000B94
+        0x008
+        registers
+      
+      
+        0x00000BA0
+        0x02
+        registers
+      
+      
+        0x00000BA4
+        0x008
+        registers
+      
+      
+        0x00000BB0
+        0x02
+        registers
+      
+      
+        0x00000BB4
+        0x008
+        registers
+      
+      
+        0x00000BC0
+        0x02
+        registers
+      
+      
+        0x00000BC4
+        0x008
+        registers
+      
+      
+        0x00000BD0
+        0x02
+        registers
+      
+      
+        0x00000BD4
+        0x008
+        registers
+      
+      
+        0x00000BE0
+        0x02
+        registers
+      
+      
+        0x00000BE4
+        0x008
+        registers
+      
+      
+        0x00000BF0
+        0x02
+        registers
+      
+      
+        0x00000BF4
+        0x008
+        registers
+      
+      
+        
+          3
+          0x400
+          
+            
+              A
+              A
+              0
+            
+            
+              B
+              B
+              1
+            
+            
+              C
+              C
+              2
+            
+          
+          MMPU[%s]
+          Bus Master MPU Registers
+          0x0000
+          
+            CTL
+            Bus Master MPU Control Register
+            0x000
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                KEY
+                Write Keyword The data written to these bits are not stored.
+                8
+                15
+                write-only
+                
+                  
+                    0xA5
+                    Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5.
+                    0xA5
+                  
+                  
+                    others
+                    Writing to the OAD and ENABLE bit is invalid.
+                    true
+                  
+                
+              
+              
+                OAD
+                Operation after detection
+                1
+                1
+                read-write
+                
+                  
+                    0
+                    Non-maskable interrupt.
+                    #0
+                  
+                  
+                    1
+                    Internal reset.
+                    #1
+                  
+                
+              
+              
+                ENABLE
+                Master Group enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Master Group is disabled. Permission of all regions.
+                    #0
+                  
+                  
+                    1
+                    Master Group is enabled. Protection of all regions.
+                    #1
+                  
+                
+              
+            
+          
+          
+            PT
+            Protection of Register
+            0x102
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                KEY
+                Write Keyword The data written to these bits are not stored.
+                8
+                15
+                write-only
+                
+                  
+                    0xA5
+                    Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.
+                    0xA5
+                  
+                  
+                    others
+                    Writing to the PROTECT bit is invalid.
+                    true
+                  
+                
+              
+              
+                PROTECT
+                Protection of region register
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    All Bus Master MPU register writing is possible.
+                    #0
+                  
+                  
+                    1
+                    All Bus Master MPU register writing is protected. Read is possible.
+                    #1
+                  
+                
+              
+            
+          
+          
+            32
+            0x10
+            REGION[%s]
+            Address Region registers
+            0x0200
+            
+              C
+              Access Control Register
+              0x00
+              16
+              read-write
+              0x0000
+              0xFFFF
+              
+                
+                  WP
+                  Write protection
+                  2
+                  2
+                  read-write
+                  
+                    
+                      0
+                      Write permission
+                      #0
+                    
+                    
+                      1
+                      Write protection
+                      #1
+                    
+                  
+                
+                
+                  RP
+                  Read protection
+                  1
+                  1
+                  read-write
+                  
+                    
+                      0
+                      Read permission
+                      #0
+                    
+                    
+                      1
+                      Read protection
+                      #1
+                    
+                  
+                
+                
+                  ENABLE
+                  Region enable
+                  0
+                  0
+                  read-write
+                  
+                    
+                      0
+                      Group m Region n unit is disabled
+                      #0
+                    
+                    
+                      1
+                      Group m Region n unit is enabled
+                      #1
+                    
+                  
+                
+              
+            
+            
+              S
+              Start Address Register
+              0x04
+              32
+              read-write
+              0x00000000
+              0xFFFFFFFF
+              
+                
+                  MMPUSmn
+                  Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0.
+                  0
+                  31
+                  read-write
+                
+              
+            
+            
+              E
+              End Address Register
+              0x08
+              32
+              read-write
+              0x00000003
+              0xFFFFFFFF
+              
+                
+                  MMPUEmn
+                  Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1.
+                  0
+                  31
+                  read-write
+                
+              
+            
+          
+        
+      
+    
+    
+      R_MPU_SMPU
+      Bus Slave MPU
+      0x40000C00
+      
+        0x00000000
+        0x02
+        registers
+      
+      
+        0x00000010
+        0x02
+        registers
+      
+      
+        0x00000014
+        0x02
+        registers
+      
+      
+        0x00000018
+        0x02
+        registers
+      
+      
+        0x0000001C
+        0x02
+        registers
+      
+      
+        0x00000020
+        0x02
+        registers
+      
+      
+        0x00000024
+        0x02
+        registers
+      
+      
+        0x00000028
+        0x02
+        registers
+      
+      
+        0x0000002C
+        0x02
+        registers
+      
+      
+        0x00000030
+        0x02
+        registers
+      
+      
+        0x00000034
+        0x02
+        registers
+      
+      
+        
+          10
+          0x4
+          
+            
+              MBIU
+              MBIU
+              0
+            
+            
+              FBIU
+              FBIU
+              1
+            
+            
+              R_SRAM
+              R_SRAM
+              2
+            
+            
+              SRAM1
+              SRAM1
+              3
+            
+            
+              P0BIU
+              P0BIU
+              4
+            
+            
+              P2BIU
+              P2BIU
+              5
+            
+            
+              P6BIU
+              P6BIU
+              6
+            
+            
+              B7BIU
+              B7BIU
+              7
+            
+            
+              EXBIU
+              EXBIU
+              8
+            
+            
+              EXBIU2
+              EXBIU2
+              9
+            
+          
+          SMPU[%s]
+          Access Control Structure for MBIU
+          0x10
+          
+            R
+            Access Control Register for MBIU
+            0x00
+            16
+            read-write
+            0x2000
+            0xFFFF
+            
+              
+                WPSRAMHS
+                SRAMHS Write Protection
+                15
+                15
+                read-write
+                
+                  
+                    0
+                    Memory protection for SRAMHS writes from master group A, B, and C disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for SRAMHS writes from master group A, B, and C enabled.
+                    #1
+                  
+                
+              
+              
+                RPSRAMHS
+                SRAMHS Read Protection
+                14
+                14
+                read-write
+                
+                  
+                    0
+                    Memory protection for SRAMHS reads from master group A, B, and C disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for SRAMHS reads from master group A, B, and C enabled.
+                    #1
+                  
+                
+              
+              
+                WPFLI
+                Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.)
+                13
+                13
+                read-write
+                
+                  
+                    0
+                    Setting prohibited
+                    #0
+                  
+                  
+                    1
+                    Memory protection for code flash memory writes from master group A, B, and C enabled.
+                    #1
+                  
+                
+              
+              
+                RPFLI
+                Code Flash Memory Read Protection
+                12
+                12
+                read-write
+                
+                  
+                    0
+                    Memory protection for code flash memory reads from master group A, B, and C disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for code flash memory reads from master group A, B, and C enabled.
+                    #1
+                  
+                
+              
+              
+                WPGRPC
+                Master Group C Write protection
+                7
+                7
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group C writes disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group C writes enabled.
+                    #1
+                  
+                
+              
+              
+                RPGRPC
+                Master Group C Read protection
+                6
+                6
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group C reads disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group C reads enabled.
+                    #1
+                  
+                
+              
+              
+                WPGRPB
+                Master Group B Write protection
+                5
+                5
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group B writes disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group B writes enabled.
+                    #1
+                  
+                
+              
+              
+                RPGRPB
+                Master Group B Read protection
+                4
+                4
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group B reads disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group B reads enabled.
+                    #1
+                  
+                
+              
+              
+                WPGRPA
+                Master Group A Write protection
+                3
+                3
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group A writes disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group A writes enabled.
+                    #1
+                  
+                
+              
+              
+                RPGRPA
+                Master Group A Read protection
+                2
+                2
+                read-write
+                
+                  
+                    0
+                    Memory protection for master group A reads disabled
+                    #0
+                  
+                  
+                    1
+                    Memory protection for master group A reads enabled.
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+          SMPUCTL
+          Slave MPU Control Register
+          0x00
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              KEY
+              Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit.
+              8
+              15
+              write-only
+              
+                
+                  0xA5
+                  Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5.
+                  0xA5
+                
+                
+                  others
+                  Writing to the  PROTECT and OAD bit is invalid.
+                  true
+                
+              
+            
+            
+              PROTECT
+              Protection of register 
+              1
+              1
+              read-write
+              
+                
+                  0
+                  All Bus Slave register writing is possible.
+                  #0
+                
+                
+                  1
+                  All Bus Slave register writing is protected. Read is possible.
+                  #1
+                
+              
+            
+            
+              OAD
+              Master Group enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Non-maskable interrupt.
+                  #0
+                
+                
+                  1
+                  Internal reset.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_MPU_SPMON
+      CPU Stack Pointer Monitor
+      0x40000D00
+      
+        0x00000000
+        0x02
+        registers
+      
+      
+        0x00000004
+        0x00E
+        registers
+      
+      
+        0x00000014
+        0x00C
+        registers
+      
+      
+        
+          2
+          0x10
+          
+            
+              M
+              M
+              0
+            
+            
+              P
+              P
+              1
+            
+          
+          SP[%s]
+          Stack Pointer Monitor
+          0x0000
+          
+            OAD
+            Stack Pointer Monitor Operation After Detection Register
+            0x00
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                KEY
+                Write Keyword The data written to these bits are not stored.
+                8
+                15
+                write-only
+                
+                  
+                    0xA5
+                    Writing to the OAD bit is valid, when the KEY bits are written 0xA5.
+                    0xA5
+                  
+                  
+                    others
+                    Writing to the OAD bit is invalid.
+                    true
+                  
+                
+              
+              
+                OAD
+                Operation after detection
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Non-maskable interrupt
+                    #0
+                  
+                  
+                    1
+                    Reset.
+                    #1
+                  
+                
+              
+            
+          
+          
+            CTL
+            Stack Pointer Monitor Access Control Register
+            0x04
+            16
+            read-write
+            0x0000
+            0xFEFF
+            
+              
+                ERROR
+                Stack Pointer Monitor Error Flag
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    Stack pointer has not overflowed or underflowed
+                    #0
+                  
+                  
+                    1
+                    Stack pointer has overflowed or underflowed
+                    #1
+                  
+                
+              
+              
+                ENABLE
+                Stack Pointer Monitor Enable
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Stack pointer monitor is disabled
+                    #0
+                  
+                  
+                    1
+                    Stack pointer monitor is enabled.
+                    #1
+                  
+                
+              
+            
+          
+          
+            PT
+            Stack Pointer Monitor Protection Register
+            0x06
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                KEY
+                Write Keyword The data written to these bits are not stored.
+                8
+                15
+                write-only
+                
+                  
+                    0xA5
+                    Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5.
+                    0xA5
+                  
+                  
+                    others
+                    Writing to the PROTECT bit is invalid.
+                    true
+                  
+                
+              
+              
+                PROTECT
+                Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Stack Pointer Monitor register writing is possible.
+                    #0
+                  
+                  
+                    1
+                    Stack Pointer Monitor register writing is protected.
+                    #1
+                  
+                
+              
+            
+          
+          
+            SA
+            Stack Pointer Monitor Start Address Register
+            0x08
+            32
+            read-write
+            0x00000000
+            0x00000003
+            
+              
+                MSPMPUSA
+                Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC         The low-order 2 bits are fixed to 0.
+                0
+                31
+                read-write
+                
+                  
+                    0x1FF00000
+                    0x200FFFFC
+                  
+                
+              
+            
+          
+          
+            EA
+            Stack Pointer Monitor End Address Register
+            0x0C
+            32
+            read-write
+            0x00000003
+            0x00000003
+            
+              
+                MSPMPUEA
+                Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF         The low-order 2 bits are fixed to 1.
+                0
+                31
+                read-write
+                
+                  
+                    0x1FF00003
+                    0x200FFFFF
+                  
+                
+              
+            
+          
+        
+      
+    
+    
+      R_MSTP
+      System-Module Stop
+      0x40047000
+      
+        0x00000000
+        0x00C
+        registers
+      
+      
+        
+          MSTPCRB
+          Module Stop Control Register B
+          0x00
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              MSTPB31
+              Serial Communication Interface 0 Module Stop
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB30
+              Serial Communication Interface 1 Module Stop
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB29
+              Serial Communication Interface 2 Module Stop
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB28
+              Serial Communication Interface 3 Module Stop
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB27
+              Serial Communication Interface 4 Module Stop
+              27
+              27
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB26
+              Serial Communication Interface 5 Module Stop
+              26
+              26
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB25
+              Serial Communication Interface 6 Module Stop
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB24
+              Serial Communication Interface 7 Module Stop
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB23
+              Serial Communication Interface 8 Module Stop
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB22
+              Serial Communication Interface 9 Module Stop
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              Reserved
+              These bits are read as 11. The write value should be 11.
+              20
+              21
+              read-write
+            
+            
+              MSTPB19
+              Serial Peripheral Interface 0 Module Stop
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB18
+              Serial Peripheral Interface Module Stop
+              18
+              18
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              Reserved
+              These bits are read as 11. The write value should be 11.
+              16
+              17
+              read-write
+            
+            
+              MSTPB15
+              ETHERC0 and EDMAC0 Module Stop
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB14
+              ETHERC1 and EDMAC1 Module Stop
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB13
+              EPTPC and PTPEDMAC Module Stop
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB12
+              Universal Serial Bus 2.0 HS Interface Module Stop
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB11
+              Universal Serial Bus 2.0 FS Interface Module Stop
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              Reserved
+              This bit is read as 1. The write value should be 1.
+              10
+              10
+              read-write
+            
+            
+              MSTPB9
+              I2C Bus Interface 0 Module Stop
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB8
+              I2C Bus Interface 1 Module Stop
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB7
+              I2C Bus Interface 2 Module Stop
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB6
+              Queued Serial Peripheral Interface Module Stop
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB5
+              IrDA Module Stop
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              Reserved
+              These bits are read as 11. The write value should be 11.
+              3
+              4
+              read-write
+            
+            
+              MSTPB2
+              RCAN0 Module Stop
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPB1
+              RCAN1 Module Stop
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              Reserved
+              This bit is read as 1. The write value should be 1.
+              0
+              0
+              read-write
+            
+          
+        
+        
+          MSTPCRC
+          Module Stop Control Register C
+          0x04
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              MSTPC31
+              AES Module Stop
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC28
+              Random Number Generator Module Stop
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state.
+                  #1
+                
+              
+            
+            
+              MSTPC14
+              Event Link Controller Module Stop
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC13
+              Data Operation Circuit Module Stop
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC4
+              Segment LCD Controller Module Stop
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC3
+              Capacitive Touch Sensing Unit Module Stop
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC1
+              CRC Calculator Module Stop
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPC0
+              CAC Module Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+          
+        
+        
+          MSTPCRD
+          Module Stop Control Register D
+          0x08
+          32
+          read-write
+          0xFFFFFFFF
+          0xFFFFFFFF
+          
+            
+              MSTPD31
+              Operational Amplifier Module Stop
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD29
+              Comparator-LP Module Stop
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD28
+              ACMPHS0 Module Stop
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD20
+              12-bit D/A Converter Module Stop
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD19
+              8-Bit D/A Converter Module Stop
+              19
+              19
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD17
+              24-bit Sigma-Delta A/DConverter Module Stop
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD16
+              16-Bit A/D Converter Module Stop
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD14
+              POEG Module Stop
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD6
+              GPT ch6 - ch1 Module Stop
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD5
+              GPT ch0 Module Stop
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD3
+              AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPD2
+              AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_OPAMP
+      Operational Amplifier
+      0x40086000
+      
+        0x00000008
+        0x005
+        registers
+      
+      
+        0x0000000E
+        0x00C
+        registers
+      
+      
+        0x0000001F
+        0x007
+        registers
+      
+      
+        
+          4
+          0x3
+          AMP[%s]
+          Input and Output Selectors for Operational Amplifier %s
+          0x0E
+          read-write
+          
+            OS
+            Output Select Register 
+            0
+            8
+            read-write
+            0x00
+            0xFF
+            
+          
+          
+            PS
+            Plus Input Select Register 
+            2
+            8
+            read-write
+            0x00
+            0xFF
+            
+          
+          
+            MS
+            Minus Input Select Register
+            1
+            8
+            read-write
+            0x00
+            0xFF
+            
+          
+        
+        
+          3
+          2
+          AMPOT[%s]
+          Operational Amplifier n Offset Trimming Registers
+          0x20
+          read-write
+          
+            P
+            Operational Amplifier n Offset Trimming Pch Register
+            0
+            8
+            read-write
+            0
+            0xD0
+            
+              
+                TRMP
+                AMPn input offset trimming Pch side
+                0
+                4
+                read-write
+              
+            
+          
+          
+            N
+            Operational Amplifier n Offset Trimming Nch Register
+            1
+            8
+            
+              
+                TRMN
+                AMPn input offset trimming Nch side
+                0
+                4
+              
+            
+          
+        
+        
+          AMPMC
+          Operational amplifier mode control register
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              AMPSP
+              Operation mode selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Low-power mode (low-speed).
+                  #0
+                
+                
+                  1
+                  High-speed mode.
+                  #1
+                
+              
+            
+            
+              3
+              1
+              AMPPC%s
+              Operational amplifier precharge control status
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Precharging is stopped.
+                  #0
+                
+                
+                  1
+                  Precharging is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          AMPTRM
+          Operational amplifier trigger mode control register
+          0x09
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              4
+              2
+              AMPTRM%s
+              Operational amplifier function activation/stop trigger control 
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Software trigger mode.
+                  #00
+                
+                
+                  01
+                  An activation and A/D trigger mode.
+                  #01
+                
+                
+                  10
+                  Setting prohibited.
+                  #10
+                
+                
+                  11
+                  An activation and A/D trigger mode.
+                  #11
+                
+              
+            
+          
+        
+        
+          AMPTRS
+          Operational Amplifier Activation Trigger Select Register
+          0x0A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              AMPTRS
+              ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. 
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3
+                  #00
+                
+                
+                  01
+                  Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1
+                  #01
+                
+                
+                  10
+                  Setting prohibited
+                  #10
+                
+                
+                  11
+                  Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0
+                  #11
+                
+              
+            
+          
+        
+        
+          AMPC
+          Operational amplifier control register
+          0x0B
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              IREFE
+              Operation control of operational amplifier reference current circuit
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Operational amplifier reference current circuit is stopped.
+                  #0
+                
+                
+                  1
+                  Operation of operational amplifier reference current circuit is enabled.
+                  #1
+                
+              
+            
+            
+              4
+              1
+              AMPE%s
+              Operation control of operational amplifier
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operation amplifier is stopped.
+                  #0
+                
+                
+                  1
+                  Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          AMPMON
+          Operational amplifier monitor register
+          0x0C
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              4
+              1
+              AMPMON%s
+              Operational amplifier status
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Operational amplifier is stopped.
+                  #0
+                
+                
+                  1
+                  Operational amplifier is operating.
+                  #1
+                
+              
+            
+          
+        
+        
+          AMPCPC
+          Operational amplifier switch charge pump control register
+          0x1A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              3
+              1
+              PUMP%sEN
+              charge pump for AMP%s enable/disable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  charge pump for AMP is disabled.
+                  #0
+                
+                
+                  1
+                  charge pump for AMP is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          AMPUOTE
+          Operational Amplifier User Offset Trimming Enable Register
+          0x1F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              3
+              1
+              AMP%sTE
+              AMP%sOT write enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Not possible to write the AMPnOTP and AMPnOTN registers
+                  #0
+                
+                
+                  1
+                  Possible to write the AMPnOTP and AMPnOTN registers
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_PDC
+      Parallel Data Capture Unit
+      0x40094000
+      
+        0x00000000
+        0x01C
+        registers
+      
+      
+        
+          PCCR0
+          PDC Control Register 0
+          0x000
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EDS
+              Endian Select
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Little endian
+                  #0
+                
+                
+                  1
+                  Big endian
+                  #1
+                
+              
+            
+            
+              PCKDIV
+              PCKO Frequency Division Ratio Select
+              11
+              13
+              read-write
+              
+                
+                  000
+                  PCKO/2
+                  #000
+                
+                
+                  001
+                  PCKO/4
+                  #001
+                
+                
+                  010
+                  PCKO/6
+                  #010
+                
+                
+                  011
+                  PCKO/8
+                  #011
+                
+                
+                  100
+                  PCKO/10
+                  #100
+                
+                
+                  101
+                  PCKO/12
+                  #101
+                
+                
+                  110
+                  PCKO/14
+                  #110
+                
+                
+                  111
+                  PCKO/16
+                  #111
+                
+              
+            
+            
+              PCKOE
+              PCKO Output Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  PCKO output is disabled (fixed to the high level)
+                  #0
+                
+                
+                  1
+                  PCKO output is enabled.
+                  #1
+                
+              
+            
+            
+              HERIE
+              Horizontal Byte Number Setting Error Interrupt Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Generation of horizontal byte number setting error interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of horizontal byte number setting error interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              VERIE
+              Vertical Line Number Setting Error Interrupt Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Generation of vertical line number setting error interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of vertical line number setting error interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              UDRIE
+              Underrun Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Generation of underrun interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of underrun interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              OVIE
+              Overrun Interrupt Enable 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Generation of overrun interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of overrun interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              FEIE
+              Frame End Interrupt Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Generation of frame end interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of frame end interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              DFIE
+              Receive Data Ready Interrupt Enable 
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Generation of receive data ready interrupt requests is disabled.
+                  #0
+                
+                
+                  1
+                  Generation of receive data ready interrupt requests is enabled.
+                  #1
+                
+              
+            
+            
+              PRST
+              PDC Reset
+              3
+              3
+              write-only
+              
+                
+                  0
+                  PDC reset is not applied.
+                  #0
+                
+                
+                  1
+                  PDC is reset.
+                  #1
+                
+              
+            
+            
+              HPS
+              HSYNC Signal Polarity Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  HSYNC signal is active high.
+                  #0
+                
+                
+                  1
+                  HSYNC signal is active low.
+                  #1
+                
+              
+            
+            
+              VPS
+              VSYNC Signal Polarity Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  VSYNC signal is active high.
+                  #0
+                
+                
+                  1
+                  VSYNC signal is active low.
+                  #1
+                
+              
+            
+            
+              PCKE
+              Channel 0 GTCNT Count Clear
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operations for reception are stopped.
+                  #0
+                
+                
+                  1
+                  Operations for reception are ongoing.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCCR1
+          PDC Control Register 1 
+          0x004
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PCE
+              PDC Operation Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operations for reception are disabled.
+                  #0
+                
+                
+                  1
+                  Operations for reception are enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCSR
+          PDC Status Register 
+          0x008
+          32
+          read-write
+          0x00000002
+          0xFFFFFFFF
+          
+            
+              HERF
+              Horizontal Byte Number Setting Error Flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Horizontal byte number setting error has not been generated.
+                  #0
+                
+                
+                  1
+                  Horizontal byte number setting error has been generated.
+                  #1
+                
+              
+            
+            
+              VERF
+              Vertical Line Number Setting Error Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Vertical line number setting error has not been generated.
+                  #0
+                
+                
+                  1
+                  Vertical line number setting error has been generated.
+                  #1
+                
+              
+            
+            
+              UDRF
+              Underrun Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Underrun has not been generated.
+                  #0
+                
+                
+                  1
+                  Underrun has been generated.
+                  #1
+                
+              
+            
+            
+              OVRF
+              Overrun Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  FIFO overrun has not been generated.
+                  #0
+                
+                
+                  1
+                  FIFO overrun has been generated.
+                  #1
+                
+              
+            
+            
+              FEF
+              Frame End Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Frame end has not been generated.
+                  #0
+                
+                
+                  1
+                  Frame end has been generated.
+                  #1
+                
+              
+            
+            
+              FEMPF
+              FIFO Empty Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  FIFO is not empty.
+                  #0
+                
+                
+                  1
+                  FIFO is empty.
+                  #1
+                
+              
+            
+            
+              FBSY
+              Frame Busy Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Operations for reception are stopped.
+                  #0
+                
+                
+                  1
+                  Operations for reception are ongoing.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCMONR
+          PDC Pin Monitor Register 
+          0x00C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              HSYNC
+              HSYNC Signal Status Flag 
+              1
+              1
+              read-only
+              
+                
+                  0
+                  HSYNC signal is at the low level.
+                  #0
+                
+                
+                  1
+                  HSYNC signal is at the high level.
+                  #1
+                
+              
+            
+            
+              VSYNC
+              VSYNC Signal Status Flag 
+              0
+              0
+              read-only
+              
+                
+                  0
+                  VSYNC signal is at the low level.
+                  #0
+                
+                
+                  1
+                  VSYNC signal is at the high level.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCDR
+          PDC Receive Data Register 
+          0x010
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PCDR
+              The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          VCR
+          Vertical Capture Register 
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              VSZ
+              Vertical Capture Size Number of lines to be captured.
+              16
+              27
+              read-write
+            
+            
+              VST
+              Vertical Capture Start Line PositionNumber of the line where capture is to start.
+              0
+              11
+              read-write
+            
+          
+        
+        
+          HCR
+          Horizontal Capture Register 
+          0x018
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              HSZ
+              Horizontal Capture Size Number of bytes to capture horizontally.
+              16
+              27
+              read-write
+            
+            
+              HST
+              Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start.
+              0
+              11
+              read-write
+            
+          
+        
+      
+    
+    
+      R_PORT0
+      I/O Ports
+      0x40040000
+      
+        0x00000000
+        0x010
+        registers
+      
+      
+        
+          PCNTR1
+          Port Control Register 1
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PODR
+              Pmn Output Data
+              16
+              31
+              read-write
+              
+                
+                  0
+                  Low output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+            
+              PDR
+              Pmn Direction
+              0
+              15
+              read-write
+              
+                
+                  0
+                  Input (functions as an input pin)
+                  #0
+                
+                
+                  1
+                  Output (functions as an output pin).
+                  #1
+                
+              
+            
+          
+        
+        
+          PODR
+          Output data register
+          PCNTR1
+          0x00
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              PODR%s
+              Pmn Output Data
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Low output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+          
+        
+        
+          PDR
+          Data direction register
+          PCNTR1
+          0x02
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              PDR%s
+              Pmn Direction
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Input (functions as an input pin)
+                  #0
+                
+                
+                  1
+                  Output (functions as an output pin).
+                  #1
+                
+              
+            
+          
+        
+        
+          PCNTR2
+          Port Control Register 2
+          0x04
+          32
+          read-only
+          0x00000000
+          0xFFFF0000
+          
+            
+              EIDR
+              Pmn Event Input Data
+              16
+              31
+              read-only
+              
+                
+                  0
+                  Low input
+                  #0
+                
+                
+                  1
+                  High input.
+                  #1
+                
+              
+            
+            
+              PIDR
+              Pmn Input Data
+              0
+              15
+              read-only
+              
+                
+                  0
+                  Low input
+                  #0
+                
+                
+                  1
+                  High input.
+                  #1
+                
+              
+            
+          
+        
+        
+          EIDR
+          Event input data register
+          PCNTR2
+          0x04
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              EIDR%s
+              Pmn Event Input Data
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Low input
+                  #0
+                
+                
+                  1
+                  High input.
+                  #1
+                
+              
+            
+          
+        
+        
+          PIDR
+          Input data register
+          PCNTR2
+          0x06
+          16
+          read-only
+          0x0000
+          0x0000
+          
+            
+              16
+              1
+              PIDR%s
+              Pmn Input Data
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Low input
+                  #0
+                
+                
+                  1
+                  High input.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCNTR3
+          Port Control Register 3
+          0x08
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PORR
+              Pmn Output Reset
+              16
+              31
+              write-only
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  Low output.
+                  #1
+                
+              
+            
+            
+              POSR
+              Pmn Output Set
+              0
+              15
+              write-only
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+          
+        
+        
+          PORR
+          Output set register
+          PCNTR3
+          0x08
+          16
+          write-only
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              PORR%s
+              Pmn Output Reset
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  Low output.
+                  #1
+                
+              
+            
+          
+        
+        
+          POSR
+          Output reset register
+          PCNTR3
+          0x0A
+          16
+          write-only
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              POSR%s
+              Pmn Output Set
+              0
+              0
+              write-only
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+          
+        
+        
+          PCNTR4
+          Port Control Register 4
+          0x0C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EORR
+              Pmn Event Output Reset
+              16
+              31
+              read-write
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  Low output
+                  #1
+                
+              
+            
+            
+              EOSR
+              Pmn Event Output Set
+              0
+              15
+              read-write
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+          
+        
+        
+          EORR
+          Event output set register
+          PCNTR4
+          0x0C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              EORR%s
+              Pmn Event Output Reset
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  Low output
+                  #1
+                
+              
+            
+          
+        
+        
+          EOSR
+          Event output reset register
+          PCNTR4
+          0x0E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              16
+              1
+              EOSR%s
+              Pmn Event Output Set
+              0
+              0
+              read-write
+              
+                
+                  0
+                  No affect to output
+                  #0
+                
+                
+                  1
+                  High output.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_PORT1
+      0x40040020
+    
+    
+      R_PORT2
+      0x40040040
+    
+    
+      R_PORT3
+      0x40040060
+    
+    
+      R_PORT4
+      0x40040080
+    
+    
+      R_PORT5
+      0x400400A0
+    
+    
+      R_PORT6
+      0x400400C0
+    
+    
+      R_PORT7
+      0x400400E0
+    
+    
+      R_PORT8
+      0x40040100
+    
+    
+      R_PORT9
+      0x40040120
+    
+    
+      R_PORT10
+      0x40040140
+    
+    
+      R_PORT11
+      0x40040160
+    
+    
+      R_PFS
+      I/O Ports-PFS
+      0x40040800
+      
+        0x00000000
+        0x040
+        registers
+      
+      
+        
+          12
+          0x40
+          PORT[%s]
+          Port %s
+          
+          16
+          4
+          PIN[%s]
+          Pin Function Selects
+          0
+          
+            PmnPFS_BY
+            Pin Function Control Register
+            0x003
+            8
+            read-write
+            0x00
+            0xFD
+            
+              
+                NCODR
+                N-Channel Open Drain Control
+                6
+                6
+                read-write
+                
+                  
+                    0
+                    CMOS output
+                    #0
+                  
+                  
+                    1
+                    NMOS open-drain output
+                    #1
+                  
+                
+              
+              
+                PIM
+                Port Input Mode Control
+                5
+                5
+                read-write
+                
+                  
+                    0
+                    CMOS input
+                    #0
+                  
+                  
+                    1
+                    TTL input
+                    #1
+                  
+                
+              
+              
+                PCR
+                Pull-up Control
+                4
+                4
+                read-write
+                
+                  
+                    0
+                    Disables an input pull-up.
+                    #0
+                  
+                  
+                    1
+                    Enables an input pull-up.
+                    #1
+                  
+                
+              
+              
+                PDR
+                Port Direction
+                2
+                2
+                read-write
+                
+                  
+                    0
+                    Input (Functions as an input pin.)
+                    #0
+                  
+                  
+                    1
+                    Output (Functions as an output pin.)
+                    #1
+                  
+                
+              
+              
+                PIDR
+                Port Input Data
+                1
+                1
+                read-only
+                
+                  
+                    0
+                    Low input
+                    #0
+                  
+                  
+                    1
+                    High input
+                    #1
+                  
+                
+              
+              
+                PODR
+                Port Output Data
+                0
+                0
+                read-write
+                
+                  
+                    0
+                    Low output
+                    #0
+                  
+                  
+                    1
+                    High output
+                    #1
+                  
+                
+              
+            
+          
+          
+            PmnPFS_HA
+            Pin Function Control Register
+            0x002
+            16
+            read-write
+            0x0000
+            0xFFFD
+            
+              
+                ASEL
+                Analog Input enable
+                15
+                15
+                read-write
+                
+                  
+                    0
+                    Used other than as analog pin
+                    #0
+                  
+                  
+                    1
+                    Used as analog pin
+                    #1
+                  
+                
+              
+              
+                ISEL
+                IRQ input enable
+                14
+                14
+                read-write
+                
+                  
+                    0
+                    Not used as IRQn input pin
+                    #0
+                  
+                  
+                    1
+                    Used as IRQn input pin
+                    #1
+                  
+                
+              
+              
+                EOFR
+                Event on Falling/Rising
+                12
+                13
+                read-write
+                
+                  
+                    00
+                    Do not care
+                    #00
+                  
+                  
+                    01
+                    Detect rising edge
+                    #01
+                  
+                  
+                    10
+                    Detect falling edge
+                    #10
+                  
+                  
+                    11
+                    Detect rising and falling edge
+                    #11
+                  
+                
+              
+              
+                DSCR
+                Drive Strength Control Register
+                10
+                11
+                read-write
+                
+                  
+                    00
+                    Normal drive output
+                    #00
+                  
+                  
+                    01
+                    Middle drive output
+                    #01
+                  
+                  
+                    10
+                    Middle drive with IIC
+                    #10
+                  
+                  
+                    11
+                    High-drive output
+                    #11
+                  
+                
+              
+            
+          
+          
+            PmnPFS
+            Pin Function Control Register
+            0x000
+            32
+            read-write
+            0x00000000
+            0xFFFFFFFD
+            
+              
+                PSEL
+                Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table
+                24
+                28
+                read-write
+              
+              
+                PMR
+                Port Mode Control
+                16
+                16
+                read-write
+                
+                  
+                    0
+                    Uses the pin as a general I/O pin. 
+                    #0
+                  
+                  
+                    1
+                    Uses the pin as an I/O port for peripheral functions.
+                    #1
+                  
+                
+              
+            
+          
+        
+        
+      
+    
+    
+      R_PMISC
+      I/O Ports-MISC
+      0x40040D00
+      
+        0x00000003
+        0x01
+        registers
+      
+      
+        
+          PFENET
+          Ethernet Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              Reserved
+              These bits are read as 00. The write value should be 00.
+              6
+              7
+              read-write
+            
+            
+              PHYMODE1
+              Ethernet Mode Setting ch1
+              5
+              5
+              read-write
+              
+                
+                  0
+                  RMII mode (ETHERC channel 1)
+                  #0
+                
+                
+                  1
+                  MII mode (ETHERC channel 1)
+                  #1
+                
+              
+            
+            
+              PHYMODE0
+              Ethernet Mode Setting ch0
+              4
+              4
+              read-write
+              
+                
+                  0
+                  RMII mode (ETHERC channel 0)
+                  #0
+                
+                
+                  1
+                  MII mode (ETHERC channel 0)
+                  #1
+                
+              
+            
+            
+              Reserved
+              These bits are read as 0000. The write value should be 0000.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          PWPR
+          Write-Protect Register 
+          3
+          8
+          read-write
+          
+            
+              PFSWE
+              PmnPFS Register Write
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Writing to the PmnPFS register is disabled
+                  #0
+                
+                
+                  1
+                  Writing to the PmnPFS register is enabled.
+                  #1
+                
+              
+            
+            
+              B0WI
+              PFSWE Bit Write Disable
+              7
+              7
+              
+                
+                  0
+                  Writing to the PFSWE bit is enabled
+                  #0
+                
+                
+                  1
+                  Writing to the PFSWE bit is disabled.
+                  true
+                
+              
+            
+          
+        
+      
+    
+    
+      R_QSPI
+      Quad Serial Peripheral Interface
+      0x64000000
+      
+        0x00000000
+        0x01C
+        registers
+      
+      
+        0x00000020
+        0x00C
+        registers
+      
+      
+        0x00000030
+        0x008
+        registers
+      
+      
+        0x00000804
+        0x04
+        registers
+      
+      
+        
+          SFMSMD
+          Transfer Mode Control Register
+          0x000
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SFMCCE
+              Read instruction code selection.
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Default instruction code set for each instruction
+                  #0
+                
+                
+                  1
+                  Instruction code written in the SFMSIC register
+                  #1
+                
+              
+            
+            
+              SFMOSW
+              Setup time adjustment for serial transmission
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Does not extend the low-level width of SCK at transmission time
+                  #0
+                
+                
+                  1
+                  Extends the low-level width of SCK by 1*PCLKA at transmission time
+                  #1
+                
+              
+            
+            
+              SFMOHW
+              Hold time adjustment for serial transmission
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Does not extend the high-level width of SCK at transmission time
+                  #0
+                
+                
+                  1
+                  Extends the high-level width of SCK by 1*PCLKA at transmission time
+                  #1
+                
+              
+            
+            
+              SFMOEX
+              Extension of the I/O buffer output enable signal for the serial interface
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Does not extend the output enable signal
+                  #0
+                
+                
+                  1
+                  Extends the output enable signal by 1*QSPCLK
+                  #1
+                
+              
+            
+            
+              SFMMD3
+              SPI mode selection. An initial value is determined by input to CFGMD3.
+              8
+              8
+              read-write
+              
+                
+                  0
+                  SPI mode 0
+                  #0
+                
+                
+                  1
+                  SPI mode 3
+                  #1
+                
+              
+            
+            
+              SFMPAE
+              Selection of the function for stopping prefetch at locations other than on byte boundaries
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disables prefetch stopping at locations other than on byte boundaries
+                  #0
+                
+                
+                  1
+                  Enables prefetch stopping at locations other than on byte boundaries
+                  #1
+                
+              
+            
+            
+              SFMPFE
+              Selection of the prefetch function
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disables prefetch
+                  #0
+                
+                
+                  1
+                  Enables prefetch
+                  #1
+                
+              
+            
+            
+              SFMSE
+              Selection of the prefetch function
+              4
+              5
+              read-write
+              
+                
+                  00
+                  Does not extend QSSL
+                  #00
+                
+                
+                  01
+                  Extends QSSL by 33*QSPCLK
+                  #01
+                
+                
+                  10
+                  Extends QSSL by 129*QSPCLK
+                  #10
+                
+                
+                  11
+                  Extends QSSL infinitely
+                  #11
+                
+              
+            
+            
+              SFMRM
+              Serial interface read mode selection
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Standard Read
+                  #000
+                
+                
+                  001
+                  Fast Read
+                  #001
+                
+                
+                  010
+                  Fast Read Dual Output
+                  #010
+                
+                
+                  011
+                  Fast Read Dual I/O
+                  #011
+                
+                
+                  100
+                  Fast Read Quad Output
+                  #100
+                
+                
+                  101
+                  Fast Read Quad I/O
+                  #101
+                
+                
+                  110
+                  Setting prohibited
+                  #110
+                
+                
+                  111
+                  Setting prohibited
+                  #111
+                
+              
+            
+          
+        
+        
+          SFMSSC
+          Chip Selection Control Register
+          0x004
+          32
+          read-write
+          0x00000037
+          0xFFFFFFFF
+          
+            
+              SFMSLD
+              QSSL signal output timing selection
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK
+                  #0
+                
+                
+                  1
+                  Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK
+                  #1
+                
+              
+            
+            
+              SFMSHD
+              QSSL signal release timing selection
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Releases QSSL 0.5*SCK after the last rising edge of QSPCLK
+                  #0
+                
+                
+                  1
+                  Releases QSSL 1.5*SCK after the last rising edge of QSPCLK
+                  #1
+                
+              
+            
+            
+              SFMSW
+              Selection of a minimum high-level width of the QSSL signal
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  1 x QSPCLK
+                  #0000
+                
+                
+                  0001
+                  2 x QSPCLK
+                  #0001
+                
+                
+                  0010
+                  3 x QSPCLK
+                  #0010
+                
+                
+                  0011
+                  4 x QSPCLK
+                  #0011
+                
+                
+                  0100
+                  5 x QSPCLK
+                  #0100
+                
+                
+                  0101
+                  6 x QSPCLK
+                  #0101
+                
+                
+                  0110
+                  7 x QSPCLK
+                  #0110
+                
+                
+                  0111
+                  8 x QSPCLK
+                  #0111
+                
+                
+                  1000
+                  9 x QSPCLK
+                  #1000
+                
+                
+                  1001
+                  10 x QSPCLK
+                  #1001
+                
+                
+                  1010
+                  11 x QSPCLK
+                  #1010
+                
+                
+                  1011
+                  12 x QSPCLK
+                  #1011
+                
+                
+                  1100
+                  13 x QSPCLK
+                  #1100
+                
+                
+                  1101
+                  14 x QSPCLK
+                  #1101
+                
+                
+                  1110
+                  15 x QSPCLK
+                  #1110
+                
+                
+                  1111
+                  16 x QSPCLK
+                  #1111
+                
+              
+            
+          
+        
+        
+          SFMSKC
+          Clock Control Register
+          0x008
+          32
+          read-write
+          0x00000008
+          0xFFFFFFFF
+          
+            
+              SFMDTY
+              Selection of a duty ratio correction function for the SCK signal
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Serial interface reference cycle selection (* Pay attention to the irregularity.)
+                  #0
+                
+                
+                  1
+                  Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number)
+                  #1
+                
+              
+            
+            
+              SFMDV
+              Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction.
+              0
+              4
+              read-write
+              
+                
+                  10000
+                  18 x PCLKA
+                  #10000
+                
+                
+                  10001
+                  20 x PCLKA
+                  #10001
+                
+                
+                  10010
+                  22 x PCLKA
+                  #10010
+                
+                
+                  10011
+                  24 x PCLKA
+                  #10011
+                
+                
+                  10100
+                  26 x PCLKA
+                  #10100
+                
+                
+                  10101
+                  28 x PCLKA
+                  #10101
+                
+                
+                  10110
+                  30 x PCLKA
+                  #10110
+                
+                
+                  10111
+                  32 x PCLKA
+                  #10111
+                
+                
+                  11000
+                  34 x PCLKA
+                  #11000
+                
+                
+                  11001
+                  36 x PCLKA
+                  #11001
+                
+                
+                  11010
+                  38 x PCLKA
+                  #11010
+                
+                
+                  11011
+                  40 x PCLKA
+                  #11011
+                
+                
+                  11100
+                  42 x PCLKA
+                  #11100
+                
+                
+                  11101
+                  44 x PCLKA
+                  #11101
+                
+                
+                  11110
+                  46 x PCLKA
+                  #11110
+                
+                
+                  11111
+                  48 x PCLKA
+                  #11111
+                
+                
+                  others
+                  ( SFMDV + 2 ) x PCLKA 
+                  true
+                
+              
+            
+          
+        
+        
+          SFMSST
+          Status Register
+          0x00C
+          32
+          read-only
+          0x00000080
+          0xFFFFFFFF
+          
+            
+              PFOFF
+              Prefetch function operation state
+              7
+              7
+              read-only
+              
+                
+                  0
+                  The prefetch function is operating.
+                  #0
+                
+                
+                  1
+                  The prefetch function is not enabled or is not operating.
+                  #1
+                
+              
+            
+            
+              PFFUL
+              Prefetch buffer state
+              6
+              6
+              read-only
+              
+                
+                  0
+                  The prefetch buffer has a free space.
+                  #0
+                
+                
+                  1
+                  The prefetch buffer is full.
+                  #1
+                
+              
+            
+            
+              PFCNT
+              Number of bytes of prefetched dataRange: 00000 - 10010  (No combination other than the above is available.)
+              0
+              4
+              read-only
+              
+                
+                  00000
+                  Nodata has been prefetched.
+                  #00000
+                
+                
+                  others
+                  Data of (PFCNT) bytes hs been prefetched.
+                  true
+                
+              
+            
+          
+        
+        
+          SFMCOM
+          Communication Port Register
+          0x010
+          32
+          read-write
+          0x00000000
+          0xFFFFFF00
+          
+            
+              SFMD
+              Port for direct communication with the SPI bus.Input/output to and from this port is converted to a SPIbus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SFMCMD
+          Communication Mode Control Register
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DCOM
+              Selection of a mode of communication with the SPI bus
+              0
+              0
+              read-write
+              
+                
+                  0
+                  ROM access mode
+                  #0
+                
+                
+                  1
+                  Direct communication mode
+                  #1
+                
+              
+            
+          
+        
+        
+          SFMCST
+          Communication Status Register
+          0x018
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              EROMR
+              Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored.
+              7
+              7
+              read-only
+              
+                
+                  0
+                  ROM access is not detected in direct communication mode
+                  #0
+                
+                
+                  1
+                  ROM access is detected in direct communication mode
+                  #1
+                
+              
+            
+            
+              COMBSY
+              SPI bus cycle completion state in direct communication
+              0
+              0
+              read-only
+              
+                
+                  0
+                  There is no serial transfer being processed.
+                  #0
+                
+                
+                  1
+                  There is a serial transfer being processed.
+                  #1
+                
+              
+            
+          
+        
+        
+          SFMSIC
+          Instruction Code Register
+          0x020
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SFMCIC
+              Serial ROM instruction code to substitute
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SFMSAC
+          Address Mode Control Register
+          0x024
+          32
+          read-write
+          0x00000002
+          0xFFFFFFFF
+          
+            
+              SFM4BC
+              Selection of a default instruction code, when Serial Interface address width is selected 4 bytes.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Does not use 4 Byte address read Instruction code
+                  #0
+                
+                
+                  1
+                  Use 4 Byte address read Instruction code
+                  #1
+                
+              
+            
+            
+              SFMAS
+              Selection the number of address bits of the serial interface
+              0
+              1
+              read-write
+              
+                
+                  00
+                  1byte
+                  #00
+                
+                
+                  01
+                  2bytes
+                  #01
+                
+                
+                  10
+                  3bytes
+                  #10
+                
+                
+                  11
+                  4 bytes
+                  #11
+                
+              
+            
+          
+        
+        
+          SFMSDC
+          Dummy Cycle Control Register
+          0x028
+          32
+          read-write
+          0x0000FF00
+          0xFFFFFFFF
+          
+            
+              SFMXD
+              Mode data for serial ROM. (Control XIP mode)
+              8
+              15
+              read-write
+              
+                
+                  0
+                  XIP mode is prohibited
+                  #0
+                
+                
+                  1
+                  XIP mode is permitted
+                  #1
+                
+              
+            
+            
+              SFMXEN
+              XIP mode permission
+              7
+              7
+              read-write
+              
+                
+                  0
+                  XIP mode is prohibited
+                  #0
+                
+                
+                  1
+                  XIP mode is permitted
+                  #1
+                
+              
+            
+            
+              SFMXST
+              XIP mode status
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Normal (non-XIP) mode is operating
+                  #0
+                
+                
+                  1
+                  XIP mode is operating
+                  #1
+                
+              
+            
+            
+              SFMDN
+              Selection of the number of dummy cycles of Fast Read instructions
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  Default dummy cycles of each instruction.
+                  #0000
+                
+                
+                  others
+                  ( SFMDN + 2 ) x SCK
+                  true
+                
+              
+            
+          
+        
+        
+          SFMSPC
+          SPI Protocol Control Register
+          0x030
+          32
+          read-write
+          0x00000010
+          0xFFFFFFFF
+          
+            
+              SFMSDE
+              Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected.
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Does not allocate minimum switch time
+                  #0
+                
+                
+                  1
+                  Allocate the minimum switch time equivalent to 1*QSPXLK
+                  #1
+                
+              
+            
+            
+              SFMSPI
+              Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately.
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Extended SPI protocol
+                  #00
+                
+                
+                  01
+                  Dual SPI protocol
+                  #01
+                
+                
+                  10
+                  Quad SPI protocol
+                  #10
+                
+                
+                  11
+                  Setting prohibited.
+                  #11
+                
+              
+            
+          
+        
+        
+          SFMPMD
+          Port Control Register
+          0x034
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SFMWPL
+              Specify level of WP pin
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Low level
+                  #0
+                
+                
+                  1
+                  High level
+                  #1
+                
+              
+            
+          
+        
+        
+          SFMCNT1
+          External QSPI Address Register 1
+          0x804
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              QSPI_EXT
+              BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.
+              26
+              31
+              read-write
+            
+          
+        
+      
+    
+    
+      R_RTC
+      Realtime Clock
+      0x40044000
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000002
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000006
+        0x01
+        registers
+      
+      
+        0x00000008
+        0x01
+        registers
+      
+      
+        0x0000000A
+        0x01
+        registers
+      
+      
+        0x0000000C
+        0x01
+        registers
+      
+      
+        0x0000000E
+        0x003
+        registers
+      
+      
+        0x00000012
+        0x01
+        registers
+      
+      
+        0x00000014
+        0x01
+        registers
+      
+      
+        0x00000016
+        0x01
+        registers
+      
+      
+        0x00000018
+        0x01
+        registers
+      
+      
+        0x0000001A
+        0x01
+        registers
+      
+      
+        0x0000001C
+        0x003
+        registers
+      
+      
+        0x00000022
+        0x01
+        registers
+      
+      
+        0x00000024
+        0x01
+        registers
+      
+      
+        0x00000028
+        0x01
+        registers
+      
+      
+        0x0000002A
+        0x005
+        registers
+      
+      
+        0x00000040
+        0x01
+        registers
+      
+      
+        0x00000042
+        0x01
+        registers
+      
+      
+        0x00000044
+        0x01
+        registers
+      
+      
+        0x00000052
+        0x01
+        registers
+      
+      
+        0x00000054
+        0x01
+        registers
+      
+      
+        0x00000056
+        0x01
+        registers
+      
+      
+        0x0000005A
+        0x01
+        registers
+      
+      
+        0x0000005C
+        0x01
+        registers
+      
+      
+        0x00000062
+        0x01
+        registers
+      
+      
+        0x00000064
+        0x01
+        registers
+      
+      
+        0x00000066
+        0x01
+        registers
+      
+      
+        0x0000006A
+        0x01
+        registers
+      
+      
+        0x0000006C
+        0x01
+        registers
+      
+      
+        0x00000072
+        0x01
+        registers
+      
+      
+        0x00000074
+        0x01
+        registers
+      
+      
+        0x00000076
+        0x01
+        registers
+      
+      
+        0x0000007A
+        0x01
+        registers
+      
+      
+        0x0000007C
+        0x01
+        registers
+      
+      
+        
+          3
+          0x2
+          RTCCR[%s]
+          Time Capture Control Register
+          0x40
+          
+            RTCCR
+            Time Capture Control Register
+            0
+            8
+            read-write
+            0x00
+            0x00
+            
+              
+                TCNF
+                Time Capture Noise Filter Control
+                4
+                5
+                read-write
+                
+                  
+                    00
+                    The noise filter is off.
+                    #00
+                  
+                  
+                    01
+                    Setting prohibited
+                    #01
+                  
+                  
+                    10
+                    The noise filter is on (count source).
+                    #10
+                  
+                  
+                    11
+                    The noise filter is on (count source by divided by 32).
+                    #11
+                  
+                
+              
+              
+                TCST
+                Time Capture Status
+                2
+                2
+                read-only
+                
+                  
+                    0
+                    No event is detected.
+                    #0
+                  
+                  
+                    1
+                    An event is detected.
+                    #1
+                  
+                
+              
+              
+                TCCT
+                Time Capture Control
+                0
+                1
+                read-write
+                
+                  
+                    00
+                    No event is detected.
+                    #00
+                  
+                  
+                    01
+                    Rising edge is detected.
+                    #01
+                  
+                  
+                    10
+                    Falling edge is detected.
+                    #10
+                  
+                  
+                    11
+                    Both edges are detected.
+                    #11
+                  
+                
+              
+            
+          
+        
+        
+          3
+          0x10
+          CP[%s]
+          Capture registers
+          0x50
+          
+            RSEC
+            Second Capture Register
+            0x02
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                SEC10
+                10-Second Capture Capture value for the tens place of seconds
+                4
+                6
+                read-only
+              
+              
+                SEC1
+                1-Second Capture Capture value for the ones place of seconds
+                0
+                3
+                read-only
+              
+            
+          
+          
+            BCNT0
+            BCNT0 Capture Register
+            RSEC
+            0x02
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                BCNT0CP
+                BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected.
+                0
+                7
+                read-only
+              
+            
+          
+          
+            RMIN
+            Minute Capture Register
+            0x04
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                MIN10
+                10-Minute Capture Capture value for the tens place of minutes
+                4
+                6
+                read-only
+              
+              
+                MIN1
+                1-Minute Capture Capture value for the ones place of minutes
+                0
+                3
+                read-only
+              
+            
+          
+          
+            BCNT1
+            BCNT1 Capture Register
+            RMIN
+            0x04
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                BCNT1CP
+                BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected.
+                0
+                7
+                read-only
+              
+            
+          
+          
+            RHR
+            Hour Capture Register
+            0x06
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                PM
+                A.m./p.m. select for time counter setting.
+                6
+                6
+                read-only
+                
+                  
+                    0
+                    a.m.
+                    #0
+                  
+                  
+                    1
+                    p.m.
+                    #1
+                  
+                
+              
+              
+                HR10
+                10-Minute Capture Capture value for the tens place of minutes
+                4
+                5
+                read-only
+              
+              
+                HR1
+                1-Minute Capture Capture value for the ones place of minutes
+                0
+                3
+                read-only
+              
+            
+          
+          
+            BCNT2
+            BCNT2 Capture Register
+            RHR
+            0x06
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                BCNT2CP
+                BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected.
+                0
+                7
+                read-only
+              
+            
+          
+          
+            RDAY
+            Date Capture Register
+            0x0A
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                DATE10
+                10-Day Capture Capture value for the tens place of minutes
+                4
+                5
+                read-only
+              
+              
+                DATE1
+                1-Day Capture Capture value for the ones place of minutes
+                0
+                3
+                read-only
+              
+            
+          
+          
+            BCNT3
+            BCNT3 Capture Register
+            RDAY
+            0x0A
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                BCNT3CP
+                BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected.
+                0
+                7
+                read-only
+              
+            
+          
+          
+            RMON
+            Month Capture Register
+            0x0C
+            8
+            read-only
+            0x00
+            0x00
+            
+              
+                MON10
+                10-Month Capture Capture value for the tens place of months
+                4
+                4
+                read-only
+              
+              
+                MON1
+                1-Month Capture Capture value for the ones place of months
+                0
+                3
+                read-only
+              
+            
+          
+        
+        
+          R64CNT
+          64-Hz Counter
+          0x00
+          8
+          read-only
+          0x00
+          0x80
+          
+            
+              F1HZ
+              1Hz
+              6
+              6
+              read-only
+            
+            
+              F2HZ
+              2Hz
+              5
+              5
+              read-only
+            
+            
+              F4HZ
+              4Hz
+              4
+              4
+              read-only
+            
+            
+              F8HZ
+              8Hz
+              3
+              3
+              read-only
+            
+            
+              F16HZ
+              16Hz
+              2
+              2
+              read-only
+            
+            
+              F32HZ
+              32Hz
+              1
+              1
+              read-only
+            
+            
+              F64HZ
+              64Hz
+              0
+              0
+              read-only
+            
+          
+        
+        
+          RSECCNT
+          Second Counter
+          0x02
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              SEC10
+              10-Second Count Counts from 0 to 5 for 60-second counting.
+              4
+              6
+              read-write
+            
+            
+              SEC1
+              1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT0
+          Binary Counter 0
+          RSECCNT
+          0x02
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT0
+              The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RMINCNT
+          Minute Counter
+          0x04
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              MIN10
+              10-Minute Count Counts from 0 to 5 for 60-minute counting.
+              4
+              6
+              read-write
+            
+            
+              MIN1
+              1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT1
+          Binary Counter 1
+          RMINCNT
+          0x04
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT1
+              The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RHRCNT
+          Hour Counter
+          0x06
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              PM
+              Time Counter Setting for a.m./p.m.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  a.m.
+                  #0
+                
+                
+                  1
+                  p.m.
+                  #1
+                
+              
+            
+            
+              HR10
+              10-Hour Count Counts from 0 to 2 once per carry from the ones place.
+              4
+              5
+              read-write
+            
+            
+              HR1
+              1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT2
+          Binary Counter 2
+          RHRCNT
+          0x06
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT2
+              The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RWKCNT
+          Day-of-Week Counter
+          0x08
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              DAYW
+              Day-of-Week Counting
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Sunday
+                  #000
+                
+                
+                  001
+                  Monday
+                  #001
+                
+                
+                  010
+                  Tuesday
+                  #010
+                
+                
+                  011
+                  Wednesday
+                  #011
+                
+                
+                  100
+                  Thursday
+                  #100
+                
+                
+                  101
+                  Friday
+                  #101
+                
+                
+                  110
+                  Saturday
+                  #110
+                
+                
+                  111
+                  Setting Prohibited 
+                  #111
+                
+              
+            
+          
+        
+        
+          BCNT3
+          Binary Counter 3
+          RWKCNT
+          0x08
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT3
+              The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RDAYCNT
+          Day Counter
+          0x0A
+          8
+          read-write
+          0x00
+          0xC0
+          
+            
+              DATE10
+              10-Day Count Counts from 0 to 3 once per carry from the ones place.
+              4
+              5
+              read-write
+            
+            
+              DATE1
+              1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          RMONCNT
+          Month Counter
+          0x0C
+          8
+          read-write
+          0x00
+          0xE0
+          
+            
+              MON10
+              10-Month Count Counts from 0 to 1 once per carry from the ones place.
+              4
+              4
+              read-write
+            
+            
+              MON1
+              1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          RYRCNT
+          Year Counter
+          0x0E
+          16
+          read-write
+          0x0000
+          0xFF00
+          
+            
+              YR10
+              10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place.
+              4
+              7
+              read-write
+            
+            
+              YR1
+              1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          RSECAR
+          Second Alarm Register
+          0x10
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RSECCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RSECCNT counter value.
+                  #1
+                
+              
+            
+            
+              SEC10
+              10-Seconds Value for the tens place of seconds
+              4
+              6
+              read-write
+            
+            
+              SEC1
+              1-Second Value for the ones place of seconds
+              0
+              3
+              write-only
+            
+          
+        
+        
+          BCNT0AR
+          Binary Counter 0 Alarm Register
+          RSECAR
+          0x10
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT0AR
+              he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RMINAR
+          Minute Alarm Register
+          0x12
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RMINCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RMINCNT counter value.
+                  #1
+                
+              
+            
+            
+              MIN10
+              10-Minute Count Value for the tens place of minutes
+              4
+              6
+              read-write
+            
+            
+              MIN1
+              1-Minute Count Value for the ones place of minutes
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT1AR
+          Binary Counter 1 Alarm Register
+          RMINAR
+          0x12
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT1AR
+              he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RHRAR
+          Hour Alarm Register
+          0x14
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RHRCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RHRCNT counter value.
+                  #1
+                
+              
+            
+            
+              PM
+              Time Counter Setting for a.m./p.m.
+              6
+              6
+              read-write
+              
+                
+                  0
+                  a.m.
+                  #0
+                
+                
+                  1
+                  p.m.
+                  #1
+                
+              
+            
+            
+              HR10
+              10-Hour Count Value for the tens place of hours
+              4
+              5
+              read-write
+            
+            
+              HR1
+              1-Hour Count Value for the ones place of hours
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT2AR
+          Binary Counter 2 Alarm Register
+          RHRAR
+          0x14
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT2AR
+              The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RWKAR
+          Day-of-Week Alarm Register
+          0x16
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RWKCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RWKCNT counter value.
+                  #1
+                
+              
+            
+            
+              DAYW
+              Day-of-Week Counting
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Sunday
+                  #000
+                
+                
+                  001
+                  Monday
+                  #001
+                
+                
+                  010
+                  Tuesday
+                  #010
+                
+                
+                  011
+                  Wednesday
+                  #011
+                
+                
+                  100
+                  Thursday
+                  #100
+                
+                
+                  101
+                  Friday
+                  #101
+                
+                
+                  110
+                  Saturday
+                  #110
+                
+                
+                  111
+                  Setting Prohibited 
+                  #111
+                
+              
+            
+          
+        
+        
+          BCNT3AR
+          Binary Counter 3 Alarm Register
+          RWKAR
+          0x16
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              BCNT3AR
+              The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RDAYAR
+          Date Alarm Register
+          0x18
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RDAYCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RDAYCNT counter value.
+                  #1
+                
+              
+            
+            
+              DATE10
+              10 Days Value for the tens place of days
+              4
+              5
+              read-write
+            
+            
+              DATE1
+              1 Day Value for the ones place of days
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT0AER
+          Binary Counter 0 Alarm Enable Register
+          RDAYAR
+          0x18
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RMONAR
+          Month Alarm Register
+          0x1A
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RMONCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RMONCNT counter value.
+                  #1
+                
+              
+            
+            
+              MON10
+              10 Months Value for the tens place of months
+              4
+              4
+              read-write
+            
+            
+              MON1
+              1 Month Value for the ones place of months
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT1AER
+          Binary Counter 1 Alarm Enable Register
+          RMONAR
+          0x1A
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RYRAR
+          Year Alarm Register
+          0x1C
+          16
+          read-write
+          0x0000
+          0xFF00
+          
+            
+              YR10
+              10 Years Value for the tens place of years
+              4
+              7
+              read-write
+            
+            
+              YR1
+              1 Year Value for the ones place of years
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BCNT2AER
+          Binary Counter 2 Alarm Enable Register
+          RYRAR
+          0x1C
+          16
+          read-write
+          0x0000
+          0xFF00
+          
+            
+              ENB
+              The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RYRAREN
+          Year Alarm Enable Register
+          0x1E
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              Compare enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The register value is not compared with the RYRCNT counter value.
+                  #0
+                
+                
+                  1
+                  The register value is compared with the RYRCNT counter value.
+                  #1
+                
+              
+            
+          
+        
+        
+          BCNT3AER
+          Binary Counter 3 Alarm Enable Register
+          RYRAREN
+          0x1E
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              ENB
+              The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. 
+              0
+              7
+              read-write
+            
+          
+        
+        
+          RCR1
+          RTC Control Register 1
+          0x22
+          8
+          read-write
+          0x00
+          0x0A
+          
+            
+              PES
+              Periodic Interrupt Select
+              4
+              7
+              read-write
+              
+                
+                  0110
+                  A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1).
+                  #0110
+                
+                
+                  0111
+                  A periodic interrupt is generated every 1/128 second.
+                  #0111
+                
+                
+                  1000
+                  A periodic interrupt is generated every 1/64 second.
+                  #1000
+                
+                
+                  1001
+                  A periodic interrupt is generated every 1/32 second.
+                  #1001
+                
+                
+                  1010
+                  A periodic interrupt is generated every 1/16 second.
+                  #1010
+                
+                
+                  1011
+                  A periodic interrupt is generated every 1/8 second.
+                  #1011
+                
+                
+                  1100
+                  A periodic interrupt is generated every 1/4 second.
+                  #1100
+                
+                
+                  1101
+                  A periodic interrupt is generated every 1/2 second.
+                  #1101
+                
+                
+                  1110
+                  A periodic interrupt is generated every 1 second.
+                  #1110
+                
+                
+                  1111
+                  A periodic interrupt is generated every 2 seconds.
+                  #1111
+                
+                
+                  others
+                  No periodic interrupts are generated.
+                  true
+                
+              
+            
+            
+              RTCOS
+              RTCOUT Output Select
+              3
+              3
+              read-write
+              
+                
+                  0
+                  RTCOUT outputs 1 Hz.
+                  #0
+                
+                
+                  1
+                  RTCOUT outputs 64 Hz.
+                  #1
+                
+              
+            
+            
+              PIE
+              Periodic Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  A periodic interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  A periodic interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              CIE
+              Carry Interrupt Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  A carry interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  A carry interrupt request is enabled.
+                  #1
+                
+              
+            
+            
+              AIE
+              Alarm Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  An alarm interrupt request is disabled.
+                  #0
+                
+                
+                  1
+                  An alarm interrupt request is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          RCR2
+          RTC Control Register 2
+          0x24
+          8
+          read-write
+          0x00
+          0x0E
+          
+            
+              CNTMD
+              Count Mode Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The calendar count mode.
+                  #0
+                
+                
+                  1
+                  The binary count mode.
+                  #1
+                
+              
+            
+            
+              HR24
+              Hours Mode
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The RTC operates in 12-hour mode.
+                  #0
+                
+                
+                  1
+                  The RTC operates in 24-hour mode.
+                  #1
+                
+              
+            
+            
+              AADJP
+              Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.)
+              5
+              5
+              read-write
+              
+                
+                  0
+                  The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute.
+                  #0
+                
+                
+                  1
+                  The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds.
+                  #1
+                
+              
+            
+            
+              AADJE
+              Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.)
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Automatic adjustment is disabled.
+                  #0
+                
+                
+                  1
+                  Automatic adjustment is enabled.
+                  #1
+                
+              
+            
+            
+              RTCOE
+              RTCOUT Output Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  RTCOUT output disabled.
+                  #0
+                
+                
+                  1
+                  RTCOUT output enabled.
+                  #1
+                
+              
+            
+            
+              ADJ30
+              30-Second Adjustment
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read)
+                  #0
+                
+                
+                  1
+                  30-second adjustment is executed.(write) / During 30-second adjustment.(read)
+                  #1
+                
+              
+            
+            
+              RESET
+              RTC Software Reset
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Writing is invalid.(write) /  In normal time operation, or an RTC software reset has completed.(read)
+                  #0
+                
+                
+                  1
+                  The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read)
+                  #1
+                
+              
+            
+            
+              START
+              Start
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Prescaler and time counter are stopped.
+                  #0
+                
+                
+                  1
+                  Prescaler and time counter operate normally.
+                  #1
+                
+              
+            
+          
+        
+        
+          RCR4
+          RTC Control Register 4
+          0x28
+          8
+          read-write
+          0x00
+          0xFE
+          
+            
+              RCKSEL
+              Count Source Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Sub-clock oscillator is selected.
+                  #0
+                
+                
+                  1
+                  LOCO clock oscillator is selected.
+                  #1
+                
+              
+            
+            
+              ROPSEL
+              RTC Operation Mode Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal operation mode is selected.
+                  #0
+                
+                
+                  1
+                  Low-consumption clock mode is selected.
+                  #1
+                
+              
+            
+          
+        
+        
+          RFRH
+          Frequency Register H
+          0x2A
+          16
+          read-write
+          0x0000
+          0xFFFE
+          
+            
+              RFC16
+              Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle.
+              0
+              0
+              read-write
+            
+          
+        
+        
+          RFRL
+          Frequency Register L
+          0x2C
+          16
+          read-write
+          0x0000
+          0x0000
+          
+            
+              RFC
+              Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          RADJ
+          Time Error Adjustment Register
+          0x2E
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              PMADJ
+              Plus-Minus
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Adjustment is not performed.
+                  #00
+                
+                
+                  01
+                  Adjustment is performed by the addition to the prescaler.
+                  #01
+                
+                
+                  10
+                  Adjustment is performed by the subtraction from the prescaler.
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              ADJ
+              Adjustment Value These bits specify the adjustment value from the prescaler.
+              0
+              5
+              read-write
+            
+          
+        
+      
+    
+    
+      R_SCI0
+      Serial Communications Interface
+      0x40070000
+      
+        0x00000000
+        0x01D
+        registers
+      
+      
+        
+          SMR
+          Serial Mode Register (SCMR.SMIF = 0)
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CM
+              Communication Mode
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Asynchronous mode or simple I2C mode
+                  #0
+                
+                
+                  1
+                  Clock synchronous mode
+                  #1
+                
+              
+            
+            
+              CHR
+              Character Length(Valid only in asynchronous mode)
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Transmit/receive in 9-bit data length(SCMR.CHR1=0) /  in 8bit data length(SCMR.CHR1=1)
+                  #0
+                
+                
+                  1
+                  Transmit/receive in 9-bit data length(SCMR.CHR1=0) /  in 7bit data length(SCMR.CHR1=1)
+                  #1
+                
+              
+            
+            
+              PE
+              Parity Enable(Valid only in asynchronous mode)
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )
+                  #0
+                
+                
+                  1
+                  The parity bit is added (transmitting) / The parity bit is checked (receiving)
+                  #1
+                
+              
+            
+            
+              PM
+              Parity Mode (Valid only when the PE bit is 1)
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Selects even parity
+                  #0
+                
+                
+                  1
+                  Selects odd parity
+                  #1
+                
+              
+            
+            
+              STOP
+              Stop Bit Length(Valid only in asynchronous mode)
+              3
+              3
+              read-write
+              
+                
+                  0
+                  1 stop bit
+                  #0
+                
+                
+                  1
+                  2 stop bits
+                  #1
+                
+              
+            
+            
+              MP
+              Multi-Processor Mode(Valid only in asynchronous mode)
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Multi-processor communications function is disabled
+                  #0
+                
+                
+                  1
+                  Multi-processor communications function is enabled
+                  #1
+                
+              
+            
+            
+              CKS
+              Clock Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  PCLK clock
+                  #00
+                
+                
+                  01
+                  PCLK/4 clock
+                  #01
+                
+                
+                  10
+                  PCLK/16 clock
+                  #10
+                
+                
+                  11
+                  PCLK/64 clock
+                  #11
+                
+              
+            
+          
+        
+        
+          SMR_SMCI
+          Serial mode register (SCMR.SMIF = 1)
+          SMR
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              GM
+              GSM Mode
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal mode operation
+                  #0
+                
+                
+                  1
+                  GSM mode operation
+                  #1
+                
+              
+            
+            
+              BLK
+              Block Transfer Mode
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Normal mode operation
+                  #0
+                
+                
+                  1
+                  Block transfer mode operation
+                  #1
+                
+              
+            
+            
+              PE
+              Parity Enable(Valid only in asynchronous mode)
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Setting Prohibited
+                  #0
+                
+                
+                  1
+                  Set this bit to 1 in smart card interface mode.
+                  #1
+                
+              
+            
+            
+              PM
+              Parity Mode (Valid only when the PE bit is 1)
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Selects even parity
+                  #0
+                
+                
+                  1
+                  Selects odd parity
+                  #1
+                
+              
+            
+            
+              BCP
+              Base Clock Pulse(Valid only in asynchronous mode)
+              2
+              3
+              read-write
+              
+                
+                  00
+                  93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32)  (SCMR.BCP2=1) 
+                  #00
+                
+                
+                  01
+                  128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1)
+                  #01
+                
+                
+                  10
+                  186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1)
+                  #10
+                
+                
+                  11
+                  512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1)
+                  #11
+                
+              
+            
+            
+              CKS
+              Clock Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  PCLK clock
+                  #00
+                
+                
+                  01
+                  PCLK/4 clock
+                  #01
+                
+                
+                  10
+                  PCLK/16 clock
+                  #10
+                
+                
+                  11
+                  PCLK/64 clock
+                  #11
+                
+              
+            
+          
+        
+        
+          BRR
+          Bit Rate Register
+          0x01
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              BRR
+              BRR is an 8-bit register that adjusts the bit rate.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SCR
+          Serial Control Register (SCMR.SMIF = 0)
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TIE
+              Transmit Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  SCI_TXI interrupt request is disabled
+                  #0
+                
+                
+                  1
+                  SCI_TXI interrupt request is enabled
+                  #1
+                
+              
+            
+            
+              RIE
+              Receive Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  SCI_RXI and SCI_ERI interrupt requests are disabled
+                  #0
+                
+                
+                  1
+                  SCI_RXI and SCI_ERI interrupt requests are enabled
+                  #1
+                
+              
+            
+            
+              TE
+              Transmit Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Serial transmission is disabled
+                  #0
+                
+                
+                  1
+                  Serial transmission is enabled
+                  #1
+                
+              
+            
+            
+              RE
+              Receive Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Serial reception is disabled
+                  #0
+                
+                
+                  1
+                  Serial reception is enabled
+                  #1
+                
+              
+            
+            
+              MPIE
+              Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Normal reception
+                  #0
+                
+                
+                  1
+                  When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed.
+                  #1
+                
+              
+            
+            
+              TEIE
+              Transmit End Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  SCI_TEI interrupt request is disabled
+                  #0
+                
+                
+                  1
+                  SCI_TEI interrupt request is enabled
+                  #1
+                
+              
+            
+            
+              CKE
+              Clock Enable
+              0
+              1
+              read-write
+              
+                
+                  00
+                  The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)
+                  #00
+                
+                
+                  01
+                  The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)
+                  #01
+                
+                
+                  others
+                  The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode)
+                  true
+                
+              
+            
+          
+        
+        
+          SCR_SMCI
+          Serial Control Register (SCMR.SMIF =1)
+          SCR
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TIE
+              Transmit Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  A SCI_TXI interrupt request is disabled
+                  #0
+                
+                
+                  1
+                  A SCI_TXI interrupt request is enabled
+                  #1
+                
+              
+            
+            
+              RIE
+              Receive Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  SCI_RXI and SCI_ERI interrupt requests are disabled
+                  #0
+                
+                
+                  1
+                  SCI_RXI and SCI_ERI interrupt requests are enabled
+                  #1
+                
+              
+            
+            
+              TE
+              Transmit Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Serial transmission is disabled
+                  #0
+                
+                
+                  1
+                  Serial transmission is enabled
+                  #1
+                
+              
+            
+            
+              RE
+              Receive Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Serial reception is disabled
+                  #0
+                
+                
+                  1
+                  Serial reception is enabled
+                  #1
+                
+              
+            
+            
+              MPIE
+              Multi-Processor Interrupt Enable
+              3
+              3
+              read-write
+            
+            
+              TEIE
+              Transmit End Interrupt Enable
+              2
+              2
+              read-write
+            
+            
+              CKE
+              Clock Enable
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1)
+                  #00
+                
+                
+                  01
+                  Clock Output
+                  #01
+                
+                
+                  10
+                  Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1)
+                  #10
+                
+                
+                  11
+                  Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1)
+                  #11
+                
+              
+            
+          
+        
+        
+          TDR
+          Transmit Data Register
+          0x03
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              TDR
+              TDR is an 8-bit register that stores transmit data.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SSR
+          Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)
+          0x04
+          8
+          read-write
+          0x84
+          0xFF
+          
+            
+              TDRE
+              Transmit Data Empty Flag
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Transmit data is in TDR register
+                  #0
+                
+                
+                  1
+                  No transmit data is in TDR register
+                  #1
+                
+              
+            
+            
+              RDRF
+              Receive Data Full Flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No received data is in RDR register
+                  #0
+                
+                
+                  1
+                  Received data is in RDR register
+                  #1
+                
+              
+            
+            
+              ORER
+              Overrun Error Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No overrun error occurred
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred
+                  #1
+                
+              
+            
+            
+              FER
+              Framing Error Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No framing error occurred
+                  #0
+                
+                
+                  1
+                  A framing error has occurred
+                  #1
+                
+              
+            
+            
+              PER
+              Parity Error Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No parity error occurred
+                  #0
+                
+                
+                  1
+                  A parity error has occurred
+                  #1
+                
+              
+            
+            
+              TEND
+              Transmit End Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  A character is being transmitted.
+                  #0
+                
+                
+                  1
+                  Character transfer has been completed.
+                  #1
+                
+              
+            
+            
+              MPB
+              Multi-Processor
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+            
+              MPBT
+              Multi-Processor Bit Transfer
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+          
+        
+        
+          SSR_FIFO
+          Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)
+          SSR
+          0x04
+          8
+          read-write
+          0x80
+          0xFD
+          
+            
+              TDFE
+              Transmit FIFO data empty flag
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The quantity of transmit data written in FTDR exceeds the specified transmit triggering number.
+                  #0
+                
+                
+                  1
+                  The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number
+                  #1
+                
+              
+            
+            
+              RDF
+              Receive FIFO data full flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The quantity of receive data written in FRDR falls below the specified receive triggering number.
+                  #0
+                
+                
+                  1
+                  The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number.
+                  #1
+                
+              
+            
+            
+              ORER
+              Overrun Error Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No overrun error occurred
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred
+                  #1
+                
+              
+            
+            
+              FER
+              Framing Error Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No framing error occurred.
+                  #0
+                
+                
+                  1
+                  A framing error has occurred.
+                  #1
+                
+              
+            
+            
+              PER
+              Parity Error Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No parity error occurred.
+                  #0
+                
+                
+                  1
+                  A parity error has occurred.
+                  #1
+                
+              
+            
+            
+              TEND
+              Transmit End Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  A character is being transmitted or standing by for transmission.
+                  #0
+                
+                
+                  1
+                  Character transfer has been completed.
+                  #1
+                
+              
+            
+            
+              DR
+              Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected)
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty)
+                  #0
+                
+                
+                  1
+                  Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number.
+                  #1
+                
+              
+            
+          
+        
+        
+          SSR_SMCI
+          Serial Status Register(SCMR.SMIF = 1)
+          SSR
+          0x04
+          8
+          read-write
+          0x84
+          0xFF
+          
+            
+              TDRE
+              Transmit Data Empty Flag
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Transmit data is in TDR register
+                  #0
+                
+                
+                  1
+                  No transmit data is in TDR register
+                  #1
+                
+              
+            
+            
+              RDRF
+              Receive Data Full Flag
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No received data is in RDR register
+                  #0
+                
+                
+                  1
+                  Received data is in RDR register
+                  #1
+                
+              
+            
+            
+              ORER
+              Overrun Error Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No overrun error occurred
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred
+                  #1
+                
+              
+            
+            
+              ERS
+              Error Signal Status Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Low error signal not responded
+                  #0
+                
+                
+                  1
+                  Low error signal responded
+                  #1
+                
+              
+            
+            
+              PER
+              Parity Error Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No parity error occurred
+                  #0
+                
+                
+                  1
+                  A parity error has occurred
+                  #1
+                
+              
+            
+            
+              TEND
+              Transmit End Flag
+              2
+              2
+              read-only
+              
+                
+                  0
+                  A character is being transmitted.
+                  #0
+                
+                
+                  1
+                  Character transfer has been completed.
+                  #1
+                
+              
+            
+            
+              MPB
+              Multi-ProcessorThis bit should be 0 in smart card interface mode.
+              1
+              1
+              read-only
+            
+            
+              MPBT
+              Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode.
+              0
+              0
+              read-write
+            
+          
+        
+        
+          RDR
+          Receive Data Register
+          0x05
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              RDR
+              RDR is an 8-bit register that stores receive data.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          SCMR
+          Smart Card Mode Register
+          0x06
+          8
+          read-write
+          0xF2
+          0xFF
+          
+            
+              BCP2
+              Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits
+              7
+              7
+              read-write
+              
+                
+                  0
+                  S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11)
+                  #0
+                
+                
+                  1
+                  S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11)
+                  #1
+                
+              
+            
+            
+              CHR1
+              Character Length 1(Only valid in asynchronous mode)
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Transmit/receive in 9-bit data length
+                  #0
+                
+                
+                  1
+                  Transmit/receive in 8-bit data length(SMR.CHR=0) /  in 7bit data length(SMR.CHR=1)
+                  #1
+                
+              
+            
+            
+              SDIR
+              Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Transfer with LSB first
+                  #0
+                
+                
+                  1
+                  Transfer with MSB first 
+                  #1
+                
+              
+            
+            
+              SINV
+              Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode.
+              2
+              2
+              read-write
+              
+                
+                  0
+                  TDR contents are transmitted as they are. Receive data is stored as it is in RDR.
+                  #0
+                
+                
+                  1
+                  TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR.
+                  #1
+                
+              
+            
+            
+              SMIF
+              Smart Card Interface Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode)
+                  #0
+                
+                
+                  1
+                  Smart card interface mode
+                  #1
+                
+              
+            
+          
+        
+        
+          SEMR
+          Serial Extended Mode Register
+          0x07
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              RXDESEL
+              Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The low level on the RXDn pin is detected as the start bit.
+                  #0
+                
+                
+                  1
+                  A falling edge on the RXDn pin is detected as the start bit.
+                  #1
+                
+              
+            
+            
+              BGDM
+              Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode).
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Baud rate generator outputs the clock with normal frequency.
+                  #0
+                
+                
+                  1
+                  Baud rate generator outputs the clock with doubled frequency.
+                  #1
+                
+              
+            
+            
+              NFEN
+              Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input.
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled.
+                  #0
+                
+                
+                  1
+                  Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled.
+                  #1
+                
+              
+            
+            
+              ABCS
+              Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Selects 16 base clock cycles for 1-bit period.
+                  #0
+                
+                
+                  1
+                  Selects 8 base clock cycles for 1-bit period.
+                  #1
+                
+              
+            
+            
+              ABCSE
+              Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. 
+                  #0
+                
+                
+                  1
+                  Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator.
+                  #1
+                
+              
+            
+            
+              BRME
+              Bit Rate Modulation Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Bit rate modulation function is disabled.
+                  #0
+                
+                
+                  1
+                  Bit rate modulation function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          SNFR
+          Noise Filter Setting Register
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              NFCS
+              Noise Filter Clock Select
+              0
+              2
+              read-write
+              
+                
+                  000
+                  The clock signal divided by 1 is used with the noise filter.(In asynchronous mode)
+                  #000
+                
+                
+                  001
+                  The clock signal divided by 1 is used with the noise filter.(In simple I2C mode)
+                  #001
+                
+                
+                  010
+                  The clock signal divided by 2 is used with the noise filter.(In simple I2C mode)
+                  #010
+                
+                
+                  011
+                  The clock signal divided by 4 is used with the noise filter.(In simple I2C mode)
+                  #011
+                
+                
+                  100
+                  The clock signal divided by 8 is used with the noise filter.(In simple I2C mode)
+                  #100
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          SIMR1
+          I2C Mode Register 1
+          0x09
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              IICDL
+              SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator.
+              3
+              7
+              read-write
+              
+                
+                  00000
+                  No output delay
+                  #00000
+                
+                
+                  others
+                  (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator.
+                  true
+                
+              
+            
+            
+              IICM
+              Simple I2C Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1)
+                  #0
+                
+                
+                  1
+                  Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) 
+                  #1
+                
+              
+            
+          
+        
+        
+          SIMR2
+          I2C Mode Register 2
+          0x0A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              IICACKT
+              ACK Transmission Data
+              5
+              5
+              read-write
+              
+                
+                  0
+                  ACK transmission
+                  #0
+                
+                
+                  1
+                  NACK transmission and reception of ACK/NACK
+                  #1
+                
+              
+            
+            
+              IICCSC
+              Clock Synchronization
+              1
+              1
+              read-write
+              
+                
+                  0
+                  No synchronization with the clock signal
+                  #0
+                
+                
+                  1
+                  Synchronization with the clock signal
+                  #1
+                
+              
+            
+            
+              IICINTM
+              I2C Interrupt Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Use ACK/NACK interrupts.
+                  #0
+                
+                
+                  1
+                  Use reception and transmission interrupts
+                  #1
+                
+              
+            
+          
+        
+        
+          SIMR3
+          I2C Mode Register 3
+          0x0B
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              IICSCLS
+              SCL Output Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  Serial clock output
+                  #00
+                
+                
+                  01
+                  Generate a start, restart, or stop condition.
+                  #01
+                
+                
+                  10
+                  Output the low level on the SSCLn pin.
+                  #10
+                
+                
+                  11
+                  Place the SSCLn pin in the high-impedance state.
+                  #11
+                
+              
+            
+            
+              IICSDAS
+              SDA Output Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  Serial data output
+                  #00
+                
+                
+                  01
+                  Generate a start, restart, or stop condition.
+                  #01
+                
+                
+                  10
+                  Output the low level on the SSDAn pin.
+                  #10
+                
+                
+                  11
+                  Place the SSDAn pin in the high-impedance state.
+                  #11
+                
+              
+            
+            
+              IICSTIF
+              Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.)
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  There are no requests for generating conditions or a condition is being generated.
+                  #0
+                
+                
+                  1
+                  A start, restart, or stop condition is completely generated.
+                  #1
+                
+              
+            
+            
+              IICSTPREQ
+              Stop Condition Generation
+              2
+              2
+              read-write
+              
+                
+                  0
+                  A stop condition is not generated.
+                  #0
+                
+                
+                  1
+                  A stop condition is generated.
+                  #1
+                
+              
+            
+            
+              IICRSTAREQ
+              Restart Condition Generation
+              1
+              1
+              read-write
+              
+                
+                  0
+                  A restart condition is not generated.
+                  #0
+                
+                
+                  1
+                  A restart condition is generated.
+                  #1
+                
+              
+            
+            
+              IICSTAREQ
+              Start Condition Generation
+              0
+              0
+              read-write
+              
+                
+                  0
+                  A start condition is not generated.
+                  #0
+                
+                
+                  1
+                  A start condition is generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          SISR
+          I2C Status Register
+          0x0C
+          8
+          read-only
+          0x00
+          0xCB
+          
+            
+              IICACKR
+              ACK Reception Data Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  ACK received
+                  #0
+                
+                
+                  1
+                  NACK received
+                  #1
+                
+              
+            
+          
+        
+        
+          SPMR
+          SPI Mode Register
+          0x0D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CKPH
+              Clock Phase Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Clock is not delayed.
+                  #0
+                
+                
+                  1
+                  Clock is delayed.
+                  #1
+                
+              
+            
+            
+              CKPOL
+              Clock Polarity Select
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Clock polarity is not inverted.
+                  #0
+                
+                
+                  1
+                  Clock polarity is inverted
+                  #1
+                
+              
+            
+            
+              MFF
+              Mode Fault Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No mode fault error
+                  #0
+                
+                
+                  1
+                  Mode fault error
+                  #1
+                
+              
+            
+            
+              MSS
+              Master Slave Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Transmission is through the TXDn pin and reception is through the RXDn pin (master mode).
+                  #0
+                
+                
+                  1
+                  Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode).
+                  #1
+                
+              
+            
+            
+              CTSE
+              CTS Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  CTS function is disabled (RTS output function is enabled).
+                  #0
+                
+                
+                  1
+                  CTS function is enabled.
+                  #1
+                
+              
+            
+            
+              SSE
+              SSn Pin Function Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  SSn pin function is disabled.
+                  #0
+                
+                
+                  1
+                  SSn pin function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          TDRHL
+          Transmit 9-bit Data Register
+          0x0E
+          16
+          read-write
+          0xFFFF
+          0xFFFF
+          
+            
+              TDRHL
+              TDRHL is a 16-bit register that stores transmit data.
+              0
+              15
+              write-only
+            
+          
+        
+        
+          FTDRHL
+          Transmit FIFO Data Register HL
+          TDRHL
+          0x0E
+          16
+          write-only
+          0xFFFF
+          0xFFFF
+          
+            
+              MPBT
+              Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)
+              9
+              9
+              write-only
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+            
+              TDAT
+              Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              8
+              write-only
+            
+          
+        
+        
+          FTDRH
+          Transmit FIFO Data Register H
+          TDRHL
+          0x0E
+          8
+          write-only
+          0xFF
+          0xFF
+          
+            
+              MPBT
+              Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)
+              1
+              1
+              write-only
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+            
+              TDATH
+              Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              0
+              write-only
+            
+          
+        
+        
+          FTDRL
+          Transmit FIFO Data Register L
+          TDRHL
+          0x0F
+          8
+          write-only
+          0xFF
+          0xFF
+          
+            
+              TDATL
+              Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              7
+              write-only
+            
+          
+        
+        
+          RDRHL
+          Receive 9-bit Data Register
+          0x10
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              RDRHL
+              RDRHL is an 16-bit register that stores receive data.
+              0
+              15
+              read-only
+            
+          
+        
+        
+          FRDRHL
+          Receive FIFO Data Register HL
+          RDRHL
+          0x10
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              RDF
+              Receive FIFO data full flag(It is same as SSR.RDF)
+              14
+              14
+              read-only
+              
+                
+                  0
+                  The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.
+                  #0
+                
+                
+                  1
+                  The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.
+                  #1
+                
+              
+            
+            
+              ORER
+              Overrun error flag(It is same as SSR.ORER)
+              13
+              13
+              read-only
+              
+                
+                  0
+                  No overrun error occurred.
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred.
+                  #1
+                
+              
+            
+            
+              FER
+              Framing error flag
+              12
+              12
+              read-only
+              
+                
+                  0
+                  No framing error occurred at the first data of FRDRH and FRDRL.
+                  #0
+                
+                
+                  1
+                  A framing error has occurred at the first data of FRDRH and FRDRL.
+                  #1
+                
+              
+            
+            
+              PER
+              Parity error flag
+              11
+              11
+              read-only
+              
+                
+                  0
+                  No parity error occurred at the first data of FRDRH and FRDRL.
+                  #0
+                
+                
+                  1
+                  A parity error has occurred at the first data of FRDRH and FRDRL.
+                  #1
+                
+              
+            
+            
+              DR
+              Receive data ready flag(It is same as SSR.DR)
+              10
+              10
+              read-only
+              
+                
+                  0
+                  Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.
+                  #0
+                
+                
+                  1
+                  Next receive data has not been received for a period after normal completed receiving. 
+                  #1
+                
+              
+            
+            
+              MPB
+              Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])
+              9
+              9
+              read-only
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+            
+              RDAT
+              Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              8
+              read-only
+            
+          
+        
+        
+          FRDRH
+          Receive FIFO Data Register H
+          RDRHL
+          0x10
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              RDF
+              Receive FIFO data full flag(It is same as SSR.RDF)
+              6
+              6
+              read-only
+              
+                
+                  0
+                  The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number.
+                  #0
+                
+                
+                  1
+                  The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number.
+                  #1
+                
+              
+            
+            
+              ORER
+              Overrun error flag(It is same as SSR.ORER)
+              5
+              5
+              read-only
+              
+                
+                  0
+                  No overrun error occurred
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred
+                  #1
+                
+              
+            
+            
+              FER
+              Framing error flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  No framing error occurred at the first data of FRDRH and FRDRL
+                  #0
+                
+                
+                  1
+                  A framing error has occurred at the first data of FRDRH and FRDRL
+                  #1
+                
+              
+            
+            
+              PER
+              Parity error flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  No parity error occurred at the first data of FRDRH and FRDRL
+                  #0
+                
+                
+                  1
+                  A parity error has occurred at the first data of FRDRH and FRDRL
+                  #1
+                
+              
+            
+            
+              DR
+              Receive data ready flag(It is same as SSR.DR)
+              2
+              2
+              read-only
+              
+                
+                  0
+                  Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving.
+                  #0
+                
+                
+                  1
+                  Next receive data has not been received for a period after normal completed receiving. 
+                  #1
+                
+              
+            
+            
+              MPB
+              Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Data transmission cycles
+                  #0
+                
+                
+                  1
+                  ID transmission cycles
+                  #1
+                
+              
+            
+            
+              RDATH
+              Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              0
+              read-only
+            
+          
+        
+        
+          FRDRL
+          Receive FIFO Data Register L
+          RDRHL
+          0x11
+          8
+          read-only
+          0x00
+          0xFF
+          
+            
+              RDATL
+              Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          MDDR
+          Modulation Duty Register
+          0x12
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              MDDR
+              MDDR corrects the bit rate adjusted by the BRR register.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          DCCR
+          Data Compare Match Control Register
+          0x13
+          8
+          read-write
+          0x40
+          0xFF
+          
+            
+              DCME
+              Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Address match function is disabled.
+                  #0
+                
+                
+                  1
+                  Address match function is enabled
+                  #1
+                
+              
+            
+            
+              IDSEL
+              ID frame select(Valid only in asynchronous mode(including multi-processor) 
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Always compare data regardless of the value of the MPB bit.
+                  #0
+                
+                
+                  1
+                  Compare data when the MPB bit is 1 (ID frame) only.
+                  #1
+                
+              
+            
+            
+              DFER
+              Data Compare Match Framing Error Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No framing error occurred
+                  #0
+                
+                
+                  1
+                  A framing error has occurred
+                  #1
+                
+              
+            
+            
+              DPER
+              Data Compare Match Parity Error Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No parity error occurred
+                  #0
+                
+                
+                  1
+                  A parity error has occurred
+                  #1
+                
+              
+            
+            
+              DCMF
+              Data Compare Match Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No matched 
+                  #0
+                
+                
+                  1
+                  Matched
+                  #1
+                
+              
+            
+          
+        
+        
+          FCR
+          FIFO Control Register
+          0x14
+          16
+          read-write
+          0xF800
+          0xFFFF
+          
+            
+              RSTRG
+              RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
+              12
+              15
+              read-write
+              
+                
+                  0000
+                  Trigger number 0
+                  #0000
+                
+                
+                  others
+                  Triger number n (n= 0-15)
+                  true
+                
+              
+            
+            
+              RTRG
+              Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
+              8
+              11
+              read-write
+              
+                
+                  0000
+                  Trigger number 0
+                  #0000
+                
+                
+                  others
+                  Triger number n (n= 0-15)
+                  true
+                
+              
+            
+            
+              TTRG
+              Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
+              4
+              7
+              read-write
+              
+                
+                  0000
+                  Trigger number 0
+                  #0000
+                
+                
+                  others
+                  Triger number n (n= 0-15)
+                  true
+                
+              
+            
+            
+              DRES
+              Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.)
+              3
+              3
+              read-write
+              
+                
+                  0
+                  reception data full interrupt (RXI)
+                  #0
+                
+                
+                  1
+                  receive error interrupt (ERI)
+                  #1
+                
+              
+            
+            
+              TFRST
+              Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)
+              2
+              2
+              read-write
+              
+                
+                  0
+                  The number of data stored in FTDRH and FTDRL register are NOT made 0
+                  #0
+                
+                
+                  1
+                  The number of data stored in FTDRH and FTDRL register are made 0
+                  #1
+                
+              
+            
+            
+              RFRST
+              Receive FIFO Data Register Reset(Valid only in FCR.FM=1)
+              1
+              1
+              read-write
+              
+                
+                  0
+                  The number of data stored in FRDRH and FRDRL register are NOT made 0
+                  #0
+                
+                
+                  1
+                  The number of data stored in FRDRH and FRDRL register are made 0
+                  #1
+                
+              
+            
+            
+              FM
+              FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Non-FIFO mode(Selects o TDR/RDR for communication)
+                  #0
+                
+                
+                  1
+                  FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication)
+                  #1
+                
+              
+            
+          
+        
+        
+          FDR
+          FIFO Data Count Register
+          0x16
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              T
+              Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)
+              8
+              12
+              read-only
+            
+            
+              R
+              Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1)
+              0
+              4
+              read-only
+            
+          
+        
+        
+          LSR
+          Line Status Register
+          0x18
+          16
+          read-only
+          0x0000
+          0xFFFF
+          
+            
+              PNUM
+              Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).
+              8
+              12
+              read-only
+            
+            
+              FNUM
+              Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL).
+              2
+              6
+              read-only
+            
+            
+              ORER
+              Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)
+              0
+              0
+              read-only
+              
+                
+                  0
+                  No overrun error occurred
+                  #0
+                
+                
+                  1
+                  An overrun error has occurred
+                  #1
+                
+              
+            
+          
+        
+        
+          CDR
+          Compare Match Data Register
+          0x1A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CMPD
+              Compare Match DataCompare data pattern for address match wake-up function 
+              0
+              8
+              read-write
+            
+          
+        
+        
+          SPTR
+          Serial Port Register
+          0x1C
+          8
+          read-write
+          0x03
+          0xFF
+          
+            
+              SPB2IO
+              Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)
+              2
+              2
+              read-write
+              
+                
+                  0
+                  The value of SPB2DT bit is not output in TXD pin.
+                  #0
+                
+                
+                  1
+                  The value of SPB2DT bit is output in TXD pin.
+                  #1
+                
+              
+            
+            
+              SPB2DT
+              Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Low level is output on TXD pin
+                  #0
+                
+                
+                  1
+                  High level is output on TXD pin
+                  #1
+                
+              
+            
+            
+              RXDMON
+              Serial input data monitor bit(The state of the RXD terminal is shown.)
+              0
+              0
+              read-only
+              
+                
+                  0
+                  RXD pin is low.
+                  #0
+                
+                
+                  1
+                  RXD pin is high.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_SCI1
+      0x40070020
+    
+    
+      R_SCI2
+      0x40070040
+    
+    
+      R_SCI3
+      0x40070060
+    
+    
+      R_SCI4
+      0x40070080
+    
+    
+      R_SCI5
+      0x400700A0
+    
+    
+      R_SCI6
+      0x400700C0
+    
+    
+      R_SCI7
+      0x400700E0
+    
+    
+      R_SCI8
+      0x40070100
+    
+    
+      R_SCI9
+      0x40070120
+    
+    
+      R_SDADC0
+      
+      0x4009C000
+      
+        0x00000000
+        0x02
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000008
+        0x019
+        registers
+      
+      
+        0x00000024
+        0x008
+        registers
+      
+      
+        0x00000030
+        0x01
+        registers
+      
+      
+        0x00000034
+        0x01
+        registers
+      
+      
+        0x0000003C
+        0x01
+        registers
+      
+      
+        
+          STC1
+          Startup Control Register 1
+          0x0
+          16
+          read-write
+          0XFFFF
+          
+            
+              VSBIAS
+              Reference voltage select
+              8
+              11
+              read-write
+              
+                
+                  0000
+                  0.8V
+                  #0000
+                
+                
+                  0001
+                  1.0V
+                  #0001
+                
+                
+                  0010
+                  1.2V
+                  #0010
+                
+                
+                  0011
+                  1.4V
+                  #0011
+                
+                
+                  0100
+                  1.6V
+                  #0100
+                
+                
+                  0101
+                  1.8V
+                  #0101
+                
+                
+                  0110
+                  2.0V
+                  #0110
+                
+                
+                  0111
+                  2.2V
+                  #0111
+                
+                
+                  1111
+                  2.4V(only available when VREFSEL=0)
+                  #1111
+                
+              
+            
+            
+              CLKDIV
+              SDADC24 Reference Clock Division
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  No Division
+                  #0000
+                
+                
+                  0001
+                  SDADCCLK/2
+                  #0001
+                
+                
+                  0010
+                  SDADCCLK/3
+                  #0010
+                
+                
+                  0011
+                  SDADCCLK/4
+                  #0011
+                
+                
+                  0100
+                  SDADCCLK/5
+                  #0100
+                
+                
+                  0101
+                  SDADCCLK/6
+                  #0101
+                
+                
+                  0110
+                  SDADCCLK/8
+                  #0110
+                
+                
+                  0111
+                  SDADCCLK/12
+                  #0111
+                
+                
+                  1000
+                  SDADCCLK/16
+                  #1000
+                
+              
+            
+            
+              SDADLPM
+              A/D conversion operation model select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Normal A/D conversion mode, SDADC Reference Clock: 4 MHz, Oversampingly clock: 1MHz
+                  #0
+                
+              
+            
+            
+              VREFSEL
+              VREF mode select
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Internal VREF Mode
+                  #0
+                
+              
+            
+          
+        
+        
+          STC2
+          Startup Control Register 2
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BGRPON
+              BGR part power control
+              0
+              0
+              
+                
+                  0
+                  Turn off power to ADBGR, SBIAS, VREFI, and ADREG
+                  #0
+                
+                
+                  1
+                  Turn onpower to ADBGR, SBIAS, VREFI, and ADREG
+                  #1
+                
+              
+            
+            
+              ADFPWDS
+              ADC reference supply part
+              2
+              2
+              
+                
+                  0
+                  Power of ADREG controlled by BGRPON register
+                  #0
+                
+                
+                  1
+                  Power of ADREG is off regardless of BGRPON setting
+                  #1
+                
+              
+            
+            
+              ADCPON
+              ADREG forced power-down
+              1
+              1
+              
+                
+                  0
+                  Turn off power to VBIAS, PGA and sigma-delta A/D converter
+                  #0
+                
+                
+                  1
+                  Turn on power to VBIAS, PGA and sigma-delta A/D converter
+                  #1
+                
+              
+            
+          
+        
+        
+          5
+          4
+          PGAC[%s]
+          Input Multiplexer %s Setting Register
+          0x08
+          32
+          read-write
+          0x00010040
+          0xFFFFFFFF
+          
+            
+              PGAASN
+              Selection of the mode for specifying the number of A/D conversions in ADSCAN
+              31
+              31
+              read-write
+              
+                
+                  0
+                  Specify 1 to 8,032 times by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits
+                  #0
+                
+                
+                  1
+                  Specify 1 to 255 times linearly by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits
+                  #1
+                
+              
+            
+            
+              PGACVE
+              Calibration enable
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Do not calculate the calibration correction factor
+                  #0
+                
+                
+                  1
+                  Calculate the calibration correction factor
+                  #1
+                
+              
+            
+            
+              PGAREV
+              Single-End Input A/D Converted Data Inversion Select
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Do not invert the conversion result data
+                  #0
+                
+                
+                  1
+                  Invert the conversion result data
+                  #1
+                
+              
+            
+            
+              PGAAVE
+              Selection of averaging processing
+              26
+              27
+              read-write
+              
+                
+                  00
+                  Do not average the A/D conversion results
+                  #00
+                
+                
+                  01
+                  Do not average the A/D conversion results
+                  #01
+                
+                
+                  10
+                  Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs
+                  #10
+                
+                
+                  11
+                  Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times).
+                  #11
+                
+              
+            
+            
+              PGAAVN
+              Selection of the number of data to be averaged
+              24
+              25
+              read-write
+              
+                
+                  00
+                  8
+                  #00
+                
+                
+                  01
+                  16
+                  #01
+                
+                
+                  10
+                  32
+                  #10
+                
+                
+                  11
+                  64
+                  #11
+                
+              
+            
+            
+              PGACTN
+              Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN
+              21
+              23
+              read-write
+              
+                
+                  000
+                  0
+                  #000
+                
+                
+                  001
+                  1
+                  #001
+                
+                
+                  010
+                  2
+                  #010
+                
+                
+                  011
+                  3
+                  #011
+                
+                
+                  100
+                  4
+                  #100
+                
+                
+                  101
+                  5
+                  #101
+                
+                
+                  110
+                  6
+                  #110
+                
+                
+                  111
+                  7
+                  #111
+                
+              
+            
+            
+              PGACTM
+              Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN
+              16
+              20
+              read-write
+            
+            
+              PGASEL
+              Analog Channel Input Mode Select
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Differential input mode
+                  #0
+                
+                
+                  1
+                  Single-end input mode
+                  #1
+                
+              
+            
+            
+              PGAPOL
+              Polarity select
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Positive-side single-end input
+                  #0
+                
+                
+                  1
+                  Negative-side single-end input
+                  #1
+                
+              
+            
+            
+              PGAOFS
+              Offset voltage select
+              8
+              12
+              read-write
+            
+            
+              PGAOSR
+              Oversampling ratio select
+              5
+              7
+              read-write
+              
+                
+                  000
+                  64
+                  #000
+                
+                
+                  001
+                  128
+                  #001
+                
+                
+                  010
+                  256
+                  #010
+                
+                
+                  011
+                  512
+                  #011
+                
+                
+                  100
+                  1024
+                  #100
+                
+                
+                  101
+                  2048
+                  #101
+                
+                
+                  others
+                  Settings are prohibited.
+                  true
+                
+              
+            
+            
+              PGAGC
+              Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal )
+              0
+              4
+              read-write
+              
+                
+                  00000
+                  (1, 1, 1)
+                  #00000
+                
+                
+                  00100
+                  (2, 1, 2)
+                  #00100
+                
+                
+                  01000
+                  (3, 1, 3)
+                  #01000
+                
+                
+                  01100
+                  (4, 1, 4)
+                  #01100
+                
+                
+                  10000
+                  (8, 1, 8)
+                  #10000
+                
+                
+                  00001
+                  (1, 2, 2)
+                  #00001
+                
+                
+                  00101
+                  (2, 2, 4)
+                  #00101
+                
+                
+                  01001
+                  (3, 2, 6)
+                  #01001
+                
+                
+                  01101
+                  (4, 2, 8)
+                  #01101
+                
+                
+                  10001
+                  (8, 2, 16)
+                  #10001
+                
+                
+                  00010
+                  (1, 4, 4)
+                  #00010
+                
+                
+                  00110
+                  (2, 4, 8)
+                  #00110
+                
+                
+                  01010
+                  (3, 4, 12)
+                  #01010
+                
+                
+                  01110
+                  (4, 4, 16)
+                  #01110
+                
+                
+                  10010
+                  (8, 4, 32)
+                  #10010
+                
+                
+                  00011
+                  (1, 8, 8)
+                  #00011
+                
+                
+                  00111
+                  (2, 8, 16)
+                  #00111
+                
+                
+                  01011
+                  (3, 8, 24)
+                  #01011
+                
+                
+                  01111
+                  (4, 8, 32).
+                  #01111
+                
+                
+                  others
+                  Settings are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          ADC1
+          Sigma-Delta A/D Converter Control Register 1
+          0x1C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              PGASLFT
+              PGA offset self-diagnosis enable
+              20
+              20
+              read-write
+              
+                
+                  0
+                  Disable PGA offset self-diagnosis
+                  #0
+                
+                
+                  1
+                  Enable PGA offset self-diagnosis
+                  #1
+                
+              
+            
+            
+              PGADISC
+              Disconnection Detection Assist Setting
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Discharge
+                  #0
+                
+                
+                  1
+                  Pre-charge
+                  #1
+                
+              
+            
+            
+              PGADISA
+              Control of disconnection detection
+              16
+              16
+              read-write
+              
+                
+                  0
+                  Normal operation
+                  #0
+                
+                
+                  1
+                  State of disconnection detection
+                  #1
+                
+              
+            
+            
+              SDADBMP
+              A/D conversion control of the signal from input multiplexer
+              8
+              12
+              read-write
+            
+            
+              SDADTMD
+              Selection of A/D conversion trigger signal
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Software trigger (conversion is started by a write to SFR)
+                  #0
+                
+                
+                  1
+                  Hardware trigger (conversion is started in synchronization with the event signal selected by ELC_SDADC24).
+                  #1
+                
+              
+            
+            
+              SDADSCM
+              Selection of autoscan mode
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Continuous scan mode
+                  #0
+                
+                
+                  1
+                  Single scan mode
+                  #1
+                
+              
+            
+          
+        
+        
+          ADC2
+          Sigma-Delta A/D Converter Control Register 2
+          0x20
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SDADST
+              Control of A/D conversion
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Stop A/D conversion
+                  #0
+                
+                
+                  1
+                  Start A/D conversion
+                  #1
+                
+              
+            
+          
+        
+        
+          ADCR
+          Sigma-delta A/D Converter Conversion Result Register
+          0x24
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SDADCRC
+              Channel number for an A/D conversion result
+              25
+              27
+              read-only
+              
+                
+                  000
+                  Reset value (Conversion result is invalid)
+                  #000
+                
+                
+                  001
+                  Input multiplexer 0 (ANSD0P / ANSD0N)
+                  #001
+                
+                
+                  010
+                  Input multiplexer 1 (ANSD1P / ANSD1N)
+                  #010
+                
+                
+                  011
+                  Input multiplexer 2 (ANSD2P / ANSD2N)
+                  #011
+                
+                
+                  100
+                  Input multiplexer 3 (ANSD3P / ANSD3N)
+                  #100
+                
+                
+                  101
+                  Input multiplexer 4 (AMP0O / AMP1O)
+                  #101
+                
+              
+            
+            
+              SDADCRS
+              Status of an A/D conversion result
+              24
+              24
+              read-only
+              
+                
+                  0
+                  Normal status (within the range)
+                  #0
+                
+                
+                  1
+                  Overflow occurred
+                  #1
+                
+              
+            
+            
+              SDADCRD
+              The 24-bit A/D conversion result
+              0
+              23
+              read-only
+            
+          
+        
+        
+          ADAR
+          Sigma-delta A/D Converter Average Value Register
+          0x28
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SDADMVC
+              Channel number for an A/D conversion result
+              25
+              27
+              read-only
+              
+                
+                  000
+                  Reset value (Conversion result is invalid)
+                  #000
+                
+                
+                  001
+                  Input multiplexer 0 (ANSD0P / ANSD0N)
+                  #001
+                
+                
+                  010
+                  Input multiplexer 1 (ANSD1P / ANSD1N)
+                  #010
+                
+                
+                  011
+                  Input multiplexer 2 (ANSD2P / ANSD2N)
+                  #011
+                
+                
+                  100
+                  Input multiplexer 3 (ANSD3P / ANSD3N)
+                  #100
+                
+                
+                  101
+                  Input multiplexer 4 (AMP0O / AMP1O).
+                  #101
+                
+              
+            
+            
+              SDADMVS
+              Status of an A/D conversion result
+              24
+              24
+              read-only
+              
+                
+                  0
+                  Normal status (within the range)
+                  #0
+                
+                
+                  1
+                  Overflow occurred
+                  #1
+                
+              
+            
+            
+              SDADMVD
+              The 24-bit A/D average value
+              0
+              23
+              read-only
+            
+          
+        
+        
+          CLBC
+          Calibration Control Register
+          0x30
+          8
+          0x00
+          0xFF
+          
+            
+              CLBMD
+              These bits are read as 0. The write value should be 0.
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Internal calibration mode
+                  #00
+                
+                
+                  01
+                  External offset calibration mode
+                  #01
+                
+                
+                  10
+                  External gain calibration mode
+                  #10
+                
+                
+                  11
+                  Settings are prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          CLBSTR
+          Calibration Start Control Register
+          0x34
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CLBST
+              Calibration start control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable writing
+                  #0
+                
+                
+                  1
+                  Start calibration
+                  #1
+                
+              
+            
+          
+        
+        
+          CLBSSR
+          Calibration Status Register
+          0x3C
+          8
+          read-only
+          0x00
+          
+            
+              CLBSS
+              Calibration status
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Calibration is not running
+                  #0
+                
+                
+                  1
+                  Calibration is running
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_SDHI0
+      SD/MMC Host Interface
+      0x40062000
+      
+        0x00000000
+        0x04
+        registers
+      
+      
+        0x00000008
+        0x04C
+        registers
+      
+      
+        0x00000058
+        0x00C
+        registers
+      
+      
+        0x00000068
+        0x00C
+        registers
+      
+      
+        0x000001B0
+        0x04
+        registers
+      
+      
+        0x000001C0
+        0x04
+        registers
+      
+      
+        0x000001CC
+        0x04
+        registers
+      
+      
+        0x000001E0
+        0x04
+        registers
+      
+      
+        
+          SD_CMD
+          Command Type Register
+          0x000
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CMD12AT
+              Multiple Block Transfer Mode (enabled at multiple block transfer)
+              14
+              15
+              read-write
+              
+                
+                  00
+                  CMD12 is automatically issued at multiple block transfer.
+                  #00
+                
+                
+                  01
+                  CMD12 is not automatically issued at multiple block transfer.
+                  #01
+                
+                
+                  10
+                  Setting prohibited
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              TRSTP
+              Single/Multiple Block Transfer (enabled when the command with data is handled)
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Single block transfer
+                  #0
+                
+                
+                  1
+                  Multiple block transfer
+                  #1
+                
+              
+            
+            
+              CMDRW
+              Write/Read Mode (enabled when the command with data is handled)
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Write (SD/MMC host interface -> SD card/MMC)
+                  #0
+                
+                
+                  1
+                  Read (SD/MMC host interface <- SD card/MMC)
+                  #1
+                
+              
+            
+            
+              CMDTP
+              Data Mode (Command Type)
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Command does not include data transfer (bc, bcr, or ac)
+                  #0
+                
+                
+                  1
+                  Command includes data transfer (adtc)
+                  #1
+                
+              
+            
+            
+              RSPTP
+              Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type.
+              8
+              10
+              read-write
+              
+                
+                  000
+                  Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. 
+                  #000
+                
+                
+                  011
+                  Expansion mode and no response
+                  #011
+                
+                
+                  100
+                  Expansion mode and R1, R5, R6, or R7 response
+                  #100
+                
+                
+                  101
+                  Expansion mode and R1b response
+                  #101
+                
+                
+                  110
+                  Expansion mode and R2 response
+                  #110
+                
+                
+                  111
+                  Expansion mode and R3 or R4 response
+                  #111
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+            
+              ACMD
+              Command Type Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  CMD
+                  #00
+                
+                
+                  01
+                  ACMD
+                  #01
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              CMDIDX
+              Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SD_ARG
+          SD Command Argument Register
+          0x008
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_ARG
+              Argument RegisterSet command format[39:8] (argument)
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SD_ARG1
+          SD Command Argument Register 1
+          0x00C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_ARG1
+              Argument Register 1Set command format[39:24] (argument)
+              0
+              15
+              read-write
+            
+          
+        
+        
+          SD_STOP
+          Data Stop Register
+          0x010
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SEC
+              Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1.
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Disables SD_SECCNT setting value.
+                  #0
+                
+                
+                  1
+                  Enables SD_SECCNT setting value.
+                  #1
+                
+              
+            
+            
+              STP
+              Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set.
+              0
+              0
+              read-write
+            
+          
+        
+        
+          SD_SECCNT
+          Block Count Register
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_SECCNT
+              Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1.
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SD_RSP10
+          SD Card Response Register 10
+          0x018
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP10
+              Store the response from the SD card/MMC
+              0
+              31
+              read-only
+            
+          
+        
+        
+          SD_RSP1
+          SD Card Response Register 1
+          0x01C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP1
+              Store the response from the SD card/MMC
+              0
+              15
+              read-only
+            
+          
+        
+        
+          SD_RSP32
+          SD Card Response Register 32
+          0x020
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP32
+              Store the response from the SD card/MMC
+              0
+              31
+              read-only
+            
+          
+        
+        
+          SD_RSP3
+          SD Card Response Register 3
+          0x024
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP3
+              Store the response from the SD card/MMC
+              0
+              15
+              read-only
+            
+          
+        
+        
+          SD_RSP54
+          SD Card Response Register 54
+          0x028
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP54
+              Store the response from the SD card/MMC
+              0
+              31
+              read-only
+            
+          
+        
+        
+          SD_RSP5
+          SD Card Response Register 5
+          0x02C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP5
+              Store the response from the SD card/MMC
+              0
+              15
+              read-only
+            
+          
+        
+        
+          SD_RSP76
+          SD Card Response Register 76
+          0x030
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP76
+              Store the response from the SD card/MMC
+              0
+              23
+              read-only
+            
+          
+        
+        
+          SD_RSP7
+          SD Card Response Register 7
+          0x034
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SD_RSP7
+              Store the response from the SD card/MMC
+              0
+              7
+              read-only
+            
+          
+        
+        
+          SD_INFO1
+          SD Card Interrupt Flag Register 1
+          0x038
+          32
+          read-write
+          0x00000000
+          0xFFFFFB5F
+          
+            
+              SDD3MON
+              Inticates the SDnDAT3 State
+              10
+              10
+              read-only
+              
+                
+                  0
+                  SDnDAT3 is set to 0.
+                  #0
+                
+                
+                  1
+                  SDnDAT3 is set to 1.
+                  #1
+                
+              
+            
+            
+              SDD3IN
+              SDnDAT3 Card Insertion
+              9
+              9
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SD card insertion not detected
+                  #0
+                
+                
+                  1
+                  SD card insertion detected
+                  #1
+                
+              
+            
+            
+              SDD3RM
+              SDnDAT3 Card Removal
+              8
+              8
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SD card removal not detected
+                  #0
+                
+                
+                  1
+                  SD card removal detected
+                  #1
+                
+              
+            
+            
+              SDWPMON
+              Indicates the SDnWP state
+              7
+              7
+              read-only
+              
+                
+                  0
+                  SDnWP is set to 1.
+                  #0
+                
+                
+                  1
+                  SDnWP is set to 0.
+                  #1
+                
+              
+            
+            
+              SDCDMON
+              Indicates the SDnCD state
+              5
+              5
+              read-only
+              
+                
+                  0
+                  Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.)
+                  #0
+                
+                
+                  1
+                  Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.)
+                  #1
+                
+              
+            
+            
+              SDCDIN
+              SDnCD Card Insertion
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Card insertion not detected
+                  #0
+                
+                
+                  1
+                  Card insertion detected
+                  #1
+                
+              
+            
+            
+              SDCDRM
+              SDnCD  Card Removal
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Card removal not detected
+                  #0
+                
+                
+                  1
+                  Card removal detected
+                  #1
+                
+              
+            
+            
+              ACEND
+              Access End
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Access end is not detected
+                  #0
+                
+                
+                  1
+                  Access end is detected
+                  #1
+                
+              
+            
+            
+              RSPEND
+              Response End Detection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Response end is not detected
+                  #0
+                
+                
+                  1
+                  Response end is detected
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_INFO2
+          SD Card Interrupt Flag Register 2
+          0x03C
+          32
+          read-write
+          0x00002000
+          0xFFFFFF7F
+          
+            
+              ILA
+              Illegal Access Error
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Illegal access error not detected
+                  #0
+                
+                
+                  1
+                  Illegal access error detected
+                  #1
+                
+              
+            
+            
+              CBSY
+              Command Type Register Busy
+              14
+              14
+              read-only
+              
+                
+                  0
+                  A command sequence is being executed.
+                  #0
+                
+                
+                  1
+                  A command sequence has been completed.
+                  #1
+                
+              
+            
+            
+              SD_CLK_CTRLEN
+              When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence.
+              13
+              13
+              read-only
+              
+                
+                  0
+                  The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible.
+                  #0
+                
+                
+                  1
+                  The SD/MMC bus (CMD, DAT) is not busy.
+                  #1
+                
+              
+            
+            
+              BWE
+              SD_BUF Write Enable
+              9
+              9
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  1
+                  Data can be written in SD_BUF0.
+                  #1
+                
+                
+                  0
+                  Data cannot be written in SD_BUF0.
+                  #0
+                
+              
+            
+            
+              BRE
+              SD_BUF Read Enable
+              8
+              8
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  1
+                  Data can be read from SD_BUF0.
+                  #1
+                
+                
+                  0
+                  Data cannot be read from SD_BUF0.
+                  #0
+                
+              
+            
+            
+              SDD0MON
+              SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL.
+              7
+              7
+              read-only
+              
+                
+                  1
+                  SDDAT0 is set to 1.
+                  #1
+                
+                
+                  0
+                  SDDAT0 is set to 0.
+                  #0
+                
+              
+            
+            
+              RSPTO
+              Response Timeout
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Response timeout not detected
+                  #0
+                
+                
+                  1
+                  Response timeout detected
+                  #1
+                
+              
+            
+            
+              ILR
+              SD_BUF Illegal Read Access
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Illegal read access to the SD_BUF register not detected
+                  #0
+                
+                
+                  1
+                  Illegal read access to the SD_BUF register detected
+                  #1
+                
+              
+            
+            
+              ILW
+              SD_BUF Illegal Write Access
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Illegal write access to the SD_BUF register not detected
+                  #0
+                
+                
+                  1
+                  Illegal write access to the SD_BUF register detected
+                  #1
+                
+              
+            
+            
+              DTO
+              Data Timeout 
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Data timeout not detected
+                  #0
+                
+                
+                  1
+                  Data timeout detected
+                  #1
+                
+              
+            
+            
+              ENDE
+              END Error
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  End bit error not detected
+                  #0
+                
+                
+                  1
+                  End bit error detected
+                  #1
+                
+              
+            
+            
+              CRCE
+              CRC Error
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  CRC error not detected
+                  #0
+                
+                
+                  1
+                  CRC error detected
+                  #1
+                
+              
+            
+            
+              CMDE
+              Command Error
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Command error not detected
+                  #0
+                
+                
+                  1
+                  Command error detected
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_INFO1_MASK
+          SD_INFO1 Interrupt Mask Register
+          0x040
+          32
+          read-write
+          0x0000031D
+          0xFFFFFFFF
+          
+            
+              SDD3INM
+              SDnDAT3 Card Insertion Interrupt Request Mask
+              9
+              9
+              read-write
+              
+                
+                  0
+                  SD card insertion interrupt request by the SDnDAT3  is not masked
+                  #0
+                
+                
+                  1
+                  SD card insertion interrupt request by the SDnDAT3 is masked
+                  #1
+                
+              
+            
+            
+              SDD3RMM
+              SDnDAT3 Card Removal Interrupt Request Mask
+              8
+              8
+              read-write
+              
+                
+                  0
+                  SD card removal interrupt request by the SDnDAT3 is not masked
+                  #0
+                
+                
+                  1
+                  SD card removal interrupt request by the SDnDAT3 is masked
+                  #1
+                
+              
+            
+            
+              SDCDINM
+              SDnCD card Insertion Interrupt Request Mask
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Card insertion interrupt request by the SDnCD is not masked
+                  #0
+                
+                
+                  1
+                  Card insertion interrupt request by the SDnCD is masked
+                  #1
+                
+              
+            
+            
+              SDCDRMM
+              SDnCD card Removal Interrupt Request Mask
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Card removal interrupt request by the by the SDnCD is not masked
+                  #0
+                
+                
+                  1
+                  Card removal interrupt request by the by the SDnCD is masked
+                  #1
+                
+              
+            
+            
+              ACENDM
+               Access End Interrupt Request Mask
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Access end interrupt request is not masked
+                  #0
+                
+                
+                  1
+                  Access end interrupt request is masked
+                  #1
+                
+              
+            
+            
+              RSPENDM
+               Response End Interrupt Request Mask
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Response end interrupt request is not masked
+                  #0
+                
+                
+                  1
+                  Response end interrupt request is masked
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_INFO2_MASK
+          SD_INFO2 Interrupt Mask Register
+          0x044
+          32
+          read-write
+          0x00008B7F
+          0xFFFFFFFF
+          
+            
+              ILAM
+              Illegal Access Error Interrupt Request Mask
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Illegal access error interrupt request not masked
+                  #0
+                
+                
+                  1
+                  Illegal access error interrupt request masked
+                  #1
+                
+              
+            
+            
+              BWEM
+              BWE Interrupt Request Mask
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Write enable interrupt request for the SD_BUF register not masked
+                  #0
+                
+                
+                  1
+                  Write enable interrupt request for the SD_BUF register masked
+                  #1
+                
+              
+            
+            
+              BREM
+              BRE Interrupt Request Mask
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Read enable interrupt request for the SD buffer not masked
+                  #0
+                
+                
+                  1
+                  Read enable interrupt request for the SD buffer masked
+                  #1
+                
+              
+            
+            
+              RSPTOM
+               Response Timeout Interrupt Request Mask
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Response timeout interrupt request not masked
+                  #0
+                
+                
+                  1
+                  Response timeout interrupt request masked
+                  #1
+                
+              
+            
+            
+              ILRM
+              SD_BUF Register Illegal Read Interrupt Request Mask
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Illegal read detection interrupt request for the SD_BUF register not masked
+                  #0
+                
+                
+                  1
+                  Illegal read detection interrupt request for the SD_BUF register masked
+                  #1
+                
+              
+            
+            
+              ILWM
+              SD_BUF Register Illegal Write Interrupt Request Mask
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Illegal write detection interrupt request for the SD_BUF register not masked
+                  #0
+                
+                
+                  1
+                  Illegal write detection interrupt request for the SD_BUF register masked
+                  #1
+                
+              
+            
+            
+              DTOM
+               Data Timeout Interrupt Request Mask
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Data timeout interrupt request not masked
+                  #0
+                
+                
+                  1
+                  Data timeout interrupt request masked
+                  #1
+                
+              
+            
+            
+              ENDEM
+               End Bit Error Interrupt Request Mask
+              2
+              2
+              read-write
+              
+                
+                  0
+                  End bit detection error interrupt request not masked
+                  #0
+                
+                
+                  1
+                  End bit detection error interrupt request masked
+                  #1
+                
+              
+            
+            
+              CRCEM
+              CRC Error Interrupt Request Mask
+              1
+              1
+              read-write
+              
+                
+                  0
+                  CRC error interrupt request not masked
+                  #0
+                
+                
+                  1
+                  CRC error interrupt request masked
+                  #1
+                
+              
+            
+            
+              CMDEM
+              Command Error Interrupt Request Mask
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Command error interrupt request not masked
+                  #0
+                
+                
+                  1
+                  Command error interrupt request masked
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_CLK_CTRL
+          SD Clock Control Register
+          0x048
+          32
+          read-write
+          0x00000020
+          0xFFFFFFFF
+          
+            
+              CLKCTRLEN
+              SD/MMC Clock Output Automatic Control Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Automatic control for SD/MMC Clock output is disabled.
+                  #0
+                
+                
+                  1
+                  Automatic control for SD/MMC Clock output is enabled.
+                  #1
+                
+              
+            
+            
+              CLKEN
+              SD/MMC Clock Output Control Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  SD/MMC Clock output is disabled. The SDCLK signal is fixed 0.
+                  #0
+                
+                
+                  1
+                  SD/MMC Clock output is enabled.
+                  #1
+                
+              
+            
+            
+              CLKSEL
+              SDHI Clock Frequency Select
+              0
+              7
+              read-write
+              
+                
+                  0x00
+                  PCLKA divided by 2
+                  0x00
+                
+                
+                  0x01
+                  PCLKA divided by 4
+                  0x01
+                
+                
+                  0x02
+                  PCLKA divided by 8
+                  0x02
+                
+                
+                  0x04
+                  PCLKA divided by 16
+                  0x04
+                
+                
+                  0x08
+                  PCLKA divided by 32
+                  0x08
+                
+                
+                  0x10
+                  PCLKA divided by 64
+                  0x10
+                
+                
+                  0x20
+                  PCLKA divided by 128
+                  0x20
+                
+                
+                  0x40
+                  PCLKA divided by 256
+                  0x40
+                
+                
+                  0x80
+                  PCLKA divided by 512
+                  0x80
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          SD_SIZE
+          Transfer Data Length Register
+          0x04C
+          32
+          read-write
+          0x00000200
+          0xFFFFFFFF
+          
+            
+              LEN
+              Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0.
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SD_OPTION
+          SD Card Access Control Option Register
+          0x050
+          32
+          read-write
+          0x000040EE
+          0xFFFFFFFF
+          
+            
+              WIDTH
+              Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0.
+              15
+              15
+              read-write
+              
+                
+                  0
+                  4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1)  
+                  #0
+                
+                
+                  1
+                  1-bit width (WIDTH8=0 or 1 ) 
+                  #1
+                
+              
+            
+            
+              WIDTH8
+              Bus Widthsee b15, WIDTH bit
+              13
+              13
+              read-write
+            
+            
+              TOUTMASK
+              Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence.
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Activate Timeout
+                  #0
+                
+                
+                  1
+                  Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set)
+                  #1
+                
+              
+            
+            
+              TOP
+              Timeout Counter
+              4
+              7
+              read-write
+              
+                
+                  1111
+                  Setting prohibited
+                  #1111
+                
+                
+                  others
+                  SDHI clock x 2^(TOP+13)
+                  true
+                
+              
+            
+            
+              CTOP
+              Card Detect Time Counter
+              0
+              3
+              read-write
+              
+                
+                  1111
+                  Setting prohibited
+                  #1111
+                
+                
+                  others
+                  IMCLK x 2^(CTOP+10)
+                  true
+                
+              
+            
+          
+        
+        
+          SD_ERR_STS1
+          SD Error Status Register 1
+          0x058
+          32
+          read-only
+          0x00002000
+          0xFFFFFFFF
+          
+            
+              CRCTK
+              CRC Status TokenStore the CRC status token value (normal value is 010b)
+              12
+              14
+              read-only
+            
+            
+              CRCTKE
+               CRC Status Token Error
+              11
+              11
+              read-only
+              
+                
+                  0
+                  An error has not occured in the CRC status.
+                  #0
+                
+                
+                  1
+                  An error has occured in the CRC status.
+                  #1
+                
+              
+            
+            
+              RDCRCE
+               Read Data CRC Error
+              10
+              10
+              read-only
+              
+                
+                  0
+                  CRC error has detected in read data
+                  #0
+                
+                
+                  1
+                  CRC error has not detected in read data
+                  #1
+                
+              
+            
+            
+              RSPCRCE1
+               Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0.
+              9
+              9
+              read-only
+              
+                
+                  0
+                  CRC error has not occured.
+                  #0
+                
+                
+                  1
+                  CRC error has occured in the response to a command issued within a command sequence.
+                  #1
+                
+              
+            
+            
+              RSPCRCE0
+               Response CRC Error 0NOTE: other than a response to a command issued within a command sequence
+              8
+              8
+              read-only
+              
+                
+                  0
+                  A CRC error has not occur in a response
+                  #0
+                
+                
+                  1
+                  A CRC error has occured in a response
+                  #1
+                
+              
+            
+            
+              CRCLENE
+               CRC Status Token Length Error
+              5
+              5
+              read-only
+              
+                
+                  0
+                  An error has not occured in the CRC status length.
+                  #0
+                
+                
+                  1
+                  An error has occured in the CRC status length (and the end bit has not been detected)
+                  #1
+                
+              
+            
+            
+              RDLENE
+               Read Data Length Error
+              4
+              4
+              read-only
+              
+                
+                  0
+                  An error has occurred not in the read data length.
+                  #0
+                
+                
+                  1
+                  An error has occured in the read data length (and the end bit has not been detected among the valid bits).
+                  #1
+                
+              
+            
+            
+              RSPLENE1
+               Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0.
+              3
+              3
+              read-only
+              
+                
+                  0
+                  An error has not occurred in the response length to a command issued within a command sequence.
+                  #0
+                
+                
+                  1
+                  An error has occured in the response length to a command issued within a command sequence.
+                  #1
+                
+              
+            
+            
+              RSPLENE0
+               Response Length Error 0NOTE: other than a response to a command issued within a command sequence
+              2
+              2
+              read-only
+              
+                
+                  0
+                  An error has not occured in the response length
+                  #0
+                
+                
+                  1
+                  An error has occured in the response length
+                  #1
+                
+              
+            
+            
+              CMDE1
+              Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0.
+              1
+              1
+              read-only
+              
+                
+                  0
+                  An error has not occurs in the command index of the response to a command issued within a command sequence.
+                  #0
+                
+                
+                  1
+                  An error has occured in the command index of the response to a command issued within a command sequence.
+                  #1
+                
+              
+            
+            
+              CMDE0
+              Command Error 0NOTE: other than a response to a command issued within a command sequence
+              0
+              0
+              read-only
+              
+                
+                  0
+                  An error has not occured in the command index of a response.
+                  #0
+                
+                
+                  1
+                  An error has occured in the command index of a response.
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_ERR_STS2
+          SD Error Status Register 2
+          0x05C
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              CRCBSYTO
+              CRC Status Token Busy Timeout
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Not timeout
+                  #0
+                
+                
+                  1
+                  The busy state continues for longer than N-cycle after the CRC status
+                  #1
+                
+              
+            
+            
+              CRCTO
+              CRC Status Token Timeout
+              5
+              5
+              read-only
+              
+                
+                  0
+                  Not timeout
+                  #0
+                
+                
+                  1
+                  The CRC status is not received though a longer time than N-cycle has elapsed after data writing.
+                  #1
+                
+              
+            
+            
+              RDTO
+              Read Data Timeout 
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Not timeout
+                  #0
+                
+                
+                  1
+                  The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state.
+                  #1
+                
+              
+            
+            
+              BSYTO1
+               Busy Timeout 1
+              3
+              3
+              read-only
+              
+                
+                  0
+                  Not timeout.
+                  #0
+                
+                
+                  1
+                  The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0.
+                  #1
+                
+              
+            
+            
+              BSYTO0
+               Busy Timeout 0
+              2
+              2
+              read-only
+              
+                
+                  0
+                  Not timeout.
+                  #0
+                
+                
+                  1
+                  The busy state for longer than N-cycle continues after R1b response.
+                  #1
+                
+              
+            
+            
+              RSPTO1
+              Response Timeout 1 
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Not timeout.
+                  #0
+                
+                
+                  1
+                  The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0.
+                  #1
+                
+              
+            
+            
+              RSPTO0
+              Response Timeout 0
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Not timeout.
+                  #0
+                
+                
+                  1
+                  The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed.
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_BUF0
+          SD Buffer Register
+          0x060
+          32
+          read-write
+          0x00000000
+          0x00000000
+          
+            
+              SD_BUF
+              SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data.  
+              0
+              31
+              read-write
+            
+          
+        
+        
+          SDIO_MODE
+          SDIO Mode Control Register
+          0x068
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              C52PUB
+              SDIO None AbortNOTE: See manual 
+              9
+              9
+              read-write
+            
+            
+              IOABT
+              SDIO AbortNOTE: See manual
+              8
+              8
+              read-write
+            
+            
+              RWREQ
+              Read Wait Request
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Allow SD/MMC to exit read wait state
+                  #0
+                
+                
+                  1
+                  Request for SD/MMC to enter read wait state.
+                  #1
+                
+              
+            
+            
+              INTEN
+               SDIO Mode
+              0
+              0
+              read-write
+              
+                
+                  1
+                  Enables the SD host interface to receive SDIO interrupt from the SDIO card
+                  #1
+                
+                
+                  0
+                  Disables the SD host interface to receive SDIO interrupt from the SDIO card
+                  #0
+                
+              
+            
+          
+        
+        
+          SDIO_INFO1
+          SDIO Interrupt Flag Register 1
+          0x06C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFF9
+          
+            
+              EXWT
+              EXWT Status FlagNOTE: See manual
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+            
+            
+              EXPUB52
+              EXPUB52 Status FlagNOTE: See manual
+              14
+              14
+              read-write
+              zeroToClear
+              modify
+            
+            
+              IOIRQ
+              SDIO Interrupt Status
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SDIO interrupt not accepted
+                  #0
+                
+                
+                  1
+                  SDIO interrupt accepted
+                  #1
+                
+              
+            
+          
+        
+        
+          SDIO_INFO1_MASK
+          SDIO_INFO1 Interrupt Mask Register
+          0x070
+          32
+          read-write
+          0x0000C007
+          0xFFFFFFFF
+          
+            
+              EXWTM
+              EXWT Interrupt Request Mask Control
+              15
+              15
+              read-write
+              
+                
+                  0
+                  EXWT interrupt request not masked
+                  #0
+                
+                
+                  1
+                  EXWT interrupt request masked
+                  #1
+                
+              
+            
+            
+              EXPUB52M
+              EXPUB52 Interrupt Request Mask Control
+              14
+              14
+              read-write
+              
+                
+                  0
+                  EXPUB52 interrupt request not masked
+                  #0
+                
+                
+                  1
+                  EXPUB52 interrupt request masked
+                  #1
+                
+              
+            
+            
+              IOIRQM
+              IOIRQ Interrupt Mask Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  IOIRQ interrupt not masked
+                  #0
+                
+                
+                  1
+                  IOIRQ interrupt masked
+                  #1
+                
+              
+            
+          
+        
+        
+          SD_DMAEN
+          DMA Mode Enable Register
+          0x1B0
+          32
+          read-write
+          0x00001010
+          0xFFFFFFFF
+          
+            
+              DMAEN
+              SD_BUF Read/Write DMA Transfer
+              1
+              1
+              read-write
+              
+                
+                  0
+                  The SD_BUF read/write DMA transfer is disabled.
+                  #0
+                
+                
+                  1
+                  The SD_BUF read/write DMA transfer is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          SOFT_RST
+          Software Reset Register
+          0x1C0
+          32
+          read-write
+          0x00000007
+          0xFFFFFFFF
+          
+            
+              SDRST
+              Software Reset of SD I/F Unit
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Reset
+                  #0
+                
+                
+                  1
+                  Reset released
+                  #1
+                
+              
+            
+          
+        
+        
+          SDIF_MODE
+          SD Interface Mode Setting Register
+          0x1CC
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              NOCHKCR
+              CRC Check Mask (for MMC test commands)
+              8
+              8
+              read-write
+              
+                
+                  0
+                  CRC check is valid
+                  #0
+                
+                
+                  1
+                  CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write)
+                  #1
+                
+              
+            
+          
+        
+        
+          EXT_SWAP
+          Swap Control Register
+          0x1E0
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              BRSWP
+              SD_BUF0 Swap Read
+              7
+              7
+              read-write
+              
+                
+                  0
+                  The current data are read without swapping.
+                  #0
+                
+                
+                  1
+                  Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds.
+                  #1
+                
+              
+            
+            
+              BWSWP
+              SD_BUF0 Swap Write
+              6
+              6
+              read-write
+              
+                
+                  0
+                  The current data are written without swapping.
+                  #0
+                
+                
+                  1
+                  Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_SDHI1
+      0x40062400
+    
+    
+      R_SLCDC
+      Segment LCD Controller/Driver
+      0x40082000
+      
+        0x00
+        4
+        registers
+      
+      
+        0x100
+        38
+        registers
+      
+      
+        
+          LCDM0
+          LCD Mode Register 0 
+          0x000
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MDSET
+              LCD drive voltage generator selection
+              6
+              7
+              read-write
+              
+                
+                  00
+                  External resistance division method
+                  #00
+                
+                
+                  01
+                  Internal voltage boosting method
+                  #01
+                
+                
+                  10
+                  Capacitor split method
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+            
+              LWAVE
+              LCD display waveform selection
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Waveform A
+                  #0
+                
+                
+                  1
+                  Waveform B
+                  #1
+                
+              
+            
+            
+              LDTY
+              Time Slice of LCD Display Select
+              2
+              4
+              read-write
+              
+                
+                  000
+                  Static
+                  #000
+                
+                
+                  001
+                  2-time slice
+                  #001
+                
+                
+                  010
+                  3-time slice
+                  #010
+                
+                
+                  011
+                  4-time slice
+                  #011
+                
+                
+                  101
+                  8-time slice
+                  #101
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              LBAS
+              LCD Display Bias Method Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  1/2 bias method
+                  #00
+                
+                
+                  01
+                  1/3 bias method
+                  #01
+                
+                
+                  10
+                  1/4 bias method
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          LCDM1
+          LCD Mode Register 1 
+          0x001
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LCDON
+              LCD Display Enable/Disable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1)
+                  #0
+                
+                
+                  1
+                  Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1)
+                  #1
+                
+              
+            
+            
+              SCOC
+              LCD Display Enable/Disable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1)
+                  #0
+                
+                
+                  1
+                  Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1)
+                  #1
+                
+              
+            
+            
+              VLCON
+              Voltage boost circuit or capacitor split circuit operation enable/disable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Stops voltage boost circuit or capacitor split circuit operation
+                  #0
+                
+                
+                  1
+                  Enables voltage boost circuit or capacitor split circuit operation
+                  #1
+                
+              
+            
+            
+              BLON
+              Display data area control
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1)
+                  #0
+                
+                
+                  1
+                  Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))
+                  #1
+                
+              
+            
+            
+              LCDSEL
+              Display data area control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1)
+                  #0
+                
+                
+                  1
+                  Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1)
+                  #1
+                
+              
+            
+            
+              Reserved
+              These bits are read as 00. The write value should be 00.
+              1
+              2
+              read-write
+            
+            
+              LCDVLM
+              Voltage Boosting Pin Initial Value Switching Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Set when VDD >= 2.7 V
+                  #0
+                
+                
+                  1
+                  Set when VDD <= 4.2 V 
+                  #1
+                
+              
+            
+          
+        
+        
+          LCDC0
+          LCD Clock Control Register 0 
+          0x002
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LCDC
+              LCD clock (LCDCL)
+              0
+              5
+              read-write
+              
+                
+                  000001
+                  (Sub clock)/22  or  (LOCO clock)/22
+                  #000001
+                
+                
+                  000010
+                  (Sub clock)/23  or  (LOCO clock)/23
+                  #000010
+                
+                
+                  000011
+                  (Sub clock)/24  or  (LOCO clock)/24 
+                  #000011
+                
+                
+                  000100
+                  (Sub clock)/25  or  (LOCO clock)/25 
+                  #000100
+                
+                
+                  000101
+                  (Sub clock)/26  or  (LOCO clock)/26 
+                  #000101
+                
+                
+                  000110
+                  (Sub clock)/27  or  (LOCO clock)/27
+                  #000110
+                
+                
+                  000111
+                  (Sub clock)/28  or  (LOCO clock)/28
+                  #000111
+                
+                
+                  001000
+                  (Sub clock)/29  or  (LOCO clock)/29
+                  #001000
+                
+                
+                  001001
+                  (Sub clock)/210 or  (LOCO clock)/210
+                  #001001
+                
+                
+                  010001
+                  (Main clock)/28 or  (HOCO clock)/28 
+                  #010001
+                
+                
+                  010010
+                  (Main clock)/29 or  (HOCO clock)/29
+                  #010010
+                
+                
+                  010011
+                  (Main clock)/210 or  (HOCO clock)/210
+                  #010011
+                
+                
+                  010100
+                  (Main clock)/211 or  (HOCO clock)/211
+                  #010100
+                
+                
+                  010101
+                  (Main clock)/212 or  (HOCO clock)/212
+                  #010101
+                
+                
+                  010110
+                  (Main clock)/213 or  (HOCO clock)/213 
+                  #010110
+                
+                
+                  010111
+                  (Main clock)/214 or  (HOCO clock)/214
+                  #010111
+                
+                
+                  011000
+                  (Main clock)/215 or  (HOCO clock)/215
+                  #011000
+                
+                
+                  011001
+                  (Main clock)/216 or  (HOCO clock)/216
+                  #011001
+                
+                
+                  011010
+                  (Main clock)/217 or  (HOCO clock)/217
+                  #011010
+                
+                
+                  011011
+                  (Main clock)/218 or  (HOCO clock)/218
+                  #011011
+                
+                
+                  101011
+                  (Main clock)/219 or  (HOCO clock)/219
+                  #101011
+                
+                
+                  others
+                  Other than above Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          VLCD
+          LCD Boost Level Control Register 
+          0x003
+          8
+          read-write
+          0x04
+          0xFF
+          
+            
+              VLCD
+              Reference Voltage(Contrast Adjustment) Select
+              0
+              4
+              read-write
+              
+                
+                  00100
+                  Reference voltageselection(contrast adjustment):  1.00 V (default)  VL4 voltage:  3.00 V(1/3 bias method)/4.00 V(1/4 bias method)
+                  #00100
+                
+                
+                  00101
+                  Reference voltageselection(contrast adjustment):  1.05 V  VL4 voltage:  3.15 V(1/3 bias method)/4.20 V(1/4 bias method)
+                  #00101
+                
+                
+                  00110
+                  Reference voltageselection(contrast adjustment):  1.10 V  VL4 voltage:  3.30 V(1/3 bias method)/4.40 V(1/4 bias method)
+                  #00110
+                
+                
+                  00111
+                  Reference voltageselection(contrast adjustment):  1.15 V   VL4 voltage:  3.45 V(1/3 bias method)/4.60 V(1/4 bias method)
+                  #00111
+                
+                
+                  01000
+                  Reference voltageselection(contrast adjustment):  1.20 V  VL4 voltage:  3.60 V(1/3 bias method)/4.80 V(1/4 bias method)
+                  #01000
+                
+                
+                  01001
+                  Reference voltageselection(contrast adjustment):  1.25 V  VL4 voltage:  3.75 V(1/3 bias method)/5.00 V(1/4 bias method)
+                  #01001
+                
+                
+                  01010
+                  Reference voltageselection(contrast adjustment):  1.30 V  VL4 voltage:  3.90 V(1/3 bias method)/5.20 V(1/4 bias method)
+                  #01010
+                
+                
+                  01011
+                  Reference voltageselection(contrast adjustment):  1.35 V  VL4 voltage:  4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #01011
+                
+                
+                  01100
+                  Reference voltageselection(contrast adjustment):  1.40 V  VL4 voltage:  4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #01100
+                
+                
+                  01101
+                  Reference voltageselection(contrast adjustment):  1.45 V  VL4 voltage:  4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #01101
+                
+                
+                  01110
+                  Reference voltageselection(contrast adjustment):  1.50 V  VL4 voltage:  4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #01110
+                
+                
+                  01111
+                  Reference voltageselection(contrast adjustment):  1.55 V  VL4 voltage:  4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #01111
+                
+                
+                  10000
+                  Reference voltageselection(contrast adjustment):  1.60 V   VL4 voltage:  4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #10000
+                
+                
+                  10001
+                  Reference voltageselection(contrast adjustment):  1.65 V   VL4 voltage:  4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #10001
+                
+                
+                  10010
+                  Reference voltageselection(contrast adjustment):  1.70 V   VL4 voltage:  5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #10010
+                
+                
+                  10011
+                  Reference voltageselection(contrast adjustment):  1.75 V   VL4 voltage:  5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method)
+                  #10011
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          38
+          0x1
+          SEG[%s]
+          LCD Display Data Array
+          0x100
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              A
+              A-Pattern Area
+              0
+              3
+              read-write
+            
+            
+              B
+              B-Pattern Area
+              4
+              7
+              read-write
+            
+          
+        
+      
+    
+    
+      R_SPI0
+      Serial Peripheral Interface
+      0x40072000
+      
+        0x00000000
+        0x008
+        registers
+      
+      
+        0x0000000A
+        0x008
+        registers
+      
+      
+        
+          SPCR
+          SPI Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SPRIE
+              SPI Receive Buffer Full Interrupt Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disables the generation of SPI receive buffer full interrupt requests
+                  #0
+                
+                
+                  1
+                  Enables the generation of SPI receive buffer full interrupt requests
+                  #1
+                
+              
+            
+            
+              SPE
+              SPI Function Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disables the SPI function
+                  #0
+                
+                
+                  1
+                  Enables the SPI function
+                  #1
+                
+              
+            
+            
+              SPTIE
+              Transmit Buffer Empty Interrupt Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disables the generation of transmit buffer empty interrupt requests
+                  #0
+                
+                
+                  1
+                  Enables the generation of transmit buffer empty interrupt requests
+                  #1
+                
+              
+            
+            
+              SPEIE
+              SPI Error Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disables the generation of SPI error interrupt requests
+                  #0
+                
+                
+                  1
+                  Enables the generation of SPI error interrupt requests
+                  #1
+                
+              
+            
+            
+              MSTR
+              SPI Master/Slave Mode Select
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Slave mode
+                  #0
+                
+                
+                  1
+                  Master mode
+                  #1
+                
+              
+            
+            
+              MODFEN
+              Mode Fault Error Detection Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disables the detection of mode fault error
+                  #0
+                
+                
+                  1
+                  Enables the detection of mode fault error
+                  #1
+                
+              
+            
+            
+              TXMD
+              Communications Operating Mode Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Full-duplex synchronous serial communications
+                  #0
+                
+                
+                  1
+                  Serial communications consisting of only transmit operations
+                  #1
+                
+              
+            
+            
+              SPMS
+              SPI Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  SPI operation (4-wire method)
+                  #0
+                
+                
+                  1
+                  Clock synchronous operation (3-wire method)
+                  #1
+                
+              
+            
+          
+        
+        
+          SSLP
+          SPI Slave Select Polarity Register
+          0x01
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SSL3P
+              SSL3 Signal Polarity Setting
+              3
+              3
+              read-write
+              
+                
+                  0
+                  SSL3 signal is active low
+                  #0
+                
+                
+                  1
+                  SSL3 signal is active high
+                  #1
+                
+              
+            
+            
+              SSL2P
+              SSL2 Signal Polarity Setting
+              2
+              2
+              read-write
+              
+                
+                  0
+                  SSL2 signal is active low
+                  #0
+                
+                
+                  1
+                  SSL2 signal is active high
+                  #1
+                
+              
+            
+            
+              SSL1P
+              SSL1 Signal Polarity Setting
+              1
+              1
+              read-write
+              
+                
+                  0
+                  SSL1 signal is active low
+                  #0
+                
+                
+                  1
+                  SSL1 signal is active high
+                  #1
+                
+              
+            
+            
+              SSL0P
+              SSL0 Signal Polarity Setting
+              0
+              0
+              read-write
+              
+                
+                  0
+                  SSL0 signal is active low
+                  #0
+                
+                
+                  1
+                  SSL0 signal is active high
+                  #1
+                
+              
+            
+          
+        
+        
+          SPPCR
+          SPI Pin Control Register
+          0x02
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MOIFE
+              MOSI Idle Value Fixing Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  MOSI output value equals final data from previous transfer
+                  #0
+                
+                
+                  1
+                  MOSI output value equals the value set in the MOIFV bit
+                  #1
+                
+              
+            
+            
+              MOIFV
+              MOSI Idle Fixed Value
+              4
+              4
+              read-write
+              
+                
+                  0
+                  The level output on the MOSIn pin during MOSI idling corresponds to low.
+                  #0
+                
+                
+                  1
+                  The level output on the MOSIn pin during MOSI idling corresponds to high.
+                  #1
+                
+              
+            
+            
+              SPLP2
+              SPI Loopback 2
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Loopback mode (data is not inverted for transmission)
+                  #1
+                
+              
+            
+            
+              SPLP
+              SPI Loopback
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Loopback mode (data is inverted for transmission)
+                  #1
+                
+              
+            
+          
+        
+        
+          SPSR
+          SPI Status Register
+          0x03
+          8
+          read-write
+          0x20
+          0xFF
+          
+            
+              SPRF
+              SPI Receive Buffer Full Flag
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No valid data in SPDR
+                  #0
+                
+                
+                  1
+                  Valid data found in SPDR
+                  #1
+                
+              
+            
+            
+              SPTEF
+              SPI Transmit Buffer Empty Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Data found in the transmit buffer
+                  #0
+                
+                
+                  1
+                  No data in the transmit buffer
+                  #1
+                
+              
+            
+            
+              UDRF
+              Underrun Error Flag(When MODF is 0,  This bit is invalid.)
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  A mode fault error occurs (MODF=1)
+                  #0
+                
+                
+                  1
+                  An underrun error occurs (MODF=1)
+                  #1
+                
+              
+            
+            
+              PERF
+              Parity Error Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No parity error occurs
+                  #0
+                
+                
+                  1
+                  A parity error occurs
+                  #1
+                
+              
+            
+            
+              MODF
+              Mode Fault Error Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Neither mode fault error nor underrun error occurs
+                  #0
+                
+                
+                  1
+                  A mode fault error or an underrun error occurs.
+                  #1
+                
+              
+            
+            
+              IDLNF
+              SPI Idle Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  SPI is in the idle state
+                  #0
+                
+                
+                  1
+                  SPI is in the transfer state
+                  #1
+                
+              
+            
+            
+              OVRF
+              Overrun Error Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No overrun error occurs
+                  #0
+                
+                
+                  1
+                  An overrun error occurs
+                  #1
+                
+              
+            
+          
+        
+        
+          SPDR
+          SPI Data Register
+          0x04
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+        
+        
+          SPDR_HA
+          SPI Data Register ( halfword access )
+          SPDR
+          0x04
+          16
+          read-write
+          0x0000
+          0xFFFF
+        
+        
+          SPDR_BY
+          SPI Data Register ( byte access )
+          SPDR
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+        
+        
+          SPSCR
+          SPI Sequence Control Register
+          0x08
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              Reserved
+              These bits are read as 00000. The write value should be 00000.
+              3
+              7
+              read-write
+            
+            
+              SPSLN
+              RSPI Sequence Length Specification
+The order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0.
+              0
+              2
+              read-write
+              
+                
+                  000
+                  Length 1    SPDMDx   x = 0->0->...
+                  #000
+                
+                
+                  001
+                  Length 2    SPDMDx   x = 0->1->0->...
+                  #001
+                
+                
+                  010
+                  Length 3    SPDMDx   x = 0->1->2->0->...
+                  #010
+                
+                
+                  011
+                  Length 4    SPDMDx   x = 0->1->2->3->0->...
+                  #011
+                
+                
+                  100
+                  Length 5    SPDMDx   x = 0->1->2->3->4->0->...
+                  #100
+                
+                
+                  101
+                  Length 6    SPDMDx   x = 0->1->2->3->4->5->0->...
+                  #101
+                
+                
+                  110
+                  Length 7    SPDMDx   x = 0->1->2->3->4->5->6->0->...
+                  #110
+                
+                
+                  111
+                  Length 8    SPDMDx   x = 0->1->2->3->4->5->6->7->0->...
+                  #111
+                
+              
+            
+          
+        
+        
+          SPBR
+          SPI Bit Rate Register
+          0x0A
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              SPR
+              SPBR sets the bit rate in master mode.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SPDCR
+          SPI Data Control Register
+          0x0B
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SPBYT
+              SPI Byte Access Specification
+              6
+              6
+              read-write
+              
+                
+                  0
+                  SPDR is accessed in halfword or word (SPLW is valid)
+                  #0
+                
+                
+                  1
+                  SPDR is accessed in byte (SPLW is invalid).
+                  #1
+                
+              
+            
+            
+              SPLW
+              SPI Word Access/Halfword Access Specification
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Set SPDR_HA to valid for halfword access
+                  #0
+                
+                
+                  1
+                  Set SPDR to valid for word access.
+                  #1
+                
+              
+            
+            
+              SPRDTD
+              SPI Receive/Transmit Data Selection
+              4
+              4
+              read-write
+              
+                
+                  0
+                  SPDR values are read from the receive buffer
+                  #0
+                
+                
+                  1
+                  SPDR values are read from the transmit buffer (but only if the transmit buffer is empty)
+                  #1
+                
+              
+            
+            
+              SPFC
+              Number of Frames Specification
+              0
+              1
+              read-write
+              
+                
+                  00
+                  1 frame
+                  #00
+                
+                
+                  01
+                  2 frames
+                  #01
+                
+                
+                  10
+                  3 frames
+                  #10
+                
+                
+                  11
+                  4 frames.
+                  #11
+                
+              
+            
+          
+        
+        
+          SPCKD
+          SPI Clock Delay Register
+          0x0C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SCKDL
+              RSPCK Delay Setting
+              0
+              2
+              read-write
+              
+                
+                  000
+                  1 RSPCK
+                  #000
+                
+                
+                  001
+                  2 RSPCK
+                  #001
+                
+                
+                  010
+                  3 RSPCK
+                  #010
+                
+                
+                  011
+                  4 RSPCK
+                  #011
+                
+                
+                  100
+                  5 RSPCK
+                  #100
+                
+                
+                  101
+                  6 RSPCK
+                  #101
+                
+                
+                  110
+                  7 RSPCK
+                  #110
+                
+                
+                  111
+                  8 RSPCK
+                  #111
+                
+              
+            
+          
+        
+        
+          SSLND
+          SPI Slave Select Negation Delay Register
+          0x0D
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SLNDL
+              SSL Negation Delay Setting
+              0
+              2
+              read-write
+              
+                
+                  000
+                  1 RSPCK
+                  #000
+                
+                
+                  001
+                  2 RSPCK
+                  #001
+                
+                
+                  010
+                  3 RSPCK
+                  #010
+                
+                
+                  011
+                  4 RSPCK
+                  #011
+                
+                
+                  100
+                  5 RSPCK
+                  #100
+                
+                
+                  101
+                  6 RSPCK
+                  #101
+                
+                
+                  110
+                  7 RSPCK
+                  #110
+                
+                
+                  111
+                  8 RSPCK
+                  #111
+                
+              
+            
+          
+        
+        
+          SPND
+          SPI Next-Access Delay Register
+          0x0E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SPNDL
+              SPI Next-Access Delay Setting
+              0
+              2
+              read-write
+              
+                
+                  000
+                  1 RSPCK + 2 PCLK
+                  #000
+                
+                
+                  001
+                  2 RSPCK + 2 PCLK
+                  #001
+                
+                
+                  010
+                  3 RSPCK + 2 PCLK
+                  #010
+                
+                
+                  011
+                  4 RSPCK + 2 PCLK
+                  #011
+                
+                
+                  100
+                  5 RSPCK + 2 PCLK
+                  #100
+                
+                
+                  101
+                  6 RSPCK + 2 PCLK
+                  #101
+                
+                
+                  110
+                  7 RSPCK + 2 PCLK
+                  #110
+                
+                
+                  111
+                  8 RSPCK + 2 PCLK
+                  #111
+                
+              
+            
+          
+        
+        
+          SPCR2
+          SPI Control Register 2
+          0x0F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SCKASE
+              RSPCK Auto-Stop Function Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disables the RSPCK auto-stop function
+                  #0
+                
+                
+                  1
+                  Enables the RSPCK auto-stop function
+                  #1
+                
+              
+            
+            
+              PTE
+              Parity Self-Testing
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disables the self-diagnosis function of the parity circuit
+                  #0
+                
+                
+                  1
+                  Enables the self-diagnosis function of the parity circuit
+                  #1
+                
+              
+            
+            
+              SPIIE
+              SPI Idle Interrupt Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disables the generation of idle interrupt requests
+                  #0
+                
+                
+                  1
+                  Enables the generation of idle interrupt requests
+                  #1
+                
+              
+            
+            
+              SPOE
+              Parity Mode
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Selects even parity for use in transmission and reception
+                  #0
+                
+                
+                  1
+                  Selects odd parity for use in transmission and reception
+                  #1
+                
+              
+            
+            
+              SPPE
+              Parity Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Does not add the parity bit to transmit data and does not check the parity bit of receive data
+                  #0
+                
+                
+                  1
+                  Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1)
+                  #1
+                
+              
+            
+          
+        
+        
+          8
+          0x02
+          SPCMD[%s]
+          SPI Command Register %s
+          0x10
+          16
+          read-write
+          0x070D
+          0xFFFF
+          
+            
+              SCKDEN
+              RSPCK Delay Setting Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  An RSPCK delay of 1 RSPCK
+                  #0
+                
+                
+                  1
+                  An RSPCK delay is equal to the setting of the SPI clock delay register (SPCKD)
+                  #1
+                
+              
+            
+            
+              SLNDEN
+              SSL Negation Delay Setting Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  An SSL negation delay of 1 RSPCK
+                  #0
+                
+                
+                  1
+                  An SSL negation delay is equal to the setting of the SPI slave select negation delay register (SSLND)
+                  #1
+                
+              
+            
+            
+              SPNDEN
+              SPI Next-Access Delay Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  A next-access delay of 1 RSPCK + 2 PCLK
+                  #0
+                
+                
+                  1
+                  A next-access delay is equal to the setting of the SPI next-access delay register (SPND)
+                  #1
+                
+              
+            
+            
+              LSBF
+              SPI LSB First
+              12
+              12
+              read-write
+              
+                
+                  0
+                  MSB first
+                  #0
+                
+                
+                  1
+                  LSB first
+                  #1
+                
+              
+            
+            
+              SPB
+              SPI Data Length Setting
+              8
+              11
+              read-write
+              
+                
+                  0100
+                  8 bits
+                  #0100
+                
+                
+                  0101
+                  8 bits
+                  #0101
+                
+                
+                  0110
+                  8 bits
+                  #0110
+                
+                
+                  0111
+                  8 bits
+                  #0111
+                
+                
+                  1000
+                  9 bits
+                  #1000
+                
+                
+                  1001
+                  10 bits
+                  #1001
+                
+                
+                  1010
+                  11 bits
+                  #1010
+                
+                
+                  1011
+                  12 bits
+                  #1011
+                
+                
+                  1100
+                  13 bits
+                  #1100
+                
+                
+                  1101
+                  14 bits
+                  #1101
+                
+                
+                  1110
+                  15 bits
+                  #1110
+                
+                
+                  1111
+                  16 bits
+                  #1111
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              SSLKP
+              SSL Signal Level Keeping
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Negates all SSL signals upon completion of transfer
+                  #0
+                
+                
+                  1
+                  Keeps the SSL signal level from the end of transfer until the beginning of the next access
+                  #1
+                
+              
+            
+            
+              SSLA
+              SSL Signal Assertion Setting
+              4
+              6
+              read-write
+              
+                
+                  000
+                  SSL0
+                  #000
+                
+                
+                  001
+                  SSL1
+                  #001
+                
+                
+                  010
+                  SSL2
+                  #010
+                
+                
+                  011
+                  SSL3
+                  #011
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              BRDV
+              Bit Rate Division Setting
+              2
+              3
+              read-write
+              
+                
+                  00
+                  These bits select the base bit rate
+                  #00
+                
+                
+                  01
+                  These bits select the base bit rate divided by 2
+                  #01
+                
+                
+                  10
+                  These bits select the base bit rate divided by 4
+                  #10
+                
+                
+                  11
+                  These bits select the base bit rate divided by 8
+                  #11
+                
+              
+            
+            
+              CPOL
+              RSPCK Polarity Setting
+              1
+              1
+              read-write
+              
+                
+                  0
+                  RSPCK is low when idle
+                  #0
+                
+                
+                  1
+                  RSPCK is high when idle
+                  #1
+                
+              
+            
+            
+              CPHA
+              RSPCK Phase Setting
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Data sampling on odd edge, data variation on even edge
+                  #0
+                
+                
+                  1
+                  Data variation on odd edge, data sampling on even edge
+                  #1
+                
+              
+            
+          
+        
+        
+          SPDCR2
+          SPI Data Control Register 2
+          0x20
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BYSW
+              Byte Swap Operating Mode  Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Byte Swap Operating Mode disabled
+                  #0
+                
+                
+                  1
+                  Byte Swap Operating Mode enabled
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_SPI1
+      0x40072100
+    
+    
+      R_SRAM
+      SRAM
+      0x40002000
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000004
+        0x01
+        registers
+      
+      
+        0x00000008
+        0x01
+        registers
+      
+      
+        0x000000C0
+        0x005
+        registers
+      
+      
+        0x000000D0
+        0x01
+        registers
+      
+      
+        0x000000D4
+        0x01
+        registers
+      
+      
+        0x000000D8
+        0x01
+        registers
+      
+      
+        
+          PARIOAD
+          SRAM Parity Error Operation After Detection Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OAD
+              Operation after Detection
+              0
+              0
+              read-write
+              
+                
+                  1
+                  Reset
+                  #1
+                
+                
+                  0
+                  Non maskable interrupt.
+                  #0
+                
+              
+            
+          
+        
+        
+          SRAMPRCR
+          SRAM Protection Register
+          0x04
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              KW
+              Write Key Code
+              1
+              7
+              write-only
+              
+                
+                  1111000
+                  Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b.
+                  #1111000
+                
+                
+                  others
+                  Writing to the RAMPRCR bit is invalid.
+                  true
+                
+              
+            
+            
+              SRAMPRCR
+              Register Write Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable writes to protected registers
+                  #0
+                
+                
+                  1
+                  Enable writes to protected registers.
+                  #1
+                
+              
+            
+          
+        
+        
+          SRAMWTSC
+          RAM Wait State Control Register
+          0x08
+          8
+          read-write
+          0x0E
+          0xFF
+          
+            
+              SRAMHSWTEN
+              SRAMHS Wait Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Not add wait state in read access cycle to SRAMHS
+                  #0
+                
+                
+                  1
+                  Add wait state in read access cycle to SRAMHS
+                  #1
+                
+              
+            
+            
+              SRAM1WTEN
+              SRAM1 Wait Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Not add wait state in read access cycle to SRAM1
+                  #0
+                
+                
+                  1
+                  Add wait state in read access cycle to SRAM1
+                  #1
+                
+              
+            
+            
+              SRAM0WTEN
+              SRAM0 Wait Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Not add wait state in read access cycle to SRAM0
+                  #0
+                
+                
+                  1
+                  Add wait state in read access cycle to SRAM0
+                  #1
+                
+              
+            
+            
+              ECCRAMRDWTEN
+              ECCRAM Read wait enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Not add wait state in read access cycle to SRAM0 (ECC area)
+                  #0
+                
+                
+                  1
+                  Add wait state in read access cycle to SRAM0 (ECC area)
+                  #1
+                
+              
+            
+            
+              ECCRAMWRWTEN
+              ECCRAM Write Wait Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Not add wait state in write access cycle to SRAM0 (ECC area)
+                  #0
+                
+                
+                  1
+                  Add wait state in write access cycle to SRAM0 (ECC area)
+                  #1
+                
+              
+            
+          
+        
+        
+          ECCMODE
+          ECC Operating Mode Control Register
+          0xC0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ECCMOD
+              ECC Operating Mode Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Disable ECC function
+                  #00
+                
+                
+                  01
+                  Setting prohibited
+                  #01
+                
+                
+                  10
+                  Enable ECC function without error checking
+                  #10
+                
+                
+                  11
+                  Enable ECC function with error checking
+                  #11
+                
+              
+            
+          
+        
+        
+          ECC2STS
+          ECC 2-Bit Error Status Register
+          0xC1
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ECC2ERR
+              ECC 2-Bit Error Status
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No 2-bit ECC error occurred
+                  #0
+                
+                
+                  1
+                  2-bit ECC error occurred.
+                  #1
+                
+              
+            
+          
+        
+        
+          ECC1STSEN
+          ECC 1-Bit Error Information Update Enable Register
+          0xC2
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              E1STSEN
+              ECC 1-Bit Error Information Update Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disables updating of the 1-bit ECC error information.
+                  #0
+                
+                
+                  1
+                  Enables updating of the 1-bit ECC error information.
+                  #1
+                
+              
+            
+          
+        
+        
+          ECC1STS
+          ECC 1-Bit Error Status Register
+          0xC3
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              ECC1ERR
+              ECC 1-Bit Error Status
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No 1-bit ECC error occurred
+                  #0
+                
+                
+                  1
+                  1-bit ECC error occurred
+                  #1
+                
+              
+            
+          
+        
+        
+          ECCPRCR
+          ECC Protection Register
+          0xC4
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              KW
+              Write Key Code
+              1
+              7
+              write-only
+              
+                
+                  1111000
+                  Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b.
+                  #1111000
+                
+                
+                  others
+                  Writing to the ECCRAMPRCR bit is invalid.
+                  true
+                
+              
+            
+            
+              ECCPRCR
+              Register Write Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable writes to the protected registers
+                  #0
+                
+                
+                  1
+                  Enable writes to the protected registers
+                  #1
+                
+              
+            
+          
+        
+        
+          ECCPRCR2
+          ECC Protection Register 2
+          0xD0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              KW2
+              Write Key Code
+              1
+              7
+              write-only
+              
+                
+                  1111000
+                  These bits enable or disable writes to the ECCPRCR2 bit..
+                  #1111000
+                
+                
+                  others
+                  Writing to the ECCRAMPRCR2 bit is invalid.
+                  true
+                
+              
+            
+            
+              ECCPRCR2
+              Register Write Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable writes to the protected registers
+                  #0
+                
+                
+                  1
+                  Enable writes to the protected registers.
+                  #1
+                
+              
+            
+          
+        
+        
+          ECCETST
+          ECC Test Control Register
+          0xD4
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TSTBYP
+              ECC Bypass Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  ECC bypass disabled.
+                  #0
+                
+                
+                  1
+                  ECC bypass enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          ECCOAD
+          SRAM ECC Error Operation After Detection Register
+          0xD8
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OAD
+              Operation after Detection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Non-maskable interrupt
+                  #0
+                
+                
+                  1
+                  Reset
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_SRC
+      Sampling Rate Converter
+      0x40048000
+      
+        0x00000000
+        0x56C0
+        registers
+      
+      
+        0x00005FF0
+        0x010
+        registers
+      
+      
+        
+          5552
+          0x4
+          SRCFCTR[%s]
+          Filter Coefficient Table [%s]
+          0x00
+          32
+          read-write
+          0x00000000
+          0xFFC00000
+          
+            
+              SRCFCOE
+              Stores a filter coefficient value.
+              0
+              21
+              read-write
+            
+          
+        
+        
+          SRCID
+          Input Data Register
+          0x5FF0
+          32
+          write-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SRCID
+              SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0.
+              0
+              31
+              write-only
+            
+          
+        
+        
+          SRCOD
+          Output Data Register
+          0x5FF4
+          32
+          read-only
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SRCOD
+              SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again.
+              0
+              31
+              read-only
+            
+          
+        
+        
+          SRCIDCTRL
+          Input Data Control Register
+          0x5FF8
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              IED
+              Input Data Endian
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Endian formats 1 are the same between the CPU and input data.
+                  #0
+                
+                
+                  1
+                  Endian formats 1 are different between the CPU and input data.
+                  #1
+                
+              
+            
+            
+              IEN
+              Input FIFO Empty Interrupt Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Input FIFO empty interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Input FIFO empty interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              IFTRG
+              Input FIFO Data Triggering Number
+              0
+              1
+              read-write
+              
+                
+                  00
+                  0
+                  #00
+                
+                
+                  01
+                  2
+                  #01
+                
+                
+                  10
+                  4
+                  #10
+                
+                
+                  11
+                  6
+                  #11
+                
+              
+            
+          
+        
+        
+          SRCCTRL
+          Control Register
+          0x5FFC
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FICRAE
+              Filter Coefficient Table Access Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Reading/writing to filter coefficient table RAM is disabled.
+                  #0
+                
+                
+                  1
+                  Reading/writing to filter coefficient table RAM is enabled.
+                  #1
+                
+              
+            
+            
+              CEEN
+              Conversion End Interrupt Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Disables conversion end interrupt requests.
+                  #0
+                
+                
+                  1
+                  Enables conversion end interrupt requests.
+                  #1
+                
+              
+            
+            
+              SRCEN
+              Module Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Disables this module operation.
+                  #0
+                
+                
+                  1
+                  Enables this module operation.
+                  #1
+                
+              
+            
+            
+              UDEN
+              Output Data FIFO Underflow Interrupt Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Disables output data FIFO underflow interrupt requests.
+                  #0
+                
+                
+                  1
+                  Enables output data FIFO underflow interrupt requests.
+                  #1
+                
+              
+            
+            
+              OVEN
+              Output Data FIFO Overwrite Interrupt Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Output data FIFO overwrite interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Output data FIFO overwrite interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              FL
+              Internal Work Memory Flush
+              9
+              9
+              read-write
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing).
+                  #1
+                
+              
+            
+            
+              CL
+              Internal Work Memory Clear
+              8
+              8
+              read-write
+              
+                
+                  0
+                  no effect
+                  #0
+                
+                
+                  1
+                  Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator.
+                  #1
+                
+              
+            
+            
+              IFS
+              Input Sampling Rate
+              4
+              7
+              read-write
+              
+                
+                  0000
+                  8.0 kHz
+                  #0000
+                
+                
+                  0001
+                  11.025 kHz
+                  #0001
+                
+                
+                  0010
+                  12.0 kHz
+                  #0010
+                
+                
+                  0011
+                  Setting prohibited
+                  #0011
+                
+                
+                  0100
+                  16.0 kHz
+                  #0100
+                
+                
+                  0101
+                  22.05 kHz
+                  #0101
+                
+                
+                  0110
+                  24.0 kHz
+                  #0110
+                
+                
+                  0111
+                  Setting prohibited
+                  #0111
+                
+                
+                  1000
+                  32.0 kHz
+                  #1000
+                
+                
+                  1001
+                  44.1 kHz
+                  #1001
+                
+                
+                  1010
+                  48.0 kHz
+                  #1010
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+            
+              OFS
+              Output Sampling Rate
+              0
+              2
+              read-write
+              
+                
+                  000
+                  44.1 kHz
+                  #000
+                
+                
+                  001
+                  48.0 kHz
+                  #001
+                
+                
+                  010
+                  32.0 kHz
+                  #010
+                
+                
+                  011
+                  Setting prohibited
+                  #011
+                
+                
+                  100
+                  8.0 kHz  ( Valid only when IFS[3:0] =1001b )
+                  #100
+                
+                
+                  101
+                  16.0 kHz  ( Valid only when IFS[3:0] =1001b )
+                  #101
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          SRCODCTRL
+          Output Data Control Register
+          0x5FFA
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              OCH
+              Output Data Channel Exchange
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Does not exchange the channels (the same order as data input)
+                  #0
+                
+                
+                  1
+                  Exchanges the channels (the opposite order from data input)
+                  #1
+                
+              
+            
+            
+              OED
+              Output Data Endian
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Endian formats are the same between the chip and input data.
+                  #0
+                
+                
+                  1
+                  Endian formats are different between the chip and input data.
+                  #1
+                
+              
+            
+            
+              OEN
+              Output Data FIFO Full Interrupt Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Output data FIFO full interrupt is disabled.
+                  #0
+                
+                
+                  1
+                  Output data FIFO full interrupt is enabled.
+                  #1
+                
+              
+            
+            
+              OFTRG
+              Output FIFO Data Trigger Number
+              0
+              1
+              read-write
+              
+                
+                  00
+                  1
+                  #00
+                
+                
+                  01
+                  4
+                  #01
+                
+                
+                  10
+                  8
+                  #10
+                
+                
+                  11
+                  12
+                  #11
+                
+              
+            
+          
+        
+        
+          SRCSTAT
+          Status Register
+          0x5FFE
+          16
+          read-write
+          0x0002
+          0xFFFF
+          
+            
+              OFDN
+              Output FIFO Data CountIndicates the number of data units in the output FIFO.
+              11
+              15
+              read-write
+            
+            
+              IFDN
+              Input FIFO Data CountIndicates the number of data units in the input FIFO.
+              7
+              10
+              read-write
+            
+            
+              CEF
+              Conversion End Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  All of the output data has not been read out.
+                  #0
+                
+                
+                  1
+                  All of the output data has been read out.
+                  #1
+                
+              
+            
+            
+              FLF
+              Flush Processing Status Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Flash processing is completed.
+                  #0
+                
+                
+                  1
+                  Flash processing is in progress.
+                  #1
+                
+              
+            
+            
+              UDF
+              Output FIFO Underflow Interrupt Request Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Output data FIFO has not been read out.
+                  #0
+                
+                
+                  1
+                  Output data FIFO has been read out.
+                  #1
+                
+              
+            
+            
+              OVF
+              Output Data FIFO Overwrite Interrupt Request Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Next data conversion processing is not completed.
+                  #0
+                
+                
+                  1
+                  Next data conversion processing is completed.
+                  #1
+                
+              
+            
+            
+              IINT
+              Input Data FIFO Empty Interrupt Request Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number.
+                  #0
+                
+                
+                  1
+                  Number of data units in the input FIFO has become equal to or smaller than the specified triggering number.
+                  #1
+                
+              
+            
+            
+              OINT
+              Output Data FIFO Full Interrupt Request Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Number of data units in the output FIFO has not become equal to or greater than the specified triggering number.
+                  #0
+                
+                
+                  1
+                  Number of data units in the output FIFO has become equal to or greater than the specified triggering number.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+        R_SSI0
+        Serial Sound Interface Enhanced (SSIE)
+        0x4004E000
+        
+            0x00
+            8
+            registers
+        
+        
+            0x10
+            24
+            registers
+        
+        
+            
+                SSICR
+                Control Register
+                0x00
+                32
+                read-write
+                0x00000000
+                0xFFFFFFFF
+                
+                    
+                        CKS
+                        Oversampling Clock Select
+                        30
+                        30
+                        read-write
+                        
+                            
+                                0
+                                AUDIO_CLK input
+                                #0
+                            
+                            
+                                1
+                                Setting prohibited
+                                #1
+                            
+                        
+                    
+                    
+                        TUIEN
+                        Transmit Underflow Interrupt Enable
+                        29
+                        29
+                        read-write
+                        
+                            
+                                0
+                                Disables an underflow interrupt.
+                                #0
+                            
+                            
+                                1
+                                Enables an underflow interrupt.
+                                #1
+                            
+                        
+                    
+                    
+                        TOIEN
+                        Transmit Overflow Interrupt Enable
+                        28
+                        28
+                        read-write
+                        
+                            
+                                0
+                                Disables an overflow interrupt.
+                                #0
+                            
+                            
+                                1
+                                Enables an overflow interrupt.
+                                #1
+                            
+                        
+                    
+                    
+                        RUIEN
+                        Receive Underflow Interrupt Enable
+                        27
+                        27
+                        read-write
+                        
+                            
+                                0
+                                Disables an underflow interrupt.
+                                #0
+                            
+                            
+                                1
+                                Enables an underflow interrupt.
+                                #1
+                            
+                        
+                    
+                    
+                        ROIEN
+                        Receive Overflow Interrupt Enable
+                        26
+                        26
+                        read-write
+                        
+                            
+                                0
+                                Disables an overflow interrupt.
+                                #0
+                            
+                            
+                                1
+                                Enables an overflow interrupt.
+                                #1
+                            
+                        
+                    
+                    
+                        IIEN
+                        Idle Mode Interrupt Enable
+                        25
+                        25
+                        read-write
+                        
+                            
+                                0
+                                Disables an idle mode interrupt.
+                                #0
+                            
+                            
+                                1
+                                Enables an idle mode interrupt.
+                                #1
+                            
+                        
+                    
+                    
+                        FRM
+                        Channels
+                        22
+                        23
+                        read-write
+                        
+                            
+                                00
+                                One channel
+                                #00
+                            
+                            
+                                others
+                                Settings other than above are prohibited.
+                                true
+                            
+                        
+                    
+                    
+                        DWL
+                        Data Word Length
+                        19
+                        21
+                        read-write
+                        
+                            
+                                000
+                                8 bits
+                                #000
+                            
+                            
+                                001
+                                16 bits
+                                #001
+                            
+                            
+                                010
+                                18 bits
+                                #010
+                            
+                            
+                                011
+                                20 bits
+                                #011
+                            
+                            
+                                100
+                                22 bits
+                                #100
+                            
+                            
+                                101
+                                24 bits
+                                #101
+                            
+                            
+                                others
+                                Settings other than above are prohibited.
+                                true
+                            
+                        
+                    
+                    
+                        SWL
+                        System Word LengthSet the system word length to the bit clock frequency/2 fs.
+                        16
+                        18
+                        read-write
+                        
+                            
+                                000
+                                8 bits (serial bit clock frequency = 16fs )
+                                #000
+                            
+                            
+                                001
+                                16 bits (serial bit clock frequency = 32fs )
+                                #001
+                            
+                            
+                                010
+                                24 bits (serial bit clock frequency = 48fs )
+                                #010
+                            
+                            
+                                011
+                                32 bits (serial bit clock frequency = 64fs )
+                                #011
+                            
+                            
+                                others
+                                Settings other than above are prohibited.
+                                true
+                            
+                        
+                    
+                    
+                        MST
+                        Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited.
+                        14
+                        14
+                        read-write
+                        
+                            
+                                0
+                                Serial word select is input, slave mode.
+                                #0
+                            
+                            
+                                1
+                                Serial word select is output, master mode.
+                                #1
+                            
+                        
+                    
+                    
+                        BCKP
+                        Serial Bit Clock Polarity
+                        13
+                        13
+                        read-write
+                        
+                            
+                                0
+                                SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge).
+                                #0
+                            
+                            
+                                1
+                                SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge).
+                                #1
+                            
+                        
+                    
+                    
+                        LRCKP
+                        Serial WS Polarity
+                        12
+                        12
+                        read-write
+                        
+                            
+                                0
+                                SSIWS is low for 1st channel, high for 2nd channel.
+                                #0
+                            
+                            
+                                1
+                                SSIWS is high for 1st channel, low for 2nd channel.
+                                #1
+                            
+                        
+                    
+                    
+                        SPDP
+                        Serial Padding Polarity
+                        11
+                        11
+                        read-write
+                        
+                            
+                                0
+                                Padding bits are low.
+                                #0
+                            
+                            
+                                1
+                                Padding bits are high.
+                                #1
+                            
+                        
+                    
+                    
+                        SDTA
+                        Serial Data Alignment
+                        10
+                        10
+                        read-write
+                        
+                            
+                                0
+                                Transmitting and receiving in the order of serial data and padding bits
+                                #0
+                            
+                            
+                                1
+                                Transmitting and receiving in the order of padding bits and serial data
+                                #1
+                            
+                        
+                    
+                    
+                        PDTA
+                        Parallel Data Alignment
+                        9
+                        9
+                        read-write
+                        
+                            
+                                0
+                                The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits)
+                                #0
+                            
+                            
+                                1
+                                The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits)
+                                #1
+                            
+                        
+                    
+                    
+                        DEL
+                        Serial Data Delay
+                        8
+                        8
+                        read-write
+                        
+                            
+                                0
+                                1 clock cycle delay between SSIWS and SSIDATA
+                                #0
+                            
+                            
+                                1
+                                No delay between SSIWS and SSIDATA
+                                #1
+                            
+                        
+                    
+                    
+                        CKDV
+                        Serial Oversampling Clock Division Ratio
+                        4
+                        7
+                        read-write
+                        
+                            
+                                0x0
+                                CLK
+                                0x0
+                            
+                            
+                                0x1
+                                CLK/2
+                                0x1
+                            
+                            
+                                0x2
+                                CLK/4
+                                0x2
+                            
+                            
+                                0x3
+                                CLK/8
+                                0x3
+                            
+                            
+                                0x4
+                                CLK/16
+                                0x4
+                            
+                            
+                                0x5
+                                CLK/32
+                                0x5
+                            
+                            
+                                0x6
+                                CLK/64
+                                0x6
+                            
+                            
+                                0x7
+                                CLK/128
+                                0x7
+                            
+                            
+                                0x8
+                                CLK/6
+                                0x8
+                            
+                            
+                                0x9
+                                CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
+                                0x9
+                            
+                            
+                                0xA
+                                CLK/24
+                                0xA
+                            
+                            
+                                0xB
+                                CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
+                                0xB
+                            
+                            
+                                0xC
+                                CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)
+                                0xC
+                            
+                            
+                                others
+                                Settings other than above are prohibited.
+                                true
+                            
+                        
+                    
+                    
+                        MUEN
+                        Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing.
+                        3
+                        3
+                        read-write
+                        
+                            
+                                0
+                                This module is not muted.
+                                #0
+                            
+                            
+                                1
+                                This module is muted.
+                                #1
+                            
+                        
+                    
+                    
+                        TEN
+                        Transmit Enable
+                        1
+                        1
+                        read-write
+                        
+                            
+                                0
+                                Disables the transmit operation.
+                                #0
+                            
+                            
+                                1
+                                Enables the transmit operation.
+                                #1
+                            
+                        
+                    
+                    
+                        REN
+                        Receive Enable
+                        0
+                        0
+                        read-write
+                        
+                            
+                                0
+                                Disables the receive operation.
+                                #0
+                            
+                            
+                                1
+                                Enables the receive operation.
+                                #1
+                            
+                        
+                    
+                
+            
+            
+                SSISR
+                Status Register
+                0x04
+                32
+                read-write
+                0x02000013
+                0x3E00007F
+                
+                    
+                        TUIRQ
+                        Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+                        29
+                        29
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                No transmit underflow has occurred.
+                                #0
+                            
+                            
+                                1
+                                A transmit underflow has occurred.
+                                #1
+                            
+                        
+                    
+                    
+                        TOIRQ
+                        Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+                        28
+                        28
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                No transmit overflow has occurred.
+                                #0
+                            
+                            
+                                1
+                                A transmit overflow has occurred.
+                                #1
+                            
+                        
+                    
+                    
+                        RUIRQ
+                        Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+                        27
+                        27
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                No receive underflow has occurred.
+                                #0
+                            
+                            
+                                1
+                                A receive underflow has occurred.
+                                #1
+                            
+                        
+                    
+                    
+                        ROIRQ
+                        Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+                        26
+                        26
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                No receive overflow has occurred.
+                                #0
+                            
+                            
+                                1
+                                A receive overflow has occurred.
+                                #1
+                            
+                        
+                    
+                    
+                        IIRQ
+                        Idle Mode Interrupt Status Flag
+                        25
+                        25
+                        read-only
+                        
+                            
+                                0
+                                This module is not in idle state.
+                                #0
+                            
+                            
+                                1
+                                This module is in idle state.
+                                #1
+                            
+                        
+                    
+                    
+                        TCHNO
+                        Transmit Channel Number
+                        5
+                        6
+                        read-only
+                    
+                    
+                        TSWNO
+                        Transmit Serial Word Number
+                        4
+                        4
+                        read-only
+                    
+                    
+                        RCHNO
+                        Receive Channel Number.These bits are read as 00b.
+                        2
+                        3
+                        read-only
+                    
+                    
+                        RSWNO
+                        Receive Serial Word Number
+                        1
+                        1
+                        read-only
+                    
+                    
+                        IDST
+                        Idle Mode Status Flag
+                        0
+                        0
+                        read-only
+                        
+                            
+                                0
+                                Serial bus is operating.
+                                #0
+                            
+                            
+                                1
+                                The current communication is stopped.
+                                #1
+                            
+                        
+                    
+                
+            
+            
+                SSIFCR
+                FIFO Control Register
+                0x10
+                32
+                read-write
+                0x00000000
+                0xFFFFFFFF
+                
+                    
+                        AUCKE
+                        Oversampling Clock Enable
+                        31
+                        31
+                        read-write
+                        
+                            
+                                0
+                                The oversampling clock is disabled.
+                                #0
+                            
+                            
+                                1
+                                The oversampling clock is enabled.
+                                #1
+                            
+                        
+                    
+                    
+                        SSIRST
+                        SSI soft ware reset
+                        16
+                        16
+                        read-write
+                        
+                            
+                                0
+                                Clears the SSI software reset.
+                                #0
+                            
+                            
+                                1
+                                initiates the SSI software reset.
+                                #1
+                            
+                        
+                    
+                    
+                        TTRG
+                        Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set.
+                        6
+                        7
+                        read-write
+                        
+                            
+                                00
+                                7 (1)
+                                #00
+                            
+                            
+                                01
+                                6 (2)
+                                #01
+                            
+                            
+                                10
+                                4 (4)
+                                #10
+                            
+                            
+                                11
+                                2 (6)
+                                #11
+                            
+                        
+                    
+                    
+                        RTRG
+                        Receive Data Trigger Number
+                        4
+                        5
+                        read-write
+                        
+                            
+                                00
+                                1
+                                #00
+                            
+                            
+                                01
+                                2
+                                #01
+                            
+                            
+                                10
+                                4
+                                #10
+                            
+                            
+                                11
+                                6
+                                #11
+                            
+                        
+                    
+                    
+                        TIE
+                        Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit.
+                        3
+                        3
+                        read-write
+                        
+                            
+                                0
+                                Transmit data empty interrupt (TXI) request is disabled
+                                #0
+                            
+                            
+                                1
+                                Transmit data empty interrupt (TXI) request is enabled
+                                #1
+                            
+                        
+                    
+                    
+                        RIE
+                        Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit.
+                        2
+                        2
+                        read-write
+                        
+                            
+                                0
+                                Receive data full interrupt (RXI) request is disabled
+                                #0
+                            
+                            
+                                1
+                                Receive data full interrupt (RXI) request is enabled
+                                #1
+                            
+                        
+                    
+                    
+                        TFRST
+                        Transmit FIFO Data Register Reset
+                        1
+                        1
+                        read-write
+                        
+                            
+                                0
+                                Clears the transmit data FIFO reset.
+                                #0
+                            
+                            
+                                1
+                                Initiates the transmit data FIFO reset.
+                                #1
+                            
+                        
+                    
+                    
+                        RFRST
+                        Receive FIFO Data Register Reset
+                        0
+                        0
+                        read-write
+                        
+                            
+                                0
+                                Clears the receive data FIFO reset.
+                                #0
+                            
+                            
+                                1
+                                Initiates the receive data FIFO reset.
+                                #1
+                            
+                        
+                    
+                
+            
+            
+                SSIFSR
+                FIFO Status Register
+                0x14
+                32
+                read-write
+                0x00010000
+                0xFFFFFFFF
+                
+                    
+                        TDC
+                        Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR)
+                        24
+                        29
+                        read-only
+                    
+                    
+                        TDE
+                        Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs.
+                        16
+                        16
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number.
+                                #0
+                            
+                            
+                                1
+                                Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number.
+                                #1
+                            
+                        
+                    
+                    
+                        RDC
+                        Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR)
+                        8
+                        13
+                        read-only
+                    
+                    
+                        RDF
+                        Receive Data Full Flag NOTE:  Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read.
+                        0
+                        0
+                        read-write
+                        zeroToClear
+                        modify
+                        
+                            
+                                0
+                                Number of received data bytes in SSIFRDR is less than the set receive trigger number.
+                                #0
+                            
+                            
+                                1
+                                Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number.
+                                #1
+                            
+                        
+                    
+                
+            
+            
+                SSIFTDR
+                Transmit FIFO Data Register
+                0x18
+                32
+                write-only
+                0x00000000
+                0x00000000
+                
+                    
+                        SSIFTDR
+                        SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted.  NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs.
+                        0
+                        31
+                        write-only
+                    
+                
+            
+            
+                SSIFTDR16
+                Transmit FIFO Data Register
+                SSIFTDR
+                0x18
+                16
+                write-only
+                0x00000000
+                0x00000000
+            
+            
+                SSIFTDR8
+                Transmit FIFO Data Register
+                SSIFTDR
+                0x18
+                8
+                write-only
+                0x00000000
+                0x00000000
+            
+            
+                SSIFRDR
+                Receive FIFO Data Register
+                0x1C
+                32
+                read-only
+                0x00000000
+                0x00000000
+                
+                    
+                        SSIFRDR
+                        SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data.
+                        0
+                        31
+                        read-only
+                    
+                
+            
+            
+                SSIFRDR16
+                Receive FIFO Data Register
+                SSIFRDR
+                0x1C
+                16
+                read-only
+                0x00000000
+                0x00000000
+            
+            
+                SSIFRDR8
+                Receive FIFO Data Register
+                SSIFRDR
+                0x1C
+                8
+                read-only
+                0x00000000
+                0x00000000
+            
+            
+                SSIOFR
+                Audio Format Register
+                0x20
+                32
+                read-write
+                0x00000000
+                0xFFFFFFFF
+                
+                    
+                        BCKASTP
+                        Whether to Enable Stopping BCK Output When SSIE is in Idle Status
+                        9
+                        9
+                        read-write
+                        
+                            
+                                0
+                                Always outputs BCK to the SSIBCK pin.
+                                #0
+                            
+                            
+                                1
+                                Automatically controls output of BCK to the SSIBCK pin.
+                                #1
+                            
+                        
+                    
+                    
+                        LRCONT
+                        Whether to Enable LRCK/FS Continuation
+                        8
+                        8
+                        read-write
+                        
+                            
+                                0
+                                Disables LRCK/FS continuation.
+                                #0
+                            
+                            
+                                1
+                                Enables LRCK/FS continuation.
+                                #1
+                            
+                        
+                    
+                    
+                        OMOD
+                        Audio Format Select
+                        0
+                        1
+                        read-write
+                        
+                            
+                                00
+                                I2S format
+                                #00
+                            
+                            
+                                01
+                                TDM format
+                                #01
+                            
+                            
+                                10
+                                Monaural format
+                                #10
+                            
+                            
+                                11
+                                Setting prohibited.
+                                #11
+                            
+                        
+                    
+                
+            
+            
+                SSISCR
+                Status Control Register
+                0x24
+                32
+                read-write
+                0x00000000
+                0xFFFFFFFF
+                
+                    
+                        TDES
+                        TDE Setting Condition Select
+                        8
+                        12
+                        read-write
+                        
+                            
+                                00000
+                                SSIFTDR has one stage or more free space
+                                #00000
+                            
+                            
+                                00001
+                                SSIFTDR has two stages or more free space (snip)
+                                #00001
+                            
+                            
+                                11110
+                                SSIFTDR has thirty-one stages or more free space
+                                #11110
+                            
+                            
+                                11111
+                                SSIFTDR has thirty-two stages or more free space.
+                                #11111
+                            
+                        
+                    
+                    
+                        RDFS
+                        RDF Setting Condition Select
+                        0
+                        4
+                        read-write
+                        
+                            
+                                00000
+                                SSIFRDR has one stage or more data size
+                                #00000
+                            
+                            
+                                00001
+                                SSIFRDR has two stages or more data size (snip)
+                                #00001
+                            
+                            
+                                11110
+                                SSIFRDR has thirty-one stages or more data size
+                                #11110
+                            
+                            
+                                11111
+                                SSIFRDR has thirty-two stages or more data size.
+                                #11111
+                            
+                        
+                    
+                
+            
+        
+    
+    
+        R_SSI1
+        Serial Sound Interface Enhanced (SSIE)
+        0x4004E100
+    
+    
+      R_SYSTEM
+      System Pins
+      0x4001E000
+      
+        0x0000000C
+        0x02
+        registers
+      
+      
+        0x0000001C
+        0x009
+        registers
+      
+      
+        0x00000026
+        0x01
+        registers
+      
+      
+        0x00000028
+        0x004
+        registers
+      
+      
+        0x00000030
+        0x003
+        registers
+      
+      
+        0x00000036
+        0x01
+        registers
+      
+      
+        0x00000038
+        0x005
+        registers
+      
+      
+        0x0000003E
+        0x004
+        registers
+      
+      
+        0x00000050
+        0x01
+        registers
+      
+      
+        0x00000052
+        0x002
+        registers
+      
+      
+        0x00000061
+        0x002
+        registers
+      
+      
+        0x00000092
+        0x01
+        registers
+      
+      
+        0x00000094
+        0x01
+        registers
+      
+      
+        0x00000098
+        0x04
+        registers
+      
+      
+        0x0000009E
+        0x003
+        registers
+      
+      
+        0x000000A2
+        0x01
+        registers
+      
+      
+        0x000000A5
+        0x01
+        registers
+      
+      
+        0x000000AA
+        0x01
+        registers
+      
+      
+        0x000000C0
+        0x02
+        registers
+      
+      
+        0x000000D1
+        0x01
+        registers
+      
+      
+        0x000000E0
+        0x004
+        registers
+      
+      
+        0x000003FE
+        0x02
+        registers
+      
+      
+        0x00000402
+        0x00B
+        registers
+      
+      
+        0x0000040E
+        0x01
+        registers
+      
+      
+        0x00000410
+        0x002
+        registers
+      
+      
+        0x00000413
+        0x01
+        registers
+      
+      
+        0x00000417
+        0x002
+        registers
+      
+      
+        0x0000041A
+        0x002
+        registers
+      
+      
+        0x0000041F
+        0x01
+        registers
+      
+      
+        0x00000480
+        0x002
+        registers
+      
+      
+        0x00000490
+        0x01
+        registers
+      
+      
+        0x00000492
+        0x01
+        registers
+      
+      
+        0x000004B0
+        0x003
+        registers
+      
+      
+        0x000004B4
+        0x01
+        registers
+      
+      
+        0x000004B6
+        0x01
+        registers
+      
+      
+        0x000004B8
+        0x008
+        registers
+      
+      
+        0x00000500
+        0x200
+        registers
+      
+      
+        
+          SBYCR
+          Standby Control Register
+          0x00C
+          16
+          read-write
+          0x4000
+          0xFFFF
+          
+            
+              SSBY
+              Software Standby
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Sleep mode
+                  #0
+                
+                
+                  1
+                  Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1)
+                  #1
+                
+              
+            
+            
+              OPE
+              Output Port Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state.
+                  #0
+                
+                
+                  1
+                  In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state..
+                  #1
+                
+              
+            
+          
+        
+        
+          MSTPCRA
+          Module Stop Control Register A
+          0x01C
+          32
+          read-write
+          0xFFBFFF1C
+          0xFFFFFFFF
+          
+            
+              MSTPA22
+              DMA Controller/Data Transfer Controller Module Stop
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPA7
+              Standby RAM Module Stop
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPA6
+              ECCRAM Module Stop
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPA5
+              High-Speed RAM Module Stop
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPA1
+              RAM1 Module Stop
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+            
+              MSTPA0
+              RAM0 Module Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Cancel the module-stop state
+                  #0
+                
+                
+                  1
+                  Enter the module-stop state
+                  #1
+                
+              
+            
+          
+        
+        
+          SCKDIVCR
+          System Clock Division Control Register
+          0x020
+          32
+          read-write
+          0x22022222
+          0xFFFFFFFF
+          
+            
+              FCK
+              Flash IF Clock (FCLK) Select
+              28
+              30
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              ICK
+              System Clock (ICLK) Select
+              24
+              26
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              BCK
+              External Bus Clock (BCLK) Select
+              16
+              18
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PCKA
+              Peripheral Module Clock A (PCLKA) Select 
+              12
+              14
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PCKB
+              Peripheral Module Clock B (PCLKB) Select
+              8
+              10
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PCKC
+              Peripheral Module Clock C (PCLKC) Select
+              4
+              6
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PCKD
+              Peripheral Module Clock D (PCLKD) Select 
+              0
+              2
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4 
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          SCKDIVCR2
+          System Clock Division Control Register 2 
+          0x024
+          8
+          read-write
+          0x40
+          0xFF
+          
+            
+              UCK
+              USB Clock (UCLK) Select 
+              4
+              6
+              read-write
+              
+                
+                  010
+                  /3
+                  #010
+                
+                
+                  011
+                  /4
+                  #011
+                
+                
+                  100
+                  /5
+                  #100
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          SCKSCR
+          System Clock Source Control Register
+          0x026
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              CKSEL
+              Clock Source Select
+              0
+              2
+              read-write
+              
+                
+                  000
+                  HOCO 
+                  #000
+                
+                
+                  001
+                  MOCO
+                  #001
+                
+                
+                  010
+                  LOCO 
+                  #010
+                
+                
+                  011
+                  Main clock oscillator 
+                  #011
+                
+                
+                  100
+                  Sub-clock oscillator 
+                  #100
+                
+                
+                  101
+                  PLL
+                  #101
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          PLLCCR
+          PLL Clock Control Register
+          0x028
+          16
+          read-write
+          0x1300
+          0xFFFF
+          
+            
+              PLLMUL
+              PLL Frequency Multiplication Factor Select   [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2   Range: 0x23 - 0x3B   for example       010011: x10.0       010100: x10.5       010101: x11.0          :       011100: x14.5       011101: x15.0       011110: x15.5          :       111010: x29.5       111011: x30.0
+              8
+              13
+              read-write
+              
+                
+                  #010011
+                  #111011
+                
+              
+              
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+            
+              PLSRCSEL
+              PLL Clock Source Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Main clock oscillator
+                  #0
+                
+                
+                  1
+                  HOCO
+                  #1
+                
+              
+            
+            
+              PLIDIV
+              PLL Input Frequency Division Ratio Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  /1 
+                  #00
+                
+                
+                  01
+                  /2
+                  #01
+                
+                
+                  10
+                  /3
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          PLLCR
+          PLL Control Register
+          0x02A
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              PLLSTP
+              PLL Stop Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operate the PLL
+                  #0
+                
+                
+                  1
+                  Stop the PLL.
+                  #1
+                
+              
+            
+          
+        
+        
+          PLLCCR2
+          PLL Clock Control Register2
+          0x02B
+          8
+          read-write
+          0x07
+          0xFF
+          
+            
+              PLODIV
+              PLL Output Frequency Division Ratio Select
+              6
+              7
+              read-write
+              
+                
+                  00
+                  /1.
+                  #00
+                
+                
+                  01
+                  /2.
+                  #01
+                
+                
+                  10
+                  /4.
+                  #10
+                
+                
+                  11
+                  Setting prohibited.
+                  #11
+                
+              
+            
+            
+              PLLMUL
+              PLL Frequency Multiplication Factor Select
+              0
+              4
+              read-write
+              
+                
+                  1111
+                  Settings prohibited.
+                  #1111
+                
+                
+                  others
+                  x PLLMUL[4:0] +1
+                  true
+                
+              
+            
+          
+        
+        
+          BCKCR
+          External Bus Clock Control Register
+          0x030
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BCLKDIV
+              BCLK Pin Output Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  BCLK
+                  #0
+                
+                
+                  1
+                  BCLK/2
+                  #1
+                
+              
+            
+          
+        
+        
+          MEMWAIT
+          Memory Wait Cycle Control Register
+          0x031
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MEMWAIT
+              Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz).
+              0
+              0
+              read-write
+              
+                
+                  0
+                  no wait 
+                  #0
+                
+                
+                  1
+                  wait
+                  #1
+                
+              
+            
+          
+        
+        
+          MOSCCR
+          Main Clock Oscillator Control Register 
+          0x032
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              MOSTP
+              Main Clock Oscillator Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Main clock oscillator is operating.
+                  #0
+                
+                
+                  1
+                  Main clock oscillator is stopped.
+                  #1
+                
+              
+            
+          
+        
+        
+          HOCOCR
+          High-Speed On-Chip Oscillator Control Register
+          0x036
+          8
+          read-write
+          0x00
+          0xFE
+          
+            
+              HCSTP
+              HOCO Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operate the HOCO clock
+                  #0
+                
+                
+                  1
+                  Stop the HOCO clock
+                  #1
+                
+              
+            
+          
+        
+        
+          MOCOCR
+          Middle-Speed On-Chip Oscillator Control Register
+          0x038
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MCSTP
+              MOCO Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Operate the MOCO clock
+                  #0
+                
+                
+                  1
+                  Stop the MOCO clock
+                  #1
+                
+              
+            
+          
+        
+        
+          FLLCR1
+          FLL Control Register 1
+          0x039
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              FLLEN
+              FLL Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  FLL function is disabled.
+                  #0
+                
+                
+                  1
+                  FLL function is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          FLLCR2
+          FLL Control Register 2
+          0x03A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FLLCNTL
+              FLL Multiplication ControlMultiplication ratio  of the FLL reference clock select
+              0
+              10
+              read-write
+            
+          
+        
+        
+          OSCSF
+          Oscillation Stabilization Flag Register
+          0x03C
+          8
+          read-only
+          0x00
+          0xFE
+          
+            
+              PLLSF
+              PLL Clock Oscillation Stabilization Flag
+              5
+              5
+              read-only
+              
+                
+                  0
+                  PLL clock is stopped or is not yet stable
+                  #0
+                
+                
+                  1
+                  PLL clock is stable, so is available for use as the system clock
+                  #1
+                
+              
+            
+            
+              MOSCSF
+              Main Clock Oscillation Stabilization Flag
+              3
+              3
+              read-only
+              
+                
+                  0
+                  Main clock oscillator is stopped (MOSTP = 1) or is not yet stable
+                  #0
+                
+                
+                  1
+                  Main clock oscillator is stable, so is available for use as the system clock
+                  #1
+                
+              
+            
+            
+              HOCOSF
+              HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1.
+              0
+              0
+              read-only
+              
+                
+                  0
+                  HOCO clock is stopped or is not yet stable
+                  #0
+                
+                
+                  1
+                  HOCO clock is stable, so is available for use as the system clock
+                  #1
+                
+              
+            
+          
+        
+        
+          CKOCR
+          Clock Out Control Register
+          0x03E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CKOEN
+              Clock out enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable clock out
+                  #0
+                
+                
+                  1
+                  Enable clock out
+                  #1
+                
+              
+            
+            
+              CKODIV
+              Clock out input frequency Division Select
+              4
+              6
+              read-write
+              
+                
+                  000
+                  /1
+                  #000
+                
+                
+                  001
+                  /2
+                  #001
+                
+                
+                  010
+                  /4
+                  #010
+                
+                
+                  011
+                  /8
+                  #011
+                
+                
+                  100
+                  /16
+                  #100
+                
+                
+                  101
+                  /32
+                  #101
+                
+                
+                  110
+                  /64
+                  #110
+                
+                
+                  111
+                  /128
+                  #111
+                
+              
+            
+            
+              CKOSEL
+              Clock out source select
+              0
+              2
+              read-write
+              
+                
+                  000
+                  HOCO
+                  #000
+                
+                
+                  001
+                  MOCO
+                  #001
+                
+                
+                  010
+                  LOCO
+                  #010
+                
+                
+                  011
+                  MOSC
+                  #011
+                
+                
+                  100
+                  SOSC
+                  #100
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          TRCKCR
+          Trace Clock Control Register
+          0x03F
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              TRCKEN
+              Trace Clock operating Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable operation
+                  #0
+                
+                
+                  1
+                  Enable operation
+                  #1
+                
+              
+            
+            
+              TRCK
+              Trace Clock operating frequency select
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  /1
+                  #0000
+                
+                
+                  0001
+                  /2
+                  #0001
+                
+                
+                  0010
+                  /4
+                  #0010
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          OSTDCR
+          Oscillation Stop Detection Control Register
+          0x040
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OSTDE
+              Oscillation Stop Detection Function Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable oscillation stop detection function
+                  #0
+                
+                
+                  1
+                  Enable oscillation stop detection function
+                  #1
+                
+              
+            
+            
+              OSTDIE
+              Oscillation Stop Detection Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable oscillation stop detection interrupt (do not notify the POEG)
+                  #0
+                
+                
+                  1
+                  Enable oscillation stop detection interrupt (notify the POEG)
+                  #1
+                
+              
+            
+          
+        
+        
+          OSTDSR
+          Oscillation Stop Detection Status Register
+          0x041
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OSTDF
+              Oscillation Stop Detection Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Main clock oscillation stop not detected
+                  #0
+                
+                
+                  1
+                  Main clock oscillation stop detected
+                  #1
+                
+              
+            
+          
+        
+        
+          SLCDSCKCR
+          Segment LCD Source Clock Control Register
+          0x050
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LCDSCKEN
+              LCD Source Clock Out Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  LCD source clock out disabled
+                  #0
+                
+                
+                  1
+                  LCD source clock out enabled.
+                  #1
+                
+              
+            
+            
+              LCDSCKSEL
+              LCD Source Clock (LCDSRCCLK) Select
+              0
+              2
+              read-write
+              
+                
+                  000
+                  LOCO
+                  #000
+                
+                
+                  001
+                  SOSC
+                  #001
+                
+                
+                  010
+                  MOSC
+                  #010
+                
+                
+                  100
+                  HOCO
+                  #100
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          EBCKOCR
+          External Bus Clock Output Control Register
+          0x052
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              EBCKOEN
+              BCLK Pin Output Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable EBCLK pin output (fixed high)
+                  #0
+                
+                
+                  1
+                  Enable EBCLK pin output
+                  #1
+                
+              
+            
+          
+        
+        
+          SDCKOCR
+          SDRAM Clock Output Control Register
+          0x053
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SDCKOEN
+              SDCLK Pin Output Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable SDCLK pin output (fixed high)
+                  #0
+                
+                
+                  1
+                  Enable SDCLK pin output
+                  #1
+                
+              
+            
+          
+        
+        
+          MOCOUTCR
+          MOCO User Trimming Control Register
+          0x061
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              MOCOUTRM
+              MOCO User Trimming  1000_0000 : -128   1000_0001 : -127   1000_0010 : -126   . . .  1111_1111 : -1  0000_0000 : Center Code  0000_0001 : +1  . . .  0111_1101 : +125  0111_1110 : +126  0111_1111 : +127These bits are added to original MOCO trimming bits
+              0
+              7
+              read-write
+            
+          
+        
+        
+          HOCOUTCR
+          HOCO User Trimming Control Register
+          0x062
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              HOCOUTRM
+              HOCO User Trimming  1000_0000 : -128   1000_0001 : -127   1000_0010 : -126   . . .  1111_1111 : -1  0000_0000 : Center Code  0000_0001 : +1  . . .  0111_1101 : +125  0111_1110 : +126  0111_1111 : +127These bits are added to original HOCO trimming bits
+              0
+              7
+              read-write
+            
+          
+        
+        
+          SNZCR
+          Snooze Control Register
+          0x092
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SNZE
+              Snooze Mode Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable Snooze Mode
+                  #0
+                
+                
+                  1
+                  Enable Snooze Mode
+                  #1
+                
+              
+            
+            
+              SNZDTCEN
+              DTC Enable in Snooze Mode
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disable DTC operation
+                  #0
+                
+                
+                  1
+                  Enable DTC operation
+                  #1
+                
+              
+            
+            
+              RXDREQEN
+              RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Ignore RXD0 falling edge in Standby mode.
+                  #0
+                
+                
+                  1
+                  Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. 
+                  #1
+                
+              
+            
+          
+        
+        
+          SNZEDCR
+          Snooze End Control Register
+          0x094
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SCI0UMTED
+              SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode.
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              AD1UMTED
+              AD compare mismatch 1 Snooze End Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              AD1MATED
+              AD compare match 1 Snooze End Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              AD0UMTED
+              AD compare mismatch 0 Snooze End Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              AD0MATED
+              AD compare match 0 Snooze End Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              DTCNZRED
+              Not Last DTC transmission completion Snooze End Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              DTCZRED
+              Last DTC transmission completion Snooze End Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+            
+              AGT1UNFED
+              AGT1 underflow Snooze End Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable the Snooze End request
+                  #0
+                
+                
+                  1
+                  Enable the Snooze End request
+                  #1
+                
+              
+            
+          
+        
+        
+          SNZREQCR
+          Snooze Request Control Register
+          0x098
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              SNZREQEN30
+              Snooze Request Enable 30Enable AGT1 compare match B snooze request
+              30
+              30
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN29
+              Snooze Request Enable 29Enable AGT1 compare match A snooze request
+              29
+              29
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN28
+              Snooze Request Enable 28Enable AGT1 underflow snooze request
+              28
+              28
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN25
+              Snooze Request Enable 25Enable RTC period snooze request
+              25
+              25
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN24
+              Snooze Request Enable 24Enable RTC alarm snooze request
+              24
+              24
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN23
+              Snooze Request Enable 23Enable Comparator-LP0 snooze request
+              23
+              23
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN22
+              Snooze Request Enable 22Enable Comparator-HS0 snooze request
+              22
+              22
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              SNZREQEN17
+              Snooze Request Enable 17Enable KR snooze request
+              17
+              17
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+            
+              16
+              1
+              SNZREQEN%s
+              Snooze Request Enable 0Enable IRQ %s pin snooze request
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable snooze request
+                  #0
+                
+                
+                  1
+                  Enable snooze request
+                  #1
+                
+              
+            
+          
+        
+        
+          FLSTOP
+          Flash Operation Control Register
+          0x09E
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              FLSTPF
+              Flash Memory Operation Status Flag
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Transition completed
+                  #0
+                
+                
+                  1
+                  During transition (from the flash-stop-status to flash-operating-status or vice versa)
+                  #1
+                
+              
+            
+            
+              FLSTOP
+              Selecting ON/OFF of the Flash Memory Operation
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Code flash and data flash memory operates
+                  #0
+                
+                
+                  1
+                  Code flash and data flash memory stops.
+                  #1
+                
+              
+            
+          
+        
+        
+          PSMCR
+          Power Save Memory Control Register
+          0x09F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              PSMC
+              Power save memory control.
+              0
+              1
+              read-write
+              
+                
+                  00
+                  All RAM is on Software Standby mode.
+                  #00
+                
+                
+                  01
+                  48KB RAM is on in Software Standby mode.
+                  #01
+                
+                
+                  others
+                  Setting prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          OPCCR
+          Operating Power Control Register
+          0x0A0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              OPCMTSF
+              Operating Power Control Mode Transition Status Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Transition completed
+                  #0
+                
+                
+                  1
+                  During transition
+                  #1
+                
+              
+            
+            
+              OPCM
+              Operating Power Control Mode Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  High-speed mode
+                  #00
+                
+                
+                  01
+                  Prohibited
+                  #01
+                
+                
+                  10
+                  Prohibited
+                  #10
+                
+                
+                  11
+                  Low-speed mode 
+                  #11
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          SOPCCR
+          Sub Operating Power Control Register
+          0x0AA
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SOPCMTSF
+              Sub Operating Power Control Mode Transition Status Flag
+              4
+              4
+              read-only
+              
+                
+                  0
+                  Transition completed
+                  #0
+                
+                
+                  1
+                  During transition
+                  #1
+                
+              
+            
+            
+              SOPCM
+              Sub Operating Power Control Mode Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Other than Subosc-speed mode
+                  #0
+                
+                
+                  1
+                  Subosc-speed mode
+                  #1
+                
+              
+            
+          
+        
+        
+          MOSCWTCR
+          Main Clock Oscillator Wait Control Register
+          0x0A2
+          8
+          read-write
+          0x05
+          0xFF
+          
+            
+              MSTS
+              Main clock oscillator wait time setting
+              0
+              3
+              read-write
+              
+                
+                  0001
+                  Wait time = 35 cycles (133.5 us)
+                  #0001
+                
+                
+                  0010
+                  Wait time = 67 cycles (255.6 us)
+                  #0010
+                
+                
+                  0011
+                  Wait time = 131 cycles (499.7 us)
+                  #0011
+                
+                
+                  0100
+                  Wait time = 259 cycles (988.0 us)
+                  #0100
+                
+                
+                  0101
+                  Wait time = 547 cycles (2086.6 us) (value after reset)
+                  #0101
+                
+                
+                  0110
+                  Wait time = 1059 cycles (4039.8 us)
+                  #0110
+                
+                
+                  0111
+                  Wait time = 2147 cycles (8190.2 us)
+                  #0111
+                
+                
+                  1000
+                  Wait time = 4291 cycles (16368.9 us)
+                  #1000
+                
+                
+                  1001
+                  Wait time = 8163 cycles (31139.4 us).
+                  #1001
+                
+                
+                  others
+                  settings prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          HOCOWTCR
+          High-speed on-chip oscillator wait control register
+          0x0A5
+          8
+          read-write
+          0x02
+          0xFF
+          
+            
+              HSTS
+              HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) 
+              0
+              2
+              read-write
+            
+          
+        
+        
+          RSTSR1
+          Reset Status Register 1
+          0x0C0
+          16
+          read-write
+          0x0000
+          0xE0F8
+          
+            
+              SPERF
+              SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              12
+              12
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SP error reset not detected.
+                  #0
+                
+                
+                  1
+                  SP error reset detected.
+                  #1
+                
+              
+            
+            
+              BUSMRF
+              Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              11
+              11
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Bus Master MPU reset not detected.
+                  #0
+                
+                
+                  1
+                  Bus Master MPU reset detected.
+                  #1
+                
+              
+            
+            
+              BUSSRF
+              Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              10
+              10
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Bus Slave MPU reset not detected.
+                  #0
+                
+                
+                  1
+                  Bus Slave MPU reset detected.
+                  #1
+                
+              
+            
+            
+              REERF
+              RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              9
+              9
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  RAM ECC error reset not detected.
+                  #0
+                
+                
+                  1
+                  RAM ECC error reset detected.
+                  #1
+                
+              
+            
+            
+              RPERF
+              RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              8
+              8
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  RAM parity error reset not detected.
+                  #0
+                
+                
+                  1
+                  RAM parity error reset detected.
+                  #1
+                
+              
+            
+            
+              SWRF
+              Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Software reset not detected.
+                  #0
+                
+                
+                  1
+                  Software reset detected.
+                  #1
+                
+              
+            
+            
+              WDTRF
+              Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Watchdog timer reset not detected.
+                  #0
+                
+                
+                  1
+                  Watchdog timer reset detected.
+                  #1
+                
+              
+            
+            
+              IWDTRF
+              Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Independent watchdog timer reset not detected.
+                  #0
+                
+                
+                  1
+                  Independent watchdog timer reset detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          STCONR
+          Standby Condition Register
+          0x40F
+          8
+          read-write
+          0xC3
+          0xFF
+          
+            
+              STCON
+              SSTBY condition bit
+              0
+              1
+              read-write
+              
+                
+                  00
+                  set this value in case of transferring to Software Standby Mode in using HOCO.
+                  #00
+                
+                
+                  11
+                  set this value in case of transferring to Software Standby Mode in using expect for HOCO.
+                  #11
+                
+              
+            
+          
+        
+        
+          2
+          0x2
+          1,2
+          LVD%sCR1
+          Voltage Monitor %s Circuit Control Register 1
+          0x0E0
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              IRQSEL
+              Voltage Monitor Interrupt Type Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Non-maskable interrupt
+                  #0
+                
+                
+                  1
+                  Maskable interrupt
+                  #1
+                
+              
+            
+            
+              IDTSEL
+              Voltage Monitor Interrupt Generation Condition Select
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Generate when VCC>=Vdet (rise) is detected
+                  #00
+                
+                
+                  01
+                  Generate when VCC<Vdet (drop) is detected
+                  #01
+                
+                
+                  10
+                  Generate when drop and rise are detected
+                  #10
+                
+                
+                  11
+                  Settings prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          USBCKCR
+          USB Clock Control Register
+          0xD0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              USBCLKSEL
+              The USBCLKSEL bit selects the source of the USB clock (UCLK).
+              0
+              0
+              read-write
+              
+                
+                  0
+                  PLL
+                  #0
+                
+                
+                  1
+                  HOCO
+                  #1
+                
+              
+            
+          
+        
+        
+          SDADCCKCR
+          24-bit Sigma-Delta A/D Converter Clock Control Register
+          0xD1
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SDADCCKSEL
+              24-bit Sigma-Delta A/D Converter Clock Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  MOSC is chosen by a source clock of 24-bit Sigma-Delta A/D Converter Clock.
+                  #0
+                
+                
+                  1
+                  HOCO is chosen by a source clock of 24-bit Sigma-Delta AA/D Converter Clock.
+                  #1
+                
+              
+            
+            
+              SDADCCKEN
+              24-bit Sigma-Delta A/D Converter Clock Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  24-bit Sigma-Delta A/D Converter Clock is disabled
+                  #0
+                
+                
+                  1
+                   24-bit Sigma-Delta A/D Converter Clock is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          0x2
+          1,2
+          LVD%sSR
+          Voltage Monitor %s Circuit Status Register
+          0x0E1
+          8
+          read-write
+          0x02
+          0xFF
+          
+            
+              MON
+              Voltage Monitor 1 Signal Monitor Flag
+              1
+              1
+              read-only
+              
+                
+                  0
+                  VCC < Vdet
+                  #0
+                
+                
+                  1
+                  VCC >= Vdet or MON bit is disabled
+                  #1
+                
+              
+            
+            
+              DET
+              Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Not detected
+                  #0
+                
+                
+                  1
+                  Vdet1 passage detection
+                  #1
+                
+              
+            
+          
+        
+        
+          PRCR
+          Protect Register
+          0x3FE
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              PRKEY
+              PRKEY Key Code
+              8
+              15
+              write-only
+              
+                
+                  0x5A
+                  Enables writing to the PRCR register.
+                  0x5A
+                
+                
+                  others
+                  Disables writing to the PRCR register.
+                  true
+                
+              
+            
+            
+              PRC3
+              Enables writing to the registers related to the LVD.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Writes protected.
+                  #0
+                
+                
+                  1
+                  Writes not protected.
+                  #1
+                
+              
+            
+            
+              PRC1
+              Enables writing to the registers related to the operating modes,  the low power consumption modes and the battery backup function.
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Writes protected.
+                  #0
+                
+                
+                  1
+                  Writes not protected.
+                  #1
+                
+              
+            
+            
+              PRC0
+              Enables writing to the registers related to the clock generation circuit.
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Writes protected.
+                  #0
+                
+                
+                  1
+                  Writes not protected.
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIER0
+          Deep Standby Interrupt Enable Register 0
+          0x402
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              DIRQ%sE
+              IRQ-DS Pin Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIER1
+          Deep Standby Interrupt Enable Register 1
+          0x403
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              8-15
+              DIRQ%sE
+              IRQ-DS Pin Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIER2
+          Deep Standby Interrupt Enable Register 2
+          0x404
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DNMIE
+              NMI Pin Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DRTCAIE
+              RTC Alarm interrupt Deep Standby Cancel Signal Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DTRTCIIE
+              RTC Interval interrupt Deep Standby Cancel Signal Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DLVD2IE
+              LVD2 Deep Standby Cancel Signal Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DLVD1IE
+              LVD1 Deep Standby Cancel Signal Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIER3
+          Deep Standby Interrupt Enable Register 3
+          0x405
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DAGT1IE
+              AGT1 Underflow Deep Standby Cancel Signal Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DUSBHSIE
+              USBHS Suspend/Resume Deep Standby Cancel Signal Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+            
+              DUSBFSIE
+              USBFS Suspend/Resume Deep Standby Cancel Signal Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Canceling deep software standby mode is disabled
+                  #0
+                
+                
+                  1
+                  Canceling deep software standby mode is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIFR0
+          Deep Standby Interrupt Flag Register 0
+          0x406
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              DIRQ%sF
+              IRQ-DS Pin Deep Standby Cancel Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIFR1
+          Deep Standby Interrupt Flag Register 1
+          0x407
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              8-15
+              DIRQ%sF
+              IRQ-DS Pin Deep Standby Cancel Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIFR2
+          Deep Standby Interrupt Flag Register 2
+          0x408
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DNMIF
+              NMI Pin Deep Standby Cancel Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DRTCAIF
+              RTC Alarm interrupt Deep Standby Cancel Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DTRTCIIF
+              RTC Interval interrupt Deep Standby Cancel Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DLVD2IF
+              LVD2 Deep Standby Cancel Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DLVD1IF
+              LVD1 Deep Standby Cancel Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIFR3
+          Deep Standby Interrupt Flag Register 3
+          0x409
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DAGT1IF
+              AGT1 Underflow Deep Standby Cancel Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DUSBHSIF
+              USBHS Suspend/Resume Deep Standby Cancel Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+            
+              DUSBFSIF
+              USBFS Suspend/Resume Deep Standby Cancel Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  The cancel request is not generated
+                  #0
+                
+                
+                  1
+                  The cancel request is generated
+                  #1
+                
+              
+            
+          
+        
+        
+          2
+          1
+          DPSIEGR%s
+          Deep Standby Interrupt Edge Register %s
+          0x40A
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              8
+              1
+              DIRQ%sEG
+              IRQ-DS Pin Edge Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  A cancel request is generated at a falling edge
+                  #0
+                
+                
+                  1
+                  A cancel request is generated at a rising edge
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSIEGR2
+          Deep Standby Interrupt Edge Register 2
+          0x40C
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              DNMIEG
+              NMI Pin Edge Select
+              4
+              4
+              read-write
+              
+                
+                  0
+                  A cancel request is generated at a falling edge
+                  #0
+                
+                
+                  1
+                  A cancel request is generated at a rising edge
+                  #1
+                
+              
+            
+            
+              DLVD2IEG
+              LVD2 Edge Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  A cancel request is generated when VCC<Vdet2 (fall) is detected
+                  #0
+                
+                
+                  1
+                  A cancel request is generated when VCC>=Vdet2 (rise) is detected
+                  #1
+                
+              
+            
+            
+              DLVD1IEG
+              LVD1 Edge Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  A cancel request is generated when VCC<Vdet1 (fall) is detected
+                  #0
+                
+                
+                  1
+                  A cancel request is generated when VCC>=Vdet1 (rise) is detected
+                  #1
+                
+              
+            
+          
+        
+        
+          DPSBYCR
+          Deep Standby Control Register
+          0x400
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              DPSBY
+              Deep Software Standby
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)
+                  #0
+                
+                
+                  1
+                  Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)
+                  #1
+                
+              
+            
+            
+              IOKEEP
+              I/O Port Retention
+              6
+              6
+              read-write
+              
+                
+                  0
+                  When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.
+                  #0
+                
+                
+                  1
+                  When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. 
+                  #1
+                
+              
+            
+            
+              DEEPCUT
+              Power-Supply Control
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode.
+                  #00
+                
+                
+                  01
+                  Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode.
+                  #01
+                
+                
+                  10
+                  Setting prohibited. 
+                  #10
+                
+                
+                  11
+                  Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.
+                  #11
+                
+              
+            
+          
+        
+        
+          SYOCDCR
+          System Control OCD Control Register
+          0x40E
+          8
+          read-write
+          0x00
+          0xFE
+          
+            
+              DBGEN
+              Debugger Enable bit
+              7
+              7
+              read-write
+              
+                
+                  0
+                  On-chip debugger is disabled
+                  #0
+                
+                
+                  1
+                  On-chip debugger is enabled
+                  #1
+                
+              
+            
+            
+              DOCDF
+              Deep Standby OCD flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  On-chip debugger is disabled
+                  #0
+                
+                
+                  1
+                  On-chip debugger is enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          MOMCR
+          Main Clock Oscillator Mode Oscillation Control Register
+          0x413
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              AUTODRVEN
+              Main Clock Oscillator Drive Capability Auto Switching Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable.
+                  #1
+                
+              
+            
+            
+              MOSEL
+              Main Clock Oscillator Switching
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Resonator
+                  #0
+                
+                
+                  1
+                  External clock input
+                  #1
+                
+              
+            
+            
+              MODRV0
+              Main Clock Oscillator Drive Capability 0 Switching
+              4
+              5
+              read-write
+              
+                
+                  00
+                  20MHz to 24MHz
+                  #00
+                
+                
+                  01
+                  16MHz to 20MHz
+                  #01
+                
+                
+                  10
+                  8MHz to 16MHz
+                  #10
+                
+                
+                  11
+                  8MHz  
+                  #11
+                
+              
+            
+            
+              MODRV1
+              Main Clock Oscillator Drive Capability 1 Switching
+              3
+              3
+              read-write
+              
+                
+                  0
+                  10 MHz to 20 MHz
+                  #0
+                
+                
+                  1
+                  1 MHz to 10 MHz.
+                  #1
+                
+              
+            
+          
+        
+        
+          RSTSR0
+          Reset Status Register 0
+          0x410
+          8
+          read-write
+          0x00
+          0x70
+          
+            
+              DPSRSTF
+              Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              7
+              7
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Deep software standby mode cancelation not requested by an interrupt. 
+                  #0
+                
+                
+                  1
+                  Deep software standby mode cancelation requested by an interrupt. 
+                  #1
+                
+              
+            
+            
+              LVD2RF
+              Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Voltage Monitor 2 reset not detected.
+                  #0
+                
+                
+                  1
+                  Voltage Monitor 2 reset detected.
+                  #1
+                
+              
+            
+            
+              LVD1RF
+              Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Voltage Monitor 1 reset not detected.
+                  #0
+                
+                
+                  1
+                  Voltage Monitor 1 reset detected.
+                  #1
+                
+              
+            
+            
+              LVD0RF
+              Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Voltage Monitor 0 reset not detected.
+                  #0
+                
+                
+                  1
+                  Voltage Monitor 0 reset detected.
+                  #1
+                
+              
+            
+            
+              PORF
+              Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0.
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Power-on reset not detected.
+                  #0
+                
+                
+                  1
+                  Power-on reset detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          RSTSR2
+          Reset Status Register 2
+          0x411
+          8
+          read-write
+          0x00
+          0xFE
+          
+            
+              CWSF
+              Cold/Warm Start Determination Flag
+              0
+              0
+              read-write
+              oneToSet
+              modify
+              
+                
+                  0
+                  Cold start
+                  #0
+                
+                
+                  1
+                  Warm start
+                  #1
+                
+              
+            
+          
+        
+        
+          LVCMPCR
+          Voltage Monitor Circuit Control Register
+          0x417
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LVD2E
+              Voltage Detection 2 Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Voltage detection 2 circuit disabled
+                  #0
+                
+                
+                  1
+                  Voltage detection 2 circuit enabled
+                  #1
+                
+              
+            
+            
+              LVD1E
+              Voltage Detection 1 Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Voltage detection 1 circuit disabled
+                  #0
+                
+                
+                  1
+                  Voltage detection 1 circuit enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          LVDLVLR
+          Voltage Detection Level Select Register
+          0x418
+          8
+          read-write
+          0xF3
+          0xFF
+          
+            
+              LVD2LVL
+              Voltage Detection 2 Level Select (Standard voltage during fall in voltage)
+              5
+              7
+              read-write
+              
+                
+                  101
+                  2.99V (Vdet2_1)
+                  #101
+                
+                
+                  110
+                  2.92V (Vdet2_2)
+                  #110
+                
+                
+                  111
+                  2.85V (Vdet2_3)
+                  #111
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+            
+              LVD1LVL
+              Voltage Detection 1 Level Select (Standard voltage during fall in voltage)
+              0
+              4
+              read-write
+              
+                
+                  10001
+                  2.99V  (Vdet1_1)
+                  #10001
+                
+                
+                  10010
+                  2.92V (Vdet1_2)
+                  #10010
+                
+                
+                  10011
+                  2.85V  (Vdet1_3)
+                  #10011
+                
+                
+                  others
+                  Settings other than above are prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          2
+          0x1
+          1,2
+          LVD%sCR0
+          Voltage Monitor %s Circuit Control Register 0
+          0x41A
+          8
+          read-write
+          0x8A
+          0xF7
+          
+            
+              RN
+              Voltage Monitor Reset Negate Select
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Negation follows a stabilization time (tLVD) after VCC > Vdet is detected.
+                  #0
+                
+                
+                  1
+                  Negation follows a stabilization time (tLVD) after assertion of the LVD reset.
+                  #1
+                
+              
+            
+            
+              RI
+              Voltage Monitor Circuit Mode Select
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Voltage Monitor  interrupt during Vdet1 passage
+                  #0
+                
+                
+                  1
+                  Voltage Monitor  reset enabled when the voltage falls to and below Vdet1
+                  #1
+                
+              
+            
+            
+              FSAMP
+              Sampling Clock Select
+              4
+              5
+              read-write
+              
+                
+                  00
+                  1/2 LOCO frequency
+                  #00
+                
+                
+                  01
+                  1/4 LOCO frequency
+                  #01
+                
+                
+                  10
+                  1/8 LOCO frequency
+                  #10
+                
+                
+                  11
+                  1/16 LOCO frequency
+                  #11
+                
+              
+            
+            
+              CMPE
+              Voltage Monitor Circuit Comparison Result Output Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disable voltage monitor 1 circuit comparison result output
+                  #0
+                
+                
+                  1
+                  Enable voltage monitor 1 circuit comparison result output.
+                  #1
+                
+              
+            
+            
+              DFDIS
+              Voltage Monitor Digital Filter Disable Mode Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Enable digital filter
+                  #0
+                
+                
+                  1
+                  Disable digital filter
+                  #1
+                
+              
+            
+            
+              RIE
+              Voltage Monitor Interrupt/Reset Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable
+                  #0
+                
+                
+                  1
+                  Enable
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTCR1
+          VBATT Control Register1
+          0x41F
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              BPWSWSTP
+              Battery Power supply Switch Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Battery Power supply Switch Enable
+                  #0
+                
+                
+                  1
+                  Battery Power supply Switch stop
+                  #1
+                
+              
+            
+          
+        
+        
+          SOSCCR
+          Sub-Clock Oscillator Control Register
+          0x480
+          8
+          read-write
+          0x01
+          0xFF
+          
+            
+              SOSTP
+              Sub-Clock Oscillator Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Sub-clock oscillator is operating.
+                  #0
+                
+                
+                  1
+                  Sub-clock oscillator is stopped.
+                  #1
+                
+              
+            
+          
+        
+        
+          SOMCR
+          Sub Clock Oscillator Mode Control Register
+          0x481
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              SODRV
+              Sub-Clock Oscillator Drive Capability Switching
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Normal mode
+                  #00
+                
+                
+                  01
+                  Low power mode 1
+                  #01
+                
+                
+                  10
+                  Low power mode 2
+                  #10
+                
+                
+                  11
+                  Low power mode 3.
+                  #11
+                
+              
+            
+          
+        
+        
+          LOCOCR
+          Low-Speed On-Chip Oscillator Control Register
+          0x490
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LCSTP
+              LOCO Stop
+              0
+              0
+              read-write
+              
+                
+                  0
+                  LOCO is operating.
+                  #0
+                
+                
+                  1
+                  LOCO is stopped.
+                  #1
+                
+              
+            
+          
+        
+        
+          LOCOUTCR
+          LOCO User Trimming Control Register
+          0x492
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              LOCOUTRM
+              LOCO User Trimming  1000_0000 : -128   1000_0001 : -127   1000_0010 : -126   . . .  1111_1111 : -1  0000_0000 : Center Code  0000_0001 : +1  . . .  0111_1101 : +125  0111_1110 : +126  0111_1111 : +127These bits are added to original LOCO trimming bits
+              0
+              7
+              read-write
+            
+          
+        
+        
+          VBTCR2
+          VBATT Control Register2
+          0x4B0
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VBTLVDLVL
+              VBATT Pin Voltage Low Voltage Detect Level Select Bit
+              6
+              7
+              read-write
+              
+                
+                  00
+                  2.7V
+                  #00
+                
+                
+                  01
+                  Setting prohibited
+                  #01
+                
+                
+                  10
+                  2.3V
+                  #10
+                
+                
+                  11
+                  2.1V
+                  #11
+                
+              
+            
+            
+              VBTLVDEN
+              VBATT Pin Low Voltage Detect Enable Bit
+              4
+              4
+              read-write
+              
+                
+                  0
+                  VBATT pin low voltage detect disable
+                  #0
+                
+                
+                  1
+                  VBATT pin low voltage detect enable 
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTSR
+          VBATT Status Register
+          0x4B1
+          8
+          read-write
+          0x01
+          0xEC
+          
+            
+              VBTRVLD
+              VBATT_R Valid
+              4
+              4
+              read-only
+              
+                
+                  0
+                  VBATT_R area not valid
+                  #0
+                
+                
+                  1
+                  VBATT_R area valid
+                  #1
+                
+              
+            
+            
+              VBTBLDF
+              VBATT Battery Low voltage Detect Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  VBATT pin low voltage not detected
+                  #0
+                
+                
+                  1
+                  VBATT pin low voltage detected.
+                  #1
+                
+              
+            
+            
+              VBTRDF
+              VBAT_R Reset Detect Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  VBATT_R voltage power-on reset not detected
+                  #0
+                
+                
+                  1
+                  VBATT_R selected voltage power-on reset detected.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTCMPCR
+          VBATT Comparator Control Register
+          0x4B2
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VBTCMPE
+              VBATT pin low voltage detect circuit output enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATT pin low voltage detect circuit output disabled
+                  #0
+                
+                
+                  1
+                  VBATT pin low voltage detect circuit output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTLVDICR
+          VBATT Pin Low Voltage Detect Interrupt Control Register
+          0x4B4
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VBTLVDISEL
+              Pin Low Voltage Detect Interrupt Select bit
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Non Maskable Interrupt 
+                  #0
+                
+                
+                  1
+                  Maskable Interrupt 
+                  #1
+                
+              
+            
+            
+              VBTLVDIE
+              VBATT Pin Low Voltage Detect Interrupt Enable bit
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATT Pin Low Voltage Detect Interrupt Disable
+                  #0
+                
+                
+                  1
+                  VBATT Pin Low Voltage Detect Interrupt Enable 
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWCTLR
+          VBATT Wakeup function Control Register
+          0x4B6
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VWEN
+              VBATT wakeup enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disable Wakeup function 
+                  #0
+                
+                
+                  1
+                  Enable Wakeup function
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWCH0OTSR
+          VBATT Wakeup I/O 0 Output Trigger Select Register
+          0x4B8
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CH0VAGTUTE
+              CH0 Output AGT(ch1) underflow  Signal Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is enabled
+                  #1
+                
+              
+            
+            
+              CH0VRTCATE
+              VBATWIO0 Output RTC Alarm Signal Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled.
+                  #1
+                
+              
+            
+            
+              CH0VRTCTE
+              VBATWIO0 Output RTC Periodic Signal Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled.
+                  #1
+                
+              
+            
+            
+              CH0VCH2TE
+              VBATWIO0 Output VBATWIO2 Trigger Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled.
+                  #1
+                
+              
+            
+            
+              CH0VCH1TE
+              VBATWIO0 Output VBATWIO1 Trigger Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWCH1OTSR
+          VBATT Wakeup I/O 1 Output Trigger Select Register
+          0x4B9
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CH1VAGTUTE
+              CH1 Output AGT(ch1) underflow  Signal Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is enabled
+                  #1
+                
+              
+            
+            
+              CH1VRTCATE
+              VBATWIO1 Output RTC Alarm Signal Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled.
+                  #1
+                
+              
+            
+            
+              CH1VRTCTE
+              VBATWIO1 Output RTC Periodic Signal Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled
+                  #1
+                
+              
+            
+            
+              CH1VCH2TE
+              VBATWIO1 Output VBATWIO2 Trigger Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled.
+                  #1
+                
+              
+            
+            
+              CH1VCH0TE
+              VBATWIO1 Output VBATWIO0 Trigger Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWCH2OTSR
+          VBATT Wakeup I/O 2 Output Trigger Select Register
+          0x4BA
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              CH2VAGTUTE
+              CH2 Output AGT(CH2) underflow  Signal Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is enabled
+                  #1
+                
+              
+            
+            
+              CH2VRTCATE
+              VBATWIO2 Output RTC Alarm Signal Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled.
+                  #1
+                
+              
+            
+            
+              CH2VRTCTE
+              VBATWIO2 Output RTC Periodic Signal Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled.
+                  #1
+                
+              
+            
+            
+              CH2VCH1TE
+              VBATWIO2 Output VBATWIO1 Trigger Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled.
+                  #1
+                
+              
+            
+            
+              CH2VCH0TE
+              VBATWIO2 Output VBATWIO0 Trigger Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTICTLR
+          VBATT Input Control Register
+          0x4BB
+          8
+          read-write
+          0x00
+          0xF8
+          
+            
+              VCH2INEN
+              RTCIC2 Input Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              VCH1INEN
+              RTCIC1 Input Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              VCH0INEN
+              RTCIC0 Input Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTOCTLR
+          VBATT Output Control Register
+          0x4BC
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VOUT2LSEL
+              VBATT Wakeup I/O 2 Output Level Selection
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Output L before VBATT wake up trigger
+                  #0
+                
+                
+                  1
+                  Output H before VBATT wake up trigger
+                  #1
+                
+              
+            
+            
+              VCOU1LSEL
+              VBATT Wakeup I/O 1 Output Level Selection
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Output L before VBATT wake up trigger
+                  #0
+                
+                
+                  1
+                  Output H before VBATT wake up trigger
+                  #1
+                
+              
+            
+            
+              VOUT0LSEL
+              VBATT Wakeup I/O 0 Output Level Selection
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Output L before VBATT wakeup trigger
+                  #0
+                
+                
+                  1
+                  Output H before VBATT wakeup trigger
+                  #1
+                
+              
+            
+            
+              VCH2OEN
+              VBATT Wakeup I/O 2 Output Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  VBATWIO2 output disabled
+                  #0
+                
+                
+                  1
+                  VBATWIO2 output enabled
+                  #1
+                
+              
+            
+            
+              VCH1OEN
+              VBATT Wakeup I/O 1 Output Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  VBATWIO1 output disabled
+                  #0
+                
+                
+                  1
+                  VBATWIO1 output enabled
+                  #1
+                
+              
+            
+            
+              VCH0OEN
+              VBATT Wakeup I/O 0 Output Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATWIO0 output disabled
+                  #0
+                
+                
+                  1
+                  VBATWIO0 output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWTER
+          VBATT Wakeup Trigger source Enable Register
+          0x4BD
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VAGTUE
+              AGT(ch1) underflow  Signal Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by the AGT(ch1) underflow signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by the AGT(ch1) underflow  signal is enabled
+                  #1
+                
+              
+            
+            
+              VRTCAE
+              RTC Alarm Signal Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by RTC alarm signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by RTC alarm signal is enabled.
+                  #1
+                
+              
+            
+            
+              VRTCIE
+              RTC Periodic Signal Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by RTC periodic signal is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by RTC periodic signal is enabled.
+                  #1
+                
+              
+            
+            
+              VCH2E
+              VBATWIO2 Pin Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by the VBATWIO2 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by the VBATWIO2 pin is enabled.
+                  #1
+                
+              
+            
+            
+              VCH1E
+              VBATWIO1 Pin Enable
+              1
+              1
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by the VBATWIO1 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by the VBATWIO1 pin is enabled.
+                  #1
+                
+              
+            
+            
+              VCH0E
+              VBATWIO0 Pin Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  VBATT wakeup triggered by the VBATWIO0 pin is disabled
+                  #0
+                
+                
+                  1
+                  VBATT wakeup triggered by the VBATWIO0 pin is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWEGR
+          VBATT Wakeup Trigger source Edge Register
+          0x4BE
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VCH2EG
+              VBATWIO2 Wakeup Trigger Source Edge Select
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Wakeup trigger is generated at a falling edge
+                  #0
+                
+                
+                  1
+                  Wakeup trigger is generated at a rising edge.
+                  #1
+                
+              
+            
+            
+              VCH1EG
+              VBATWIO1 Wakeup Trigger Source Edge Select
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Wakeup trigger is generated at a falling edge
+                  #0
+                
+                
+                  1
+                  Wakeup trigger is generated at a rising edge.
+                  #1
+                
+              
+            
+            
+              VCH0EG
+              VBATWIO0 Wakeup Trigger Source Edge Select
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Wakeup trigger is generated at a falling edge
+                  #0
+                
+                
+                  1
+                  Wakeup trigger is generated at a rising edge.
+                  #1
+                
+              
+            
+          
+        
+        
+          VBTWFR
+          VBATT Wakeup trigger source Flag Register
+          0x4BF
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              VAGTUF
+              AGT(ch1) underflow   VBATT Wakeup Trigger Flag
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the AGT(ch1) underflow  is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the AGT(ch1) underflow  is generated
+                  #1
+                
+              
+            
+            
+              VRTCAF
+              VBATT RTC-Alarm Wakeup Trigger Flag
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the RTC alarm is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the RTC alarm is generated
+                  #1
+                
+              
+            
+            
+              VRTCIF
+              VBATT RTC-Interval  Wakeup Trigger Flag
+              3
+              3
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the RTC interval is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the RTC interval is generated
+                  #1
+                
+              
+            
+            
+              VCH2F
+              VBATWIO2 Wakeup Trigger Flag
+              2
+              2
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the VBATWIO2 pin is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the VBATWIO2 pin is generated
+                  #1
+                
+              
+            
+            
+              VCH1F
+              VBATWIO1 Wakeup Trigger Flag
+              1
+              1
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the VBATWIO1 pin is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the VBATWIO1 pin is generated
+                  #1
+                
+              
+            
+            
+              VCH0F
+              VBATWIO0 Wakeup Trigger Flag
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No wakeup trigger by the VBATWIO0 pin is generated
+                  #0
+                
+                
+                  1
+                  A wakeup trigger by the VBATWIO0 pin is generated
+                  #1
+                
+              
+            
+          
+        
+        
+          512
+          0x1
+          VBTBKR[%s]
+          VBATT Backup Register [%s]
+          0x500
+          8
+          read-write
+          0x00
+          0x00
+          
+            
+              VBTBKR
+              VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          FWEPROR
+          Flash P/E Protect Register
+          0x416
+          8
+          read-write
+          0x02
+          0xFF
+          
+            
+              FLWE
+              Flash Programming and Erasure
+              0
+              1
+              read-write
+              
+                
+                  00
+                  Prohibits programming and erasure of the code flash, data flash or blank checking.
+                  #00
+                
+                
+                  01
+                  Permits programming and erasure of the code flash, data flash or blank checking.
+                  #01
+                
+                
+                  10
+                  Prohibits programming and erasure of the code flash, data flash or blank checking.
+                  #10
+                
+                
+                  11
+                  Prohibits programming and erasure of the code flash, data flash or blank checking.
+                  #11
+                
+              
+            
+          
+        
+      
+    
+    
+      R_TSN
+      Temperature Sensor
+      0x407EC000
+      
+        0x00000228
+        0x002
+        registers
+      
+      
+        
+          TSCDRH
+          Temperature Sensor Calibration Data Register H
+          0x229
+          8
+          read-only
+          0x00
+          0x00
+          
+            
+              TSCDRH
+              The calibration data stores the higher 8 bits of the convertedvalue.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          TSCDRL
+          Temperature Sensor Calibration Data Register L
+          0x228
+          8
+          read-only
+          0x00
+          0x00
+          
+            
+              TSCDRL
+              The calibration data stores the lower 8 bits of the convertedvalue.
+              0
+              7
+              read-only
+            
+          
+        
+      
+    
+    
+      R_TSN_CTRL
+      Temperature Sensor
+      0x4005D000
+      
+        0x00
+        1
+        registers
+      
+      
+        
+          TSCR
+          Temperature Sensor Control Register
+          0x00
+          8
+          read-write
+          0x00
+          0xFF
+          
+            
+              TSEN
+              Temperature Sensor Output Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Stops the temperature sensor.
+                  #0
+                
+                
+                  1
+                  Starts the temperature sensor.
+                  #1
+                
+              
+            
+            
+              TSOE
+              Temperature Sensor Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disables output from the temperature sensor to the 12-bit A/D converter.
+                  #0
+                
+                
+                  1
+                  Enables output from the temperature sensor to the 12-bit A/D converter.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_USB_FS0
+      USB 2.0 Module
+      0x40090000
+      
+        0x00000000
+        0x00A
+        registers
+      
+      
+        0x0000000C
+        0x02
+        registers
+      
+      
+        0x00000014
+        0x010
+        registers
+      
+      
+        0x00000028
+        0x00C
+        registers
+      
+      
+        0x00000036
+        0x00E
+        registers
+      
+      
+        0x00000046
+        0x00C
+        registers
+      
+      
+        0x00000054
+        0x00E
+        registers
+      
+      
+        0x00000064
+        0x02
+        registers
+      
+      
+        0x00000068
+        0x02
+        registers
+      
+      
+        0x0000006C
+        0x016
+        registers
+      
+      
+        0x00000090
+        0x014
+        registers
+      
+      
+        0x000000B0
+        0x02
+        registers
+      
+      
+        0x000000C4
+        0x02
+        registers
+      
+      
+        0x000000CC
+        0x02
+        registers
+      
+      
+        0x000000D0
+        0x014
+        registers
+      
+      
+        0x000000F0
+        0x04
+        registers
+      
+      
+        0x00000100
+        0x004
+        registers
+      
+      
+        0x00000140
+        0x02
+        registers
+      
+      
+        0x00000144
+        0x008
+        registers
+      
+      
+        0x00000160
+        0x00C
+        registers
+      
+      
+        0x00000400
+        0x008
+        registers
+      
+      
+        
+          5
+          0x004
+          PIPE_TR[%s]
+          Pipe Transaction Counter Registers
+          0x090
+          
+            E
+            Pipe Transaction Counter Enable Register
+            0x00
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                TRENB
+                Transaction Counter Enable
+                9
+                9
+                read-write
+                
+                  
+                    0
+                    Transaction counter is disabled.
+                    #0
+                  
+                  
+                    1
+                    Transaction counter is enabled.
+                    #1
+                  
+                
+              
+              
+                TRCLR
+                Transaction Counter Clear
+                8
+                8
+                read-write
+                
+                  
+                    0
+                    Invalid
+                    #0
+                  
+                  
+                    1
+                    The current counter value is cleared.
+                    #1
+                  
+                
+              
+            
+          
+          
+            N
+            Pipe Transaction Counter Register
+            0x02
+            16
+            read-write
+            0x0000
+            0xFFFF
+            
+              
+                TRNCNT
+                Transaction Counter
+                0
+                15
+                read-write
+              
+            
+          
+        
+        
+          SYSCFG
+          System Configuration Control Register
+          0x000
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              SCKE
+              USB Clock Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Clock supply to the USBFS stopped
+                  #0
+                
+                
+                  1
+                  Clock supply to the USBFS enabled.
+                  #1
+                
+              
+            
+            
+              CNEN
+              CNEN Single End Receiver Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Single end receiver disabled
+                  #0
+                
+                
+                  1
+                  Single end receiver enabled
+                  #1
+                
+              
+            
+            
+              DCFM
+              Controller Function Select
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Device controller selected
+                  #0
+                
+                
+                  1
+                  Host controller selected.
+                  #1
+                
+              
+            
+            
+              DRPD
+              D+/D- Line Resistor Control
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Line pull-down disabled
+                  #0
+                
+                
+                  1
+                  Line pull-down enabled.
+                  #1
+                
+              
+            
+            
+              DPRPU
+              D+ Line Resistor Control
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Line pull-down disabled
+                  #0
+                
+                
+                  1
+                  Line pull-down enabled.
+                  #1
+                
+              
+            
+            
+              DMRPU
+              D- Line Resistor Control 
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Line pull-up disabled
+                  #0
+                
+                
+                  1
+                  Line pull-up enabled.
+                  #1
+                
+              
+            
+            
+              USBE
+              USB Operation Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          BUSWAIT
+          CPU Bus Wait Register
+          0x002
+          16
+          read-write
+          0x000F
+          0x3F3F
+          
+            
+              BWAIT
+              CPU Bus Access Wait Specification     BWAIT waits (BWAIT+2 access cycles)
+              0
+              3
+              read-write
+              
+                
+                  BWAIT
+                  BWAIT wait(s) ( BWAIT + 2 access cycles )
+                  true
+                
+              
+            
+          
+        
+        
+          SYSSTS0
+          System Configuration Status Register 0 
+          0x004
+          16
+          read-only
+          0x0000
+          0x0000
+          
+            
+              OVCMON
+              External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.
+              14
+              15
+              read-only
+            
+            
+              HTACT
+              USB Host Sequencer Status Monitor
+              6
+              6
+              read-only
+              
+                
+                  0
+                  Host sequencer completely stopped
+                  #0
+                
+                
+                  1
+                  Host sequencer not completely stopped.
+                  #1
+                
+              
+            
+            
+              SOFEA
+              SOF Active Monitor While Host Controller Function is Selected.
+              5
+              5
+              read-only
+              
+                
+                  0
+                  SOF output is stopped.
+                  #0
+                
+                
+                  1
+                  SOF output is operating.
+                  #1
+                
+              
+            
+            
+              IDMON
+              External ID0 Input Pin Monitor
+              2
+              2
+              read-only
+              
+                
+                  0
+                  USB0_ID pin is low
+                  #0
+                
+                
+                  1
+                  USB0_ID pin is high
+                  #1
+                
+              
+            
+            
+              LNST
+              USB Data Line Status Monitor
+              0
+              1
+              read-only
+              
+                
+                  00
+                  SE0 
+                  #00
+                
+                
+                  01
+                  K-State (FS) / J-State(LS)  
+                  #01
+                
+                
+                  10
+                  J-State(FS) / K-State(LS)
+                  #10
+                
+                
+                  11
+                  SE1
+                  #11
+                
+              
+            
+          
+        
+        
+          PLLSTA
+          PLL Status Register
+          0x006
+          16
+          read-only
+          0x0000
+          0x0001
+          
+            
+              PLLLOCK
+              PLL Lock Flag
+              0
+              0
+              read-only
+              
+                
+                  0
+                  PLL is not locked.
+                  #0
+                
+                
+                  1
+                  PLL is locked.
+                  #1
+                
+              
+            
+          
+        
+        
+          DVSTCTR0
+          Device State Control Register 0
+          0x008
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              HNPBTOA
+              Host Negotiation Protocol (HNP) Control     This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even  though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Normal Operation
+                  #0
+                
+                
+                  1
+                  Switching from device B to device A is enabled
+                  #1
+                
+              
+            
+            
+              EXICEN
+              USB_EXICEN Output Pin Control
+              10
+              10
+              read-write
+              
+                
+                  0
+                  External USB_EXICEN pin outputs low
+                  #0
+                
+                
+                  1
+                  External USB_EXICEN pin outputs high
+                  #1
+                
+              
+            
+            
+              VBUSEN
+              USB_VBUSEN Output Pin Control
+              9
+              9
+              read-write
+              
+                
+                  0
+                  External USB_VBUSEN pin outputs low
+                  #0
+                
+                
+                  1
+                  External USB_VBUSEN pin outputs high
+                  #1
+                
+              
+            
+            
+              WKUP
+              Wakeup Output
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Remote wakeup signal is not output.
+                  #0
+                
+                
+                  1
+                  Remote wakeup signal is output.
+                  #1
+                
+              
+            
+            
+              RWUPE
+              Wakeup Detection Enable
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Downstream port wakeup is disabled.
+                  #0
+                
+                
+                  1
+                  Downstream port wakeup is enabled.
+                  #1
+                
+              
+            
+            
+              USBRST
+              USB Bus Reset Output
+              6
+              6
+              read-write
+              
+                
+                  0
+                  USB bus reset signal is not output.
+                  #0
+                
+                
+                  1
+                  USB bus reset signal is output.
+                  #1
+                
+              
+            
+            
+              RESUME
+              Resume Output
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Resume signal is not output.
+                  #0
+                
+                
+                  1
+                  Resume signal is output.
+                  #1
+                
+              
+            
+            
+              UACT
+              USB Bus Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Downstream port is disabled (SOF transmission is disabled).
+                  #0
+                
+                
+                  1
+                  Downstream port is enabled (SOF transmission is enabled).
+                  #1
+                
+              
+            
+            
+              RHST
+              USB Bus Reset Status
+              0
+              2
+              read-only
+              
+                
+                  000
+                  Communication speed not determined
+                  #000
+                
+                
+                  001
+                  Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)
+                  #001
+                
+                
+                  010
+                  Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)
+                  #010
+                
+                
+                  011
+                  Setting prohibited
+                  #011
+                
+                
+                  others
+                  USB bus reset in progress(When the host controller function is selected)
+                  true
+                
+              
+            
+          
+        
+        
+          TESTMODE
+          USB Test Mode Register 
+          0x00C
+          16
+          read-write
+          0x0000
+          0x000F
+          
+            
+              UTST
+              Test Mode
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  Normal operation
+                  #0000
+                
+                
+                  0001
+                  Test_J TestMode(When the Function Controller Function is Selected)
+                  #0001
+                
+                
+                  0010
+                  Test_K TestMode(When the Function Controller Function is Selected)
+                  #0010
+                
+                
+                  0011
+                  Test_SE0_NAK TestMode(When the Function Controller Function is Selected)
+                  #0011
+                
+                
+                  0100
+                  Test_Packet TestMode(When the Function Controller Function is Selected)
+                  #0100
+                
+                
+                  0101
+                  Reserved TestMode(When the Function Controller Function is Selected)
+                  #0101
+                
+                
+                  0110
+                  Reserved TestMode(When the Function Controller Function is Selected)
+                  #0110
+                
+                
+                  0111
+                  Reserved TestMode(When the Function Controller Function is Selected)
+                  #0111
+                
+                
+                  1001
+                  Test_J TestMode(When the Host Controller Function is Selected)
+                  #1001
+                
+                
+                  1010
+                  Test_K TestMode(When the Host Controller Function is Selected)
+                  #1010
+                
+                
+                  1011
+                  Test_SE0_NAK TestMode(When the Host Controller Function is Selected)
+                  #1011
+                
+                
+                  1100
+                  Test_Packet TestMode(When the Host Controller Function is Selected)
+                  #1100
+                
+                
+                  1101
+                  Test_Force_EnableTestMode(When the Host Controller Function is Selected)
+                  #1101
+                
+                
+                  1110
+                  Reserved TestMode(When the Host Controller Function is Selected)
+                  #1110
+                
+                
+                  1111
+                  Reserved TestMode(When the Host Controller Function is Selected)
+                  #1111
+                
+              
+            
+          
+        
+        
+          CFIFOL
+          CFIFO Port Register L
+          0x014
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          CFIFOLL
+          CFIFO Port Register LL
+          CFIFOL
+          0x014
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          CFIFO
+          CFIFO Port Register
+          CFIFOL
+          0x014
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+        
+        
+          CFIFOH
+          CFIFO Port Register H
+          CFIFO
+          0x016
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          CFIFOHH
+          CFIFO Port Register HH
+          CFIFOH
+          0x017
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          D0FIFOL
+          D0FIFO Port Register L
+          0x018
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          D0FIFOLL
+          D0FIFO Port Register LL
+          D0FIFOL
+          0x018
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          D0FIFO
+          D0FIFO Port Register
+          D0FIFOL
+          0x018
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+        
+        
+          D0FIFOH
+          D0FIFO Port Register H
+          D0FIFO
+          0x01A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          D0FIFOHH
+          D0FIFO Port Register HH
+          D0FIFOH
+          0x01B
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          D1FIFOL
+          D1FIFO Port Register L
+          0x01C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          D1FIFOLL
+          D1FIFO Port Register LL
+          D1FIFOL
+          0x01C
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          D1FIFO
+          D1FIFO Port Register
+          D1FIFOL
+          0x01C
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+        
+        
+          D1FIFOH
+          D1FIFO Port Register H
+          D1FIFO
+          0x01E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+        
+        
+          D1FIFOHH
+          D1FIFO Port Register HH
+          D1FIFOH
+          0x01F
+          8
+          read-write
+          0x00
+          0xFF
+          
+        
+        
+          CFIFOSEL
+          CFIFO Port Select Register
+          0x020
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              RCNT
+              Read Count Mode
+              15
+              15
+              read-write
+              
+                
+                  0
+                  The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.)
+                  #0
+                
+                
+                  1
+                  The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.
+                  #1
+                
+              
+            
+            
+              REW
+              Buffer Pointer Rewind
+              14
+              14
+              read-write
+              
+                
+                  0
+                  The buffer pointer is not rewound.
+                  #0
+                
+                
+                  1
+                  The buffer pointer is rewound.
+                  #1
+                
+              
+            
+            
+              MBW
+              CFIFO Port Access Bit Width
+              10
+              11
+              read-write
+              
+                
+                  0
+                  8-bit width
+                  0
+                
+                
+                  1
+                  16-bit width
+                  1
+                
+                
+                  2
+                  32-bit width
+                  2
+                
+              
+            
+            
+              BIGEND
+              CFIFO Port Endian Control
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Little endian
+                  #0
+                
+                
+                  1
+                  Big endian
+                  #1
+                
+              
+            
+            
+              ISEL
+              CFIFO Port Access Direction When DCP is Selected
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Reading from the buffer memory is selected
+                  #0
+                
+                
+                  1
+                  Writing to the buffer memory is selected
+                  #1
+                
+              
+            
+            
+              CURPIPE
+              CFIFO Port Access Pipe Specification
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  DCP (Default control pipe)
+                  #0000
+                
+                
+                  0001
+                  Pipe 1
+                  #0001
+                
+                
+                  0010
+                  Pipe 2
+                  #0010
+                
+                
+                  0011
+                  Pipe 3
+                  #0011
+                
+                
+                  0100
+                  Pipe 4
+                  #0100
+                
+                
+                  0101
+                  Pipe 5
+                  #0101
+                
+                
+                  0110
+                  Pipe 6
+                  #0110
+                
+                
+                  0111
+                  Pipe 7
+                  #0111
+                
+                
+                  1000
+                  Pipe 8
+                  #1000
+                
+                
+                  1001
+                  Pipe 9
+                  #1001
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          CFIFOCTR
+          CFIFO Port Control Register
+          0x022
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              BVAL
+              Buffer Memory Valid Flag
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Writing ended
+                  #1
+                
+              
+            
+            
+              BCLR
+              CPU Buffer ClearNote: Only 0 can be read.
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Does not operate
+                  #0
+                
+                
+                  1
+                  FIFO buffer cleared on the CPU side.
+                  #1
+                
+              
+            
+            
+              FRDY
+              FIFO Port Ready
+              13
+              13
+              read-only
+              
+                
+                  0
+                  FIFO port access is disabled.
+                  #0
+                
+                
+                  1
+                  FIFO port access is enabled.
+                  #1
+                
+              
+            
+            
+              DTLN
+              Receive Data LengthIndicates the length of the receive data.
+              0
+              11
+              read-only
+            
+          
+        
+        
+          D0FIFOSEL
+          D0FIFO Port Select Register
+          0x028
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              RCNT
+              Read Count Mode
+              15
+              15
+              read-write
+              
+                
+                  0
+                  The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
+                  #0
+                
+                
+                  1
+                  The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
+                  #1
+                
+              
+            
+            
+              REW
+              Buffer Pointer RewindNote: Only 0 can be read.
+              14
+              14
+              read-write
+              
+                
+                  0
+                  The buffer pointer is not rewound.
+                  #0
+                
+                
+                  1
+                  The buffer pointer is rewound.
+                  #1
+                
+              
+            
+            
+              DCLRM
+              Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Auto buffer clear mode is disabled.
+                  #0
+                
+                
+                  1
+                  Auto buffer clear mode is enabled.
+                  #1
+                
+              
+            
+            
+              DREQE
+              DMA/DTC Transfer Request Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  DMA/DTC transfer request is disabled.
+                  #0
+                
+                
+                  1
+                  DMA/DTC transfer request is enabled.
+                  #1
+                
+              
+            
+            
+              MBW
+              FIFO Port Access Bit Width
+              10
+              11
+              read-write
+              
+                
+                  0
+                  8-bit width
+                  0
+                
+                
+                  1
+                  16-bit width
+                  1
+                
+                
+                  2
+                  32-bit width
+                  2
+                
+              
+            
+            
+              BIGEND
+              FIFO Port Endian Control
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Little endian
+                  #0
+                
+                
+                  1
+                  Big endian
+                  #1
+                
+              
+            
+            
+              CURPIPE
+              FIFO Port Access Pipe Specification
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  DCP (Default control pipe)
+                  #0000
+                
+                
+                  0001
+                  Pipe 1
+                  #0001
+                
+                
+                  0010
+                  Pipe 2
+                  #0010
+                
+                
+                  0011
+                  Pipe 3
+                  #0011
+                
+                
+                  0100
+                  Pipe 4
+                  #0100
+                
+                
+                  0101
+                  Pipe 5
+                  #0101
+                
+                
+                  0110
+                  Pipe 6
+                  #0110
+                
+                
+                  0111
+                  Pipe 7
+                  #0111
+                
+                
+                  1000
+                  Pipe 8
+                  #1000
+                
+                
+                  1001
+                  Pipe 9
+                  #1001
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          D0FIFOCTR
+          D0FIFO Port Control Register
+          0x02A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              BVAL
+              Buffer Memory Valid Flag
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Writing ended
+                  #1
+                
+              
+            
+            
+              BCLR
+              CPU Buffer ClearNote: Only 0 can be read.
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Does not operate
+                  #0
+                
+                
+                  1
+                  FIFO buffer cleared on the CPU side.
+                  #1
+                
+              
+            
+            
+              FRDY
+              FIFO Port Ready
+              13
+              13
+              read-only
+              
+                
+                  0
+                  FIFO port access is disabled.
+                  #0
+                
+                
+                  1
+                  FIFO port access is enabled.
+                  #1
+                
+              
+            
+            
+              DTLN
+              Receive Data LengthIndicates the length of the receive data.
+              0
+              11
+              read-only
+            
+          
+        
+        
+          D1FIFOSEL
+          D1FIFO Port Select Register
+          0x02C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              RCNT
+              Read Count Mode
+              15
+              15
+              read-write
+              
+                
+                  0
+                  The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
+                  #0
+                
+                
+                  1
+                  The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
+                  #1
+                
+              
+            
+            
+              REW
+              Buffer Pointer Rewind
+              14
+              14
+              read-write
+              
+                
+                  0
+                  The buffer pointer is not rewound.
+                  #0
+                
+                
+                  1
+                  The buffer pointer is rewound.
+                  #1
+                
+              
+            
+            
+              DCLRM
+              Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Auto buffer clear mode is disabled.
+                  #0
+                
+                
+                  1
+                  Auto buffer clear mode is enabled.
+                  #1
+                
+              
+            
+            
+              DREQE
+              DMA/DTC Transfer Request Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  DMA/DTC transfer request is disabled.
+                  #0
+                
+                
+                  1
+                  DMA/DTC transfer request is enabled.
+                  #1
+                
+              
+            
+            
+              MBW
+              FIFO Port Access Bit Width
+              10
+              11
+              read-write
+              
+                
+                  0
+                  8-bit width
+                  0
+                
+                
+                  1
+                  16-bit width
+                  1
+                
+                
+                  2
+                  32-bit width
+                  2
+                
+              
+            
+            
+              BIGEND
+              FIFO Port Endian Control
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Little endian
+                  #0
+                
+                
+                  1
+                  Big endian
+                  #1
+                
+              
+            
+            
+              CURPIPE
+              FIFO Port Access Pipe Specification
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  DCP (Default control pipe)
+                  #0000
+                
+                
+                  0001
+                  Pipe 1
+                  #0001
+                
+                
+                  0010
+                  Pipe 2
+                  #0010
+                
+                
+                  0011
+                  Pipe 3
+                  #0011
+                
+                
+                  0100
+                  Pipe 4
+                  #0100
+                
+                
+                  0101
+                  Pipe 5
+                  #0101
+                
+                
+                  0110
+                  Pipe 6
+                  #0110
+                
+                
+                  0111
+                  Pipe 7
+                  #0111
+                
+                
+                  1000
+                  Pipe 8
+                  #1000
+                
+                
+                  1001
+                  Pipe 9
+                  #1001
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          D1FIFOCTR
+          D1FIFO Port Control Register
+          0x02E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              BVAL
+              Buffer Memory Valid Flag
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Writing ended
+                  #1
+                
+              
+            
+            
+              BCLR
+              CPU Buffer ClearNote: Only 0 can be read.
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Does not operate
+                  #0
+                
+                
+                  1
+                  FIFO buffer cleared on the CPU side.
+                  #1
+                
+              
+            
+            
+              FRDY
+              FIFO Port Ready
+              13
+              13
+              read-only
+              
+                
+                  0
+                  FIFO port access is disabled.
+                  #0
+                
+                
+                  1
+                  FIFO port access is enabled.
+                  #1
+                
+              
+            
+            
+              DTLN
+              Receive Data LengthIndicates the length of the receive data.
+              0
+              11
+              read-only
+            
+          
+        
+        
+          INTENB0
+          Interrupt Enable Register 0
+          0x030
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              VBSE
+              VBUS Interrupt Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              RSME
+              Resume Interrupt Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              SOFE
+              Frame Number Update Interrupt Enable
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              DVSE
+              Device State Transition Interrupt Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              CTRE
+              Control Transfer Stage Transition Interrupt Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              BEMPE
+              Buffer Empty Interrupt Enable
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              NRDYE
+              Buffer Not Ready Response Interrupt Enable
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              BRDYE
+              Buffer Ready Interrupt Enable
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          INTENB1
+          Interrupt Enable Register 1 
+          0x032
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              OVRCRE
+              Overcurrent Input Change Interrupt Enable
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              BCHGE
+              USB Bus Change Interrupt Enable
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              DTCHE
+              Disconnection Detection Interrupt Enable
+              12
+              12
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              ATTCHE
+              Connection Detection Interrupt Enable
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              EOFERRE
+              EOF Error Detection Interrupt Enable
+              6
+              6
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              SIGNE
+              Setup Transaction Error Interrupt Enable
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              SACKE
+              Setup Transaction Normal Response Interrupt Enable
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+            
+              PDDETINTE0
+              PDDETINT0 Detection Interrupt Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          BRDYENB
+          BRDY Interrupt Enable Register
+          0x036
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sBRDYE
+              BRDY Interrupt Enable for PIPE
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          NRDYENB
+          NRDY Interrupt Enable Register
+          0x038
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sNRDYE
+              NRDY Interrupt Enable for PIPE
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          BEMPENB
+          BEMP Interrupt Enable Register
+          0x03A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sBEMPE
+              BEMP Interrupt Enable for PIPE
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Interrupt output disabled
+                  #0
+                
+                
+                  1
+                  Interrupt output enabled
+                  #1
+                
+              
+            
+          
+        
+        
+          SOFCFG
+          SOF Output Configuration Register 
+          0x03C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              TRNENSEL
+              Transaction-Enabled Time Select 
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Not low-speed communication
+                  #0
+                
+                
+                  1
+                  Low-speed communication.
+                  #1
+                
+              
+            
+            
+              BRDYM
+              BRDY Interrupt Status Clear Timing
+              6
+              6
+              read-write
+              
+                
+                  0
+                  BRDY flag cleared by software
+                  #0
+                
+                
+                  1
+                  BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer.
+                  #1
+                
+              
+            
+            
+              INTL
+              Interrupt Output Sense Select
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Edge sense
+                  #0
+                
+                
+                  1
+                  Level sense
+                  #1
+                
+              
+            
+            
+              EDGESTS
+              Edge Interrupt Output Status Monitor 
+              4
+              4
+              read-only
+              
+                
+                  0
+                  before stopping the clock supply to the USB module
+                  #0
+                
+                
+                  1
+                  the edge interrupt output signal is in the middle of the edge processing
+                  #1
+                
+              
+            
+          
+        
+        
+          PHYSET
+          PHY Setting Register
+          0x03E
+          16
+          read-write
+          0x0033
+          0x0B3B
+          
+            
+              HSEB
+              CL-Only Mode
+              15
+              15
+              read-write
+              
+                
+                  0
+                  CL-only mode is not activated.
+                  #0
+                
+                
+                  1
+                  CL-only mode is activated.
+                  #1
+                
+              
+            
+            
+              REPSTART
+              Forcibly Start Terminating Resistance Adjustment
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Terminating resistance adjustment is forcibly started
+                  #0
+                
+                
+                  1
+                  Terminating resistance adjustment is not forcibly started
+                  #1
+                
+              
+            
+            
+              REPSEL
+              Terminating Resistance Adjustment Cycle
+              8
+              9
+              read-write
+              
+                
+                  00
+                  No cycle is set.
+                  #00
+                
+                
+                  01
+                  Adjust terminating resistance at 16-second intervals. 
+                  #01
+                
+                
+                  10
+                  Adjust terminating resistance at 64-second intervals.
+                  #10
+                
+                
+                  11
+                  Adjust terminating resistance at 128-second intervals.
+                  #11
+                
+              
+            
+            
+              CLKSEL
+              Input System Clock Frequency
+              4
+              5
+              read-write
+              
+                
+                  00
+                  Setting Prohibited
+                  #00
+                
+                
+                  01
+                  12 MHz
+                  #01
+                
+                
+                  10
+                  20 MHz
+                  #10
+                
+                
+                  11
+                  24 MHz
+                  #11
+                
+              
+            
+            
+              CDPEN
+              Charging Downstream Port Enable
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disable charging downstream port
+                  #0
+                
+                
+                  1
+                  Enable charging downstream port
+                  #1
+                
+              
+            
+            
+              PLLRESET
+              PLL Reset Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disable PLL reset control for UTMI_PHY
+                  #0
+                
+                
+                  1
+                  Enable PLL reset control for UTMI_PHY
+                  #1
+                
+              
+            
+            
+              DIRPD
+              Power-Down Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Does not enter low-power consumption mode
+                  #0
+                
+                
+                  1
+                  Enter low-power consumption mode
+                  #1
+                
+              
+            
+          
+        
+        
+          INTSTS0
+          Interrupt Status Register 0
+          0x040
+          16
+          read-write
+          0x0000
+          0xFF7F
+          
+            
+              VBINT
+              VBUS Interrupt Status
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  VBUS interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  VBUS interrupts are generated.
+                  #1
+                
+              
+            
+            
+              RESM
+              Resume Interrupt Status
+              14
+              14
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Resume interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  Resume interrupts are generated.
+                  #1
+                
+              
+            
+            
+              SOFR
+              Frame Number Refresh Interrupt Status
+              13
+              13
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SOF interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  SOF interrupts are generated.
+                  #1
+                
+              
+            
+            
+              DVST
+              Device State Transition Interrupt Status
+              12
+              12
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Device state transition interrupts are not generated. 
+                  #0
+                
+                
+                  1
+                  Device state transition interrupts are generated.
+                  #1
+                
+              
+            
+            
+              CTRT
+              Control Transfer Stage Transition Interrupt Status
+              11
+              11
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Control transfer stage transition interrupts are not generated. 
+                  #0
+                
+                
+                  1
+                  Control transfer stage transition interrupts are generated.
+                  #1
+                
+              
+            
+            
+              BEMP
+              Buffer Empty Interrupt Status
+              10
+              10
+              read-only
+              
+                
+                  0
+                  BEMP interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  BEMP interrupts are generated.
+                  #1
+                
+              
+            
+            
+              NRDY
+              Buffer Not Ready Interrupt Status
+              9
+              9
+              read-only
+              
+                
+                  0
+                  NRDY interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  NRDY interrupts are generated.
+                  #1
+                
+              
+            
+            
+              BRDY
+              Buffer Ready Interrupt Status
+              8
+              8
+              read-only
+              
+                
+                  0
+                  BRDY interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  BRDY interrupts are generated.
+                  #1
+                
+              
+            
+            
+              VBSTS
+              VBUS Input Status
+              7
+              7
+              read-only
+              
+                
+                  0
+                  USB_VBUS pin is low.
+                  #0
+                
+                
+                  1
+                  USB_VBUS pin is high.
+                  #1
+                
+              
+            
+            
+              DVSQ
+              Device State
+              4
+              6
+              read-only
+              
+                
+                  000
+                  Powered state
+                  #000
+                
+                
+                  001
+                  Default state
+                  #001
+                
+                
+                  010
+                  Address state
+                  #010
+                
+                
+                  011
+                  Configured state
+                  #011
+                
+                
+                  others
+                  Suspended state
+                  true
+                
+              
+            
+            
+              VALID
+              USB Request Reception
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Setup packet is not received
+                  #0
+                
+                
+                  1
+                  Setup packet is received
+                  #1
+                
+              
+            
+            
+              CTSQ
+              Control Transfer Stage
+              0
+              2
+              read-only
+              
+                
+                  000
+                  Idle or setup stage
+                  #000
+                
+                
+                  001
+                  Control read data stage
+                  #001
+                
+                
+                  010
+                  Control read status stage
+                  #010
+                
+                
+                  011
+                  Control write data stage
+                  #011
+                
+                
+                  100
+                  Control write status stage
+                  #100
+                
+                
+                  101
+                  Control write (no data) status stage
+                  #101
+                
+                
+                  110
+                  Control transfer sequence error
+                  #110
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          INTSTS1
+          Interrupt Status Register 1
+          0x042
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              OVRCR
+              Overcurrent Input Change Interrupt Status
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  OVRCR interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  OVRCR interrupts are generated.
+                  #1
+                
+              
+            
+            
+              BCHG
+              USB Bus Change Interrupt Status
+              14
+              14
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  BCHG interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  BCHG interrupts are generated.
+                  #1
+                
+              
+            
+            
+              DTCH
+              USB Disconnection Detection Interrupt Status
+              12
+              12
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  DTCH interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  DTCH interrupts are generated.
+                  #1
+                
+              
+            
+            
+              ATTCH
+              ATTCH Interrupt Status
+              11
+              11
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  ATTCH interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  ATTCH interrupts are generated.
+                  #1
+                
+              
+            
+            
+              L1RSMEND
+              L1 Resume End Interrupt Status
+              9
+              9
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  L1RSMEND interrupts are not generated
+                  #0
+                
+                
+                  1
+                  L1RSMEND interrupts are generated
+                  #1
+                
+              
+            
+            
+              LPMEND
+              LPM Transaction End Interrupt Status
+              8
+              8
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  LPMEND interrupts are not generated
+                  #0
+                
+                
+                  1
+                  LPMEND interrupts are generated
+                  #1
+                
+              
+            
+            
+              EOFERR
+              EOF Error Detection Interrupt Status
+              6
+              6
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  EOFERR interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  EOFERR interrupts are generated.
+                  #1
+                
+              
+            
+            
+              SIGN
+              Setup Transaction Error Interrupt Status
+              5
+              5
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SIGN interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  SIGN interrupts are generated.
+                  #1
+                
+              
+            
+            
+              SACK
+              Setup Transaction Normal Response Interrupt Status
+              4
+              4
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  SACK interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  SACK interrupts are generated.
+                  #1
+                
+              
+            
+            
+              PDDETINT0
+              PDDET0 Detection Interrupt Status
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  PDDET0 detection interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  PDDET0 detection interrupts are generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          BRDYSTS
+          BRDY Interrupt Status Register
+          0x046
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sBRDY
+              BRDY Interrupt Status for PIPE
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  Interrupts are generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          NRDYSTS
+          NRDY Interrupt Status Register
+          0x048
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sNRDY
+              NRDY Interrupt Status for PIPE
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  Interrupts are generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          BEMPSTS
+          BEMP Interrupt Status Register
+          0x04A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              10
+              1
+              PIPE%sBEMP
+              BEMP Interrupt Status for PIPE
+              0
+              0
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  Interrupts are not generated.
+                  #0
+                
+                
+                  1
+                  Interrupts are generated.
+                  #1
+                
+              
+            
+          
+        
+        
+          FRMNUM
+          Frame Number Register
+          0x04C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              OVRN
+              Overrun/Underrun Detection Status
+              15
+              15
+              read-write
+              
+                
+                  0
+                  No error
+                  #0
+                
+                
+                  1
+                  An error occurred
+                  #1
+                
+              
+            
+            
+              CRCE
+              Receive Data Error
+              14
+              14
+              read-write
+              
+                
+                  0
+                  No error
+                  #0
+                
+                
+                  1
+                  An error occurred
+                  #1
+                
+              
+            
+            
+              FRNM
+              Frame NumberLatest frame number
+              0
+              10
+              read-only
+            
+          
+        
+        
+          UFRMNUM
+          uFrame Number Register 
+          0x04E
+          16
+          read-write
+          0x0000
+          0x8007
+          
+            
+              DVCHG
+              Device State Change
+              15
+              15
+              read-write
+              
+                
+                  0
+                  Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].
+                  #0
+                
+                
+                  1
+                  Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0].
+                  #1
+                
+              
+            
+            
+              UFRNM
+              MicroframeIndicate the microframe number.
+              0
+              2
+              read-only
+            
+          
+        
+        
+          USBADDR
+          USB Address Register
+          0x050
+          16
+          read-write
+          0x0000
+          0x077F
+          
+            
+              STSRECOV0
+              Status Recovery
+              8
+              10
+              read-write
+              
+                
+                  001
+                  Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)
+                  #001
+                
+                
+                  010
+                  Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected)
+                  #010
+                
+                
+                  011
+                  Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)
+                  #011
+                
+                
+                  100
+                  Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected)
+                  #100
+                
+                
+                  101
+                  Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected)
+                  #101
+                
+                
+                  110
+                  Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected)
+                  #110
+                
+                
+                  111
+                  Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected)
+                  #111
+                
+                
+                  others
+                  Setting prohibited.
+                  true
+                
+              
+            
+            
+              USBADDR
+              USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully.
+              0
+              6
+              read-only
+            
+          
+        
+        
+          USBREQ
+          USB Request Type Register
+          0x054
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              BREQUEST
+              RequestThese bits store the USB request bRequest value.
+              8
+              15
+              read-write
+            
+            
+              BMREQUESTTYPE
+              Request TypeThese bits store the USB request bmRequestType value.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          USBVAL
+          USB Request Value Register
+          0x056
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              WVALUE
+              ValueThese bits store the USB request Value value.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          USBINDX
+          USB Request Index Register
+          0x058
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              WINDEX
+              IndexThese bits store the USB request wIndex value.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          USBLENG
+          USB Request Length Register
+          0x05A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              WLENGTH
+              LengthThese bits store the USB request wLength value.
+              0
+              15
+              read-write
+            
+          
+        
+        
+          DCPCFG
+          DCP Configuration Register
+          0x05C
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              CNTMD
+              Continuous Transfer Mode
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Non-continuous transfer mode
+                  #0
+                
+                
+                  1
+                  Continuous transfer mode
+                  #1
+                
+              
+            
+            
+              SHTNAK
+              Pipe Disabled at End of Transfer
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Pipe continued at the end of transfer
+                  #0
+                
+                
+                  1
+                  Pipe disabled at the end of transfer
+                  #1
+                
+              
+            
+            
+              DIR
+              Transfer Direction
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Data receiving direction
+                  #0
+                
+                
+                  1
+                  Data transmitting direction
+                  #1
+                
+              
+            
+          
+        
+        
+          DCPMAXP
+          DCP Maximum Packet Size Register
+          0x05E
+          16
+          read-write
+          0x0040
+          0xFFFF
+          
+            
+              DEVSEL
+              Device Select
+              12
+              15
+              read-write
+              
+                
+                  0000
+                  Address 0000
+                  #0000
+                
+                
+                  0001
+                  Address 0001
+                  #0001
+                
+                
+                  0010
+                  Address 0010
+                  #0010
+                
+                
+                  0011
+                  Address 0011
+                  #0011
+                
+                
+                  0100
+                  Address 0100
+                  #0100
+                
+                
+                  0101
+                  Address 0101
+                  #0101
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+            
+              MXPS
+              Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
+              0
+              6
+              read-write
+              
+                
+                  0x08
+                  8 bytes
+                  0x08
+                
+                
+                  0x10
+                  16 bytes
+                  0x10
+                
+                
+                  0x18
+                  24 bytes
+                  0x18
+                
+                
+                  0x20
+                  32 bytes
+                  0x20
+                
+                
+                  0x28
+                  40 bytes
+                  0x28
+                
+                
+                  0x30
+                  48 bytes
+                  0x30
+                
+                
+                  0x38
+                  56 bytes
+                  0x38
+                
+                
+                  0x40
+                  64 bytes
+                  0x40
+                
+                
+                  0x48
+                  72 bytes
+                  0x48
+                
+                
+                  0x50
+                  80 bytes
+                  0x50
+                
+                
+                  0x58
+                  88 bytes
+                  0x58
+                
+                
+                  0x60
+                  96 bytes
+                  0x60
+                
+                
+                  0x68
+                  104 bytes
+                  0x68
+                
+                
+                  0x70
+                  112 bytes
+                  0x70
+                
+                
+                  0x78
+                  120 bytes
+                  0x78
+                
+                
+                  others
+                  Setting prohibited
+                  true
+                
+              
+            
+          
+        
+        
+          DCPCTR
+          DCP Control Register
+          0x060
+          16
+          read-write
+          0x0040
+          0xFFFF
+          
+            
+              BSTS
+              Buffer Status
+              15
+              15
+              read-only
+              
+                
+                  0
+                  Buffer access is disabled.
+                  #0
+                
+                
+                  1
+                  Buffer access is enabled.
+                  #1
+                
+              
+            
+            
+              SUREQ
+              Setup Token Transmission
+              14
+              14
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Transmits the setup packet.
+                  #1
+                
+              
+            
+            
+              SUREQCLR
+              SUREQ Bit Clear
+              11
+              11
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Clears the SUREQ bit to 0.
+                  #1
+                
+              
+            
+            
+              SQCLR
+              Sequence Toggle Bit Clear
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Specifies DATA0.
+                  #1
+                
+              
+            
+            
+              SQSET
+              Sequence Toggle Bit Set
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Specifies DATA1.
+                  #1
+                
+              
+            
+            
+              SQMON
+              Sequence Toggle Bit Monitor
+              6
+              6
+              read-only
+              
+                
+                  0
+                  DATA0
+                  #0
+                
+                
+                  1
+                  DATA1
+                  #1
+                
+              
+            
+            
+              PBUSY
+              Pipe Busy
+              5
+              5
+              read-only
+              
+                
+                  0
+                  DCP is not used for the transaction.
+                  #0
+                
+                
+                  1
+                  DCP is used for the transaction.
+                  #1
+                
+              
+            
+            
+              CCPL
+              Control Transfer End Enable
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Invalid
+                  #0
+                
+                
+                  1
+                  Completion of control transfer is enabled.
+                  #1
+                
+              
+            
+            
+              PID
+              Response PID
+              0
+              1
+              read-write
+              
+                
+                  00
+                  NAK response
+                  #00
+                
+                
+                  01
+                  BUF response (depending on the buffer state)
+                  #01
+                
+                
+                  10
+                  STALL response
+                  #10
+                
+                
+                  11
+                  STALL response
+                  #11
+                
+              
+            
+          
+        
+        
+          PIPESEL
+          Pipe Window Select Register
+          0x064
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              PIPESEL
+              Pipe Window Select
+              0
+              3
+              read-write
+              
+                
+                  0000
+                  No pipe selected
+                  #0000
+                
+                
+                  0001
+                  PIPE1
+                  #0001
+                
+                
+                  0010
+                  PIPE2
+                  #0010
+                
+                
+                  0011
+                  PIPE3
+                  #0011
+                
+                
+                  0100
+                  PIPE4
+                  #0100
+                
+                
+                  0101
+                  PIPE5
+                  #0101
+                
+                
+                  0110
+                  PIPE6
+                  #0110
+                
+                
+                  0111
+                  PIPE7
+                  #0111
+                
+                
+                  1000
+                  PIPE8
+                  #1000
+                
+                
+                  1001
+                  PIPE9
+                  #1001
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+          
+        
+        
+          PIPECFG
+          Pipe Configuration Register
+          0x068
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              TYPE
+              Transfer Type
+              14
+              15
+              read-write
+              
+                
+                  00
+                  Pipe not used
+                  #00
+                
+                
+                  01
+                  Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)
+                  #01
+                
+                
+                  10
+                  Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)
+                  #10
+                
+                
+                  11
+                  Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) 
+                  #11
+                
+              
+            
+            
+              BFRE
+              BRDY Interrupt Operation Specification
+              10
+              10
+              read-write
+              
+                
+                  0
+                  BRDY interrupt upon transmitting or receiving data
+                  #0
+                
+                
+                  1
+                  BRDY interrupt upon completion of reading data
+                  #1
+                
+              
+            
+            
+              DBLB
+              Double Buffer Mode
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Single buffer
+                  #0
+                
+                
+                  1
+                  Double buffer
+                  #1
+                
+              
+            
+            
+              SHTNAK
+              Pipe Disabled at End of Transfer
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Continue pipe operation after transfer ends
+                  #0
+                
+                
+                  1
+                  Disable pipe operation after transfer ends.
+                  #1
+                
+              
+            
+            
+              DIR
+              Transfer Direction
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Receiving direction
+                  #0
+                
+                
+                  1
+                  Transmitting direction
+                  #1
+                
+              
+            
+            
+              EPNUM
+              Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. 
+              0
+              3
+              read-write
+            
+          
+        
+        
+          PIPEMAXP
+          Pipe Maximum Packet Size Register 
+          0x06C
+          16
+          read-write
+          0x0000
+          0xFFBF
+          
+            
+              DEVSEL
+              Device Select
+              12
+              15
+              read-write
+              
+                
+                  0000
+                  Address 0000
+                  #0000
+                
+                
+                  0001
+                  Address 0001
+                  #0001
+                
+                
+                  0010
+                  Address 0010
+                  #0010
+                
+                
+                  0011
+                  Address 0011
+                  #0011
+                
+                
+                  0100
+                  Address 0100
+                  #0100
+                
+                
+                  0101
+                  Address 0101
+                  #0101
+                
+                
+                  others
+                  Settings prohibited.
+                  true
+                
+              
+            
+            
+              MXPS
+              Maximum Packet SizePIPE1 and PIPE2:  1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5:   8 bytes (008h), 16 bytes (010h),  32 bytes (020h), 64 bytes (040h)   (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9:  1 byte (001h) to 64 bytes (040h)  (Bits [8:7] are not provided.)
+              0
+              8
+              read-write
+            
+          
+        
+        
+          PIPEPERI
+          Pipe Cycle Control Register
+          0x06E
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              IFIS
+              Isochronous IN Buffer Flush
+              12
+              12
+              read-write
+              
+                
+                  0
+                  The buffer is not flushed.
+                  #0
+                
+                
+                  1
+                  The buffer is flushed.
+                  #1
+                
+              
+            
+            
+              IITV
+              Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2.
+              0
+              2
+              read-write
+            
+          
+        
+        
+          9
+          0x002
+          PIPE_CTR[%s]
+          Pipe %s Control Register
+          0x070
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              BSTS
+              Buffer Status
+              15
+              15
+              read-only
+              
+                
+                  0
+                  Buffer access by the CPU is disabled.
+                  #0
+                
+                
+                  1
+                  Buffer access by the CPU is enabled.
+                  #1
+                
+              
+            
+            
+              INBUFM
+              Transmit Buffer Monitor
+              14
+              14
+              read-only
+              
+                
+                  0
+                  No data to be transmitted is in the FIFO buffer
+                  #0
+                
+                
+                  1
+                  Data to be transmitted is in the FIFO buffer
+                  #1
+                
+              
+            
+            
+              CSCLR
+              CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe
+              13
+              13
+              read-write
+              
+                
+                  0
+                  Writing is disabled.
+                  #0
+                
+                
+                  1
+                  The CSSTS bit is cleared.
+                  #1
+                
+              
+            
+            
+              CSSTS
+              CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe
+              12
+              12
+              read-only
+              
+                
+                  0
+                  SSplit Transaction processing is in progress or transfer without Split Transaction is in progress.
+                  #0
+                
+                
+                  1
+                  CSplit Transaction processing is in progress.
+                  #1
+                
+              
+            
+            
+              ATREPM
+              Auto Response Mode
+              10
+              10
+              read-write
+              
+                
+                  0
+                  Auto response disabled.
+                  #0
+                
+                
+                  1
+                  Auto response enabled.
+                  #1
+                
+              
+            
+            
+              ACLRM
+              Auto Buffer Clear Mode
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled (all buffers are initialized)
+                  #1
+                
+              
+            
+            
+              SQCLR
+              Sequence Toggle Bit Clear
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Write disabled
+                  #0
+                
+                
+                  1
+                  Specifies DATA0.
+                  #1
+                
+              
+            
+            
+              SQSET
+              Sequence Toggle Bit Set
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Write disabled
+                  #0
+                
+                
+                  1
+                  Specifies DATA1.
+                  #1
+                
+              
+            
+            
+              SQMON
+              Sequence Toggle Bit Confirmation
+              6
+              6
+              read-only
+              
+                
+                  0
+                  DATA0
+                  #0
+                
+                
+                  1
+                  DATA1
+                  #1
+                
+              
+            
+            
+              PBUSY
+              Pipe Busy
+              5
+              5
+              read-only
+              
+                
+                  0
+                  Pipe n not in use for the transaction
+                  #0
+                
+                
+                  1
+                  Pipe n in use for the transaction.
+                  #1
+                
+              
+            
+            
+              PID
+              Response PID
+              0
+              1
+              read-write
+              
+                
+                  00
+                  NAK response
+                  #00
+                
+                
+                  01
+                  BUF response (depending on the buffer state)
+                  #01
+                
+                
+                  10
+                  STALL response
+                  #10
+                
+                
+                  11
+                  STALL response
+                  #11
+                
+              
+            
+          
+        
+        
+          10
+          0x002
+          DEVADD[%s]
+          Device Address Configuration Register
+          0x0D0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              UPPHUB
+              Communication Target Connecting Hub Register
+              11
+              14
+              read-write
+              
+                
+                  0x0000
+                  0x1010
+                
+              
+              
+                
+                  0000
+                  Directly connected to the port of the USBHS.
+                  #0000
+                
+                
+                  UPPHUB
+                  USB address of the hub
+                  true
+                
+              
+            
+            
+              HUBPORT
+              Communication Target Connecting Hub Port
+              8
+              10
+              read-write
+              
+                
+                  000
+                  Directly connected to the port of the USBHS. 
+                  #000
+                
+                
+                  others
+                  Port number of the hub
+                  true
+                
+              
+            
+            
+              USBSPD
+              Transfer Speed of Communication Target Device
+              6
+              7
+              read-write
+              
+                
+                  00
+                  DEVADDn is not used
+                  #00
+                
+                
+                  01
+                  Low speed
+                  #01
+                
+                
+                  10
+                  Full speed
+                  #10
+                
+                
+                  11
+                  Setting prohibited
+                  #11
+                
+              
+            
+          
+        
+        
+          USBBCCTRL0
+          BC Control Register 0
+          0x0B0
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              PDDETSTS0
+              D+ Pin 0.6 V Input Detection Status
+              9
+              9
+              read-only
+              
+                
+                  0
+                  Not detected
+                  #0
+                
+                
+                  1
+                  Detected
+                  #1
+                
+              
+            
+            
+              CHGDETSTS0
+              D- Pin 0.6 V Input Detection Status
+              8
+              8
+              read-only
+              
+                
+                  0
+                  Not detected
+                  #0
+                
+                
+                  1
+                  Detected
+                  #1
+                
+              
+            
+            
+              BATCHGE0
+              BC (Battery Charger) Function Ch0 General Enable Control
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disabled
+                  #0
+                
+                
+                  1
+                  Enabled
+                  #1
+                
+              
+            
+            
+              VDMSRCE0
+              D- Pin VDMSRC (0.6 V) Output Control
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Stop
+                  #0
+                
+                
+                  1
+                  0.6V output
+                  #1
+                
+              
+            
+            
+              IDPSINKE0
+              D+ Pin 0.6 V Input Detection (Comparator and Sink) Control
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Detection off
+                  #0
+                
+                
+                  1
+                  Detection on ( Comparator and sink current on )
+                  #1
+                
+              
+            
+            
+              VDPSRCE0
+              D+ Pin VDPSRC (0.6 V) Output Control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Stop
+                  #0
+                
+                
+                  1
+                  0.6V output
+                  #1
+                
+              
+            
+            
+              IDMSINKE0
+              D- Pin 0.6 V Input Detection (Comparator and Sink) Control
+              2
+              2
+              read-write
+              
+                
+                  0
+                  Detection off
+                  #0
+                
+                
+                  1
+                  Detection on ( Comparator and sink current on )
+                  #1
+                
+              
+            
+            
+              IDPSRCE0
+              D+ Pin IDPSRC Output Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Stop
+                  #0
+                
+                
+                  1
+                  10uA output
+                  #1
+                
+              
+            
+            
+              RPDME0
+              D- Pin Pull-Down Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Pull-down off
+                  #0
+                
+                
+                  1
+                  Pull-down on
+                  #1
+                
+              
+            
+          
+        
+        
+          UCKSEL
+          USB Clock Selection Register
+          0x0C4
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              UCKSELC
+              USB Clock Selection
+              0
+              0
+              read-write
+              
+                
+                  0
+                  High-speed on-chip oscillator clock (HOCO) is not selected as USB clock
+                  #0
+                
+                
+                  1
+                  High-speed on-chip oscillator clock (HOCO) is selected as USB clock
+                  #1
+                
+              
+            
+          
+        
+        
+          USBMC
+          USB Module Control Register
+          0x0CC
+          16
+          read-write
+          0x0002
+          0xFFFF
+          
+            
+              VDCEN
+              USB Regulator On/Off Control
+              7
+              7
+              read-write
+              
+                
+                  0
+                  USB regulator off
+                  #0
+                
+                
+                  1
+                  USB regulator on
+                  #1
+                
+              
+            
+            
+              VDDUSBE
+              USB Reference Power Supply Circuit On/Off Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  USB reference power supply circuit off
+                  #0
+                
+                
+                  1
+                  USB reference power supply circuit on
+                  #1
+                
+              
+            
+          
+        
+        
+          PHYSLEW
+          PHY Cross Point Adjustment Register 
+          0x0F0
+          32
+          read-write
+          0x0000000E
+          0xFF4CFFFF
+          
+            
+              SLEWF01
+              Receiver Cross Point Adjustment 01
+              3
+              3
+              read-write
+              
+                
+                  1
+                  Host or device controller mode.
+                  #1
+                
+              
+            
+            
+              SLEWF00
+              Receiver Cross Point Adjustment 00
+              2
+              2
+              read-write
+              
+                
+                  1
+                  Host or device controller mode.
+                  #1
+                
+              
+            
+            
+              SLEWR01
+              Receiver Cross Point Adjustment 01
+              1
+              1
+              read-write
+              
+                
+                  1
+                  Host or device controller mode.
+                  #1
+                
+              
+            
+            
+              SLEWR00
+              Receiver Cross Point Adjustment 00
+              0
+              0
+              read-write
+              
+                
+                  1
+                  Host or device controller mode.
+                  #1
+                
+              
+            
+          
+        
+        
+          LPCTRL
+          Low Power Control Register
+          0x100
+          16
+          read-write
+          0x0000
+          0x0181
+          
+            
+              HWUPM
+              Resume Return Mode Setting
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Hardware does not recover while CPU clock inactive
+                  #0
+                
+                
+                  1
+                  Hardware recovers while CPU clock inactive.
+                  #1
+                
+              
+            
+          
+        
+        
+          LPSTS
+          Low Power Status Register
+          0x102
+          16
+          read-write
+          0x0000
+          0x510B
+          
+            
+              SUSPENDM
+              UTMI SuspendM Control
+              14
+              14
+              read-write
+              
+                
+                  0
+                  UTMI suspension mode
+                  #0
+                
+                
+                  1
+                  UTMI normal mode
+                  #1
+                
+              
+            
+          
+        
+        
+          BCCTRL
+          Battery Charging Control Register
+          0x140
+          16
+          read-write
+          0x0000
+          0x033F
+          
+            
+              PDDETSTS
+              PDDET Status
+              9
+              9
+              read-only
+              
+                
+                  0
+                  The PDDET pin is at low level.
+                  #0
+                
+                
+                  1
+                  The PDDET pin is at high level.
+                  #1
+                
+              
+            
+            
+              CHGDETSTS
+              CHGDET Status
+              8
+              8
+              read-only
+              
+                
+                  0
+                  The CHGDET pin is at low level.
+                  #0
+                
+                
+                  1
+                  The CHGDET pin is at high level.
+                  #1
+                
+              
+            
+            
+              DCPMODE
+              DCP Mode Control
+              5
+              5
+              read-write
+              
+                
+                  0
+                  The RDCP_DAT resistor is disabled
+                  #0
+                
+                
+                  1
+                  The RDCP_DAT resistor is enabled.
+                  #1
+                
+              
+            
+            
+              VDMSRCE
+              VDMSRC Control
+              4
+              4
+              read-write
+              
+                
+                  0
+                  The VDM_SRC circuit is disabled. (Initial value)
+                  #0
+                
+                
+                  1
+                  The VDM_SRC circuit is enabled.
+                  #1
+                
+              
+            
+            
+              IDPSINKE
+              IDPSINK Control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  The IDP_SINK circuit is disabled. (Initial value)
+                  #0
+                
+                
+                  1
+                  The IDP_SINK circuit is enabled.
+                  #1
+                
+              
+            
+            
+              VDPSRCE
+              VDPSRC Control
+              2
+              2
+              read-write
+              
+                
+                  0
+                  The VDP_SRC circuit is disabled. (Initial value)
+                  #0
+                
+                
+                  1
+                  The VDP_SRC circuit is enabled.
+                  #1
+                
+              
+            
+            
+              IDMSINKE
+              IDMSINK Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  The IDM_SINK circuit is disabled. (Initial value)
+                  #0
+                
+                
+                  1
+                  The IDM_SINK circuit is enabled.
+                  #1
+                
+              
+            
+            
+              IDPSRCE
+              IDPSRC Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  The IDP_SRC circuit is disabled. (Initial value)
+                  #0
+                
+                
+                  1
+                  The IDP_SRC circuit is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          PL1CTRL1
+          Function L1 Control Register 1
+          0x144
+          16
+          read-write
+          0x0000
+          0x4FFF
+          
+            
+              L1EXTMD
+              PHY Control Mode at L1 Return
+              14
+              14
+              read-write
+              
+                
+                  0
+                  SUSPENDM is not set by hardware when Host K is received.
+                  #0
+                
+                
+                  1
+                  SUSPENDM is set by hardware when Host K is received.
+                  #1
+                
+              
+            
+            
+              HIRDTHR
+              L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL.
+              8
+              11
+              read-write
+            
+            
+              DVSQ
+              DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0].
+              4
+              7
+              read-only
+              
+                
+                  0000
+                  Powered state
+                  #0000
+                
+                
+                  0001
+                  Default state
+                  #0001
+                
+                
+                  0010
+                  Address state
+                  #0010
+                
+                
+                  0011
+                  Configured state
+                  #0011
+                
+                
+                  0100
+                  Suspended state
+                  #0100
+                
+                
+                  0101
+                  Suspended state
+                  #0101
+                
+                
+                  0110
+                  Suspended state
+                  #0110
+                
+                
+                  0111
+                  Suspended state
+                  #0111
+                
+                
+                  1000
+                  L1 state
+                  #1000
+                
+                
+                  1001
+                  L1 state
+                  #1001
+                
+                
+                  1010
+                  L1 state
+                  #1010
+                
+                
+                  1011
+                  L1 state
+                  #1011
+                
+                
+                  others
+                  setting prohibited
+                  true
+                
+              
+            
+            
+              L1NEGOMD
+              L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11.
+              3
+              3
+              read-write
+              
+                
+                  0
+                  When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.
+                  #0
+                
+                
+                  1
+                  When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned.
+                  #1
+                
+              
+            
+            
+              L1RESPMD
+              L1 Response Mode
+              1
+              2
+              read-write
+              
+                
+                  00
+                  NYET
+                  #00
+                
+                
+                  01
+                  ACK
+                  #01
+                
+                
+                  10
+                  STALL
+                  #10
+                
+                
+                  11
+                  According to the L1NEGOMD bit
+                  #11
+                
+              
+            
+            
+              L1RESPEN
+              L1 Response Enable
+              0
+              0
+              read-write
+              
+                
+                  0
+                  LPM is not supported.
+                  #0
+                
+                
+                  1
+                  LPM is supported.
+                  #1
+                
+              
+            
+          
+        
+        
+          PL1CTRL2
+          Function L1 Control Register 2
+          0x146
+          16
+          read-write
+          0x0000
+          0x1F00
+          
+            
+              RWEMON
+              RWE Value Monitor
+              12
+              12
+              read-write
+              
+                
+                  0
+                  The RWE bit value of the LPM token received last is reflected.
+                  #0
+                
+                
+                  1
+                  The RWE bit value of the LPM token received last is reflected.
+                  #1
+                
+              
+            
+            
+              HIRDMON
+              HIRD Value Monitor
+              8
+              11
+              read-write
+              
+                
+                  0
+                  The HIRD field value of the LPM token received last is reflected.
+                  #0
+                
+                
+                  1
+                  The HIRD field value of the LPM token received last is reflected.
+                  #1
+                
+              
+            
+          
+        
+        
+          HL1CTRL1
+          Host L1 Control Register 1
+          0x148
+          16
+          read-write
+          0x0000
+          0x0007
+          
+            
+              L1STATUS
+              L1 Request Completion Status
+              1
+              2
+              read-only
+              
+                
+                  00
+                  ACK received
+                  #00
+                
+                
+                  01
+                  NYET received
+                  #01
+                
+                
+                  10
+                  STALL received
+                  #10
+                
+                
+                  11
+                  Transaction error
+                  #11
+                
+              
+            
+            
+              L1REQ
+              L1 Transition Request
+              0
+              0
+              read-write
+              
+                
+                  0
+                  This bit is cleared to 0 by hardware when the LPM transaction is completed.
+                  #0
+                
+                
+                  1
+                  Set this bit to 1 when requesting a transition to the L1 state.
+                  #1
+                
+              
+            
+          
+        
+        
+          HL1CTRL2
+          Host L1 Control Register 2
+          0x14A
+          16
+          read-write
+          0x0000
+          0x9F0F
+          
+            
+              BESL
+              BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume.
+              15
+              15
+              read-write
+            
+            
+              L1RWE
+              LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token.
+              12
+              12
+              read-write
+            
+            
+              HIRD
+              LPM Token HIRD
+              8
+              11
+              read-write
+              
+                
+                  0000
+                  50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1)
+                  #0000
+                
+                
+                  0001
+                  125 us(BESL = 0) / 100 us(BESL = 1)
+                  #0001
+                
+                
+                  0010
+                  200 us(BESL = 0) / 150 us(BESL = 1)
+                  #0010
+                
+                
+                  0011
+                  275 us(BESL = 0) / 250 us(BESL = 1)
+                  #0011
+                
+                
+                  0100
+                  350 us(BESL = 0) / 350 us(BESL = 1)
+                  #0100
+                
+                
+                  0101
+                  425 us(BESL = 0) / 450 us(BESL = 1)
+                  #0101
+                
+                
+                  0110
+                  500 us(BESL = 0) / 950 us(BESL = 1)
+                  #0110
+                
+                
+                  0111
+                  575 us(BESL = 0) / 1950 us(BESL = 1)
+                  #0111
+                
+                
+                  1000
+                  650 us(BESL = 0) / 2950 us(BESL = 1)
+                  #1000
+                
+                
+                  1001
+                  725 us(BESL = 0) / 3950 us(BESL = 1)
+                  #1001
+                
+                
+                  1010
+                  800 us(BESL = 0) / 4950 us(BESL = 1)
+                  #1010
+                
+                
+                  1011
+                  875 us(BESL = 0) / 5950 us(BESL = 1)
+                  #1011
+                
+                
+                  1100
+                  950 us(BESL = 0) / 6950 us(BESL = 1)
+                  #1100
+                
+                
+                  1101
+                  1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1)
+                  #1101
+                
+                
+                  1110
+                  1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1)
+                  #1110
+                
+                
+                  1111
+                  1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1)
+                  #1111
+                
+              
+            
+            
+              L1ADDR
+              LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          DPUSR0R
+          Deep Standby USB Transceiver Control/Pin Monitor Register 
+          0x160
+          32
+          read-only
+          0x00000000
+          0xFF4FFFFF
+          
+            
+              DVBSTSHM
+              VBUS InputIndicates VBUS input signal on the HS side of USB port.
+              23
+              23
+              read-only
+            
+            
+              DOVCBHM
+              OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port.
+              21
+              21
+              read-only
+            
+            
+              DOVCAHM
+              OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port.
+              20
+              20
+              read-only
+            
+          
+        
+        
+          DPUSR1R
+          Deep Standby USB Suspend/Resume Interrupt Register
+          0x164
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DVBSTSH
+              Indication of Return from VBUS Interrupt Source
+              23
+              23
+              read-only
+              
+                
+                  0
+                  Indicates deep software standby mode
+                  #0
+                
+                
+                  1
+                  Indicates return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DOVCBH
+              Indication of Return from OVRCURB Interrupt Source
+              21
+              21
+              read-only
+              
+                
+                  0
+                  Indicates deep software standby mode
+                  #0
+                
+                
+                  1
+                  Indicates return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DOVCAH
+              Indication of Return from OVRCURA Interrupt Source
+              20
+              20
+              read-only
+              
+                
+                  0
+                  Indicates deep software standby mode
+                  #0
+                
+                
+                  1
+                  Indicates return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DVBSTSHE
+              VBUS Interrupt Enable/Clear
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Disables return from deep software standby mode
+                  #0
+                
+                
+                  1
+                  Enables return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DOVCBHE
+              OVRCURB Interrupt Enable Clear
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Disables return from deep software standby mode
+                  #0
+                
+                
+                  1
+                  Enables return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DOVCAHE
+              OVRCURA Interrupt Enable Clear
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Disables return from deep software standby mode
+                  #0
+                
+                
+                  1
+                  Enables return from deep software standby mode
+                  #1
+                
+              
+            
+          
+        
+        
+          DPUSR2R
+          Deep Standby USB Suspend/Resume Interrupt Register
+          0x168
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              DMINTE
+              DM Interrupt Enable Clear
+              9
+              9
+              read-write
+              
+                
+                  0
+                  Disables return from deep software standby mode
+                  #0
+                
+                
+                  1
+                  Enables return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DPINTE
+              DP Interrupt Enable Clear
+              8
+              8
+              read-write
+              
+                
+                  0
+                  Disables return from deep software standby mode
+                  #0
+                
+                
+                  1
+                  Enables return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DMVAL
+              DM InputIndicates DM input signal on the HS side of USB port.
+              5
+              5
+              read-only
+            
+            
+              DPVAL
+              DP InputIndicates DP input signal on the HS side of USB port.
+              4
+              4
+              read-only
+            
+            
+              DMINT
+              Indication of Return from DM Interrupt Source
+              1
+              1
+              read-only
+              
+                
+                  0
+                  Indicates deep software standby mode
+                  #0
+                
+                
+                  1
+                  Indicates return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              DPINT
+              Indication of Return from DP Interrupt Source
+              0
+              0
+              read-only
+              
+                
+                  0
+                  Indicates deep software standby mode
+                  #0
+                
+                
+                  1
+                  Indicates return from deep software standby mode
+                  #1
+                
+              
+            
+          
+        
+        
+          DPUSRCR
+          Deep Standby USB Suspend/Resume Command Register
+          0x16A
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              FIXPHYPD
+              USB Transceiver Control Fix for PLL
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Go to/Return from deep software standby mode
+                  #1
+                
+              
+            
+            
+              FIXPHY
+              USB Transceiver Control Fix
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Normal mode
+                  #0
+                
+                
+                  1
+                  Go to/Return from deep software standby mode
+                  #1
+                
+              
+            
+          
+        
+        
+          DPUSR0R_FS
+          Deep Software Standby USB Transceiver Control/Pin Monitor Register
+          0x400
+          32
+          read-write
+          0x00000000
+          0xFF4CFFFF
+          
+            
+              DVBSTS0
+              USB VBUS InputIndicates the VBUS input signal of the USB.
+              23
+              23
+              read-only
+            
+            
+              DOVCB0
+              USB OVRCURB InputIndicates the OVRCURB input signal of the USB.
+              21
+              21
+              read-only
+            
+            
+              DOVCA0
+              USB OVRCURA InputIndicates the OVRCURA input signal of the USB.
+              20
+              20
+              read-only
+            
+            
+              DM0
+              USB D-InputIndicates the D- input signal of the USB.
+              17
+              17
+              read-only
+            
+            
+              DP0
+              USB0 D+ InputIndicates the D+ input signal of the USB.
+              16
+              16
+              read-only
+            
+            
+              FIXPHY0
+              USB Transceiver Output Fix
+              4
+              4
+              read-write
+              
+                
+                  0
+                  The outputs are fixed in normal mode and on return from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The outputs are fixed on transitions to deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DRPD0
+              D+/D- Pull-Down Resistor Control
+              3
+              3
+              read-write
+              
+                
+                  0
+                  Disables DP/DM pull-down resistor.
+                  #0
+                
+                
+                  1
+                  Enables DP/DM pull-down resistor.
+                  #1
+                
+              
+            
+            
+              RPUE0
+              DP Pull-Up Resistor Control
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Disables DP pull-up resistor.
+                  #0
+                
+                
+                  1
+                  Enables DP pull-up resistor.
+                  #1
+                
+              
+            
+            
+              SRPC0
+              USB Single End Receiver Control
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Input through the DP and DM inputs is disabled.
+                  #0
+                
+                
+                  1
+                  Input through the DP and DM inputs is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          DPUSR1R_FS
+          Deep Software Standby USB Suspend/Resume Interrupt Register
+          0x404
+          32
+          read-write
+          0x00000000
+          0xFFFFFFFF
+          
+            
+              DVBINT0
+              USB VBUS Interrupt Source Recovery
+              23
+              23
+              read-only
+              
+                
+                  0
+                  The system has not returned from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The system has returned from deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DOVRCRB0
+              USB OVRCURB Interrupt Source Recovery
+              21
+              21
+              read-only
+              
+                
+                  0
+                  The system has not returned from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The system has returned from deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DOVRCRA0
+              USB OVRCURA Interrupt Source Recovery
+              20
+              20
+              read-only
+              
+                
+                  0
+                  The system has not returned from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The system has returned from deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DMINT0
+              USB DM Interrupt Source Recovery
+              17
+              17
+              read-only
+              
+                
+                  0
+                  The system has not returned from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The system has returned from deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DPINT0
+              USB DP Interrupt Source Recovery
+              16
+              16
+              read-only
+              
+                
+                  0
+                  The system has not returned from deep software standby mode.
+                  #0
+                
+                
+                  1
+                  The system has returned from deep software standby mode.
+                  #1
+                
+              
+            
+            
+              DVBSE0
+              USB VBUS Interrupt Enable/Clear
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Recovery from deep software standby mode is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery from deep software standby mode is enabled.
+                  #1
+                
+              
+            
+            
+              DOVRCRBE0
+              USB OVRCURB Interrupt Enable/Clear
+              5
+              5
+              read-write
+              
+                
+                  0
+                  Recovery from deep software standby mode is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery from deep software standby mode is enabled.
+                  #1
+                
+              
+            
+            
+              DOVRCRAE0
+              USB OVRCURA Interrupt Enable/Clear
+              4
+              4
+              read-write
+              
+                
+                  0
+                  Recovery from deep software standby mode is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery from deep software standby mode is enabled.
+                  #1
+                
+              
+            
+            
+              DMINTE0
+              USB DM Interrupt Enable/Clear
+              1
+              1
+              read-write
+              
+                
+                  0
+                  Recovery from deep software standby mode is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery from deep software standby mode is enabled.
+                  #1
+                
+              
+            
+            
+              DPINTE0
+              USB DP Interrupt Enable/Clear
+              0
+              0
+              read-write
+              
+                
+                  0
+                  Recovery from deep software standby mode is disabled.
+                  #0
+                
+                
+                  1
+                  Recovery from deep software standby mode is enabled.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+    
+      R_USB_HS0
+      0x40060000
+    
+    
+      R_WDT
+      Watchdog Timer
+      0x40044200
+      
+        0x00000000
+        0x01
+        registers
+      
+      
+        0x00000002
+        0x005
+        registers
+      
+      
+        0x00000008
+        0x01
+        registers
+      
+      
+        
+          WDTRR
+          WDT Refresh Register 
+          0x00
+          8
+          read-write
+          0xFF
+          0xFF
+          
+            
+              WDTRR
+              WDTRR is an 8-bit register that  refreshes the down-counter of the WDT.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          WDTCR
+          WDT Control Register 
+          0x02
+          16
+          read-write
+          0x33F3
+          0xFFFF
+          
+            
+              RPSS
+              Window Start Position Selection
+              12
+              13
+              read-write
+              
+                
+                  00
+                  25%
+                  #00
+                
+                
+                  01
+                  50%
+                  #01
+                
+                
+                  10
+                  75%
+                  #10
+                
+                
+                  11
+                  100% (window start position is not specified)
+                  #11
+                
+              
+            
+            
+              RPES
+              Window End Position Selection
+              8
+              9
+              read-write
+              
+                
+                  00
+                  75%
+                  #00
+                
+                
+                  01
+                  50%
+                  #01
+                
+                
+                  10
+                  25%
+                  #10
+                
+                
+                  11
+                  0% (window end position is not specified)
+                  #11
+                
+              
+            
+            
+              CKS
+              Clock Division Ratio Selection
+              4
+              7
+              read-write
+              
+                
+                  0001
+                  PCLK/4
+                  #0001
+                
+                
+                  0100
+                  PCLK/64
+                  #0100
+                
+                
+                  1111
+                  PCLK/128
+                  #1111
+                
+                
+                  0110
+                  PCLK/512
+                  #0110
+                
+                
+                  0111
+                  PCLK/2048
+                  #0111
+                
+                
+                  1000
+                  PCLK/8192
+                  #1000
+                
+                
+                  others
+                  setting prohibited
+                  true
+                
+              
+            
+            
+              TOPS
+              Timeout Period Selection
+              0
+              1
+              read-write
+              
+                
+                  00
+                  1,024 cycles (03FFh)
+                  #00
+                
+                
+                  01
+                  4,096 cycles (0FFFh)
+                  #01
+                
+                
+                  10
+                  8,192 cycles (1FFFh)
+                  #10
+                
+                
+                  11
+                  16,384 cycles (3FFFh)
+                  #11
+                
+              
+            
+          
+        
+        
+          WDTSR
+          WDT Status Register 
+          0x04
+          16
+          read-write
+          0x0000
+          0xFFFF
+          
+            
+              REFEF
+              Refresh Error Flag 
+              15
+              15
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No refresh error occurred
+                  #0
+                
+                
+                  1
+                  Refresh error occurred
+                  #1
+                
+              
+            
+            
+              UNDFF
+              Underflow Flag
+              14
+              14
+              read-write
+              zeroToClear
+              modify
+              
+                
+                  0
+                  No underflow occurred
+                  #0
+                
+                
+                  1
+                  Underflow occurred
+                  #1
+                
+              
+            
+            
+              CNTVAL
+              Down-Counter Value
+              0
+              13
+              read-only
+            
+          
+        
+        
+          WDTRCR
+          WDT Reset Control Register 
+          0x06
+          8
+          read-write
+          0x80
+          0xFF
+          
+            
+              RSTIRQS
+              Reset Interrupt Request Selection
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Non-maskable interrupt request or interrupt request output is enabled
+                  #0
+                
+                
+                  1
+                  Reset output is enabled.
+                  #1
+                
+              
+            
+          
+        
+        
+          WDTCSTPR
+          WDT Count Stop Control Register 
+          0x08
+          8
+          read-write
+          0x80
+          0xFF
+          
+            
+              SLCSTP
+              Sleep-Mode Count Stop Control
+              7
+              7
+              read-write
+              
+                
+                  0
+                  Count stop is disabled.
+                  #0
+                
+                
+                  1
+                  Count is stopped at a transition to sleep mode.
+                  #1
+                
+              
+            
+          
+        
+      
+    
+  
+
\ No newline at end of file
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
new file mode 100644
index 0000000000..dfb1c8b7e2
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c
@@ -0,0 +1,144 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* Defines function pointers to be used with vector table. */
+typedef void (* exc_ptr_t)(void);
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+void    Reset_Handler(void);
+void    Default_Handler(void);
+int32_t main(void);
+
+/*******************************************************************************************************************//**
+ * MCU starts executing here out of reset. Main stack pointer is set up already.
+ **********************************************************************************************************************/
+void Reset_Handler (void)
+{
+    /* Initialize system using BSP. */
+    SystemInit();
+
+    /* Call user application. */
+    main();
+
+    while (1)
+    {
+        /* Infinite Loop. */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Default exception handler.
+ **********************************************************************************************************************/
+void Default_Handler (void)
+{
+    /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
+     *  or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
+     *  registers for more information.
+     */
+    BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
+}
+
+/* Main stack */
+static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) BSP_PLACE_IN_SECTION(
+    BSP_SECTION_STACK);
+
+/* Heap */
+#if (BSP_CFG_HEAP_BYTES > 0)
+
+BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
+    BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
+#endif
+
+/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle
+ * these exceptions in their code they should define their own function with the same name.
+ */
+#if defined(__ICCARM__)
+ #define WEAK_REF_ATTRIBUTE
+
+ #pragma weak HardFault_Handler                        = Default_Handler
+ #pragma weak MemManage_Handler                        = Default_Handler
+ #pragma weak BusFault_Handler                         = Default_Handler
+ #pragma weak UsageFault_Handler                       = Default_Handler
+ #pragma weak SVC_Handler                              = Default_Handler
+ #pragma weak DebugMon_Handler                         = Default_Handler
+ #pragma weak PendSV_Handler                           = Default_Handler
+ #pragma weak SysTick_Handler                          = Default_Handler
+#elif defined(__GNUC__)
+
+ #define WEAK_REF_ATTRIBUTE    __attribute__((weak, alias("Default_Handler")))
+#endif
+
+void NMI_Handler(void);                // NMI has many sources and is handled by BSP
+void HardFault_Handler(void) WEAK_REF_ATTRIBUTE;
+void MemManage_Handler(void) WEAK_REF_ATTRIBUTE;
+void BusFault_Handler(void) WEAK_REF_ATTRIBUTE;
+void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE;
+void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
+void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE;
+void PendSV_Handler(void) WEAK_REF_ATTRIBUTE;
+void SysTick_Handler(void) WEAK_REF_ATTRIBUTE;
+
+/* Vector table. */
+BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION(
+    BSP_SECTION_FIXED_VECTORS) =
+{
+    (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /*      Initial Stack Pointer     */
+    Reset_Handler,                                             /*      Reset Handler             */
+    NMI_Handler,                                               /*      NMI Handler               */
+    HardFault_Handler,                                         /*      Hard Fault Handler        */
+    MemManage_Handler,                                         /*      MPU Fault Handler         */
+    BusFault_Handler,                                          /*      Bus Fault Handler         */
+    UsageFault_Handler,                                        /*      Usage Fault Handler       */
+    0,                                                         /*      Reserved                  */
+    0,                                                         /*      Reserved                  */
+    0,                                                         /*      Reserved                  */
+    0,                                                         /*      Reserved                  */
+    SVC_Handler,                                               /*      SVCall Handler            */
+    DebugMon_Handler,                                          /*      Debug Monitor Handler     */
+    0,                                                         /*      Reserved                  */
+    PendSV_Handler,                                            /*      PendSV Handler            */
+    SysTick_Handler,                                           /*      SysTick Handler           */
+};
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
new file mode 100644
index 0000000000..5122e34cfb
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c
@@ -0,0 +1,354 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "../../../../mcu/all/bsp_clocks.h"
+#include 
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Mask to select CP bits( 0xF00000 ) */
+#define CP_MASK                                       (0x0000000FU << 20)
+
+/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
+#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION    (0xA500U)
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY                              (0xA500U)
+#define BSP_PRV_PRCR_PRC1_UNLOCK                      ((BSP_PRV_PRCR_KEY) | 0x2U)
+#define BSP_PRV_PRCR_LOCK                             ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock = 0U;
+
+#if defined(__ARMCC_VERSION)
+extern uint32_t Image$$BSS$$ZI$$Base;
+extern uint32_t Image$$BSS$$ZI$$Length;
+extern uint32_t Load$$DATA$$Base;
+extern uint32_t Image$$DATA$$Base;
+extern uint32_t Image$$DATA$$Length;
+extern uint32_t Image$$STACK$$RW$$Base;
+extern uint32_t Image$$STACK$$RW$$Length;
+#elif defined(__GNUC__)
+
+/* Generated by linker. */
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackLimit;
+extern uint32_t __StackTop;
+#elif defined(__ICCARM__)
+ #pragma section=".bss"
+ #pragma section=".data"
+ #pragma section=".data_init"
+ #pragma section=".stack"
+#endif
+
+/* Initialize static constructors */
+#if defined(__ARMCC_VERSION)
+extern void (* Image$$INIT_ARRAY$$Base[])(void);
+extern void (* Image$$INIT_ARRAY$$Limit[])(void);
+#elif defined(__GNUC__)
+
+extern void (* __init_array_start[])(void);
+
+extern void (* __init_array_end[])(void);
+#elif defined(__ICCARM__)
+extern void __call_ctors(void const *, void const *);
+
+ #pragma section = "SHT$$PREINIT_ARRAY" const
+ #pragma section = "SHT$$INIT_ARRAY" const
+#endif
+
+extern void * __Vectors[];
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+#if BSP_FEATURE_BSP_RESET_TRNG
+static void bsp_reset_trng_circuit(void);
+
+#endif
+
+#if defined(__ICCARM__)
+ #pragma weak R_BSP_WarmStart
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initialize the MCU and the runtime environment.
+ **********************************************************************************************************************/
+void SystemInit (void)
+{
+#if __FPU_USED
+
+    /* Enable the Cortex-M4 FPU only when -mfloat-abi=hard.
+     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */
+
+    /* Set bits 20-23 to enable CP10 and CP11 coprocessor */
+    /* SCB is a CMSIS defined element over which we have no control. */
+    SCB->CPACR |= (uint32_t) CP_MASK;
+#endif
+
+#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP
+
+    /* Unlock VBTCR1 register. */
+    R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+
+    /* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1
+     * "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual
+     * R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot
+     * be accessed until VBTSR.VBTRVLD is set. */
+    R_SYSTEM->VBTCR1 = 1U;
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U);
+
+    /* Lock VBTCR1 register. */
+    R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+#endif
+
+    /* Call pre clock initialization hook. */
+    R_BSP_WarmStart(BSP_WARM_START_RESET);
+
+    /* Configure system clocks. */
+    bsp_clock_init();
+
+#if BSP_FEATURE_BSP_RESET_TRNG
+
+    /* To prevent an undesired current draw, this MCU requires a reset
+     * of the TRNG circuit after the clocks are initialized */
+    bsp_reset_trng_circuit();
+#endif
+
+    /* Call post clock initialization hook. */
+    R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
+
+    /* Initialize C runtime environment. */
+    /* Zero out BSS */
+#if defined(__ARMCC_VERSION)
+    memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length);
+#elif defined(__GNUC__)
+    memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__));
+#elif defined(__ICCARM__)
+    memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss"));
+#endif
+
+    /* Copy initialized RAM data from ROM to RAM. */
+#if defined(__ARMCC_VERSION)
+    memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
+#elif defined(__GNUC__)
+    memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
+#elif defined(__ICCARM__)
+    memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
+           (uint32_t) __section_size(".data"));
+
+    /* Copy functions to be executed from RAM. */
+ #pragma section=".code_in_ram"
+ #pragma section=".code_in_ram_init"
+    memcpy((uint32_t *) __section_begin(".code_in_ram"),
+           (uint32_t *) __section_begin(".code_in_ram_init"),
+           (uint32_t) __section_size(".code_in_ram"));
+
+    /* Copy main thread TLS to RAM. */
+ #pragma section="__DLIB_PERTHREAD_init"
+ #pragma section="__DLIB_PERTHREAD"
+    memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
+           (uint32_t) __section_size("__DLIB_PERTHREAD_init"));
+#endif
+
+    /* Disable MSP monitoring  */
+    R_MPU_SPMON->SP[0].CTL = 0;
+
+    /* Setup NMI interrupt  */
+    R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION;
+#if defined(__ICCARM__)
+
+    /* Setup start address  */
+    R_MPU_SPMON->SP[0].SA = (uint32_t) __section_begin(".stack");
+
+    /* Setup end address  */
+    R_MPU_SPMON->SP[0].EA = (uint32_t) __section_end(".stack");
+#elif defined(__ARMCC_VERSION)
+
+    /* Setup start address  */
+    R_MPU_SPMON->SP[0].SA = (uint32_t) &Image$$STACK$$RW$$Base;
+
+    /* Setup end address  */
+    R_MPU_SPMON->SP[0].EA = (uint32_t) &Image$$STACK$$RW$$Base + (uint32_t) &Image$$STACK$$RW$$Length;
+#elif defined(__GNUC__)
+
+    /* Setup start address  */
+    R_MPU_SPMON->SP[0].SA = (uint32_t) &__StackLimit;
+
+    /* Setup end address  */
+    R_MPU_SPMON->SP[0].EA = (uint32_t) &__StackTop;
+#endif
+
+    /* Disable stack monitoring for FreeRTOS. Not yet supported. */
+#if (BSP_CFG_RTOS == 0)
+
+    /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need
+     * to read-modify-write. */
+    R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;
+
+    /* Enable MSP monitoring  */
+    R_MPU_SPMON->SP[0].CTL = 1U;
+#endif
+
+    /* Initialize SystemCoreClock variable. */
+    SystemCoreClockUpdate();
+
+#if !BSP_CFG_PFS_PROTECT
+    R_PMISC->PWPR = 0;                              ///< Clear BOWI bit - writing to PFSWE bit enabled
+    R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
+#endif
+
+    /* Call Post C runtime initialization hook. */
+    R_BSP_WarmStart(BSP_WARM_START_POST_C);
+
+    /* Initialize static constructors */
+#if defined(__ARMCC_VERSION)
+    int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base;
+    for (int32_t i = 0; i < count; i++)
+    {
+        void (* p_init_func)(void) =
+            (void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
+        p_init_func();
+    }
+
+#elif defined(__GNUC__)
+    int32_t count = __init_array_end - __init_array_start;
+    for (int32_t i = 0; i < count; i++)
+    {
+        __init_array_start[i]();
+    }
+
+#elif defined(__ICCARM__)
+    void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
+    void const * ilimit = __section_end("SHT$$INIT_ARRAY");
+    __call_ctors(pibase, ilimit);
+#endif
+
+    /* Initialize ELC events that will be used to trigger NVIC interrupts. */
+    bsp_irq_cfg();
+
+    /* Call any BSP specific code. No arguments are needed so NULL is sent. */
+    bsp_init(NULL);
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.
+ * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
+ * implemented version. One of the main uses for this function is to call functional safety code during the startup
+ * process. To use this function just copy this function into your own code and modify it to meet your needs.
+ *
+ * @param[in]  event    Where the code currently is in the start up process
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+        /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
+    }
+
+    if (BSP_WARM_START_POST_CLOCK == event)
+    {
+        /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
+    }
+    else if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment, system clocks, and pins are all setup. */
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module
+ * is not in use.
+ **********************************************************************************************************************/
+#if BSP_FEATURE_BSP_RESET_TRNG
+static void bsp_reset_trng_circuit (void)
+{
+    volatile uint8_t read_port = 0U;
+    FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning
+
+    /* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
+     * of initial setting flow for an unused circuit") */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+
+    /* Enable TRNG function (disable stop function) */
+ #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
+    R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
+ #elif BSP_FEATURE_BSP_HAS_SCE5
+    R_BSP_MODULE_START(FSP_IP_SCE, 0);  ///< TRNG Module Stop needs to be started/stopped for RA4 series.
+ #else
+  #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
+ #endif
+
+    /* Wait for at least 3 PCLKB cycles */
+    read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
+    read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
+    read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
+
+    /* Disable TRNG function */
+ #if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
+    R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
+ #elif BSP_FEATURE_BSP_HAS_SCE5
+    R_BSP_MODULE_STOP(FSP_IP_SCE, 0);  ///< TRNG Module Stop needs to be started/stopped for RA4 series.
+ #else
+  #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
+ #endif
+
+    /* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
+     * of initial setting flow for an unused circuit") */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
new file mode 100644
index 0000000000..f3e97ceeaa
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -0,0 +1,945 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_clocks.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY                        (0xA500U)
+#define BSP_PRV_PRCR_UNLOCK                     ((BSP_PRV_PRCR_KEY) | 0x3U)
+#define BSP_PRV_PRCR_LOCK                       ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+#define BSP_PRV_MAXIMUM_HOCOWTR_HSTS            ((uint8_t) 0x6U)
+
+/* Wait state definitions for MEMWAIT. */
+#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES        (0U)
+#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES         (1U)
+#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ      (32000000U)
+
+/* Wait state definitions for FLDWAITR. */
+#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES        (0U)
+#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES        (1U)
+#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ      (32000000U)
+
+/* Temporary solution until R_FACI is added to renesas.h. */
+#define BSP_PRV_FLDWAITR_REG_ACCESS             (*((volatile uint8_t *) (0x407EFFC4U)))
+
+/* Wait state definitions for MCUS with SRAMWTSC and FLWT. */
+#define BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS     (60000000U)
+#define BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS    (40000000U)
+#define BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS    (80000000U)
+#define BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES       (0U)
+#define BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES        (0xEU)
+#define BSP_PRV_ROM_ZERO_WAIT_CYCLES            (0U)
+#define BSP_PRV_ROM_ONE_WAIT_CYCLES             (1U)
+#define BSP_PRV_ROM_TWO_WAIT_CYCLES             (2U)
+#define BSP_PRV_SRAM_PRCR_KEY                   (0x78U)
+#define BSP_PRV_SRAM_UNLOCK                     (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U)
+#define BSP_PRV_SRAM_LOCK                       (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U)
+
+/* Calculate value to write to MOMCR (MODRV controls main clock drive strength and MOSEL determines the source of the
+ * main oscillator). */
+#define BSP_PRV_MOMCR_MOSEL_BIT                 (6)
+#define BSP_PRV_MODRV                           ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \
+                                                 BSP_FEATURE_CGC_MODRV_MASK)
+#define BSP_PRV_MOSEL                           (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << BSP_PRV_MOMCR_MOSEL_BIT)
+#define BSP_PRV_MOMCR                           (BSP_PRV_MODRV | BSP_PRV_MOSEL)
+
+/* Locations of bitfields used to configure CLKOUT. */
+#define BSP_PRV_CKOCR_CKODIV_BIT                (4U)
+#define BSP_PRV_CKOCR_CKOEN_BIT                 (7U)
+
+/* Location of bitfield used to configure USB clock divider. */
+#define BSP_PRV_SCKDIVCR2_UCK_BIT               (4U)
+
+/* Calculate the value to write to SCKDIVCR. */
+#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS      ((BSP_CFG_ICLK_DIV & 7U) << 24U)
+#if BSP_FEATURE_CGC_HAS_PCLKD
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS    (BSP_CFG_PCLKD_DIV & 0x7U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS    (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKC
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS    ((BSP_CFG_PCLKC_DIV & 0x7U) << 4U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS    (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKB
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS    ((BSP_CFG_PCLKB_DIV & 0x7U) << 8U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS    (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKA
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS    ((BSP_CFG_PCLKA_DIV & 0x7U) << 12U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS    (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_BCLK
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS     ((BSP_CFG_BCLK_DIV & 0x7U) << 16U)
+#elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
+
+/* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS     ((BSP_CFG_PCLKB_DIV & 0x7U) << 16U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS     (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_FCLK
+ #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS     ((BSP_CFG_FCLK_DIV & 0x7U) << 28U)
+#else
+ #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS     (0U)
+#endif
+#define BSP_PRV_STARTUP_SCKDIVCR                (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS |  \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS |  \
+                                                 BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS)
+
+/* The number of clocks is used to size the g_clock_freq array. */
+#if BSP_PRV_PLL_SUPPORTED
+ #define BSP_PRV_NUM_CLOCKS                     ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + 1U)
+#else
+ #define BSP_PRV_NUM_CLOCKS                     ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U)
+#endif
+
+/* Frequencies of clocks with fixed freqencies. */
+#define BSP_PRV_LOCO_FREQ                       (32768U)   // LOCO frequency is fixed at 32768 Hz
+#define BSP_PRV_SUBCLOCK_FREQ                   (32768U)   // Subclock frequency is 32768 Hz
+#define BSP_PRV_MOCO_FREQ                       (8000000U) // MOCO frequency is fixed at 8 MHz
+
+/* Calculate PLLCCR value. */
+#if BSP_PRV_PLL_SUPPORTED
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+  #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
+   #define BSP_PRV_PLSRCSEL              (0)
+  #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+   #define BSP_PRV_PLSRCSEL              (1)
+  #endif
+  #define BSP_PRV_PLLCCR_PLLMUL_MASK     (0x3F) // PLLMUL in PLLCCR is 6 bits wide
+  #define BSP_PRV_PLLCCR_PLLMUL_BIT      (8)    // PLLMUL in PLLCCR starts at bit 8
+  #define BSP_PRV_PLLCCR_PLSRCSEL_BIT    (4)    // PLSRCSEL in PLLCCR starts at bit 4
+  #define BSP_PRV_PLLCCR                 ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) <<   \
+                                            BSP_PRV_PLLCCR_PLLMUL_BIT) |                        \
+                                           (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \
+                                          BSP_CFG_PLL_DIV)
+ #endif
+ #if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+  #define BSP_PRV_PLLCCR2_PLLMUL_MASK    (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide
+  #define BSP_PRV_PLLCCR2_PLODIV_BIT     (6)    // PLODIV in PLLCCR2 starts at bit 6
+
+  #define BSP_PRV_PLLCCR2_PLLMUL         (BSP_CFG_PLL_MUL >> 1)
+  #define BSP_PRV_PLLCCR                 (BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \
+    (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)
+ #endif
+#endif
+
+/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock
+ * frequency. */
+#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \
+    BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE
+ #define BSP_PRV_STARTUP_OPERATING_MODE    (BSP_PRV_OPERATING_MODE_LOW_SPEED)
+#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ
+ #define BSP_PRV_STARTUP_OPERATING_MODE    (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED)
+#else
+ #define BSP_PRV_STARTUP_OPERATING_MODE    (BSP_PRV_OPERATING_MODE_HIGH_SPEED)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz);
+static void    bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state);
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode);
+
+#endif
+
+#if !BSP_CFG_SOFT_RESET_SUPPORTED
+static void bsp_prv_clock_set_hard_reset(void);
+
+#endif
+
+/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C
+ * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime
+ * environment is initialized. */
+static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS]  BSP_PLACE_IN_SECTION(".noinit");
+
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+
+/* List of MSTP bits that must be set before entering low power modes or changing SCKDIVCR. */
+static const uint8_t g_bsp_prv_power_change_mstp_data[][2] = BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY;
+
+static const uint8_t g_bsp_prv_power_change_mstp_length = sizeof(g_bsp_prv_power_change_mstp_data) /
+                                                          sizeof(g_bsp_prv_power_change_mstp_data[0]);
+
+static volatile uint32_t * const gp_bsp_prv_mstp = &R_MSTP->MSTPCRB;
+#endif
+
+/*******************************************************************************************************************//**
+ * @internal
+ * @addtogroup BSP_MCU_PRV Internal BSP Documentation
+ * @ingroup RENESAS_INTERNAL
+ * @{
+ **********************************************************************************************************************/
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+
+/***********************************************************************************************************************
+ * Changes the operating speed in OPCCR.  Assumes the LPM registers are unlocked in PRCR and cache is off.
+ *
+ * @param[in]  operating_mode  Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be
+ *                             BSP_PRV_OPERATING_MODE_SUBOSC_SPEED
+ **********************************************************************************************************************/
+static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode)
+{
+ #if BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR
+
+    /* If the desired operating mode is already set, return. */
+    if (operating_mode == R_SYSTEM->OPCCR)
+    {
+        return;
+    }
+
+    /* On some MCUs, the HOCO must be stable before updating OPCCR.OPCM. */
+    if (0U == R_SYSTEM->HOCOCR)
+    {
+        /* Wait for HOCO to stabilize. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
+    }
+ #endif
+
+    /* Wait for transition to complete. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U);
+
+    /* Apply requested operating speed mode. */
+    R_SYSTEM->OPCCR = operating_mode;
+
+    /* Wait for transition to complete. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U);
+}
+
+#endif
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+
+/***********************************************************************************************************************
+ * Changes the operating speed mode.  Assumes the LPM registers are unlocked in PRCR and cache is off.
+ *
+ * @param[in]  operating_mode  Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros
+ **********************************************************************************************************************/
+void bsp_prv_operating_mode_set (uint8_t operating_mode)
+{
+    if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode)
+    {
+        /* Wait for transition to complete. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
+
+        /* Set subosc speed mode. */
+        R_SYSTEM->SOPCCR = 0x1U;
+
+        /* Wait for transition to complete. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
+    }
+    else
+    {
+        /* Wait for transition to complete. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U);
+
+        /* Exit subosc speed mode first. */
+        R_SYSTEM->SOPCCR = 0U;
+
+        /* Wait for transition to complete. Check the entire register here since it should be set to 0 at this point.
+         * Checking the entire register is slightly more efficient. This will also hang the program if the LPM
+         * registers are not unlocked, which can help catch programming errors. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U);
+
+        bsp_prv_operating_mode_opccr_set(operating_mode);
+    }
+}
+
+#endif
+
+#if BSP_PRV_PLL_SUPPORTED
+
+/***********************************************************************************************************************
+ * Updates the operating frequency of the PLL.
+ *
+ * @param[in] pll_freq_hz              New frequency of the PLL after the PLL is configured
+ **********************************************************************************************************************/
+void bsp_prv_prepare_pll (uint32_t pll_freq_hz)
+{
+    /* Store the PLL frequency, which is required to update SystemCoreClock after switching to PLL. */
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = pll_freq_hz;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Update SystemCoreClock variable based on current clock settings.
+ **********************************************************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+    uint32_t clock_index = R_SYSTEM->SCKSCR;
+    SystemCoreClock = g_clock_freq[clock_index] >> R_SYSTEM->SCKDIVCR_b.ICK;
+}
+
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+
+/*******************************************************************************************************************//**
+ * Sets MSTP bits as required by the hardware manual for the MCU (reference Figure 9.2 "Example flow for changing the
+ * value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100).
+ *
+ * This function must be called before entering standby or changing SCKDIVCR.
+ *
+ * @return bitmask of bits set, where each bit corresponds to an index in g_bsp_prv_power_change_mstp_data
+ **********************************************************************************************************************/
+uint32_t bsp_prv_power_change_mstp_set (void)
+{
+    uint32_t mstp_set_bitmask = 0U;
+    for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++)
+    {
+        /* Get the MSTP register index and the bit to test from the MCU specific array. */
+        uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0];
+        uint32_t mstp_bit   = 1U << g_bsp_prv_power_change_mstp_data[i][1];
+
+        /* Only set the bit if it's currently cleared. */
+        if (!(gp_bsp_prv_mstp[mstp_index] & mstp_bit))
+        {
+            gp_bsp_prv_mstp[mstp_index] |= mstp_bit;
+            mstp_set_bitmask            |= 1U << i;
+        }
+
+        /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being set. It was measured
+         * at 58 cycles for default IAR build configurations and 59 cycles for default GCC build configurations. */
+    }
+
+    /* The time between setting last MSTP bit and setting SCKDIVCR takes over 750 ns (90 cycles at 120 MHz). It was
+     * measured at 96 cycles for default IAR build configurations and 102 cycles for default GCC build
+     * configurations. */
+
+    return mstp_set_bitmask;
+}
+
+#endif
+
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+
+/*******************************************************************************************************************//**
+ * Clears MSTP bits set by bsp_prv_power_change_mstp_set as required by the hardware manual for the MCU (reference
+ * Figure 9.2 "Example flow for changing the value of SCKDIVCR" in the RA6M3 manual R01UH0886EJ0100).
+ *
+ * This function must be called after exiting standby or changing SCKDIVCR.
+ *
+ * @param[in] mstp_clear_bitmask       bitmask of bits to clear, where each bit corresponds to an index in
+ *                                     g_bsp_prv_power_change_mstp_data
+ **********************************************************************************************************************/
+void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask)
+{
+    /* The time between setting SCKDIVCR and clearing the first MSTP bit takes over 250 ns (30 cycles at 120 MHz). It
+     * was measured at 38 cycles for default IAR build configurations and 68 cycles for default GCC build
+     * configurations. */
+
+    for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++)
+    {
+        /* Only clear the bit if it was set in bsp_prv_power_change_mstp_set. */
+        if ((1U << i) & mstp_clear_bitmask)
+        {
+            /* Get the MSTP register index and the bit to test from the MCU specific array. */
+            uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0];
+            uint32_t mstp_bit   = 1U << g_bsp_prv_power_change_mstp_data[i][1];
+
+            gp_bsp_prv_mstp[mstp_index] &= ~mstp_bit;
+        }
+
+        /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being cleared. It was measured
+         * at 44 cycles for default IAR build configurations and 53 cycles for default GCC build configurations. */
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Applies system core clock source and divider changes.  The MCU is expected to be in high speed mode during this
+ * configuration and the CGC registers are expected to be unlocked in PRCR.
+ *
+ * @param[in] clock                    Desired system clock
+ * @param[in] sckdivcr                 Value to set in SCKDIVCR register
+ **********************************************************************************************************************/
+void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr)
+{
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+
+    /* Set MSTP bits as required by the hardware manual. This is done first to ensure the 750 ns delay required after
+     * increasing any division ratio in SCKDIVCR is met. */
+    uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set();
+#endif
+
+    uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
+
+    /* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be
+     * set is higher than before. */
+    uint32_t clock_freq_hz_post_change = g_clock_freq[clock] >> iclk_div;
+    uint8_t  new_rom_wait_state        = bsp_clock_set_prechange(clock_freq_hz_post_change);
+
+    /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
+     * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
+
+    /* If the current ICLK divider is less (higher frequency) than the requested ICLK divider, set the divider
+     * first. */
+    sckdivcr = sckdivcr & BSP_PRV_SCKDIVCR_MASK;
+    if (R_SYSTEM->SCKDIVCR_b.ICK < iclk_div)
+    {
+        /* Set the system dividers */
+        R_SYSTEM->SCKDIVCR = sckdivcr;
+
+        /* Set the system source clock */
+        R_SYSTEM->SCKSCR = (uint8_t) clock;
+    }
+
+    /* If the current ICLK divider is greater (lower frequency) than the requested ICLK divider, set the clock
+     * source first. If the ICLK divider is the same, order does not matter. */
+    else
+    {
+        /* Set the system source clock */
+        R_SYSTEM->SCKSCR = (uint8_t) clock;
+
+        /* Set the system dividers */
+        R_SYSTEM->SCKDIVCR = sckdivcr;
+    }
+
+    /* Clock is now at requested frequency. */
+
+    /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
+    SystemCoreClock = clock_freq_hz_post_change;
+
+    /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be
+     * set is lower than previous. */
+    bsp_clock_set_postchange(SystemCoreClock, new_rom_wait_state);
+
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+
+    /* Clear MSTP bits as required by the hardware manual. This is done last to ensure the 250 ns delay required after
+     * decreasing any division ratio in SCKDIVCR is met. */
+    bsp_prv_power_change_mstp_clear(mstp_set_bitmask);
+#endif
+}
+
+#if !BSP_CFG_SOFT_RESET_SUPPORTED
+
+static void bsp_prv_clock_set_hard_reset (void)
+{
+    /* Wait states in SRAMWTSC are set after hard reset. No change required here. */
+
+    /* Calculate the wait states for ROM */
+ #if BSP_FEATURE_CGC_HAS_FLWT
+  #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS
+
+    /* Do nothing. Default setting in FLWT is correct. */
+  #elif BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS
+    R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES;
+  #else
+    R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES;
+  #endif
+ #endif
+
+ #if BSP_FEATURE_CGC_HAS_MEMWAIT
+  #if BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ
+
+    /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */
+    R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES;
+  #endif
+ #endif
+
+ #if BSP_FEATURE_CGC_HAS_FLDWAITR
+  #if BSP_STARTUP_ICLK_HZ > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ
+
+    /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */
+    BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES;
+  #endif
+ #endif
+
+    /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and
+     * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */
+
+    /* ICLK divider at reset is lowest possible, so set dividers first. */
+
+    /* Set the system dividers first if ICLK divisor is larger than reset value. */
+ #if BSP_CFG_ICLK_DIV >= BSP_FEATURE_CGC_ICLK_DIV_RESET
+    R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
+
+    /* Set the system source clock */
+    R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE;
+
+    /* Set the system dividers after setting the system clock source if ICLK divisor is smaller than reset value. */
+ #if BSP_CFG_ICLK_DIV < BSP_FEATURE_CGC_ICLK_DIV_RESET
+    R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR;
+ #endif
+
+    /* Clock is now at requested frequency. */
+
+    /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
+    SystemCoreClockUpdate();
+
+    /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be
+     * set is lower than previous. */
+ #if BSP_FEATURE_CGC_HAS_SRAMWTSC
+  #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS
+    R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+    R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES;
+    R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
+  #endif
+ #endif
+
+    /* ROM wait states are 0 by default.  No change required here. */
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initializes system clocks.  Makes no assumptions about current register settings.
+ **********************************************************************************************************************/
+void bsp_clock_init (void)
+{
+    /* Unlock CGC and LPM protection registers. */
+    R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK;
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE
+
+    /* Disable ROM cache. */
+    R_FCACHE->FCACHEE = 0U;
+#endif
+#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
+
+    /* Disable the flash prefetch buffer. */
+    R_FACI_LP->PFBER = 0;
+#endif
+
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO]     = BSP_HOCO_HZ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO]     = BSP_PRV_MOCO_FREQ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO]     = BSP_PRV_LOCO_FREQ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ;
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_PRV_SUBCLOCK_FREQ;
+#if BSP_PRV_PLL_SUPPORTED
+
+    /* The PLL value will be calculated at initialization. */
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ;
+#endif
+
+    /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
+    SystemCoreClockUpdate();
+
+#if BSP_CFG_SOFT_RESET_SUPPORTED
+
+    /* Update the main oscillator drive, source, and wait states if the main oscillator is stopped.  If the main
+     * oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */
+    if (R_SYSTEM->MOSCCR)
+    {
+        /* Don't write to MOSCWTCR unless MOSTP is 1 and MOSCSF = 0. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 0U);
+
+        /* Configure main oscillator drive. */
+        R_SYSTEM->MOMCR = BSP_PRV_MOMCR;
+
+        /* Set the main oscillator wait time. */
+        R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT;
+    }
+#else
+
+    /* Configure main oscillator drive. */
+    R_SYSTEM->MOMCR = BSP_PRV_MOMCR;
+
+    /* Set the main oscillator wait time. */
+    R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT;
+#endif
+
+#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+
+    /* If the board has a subclock, set the subclock drive and start the subclock if the subclock is stopped.  If the
+     * subclock is running, the subclock drive is assumed to be set appropriately. */
+    if (R_SYSTEM->SOSCCR)
+    {
+        /* Configure the subclock drive if the subclock is not already running. */
+        R_SYSTEM->SOMCR  = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK);
+        R_SYSTEM->SOSCCR = 0U;
+ #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE
+
+        /* If the subclock is the system clock source, wait for it to stabilize. */
+        R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS);
+ #endif
+    }
+#else
+    R_SYSTEM->SOSCCR = 1U;
+#endif
+
+#if BSP_FEATURE_CGC_HAS_HOCOWTCR
+ #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY
+
+    /* These MCUs only require writes to HOCOWTCR if HOCO is set to 64 MHz. */
+  #if 64000000 == BSP_HOCO_HZ
+   #if BSP_CFG_USE_LOW_VOLTAGE_MODE
+
+    /* Wait for HOCO to stabilize before writing to HOCOWTCR. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
+   #else
+
+    /* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating
+     * power control mode. */
+   #endif
+    R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
+  #endif
+ #else
+
+    /* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode.  There is no restriction to
+     * writing this register. */
+    R_SYSTEM->HOCOWTCR = BSP_PRV_MAXIMUM_HOCOWTR_HSTS;
+ #endif
+#endif
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+
+    /* Switch to high-speed to prevent any issues with the subsequent clock configurations. */
+    bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
+ #elif BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ > 0U
+
+    /* MCUs that support low voltage mode start up in low voltage mode. */
+    bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED);
+
+  #if BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_CLOCK_SOURCE && BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE
+
+    /* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low
+     * voltage mode. */
+    R_SYSTEM->HOCOCR = 1U;
+  #endif
+ #endif
+#endif
+
+    /* If the PLL is the desired source clock, ensure the source clock is running and stable and the power mode
+     * allows PLL operation. */
+#if BSP_PRV_PLL_SUPPORTED
+ #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
+
+    /* Start PLL source clock. */
+  #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+    R_SYSTEM->HOCOCR = 0U;
+  #else
+    R_SYSTEM->MOSCCR = 0U;
+  #endif
+
+    /* Store PLL frequency. */
+    g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ;
+
+    /* Configure the PLL registers. */
+  #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE
+    R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR;
+  #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE
+    R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR;
+  #endif
+
+  #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0
+
+    /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some
+     * MCUs (see PLLSTP notes in Section 8.2.4 "PLL Control Register (PLLCR)" of the RA4M1 manual R01UH0887EJ0100).
+     * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of
+     * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running
+     * while setting PLLCCR. */
+    bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US));
+  #endif
+
+    /* Verify PLL source is stable before starting PLL. */
+  #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+
+    /* Wait for HOCO to stabilize. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
+  #else
+
+    /* Wait for main oscillator to stabilize. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
+  #endif
+ #endif
+#endif
+
+    /* Start source clock. */
+#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
+    R_SYSTEM->HOCOCR = 0U;
+
+    /* Wait for HOCO to stabilize. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U);
+#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+
+    /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */
+    if (0U != R_SYSTEM->MOCOCR)
+    {
+        R_SYSTEM->MOCOCR = 0U;
+        R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+    }
+ #endif
+#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+
+    /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */
+    if (0U != R_SYSTEM->LOCOCR)
+    {
+        R_SYSTEM->LOCOCR = 0U;
+        R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+    }
+ #else
+    R_SYSTEM->LOCOCR = 0U;
+    R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+ #endif
+#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
+    R_SYSTEM->MOSCCR = 0U;
+
+    /* Wait for main oscillator to stabilize. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U);
+#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
+    R_SYSTEM->PLLCR = 0U;
+
+    /* Wait for PLL to stabilize. */
+    FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U);
+#else
+
+    /* Do nothing. Subclock is already started and stabilized if it is populated and selected as system clock. */
+#endif
+
+    /* Set source clock and dividers. */
+#if BSP_CFG_SOFT_RESET_SUPPORTED
+    bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR);
+#else
+    bsp_prv_clock_set_hard_reset();
+#endif
+
+    /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+ #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED
+  #if BSP_PRV_PLL_SUPPORTED
+   #if BSP_CFG_SOFT_RESET_SUPPORTED
+    if (BSP_PRV_OPERATING_MODE_LOW_SPEED == BSP_PRV_STARTUP_OPERATING_MODE)
+    {
+        /* If the MCU has a PLL, ensure PLL is stopped and stable before entering low speed mode. */
+        R_SYSTEM->PLLCR = 1U;
+
+        /* Wait for PLL to stabilize. */
+        FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0U);
+    }
+   #endif
+  #endif
+    bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE);
+ #endif
+#endif
+
+    /* Set USB clock divisor if it exists on the MCU. */
+#ifdef BSP_CFG_UCK_DIV
+    R_SYSTEM->SCKDIVCR2 = BSP_CFG_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT;
+#endif
+
+#if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL
+
+    /* Some MCUs have an alternate register for selecting the USB clock source. */
+ #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT
+  #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCK_SOURCE
+
+    /* Write to USBCKCR to select the PLL. */
+    R_SYSTEM->USBCKCR = 0;
+  #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCK_SOURCE
+
+    /* Write to USBCKCR to select the HOCO. */
+    R_SYSTEM->USBCKCR = 1;
+  #endif
+ #endif
+#endif
+
+    /* Configure BCLK if it exists on the MCU. */
+#ifdef BSP_CFG_BCLK_OUTPUT
+ #if BSP_CFG_BCLK_OUTPUT > 0U
+    R_SYSTEM->BCKCR   = BSP_CFG_BCLK_OUTPUT - 1U;
+    R_SYSTEM->EBCKOCR = 1U;
+ #else
+  #if BSP_CFG_SOFT_RESET_SUPPORTED
+    R_SYSTEM->EBCKOCR = 0U;
+  #endif
+ #endif
+#endif
+
+    /* Configure SDRAM clock if it exists on the MCU. */
+#ifdef BSP_CFG_SDCLK_OUTPUT
+    R_SYSTEM->SDCKOCR = BSP_CFG_SDCLK_OUTPUT;
+#endif
+
+    /* Configure CLKOUT. */
+#if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLKOUT_DISABLED
+ #if BSP_CFG_SOFT_RESET_SUPPORTED
+    R_SYSTEM->CKOCR = 0U;
+ #endif
+#else
+    uint8_t ckocr = BSP_CFG_CLKOUT_SOURCE | (BSP_CFG_CLKOUT_DIV << BSP_PRV_CKOCR_CKODIV_BIT);
+    R_SYSTEM->CKOCR = ckocr;
+    ckocr          |= (1U << BSP_PRV_CKOCR_CKOEN_BIT);
+    R_SYSTEM->CKOCR = ckocr;
+#endif
+
+    /* Lock CGC and LPM protection registers. */
+    R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+
+#if BSP_FEATURE_BSP_FLASH_CACHE
+
+    /* Invalidate flash cache. */
+    R_FCACHE->FCACHEIV = 1U;
+    FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
+
+    /* Enable flash cache. */
+    R_FCACHE->FCACHEE = 1U;
+#endif
+
+#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
+    R_FACI_LP->PFBER = 1;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change.
+ *
+ * @param[in] requested_freq_hz        New core clock frequency after the clock change.
+ *
+ * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist).
+ **********************************************************************************************************************/
+static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz)
+{
+    uint8_t new_rom_wait_state = 0U;
+
+#if BSP_FEATURE_CGC_HAS_SRAMWTSC
+
+    /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */
+    if (requested_freq_hz > BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS)
+    {
+        R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+        R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES;
+        R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_FLWT
+
+    /* Calculate the wait states for ROM */
+    if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS)
+    {
+        new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES;
+    }
+    else if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS)
+    {
+        new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES;
+    }
+    else
+    {
+        new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES;
+    }
+
+    /* If more wait states are required after the change, then set the wait states before changing the clock. */
+    if (new_rom_wait_state > R_FCACHE->FLWT)
+    {
+        R_FCACHE->FLWT = new_rom_wait_state;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_MEMWAIT
+    if (requested_freq_hz > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ)
+    {
+        /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as
+         * a precondition to bsp_prv_clock_set. */
+        R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_FLDWAITR
+    if (requested_freq_hz > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ)
+    {
+        /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as
+         * a precondition to bsp_prv_clock_set. */
+        BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES;
+    }
+#endif
+
+    return new_rom_wait_state;
+}
+
+/*******************************************************************************************************************//**
+ * Decreases the ROM and RAM wait state settings to the minimum supported based on the applied clock change.
+ *
+ * @param[in] updated_freq_hz          New clock frequency after clock change
+ * @param[in] new_rom_wait_state       Optimal value for FLWT if it exists, 0 if FLWT does not exist on the MCU
+ **********************************************************************************************************************/
+static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_wait_state)
+{
+    /* These variables are unused for some MCUs. */
+    FSP_PARAMETER_NOT_USED(new_rom_wait_state);
+    FSP_PARAMETER_NOT_USED(updated_freq_hz);
+
+#if BSP_FEATURE_CGC_HAS_SRAMWTSC
+
+    /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */
+    if (updated_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS)
+    {
+        R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK;
+        R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES;
+        R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_FLWT
+    if (new_rom_wait_state != R_FCACHE->FLWT)
+    {
+        R_FCACHE->FLWT = new_rom_wait_state;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_MEMWAIT
+    if (updated_freq_hz <= BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ)
+    {
+        R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES;
+    }
+#endif
+
+#if BSP_FEATURE_CGC_HAS_FLDWAITR
+    if (updated_freq_hz <= BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ)
+    {
+        BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES;
+    }
+#endif
+}
+
+/** @} (end addtogroup BSP_MCU_PRV) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
new file mode 100644
index 0000000000..e2fd781def
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_clocks.h
@@ -0,0 +1,262 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_CLOCKS_H
+#define BSP_CLOCKS_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_clock_cfg.h"
+#include "bsp_api.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */
+/* Must match SCKCR.CKSEL values. */
+#define BSP_CLOCKS_SOURCE_CLOCK_HOCO        (0) // The high speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_MOCO        (1) // The middle speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_LOCO        (2) // The low speed on chip oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC    (3) // The main oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK    (4) // The subclock oscillator.
+#define BSP_CLOCKS_SOURCE_CLOCK_PLL         (5) // The PLL oscillator.
+
+/* PLL is not supported in the following scenarios:
+ *  - When using low voltage mode
+ *  - When using an MCU that does not have a PLL
+ *  - When the PLL only accepts the main oscillator as a source and XTAL is not used
+ */
+#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
+    !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
+ #define BSP_PRV_PLL_SUPPORTED              (1)
+#else
+ #define BSP_PRV_PLL_SUPPORTED              (0)
+#endif
+
+/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency
+ * calculated here is also used to initialize the g_clock_freq array. */
+#if BSP_PRV_PLL_SUPPORTED
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE)
+  #define BSP_PRV_PLL_SOURCE_FREQ_HZ           (BSP_HOCO_HZ)
+ #else
+  #define BSP_PRV_PLL_SOURCE_FREQ_HZ           (BSP_CFG_XTAL_HZ)
+ #endif
+#endif
+
+#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ           (BSP_HOCO_HZ)
+#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ           (BSP_PRV_MOCO_FREQ)
+#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ           (BSP_PRV_LOCO_FREQ)
+#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ           (BSP_PRV_SUBCLOCK_FREQ)
+#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
+ #define BSP_STARTUP_SOURCE_CLOCK_HZ           (BSP_CFG_XTAL_HZ)
+#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
+ #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+  #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
+   #define BSP_PRV_PLL_SOURCE_FREQ_HZ          (BSP_CFG_XTAL_HZ)
+  #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
+   #define BSP_PRV_PLL_SOURCE_FREQ_HZ          (BSP_HOCO_HZ)
+  #endif
+  #define BSP_STARTUP_SOURCE_CLOCK_HZ          (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \
+                                                (BSP_CFG_PLL_DIV + 1U))
+ #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
+  #define BSP_PRV_PLL_SOURCE_FREQ_HZ           (BSP_CFG_XTAL_HZ)
+  #define BSP_STARTUP_SOURCE_CLOCK_HZ          ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \
+                                                (BSP_CFG_PLL_DIV))
+ #endif
+#endif
+
+/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
+ * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
+#define BSP_STARTUP_ICLK_HZ                    (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV)
+#define BSP_STARTUP_PCLKA_HZ                   (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
+#define BSP_STARTUP_PCLKB_HZ                   (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
+#define BSP_STARTUP_PCLKC_HZ                   (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV)
+#define BSP_STARTUP_PCLKD_HZ                   (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
+#define BSP_STARTUP_BCLK_HZ                    (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV)
+#define BSP_STARTUP_FCLK_HZ                    (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV)
+
+/* System clock divider options. */
+#define BSP_CLOCKS_SYS_CLOCK_DIV_1             (0) // System clock divided by 1.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_2             (1) // System clock divided by 2.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_4             (2) // System clock divided by 4.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_8             (3) // System clock divided by 8.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_16            (4) // System clock divided by 16.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_32            (5) // System clock divided by 32.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_64            (6) // System clock divided by 64.
+#define BSP_CLOCKS_SYS_CLOCK_DIV_128           (7) // System clock divided by 128 (available for CLKOUT only).
+
+/* USB clock divider options. */
+#define BSP_CLOCKS_USB_CLOCK_DIV_3             (2) // Divide USB source clock by 3
+#define BSP_CLOCKS_USB_CLOCK_DIV_4             (3) // Divide USB source clock by 4
+#define BSP_CLOCKS_USB_CLOCK_DIV_5             (4) // Divide USB source clock by 5
+
+/* PLL divider options. */
+#define BSP_CLOCKS_PLL_DIV_1                   (0)
+#define BSP_CLOCKS_PLL_DIV_2                   (1)
+#define BSP_CLOCKS_PLL_DIV_3                   (2)
+#define BSP_CLOCKS_PLL_DIV_4                   (2)
+
+/* PLL multiplier options. */
+#define BSP_CLOCKS_PLL_MUL_8_0                 (0xF)
+#define BSP_CLOCKS_PLL_MUL_9_0                 (0x11)
+#define BSP_CLOCKS_PLL_MUL_10_0                (0x13)
+#define BSP_CLOCKS_PLL_MUL_10_5                (0x14)
+#define BSP_CLOCKS_PLL_MUL_11_0                (0x15)
+#define BSP_CLOCKS_PLL_MUL_11_5                (0x16)
+#define BSP_CLOCKS_PLL_MUL_12_0                (0x17)
+#define BSP_CLOCKS_PLL_MUL_12_5                (0x18)
+#define BSP_CLOCKS_PLL_MUL_13_0                (0x19)
+#define BSP_CLOCKS_PLL_MUL_13_5                (0x1A)
+#define BSP_CLOCKS_PLL_MUL_14_0                (0x1B)
+#define BSP_CLOCKS_PLL_MUL_14_5                (0x1c)
+#define BSP_CLOCKS_PLL_MUL_15_0                (0x1d)
+#define BSP_CLOCKS_PLL_MUL_15_5                (0x1e)
+#define BSP_CLOCKS_PLL_MUL_16_0                (0x1f)
+#define BSP_CLOCKS_PLL_MUL_16_5                (0x20)
+#define BSP_CLOCKS_PLL_MUL_17_0                (0x21)
+#define BSP_CLOCKS_PLL_MUL_17_5                (0x22)
+#define BSP_CLOCKS_PLL_MUL_18_0                (0x23)
+#define BSP_CLOCKS_PLL_MUL_18_5                (0x24)
+#define BSP_CLOCKS_PLL_MUL_19_0                (0x25)
+#define BSP_CLOCKS_PLL_MUL_19_5                (0x26)
+#define BSP_CLOCKS_PLL_MUL_20_0                (0x27)
+#define BSP_CLOCKS_PLL_MUL_20_5                (0x28)
+#define BSP_CLOCKS_PLL_MUL_21_0                (0x29)
+#define BSP_CLOCKS_PLL_MUL_21_5                (0x2A)
+#define BSP_CLOCKS_PLL_MUL_22_0                (0x2B)
+#define BSP_CLOCKS_PLL_MUL_22_5                (0x2c)
+#define BSP_CLOCKS_PLL_MUL_23_0                (0x2d)
+#define BSP_CLOCKS_PLL_MUL_23_5                (0x2e)
+#define BSP_CLOCKS_PLL_MUL_24_0                (0x2f)
+#define BSP_CLOCKS_PLL_MUL_24_5                (0x30)
+#define BSP_CLOCKS_PLL_MUL_25_0                (0x31)
+#define BSP_CLOCKS_PLL_MUL_25_5                (0x32)
+#define BSP_CLOCKS_PLL_MUL_26_0                (0x33)
+#define BSP_CLOCKS_PLL_MUL_26_5                (0x34)
+#define BSP_CLOCKS_PLL_MUL_27_0                (0x35)
+#define BSP_CLOCKS_PLL_MUL_27_5                (0x36)
+#define BSP_CLOCKS_PLL_MUL_28_0                (0x37)
+#define BSP_CLOCKS_PLL_MUL_28_5                (0x38)
+#define BSP_CLOCKS_PLL_MUL_29_0                (0x39)
+#define BSP_CLOCKS_PLL_MUL_29_5                (0x3A)
+#define BSP_CLOCKS_PLL_MUL_30_0                (0x3B)
+#define BSP_CLOCKS_PLL_MUL_31_0                (0x3D)
+
+/* Configuration option used to disable CLKOUT output. */
+#define BSP_CLOCKS_CLKOUT_DISABLED             (0xFFU)
+
+/* HOCO cycles per microsecond. */
+#define BSP_PRV_HOCO_CYCLES_PER_US             (BSP_HOCO_HZ / 1000000U)
+
+/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */
+#if BSP_HOCO_HZ < 48000000U
+ #define BSP_PRV_MAX_HOCO_CYCLES_PER_US        (BSP_PRV_HOCO_CYCLES_PER_US)
+#else
+ #define BSP_PRV_MAX_HOCO_CYCLES_PER_US        (48U)
+#endif
+
+/* Create a mask of valid bits in SCKDIVCR. */
+#define BSP_PRV_SCKDIVCR_ICLK_MASK             (7U << 24)
+#if BSP_FEATURE_CGC_HAS_PCLKD
+ #define BSP_PRV_SCKDIVCR_PCLKD_MASK           (7U << 0)
+#else
+ #define BSP_PRV_SCKDIVCR_PCLKD_MASK           (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKC
+ #define BSP_PRV_SCKDIVCR_PCLKC_MASK           (7U << 4)
+#else
+ #define BSP_PRV_SCKDIVCR_PCLKC_MASK           (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKB
+ #define BSP_PRV_SCKDIVCR_PCLKB_MASK           (7U << 8)
+#else
+ #define BSP_PRV_SCKDIVCR_PCLKB_MASK           (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_PCLKA
+ #define BSP_PRV_SCKDIVCR_PCLKA_MASK           (7U << 12)
+#else
+ #define BSP_PRV_SCKDIVCR_PCLKA_MASK           (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
+ #define BSP_PRV_SCKDIVCR_BCLK_MASK            (7U << 16)
+#else
+ #define BSP_PRV_SCKDIVCR_BCLK_MASK            (0U)
+#endif
+#if BSP_FEATURE_CGC_HAS_FCLK
+ #define BSP_PRV_SCKDIVCR_FCLK_MASK            (7U << 28)
+#else
+ #define BSP_PRV_SCKDIVCR_FCLK_MASK            (0U)
+#endif
+#define BSP_PRV_SCKDIVCR_MASK                  ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) |  \
+                                                    BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \
+                                                  BSP_PRV_SCKDIVCR_PCLKA_MASK) |                                  \
+                                                 BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK)
+
+/* Operating power control modes. */
+#define BSP_PRV_OPERATING_MODE_HIGH_SPEED      (0U) // Should match OPCCR OPCM high speed
+#define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED    (1U) // Should match OPCCR OPCM middle speed
+#define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE     (2U) // Should match OPCCR OPCM low voltage
+#define BSP_PRV_OPERATING_MODE_LOW_SPEED       (3U) // Should match OPCCR OPCM low speed
+#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED    (4U) // Can be any value not otherwise used
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_clock_init(void);             // Used internally by BSP
+
+/* Used internally by CGC */
+
+#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
+void bsp_prv_operating_mode_set(uint8_t operating_mode);
+
+#endif
+
+#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
+uint32_t bsp_prv_power_change_mstp_set(void);
+void     bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask);
+
+#endif
+
+void bsp_prv_prepare_pll(uint32_t pll_freq_hz);
+void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c
new file mode 100644
index 0000000000..e8e73f6338
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.c
@@ -0,0 +1,202 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ *
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if defined(__ICCARM__)
+ #define WEAK_ERROR_ATTRIBUTE
+ #define WEAK_INIT_ATTRIBUTE
+ #pragma weak fsp_error_log                            = fsp_error_log_internal
+ #pragma weak bsp_init                                 = bsp_init_internal
+#elif defined(__GNUC__)
+
+ #define WEAK_ERROR_ATTRIBUTE    __attribute__((weak, alias("fsp_error_log_internal")))
+
+ #define WEAK_INIT_ATTRIBUTE     __attribute__((weak, alias("bsp_init_internal")))
+#endif
+
+#define FSP_SECTION_VERSION      ".version"
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+/** Prototype of initialization function called before main.  This prototype sets the weak association of this
+ * function to an internal example implementation. If this function is defined in the application code, the
+ * application code version is used. */
+
+void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
+
+void bsp_init_internal(void * p_args); /// Default initialization function
+
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1.  This
+ * prototype sets the weak association of this function to an internal example implementation. */
+
+void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
+
+void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function
+
+#endif
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* BSP version structure. */
+const fsp_version_t g_bsp_version =
+{
+    .api_version_minor  = BSP_API_VERSION_MINOR,
+    .api_version_major  = BSP_API_VERSION_MAJOR,
+    .code_version_major = BSP_CODE_VERSION_MAJOR,
+    .code_version_minor = BSP_CODE_VERSION_MINOR
+};
+
+/* FSP pack version structure. */
+static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
+{
+    .minor = FSP_VERSION_MINOR,
+    .major = FSP_VERSION_MAJOR,
+    .build = FSP_VERSION_BUILD,
+    .patch = FSP_VERSION_PATCH
+};
+
+/* Public FSP version name. */
+static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
+    FSP_VERSION_STRING;
+
+/* Unique FSP version ID. */
+static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
+    FSP_VERSION_BUILD_STRING;
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Get the BSP version based on compile time macros.
+ *
+ * @param[out] p_version        Memory address to return version information to.
+ *
+ * @retval FSP_SUCCESS          Version information stored.
+ * @retval FSP_ERR_ASSERTION    The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_BSP_VersionGet (fsp_version_t * p_version)
+{
+#if BSP_CFG_PARAM_CHECKING_ENABLE
+
+    /** Verify parameters are valid */
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    p_version->api_version_major  = BSP_API_VERSION_MAJOR;
+    p_version->api_version_minor  = BSP_API_VERSION_MINOR;
+    p_version->code_version_major = BSP_CODE_VERSION_MAJOR;
+    p_version->code_version_minor = BSP_CODE_VERSION_MINOR;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get the FSP version based on compile time macros.
+ *
+ * @param[out] p_version        Memory address to return version information to.
+ *
+ * @retval FSP_SUCCESS          Version information stored.
+ * @retval FSP_ERR_ASSERTION    The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
+{
+#if BSP_CFG_PARAM_CHECKING_ENABLE
+
+    /** Verify parameters are valid */
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    *p_version = g_fsp_version;
+
+    return FSP_SUCCESS;
+}
+
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/*******************************************************************************************************************//**
+ * Default error logger function, used only if fsp_error_log is not defined in the user application.
+ *
+ * @param[in]  err     The error code encountered.
+ * @param[in]  file    The file name in which the error code was encountered.
+ * @param[in]  line    The line number at which the error code was encountered.
+ **********************************************************************************************************************/
+void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
+{
+    /** Do nothing. Do not generate any 'unused' warnings. */
+    FSP_PARAMETER_NOT_USED(err);
+    FSP_PARAMETER_NOT_USED(file);
+    FSP_PARAMETER_NOT_USED(line);
+}
+
+#endif
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ * Default initialization function, used only if bsp_init is not defined in the user application.
+ **********************************************************************************************************************/
+void bsp_init_internal (void * p_args)
+{
+    /* Do nothing. */
+    FSP_PARAMETER_NOT_USED(p_args);
+}
+
+#if defined(__ARMCC_VERSION)
+
+/*******************************************************************************************************************//**
+ * Default implementation of assert for AC6.
+ **********************************************************************************************************************/
+__attribute__((weak, noreturn))
+void __aeabi_assert (const char * expr, const char * file, int line) {
+    FSP_PARAMETER_NOT_USED(expr);
+    FSP_PARAMETER_NOT_USED(file);
+    FSP_PARAMETER_NOT_USED(line);
+    __BKPT(0);
+    while (1)
+    {
+        /* Do nothing. */
+    }
+}
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h
new file mode 100644
index 0000000000..7d4d63a2a5
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_common.h
@@ -0,0 +1,286 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_COMMON_H
+#define BSP_COMMON_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/* C99 includes. */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Different compiler support. */
+#include "../../inc/fsp_common_api.h"
+#include "bsp_compiler_support.h"
+#include "bsp_cfg.h"
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** Used to signify that an ELC event is not able to be used as an interrupt. */
+#define BSP_IRQ_DISABLED          (0xFFU)
+
+/* Version of this module's code and API. */
+#define BSP_CODE_VERSION_MAJOR    (1U)
+#define BSP_CODE_VERSION_MINOR    (1U)
+#define BSP_API_VERSION_MAJOR     (1U)
+#define BSP_API_VERSION_MINOR     (0U)
+
+#define FSP_CONTEXT_SAVE
+#define FSP_CONTEXT_RESTORE
+
+/** Macro to log and return error without an assertion. */
+#ifndef FSP_RETURN
+
+ #define FSP_RETURN(err)    FSP_ERROR_LOG((err)); \
+    return err;
+#endif
+
+/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
+ * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
+#if (1 == BSP_CFG_ERROR_LOG)
+
+ #ifndef FSP_ERROR_LOG
+  #define FSP_ERROR_LOG(err) \
+    fsp_error_log((err), __FILE__, __LINE__);
+ #endif
+#else
+
+ #define FSP_ERROR_LOG(err)
+#endif
+
+/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
+ * functions. */
+#if (3 == BSP_CFG_ASSERT)
+ #define FSP_ASSERT(a)
+#elif (2 == BSP_CFG_ASSERT)
+ #define FSP_ASSERT(a)    {assert(a);}
+#else
+ #define FSP_ASSERT(a)    FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
+#endif                                 // ifndef FSP_ASSERT
+
+/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
+ * to identify runtime errors in FSP functions. */
+
+#define FSP_ERROR_RETURN(a, err)                        \
+    {                                                   \
+        if ((a))                                        \
+        {                                               \
+            (void) 0;                  /* Do nothing */ \
+        }                                               \
+        else                                            \
+        {                                               \
+            FSP_ERROR_LOG(err);                         \
+            return err;                                 \
+        }                                               \
+    }
+
+/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
+ * This macro can be redefined to add a timeout if necessary. */
+#ifndef FSP_HARDWARE_REGISTER_WAIT
+ #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value)    while (reg != required_value) { /* Wait. */}
+#endif
+
+/** Version data structure used by error logger macro. */
+extern const fsp_version_t g_bsp_version;
+
+/****************************************************************
+ *
+ * This check is performed to select suitable ASM API with respect to core
+ *
+ * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
+ * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
+
+#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \
+    defined(__ARM_ARCH_7EM__)          // CM4
+ #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
+  #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION    (0U)
+ #endif
+#else // CM23
+ #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
+  #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
+ #endif
+ #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION    (0U)
+#endif
+
+/* This macro defines a variable for saving previous mask value */
+#ifndef FSP_CRITICAL_SECTION_DEFINE
+
+ #define FSP_CRITICAL_SECTION_DEFINE               uint32_t old_mask_level = 0U
+#endif
+
+/* These macros abstract methods to save and restore the interrupt state for different architectures. */
+#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
+ #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE    __get_PRIMASK
+ #define FSP_CRITICAL_SECTION_SET_STATE            __set_PRIMASK
+ #define FSP_CRITICAL_SECTION_IRQ_MASK_SET         (1U)
+#else
+ #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE    __get_BASEPRI
+ #define FSP_CRITICAL_SECTION_SET_STATE            __set_BASEPRI
+ #define FSP_CRITICAL_SECTION_IRQ_MASK_SET         ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
+                                                               (8U - __NVIC_PRIO_BITS)))
+#endif
+
+/** This macro temporarily saves the current interrupt state and disables interrupts. */
+#ifndef FSP_CRITICAL_SECTION_ENTER
+ #define FSP_CRITICAL_SECTION_ENTER                            \
+    old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
+    FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
+#endif
+
+/** This macro restores the previously saved interrupt state, reenabling interrupts. */
+#ifndef FSP_CRITICAL_SECTION_EXIT
+ #define FSP_CRITICAL_SECTION_EXIT              FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
+#endif
+
+/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
+#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS    (16U)
+
+/** Used to signify that the requested IRQ vector is not defined in this system. */
+#define FSP_INVALID_VECTOR                      ((IRQn_Type) - 33)
+
+/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */
+#define FSP_PRIV_SCKDIVCR_DIV_MASK              (7)
+
+#define BSP_MCU_INFO_POINTER_LOCATION           (0x407FB19C)
+#define BSP_UNIQUE_ID_OFFSET                    (0x14)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Different warm start entry locations in the BSP. */
+typedef enum e_bsp_warm_start_event
+{
+    BSP_WARM_START_RESET = 0,          ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
+    BSP_WARM_START_POST_CLOCK,         ///< Called after clock initialization. No C runtime environment or IRQs.
+    BSP_WARM_START_POST_C              ///< Called after clocks and C runtime environment have been set up
+} bsp_warm_start_event_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/* Private enum used in R_FSP_SystemClockHzGet.  Maps clock name to base bit in SCKDIVCR. */
+typedef enum e_fsp_priv_clock
+{
+    FSP_PRIV_CLOCK_PCLKD = 0,
+    FSP_PRIV_CLOCK_PCLKC = 4,
+    FSP_PRIV_CLOCK_PCLKB = 8,
+    FSP_PRIV_CLOCK_PCLKA = 12,
+    FSP_PRIV_CLOCK_BCLK  = 16,
+    FSP_PRIV_CLOCK_ICLK  = 24,
+    FSP_PRIV_CLOCK_FCLK  = 28,
+} fsp_priv_clock_t;
+
+typedef struct st_bsp_unique_id
+{
+    union
+    {
+        uint32_t unique_id_words[4];
+        uint8_t  unique_id_bytes[16];
+    };
+} bsp_unique_id_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Global variables (defined in other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Inline Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Return active interrupt vector number value
+ *
+ * @return     Active interrupt vector number value
+ **********************************************************************************************************************/
+__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
+{
+    xPSR_Type xpsr_value;
+    xpsr_value.w = __get_xPSR();
+
+    return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
+}
+
+/*******************************************************************************************************************//**
+ * Gets the frequency of a system clock.
+ *
+ * @return     Frequency of requested clock in Hertz.
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
+{
+    uint32_t sckdivcr  = R_SYSTEM->SCKDIVCR;
+    uint32_t iclk_div  = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
+    uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK;
+
+    return (SystemCoreClock << iclk_div) >> clock_div;
+}
+
+/*******************************************************************************************************************//**
+ * Get unique ID for this device.
+ *
+ * @return  A pointer to the unique identifier structure
+ **********************************************************************************************************************/
+__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
+{
+    return (bsp_unique_id_t *) ((*(uint32_t *) BSP_MCU_INFO_POINTER_LOCATION) + BSP_UNIQUE_ID_OFFSET);
+}
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
+
+/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
+void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
+
+#endif
+
+/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
+ *  alert the user of the error. The user can override this default behavior by defining their own
+ *  BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
+ */
+#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
+
+ #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)    __BKPT((x))
+#endif
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
new file mode 100644
index 0000000000..e0dfd42d06
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
@@ -0,0 +1,81 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_COMPILER_SUPPORT_H
+#define BSP_COMPILER_SUPPORT_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#if defined(__ARMCC_VERSION)           /* AC6 compiler */
+ #define BSP_SECTION_HEAP                  ".bss.heap"
+ #define BSP_DONT_REMOVE
+ #define BSP_ATTRIBUTE_STACKLESS           __attribute__((naked))
+ #define BSP_FORCE_INLINE                  __attribute__((always_inline))
+#elif   defined(__GNUC__)              /* GCC compiler */
+ #define BSP_SECTION_HEAP                  ".heap"
+ #define BSP_DONT_REMOVE
+ #define BSP_ATTRIBUTE_STACKLESS           __attribute__((naked))
+ #define BSP_FORCE_INLINE                  __attribute__((always_inline))
+#elif defined(__ICCARM__)              /* IAR compiler */
+ #define BSP_SECTION_HEAP                  "HEAP"
+ #define BSP_DONT_REMOVE                   __root
+ #define BSP_ATTRIBUTE_STACKLESS           __stackless
+ #define BSP_FORCE_INLINE                  _Pragma("inline=forced")
+#endif
+
+#define BSP_SECTION_STACK                  ".stack"
+#define BSP_SECTION_FIXED_VECTORS          ".fixed_vectors"
+#define BSP_SECTION_APPLICATION_VECTORS    ".application_vectors"
+#define BSP_SECTION_ROM_REGISTERS          ".rom_registers"
+#define BSP_SECTION_ID_CODE                ".id_code"
+
+/* Compiler neutral macros. */
+#define BSP_PLACE_IN_SECTION(x)    __attribute__((section(x))) __attribute__((__used__))
+
+#define BSP_ALIGN_VARIABLE(x)      __attribute__((aligned(x)))
+
+#define BSP_PACKED             __attribute__((aligned(1)))
+
+#define BSP_WEAK_REFERENCE     __attribute__((weak))
+
+/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
+#define BSP_STACK_ALIGNMENT    (8)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/** @} (end of addtogroup BSP_MCU) */
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c
new file mode 100644
index 0000000000..b8349c10fa
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.c
@@ -0,0 +1,166 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include "bsp_delay.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_DELAY_NS_PER_SECOND    (1000000000)
+#define BSP_DELAY_NS_PER_US        (1000)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ *              Delay for at least the specified duration in units and return.
+ * @param[in]   delay  The number of 'units' to delay.
+ * @param[in]   units  The 'base' (bsp_delay_units_t) for the units specified. Valid values are:
+ *              BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n
+ *              For example:@n
+ *              At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n
+ *              At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n
+ *              Therefore one run through bsp_prv_software_delay_loop() takes:
+ *              ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns.
+ *              A delay of 2 us therefore requires 2000ns/332ns or 6 loops.
+ *
+ *              The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate.
+ *              @120MHz:  ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds.
+ *              @32MHz:  ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds
+ *
+ *              Note that requests for very large delays will be affected by rounding in the calculations and the actual delay
+ *              achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.
+ *
+ *              Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called
+ *              at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
+ *              overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
+ *
+ *
+ * @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires
+ *       that the BSP has already initialized the CGC (which it does as part of the Sysinit).
+ *       Care should be taken to ensure this remains the case if in the future this function were to be called as part
+ *       of the BSP initialization.
+ **********************************************************************************************************************/
+
+void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
+{
+    uint32_t iclk_hz;
+    uint32_t cycles_requested;
+    uint32_t ns_per_cycle;
+    uint32_t loops_required = 0;
+    uint32_t total_us       = (delay * units);                        /** Convert the requested time to microseconds. */
+    uint64_t ns_64bits;
+
+    iclk_hz = SystemCoreClock;                                        /** Get the system clock frequency in Hz. */
+
+    /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution
+     * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting
+     * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single
+     * pass through the delay loop.  For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request
+     * will generate a minimum delay of ~200 us.*/
+    ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz;                 /** Get the # of nanoseconds/cycle. */
+
+    /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */
+    /* division as that pulls in a division library. */
+    ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
+
+    /* Have we overflowed 32 bits? */
+    if (ns_64bits <= UINT32_MAX)
+    {
+        /* No, we will not overflow. */
+        cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle);
+        loops_required   = cycles_requested / BSP_DELAY_LOOP_CYCLES;
+    }
+    else
+    {
+        /* We did overflow. Try dividing down first. */
+        total_us  = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES));
+        ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
+
+        /* Have we overflowed 32 bits? */
+        if (ns_64bits <= UINT32_MAX)
+        {
+            /* No, we will not overflow. */
+            loops_required = (uint32_t) ns_64bits;
+        }
+        else
+        {
+            /* We still overflowed, use the max count for cycles */
+            loops_required = UINT32_MAX;
+        }
+    }
+
+    /** Only delay if the supplied parameters constitute a delay. */
+    if (loops_required > (uint32_t) 0)
+    {
+        bsp_prv_software_delay_loop(loops_required);
+    }
+}
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ *        This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
+ *        occur when the loop exits. The 'naked' attribute  indicates that the specified function does not need
+ *        prologue/epilogue sequences generated by the compiler.
+ * @param[in]     loop_cnt  The number of loops to iterate.
+ **********************************************************************************************************************/
+BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
+{
+    __asm volatile ("sw_delay_loop:         \n"
+
+#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
+                    "   subs r0, #1         \n"   ///< 1 cycle
+#elif defined(__GNUC__)
+                    "   sub r0, r0, #1      \n"   ///< 1 cycle
+#endif
+
+                    "   cmp r0, #0          \n"   ///< 1 cycle
+
+/* CM0 and CM23 have a different instruction set */
+#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
+                    "   bne sw_delay_loop   \n"   ///< 2 cycles
+#else
+                    "   bne.n sw_delay_loop \n"   ///< 2 cycles
+#endif
+                    "   bx lr               \n"); ///< 2 cycles
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h
new file mode 100644
index 0000000000..e4bbe015a3
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_delay.h
@@ -0,0 +1,75 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_DELAY_H
+#define BSP_DELAY_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#include "bsp_compiler_support.h"
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* The number of cycles required per software delay loop. */
+#ifndef BSP_DELAY_LOOP_CYCLES
+ #define BSP_DELAY_LOOP_CYCLES    (4)
+#endif
+
+/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle
+ * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures
+ * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count
+ * of 0. */
+#define BSP_DELAY_LOOPS_CALCULATE(cycles)    (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U)
+
+/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */
+typedef enum
+{
+    BSP_DELAY_UNITS_SECONDS      = 1000000, ///< Requested delay amount is in seconds
+    BSP_DELAY_UNITS_MILLISECONDS = 1000,    ///< Requested delay amount is in milliseconds
+    BSP_DELAY_UNITS_MICROSECONDS = 1        ///< Requested delay amount is in microseconds
+} bsp_delay_units_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
new file mode 100644
index 0000000000..5098697f37
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c
@@ -0,0 +1,121 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_GRP_IRQ_TOTAL_ITEMS    (13U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** This array holds callback functions. */
+static bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] = {0};
+
+void        NMI_Handler(void);
+static void bsp_group_irq_call(bsp_grp_irq_t irq);
+
+/*******************************************************************************************************************//**
+ * Calls the callback function for an interrupt if a callback has been registered.
+ *
+ * @param[in]   irq         Which interrupt to check and possibly call.
+ *
+ * @retval FSP_SUCCESS              Callback was called.
+ * @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source.
+ *
+ * @warning This function is called from within an interrupt
+ **********************************************************************************************************************/
+static void bsp_group_irq_call (bsp_grp_irq_t irq)
+{
+    /** Check for valid callback */
+    if (NULL != g_bsp_group_irq_sources[irq])
+    {
+        /** Callback has been found. Call it. */
+        g_bsp_group_irq_sources[irq](irq);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any
+ * previously registered callbacks are unregistered.
+ *
+ * @param[in]  irq          Interrupt for which  to register a callback.
+ * @param[in]  p_callback   Pointer to function to call when interrupt occurs.
+ *
+ * @retval     FSP_SUCCESS                  Callback registered
+ * @retval     FSP_ERR_ASSERTION            Callback pointer is NULL
+ **********************************************************************************************************************/
+fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq))
+{
+#if BSP_CFG_PARAM_CHECKING_ENABLE
+
+    /* Check pointer for NULL value. */
+    FSP_ASSERT(p_callback);
+#endif
+
+    /* Register callback. */
+    g_bsp_group_irq_sources[irq] = p_callback;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because
+ * there are many sources that map to the NMI exception.
+ **********************************************************************************************************************/
+void NMI_Handler (void)
+{
+    uint16_t nmisr = R_ICU->NMISR;
+
+    /* Loop over all NMI status flags */
+    for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_MPU_STACK; irq++)
+    {
+        /* If the current irq status register is set call the irq callback. */
+        if (0U != (nmisr & (1U << irq)))
+        {
+            (void) bsp_group_irq_call(irq);
+        }
+    }
+
+    /* Clear status flags that have been handled. */
+    R_ICU->NMICLR = nmisr;
+}
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
new file mode 100644
index 0000000000..a51e154e5f
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
@@ -0,0 +1,77 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_GROUP_IRQ_H
+#define BSP_GROUP_IRQ_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Which interrupts can have callbacks registered. */
+typedef enum e_bsp_grp_irq
+{
+    BSP_GRP_IRQ_IWDT_ERROR      = 0,   ///< IWDT underflow/refresh error has occurred
+    BSP_GRP_IRQ_WDT_ERROR       = 1,   ///< WDT underflow/refresh error has occurred
+    BSP_GRP_IRQ_LVD1            = 2,   ///< Voltage monitoring 1 interrupt
+    BSP_GRP_IRQ_LVD2            = 3,   ///< Voltage monitoring 2 interrupt
+    BSP_GRP_IRQ_VBATT           = 4,   ///< VBATT monitor interrupt
+    BSP_GRP_IRQ_OSC_STOP_DETECT = 6,   ///< Oscillation stop is detected
+    BSP_GRP_IRQ_NMI_PIN         = 7,   ///< NMI Pin interrupt
+    BSP_GRP_IRQ_RAM_PARITY      = 8,   ///< RAM Parity Error
+    BSP_GRP_IRQ_RAM_ECC         = 9,   ///< RAM ECC Error
+    BSP_GRP_IRQ_MPU_BUS_SLAVE   = 10,  ///< MPU Bus Slave Error
+    BSP_GRP_IRQ_MPU_BUS_MASTER  = 11,  ///< MPU Bus Master Error
+    BSP_GRP_IRQ_MPU_STACK       = 12,  ///< MPU Stack Error
+} bsp_grp_irq_t;
+
+/* Callback type. */
+typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq);
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_group_interrupt_open(void);   // Used internally by BSP
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c
new file mode 100644
index 0000000000..66c88ca851
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.c
@@ -0,0 +1,41 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+volatile uint32_t g_protect_pfswe_counter;
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h
new file mode 100644
index 0000000000..4eec4289d6
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_io.h
@@ -0,0 +1,387 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @defgroup BSP_IO BSP I/O access
+ * @ingroup RENESAS_COMMON
+ * @brief This module provides basic read/write access to port pins.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef BSP_IO_H
+#define BSP_IO_H
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Private definition to set enumeration values. */
+#define BSP_IO_PRV_PFS_PSEL_OFFSET    (24)
+#define BSP_IO_PRV_8BIT_MASK          (0xFF)
+#define BSP_IO_PWPR_B0WI_OFFSET       (7U)
+#define BSP_IO_PWPR_PFSWE_OFFSET      (6U)
+#define BSP_IO_PFS_PDR_OUTPUT         (4U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/** Levels that can be set and read for individual pins */
+typedef enum e_bsp_io_level
+{
+    BSP_IO_LEVEL_LOW = 0,              ///< Low
+    BSP_IO_LEVEL_HIGH                  ///< High
+} bsp_io_level_t;
+
+/** Direction of individual pins */
+typedef enum e_bsp_io_dir
+{
+    BSP_IO_DIRECTION_INPUT = 0,        ///< Input
+    BSP_IO_DIRECTION_OUTPUT            ///< Output
+} bsp_io_direction_t;
+
+/** Superset list of all possible IO ports. */
+typedef enum e_bsp_io_port
+{
+    BSP_IO_PORT_00 = 0x0000,           ///< IO port 0
+    BSP_IO_PORT_01 = 0x0100,           ///< IO port 1
+    BSP_IO_PORT_02 = 0x0200,           ///< IO port 2
+    BSP_IO_PORT_03 = 0x0300,           ///< IO port 3
+    BSP_IO_PORT_04 = 0x0400,           ///< IO port 4
+    BSP_IO_PORT_05 = 0x0500,           ///< IO port 5
+    BSP_IO_PORT_06 = 0x0600,           ///< IO port 6
+    BSP_IO_PORT_07 = 0x0700,           ///< IO port 7
+    BSP_IO_PORT_08 = 0x0800,           ///< IO port 8
+    BSP_IO_PORT_09 = 0x0900,           ///< IO port 9
+    BSP_IO_PORT_10 = 0x0A00,           ///< IO port 10
+    BSP_IO_PORT_11 = 0x0B00,           ///< IO port 11
+} bsp_io_port_t;
+
+/** Superset list of all possible IO port pins. */
+typedef enum e_bsp_io_port_pin_t
+{
+    BSP_IO_PORT_00_PIN_00 = 0x0000,    ///< IO port 0 pin 0
+    BSP_IO_PORT_00_PIN_01 = 0x0001,    ///< IO port 0 pin 1
+    BSP_IO_PORT_00_PIN_02 = 0x0002,    ///< IO port 0 pin 2
+    BSP_IO_PORT_00_PIN_03 = 0x0003,    ///< IO port 0 pin 3
+    BSP_IO_PORT_00_PIN_04 = 0x0004,    ///< IO port 0 pin 4
+    BSP_IO_PORT_00_PIN_05 = 0x0005,    ///< IO port 0 pin 5
+    BSP_IO_PORT_00_PIN_06 = 0x0006,    ///< IO port 0 pin 6
+    BSP_IO_PORT_00_PIN_07 = 0x0007,    ///< IO port 0 pin 7
+    BSP_IO_PORT_00_PIN_08 = 0x0008,    ///< IO port 0 pin 8
+    BSP_IO_PORT_00_PIN_09 = 0x0009,    ///< IO port 0 pin 9
+    BSP_IO_PORT_00_PIN_10 = 0x000A,    ///< IO port 0 pin 10
+    BSP_IO_PORT_00_PIN_11 = 0x000B,    ///< IO port 0 pin 11
+    BSP_IO_PORT_00_PIN_12 = 0x000C,    ///< IO port 0 pin 12
+    BSP_IO_PORT_00_PIN_13 = 0x000D,    ///< IO port 0 pin 13
+    BSP_IO_PORT_00_PIN_14 = 0x000E,    ///< IO port 0 pin 14
+    BSP_IO_PORT_00_PIN_15 = 0x000F,    ///< IO port 0 pin 15
+
+    BSP_IO_PORT_01_PIN_00 = 0x0100,    ///< IO port 1 pin 0
+    BSP_IO_PORT_01_PIN_01 = 0x0101,    ///< IO port 1 pin 1
+    BSP_IO_PORT_01_PIN_02 = 0x0102,    ///< IO port 1 pin 2
+    BSP_IO_PORT_01_PIN_03 = 0x0103,    ///< IO port 1 pin 3
+    BSP_IO_PORT_01_PIN_04 = 0x0104,    ///< IO port 1 pin 4
+    BSP_IO_PORT_01_PIN_05 = 0x0105,    ///< IO port 1 pin 5
+    BSP_IO_PORT_01_PIN_06 = 0x0106,    ///< IO port 1 pin 6
+    BSP_IO_PORT_01_PIN_07 = 0x0107,    ///< IO port 1 pin 7
+    BSP_IO_PORT_01_PIN_08 = 0x0108,    ///< IO port 1 pin 8
+    BSP_IO_PORT_01_PIN_09 = 0x0109,    ///< IO port 1 pin 9
+    BSP_IO_PORT_01_PIN_10 = 0x010A,    ///< IO port 1 pin 10
+    BSP_IO_PORT_01_PIN_11 = 0x010B,    ///< IO port 1 pin 11
+    BSP_IO_PORT_01_PIN_12 = 0x010C,    ///< IO port 1 pin 12
+    BSP_IO_PORT_01_PIN_13 = 0x010D,    ///< IO port 1 pin 13
+    BSP_IO_PORT_01_PIN_14 = 0x010E,    ///< IO port 1 pin 14
+    BSP_IO_PORT_01_PIN_15 = 0x010F,    ///< IO port 1 pin 15
+
+    BSP_IO_PORT_02_PIN_00 = 0x0200,    ///< IO port 2 pin 0
+    BSP_IO_PORT_02_PIN_01 = 0x0201,    ///< IO port 2 pin 1
+    BSP_IO_PORT_02_PIN_02 = 0x0202,    ///< IO port 2 pin 2
+    BSP_IO_PORT_02_PIN_03 = 0x0203,    ///< IO port 2 pin 3
+    BSP_IO_PORT_02_PIN_04 = 0x0204,    ///< IO port 2 pin 4
+    BSP_IO_PORT_02_PIN_05 = 0x0205,    ///< IO port 2 pin 5
+    BSP_IO_PORT_02_PIN_06 = 0x0206,    ///< IO port 2 pin 6
+    BSP_IO_PORT_02_PIN_07 = 0x0207,    ///< IO port 2 pin 7
+    BSP_IO_PORT_02_PIN_08 = 0x0208,    ///< IO port 2 pin 8
+    BSP_IO_PORT_02_PIN_09 = 0x0209,    ///< IO port 2 pin 9
+    BSP_IO_PORT_02_PIN_10 = 0x020A,    ///< IO port 2 pin 10
+    BSP_IO_PORT_02_PIN_11 = 0x020B,    ///< IO port 2 pin 11
+    BSP_IO_PORT_02_PIN_12 = 0x020C,    ///< IO port 2 pin 12
+    BSP_IO_PORT_02_PIN_13 = 0x020D,    ///< IO port 2 pin 13
+    BSP_IO_PORT_02_PIN_14 = 0x020E,    ///< IO port 2 pin 14
+    BSP_IO_PORT_02_PIN_15 = 0x020F,    ///< IO port 2 pin 15
+
+    BSP_IO_PORT_03_PIN_00 = 0x0300,    ///< IO port 3 pin 0
+    BSP_IO_PORT_03_PIN_01 = 0x0301,    ///< IO port 3 pin 1
+    BSP_IO_PORT_03_PIN_02 = 0x0302,    ///< IO port 3 pin 2
+    BSP_IO_PORT_03_PIN_03 = 0x0303,    ///< IO port 3 pin 3
+    BSP_IO_PORT_03_PIN_04 = 0x0304,    ///< IO port 3 pin 4
+    BSP_IO_PORT_03_PIN_05 = 0x0305,    ///< IO port 3 pin 5
+    BSP_IO_PORT_03_PIN_06 = 0x0306,    ///< IO port 3 pin 6
+    BSP_IO_PORT_03_PIN_07 = 0x0307,    ///< IO port 3 pin 7
+    BSP_IO_PORT_03_PIN_08 = 0x0308,    ///< IO port 3 pin 8
+    BSP_IO_PORT_03_PIN_09 = 0x0309,    ///< IO port 3 pin 9
+    BSP_IO_PORT_03_PIN_10 = 0x030A,    ///< IO port 3 pin 10
+    BSP_IO_PORT_03_PIN_11 = 0x030B,    ///< IO port 3 pin 11
+    BSP_IO_PORT_03_PIN_12 = 0x030C,    ///< IO port 3 pin 12
+    BSP_IO_PORT_03_PIN_13 = 0x030D,    ///< IO port 3 pin 13
+    BSP_IO_PORT_03_PIN_14 = 0x030E,    ///< IO port 3 pin 14
+    BSP_IO_PORT_03_PIN_15 = 0x030F,    ///< IO port 3 pin 15
+
+    BSP_IO_PORT_04_PIN_00 = 0x0400,    ///< IO port 4 pin 0
+    BSP_IO_PORT_04_PIN_01 = 0x0401,    ///< IO port 4 pin 1
+    BSP_IO_PORT_04_PIN_02 = 0x0402,    ///< IO port 4 pin 2
+    BSP_IO_PORT_04_PIN_03 = 0x0403,    ///< IO port 4 pin 3
+    BSP_IO_PORT_04_PIN_04 = 0x0404,    ///< IO port 4 pin 4
+    BSP_IO_PORT_04_PIN_05 = 0x0405,    ///< IO port 4 pin 5
+    BSP_IO_PORT_04_PIN_06 = 0x0406,    ///< IO port 4 pin 6
+    BSP_IO_PORT_04_PIN_07 = 0x0407,    ///< IO port 4 pin 7
+    BSP_IO_PORT_04_PIN_08 = 0x0408,    ///< IO port 4 pin 8
+    BSP_IO_PORT_04_PIN_09 = 0x0409,    ///< IO port 4 pin 9
+    BSP_IO_PORT_04_PIN_10 = 0x040A,    ///< IO port 4 pin 10
+    BSP_IO_PORT_04_PIN_11 = 0x040B,    ///< IO port 4 pin 11
+    BSP_IO_PORT_04_PIN_12 = 0x040C,    ///< IO port 4 pin 12
+    BSP_IO_PORT_04_PIN_13 = 0x040D,    ///< IO port 4 pin 13
+    BSP_IO_PORT_04_PIN_14 = 0x040E,    ///< IO port 4 pin 14
+    BSP_IO_PORT_04_PIN_15 = 0x040F,    ///< IO port 4 pin 15
+
+    BSP_IO_PORT_05_PIN_00 = 0x0500,    ///< IO port 5 pin 0
+    BSP_IO_PORT_05_PIN_01 = 0x0501,    ///< IO port 5 pin 1
+    BSP_IO_PORT_05_PIN_02 = 0x0502,    ///< IO port 5 pin 2
+    BSP_IO_PORT_05_PIN_03 = 0x0503,    ///< IO port 5 pin 3
+    BSP_IO_PORT_05_PIN_04 = 0x0504,    ///< IO port 5 pin 4
+    BSP_IO_PORT_05_PIN_05 = 0x0505,    ///< IO port 5 pin 5
+    BSP_IO_PORT_05_PIN_06 = 0x0506,    ///< IO port 5 pin 6
+    BSP_IO_PORT_05_PIN_07 = 0x0507,    ///< IO port 5 pin 7
+    BSP_IO_PORT_05_PIN_08 = 0x0508,    ///< IO port 5 pin 8
+    BSP_IO_PORT_05_PIN_09 = 0x0509,    ///< IO port 5 pin 9
+    BSP_IO_PORT_05_PIN_10 = 0x050A,    ///< IO port 5 pin 10
+    BSP_IO_PORT_05_PIN_11 = 0x050B,    ///< IO port 5 pin 11
+    BSP_IO_PORT_05_PIN_12 = 0x050C,    ///< IO port 5 pin 12
+    BSP_IO_PORT_05_PIN_13 = 0x050D,    ///< IO port 5 pin 13
+    BSP_IO_PORT_05_PIN_14 = 0x050E,    ///< IO port 5 pin 14
+    BSP_IO_PORT_05_PIN_15 = 0x050F,    ///< IO port 5 pin 15
+
+    BSP_IO_PORT_06_PIN_00 = 0x0600,    ///< IO port 6 pin 0
+    BSP_IO_PORT_06_PIN_01 = 0x0601,    ///< IO port 6 pin 1
+    BSP_IO_PORT_06_PIN_02 = 0x0602,    ///< IO port 6 pin 2
+    BSP_IO_PORT_06_PIN_03 = 0x0603,    ///< IO port 6 pin 3
+    BSP_IO_PORT_06_PIN_04 = 0x0604,    ///< IO port 6 pin 4
+    BSP_IO_PORT_06_PIN_05 = 0x0605,    ///< IO port 6 pin 5
+    BSP_IO_PORT_06_PIN_06 = 0x0606,    ///< IO port 6 pin 6
+    BSP_IO_PORT_06_PIN_07 = 0x0607,    ///< IO port 6 pin 7
+    BSP_IO_PORT_06_PIN_08 = 0x0608,    ///< IO port 6 pin 8
+    BSP_IO_PORT_06_PIN_09 = 0x0609,    ///< IO port 6 pin 9
+    BSP_IO_PORT_06_PIN_10 = 0x060A,    ///< IO port 6 pin 10
+    BSP_IO_PORT_06_PIN_11 = 0x060B,    ///< IO port 6 pin 11
+    BSP_IO_PORT_06_PIN_12 = 0x060C,    ///< IO port 6 pin 12
+    BSP_IO_PORT_06_PIN_13 = 0x060D,    ///< IO port 6 pin 13
+    BSP_IO_PORT_06_PIN_14 = 0x060E,    ///< IO port 6 pin 14
+    BSP_IO_PORT_06_PIN_15 = 0x060F,    ///< IO port 6 pin 15
+
+    BSP_IO_PORT_07_PIN_00 = 0x0700,    ///< IO port 7 pin 0
+    BSP_IO_PORT_07_PIN_01 = 0x0701,    ///< IO port 7 pin 1
+    BSP_IO_PORT_07_PIN_02 = 0x0702,    ///< IO port 7 pin 2
+    BSP_IO_PORT_07_PIN_03 = 0x0703,    ///< IO port 7 pin 3
+    BSP_IO_PORT_07_PIN_04 = 0x0704,    ///< IO port 7 pin 4
+    BSP_IO_PORT_07_PIN_05 = 0x0705,    ///< IO port 7 pin 5
+    BSP_IO_PORT_07_PIN_06 = 0x0706,    ///< IO port 7 pin 6
+    BSP_IO_PORT_07_PIN_07 = 0x0707,    ///< IO port 7 pin 7
+    BSP_IO_PORT_07_PIN_08 = 0x0708,    ///< IO port 7 pin 8
+    BSP_IO_PORT_07_PIN_09 = 0x0709,    ///< IO port 7 pin 9
+    BSP_IO_PORT_07_PIN_10 = 0x070A,    ///< IO port 7 pin 10
+    BSP_IO_PORT_07_PIN_11 = 0x070B,    ///< IO port 7 pin 11
+    BSP_IO_PORT_07_PIN_12 = 0x070C,    ///< IO port 7 pin 12
+    BSP_IO_PORT_07_PIN_13 = 0x070D,    ///< IO port 7 pin 13
+    BSP_IO_PORT_07_PIN_14 = 0x070E,    ///< IO port 7 pin 14
+    BSP_IO_PORT_07_PIN_15 = 0x070F,    ///< IO port 7 pin 15
+
+    BSP_IO_PORT_08_PIN_00 = 0x0800,    ///< IO port 8 pin 0
+    BSP_IO_PORT_08_PIN_01 = 0x0801,    ///< IO port 8 pin 1
+    BSP_IO_PORT_08_PIN_02 = 0x0802,    ///< IO port 8 pin 2
+    BSP_IO_PORT_08_PIN_03 = 0x0803,    ///< IO port 8 pin 3
+    BSP_IO_PORT_08_PIN_04 = 0x0804,    ///< IO port 8 pin 4
+    BSP_IO_PORT_08_PIN_05 = 0x0805,    ///< IO port 8 pin 5
+    BSP_IO_PORT_08_PIN_06 = 0x0806,    ///< IO port 8 pin 6
+    BSP_IO_PORT_08_PIN_07 = 0x0807,    ///< IO port 8 pin 7
+    BSP_IO_PORT_08_PIN_08 = 0x0808,    ///< IO port 8 pin 8
+    BSP_IO_PORT_08_PIN_09 = 0x0809,    ///< IO port 8 pin 9
+    BSP_IO_PORT_08_PIN_10 = 0x080A,    ///< IO port 8 pin 10
+    BSP_IO_PORT_08_PIN_11 = 0x080B,    ///< IO port 8 pin 11
+    BSP_IO_PORT_08_PIN_12 = 0x080C,    ///< IO port 8 pin 12
+    BSP_IO_PORT_08_PIN_13 = 0x080D,    ///< IO port 8 pin 13
+    BSP_IO_PORT_08_PIN_14 = 0x080E,    ///< IO port 8 pin 14
+    BSP_IO_PORT_08_PIN_15 = 0x080F,    ///< IO port 8 pin 15
+
+    BSP_IO_PORT_09_PIN_00 = 0x0900,    ///< IO port 9 pin 0
+    BSP_IO_PORT_09_PIN_01 = 0x0901,    ///< IO port 9 pin 1
+    BSP_IO_PORT_09_PIN_02 = 0x0902,    ///< IO port 9 pin 2
+    BSP_IO_PORT_09_PIN_03 = 0x0903,    ///< IO port 9 pin 3
+    BSP_IO_PORT_09_PIN_04 = 0x0904,    ///< IO port 9 pin 4
+    BSP_IO_PORT_09_PIN_05 = 0x0905,    ///< IO port 9 pin 5
+    BSP_IO_PORT_09_PIN_06 = 0x0906,    ///< IO port 9 pin 6
+    BSP_IO_PORT_09_PIN_07 = 0x0907,    ///< IO port 9 pin 7
+    BSP_IO_PORT_09_PIN_08 = 0x0908,    ///< IO port 9 pin 8
+    BSP_IO_PORT_09_PIN_09 = 0x0909,    ///< IO port 9 pin 9
+    BSP_IO_PORT_09_PIN_10 = 0x090A,    ///< IO port 9 pin 10
+    BSP_IO_PORT_09_PIN_11 = 0x090B,    ///< IO port 9 pin 11
+    BSP_IO_PORT_09_PIN_12 = 0x090C,    ///< IO port 9 pin 12
+    BSP_IO_PORT_09_PIN_13 = 0x090D,    ///< IO port 9 pin 13
+    BSP_IO_PORT_09_PIN_14 = 0x090E,    ///< IO port 9 pin 14
+    BSP_IO_PORT_09_PIN_15 = 0x090F,    ///< IO port 9 pin 15
+
+    BSP_IO_PORT_10_PIN_00 = 0x0A00,    ///< IO port 10 pin 0
+    BSP_IO_PORT_10_PIN_01 = 0x0A01,    ///< IO port 10 pin 1
+    BSP_IO_PORT_10_PIN_02 = 0x0A02,    ///< IO port 10 pin 2
+    BSP_IO_PORT_10_PIN_03 = 0x0A03,    ///< IO port 10 pin 3
+    BSP_IO_PORT_10_PIN_04 = 0x0A04,    ///< IO port 10 pin 4
+    BSP_IO_PORT_10_PIN_05 = 0x0A05,    ///< IO port 10 pin 5
+    BSP_IO_PORT_10_PIN_06 = 0x0A06,    ///< IO port 10 pin 6
+    BSP_IO_PORT_10_PIN_07 = 0x0A07,    ///< IO port 10 pin 7
+    BSP_IO_PORT_10_PIN_08 = 0x0A08,    ///< IO port 10 pin 8
+    BSP_IO_PORT_10_PIN_09 = 0x0A09,    ///< IO port 10 pin 9
+    BSP_IO_PORT_10_PIN_10 = 0x0A0A,    ///< IO port 10 pin 10
+    BSP_IO_PORT_10_PIN_11 = 0x0A0B,    ///< IO port 10 pin 11
+    BSP_IO_PORT_10_PIN_12 = 0x0A0C,    ///< IO port 10 pin 12
+    BSP_IO_PORT_10_PIN_13 = 0x0A0D,    ///< IO port 10 pin 13
+    BSP_IO_PORT_10_PIN_14 = 0x0A0E,    ///< IO port 10 pin 14
+    BSP_IO_PORT_10_PIN_15 = 0x0A0F,    ///< IO port 10 pin 15
+
+    BSP_IO_PORT_11_PIN_00 = 0x0B00,    ///< IO port 11 pin 0
+    BSP_IO_PORT_11_PIN_01 = 0x0B01,    ///< IO port 11 pin 1
+    BSP_IO_PORT_11_PIN_02 = 0x0B02,    ///< IO port 11 pin 2
+    BSP_IO_PORT_11_PIN_03 = 0x0B03,    ///< IO port 11 pin 3
+    BSP_IO_PORT_11_PIN_04 = 0x0B04,    ///< IO port 11 pin 4
+    BSP_IO_PORT_11_PIN_05 = 0x0B05,    ///< IO port 11 pin 5
+    BSP_IO_PORT_11_PIN_06 = 0x0B06,    ///< IO port 11 pin 6
+    BSP_IO_PORT_11_PIN_07 = 0x0B07,    ///< IO port 11 pin 7
+    BSP_IO_PORT_11_PIN_08 = 0x0B08,    ///< IO port 11 pin 8
+    BSP_IO_PORT_11_PIN_09 = 0x0B09,    ///< IO port 11 pin 9
+    BSP_IO_PORT_11_PIN_10 = 0x0B0A,    ///< IO port 11 pin 10
+    BSP_IO_PORT_11_PIN_11 = 0x0B0B,    ///< IO port 11 pin 11
+    BSP_IO_PORT_11_PIN_12 = 0x0B0C,    ///< IO port 11 pin 12
+    BSP_IO_PORT_11_PIN_13 = 0x0B0D,    ///< IO port 11 pin 13
+    BSP_IO_PORT_11_PIN_14 = 0x0B0E,    ///< IO port 11 pin 14
+    BSP_IO_PORT_11_PIN_15 = 0x0B0F,    ///< IO port 11 pin 15
+} bsp_io_port_pin_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern volatile uint32_t g_protect_pfswe_counter;
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Read the current input level of the pin.
+ *
+ * @param[in]  pin             The pin
+ *
+ * @retval     Current input level
+ **********************************************************************************************************************/
+__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin)
+{
+    /* Read pin level. */
+    return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR;
+}
+
+/*******************************************************************************************************************//**
+ * Set a pin to output and set the output level to the level provided
+ *
+ * @param[in]  pin      The pin
+ * @param[in]  level    The level
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level)
+{
+    /* Set output level and pin direction to output. */
+    uint32_t lvl = (uint32_t) level;
+    R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = BSP_IO_PFS_PDR_OUTPUT | lvl;
+}
+
+/*******************************************************************************************************************//**
+ * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur
+ * via multiple threads or an ISR re-entering this code.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinAccessEnable (void)
+{
+#if BSP_CFG_PFS_PROTECT
+
+    /** Get the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /** If this is first entry then allow writing of PFS. */
+    if (0 == g_protect_pfswe_counter)
+    {
+        R_PMISC->PWPR = 0;                              ///< Clear BOWI bit - writing to PFSWE bit enabled
+        R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
+    }
+
+    /** Increment the protect counter */
+    g_protect_pfswe_counter++;
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via
+ * multiple threads or an ISR re-entering this code.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_PinAccessDisable (void)
+{
+#if BSP_CFG_PFS_PROTECT
+
+    /** Get the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /** Is it safe to disable PFS register? */
+    if (0 != g_protect_pfswe_counter)
+    {
+        /* Decrement the protect counter */
+        g_protect_pfswe_counter--;
+    }
+
+    /** Is it safe to disable writing of PFS? */
+    if (0 == g_protect_pfswe_counter)
+    {
+        R_PMISC->PWPR = 0;                             ///< Clear PFSWE bit - writing to PFS register disabled
+        R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled
+    }
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+#endif
+}
+
+/** @} (end addtogroup BSP_IO) */
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c
new file mode 100644
index 0000000000..edd9e64fec
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.c
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/** ELC event definitions. */
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_IRQ_UINT32_MAX    (0xFFFFFFFFU)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* This table is used to store the context in the ISR. */
+void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE;
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+/*******************************************************************************************************************//**
+ *        Using the vector table information section that has been built by the linker and placed into ROM in the
+ * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts
+ * in the NVIC.
+ *
+ **********************************************************************************************************************/
+void bsp_irq_cfg (void)
+{
+    for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
+    {
+        R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i];
+    }
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h
new file mode 100644
index 0000000000..768a84fe50
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_irq.h
@@ -0,0 +1,217 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/** @} (end addtogroup BSP_MCU) */
+
+#ifndef BSP_IRQ_H
+#define BSP_IRQ_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define BSP_ICU_VECTOR_MAX_ENTRIES    (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @brief      Sets the ISR context associated with the requested IRQ.
+ *
+ * @param[in]  irq            IRQ number (parameter checking must ensure the IRQ number is valid before calling this
+ *                            function.
+ * @param[in]  p_context      ISR context for IRQ.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
+{
+    /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
+     * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
+    gp_renesas_isr_context[irq] = p_context;
+}
+
+/*******************************************************************************************************************//**
+ * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit
+ * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately.
+ *
+ * @param[in] irq            Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
+{
+    /* Clear the IR bit in the selected IELSR register. */
+    R_ICU->IELSR_b[irq].IR = 0U;
+}
+
+/*******************************************************************************************************************//**
+ * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt.
+ *
+ * @param[in] irq            Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
+{
+    /* Clear the IR bit in the selected IELSR register. */
+    R_BSP_IrqStatusClear(irq);
+
+    /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
+     * exceptions every time an interrupt is cleared in the NVIC. */
+    uint32_t _irq = (uint32_t) irq;
+    NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt priority and context.
+ *
+ * @param[in] irq            The IRQ to configure.
+ * @param[in] priority       NVIC priority of the interrupt
+ * @param[in] p_context      The interrupt context is a pointer to data required in the ISR.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions
+     * every time a priority is configured in the NVIC. */
+#if (4U == __CORTEX_M)
+    NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
+#elif (23 == __CORTEX_M)
+    NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) |
+                               (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq)));
+#else
+    NVIC_SetPriority(irq, priority);
+#endif
+
+    /* Store the context. The context is recovered in the ISR. */
+    R_FSP_IsrContextSet(irq, p_context);
+}
+
+/*******************************************************************************************************************//**
+ * Enable the IRQ in the NVIC (Without clearing the pending bit).
+ *
+ * @param[in] irq            The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex
+ *                           Processor Exceptions Numbers.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
+{
+    /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
+     * every time an interrupt is enabled in the NVIC. */
+    uint32_t _irq = (uint32_t) irq;
+    NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
+}
+
+/*******************************************************************************************************************//**
+ * Clears pending interrupts in both ICU and NVIC, then enables the interrupt.
+ *
+ * @param[in] irq            Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed
+ *                           for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
+{
+    /* Clear pending interrupts in the ICU and NVIC. */
+    R_BSP_IrqClearPending(irq);
+
+    /* Enable the IRQ in the NVIC. */
+    R_BSP_IrqEnableNoClear(irq);
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupts in the NVIC.
+ *
+ * @param[in] irq            The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are
+ *                           only those for the Cortex Processor Exceptions Numbers.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
+{
+    /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system
+     * exceptions every time an interrupt is cleared in the NVIC. */
+    uint32_t _irq = (uint32_t) irq;
+    NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
+
+    __DSB();
+    __ISB();
+}
+
+/*******************************************************************************************************************//**
+ * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
+ *
+ * @param[in] irq            Interrupt number.
+ * @param[in] priority       NVIC priority of the interrupt
+ * @param[in] p_context      The interrupt context is a pointer to data required in the ISR.
+ *
+ * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
+ **********************************************************************************************************************/
+__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    R_BSP_IrqCfg(irq, priority, p_context);
+    R_BSP_IrqEnable(irq);
+}
+
+/*******************************************************************************************************************//**
+ * @brief      Finds the ISR context associated with the requested IRQ.
+ *
+ * @param[in]  irq            IRQ number (parameter checking must ensure the IRQ number is valid before calling this
+ *                            function.
+ * @return  ISR context for IRQ.
+ **********************************************************************************************************************/
+__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
+{
+    /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
+     * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
+    return gp_renesas_isr_context[irq];
+}
+
+/*******************************************************************************************************************//**
+ * @internal
+ * @addtogroup BSP_MCU_PRV Internal BSP Documentation
+ * @ingroup RENESAS_INTERNAL
+ * @{
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_irq_cfg(void);                // Used internally by BSP
+
+/** @} (end addtogroup BSP_MCU_PRV) */
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
new file mode 100644
index 0000000000..f0c07c6fd1
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_MCU_API_H
+#define BSP_MCU_API_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+typedef struct st_bsp_event_info
+{
+    IRQn_Type   irq;
+    elc_event_t event;
+} bsp_event_info_t;
+
+void      R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect);
+void      R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect);
+fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq));
+void      R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units);
+fsp_err_t R_BSP_VersionGet(fsp_version_t * p_version);
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
new file mode 100644
index 0000000000..a70c3bd00e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
@@ -0,0 +1,140 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_MODULE_H
+#define BSP_MODULE_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Cancels the module stop state.
+ *
+ * @param      ip       fsp_ip_t enum value for the module to be stopped
+ * @param      channel  The channel. Use channel 0 for modules without channels.
+ **********************************************************************************************************************/
+#define R_BSP_MODULE_START(ip, channel)         {FSP_CRITICAL_SECTION_DEFINE;                          \
+                                                 FSP_CRITICAL_SECTION_ENTER;                           \
+                                                 BSP_MSTP_REG_ ## ip &= ~BSP_MSTP_BIT_ ## ip(channel); \
+                                                 FSP_CRITICAL_SECTION_EXIT;}
+
+/*******************************************************************************************************************//**
+ * Enables the module stop state.
+ *
+ * @param      ip       fsp_ip_t enum value for the module to be stopped
+ * @param      channel  The channel. Use channel 0 for modules without channels.
+ **********************************************************************************************************************/
+#define R_BSP_MODULE_STOP(ip, channel)          {FSP_CRITICAL_SECTION_DEFINE;                         \
+                                                 FSP_CRITICAL_SECTION_ENTER;                          \
+                                                 BSP_MSTP_REG_ ## ip |= BSP_MSTP_BIT_ ## ip(channel); \
+                                                 FSP_CRITICAL_SECTION_EXIT;}
+
+/** @} (end addtogroup BSP_MCU) */
+
+#define BSP_MSTP_REG_FSP_IP_GPT        R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_GPT(channel)        ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \
+                                                  channel) ? (1U << 5U) : (1U << 6U));
+
+#define BSP_MSTP_REG_FSP_IP_DMAC       R_SYSTEM->MSTPCRA
+#define BSP_MSTP_BIT_FSP_IP_DMAC(channel)       (1U << (22U));
+#define BSP_MSTP_REG_FSP_IP_DTC        R_SYSTEM->MSTPCRA
+#define BSP_MSTP_BIT_FSP_IP_DTC(channel)        (1U << (22U));
+#define BSP_MSTP_REG_FSP_IP_CAN        R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_CAN(channel)        (1U << (2U - channel));
+#define BSP_MSTP_REG_FSP_IP_IRDA       R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_IRDA(channel)       (1U << (5U - channel));
+#define BSP_MSTP_REG_FSP_IP_QSPI       R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_QSPI(channel)       (1U << (6U - channel));
+#define BSP_MSTP_REG_FSP_IP_IIC        R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_IIC(channel)        (1U << (9U - channel));
+#define BSP_MSTP_REG_FSP_IP_USBFS      R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_USBFS(channel)      (1U << (11U - channel));
+#define BSP_MSTP_REG_FSP_IP_USBHS      R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_USBHS(channel)      (1U << (12U - channel));
+#define BSP_MSTP_REG_FSP_IP_EPTPC      R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel)      (1U << (13U - channel));
+#define BSP_MSTP_REG_FSP_IP_ETHER      R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_ETHER(channel)      (1U << (15U - channel));
+#define BSP_MSTP_REG_FSP_IP_SPI        R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_SPI(channel)        (1U << (19U - channel));
+#define BSP_MSTP_REG_FSP_IP_SCI        R_MSTP->MSTPCRB
+#define BSP_MSTP_BIT_FSP_IP_SCI(channel)        (1U << (31U - channel));
+#define BSP_MSTP_REG_FSP_IP_CAC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_CAC(channel)        (1U << (0U - channel));
+#define BSP_MSTP_REG_FSP_IP_CRC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_CRC(channel)        (1U << (1U - channel));
+#define BSP_MSTP_REG_FSP_IP_PDC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_PDC(channel)        (1U << (2U - channel));
+#define BSP_MSTP_REG_FSP_IP_CTSU       R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_CTSU(channel)       (1U << (3U - channel));
+#define BSP_MSTP_REG_FSP_IP_SLCDC      R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel)      (1U << (4U - channel));
+#define BSP_MSTP_REG_FSP_IP_GLCDC      R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel)      (1U << (4U - channel));
+#define BSP_MSTP_REG_FSP_IP_JPEG       R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_JPEG(channel)       (1U << (5U - channel));
+#define BSP_MSTP_REG_FSP_IP_DRW        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_DRW(channel)        (1U << (6U - channel));
+#define BSP_MSTP_REG_FSP_IP_SSI        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_SSI(channel)        (1U << (8U - channel));
+#define BSP_MSTP_REG_FSP_IP_SRC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_SRC(channel)        (1U << (9U - channel));
+#define BSP_MSTP_REG_FSP_IP_SDHIMMC    R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel)    (1U << (12U - channel));
+#define BSP_MSTP_REG_FSP_IP_DOC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_DOC(channel)        (1U << (13U - channel));
+#define BSP_MSTP_REG_FSP_IP_ELC        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_ELC(channel)        (1U << (14U - channel));
+#define BSP_MSTP_REG_FSP_IP_TRNG       R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_TRNG(channel)       (1U << (28U - channel));
+#define BSP_MSTP_REG_FSP_IP_SCE        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_SCE(channel)        (1U << (31U - channel));
+#define BSP_MSTP_REG_FSP_IP_AES        R_MSTP->MSTPCRC
+#define BSP_MSTP_BIT_FSP_IP_AES(channel)        (1U << (31U - channel));
+#define BSP_MSTP_REG_FSP_IP_AGT        R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_AGT(channel)        (1U << (3U - channel));
+#define BSP_MSTP_REG_FSP_IP_POEG       R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_POEG(channel)       (1U << (14U));
+#define BSP_MSTP_REG_FSP_IP_ADC        R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_ADC(channel)        (1U << (16U - channel));
+#define BSP_MSTP_REG_FSP_IP_SDADC      R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_SDADC(channel)      (1U << (17U - channel));
+#define BSP_MSTP_REG_FSP_IP_DAC8       R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_DAC8(channel)       (1U << (19U - channel));
+#define BSP_MSTP_REG_FSP_IP_DAC        R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_DAC(channel)        (1U << (20U));
+#define BSP_MSTP_REG_FSP_IP_TSN        R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_TSN(channel)        (1U << (22U - channel));
+#define BSP_MSTP_REG_FSP_IP_ACMPHS     R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel)     (1U << (28U - channel));
+#define BSP_MSTP_REG_FSP_IP_ACMPLP     R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel)     (1U << 29U);
+#define BSP_MSTP_REG_FSP_IP_OPAMP      R_MSTP->MSTPCRD
+#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel)      (1U << (31U - channel));
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
new file mode 100644
index 0000000000..e19c87250a
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -0,0 +1,127 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY    (0xA500U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** Used for holding reference counters for protection bits. */
+static volatile uint16_t g_protect_counters[] =
+{
+    0U, 0U, 0U
+};
+
+/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
+static const uint16_t g_prcr_masks[] =
+{
+    0x0001U,                           /* PRC0. */
+    0x0002U,                           /* PRC1. */
+    0x0008U,                           /* PRC3. */
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ *
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ *        Enable register protection. Registers that are protected cannot be written to. Register protection is
+ *          enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
+ *
+ * @param[in] regs_to_protect Registers which have write protection enabled.
+ **********************************************************************************************************************/
+void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
+{
+    /** Get/save the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /* Is it safe to disable write access? */
+    if (0U != g_protect_counters[regs_to_protect])
+    {
+        /* Decrement the protect counter */
+        g_protect_counters[regs_to_protect]--;
+    }
+
+    /* Is it safe to disable write access? */
+    if (0U == g_protect_counters[regs_to_protect])
+    {
+        /** Enable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
+    }
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+}
+
+/*******************************************************************************************************************//**
+ *        Disable register protection. Registers that are protected cannot be written to. Register protection is
+ *          disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
+ *
+ * @param[in] regs_to_unprotect Registers which have write protection disabled.
+ **********************************************************************************************************************/
+void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
+{
+    /** Get/save the current state of interrupts */
+    FSP_CRITICAL_SECTION_DEFINE;
+    FSP_CRITICAL_SECTION_ENTER;
+
+    /* If this is first entry then disable protection. */
+    if (0U == g_protect_counters[regs_to_unprotect])
+    {
+        /** Disable protection using PRCR register. */
+
+        /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
+         * disable writes. */
+        R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
+    }
+
+    /** Increment the protect counter */
+    g_protect_counters[regs_to_unprotect]++;
+
+    /** Restore the interrupt state */
+    FSP_CRITICAL_SECTION_EXIT;
+}
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
new file mode 100644
index 0000000000..7bd186c003
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h
@@ -0,0 +1,71 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_REGISTER_PROTECTION_H
+#define BSP_REGISTER_PROTECTION_H
+
+/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/** The different types of registers that can be protected. */
+typedef enum e_bsp_reg_protect
+{
+    /** Enables writing to the registers related to the clock generation circuit. */
+    BSP_REG_PROTECT_CGC = 0,
+
+    /** Enables writing to the registers related to operating modes, low power consumption, and battery backup
+     * function. */
+    BSP_REG_PROTECT_OM_LPC_BATT,
+
+    /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0,
+     * LVD2CR1, LVD2SR. */
+    BSP_REG_PROTECT_LVD,
+} bsp_reg_protect_t;
+
+/** @} (end addtogroup BSP_MCU) */
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/* Public functions defined in bsp.h */
+void bsp_register_protect_open(void);  // Used internally by BSP
+
+/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
new file mode 100644
index 0000000000..1d1f63f93d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c
@@ -0,0 +1,100 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** OR in the HOCO frequency setting from bsp_clock_cfg.h with the OFS1 setting from bsp_cfg.h. */
+#define BSP_ROM_REG_OFS1_SETTING                                             \
+    (((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \
+     ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET))
+
+/** Build up SECMPUAC register based on MPU settings. */
+#define BSP_ROM_REG_MPU_CONTROL_SETTING                     \
+    ((0xFFFFFCF0U) |                                        \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) |     \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) |     \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE) |      \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \
+     ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3))
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
+BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) =
+{
+    (uint32_t) BSP_CFG_ROM_REG_OFS0,
+    (uint32_t) BSP_ROM_REG_OFS1_SETTING,
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU),
+    (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU),
+    ((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U),
+    (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U),
+    (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U),
+    (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U),
+    (((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U),
+    (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
+};
+
+/** ID code definitions defined here. */
+BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
+{
+    BSP_CFG_ID_CODE_LONG_1,
+#if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+#endif
+    BSP_CFG_ID_CODE_LONG_2,
+#if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+#endif
+    BSP_CFG_ID_CODE_LONG_3,
+#if BSP_FEATURE_BSP_OSIS_PADDING
+    0xFFFFFFFFU,
+#endif
+    BSP_CFG_ID_CODE_LONG_4
+};
+
+/** @} (end addtogroup BSP_MCU) */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
new file mode 100644
index 0000000000..3425c72b70
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c
@@ -0,0 +1,106 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#include "bsp_api.h"
+#include 
+#include 
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+caddr_t _sbrk(int incr);
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * FSP implementation of the standard library _sbrk() function.
+ * @param[in]   inc  The number of bytes being asked for by malloc().
+ *
+ * @note This function overrides the _sbrk version that exists in the newlib library that is linked with.
+ *       That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and
+ *       worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc()
+ *       only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by
+ *       malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc().
+ * @retval        Address of allocated area if successful, -1 otherwise.
+ **********************************************************************************************************************/
+
+caddr_t _sbrk (int incr)
+{
+    extern char _Heap_Begin __asm("__HeapBase");  ///< Defined by the linker.
+
+    extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker.
+
+    uint32_t      bytes            = (uint32_t) incr;
+    static char * current_heap_end = 0;
+    char        * current_block_address;
+
+    if (current_heap_end == 0)
+    {
+        current_heap_end = &_Heap_Begin;
+    }
+
+    current_block_address = current_heap_end;
+
+    /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support
+     * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple
+     * of 4. */
+    bytes = (bytes + 3U) & (~3U);
+    if (current_heap_end + bytes > &_Heap_Limit)
+    {
+        /** Heap has overflowed */
+        errno = ENOMEM;
+
+        return (caddr_t) -1;
+    }
+
+    current_heap_end += bytes;
+
+    return (caddr_t) current_block_address;
+}
+
+#endif
+
+/******************************************************************************************************************//**
+ * @} (end addtogroup BSP_MCU)
+ *********************************************************************************************************************/
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h
new file mode 100644
index 0000000000..833a1991e5
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_elc.h
@@ -0,0 +1,237 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_ELC_H
+#define BSP_ELC_H
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup BSP_MCU_RA4W1
+ * @{
+ **********************************************************************************************************************/
+
+/** Sources of event signals to be linked to other peripherals or the CPU1
+ * @note This list may change based on device. This list is for RA4W1.
+ * */
+typedef enum e_elc_event
+{
+    ELC_EVENT_NONE                   = (0),   // Link disabled
+    ELC_EVENT_ICU_IRQ0               = (1),   // External pin interrupt 0
+    ELC_EVENT_ICU_IRQ1               = (2),   // External pin interrupt 1
+    ELC_EVENT_ICU_IRQ2               = (3),   // External pin interrupt 2
+    ELC_EVENT_ICU_IRQ3               = (4),   // External pin interrupt 3
+    ELC_EVENT_ICU_IRQ4               = (5),   // External pin interrupt 4
+    ELC_EVENT_ICU_IRQ6               = (7),   // External pin interrupt 6
+    ELC_EVENT_ICU_IRQ7               = (8),   // External pin interrupt 7
+    ELC_EVENT_ICU_IRQ8               = (9),   // Interrupt for BLE middleware use only
+    ELC_EVENT_ICU_IRQ9               = (10),  // External pin interrupt 9
+    ELC_EVENT_ICU_IRQ11              = (12),  // External pin interrupt 11
+    ELC_EVENT_ICU_IRQ14              = (15),  // External pin interrupt 14
+    ELC_EVENT_ICU_IRQ15              = (16),  // External pin interrupt 15
+    ELC_EVENT_DMAC0_INT              = (17),  // DMAC transfer end 0
+    ELC_EVENT_DMAC1_INT              = (18),  // DMAC transfer end 1
+    ELC_EVENT_DMAC2_INT              = (19),  // DMAC transfer end 2
+    ELC_EVENT_DMAC3_INT              = (20),  // DMAC transfer end 3
+    ELC_EVENT_DTC_COMPLETE           = (21),  // DTC last transfer
+    ELC_EVENT_DTC_END                = (22),  // DTC transfer end
+    ELC_EVENT_ICU_SNOOZE_CANCEL      = (23),  // Canceling from Snooze mode
+    ELC_EVENT_FCU_FRDYI              = (24),  // Flash ready interrupt
+    ELC_EVENT_LVD_LVD1               = (25),  // Voltage monitor 1 interrupt
+    ELC_EVENT_LVD_VBATT              = (27),  // VBATT low voltage detect
+    ELC_EVENT_CGC_MOSC_STOP          = (28),  // Main Clock oscillation stop
+    ELC_EVENT_LPM_SNOOZE_REQUEST     = (29),  // Snooze entry
+    ELC_EVENT_AGT0_INT               = (30),  // AGT interrupt
+    ELC_EVENT_AGT0_COMPARE_A         = (31),  // Compare match A
+    ELC_EVENT_AGT0_COMPARE_B         = (32),  // Compare match B
+    ELC_EVENT_AGT1_INT               = (33),  // AGT interrupt
+    ELC_EVENT_AGT1_COMPARE_A         = (34),  // Compare match A
+    ELC_EVENT_AGT1_COMPARE_B         = (35),  // Compare match B
+    ELC_EVENT_IWDT_UNDERFLOW         = (36),  // IWDT underflow
+    ELC_EVENT_WDT_UNDERFLOW          = (37),  // WDT underflow
+    ELC_EVENT_RTC_ALARM              = (38),  // Alarm interrupt
+    ELC_EVENT_RTC_PERIOD             = (39),  // Periodic interrupt
+    ELC_EVENT_RTC_CARRY              = (40),  // Carry interrupt
+    ELC_EVENT_ADC0_SCAN_END          = (41),  // A/D scan end interrupt
+    ELC_EVENT_ADC0_SCAN_END_B        = (42),  // A/D scan end interrupt for group B
+    ELC_EVENT_ADC0_WINDOW_A          = (43),  // Window A Compare match
+    ELC_EVENT_ADC0_WINDOW_B          = (44),  // Window B Compare match
+    ELC_EVENT_ADC0_COMPARE_MATCH     = (45),  // Compare match
+    ELC_EVENT_ADC0_COMPARE_MISMATCH  = (46),  // Compare mismatch
+    ELC_EVENT_ACMPLP0_INT            = (47),  // Analog Comparator Channel 0 interrupt
+    ELC_EVENT_ACMPLP1_INT            = (48),  // Analog Comparator Channel 1 interrupt
+    ELC_EVENT_USBFS_FIFO_0           = (49),  // DMA transfer request 0
+    ELC_EVENT_USBFS_FIFO_1           = (50),  // DMA transfer request 1
+    ELC_EVENT_USBFS_INT              = (51),  // USBFS interrupt
+    ELC_EVENT_USBFS_RESUME           = (52),  // USBFS resume interrupt
+    ELC_EVENT_IIC0_RXI               = (53),  // Receive data full
+    ELC_EVENT_IIC0_TXI               = (54),  // Transmit data empty
+    ELC_EVENT_IIC0_TEI               = (55),  // Transmit end
+    ELC_EVENT_IIC0_ERI               = (56),  // Transfer error
+    ELC_EVENT_IIC0_WUI               = (57),  // Slave address match
+    ELC_EVENT_IIC1_RXI               = (58),  // Receive data full
+    ELC_EVENT_IIC1_TXI               = (59),  // Transmit data empty
+    ELC_EVENT_IIC1_TEI               = (60),  // Transmit end
+    ELC_EVENT_IIC1_ERI               = (61),  // Transfer error
+    ELC_EVENT_SSI0_TXI               = (66),  // Transmit data empty
+    ELC_EVENT_SSI0_RXI               = (67),  // Receive data full
+    ELC_EVENT_SSI0_INT               = (69),  // Error interrupt
+    ELC_EVENT_CTSU_WRITE             = (70),  // Write request interrupt
+    ELC_EVENT_CTSU_READ              = (71),  // Measurement data transfer request interrupt
+    ELC_EVENT_CTSU_END               = (72),  // Measurement end interrupt
+    ELC_EVENT_KEY_INT                = (73),  // Key interrupt
+    ELC_EVENT_DOC_INT                = (74),  // Data operation circuit interrupt
+    ELC_EVENT_CAC_FREQUENCY_ERROR    = (75),  // Frequency error interrupt
+    ELC_EVENT_CAC_MEASUREMENT_END    = (76),  // Measurement end interrupt
+    ELC_EVENT_CAC_OVERFLOW           = (77),  // Overflow interrupt
+    ELC_EVENT_CAN0_ERROR             = (78),  // Error interrupt
+    ELC_EVENT_CAN0_FIFO_RX           = (79),  // Receive FIFO interrupt
+    ELC_EVENT_CAN0_FIFO_TX           = (80),  // Transmit FIFO interrupt
+    ELC_EVENT_CAN0_MAILBOX_RX        = (81),  // Reception complete interrupt
+    ELC_EVENT_CAN0_MAILBOX_TX        = (82),  // Transmission complete interrupt
+    ELC_EVENT_IOPORT_EVENT_1         = (83),  // Port 1 event
+    ELC_EVENT_IOPORT_EVENT_2         = (84),  // Port 2 event
+    ELC_EVENT_IOPORT_EVENT_3         = (85),  // Port 3 event
+    ELC_EVENT_IOPORT_EVENT_4         = (86),  // Port 4 event
+    ELC_EVENT_ELC_SOFTWARE_EVENT_0   = (87),  // Software event 0
+    ELC_EVENT_ELC_SOFTWARE_EVENT_1   = (88),  // Software event 1
+    ELC_EVENT_POEG0_EVENT            = (89),  // Port Output disable interrupt A
+    ELC_EVENT_POEG1_EVENT            = (90),  // Port Output disable interrupt B
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (91),  // Compare match A
+    ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (92),  // Compare match B
+    ELC_EVENT_GPT0_COMPARE_C         = (93),  // Compare match C
+    ELC_EVENT_GPT0_COMPARE_D         = (94),  // Compare match D
+    ELC_EVENT_GPT0_COMPARE_E         = (95),  // Compare match E
+    ELC_EVENT_GPT0_COMPARE_F         = (96),  // Compare match F
+    ELC_EVENT_GPT0_COUNTER_OVERFLOW  = (97),  // Overflow
+    ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (98),  // Underflow
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (99),  // Compare match A
+    ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (100), // Compare match B
+    ELC_EVENT_GPT1_COMPARE_C         = (101), // Compare match C
+    ELC_EVENT_GPT1_COMPARE_D         = (102), // Compare match D
+    ELC_EVENT_GPT1_COMPARE_E         = (103), // Compare match E
+    ELC_EVENT_GPT1_COMPARE_F         = (104), // Compare match F
+    ELC_EVENT_GPT1_COUNTER_OVERFLOW  = (105), // Overflow
+    ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (106), // Underflow
+    ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (107), // Compare match A
+    ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (108), // Compare match B
+    ELC_EVENT_GPT2_COMPARE_C         = (109), // Compare match C
+    ELC_EVENT_GPT2_COMPARE_D         = (110), // Compare match D
+    ELC_EVENT_GPT2_COMPARE_E         = (111), // Compare match E
+    ELC_EVENT_GPT2_COMPARE_F         = (112), // Compare match F
+    ELC_EVENT_GPT2_COUNTER_OVERFLOW  = (113), // Overflow
+    ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (114), // Underflow
+    ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (115), // Compare match A
+    ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (116), // Compare match B
+    ELC_EVENT_GPT3_COMPARE_C         = (117), // Compare match C
+    ELC_EVENT_GPT3_COMPARE_D         = (118), // Compare match D
+    ELC_EVENT_GPT3_COMPARE_E         = (119), // Compare match E
+    ELC_EVENT_GPT3_COMPARE_F         = (120), // Compare match F
+    ELC_EVENT_GPT3_COUNTER_OVERFLOW  = (121), // Overflow
+    ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (122), // Underflow
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (123), // Compare match A
+    ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (124), // Compare match B
+    ELC_EVENT_GPT4_COMPARE_C         = (125), // Compare match C
+    ELC_EVENT_GPT4_COMPARE_D         = (126), // Compare match D
+    ELC_EVENT_GPT4_COMPARE_E         = (127), // Compare match E
+    ELC_EVENT_GPT4_COMPARE_F         = (128), // Compare match F
+    ELC_EVENT_GPT4_COUNTER_OVERFLOW  = (129), // Overflow
+    ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (130), // Underflow
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (131), // Compare match A
+    ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (132), // Compare match B
+    ELC_EVENT_GPT5_COMPARE_C         = (133), // Compare match C
+    ELC_EVENT_GPT5_COMPARE_D         = (134), // Compare match D
+    ELC_EVENT_GPT5_COMPARE_E         = (135), // Compare match E
+    ELC_EVENT_GPT5_COMPARE_F         = (136), // Compare match F
+    ELC_EVENT_GPT5_COUNTER_OVERFLOW  = (137), // Overflow
+    ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (138), // Underflow
+    ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (155), // Compare match A
+    ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (156), // Compare match B
+    ELC_EVENT_GPT8_COMPARE_C         = (157), // Compare match C
+    ELC_EVENT_GPT8_COMPARE_D         = (158), // Compare match D
+    ELC_EVENT_GPT8_COMPARE_E         = (159), // Compare match E
+    ELC_EVENT_GPT8_COMPARE_F         = (160), // Compare match F
+    ELC_EVENT_GPT8_COUNTER_OVERFLOW  = (161), // Overflow
+    ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (162), // Underflow
+    ELC_EVENT_OPS_UVW_EDGE           = (171), // UVW edge event
+    ELC_EVENT_SCI0_RXI               = (172), // Receive data full
+    ELC_EVENT_SCI0_TXI               = (173), // Transmit data empty
+    ELC_EVENT_SCI0_TEI               = (174), // Transmit end
+    ELC_EVENT_SCI0_ERI               = (175), // Receive error
+    ELC_EVENT_SCI0_AM                = (176), // Address match event
+    ELC_EVENT_SCI0_RXI_OR_ERI        = (177), // Receive data full/Receive
+    ELC_EVENT_SCI1_RXI               = (178), // Received data full
+    ELC_EVENT_SCI1_TXI               = (179), // Transmit data empty
+    ELC_EVENT_SCI1_TEI               = (180), // Transmit end
+    ELC_EVENT_SCI1_ERI               = (181), // Receive error
+    ELC_EVENT_SCI1_AM                = (182), // Address match event
+    ELC_EVENT_SCI4_RXI               = (193), // Received data full
+    ELC_EVENT_SCI4_TXI               = (194), // Transmit data empty
+    ELC_EVENT_SCI4_TEI               = (195), // Transmit end
+    ELC_EVENT_SCI4_ERI               = (196), // Receive error
+    ELC_EVENT_SCI4_AM                = (197), // Address match event
+    ELC_EVENT_SCI9_RXI               = (198), // Received data full
+    ELC_EVENT_SCI9_TXI               = (199), // Transmit data empty
+    ELC_EVENT_SCI9_TEI               = (200), // Transmit end
+    ELC_EVENT_SCI9_ERI               = (201), // Receive error
+    ELC_EVENT_SCI9_AM                = (202), // Address match event
+    ELC_EVENT_SPI0_RXI               = (203), // Receive buffer full
+    ELC_EVENT_SPI0_TXI               = (204), // Transmit buffer empty
+    ELC_EVENT_SPI0_IDLE              = (205), // Idle
+    ELC_EVENT_SPI0_ERI               = (206), // Error
+    ELC_EVENT_SPI0_TEI               = (207), // Transmission complete event
+    ELC_EVENT_SPI1_RXI               = (208), // Receive buffer full
+    ELC_EVENT_SPI1_TXI               = (209), // Transmit buffer empty
+    ELC_EVENT_SPI1_IDLE              = (210), // Idle
+    ELC_EVENT_SPI1_ERI               = (211), // Error
+    ELC_EVENT_SPI1_TEI               = (212), // Transmission complete event
+    ELC_EVENT_QSPI_INT               = (213), // Error
+    ELC_EVENT_SDHIMMC0_ACCS          = (214), // Card access
+    ELC_EVENT_SDHIMMC0_SDIO          = (215), // SDIO access
+    ELC_EVENT_SDHIMMC0_CARD          = (216), // Card detect
+    ELC_EVENT_SDHIMMC0_DMA_REQ       = (217), // DMA transfer request
+    ELC_EVENT_SCE_PROC_BUSY          = (218),
+    ELC_EVENT_SCE_ROMOK              = (219),
+    ELC_EVENT_SCE_LONG_PLG           = (220),
+    ELC_EVENT_SCE_TEST_BUSY          = (221),
+    ELC_EVENT_SCE_WRRDY_0            = (222),
+    ELC_EVENT_SCE_WRRDY_4            = (223),
+    ELC_EVENT_SCE_RDRDY_0            = (224),
+    ELC_EVENT_SCE_INTEGRATE_WRRDY    = (225),
+    ELC_EVENT_SCE_INTEGRATE_RDRDY    = (226),
+} elc_event_t;
+
+/** @} (end addtogroup BSP_MCU_RA4W1) */
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
new file mode 100644
index 0000000000..47c72c8e0b
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h
@@ -0,0 +1,234 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#ifndef BSP_FEATURE_H
+#define BSP_FEATURE_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */
+#if (BSP_CFG_XTAL_HZ > (9999999))
+ #define CGC_MAINCLOCK_DRIVE    (0x00U)
+#else
+ #define CGC_MAINCLOCK_DRIVE    (0x01U)
+#endif
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global variables (to be accessed by other files)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+
+#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US            (0) // Feature not available on this MCU
+#define BSP_FEATURE_ACMPHS_VREF                        (0) // Feature not available on this MCU
+
+#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS       (1)
+#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US            (100U)
+
+#define BSP_FEATURE_ADC_ADDITION_SUPPORTED             (1U)
+#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE      (0U)
+#define BSP_FEATURE_ADC_CLOCK_SOURCE                   (FSP_PRIV_CLOCK_PCLKC)
+#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED        (0U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC                (1U)
+#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT               (1U)
+#define BSP_FEATURE_ADC_HAS_PGA                        (0) // Feature not available on this MCU
+#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG            (0U)
+#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS            (14U)
+#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE              (1U)
+#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME       (5000U)
+#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE      (1U)
+#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE          (0U)
+#define BSP_FEATURE_ADC_TSN_SLOPE                      (-3650)
+#define BSP_FEATURE_ADC_UNIT_0_CHANNELS                (0x1A0670) // 4 to 6, 9, 10, 17, 19, 20 in unit 0
+#define BSP_FEATURE_ADC_UNIT_1_CHANNELS                (0)
+#define BSP_FEATURE_ADC_VALID_UNIT_MASK                (1U)
+#define BSP_FEATURE_ADC_HAS_VREFAMPCNT                 (0U)
+
+#define BSP_FEATURE_BSP_FLASH_CACHE                    (1U)
+#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER          (0)
+#define BSP_FEATURE_BSP_HAS_SCE5                       (1)
+#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2                 (0)  // Feature not available on this MCU
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL              (1U)
+#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT          (1U)
+#define BSP_FEATURE_BSP_MPU_REGION0_MASK               (0x00FFFFFFU)
+#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH         (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU.
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK              (0xFFFF8FFFU)
+#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET            (12U)
+#define BSP_FEATURE_BSP_OSIS_PADDING                   (1)
+#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED     (0U)
+#define BSP_FEATURE_BSP_RESET_TRNG                     (1U)
+#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP      (1U)
+
+#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO              (1U)
+#define BSP_FEATURE_CAN_CLOCK                          (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_CAN_MCLOCK_ONLY                    (0U)
+#define BSP_FEATURE_CAN_NUM_CHANNELS                   (1U)
+
+#define BSP_FEATURE_CGC_HAS_BCLK                       (0U) // This MCU does not have a BCLK
+#define BSP_FEATURE_CGC_HAS_FCLK                       (1U)
+#define BSP_FEATURE_CGC_HAS_FLDWAITR                   (0U)
+#define BSP_FEATURE_CGC_HAS_FLWT                       (0U)
+#define BSP_FEATURE_CGC_HAS_HOCOWTCR                   (1U)
+#define BSP_FEATURE_CGC_HAS_MEMWAIT                    (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKA                      (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKB                      (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKC                      (1U)
+#define BSP_FEATURE_CGC_HAS_PCLKD                      (1U)
+#define BSP_FEATURE_CGC_HAS_PLL                        (1U)
+#define BSP_FEATURE_CGC_HAS_SRAMWTSC                   (0U)
+#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR            (1U)
+#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY            (1U)
+#define BSP_FEATURE_CGC_ICLK_DIV_RESET                 (BSP_CLOCKS_SYS_CLOCK_DIV_16)
+#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US      (100U)
+#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ          (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
+#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ        (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz
+#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ       (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz
+#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US      (1U)
+#define BSP_FEATURE_CGC_MODRV_MASK                     (0x08U)
+#define BSP_FEATURE_CGC_MODRV_SHIFT                    (0x3U)
+#define BSP_FEATURE_CGC_PLLCCR_TYPE                    (2U)
+#define BSP_FEATURE_CGC_PLLCCR_WAIT_US                 (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP
+#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB    (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB
+#define BSP_FEATURE_CGC_SODRV_MASK                     (0x03U)
+#define BSP_FEATURE_CGC_SODRV_SHIFT                    (0x0U)
+
+#define BSP_FEATURE_CRYPTO_HAS_AES                     (1)
+#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED             (1)
+#define BSP_FEATURE_CRYPTO_HAS_ECC                     (0)
+#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED             (0)
+#define BSP_FEATURE_CRYPTO_HAS_HASH                    (0)
+#define BSP_FEATURE_CRYPTO_HAS_RSA                     (0)
+#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED             (0)
+
+#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT       (5U)
+#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT      (5U)
+#define BSP_FEATURE_CTSU_HAS_TXVSEL                    (0)
+#define BSP_FEATURE_CTSU_VERSION                       (1)
+
+#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP                (0U)
+#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE         (0U)
+#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE             (0U)
+#define BSP_FEATURE_DAC8_MAX_CHANNELS                  (2U)
+
+#define BSP_FEATURE_DAC_HAS_CHARGEPUMP                 (0U)
+#define BSP_FEATURE_DAC_HAS_DAVREFCR                   (1U)
+#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER           (0U)
+#define BSP_FEATURE_DAC_MAX_CHANNELS                   (1U)
+
+#define BSP_FEATURE_DMAC_MAX_CHANNEL                   (4U)
+
+#define BSP_FEATURE_DWT_CYCCNT                         (1U)          // RA4W1 has Data Watchpoint Cycle Count Register
+
+#define BSP_FEATURE_ELC_PERIPHERAL_MASK                (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU
+
+#define BSP_FEATURE_ETHER_FIFO_DEPTH                   (0)           // Feature not available on this MCU
+#define BSP_FEATURE_ETHER_MAX_CHANNELS                 (0)           // Feature not available on this MCU
+
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE     (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE           (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE     (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE             (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE             (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE             (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_HP_VERSION                   (0)           // Feature not available on this MCU
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK              (0xFFFU)
+#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT             (10)
+#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE             (0x800U)
+#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE             (8)
+#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE             (0x400U)
+#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE             (1)
+#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC           ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4W1 FlashIF uses FCLK
+#define BSP_FEATURE_FLASH_LP_VERSION                   (3)
+
+#define BSP_FEATURE_GPTEH_CHANNEL_MASK                 (0)
+
+#define BSP_FEATURE_GPTE_CHANNEL_MASK                  (0)
+
+#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK             (0xF)
+#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK             (0x13F)
+
+#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK              (0xCBDFU)
+#define BSP_FEATURE_ICU_WUPEN_MASK                     (0xFB97CADFU)
+
+#define BSP_FEATURE_IIC_FAST_MODE_PLUS                 (0U)
+
+#define BSP_FEATURE_IOPORT_ELC_PORTS                   (4)
+#define BSP_FEATURE_IOPORT_HAS_ETHERNET                (0U)
+
+#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY              (0) // Feature not available on this MCU
+#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED           (0U)
+#define BSP_FEATURE_LPM_DPSIEGR_MASK                   (0) // Feature not available on this MCU
+#define BSP_FEATURE_LPM_DPSIER_MASK                    (0) // Feature not available on this MCU
+#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY               (0U)
+#define BSP_FEATURE_LPM_HAS_SBYCR_OPE                  (1U)
+#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14               (0)
+#define BSP_FEATURE_LPM_SNZEDCR_MASK                   (0x0000009FU)
+#define BSP_FEATURE_LPM_SNZREQCR_MASK                  (0x7382CADFU)
+
+#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER             (0U)
+#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD         (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V
+#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD        (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V
+#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD         (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V
+#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD        (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V
+#define BSP_FEATURE_LVD_STABILIZATION_TIME_US          (300U)                                // Time in microseconds required for LVD to stabilize
+
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US          (13U)
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US          (650U)                                // This information comes from the Electrical Characteristics chapter of the hardware manual.
+#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US          (0xFFFFU)                             // Middle speed mode not supported
+#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK         (0xFU)
+#define BSP_FEATURE_OPAMP_HAS_SWITCHES                 (0U)
+#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL            (1U)
+#define BSP_FEATURE_OPAMP_TRIM_CAPABLE                 (0U)
+#define BSP_FEATURE_OPAMP_BASE_ADDRESS                 (1U)
+
+#define BSP_FEATURE_POEG_CHANNEL_MASK                  (0x3U)
+
+#define BSP_FEATURE_SCI_CHANNELS                       (0x213U)
+#define BSP_FEATURE_SCI_CLOCK                          (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS             (0x3U)
+#define BSP_FEATURE_SCI_UART_FIFO_DEPTH                (16U)
+
+#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION            (0) // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC            (0) // Feature not available on this MCU
+#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK            (0) // Feature not available on this MCU
+
+#define BSP_FEATURE_SLCDC_MAX_NUM_SEG                  (54U)
+
+#define BSP_FEATURE_SPI_CLK                            (FSP_PRIV_CLOCK_PCLKA)
+#define BSP_FEATURE_SPI_HAS_BYTE_SWAP                  (1U)
+#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP             (1U)
+#define BSP_FEATURE_SPI_MAX_CHANNEL                    (2U)
+
+#define BSP_FEATURE_SSI_FIFO_NUM_STAGES                (8U)
+#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK             (1U)
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h
new file mode 100644
index 0000000000..b6af370b91
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h
@@ -0,0 +1,58 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup BSP_MCU
+ * @defgroup BSP_MCU_RA4W1 RA4W1
+ * @includedoc config_bsp_ra4w1_fsp.html
+ * @{
+ **********************************************************************************************************************/
+
+/** @} (end defgroup BSP_MCU_RA4W1) */
+
+#ifndef BSP_MCU_INFO_H
+#define BSP_MCU_INFO_H
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+
+/* BSP MCU Specific Includes. */
+#include "../../src/bsp/mcu/ra4w1/bsp_elc.h"
+#include "../../src/bsp/mcu/ra4w1/bsp_feature.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+typedef elc_event_t bsp_interrupt_event_t;
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Exported global functions (to be accessed by other files)
+ **********************************************************************************************************************/
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c
new file mode 100644
index 0000000000..353bd0247e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_agt/r_agt.c
@@ -0,0 +1,915 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_agt.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "AGT" in ASCII, used to determine if channel is open. */
+#define AGT_OPEN                                (0x00414754ULL)
+
+#define AGT_PRV_VALID_CHANNEL_MASK              (0x3U)
+
+#define AGT_COMPARE_MATCH_A_OUTPUT              (0x03U) ///< Enabling AGTOAn pin
+#define AGT_COMPARE_MATCH_B_OUTPUT              (0x30U) ///< Enabling AGTOBn pin
+
+#define AGT_SOURCE_CLOCK_PCLKB_BITS             (0x3U)
+
+#define FSUB_FREQUENCY_HZ                       (32768U)
+
+#define AGT_PRV_CLOCK_PCLKB_DIV_8               (1U)
+#define AGT_PRV_CLOCK_PCLKB_DIV_2               (3U)
+
+#define AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER       (2U)
+#define AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH         (3U)
+
+#define AGT_PRV_AGTCR_FORCE_STOP                (0xF4U)
+#define AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS    (0x4U)
+#define AGT_PRV_AGTCR_STATUS_FLAGS              (0xF0U)
+#define AGT_PRV_AGTCR_STOP_TIMER                (0xF0U)
+#define AGT_PRV_AGTCR_START_TIMER               (0xF1U)
+
+#define AGT_PRV_AGTCMSR_PIN_B_OFFSET            (4U)
+#define AGT_PRV_AGTCMSR_VALID_BITS              (0x77U)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void r_agt_period_register_set(agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts);
+
+static void r_agt_hardware_cfg(agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static uint32_t r_agt_clock_frequency_get(R_AGT0_Type * p_agt_regs);
+
+static fsp_err_t r_agt_common_preamble(agt_instance_ctrl_t * p_instance_ctrl);
+
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+static fsp_err_t r_agt_open_param_checking(agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+#endif
+
+/* ISRs. */
+void agt_int_isr(void);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/** Version data structure. */
+static const fsp_version_t s_agt_version =
+{
+    .api_version_minor  = TIMER_API_VERSION_MINOR,
+    .api_version_major  = TIMER_API_VERSION_MAJOR,
+    .code_version_minor = AGT_CODE_VERSION_MINOR,
+    .code_version_major = AGT_CODE_VERSION_MAJOR,
+};
+
+/* The period for channel 0 must be known to calculate the frequency of channel 1 if the count source is AGT0
+ * underflow. */
+static uint32_t gp_prv_agt_periods[2];
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/** AGT Implementation of General Timer Driver  */
+const timer_api_t g_timer_on_agt =
+{
+    .open         = R_AGT_Open,
+    .stop         = R_AGT_Stop,
+    .start        = R_AGT_Start,
+    .reset        = R_AGT_Reset,
+    .enable       = R_AGT_Enable,
+    .disable      = R_AGT_Disable,
+    .periodSet    = R_AGT_PeriodSet,
+    .dutyCycleSet = R_AGT_DutyCycleSet,
+    .infoGet      = R_AGT_InfoGet,
+    .statusGet    = R_AGT_StatusGet,
+    .close        = R_AGT_Close,
+    .versionGet   = R_AGT_VersionGet
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup AGT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the AGT module instance. Implements @ref timer_api_t::open.
+ *
+ * The AGT hardware does not support one-shot functionality natively.  The one-shot feature is therefore implemented in
+ * the AGT HAL layer. For a timer configured as a one-shot timer, the timer is stopped upon the first timer expiration.
+ *
+ * The AGT implementation of the general timer can accept an optional agt_extended_cfg_t extension parameter.  For
+ * AGT, the extension specifies the clock to be used as timer source and the output pin configurations.  If the
+ * extension parameter is not specified (NULL), the default clock PCLKB is used and the output pins are disabled.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_Open
+ *
+ * @retval FSP_SUCCESS                 Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION           A required input pointer is NULL or the period is not in the valid range of
+ *                                     1 to 0xFFFF.
+ * @retval FSP_ERR_ALREADY_OPEN        R_AGT_Open has already been called for this p_ctrl.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED    A required interrupt has not been enabled in the vector table.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT  Requested channel number is not available on AGT.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    fsp_err_t err = r_agt_open_param_checking(p_instance_ctrl, p_cfg);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+#endif
+
+    uint32_t base_address = (uint32_t) R_AGT0 + (p_cfg->channel * ((uint32_t) R_AGT1 - (uint32_t) R_AGT0));
+    p_instance_ctrl->p_reg = (R_AGT0_Type *) base_address;
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* Power on the AGT channel. */
+    R_BSP_MODULE_START(FSP_IP_AGT, p_cfg->channel);
+
+    /* Forcibly stop timer and clear flags. */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS;
+
+    /* Clear AGTMR2 before AGTMR1 is set. Reference Note 3 in section 25.2.6 "AGT Mode Register 2 (AGTMR2)"
+     * of the RA6M3 manual R01UH0886EJ0100. */
+    p_instance_ctrl->p_reg->AGTMR2 = 0U;
+
+    /* Set count source and divider and configure pins. */
+    r_agt_hardware_cfg(p_instance_ctrl, p_cfg);
+
+    /* Set period register and update duty cycle if output mode is used for one-shot or periodic mode. */
+    r_agt_period_register_set(p_instance_ctrl, p_cfg->period_counts);
+
+    if (p_cfg->cycle_end_irq >= 0)
+    {
+        R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl);
+    }
+
+    p_instance_ctrl->open = AGT_OPEN;
+
+    /* All done.  */
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Starts timer. Implements @ref timer_api_t::start.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_Start
+ *
+ * @retval FSP_SUCCESS                 Timer started.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is null.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Start timer */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER;
+
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* If using output compare in one-shot mode, update the compare match registers after starting the timer. This
+     * ensures the output pin will not toggle again right after the period ends. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        /* Verify the timer is started before modifying any other AGT registers. Reference section 25.4.1 "Count
+         * Operation Start and Stop Control" in the RA6M3 manual R01UH0886EJ0100. */
+        FSP_HARDWARE_REGISTER_WAIT(1U, p_instance_ctrl->p_reg->AGTCR_b.TCSTF);
+        p_instance_ctrl->p_reg->AGTCMA = UINT16_MAX;
+        p_instance_ctrl->p_reg->AGTCMB = UINT16_MAX;
+    }
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops the timer.  Implements @ref timer_api_t::stop.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_Stop
+ *
+ * @retval FSP_SUCCESS                 Timer stopped.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Stop (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets the counter value to the period minus one. Implements @ref timer_api_t::reset.
+ *
+ * @retval FSP_SUCCESS                 Counter reset.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is NULL
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Reset (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Reset counter to period minus one. */
+    p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_Enable
+ *
+ * @retval FSP_SUCCESS                 External events successfully enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Enable (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Reset counter to period minus one. */
+    p_instance_ctrl->p_reg->AGT = (uint16_t) (p_instance_ctrl->period - 1U);
+
+    /* Enable captures. */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_START_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_Disable
+ *
+ * @retval FSP_SUCCESS                 External events successfully disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Disable (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Disable captures. */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_STOP_TIMER;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates period. The new period is updated immediately and the counter is reset to the maximum value. Implements
+ * @ref timer_api_t::periodSet.
+ *
+ * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register.
+ * If this function is called while the timer is running and an AGT underflow occurs during processing, the duty cycle
+ * will not be the desired 50% duty cycle until the counter underflow after processing completes.
+ *
+ * @warning Stop the timer before calling this function if one-shot output is used.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_PeriodSet
+ *
+ * @retval FSP_SUCCESS                 Period value updated.
+ * @retval FSP_ERR_ASSERTION           A required pointer was NULL, or the period was not in the valid range of
+ *                                     1 to 0xFFFF.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+
+    /* Validate period parameter. */
+    FSP_ASSERT(0U != period_counts);
+    FSP_ASSERT(period_counts <= AGT_MAX_PERIOD);
+#endif
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Set period. */
+    r_agt_period_register_set(p_instance_ctrl, period_counts);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Updates duty cycle. If the timer is counting, the new duty cycle is reflected after the next counter underflow.
+ * Implements @ref timer_api_t::dutyCycleSet.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_DutyCycleSet
+ *
+ * @retval FSP_SUCCESS                 Duty cycle updated.
+ * @retval FSP_ERR_ASSERTION           A required pointer was NULL, or the pin was not AGT_AGTO_AGTOA or AGT_AGTO_AGTOB.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Duty cycle was not in the valid range of 0 to period (counts) - 1
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ * @retval FSP_ERR_UNSUPPORTED         AGT_CFG_OUTPUT_SUPPORT_ENABLE is 0.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
+{
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+ #if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT((pin == AGT_OUTPUT_PIN_AGTOA) || (pin == AGT_OUTPUT_PIN_AGTOB));
+ #endif
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+ #if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ERROR_RETURN(duty_cycle_counts < (p_instance_ctrl->period), FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    uint32_t temp_duty_cycle_counts         = duty_cycle_counts;
+    uint32_t agtcmsr_agtoab_start_level_bit = 1U << 2 << (4 * pin);
+    agt_extended_cfg_t const * p_extend     = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
+    if (p_extend->agtoab_settings & agtcmsr_agtoab_start_level_bit)
+    {
+        /* Invert duty cycle if this pin starts high since the high portion is at the beginning of the cycle. */
+        temp_duty_cycle_counts = p_instance_ctrl->period - temp_duty_cycle_counts;
+    }
+
+    /* Set duty cycle. */
+    volatile uint16_t * const p_agtcm = &p_instance_ctrl->p_reg->AGTCMA;
+    p_agtcm[pin] = (uint16_t) temp_duty_cycle_counts;
+
+    return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(duty_cycle_counts);
+    FSP_PARAMETER_NOT_USED(pin);
+
+    FSP_RETURN(FSP_ERR_UNSUPPORTED);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Gets timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_InfoGet
+ *
+ * @retval FSP_SUCCESS                 Period, count direction, and frequency stored in p_info.
+ * @retval FSP_ERR_ASSERTION           A required pointer is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_info);
+#endif
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Get and store period */
+    p_info->period_counts = p_instance_ctrl->period;
+
+    /* Get and store clock frequency */
+    agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
+    if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source)
+    {
+        /* Clock frequency is the AGT0 clock frequency divided by the period of AGT0. */
+        p_info->clock_frequency = r_agt_clock_frequency_get(R_AGT0) / gp_prv_agt_periods[0];
+    }
+    else
+    {
+        p_info->clock_frequency = r_agt_clock_frequency_get(p_instance_ctrl->p_reg);
+    }
+
+    /* AGT supports only counting down direction */
+    p_info->count_direction = TIMER_DIRECTION_DOWN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Retrieves the current state and counter value stores them in p_status. Implements @ref timer_api_t::statusGet.
+ *
+ * Example:
+ * @snippet r_agt_example.c R_AGT_StatusGet
+ *
+ * @retval FSP_SUCCESS                 Current status and counter value provided in p_status.
+ * @retval FSP_ERR_ASSERTION           A required pointer is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_status);
+#endif
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Read the state. */
+    p_status->state = (timer_state_t) p_instance_ctrl->p_reg->AGTCR_b.TCSTF;
+
+    /* Read counter value */
+    p_status->counter = p_instance_ctrl->p_reg->AGT;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops counter, disables interrupts, disables output pins, and clears internal driver data.  Implements
+ * @ref timer_api_t::close.
+ *
+ *
+ *
+ * @retval FSP_SUCCESS                 Timer closed.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_Close (timer_ctrl_t * const p_ctrl)
+{
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl;
+
+    fsp_err_t err = r_agt_common_preamble(p_instance_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
+
+    /* Clear AGT output. */
+    p_instance_ctrl->p_reg->AGTIOC = 0U;
+
+    if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq)
+    {
+        NVIC_DisableIRQ(p_instance_ctrl->p_cfg->cycle_end_irq);
+        R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl);
+    }
+
+    p_instance_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets driver version based on compile time macros.  Implements @ref timer_api_t::versionGet.
+ *
+ * @retval     FSP_SUCCESS          Version in p_version.
+ * @retval     FSP_ERR_ASSERTION    The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_AGT_VersionGet (fsp_version_t * const p_version)
+{
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify parameters are valid */
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    p_version->version_id = s_agt_version.version_id;
+
+    return FSP_SUCCESS;
+}
+
+/** @} (end addtogroup AGT) */
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+
+/*******************************************************************************************************************//**
+ * Parameter checking for R_AGT_Open.
+ *
+ * @param[in] p_instance_ctrl          Pointer to instance control structure.
+ * @param[in]  p_cfg              Configuration structure for this instance
+ *
+ * @retval FSP_SUCCESS                 Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION           A required input pointer is NULL or the period is not in the valid range of
+ *                                     1 to 0xFFFF.
+ * @retval FSP_ERR_ALREADY_OPEN        R_AGT_Open has already been called for this p_ctrl.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED    A required interrupt has not been enabled in the vector table.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT  Requested channel number is not available on AGT.
+ **********************************************************************************************************************/
+static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_extend);
+    FSP_ERROR_RETURN(AGT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    /* Enable IRQ if user supplied a callback function,
+     *  or if the timer is a one-shot timer (so the driver is able to
+     *  turn off the timer after one period. */
+    if ((NULL != p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode))
+    {
+        /* Return error if IRQ is required and not in the vector table. */
+        FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+    }
+
+    FSP_ASSERT(0U != p_cfg->period_counts);
+
+    /* Validate period parameter. */
+    FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD);
+
+    /* Validate channel number. */
+    FSP_ERROR_RETURN(((1U << p_cfg->channel) & AGT_PRV_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+
+    /* AGT_CLOCK_AGT0_UNDERFLOW is not allowed on AGT channel 0. */
+    agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend;
+    FSP_ASSERT((AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source) || (1U == p_cfg->channel));
+
+    /* Validate divider. */
+    if (AGT_CLOCK_PCLKB == p_extend->count_source)
+    {
+        /* Allowed dividers for PCLKB are 1, 2, and 8. */
+        FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_8);
+        FSP_ASSERT(p_cfg->source_div != TIMER_SOURCE_DIV_4);
+    }
+    else if (AGT_CLOCK_AGT0_UNDERFLOW == p_extend->count_source)
+    {
+        /* Divider not used if AGT0 underflow is selected as count source. */
+        FSP_ASSERT(p_cfg->source_div == TIMER_SOURCE_DIV_1);
+    }
+    else
+    {
+        /* Allowed dividers for LOCO and SUBCLOCK are 1, 2, 4, 8, 16, 32, 64, and 128. */
+        FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128);
+    }
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Common code at the beginning of all AGT functions except open.
+ *
+ * @param[in] p_instance_ctrl          Pointer to instance control structure.
+ *
+ * @retval FSP_SUCCESS                 No invalid conditions detected, timer state matches expected state.
+ * @retval FSP_ERR_ASSERTION           p_ctrl is null.
+ * @retval FSP_ERR_NOT_OPEN            The instance control structure is not opened.
+ **********************************************************************************************************************/
+static fsp_err_t r_agt_common_preamble (agt_instance_ctrl_t * p_instance_ctrl)
+{
+#if AGT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Ensure timer state reflects expected status. Reference section 25.4.1 "Count Operation Start and Stop Control"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    uint32_t agtcr_tstart = p_instance_ctrl->p_reg->AGTCR_b.TSTART;
+    FSP_HARDWARE_REGISTER_WAIT(agtcr_tstart, p_instance_ctrl->p_reg->AGTCR_b.TCSTF);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets count source and divider.
+ *
+ * @note Counter must be stopped before entering this function.
+ *
+ * @param[in]  p_instance_ctrl    Control block for this instance
+ * @param[in]  p_cfg              Configuration structure for this instance
+ **********************************************************************************************************************/
+static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Update the divider for PCLKB. */
+    agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend;
+    uint32_t count_source_int           = (uint32_t) p_extend->count_source;
+    uint32_t agtmr2  = 0U;
+    uint32_t agtcmsr = 0U;
+    uint32_t tedgsel = 0U;
+    uint32_t agtioc  = p_extend->agtio_filter;
+    uint32_t mode    = p_extend->measurement_mode & R_AGT0_AGTMR1_TMOD_Msk;
+    uint32_t edge    = 0U;
+    if (AGT_CLOCK_PCLKB == p_extend->count_source)
+    {
+        if (TIMER_SOURCE_DIV_1 != p_cfg->source_div)
+        {
+            /* Toggle the second bit if the count_source_int is not 0 to map PCLKB / 8 to 1 and PCLKB / 2 to 3. */
+            count_source_int   = p_cfg->source_div ^ 2U;
+            count_source_int <<= R_AGT0_AGTMR1_TCK_Pos;
+        }
+    }
+
+#if AGT_CFG_INPUT_SUPPORT_ENABLE
+    else if (AGT_CLOCK_AGTIO & p_extend->count_source)
+    {
+        /* If the count source is external, configure the AGT for event counter mode. */
+        mode                             = AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER;
+        count_source_int                 = 0U;
+        edge                            |= (p_extend->trigger_edge & R_AGT0_AGTMR1_TEDGPL_Msk);
+        agtioc                          |= (p_extend->enable_pin & R_AGT0_AGTIOC_TIOGT_Msk);
+        p_instance_ctrl->p_reg->AGTISR   = (p_extend->enable_pin & R_AGT0_AGTISR_EEPS_Msk);
+        p_instance_ctrl->p_reg->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO);
+    }
+#endif
+    else if (AGT_CLOCK_AGT0_UNDERFLOW != p_extend->count_source)
+    {
+        /* Update the divider for LOCO/subclock. */
+        agtmr2 = p_cfg->source_div;
+    }
+    else
+    {
+        /* No divider can be used when count source is AGT_CLOCK_AGT0_UNDERFLOW. */
+    }
+
+    uint32_t agtmr1 = (count_source_int | edge) | mode;
+
+    /* Configure output settings. */
+
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Set output if requested */
+    agtcmsr = p_extend->agtoab_settings & AGT_PRV_AGTCMSR_VALID_BITS;
+
+    /* Set initial duty cycle for PWM mode in open.  Duty cycle is set for other modes in r_agt_period_register_set. */
+    if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode)
+    {
+        uint32_t inverted_duty_cycle = p_instance_ctrl->p_cfg->period_counts -
+                                       p_instance_ctrl->p_cfg->duty_cycle_counts;
+        uint32_t agtcma = p_instance_ctrl->p_cfg->duty_cycle_counts;
+        uint32_t agtcmb = p_instance_ctrl->p_cfg->duty_cycle_counts;
+        if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtoa)
+        {
+            agtcma = inverted_duty_cycle;
+        }
+
+        if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtob)
+        {
+            agtcmb = inverted_duty_cycle;
+        }
+
+        p_instance_ctrl->p_reg->AGTCMA = (uint16_t) agtcma;
+        p_instance_ctrl->p_reg->AGTCMB = (uint16_t) agtcmb;
+    }
+
+    /* Configure TEDGSEL bit based on user input. */
+    if (AGT_PIN_CFG_DISABLED != p_extend->agto)
+    {
+        /* Set the TOE bit if AGTO is enabled.  AGTO can be enabled in any mode. */
+        agtioc |= (1U << R_AGT0_AGTIOC_TOE_Pos);
+
+        if (AGT_PIN_CFG_START_LEVEL_LOW == p_extend->agto)
+        {
+            /* Configure the start level of AGTO. */
+            tedgsel |= (1U << R_AGT0_AGTIOC_TEDGSEL_Pos);
+        }
+    }
+#endif
+#if AGT_CFG_INPUT_SUPPORT_ENABLE && AGT_CFG_OUTPUT_SUPPORT_ENABLE
+    else
+#endif
+#if AGT_CFG_INPUT_SUPPORT_ENABLE
+    {
+        /* This if statement applies when p_extend->measurement_mode is AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL or
+         * AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL because the high level bit is in bit 4 and was masked off of mode. */
+        if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == mode)
+        {
+            /* Level is stored with measurement mode for pulse width mode. */
+            tedgsel = p_extend->measurement_mode >> 4U;
+        }
+        else
+        {
+            /* Use the trigger edge for pulse period or event counting modes. */
+            tedgsel = (p_extend->trigger_edge & R_AGT0_AGTIOC_TEDGSEL_Msk);
+        }
+    }
+#endif
+
+    agtioc |= tedgsel;
+
+    p_instance_ctrl->p_reg->AGTIOC  = (uint8_t) agtioc;
+    p_instance_ctrl->p_reg->AGTCMSR = (uint8_t) agtcmsr;
+    p_instance_ctrl->p_reg->AGTMR1  = (uint8_t) agtmr1;
+    p_instance_ctrl->p_reg->AGTMR2  = (uint8_t) agtmr2;
+}
+
+/*******************************************************************************************************************//**
+ * Sets period register and updates compare match registers in one-shot and periodic mode.
+ *
+ * @param[in]  p_instance_ctrl    Control block for this instance
+ * @param[in]  period_counts      AGT period in counts
+ **********************************************************************************************************************/
+static void r_agt_period_register_set (agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts)
+{
+    /* Store the period value so it can be retrieved later. */
+    p_instance_ctrl->period = period_counts;
+    gp_prv_agt_periods[p_instance_ctrl->p_cfg->channel] = period_counts;
+
+    uint16_t period_reg = (uint16_t) (period_counts - 1U);
+
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+    uint16_t duty_cycle_counts = 0U;
+    if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
+    {
+        duty_cycle_counts = (uint16_t) (period_counts >> 1);
+    }
+    else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        duty_cycle_counts = period_reg;
+    }
+    else
+    {
+        /* Do nothing, duty cycle should not be updated in R_AGT_PeriodSet. */
+    }
+
+    if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode)
+    {
+        p_instance_ctrl->p_reg->AGTCMA = duty_cycle_counts;
+        p_instance_ctrl->p_reg->AGTCMB = duty_cycle_counts;
+    }
+#endif
+
+    /* Set counter to period minus one. */
+    p_instance_ctrl->p_reg->AGT = period_reg;
+}
+
+/*******************************************************************************************************************//**
+ * Obtains the clock frequency of AGT for all clock sources except AGT0 underflow, with divisor applied.
+ *
+ * @param[in]  p_agt_regs         Registers of AGT channel used
+ *
+ * @return Source clock frequency of AGT in Hz, divider applied.
+ **********************************************************************************************************************/
+static uint32_t r_agt_clock_frequency_get (R_AGT0_Type * p_agt_regs)
+{
+    uint32_t           clock_freq_hz    = 0U;
+    uint8_t            count_source_int = p_agt_regs->AGTMR1_b.TCK;
+    timer_source_div_t divider          = TIMER_SOURCE_DIV_1;
+    if (0U == (count_source_int & (~AGT_SOURCE_CLOCK_PCLKB_BITS)))
+    {
+        /* Call CGC function to obtain current PCLKB clock frequency. */
+        clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB);
+
+        /* If Clock source is PCLKB or derived from PCLKB */
+        divider = (timer_source_div_t) count_source_int;
+        if (0U != divider)
+        {
+            /* Set divider to 3 to divide by 8 when AGTMR1.TCK is 1 (PCLKB / 8). Set divider to 1 to divide by 2 when
+             * AGTMR1.TCK is 3 (PCLKB / 2). XOR with 2 to convert 1 to 3 and 3 to 1. */
+            divider ^= 2U;
+        }
+    }
+    else
+    {
+        /* Else either fSUB clock or LOCO clock is used. The frequency is set to 32Khz (32768). This function does not
+         * support AGT0 underflow as count source.  */
+        clock_freq_hz = FSUB_FREQUENCY_HZ;
+
+        divider = (timer_source_div_t) p_agt_regs->AGTMR2_b.CKS;
+    }
+
+    clock_freq_hz >>= divider;
+
+    return clock_freq_hz;
+}
+
+/*********************************************************************************************************************
+ * AGT counter underflow interrupt.
+ **********************************************************************************************************************/
+void agt_int_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Save AGTCR to determine the source of the interrupt. */
+    uint32_t agtcr = p_instance_ctrl->p_reg->AGTCR;
+
+    /* If the channel is configured to be one-shot mode, stop the timer. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+
+        /* Forcibly stopping the timer resets AGTCMSR, AGTCMA, and AGTCMB. AGTCMA and AGTCMB are based on the
+         * timer period, but AGTCMSR must be saved so it can be restored. */
+        uint8_t agtcmsr = p_instance_ctrl->p_reg->AGTCMSR;
+#endif
+
+        /* Stop timer */
+        p_instance_ctrl->p_reg->AGTCR = AGT_PRV_AGTCR_FORCE_STOP;
+        agtcr &= AGT_PRV_AGTCR_STATUS_FLAGS;
+
+        /* Set counter to period minus one. */
+        r_agt_period_register_set(p_instance_ctrl, p_instance_ctrl->period);
+
+#if AGT_CFG_OUTPUT_SUPPORT_ENABLE
+
+        /* Restore AGTCMSR. */
+        p_instance_ctrl->p_reg->AGTCMSR = agtcmsr;
+#endif
+    }
+
+    /* Invoke the callback function if it is set. */
+    if (NULL != p_instance_ctrl->p_cfg->p_callback)
+    {
+        /* Setup parameters for the user-supplied callback function. */
+        timer_callback_args_t callback_args;
+        if (agtcr & R_AGT0_AGTCR_TUNDF_Msk)
+        {
+            callback_args.event = TIMER_EVENT_CYCLE_END;
+        }
+
+#if AGT_CFG_INPUT_SUPPORT_ENABLE
+        else
+        {
+            callback_args.event = TIMER_EVENT_CAPTURE_A;
+            uint32_t reload_value = p_instance_ctrl->period - 1U;
+            callback_args.capture = reload_value - p_instance_ctrl->p_reg->AGT;
+
+            /* The AGT counter is not reset in pulse width measurement mode. Reset it by software. Note that this
+             * will restart the counter if a new capture has already started. Application writers must ensure that
+             * this interrupt processing completes before the next capture begins. */
+            if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == p_instance_ctrl->p_reg->AGTMR1_b.TMOD)
+            {
+                p_instance_ctrl->p_reg->AGT = (uint16_t) reload_value;
+            }
+            else
+            {
+                /* Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1
+                 * Reference section 25.4.5 of the RA6M3 manual R01UH0886EJ0100. */
+                callback_args.capture++;
+            }
+        }
+#endif
+
+        callback_args.p_context = p_instance_ctrl->p_cfg->p_context;
+        p_instance_ctrl->p_cfg->p_callback(&callback_args);
+    }
+
+    /* Clear flags in AGTCR. */
+    p_instance_ctrl->p_reg->AGTCR = (uint8_t) (agtcr & ~AGT_PRV_AGTCR_STATUS_FLAGS);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c
new file mode 100644
index 0000000000..2f027e1c60
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_flash_lp/r_flash_lp.c
@@ -0,0 +1,2636 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "bsp_api.h"
+#include 
+
+#include "r_flash_lp.h"
+
+/* Configuration for this package. */
+#include "r_flash_lp_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "OPEN" in ASCII, used to avoid multiple open. */
+#define FLASH_HP_OPEN                                 (0x4f50454eULL)
+
+#define FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ          4000000U /// Minimum FCLK for Flash Operations in Hz
+
+/* The number of CPU cycles per each timeout loop. */
+#ifndef FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP
+ #if defined(__GNUC__)
+  #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP    (6U)
+ #elif defined(__ICCARM__)
+  #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP    (6U)
+ #endif
+#endif
+
+#define FLASH_LP_HZ_IN_MHZ                            (1000000U)
+
+#if defined(__ICCARM__)
+ #define BSP_ATTRIBUTE_STACKLESS                      __stackless
+#elif defined(__GNUC__)
+
+ #define BSP_ATTRIBUTE_STACKLESS                      __attribute__((naked))
+#endif
+
+/* Roughly 4 cycles per loop */
+#define FLASH_LP_DELAY_LOOP_CYCLES                    4U
+
+/*  flash mode definition (FENTRYR Register setting)*/
+#define FLASH_LP_FENTRYR_DATAFLASH_PE_MODE            (0xAA80U)
+#define FLASH_LP_FENTRYR_CODEFLASH_PE_MODE            (0xAA01U)
+#define FLASH_LP_FENTRYR_READ_MODE                    (0xAA00U)
+
+/*  flash mode definition (FPMCR Register setting)*/
+#define FLASH_LP_DATAFLASH_PE_MODE                    (0x10U)
+#define FLASH_LP_READ_MODE                            (0x08U)
+#define FLASH_LP_LVPE_MODE                            (0x40U)
+#define FLASH_LP_DISCHARGE_1                          (0x12U)
+#define FLASH_LP_DISCHARGE_2                          (0x92U)
+#define FLASH_LP_CODEFLASH_PE_MODE                    (0x82U)
+
+/*  operation definition (FCR Register setting)*/
+#define FLASH_LP_FCR_WRITE                            (0x81U)
+#define FLASH_LP_FCR_ERASE                            (0x84U)
+#define FLASH_LP_FCR_BLANKCHECK                       (0x83U)
+#define FLASH_LP_FCR_CLEAR                            (0x00U)
+
+/*  operation definition (FEXCR Register setting)*/
+#define FLASH_LP_FEXCR_STARTUP                        (0x81U)
+#define FLASH_LP_FEXCR_AW                             (0x82U)
+#define FLASH_LP_FEXCR_OCDID1                         (0x83U)
+#define FLASH_LP_FEXCR_OCDID2                         (0x84U)
+#define FLASH_LP_FEXCR_OCDID3                         (0x85U)
+#define FLASH_LP_FEXCR_OCDID4                         (0x86U)
+#define FLASH_LP_FEXCR_CLEAR                          (0x00U)
+#define FLASH_LP_FEXCR_MF4_AW_STARTUP                 (0x82U)
+
+/* Wait Process definition */
+#define FLASH_LP_WAIT_TDIS                            (3U)
+#define FLASH_LP_WAIT_TMS_MID                         (4U)
+#define FLASH_LP_WAIT_TMS_HIGH                        (6U)
+#define FLASH_LP_WAIT_TDSTOP                          (6U)
+
+/* Flash information */
+/* Used for DataFlash */
+#define FLASH_LP_DATAFLASH_READ_BASE_ADDR             (0x40100000U)
+#define FLASH_LP_DATAFLASH_WRITE_BASE_ADDR            (0xFE000000U)
+#define FLASH_LP_DATAFLASH_ADDR_OFFSET                (FLASH_LP_DATAFLASH_WRITE_BASE_ADDR - \
+                                                       FLASH_LP_DATAFLASH_READ_BASE_ADDR)
+
+#define FLASH_LP_FENTRYR_DF_PE_MODE                   (0x0080U)
+#define FLASH_LP_FENTRYR_CF_PE_MODE                   (0x0001U)
+#define FLASH_LP_FENTRYR_PE_MODE_BITS                 (FLASH_LP_FENTRYR_DF_PE_MODE | FLASH_LP_FENTRYR_CF_PE_MODE)
+
+#if BSP_FEATURE_FLASH_LP_VERSION == 4
+ #define FLASH_LP_PRV_FENTRYR                         R_FACI_LP->FENTRYR_MF4
+#else
+ #define FLASH_LP_PRV_FENTRYR                         R_FACI_LP->FENTRYR
+#endif
+
+#define FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS           (0xFEFFU)
+
+#define FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK         (0x8000U)
+
+#define FLASH_LP_FCR_PROCESSING_MASK                  (0x80U)
+#define FLASH_LP_FEXCR_PROCESSING_MASK                (0x80U)
+
+#define FLASH_LP_MAX_WRITE_CF_TIME_US                 (1411)
+#define FLASH_LP_MAX_WRITE_DF_TIME_US                 (886)
+#define FLASH_LP_MAX_BLANK_CHECK_TIME_US              (88)
+#define FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US           (289000)
+#define FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US           (299000)
+#define FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US         (592000)
+
+#define FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS           (0x10)
+#define FLASH_LP_FSTATR2_ERASE_ERROR_BITS             (0x11)
+#define FLASH_LP_FSTATR2_WRITE_ERROR_BITS             0x12
+
+#define FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ        (32)
+
+#define FLASH_LP_6BIT_MASK                            (0x3FU)
+#define FLASH_LP_5BIT_MASK                            (0x1FU)
+
+#define FLASH_LP_DF_START_ADDRESS                     (0x40100000)
+
+#define FLASH_LP_FPR_UNLOCK                           0xA5U
+
+/** The maximum timeout for commands is 100usec when FCLK is 16 MHz i.e. 1600 FCLK cycles.
+ * Assuming worst case of ICLK at 240 MHz and FCLK at 4 MHz, and optimization set to max such that
+ * each count decrement loop takes only 5 cycles, then ((240/4)*1600)/5 = 19200 */
+#define FLASH_LP_FRDY_CMD_TIMEOUT                     (19200)
+
+#define FLASH_LP_REGISTER_WAIT_TIMEOUT(val, reg, timeout, err) \
+    while (val != reg)                                         \
+    {                                                          \
+        if (0 == timeout)                                      \
+        {                                                      \
+            return err;                                        \
+        }                                                      \
+        timeout--;                                             \
+    }
+
+/******************************************************************************
+ * Typedef definitions
+ ******************************************************************************/
+
+/**
+ * @struct r_dataflash_data_t
+ * DATAFLASH information values
+ */
+typedef struct r_dataflash_data_t
+{
+    uint32_t start_addr;               /* start address (Erase) or Ram Source for Write, Dest for read */
+    uint32_t end_addr;                 /* end address (Erase), or Flash Start address which will be read/written */
+    uint32_t write_cnt;                /* bytes remaining to do */
+} r_dataflash_data_t;
+
+typedef struct r_dataflash_erase_t
+{
+    uint32_t start_addr;               /* start address (Erase) or Ram Source for Write, Dest for read */
+    uint32_t end_addr;                 /* end address (Erase), or Flash Start address which will be read/written */
+    uint32_t write_cnt;                /* bytes remaining to do */
+} r_dataflash_erase_t;
+
+/**   FLASH operation command values */
+typedef enum e_flash_command
+{
+    FLASH_COMMAND_ACCESSWINDOW,        /**< Flash access window command */
+    FLASH_COMMAND_STARTUPAREA          /**< Flash change startup area command */
+} r_flash_command_t;
+
+/******************************************************************************
+ * Exported global variables
+ ******************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void r_flash_lp_init(flash_lp_instance_ctrl_t * p_ctrl);
+
+static void r_flash_lp_df_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl);
+
+static inline bool r_flash_lp_frdyi_df_bgo_blankcheck(flash_lp_instance_ctrl_t * p_ctrl,
+                                                      flash_callback_args_t    * p_cb_data);
+
+static inline bool r_flash_lp_frdyi_df_bgo_erase(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data);
+
+static inline bool r_flash_lp_frdyi_df_bgo_write(flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data);
+
+static fsp_err_t r_flash_lp_set_fisr(flash_lp_instance_ctrl_t * const p_ctrl);
+
+static fsp_err_t r_flash_lp_df_write_monitor(flash_lp_instance_ctrl_t * const p_ctrl);
+
+static fsp_err_t r_flash_lp_pe_mode_exit(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_setup(flash_lp_instance_ctrl_t * p_ctrl);
+
+static void r_flash_lp_df_write_operation(const uint32_t psrc_addr, uint32_t dest_addr);
+
+static void r_flash_lp_process_command(const uint32_t start_addr, uint32_t num_bytes,
+                                       uint32_t command) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_command_finish(uint32_t timeout) PLACE_IN_RAM_SECTION;
+
+static void r_flash_lp_delay_us(uint32_t us, uint32_t mhz) PLACE_IN_RAM_SECTION __attribute__((noinline));
+
+static void r_flash_lp_reset(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION;
+
+static void r_flash_lp_write_fpmcr(uint8_t value) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_wait_for_ready(flash_lp_instance_ctrl_t * const p_ctrl,
+                                           uint32_t                         timeout,
+                                           uint32_t                         error_bits,
+                                           fsp_err_t                        return_code) PLACE_IN_RAM_SECTION;
+
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+static fsp_err_t r_flash_lp_df_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl,
+                                          uint32_t                         start_address,
+                                          uint32_t                         num_bytes,
+                                          flash_result_t                 * result);
+
+static fsp_err_t r_flash_lp_df_erase(flash_lp_instance_ctrl_t * const p_ctrl,
+                                     uint32_t                         block_address,
+                                     uint32_t                         num_blocks,
+                                     uint32_t                         block_size);
+
+static fsp_err_t r_flash_lp_df_write(flash_lp_instance_ctrl_t * const p_ctrl,
+                                     uint32_t const                   src_start_address,
+                                     uint32_t                         dest_start_address,
+                                     uint32_t                         num_bytes);
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+static void r_flash_lp_memcpy(uint8_t * const dest, uint8_t * const src, uint32_t len) PLACE_IN_RAM_SECTION;
+
+static void r_flash_lp_cf_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_extra_check(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_extra_command_finish(uint32_t timeout) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_set_startup_area_boot(flash_lp_instance_ctrl_t * const p_ctrl,
+                                                  flash_startup_area_swap_t        swap_type,
+                                                  bool                             temporary) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_cf_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl,
+                                          uint32_t                         start_address,
+                                          uint32_t                         num_bytes,
+                                          flash_result_t                 * result) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_cf_erase(flash_lp_instance_ctrl_t * const p_ctrl,
+                                     uint32_t                         block_address,
+                                     uint32_t                         num_blocks,
+                                     uint32_t                         block_size) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_cf_write(flash_lp_instance_ctrl_t * const p_ctrl,
+                                     uint32_t const                   src_start_address,
+                                     uint32_t                         dest_start_address,
+                                     uint32_t                         num_bytes) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_access_window_set(flash_lp_instance_ctrl_t * const p_ctrl,
+                                              uint32_t const                   start_addr,
+                                              uint32_t const                   end_addr) PLACE_IN_RAM_SECTION;
+
+static fsp_err_t r_flash_lp_set_id_code(flash_lp_instance_ctrl_t * const p_ctrl,
+                                        uint8_t const * const            p_id_code,
+                                        flash_id_code_mode_t             mode) PLACE_IN_RAM_SECTION;
+
+static void r_flash_lp_cf_write_operation(const uint32_t psrc_addr, const uint32_t dest_addr) PLACE_IN_RAM_SECTION;
+
+static void r_flash_lp_extra_operation(const uint32_t    start_addr_startup_value,
+                                       const uint32_t    end_addr,
+                                       r_flash_command_t command) PLACE_IN_RAM_SECTION;
+
+#endif
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+static fsp_err_t r_flash_lp_common_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl);
+
+static fsp_err_t r_flash_lp_write_read_bc_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl,
+                                                             uint32_t                         flash_address,
+                                                             uint32_t const                   num_bytes,
+                                                             bool                             check_write);
+
+#endif
+
+/** FRDY ISR is only used for DataFlash operations. For Code flash operations are blocking. Therefore ISR does
+ * not need to be located in RAM.
+ */
+void fcu_frdyi_isr(void);
+
+/***********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+const flash_api_t g_flash_on_flash_lp =
+{
+    .open                 = R_FLASH_LP_Open,
+    .close                = R_FLASH_LP_Close,
+    .write                = R_FLASH_LP_Write,
+    .erase                = R_FLASH_LP_Erase,
+    .blankCheck           = R_FLASH_LP_BlankCheck,
+    .statusGet            = R_FLASH_LP_StatusGet,
+    .infoGet              = R_FLASH_LP_InfoGet,
+    .accessWindowSet      = R_FLASH_LP_AccessWindowSet,
+    .accessWindowClear    = R_FLASH_LP_AccessWindowClear,
+    .idCodeSet            = R_FLASH_LP_IdCodeSet,
+    .reset                = R_FLASH_LP_Reset,
+    .startupAreaSelect    = R_FLASH_LP_StartUpAreaSelect,
+    .updateFlashClockFreq = R_FLASH_LP_UpdateFlashClockFreq,
+    .versionGet           = R_FLASH_LP_VersionGet
+};
+
+/** Version data structure used by error logger macro. */
+static const fsp_version_t g_flash_lp_version =
+{
+    .api_version_minor  = FLASH_API_VERSION_MINOR,
+    .api_version_major  = FLASH_API_VERSION_MAJOR,
+    .code_version_major = FLASH_LP_CODE_VERSION_MAJOR,
+    .code_version_minor = FLASH_LP_CODE_VERSION_MINOR
+};
+
+/** Name of module used by error logger macro */
+#if BSP_CFG_ERROR_LOG != 0
+static const char g_module_name[] = "r_flash_lp";
+#endif
+
+const flash_block_info_t g_code_flash_macro_info =
+{
+    .block_section_st_addr  = 0,
+    .block_section_end_addr = BSP_ROM_SIZE_BYTES - 1,
+    .block_size             = BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE,
+    .block_size_write       = BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE
+};
+
+static flash_regions_t g_flash_code_region =
+{
+    .num_regions   = 1,
+    .p_block_array = &g_code_flash_macro_info
+};
+
+const flash_block_info_t g_data_flash_macro_info =
+{
+    .block_section_st_addr  = FLASH_LP_DF_START_ADDRESS,
+    .block_section_end_addr = FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1,
+    .block_size             = BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE,
+    .block_size_write       = BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE
+};
+
+static flash_regions_t g_flash_data_region =
+{
+    .num_regions   = 1,
+    .p_block_array = &g_data_flash_macro_info
+};
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @addtogroup FLASH_LP
+ * @{
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initialize the Low Power flash peripheral. Implements @ref flash_api_t::open.
+ *
+ * The Open function initializes the Flash.
+ *
+ * This function must be called once prior to calling any other FLASH API functions. If a user supplied callback
+ * function is supplied, then the Flash Ready interrupt will be configured to call the users callback routine with an
+ * Event type describing the source of the interrupt for Data Flash operations.
+ *
+ * Example:
+ * @snippet r_flash_lp_example.c R_FLASH_LP_Open
+ *
+ * @note       Providing a callback function in the supplied p_cfg->callback field automatically configures the Flash
+ *             for Data Flash to operate in non-blocking background operation (BGO) mode.
+ *
+ * @retval     FSP_SUCCESS               Initialization was successful and timer has started.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl, p_cfg or p_callback if BGO is enabled.
+ * @retval     FSP_ERR_IRQ_BSP_DISABLED  Caller is requesting BGO but the Flash interrupts are not enabled.
+ * @retval     FSP_ERR_FCLK              FCLK must be a minimum of 4 MHz for Flash operations.
+ * @retval     FSP_ERR_ALREADY_OPEN      Flash Open() has already been called.
+ * @retval     FSP_ERR_TIMEOUT           Failed to exit P/E mode after configuring flash.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* If null pointers return error. */
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(p_cfg);
+    FSP_ASSERT(p_ctrl);
+
+    /* If open return error. */
+    FSP_ERROR_RETURN((FLASH_HP_OPEN != p_ctrl->opened), FSP_ERR_ALREADY_OPEN);
+
+    /* Background operations for data flash are enabled but the flash interrupt is disabled. */
+    if (p_cfg->data_flash_bgo)
+    {
+        FSP_ERROR_RETURN(p_cfg->irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED);
+        FSP_ASSERT(p_cfg->p_callback);
+    }
+#endif
+
+    p_ctrl->p_cfg = p_cfg;
+
+    if (p_cfg->data_flash_bgo)
+    {
+        R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl);
+    }
+
+    p_ctrl->current_operation = FLASH_OPERATION_NON_BGO;
+
+    /* Check FCLK, calculate timeout values. */
+    err = r_flash_lp_setup(p_ctrl);
+    FSP_ERROR_RETURN((err == FSP_SUCCESS), err);
+
+    /* Set the FlashIF peripheral clock frequency. */
+    err = r_flash_lp_set_fisr(p_ctrl);
+    FSP_ERROR_RETURN((err == FSP_SUCCESS), err);
+
+    p_ctrl->opened = FLASH_HP_OPEN;
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Write to the specified Code or Data Flash memory area. Implements @ref flash_api_t::write.
+ *
+ * Example:
+ * @snippet r_flash_lp_example.c R_FLASH_LP_Write
+ *
+ * @retval     FSP_SUCCESS               Operation successful. If BGO is enabled this means the operation was started
+ *                                       successfully.
+ * @retval     FSP_ERR_IN_USE            The Flash peripheral is busy with a prior on-going transaction.
+ * @retval     FSP_ERR_NOT_OPEN          The Flash API is not Open.
+ * @retval     FSP_ERR_WRITE_FAILED      Status is indicating a Programming error for the requested operation. This may
+ *                                       be returned if the requested Flash area is not blank.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for FCU operation to complete.
+ * @retval     FSP_ERR_INVALID_SIZE      Number of bytes provided was not a multiple of the programming size or exceeded
+ *                                       the maximum range.
+ * @retval     FSP_ERR_INVALID_ADDRESS   Invalid address was input or address not on programming boundary.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_Write (flash_ctrl_t * const p_api_ctrl,
+                            uint32_t const       src_address,
+                            uint32_t             flash_address,
+                            uint32_t const       num_bytes)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+    /* Check parameters. If failure return error */
+    err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true);
+    FSP_ERROR_RETURN((err == FSP_SUCCESS), err);
+#endif
+
+    p_ctrl->current_operation = FLASH_OPERATION_NON_BGO;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+    /* Configure the current parameters for code flash or data flash depending on address. */
+    if (flash_address < BSP_ROM_SIZE_BYTES)
+    {
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+        /* Verify the source address is not in code flash. It will not be available in P/E mode. */
+        FSP_ASSERT(src_address > BSP_ROM_SIZE_BYTES);
+ #endif
+
+        /* Write the data */
+        err =
+            r_flash_lp_cf_write(p_ctrl, src_address, flash_address, num_bytes);
+    }
+    else
+#endif
+    {
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+        /* Write the data */
+        err =
+            r_flash_lp_df_write(p_ctrl, src_address, flash_address, num_bytes);
+#endif
+    }
+
+    /* Return status. */
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Erase the specified Code or Data Flash blocks. Implements @ref flash_api_t::erase.
+ *
+ * Example:
+ * @snippet r_flash_lp_example.c R_FLASH_LP_Erase
+ *
+ * @retval     FSP_SUCCESS               Successful open.
+ * @retval     FSP_ERR_INVALID_BLOCKS    Invalid number of blocks specified
+ * @retval     FSP_ERR_INVALID_ADDRESS   Invalid address specified
+ * @retval     FSP_ERR_IN_USE            Other flash operation in progress, or API not initialized
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN          The Flash API is not Open.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for FCU to be ready.
+ * @retval     FSP_ERR_ERASE_FAILED      Status is indicating a Erase error.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* If invalid number of blocks return error. */
+    FSP_ERROR_RETURN(num_blocks != 0U, FSP_ERR_INVALID_BLOCKS);
+#endif
+
+    p_ctrl->current_operation = FLASH_OPERATION_NON_BGO;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+    /* Configure the current parameters based on if the operation is for code flash or data flash. */
+    if (address < BSP_ROM_SIZE_BYTES)
+    {
+        uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE - 1);
+
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+        uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE;
+
+        FSP_ERROR_RETURN(start_address + num_bytes <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_BLOCKS);
+ #endif
+
+        err = r_flash_lp_cf_erase(p_ctrl, start_address, num_blocks, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE);
+    }
+    else
+#endif
+    {
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+        uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE - 1);
+
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+        uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE;
+
+        FSP_ERROR_RETURN((start_address >= (FLASH_LP_DF_START_ADDRESS)) &&
+                         (start_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)),
+                         FSP_ERR_INVALID_ADDRESS);
+
+        FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES),
+                         FSP_ERR_INVALID_BLOCKS);
+ #endif
+
+        /* If this is a request to erase Data Flash configure BGO mode if it is enabled. */
+        if (p_ctrl->p_cfg->data_flash_bgo)
+        {
+            p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_ERASE;
+        }
+
+        /* Initiate the flash erase. */
+        err = r_flash_lp_df_erase(p_ctrl, start_address, num_blocks, BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE);
+#else
+
+        return FSP_ERR_INVALID_ADDRESS;
+#endif
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Perform a blank check on the specified address area. Implements @ref flash_api_t::blankCheck.
+ *
+ * Example:
+ * @snippet r_flash_lp_example.c R_FLASH_LP_BlankCheck
+ *
+ * @retval     FSP_SUCCESS                 Blankcheck operation completed with result in p_blank_check_result, or
+ *                                         blankcheck started and in-progess (BGO mode).
+ * @retval     FSP_ERR_INVALID_ADDRESS     Invalid data flash address was input
+ * @retval     FSP_ERR_INVALID_SIZE        'num_bytes' was either too large or not aligned for the CF/DF boundary size.
+ * @retval     FSP_ERR_IN_USE              Flash is busy with an on-going operation.
+ * @retval     FSP_ERR_ASSERTION           NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN            Flash API has not yet been opened.
+ * @retval     FSP_ERR_TIMEOUT             Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_BLANK_CHECK_FAILED  An error occurred during blank checking.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_BlankCheck (flash_ctrl_t * const p_api_ctrl,
+                                 uint32_t const       address,
+                                 uint32_t             num_bytes,
+                                 flash_result_t     * p_blank_check_result)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+    /* Check parameters. If failure return error */
+    err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, address, num_bytes, false);
+    FSP_ERROR_RETURN((err == FSP_SUCCESS), err);
+#endif
+
+    p_ctrl->current_operation = FLASH_OPERATION_NON_BGO;
+
+    /* Initiate the Blank Check operation */
+    /* Configure the current operation and wait count based on the number of bytes and if it's a data flash or code flash operation. */
+    /* Is this a request to Blank check Code Flash? */
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+    if (address < BSP_ROM_SIZE_BYTES)
+    {
+        /* This is a request to Blank check Code Flash */
+        err = r_flash_lp_cf_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result);
+    }
+    else
+#endif
+    {
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+        /* This is a request to Blank check Data Flash */
+        /* No errors in parameters. Enter Data Flash PE mode*/
+        if (p_ctrl->p_cfg->data_flash_bgo)
+        {
+            p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_BLANKCHECK;
+        }
+        err = r_flash_lp_df_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result);
+#endif
+    }
+
+    /* If failure reset the flash. */
+    /* FSP_ERR_IN_USE would indicate that a BGO operation is underway, so don't reset in that case */
+    if ((FSP_SUCCESS != err) && (FSP_ERR_IN_USE != err))
+    {
+        /* This will clear error flags and exit the P/E mode*/
+        r_flash_lp_reset(p_ctrl);
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Query the FLASH for its status. Implements @ref flash_api_t::statusGet.
+ *
+ * Example:
+ * @snippet r_flash_lp_example.c R_FLASH_LP_StatusGet
+ *
+ * @retval     FSP_SUCCESS        Flash is ready and available to accept commands.
+ * @retval     FSP_ERR_ASSERTION  NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN   Flash API has not yet been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_StatusGet (flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    /* If null control block return error. */
+    FSP_ASSERT(p_ctrl);
+
+    /* If null status pointer return error. */
+    FSP_ASSERT(p_status);
+
+    /* If control block is not open return error. */
+    FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_api_ctrl);
+#endif
+
+    /* Return flash status */
+    if ((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U)
+    {
+        *p_status = FLASH_STATUS_IDLE;
+    }
+    else
+    {
+        *p_status = FLASH_STATUS_BUSY;
+    }
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Configure an access window for the Code Flash memory. Implements @ref flash_api_t::accessWindowSet.
+ *
+ * An access window defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on
+ * block boundaries. The block containing start_addr is the first block. The block containing end_addr is the last
+ * block. The access window then becomes first block (inclusive) --> last block (exclusive). Anything outside this range
+ * of Code Flash is then write protected. As an example, if you wanted to place an accesswindow on Code Flash Blocks 0
+ * and 1, such that only those two blocks were writable, you would need to specify (address in block 0, address in block
+ * 2) as the respective start and end address.
+ * @note       If the start address and end address are set to the same value, then the access window is effectively
+ *             removed. This accomplishes the same functionality as R_FLASH_LP_AccessWindowClear().
+ *
+ * The invalid address and programming boundaries supported and enforced by this function are dependent on the MCU in
+ * use as well as the part package size. Please see the User manual and/or requirements document for additional
+ * information.
+ *
+ * @param      p_api_ctrl                The p api control
+ * @param[in]  start_addr                The start address
+ * @param[in]  end_addr                  The end address
+ *
+ * @retval     FSP_SUCCESS               Access window successfully configured.
+ * @retval     FSP_ERR_INVALID_ADDRESS   Invalid settings for start_addr and/or end_addr.
+ * @retval     FSP_ERR_IN_USE            FLASH peripheral is busy with a prior operation.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl.
+ * @retval     FSP_ERR_UNSUPPORTED       Code Flash Programming is not enabled.
+ * @retval     FSP_ERR_NOT_OPEN          Flash API has not yet been opened.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_WRITE_FAILED      Status is indicating a Programming error for the requested operation.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_AccessWindowSet (flash_ctrl_t * const p_api_ctrl,
+                                      uint32_t const       start_addr,
+                                      uint32_t const       end_addr)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Note that the end_addr indicates the address up to, but not including the block that contains that address. */
+    /* Therefore to allow the very last Block to be included in the access window we must allow for FLASH_CF_BLOCK_END+1 */
+    /* If the start or end addresses are invalid return error. */
+    FSP_ERROR_RETURN((start_addr <= end_addr) && (end_addr <= BSP_ROM_SIZE_BYTES), FSP_ERR_INVALID_ADDRESS);
+ #endif
+
+    /* Set the access window. */
+    err = r_flash_lp_access_window_set(p_ctrl, start_addr, end_addr);
+#else
+
+    /* Remove warnings generated when Code Flash code is DISABLED. */
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(start_addr);
+    FSP_PARAMETER_NOT_USED(end_addr);
+
+    /* If not code flash return error. */
+    err = FSP_ERR_UNSUPPORTED;         // For consistency with _LP API we return error if Code Flash not enabled
+#endif
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Remove any access window that is configured in the Code Flash. Implements @ref flash_api_t::accessWindowClear. On
+ * successful return from this call all Code Flash is writable.
+ *
+ * @retval     FSP_SUCCESS               Access window successfully removed.
+ * @retval     FSP_ERR_IN_USE            FLASH peripheral is busy with a prior operation.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl.
+ * @retval     FSP_ERR_UNSUPPORTED       Code Flash Programming is not enabled.
+ * @retval     FSP_ERR_NOT_OPEN          Flash API has not yet been opened.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_WRITE_FAILED      Status is indicating a Programming error for the requested operation.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_AccessWindowClear (flash_ctrl_t * const p_api_ctrl)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    /* Eliminate warning if parameter checking is disabled. */
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+ #endif
+
+    /* If successful clear the access window. When the start address and end address are set to the same value,
+     * then the access window is effectively removed.  */
+    err = r_flash_lp_access_window_set(p_ctrl, 0, 0);
+#else
+
+    /* Return error if Code Flash not enabled. */
+    err = FSP_ERR_UNSUPPORTED;
+#endif
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Write the ID code provided to the id code registers. Implements @ref flash_api_t::idCodeSet.
+ *
+ * @retval     FSP_SUCCESS               ID code successfully configured.
+ * @retval     FSP_ERR_IN_USE            FLASH peripheral is busy with a prior operation.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl.
+ * @retval     FSP_ERR_UNSUPPORTED       Code Flash Programming is not enabled.
+ * @retval     FSP_ERR_NOT_OPEN          Flash API has not yet been opened.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for completion of extra command.
+ * @retval     FSP_ERR_WRITE_FAILED      Status is indicating a Programming error for the requested operation.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_IdCodeSet (flash_ctrl_t * const  p_api_ctrl,
+                                uint8_t const * const p_id_code,
+                                flash_id_code_mode_t  mode)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Verify the id bytes are not in code flash. They will not be available in P/E mode. */
+    FSP_ASSERT(((uint32_t) p_id_code) > BSP_ROM_SIZE_BYTES);
+ #endif
+
+    /* Set the id code. */
+    err = r_flash_lp_set_id_code(p_ctrl, p_id_code, mode);
+#else
+
+    /* Eliminate warning if code flash programming is disabled. */
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(p_id_code);
+    FSP_PARAMETER_NOT_USED(mode);
+
+    err = FSP_ERR_UNSUPPORTED;         // For consistency with _LP API we return error if Code Flash not enabled
+#endif
+
+    /* Return status. */
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Reset the FLASH peripheral. Implements @ref flash_api_t::reset.
+ *
+ * No attempt is made to check if the flash is busy before executing the reset since the assumption is that a reset
+ * will terminate any existing operation.
+ * @retval     FSP_SUCCESS        Flash circuit successfully reset.
+ * @retval     FSP_ERR_ASSERTION  NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN   Flash API has not yet been opened.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_Reset (flash_ctrl_t * const p_api_ctrl)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* If null control block return error. */
+    FSP_ASSERT(p_ctrl);
+
+    /* If control block is not open return error. */
+    FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Reset the flash. */
+    r_flash_lp_reset(p_ctrl);
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Select which block is used as the startup area block. Implements @ref flash_api_t::startupAreaSelect.
+ *
+ * Selects which block - Default (Block 0) or Alternate (Block 1) is used as the startup area block. The provided
+ * parameters determine which block will become the active startup block and whether that action will be immediate (but
+ * temporary), or permanent subsequent to the next reset. Doing a temporary switch might appear to have limited
+ * usefulness. If there is an access window in place such that Block 0 is write protected, then one could do a temporary
+ * switch, update the block and switch them back without having to touch the access window.
+ *
+ * @retval     FSP_SUCCESS               Start-up area successfully toggled.
+ * @retval     FSP_ERR_IN_USE            Flash is busy with an on-going operation.
+ * @retval     FSP_ERR_ASSERTION         NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN          Flash API has not yet been opened.
+ * @retval     FSP_ERR_WRITE_FAILED      Status is indicating a Programming error for the requested operation.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_UNSUPPORTED       Code Flash Programming is not enabled. Cannot set FLASH_STARTUP_AREA_BTFLG
+ *                                       when the temporary flag is false.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_StartUpAreaSelect (flash_ctrl_t * const      p_api_ctrl,
+                                        flash_startup_area_swap_t swap_type,
+                                        bool                      is_temporary)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+ #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+ #endif
+
+    /* If the swap type is BTFLG and the operation is temporary there's nothing to do. */
+    FSP_ASSERT(!((swap_type == FLASH_STARTUP_AREA_BTFLG) && (is_temporary == false)));
+
+    err = r_flash_lp_set_startup_area_boot(p_ctrl, swap_type, is_temporary);
+#else
+
+    /* Eliminate warning if code flash programming is disabled. */
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(swap_type);
+    FSP_PARAMETER_NOT_USED(is_temporary);
+
+    err = FSP_ERR_UNSUPPORTED;         // For consistency with _LP API we return error if Code Flash not enabled
+#endif
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Indicate to the already open Flash API that the FCLK has changed. Implements flash_api_t::updateFlashClockFreq.
+ *
+ * This could be the case if the application has changed the system clock, and therefore the FCLK. Failure to call this
+ * function subsequent to changing the FCLK could result in damage to the flash macro.
+ *
+ * @retval     FSP_SUCCESS        Start-up area successfully toggled.
+ * @retval     FSP_ERR_IN_USE     Flash is busy with an on-going operation.
+ * @retval     FSP_ERR_FCLK       Invalid flash clock source frequency.
+ * @retval     FSP_ERR_ASSERTION  NULL provided for p_ctrl
+ * @retval     FSP_ERR_NOT_OPEN   Flash API has not yet been opened.
+ * @retval     FSP_ERR_TIMEOUT    Timed out waiting for the FCU to become ready.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_UpdateFlashClockFreq (flash_ctrl_t * const p_api_ctrl)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    fsp_err_t err = FSP_SUCCESS;
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify the control block is not null and is opened. */
+    err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+#endif
+
+    /* Check FCLK, calculate timeout values. */
+    err = r_flash_lp_setup(p_ctrl);
+    FSP_ERROR_RETURN((err == FSP_SUCCESS), err);
+
+    /* Set the FlashIF peripheral clock frequency. */
+    err = r_flash_lp_set_fisr(p_ctrl);
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Returns the information about the flash regions. Implements @ref flash_api_t::infoGet.
+ *
+ * @retval     FSP_SUCCESS        Successful retrieved the request information.
+ * @retval     FSP_ERR_ASSERTION  NULL provided for p_ctrl or p_info.
+ * @retval     FSP_ERR_NOT_OPEN   The flash is not open.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_InfoGet (flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info)
+{
+#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+    /* If null control block return error. */
+    FSP_ASSERT(p_ctrl);
+
+    /* If control block is not open return error. */
+    FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN);
+
+    // todo add back the NULL !=
+    FSP_ASSERT(p_info);
+#else
+    FSP_PARAMETER_NOT_USED(p_api_ctrl);
+#endif
+
+    /* Copy the region data to the info structure. */
+    p_info->code_flash = g_flash_code_region;
+    p_info->data_flash = g_flash_data_region;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Release any resources that were allocated by the Flash API. Implements @ref flash_api_t::close.
+ *
+ * @retval     FSP_SUCCESS        Successful close.
+ * @retval     FSP_ERR_ASSERTION  NULL provided for p_ctrl or p_cfg.
+ * @retval     FSP_ERR_NOT_OPEN   Flash API has not yet been opened.
+ * @retval     FSP_ERR_IN_USE     The flash is currently in P/E mode.
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_Close (flash_ctrl_t * const p_api_ctrl)
+{
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl;
+
+#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the control block is not null and is opened. */
+    fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+#endif
+
+    /* Mark the control block as closed. */
+    p_ctrl->opened = 0;
+
+    /* Disable the flash interrupt. */
+    if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->irq)
+    {
+        /* Disable interrupt in ICU*/
+        R_BSP_IrqDisable(p_ctrl->p_cfg->irq);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get Flash LP driver version.
+ *
+ * @retval     FSP_SUCCESS        Operation performed successfully
+ * @retval     FSP_ERR_ASSERTION  Null Pointer
+ **********************************************************************************************************************/
+fsp_err_t R_FLASH_LP_VersionGet (fsp_version_t * const p_version)
+{
+#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE
+
+    /* If null pointer return error. */
+    FSP_ASSERT(p_version);
+#endif
+
+    /* Return the version id of the flash lp module. */
+    p_version->version_id = g_flash_lp_version.version_id;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup FLASH_LP)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * This function verifies that FCLK falls within the allowable range and calculates the timeout values based on the
+ * current FCLK frequency.
+ * @param      p_ctrl        The p control
+ * @retval     FSP_SUCCESS   Success
+ * @retval     FSP_ERR_FCLK  FCLK must be >= 4 MHz.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_setup (flash_lp_instance_ctrl_t * p_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* Get the frequency of the clock driving the flash. */
+    p_ctrl->flash_clock_frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC);
+
+    /* FCLK must be a minimum of 4 MHz for Flash operations. If not return error. */
+    FSP_ERROR_RETURN(p_ctrl->flash_clock_frequency >= FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ, FSP_ERR_FCLK);
+
+    /* Get the frequency of the system clock. */
+    p_ctrl->system_clock_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK);
+
+    /* Initialize the flash timeout calculations and transfer global parameters to code and data flash layers. */
+    r_flash_lp_init(p_ctrl);
+
+    /* Enable the DataFlash if not already enabled */
+    if (1U != R_FACI_LP->DFLCTL)
+    {
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Wait for (tDSTOP) before reading from data flash. */
+        r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency);
+    }
+
+    return err;
+}
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function performs the parameter checking required by Write, Read and BlankCheck functions.
+ *
+ * @param      p_ctrl                   Pointer to the control block
+ * @param[in]  flash_address            The flash address
+ * @param[in]  num_bytes                The number bytes
+ * @param[in]  check_write              Check paramters for writing.
+ *
+ * @retval     FSP_SUCCESS              Parameter checking completed without error.
+ * @retval     FSP_ERR_NOT_OPEN         The Flash API is not Open.
+ * @retval     FSP_ERR_ASSERTION        Null pointer
+ * @retval     FSP_ERR_INVALID_SIZE     Number of bytes provided was not a multiple of the programming size or exceeded
+ *                                      the maximum range.
+ * @retval     FSP_ERR_INVALID_ADDRESS  Invalid address was input or address not on programming boundary.
+ * @retval     FSP_ERR_IN_USE           The flash is currently in P/E mode.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_write_read_bc_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl,
+                                                              uint32_t                         flash_address,
+                                                              uint32_t const                   num_bytes,
+                                                              bool                             check_write)
+{
+    /* Verify the control block is not null and is opened. */
+    fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* If invalid address or number of bytes return error. */
+ #if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 0)
+    FSP_PARAMETER_NOT_USED(check_write);
+ #else
+    if (flash_address < BSP_ROM_SIZE_BYTES)
+    {
+        /* If the start address is in code flash verify the end address is in code flash. */
+        FSP_ERROR_RETURN(flash_address + num_bytes <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_SIZE);
+
+        if (check_write)
+        {
+            FSP_ERROR_RETURN(!(flash_address & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_ADDRESS);
+            FSP_ERROR_RETURN(!(num_bytes & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_SIZE);
+        }
+    }
+    else
+ #endif
+    {
+ #if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+        FSP_ERROR_RETURN((flash_address >= (FLASH_LP_DF_START_ADDRESS)) &&
+                         (flash_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)),
+                         FSP_ERR_INVALID_ADDRESS);
+        FSP_ERROR_RETURN((flash_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)),
+                         FSP_ERR_INVALID_SIZE);
+ #else
+
+        return FSP_ERR_INVALID_ADDRESS;
+ #endif
+    }
+
+    /* If invalid number of bytes return error. */
+    FSP_ERROR_RETURN((0 != num_bytes), FSP_ERR_INVALID_SIZE);
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function performs the parameter checking required by the R_FLASH_LP_Write() function.
+ * @param      p_ctrl             Pointer to the control block
+ *
+ * @retval     FSP_SUCCESS        Parameter checking completed without error.
+ * @retval     FSP_ERR_ASSERTION  Null pointer
+ * @retval     FSP_ERR_NOT_OPEN   The flash module is not open.
+ * @retval     FSP_ERR_IN_USE     The flash is currently in P/E mode.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_common_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    /* If null control block return error. */
+    FSP_ASSERT(p_ctrl);
+
+    /* If control block is not open return error. */
+    FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN);
+
+    /* If the API is not ready return error. */
+    FSP_ERROR_RETURN((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U, FSP_ERR_IN_USE);
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * This function will calculate the timeout values for various operations.
+ * @param[in]  p_ctrl          Pointer to the Flash control block
+ **********************************************************************************************************************/
+void r_flash_lp_init (flash_lp_instance_ctrl_t * p_ctrl)
+{
+    /* Round up the frequency to a whole number. */
+    p_ctrl->flash_clock_frequency = (p_ctrl->flash_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) /
+                                    FLASH_LP_HZ_IN_MHZ;
+
+    /* If the frequency is over 32MHz round up to an even number. */
+#if BSP_FEATURE_FLASH_LP_VERSION == 4
+    if ((p_ctrl->flash_clock_frequency > FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) &&
+        (1 == p_ctrl->flash_clock_frequency % 2))
+    {
+        p_ctrl->flash_clock_frequency++;
+    }
+#endif
+
+    p_ctrl->system_clock_frequency = (p_ctrl->system_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) /
+                                     FLASH_LP_HZ_IN_MHZ;
+
+    /*  According to HW Manual the Max Programming Time for 4 bytes(RA2L1) or 8 bytes(RA2A1/RA4M1)(ROM)
+     *  is 1411us.  This is with a FCLK of 1MHz. The calculation below
+     *  calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_write_cf =
+        (uint32_t) (FLASH_LP_MAX_WRITE_CF_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /*  According to HW Manual the Max Programming Time for 1 byte
+     *  (Data Flash) is 886us.  This is with a FCLK of 4MHz. The calculation
+     *  below calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_write_df =
+        (uint32_t) (FLASH_LP_MAX_WRITE_DF_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /*  According to HW Manual the Max Blank Check time for 2 bytes (S12*) or 8 bytes (RA2A1/RA4M1)
+     *  (Code Flash) is 87.7 usec.  This is with a FCLK of 1MHz. The calculation
+     *  below calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_blank_check =
+        (uint32_t) (FLASH_LP_MAX_BLANK_CHECK_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /*  According to HW Manual the Max Erasure Time for a 1KB block (S12*) or 2KB bytes (RA2A1/RA4M1) is
+     *  around 289ms.  This is with a FCLK of 1MHz. The calculation below
+     *  calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_erase_cf_block =
+        (uint32_t) (FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /*  According to HW Manual the Max Erasure Time for a 1KB Data Flash block is
+     *  around 299ms.  This is with a FCLK of 4MHz. The calculation below
+     *  calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_erase_df_block =
+        (uint32_t) (FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /*  According to HW Manual the Max Erasure Time for writing to the extra area is
+     *  around 585ms. This is with a FCLK of 1MHz. The calculation below
+     *  calculates the number of ICLK ticks needed for the timeout delay.
+     */
+    p_ctrl->timeout_write_extra_area =
+        (uint32_t) (FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US * p_ctrl->system_clock_frequency) /
+        FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP;
+
+    /* FLWAITR should be set to 0 when the FCLK/ICLK is within the acceptable range. */
+    R_FACI_LP->FLWAITR = 0U;
+}
+
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function erases a specified number of Code or Data Flash blocks
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  block_address         The starting address of the first block to erase.
+ * @param[in]  num_blocks            The number of blocks to erase.
+ * @param[in]  block_size            The Flash block size.
+ *
+ * @retval     FSP_SUCCESS           Successfully erased (non-BGO) mode or operation successfully started (BGO).
+ * @retval     FSP_ERR_ERASE_FAILED  Erase failed. Flash could be locked or address could be under access window
+ *                                   control.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the FCU to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_df_erase (flash_lp_instance_ctrl_t * const p_ctrl,
+                                      uint32_t                         block_address,
+                                      uint32_t                         num_blocks,
+                                      uint32_t                         block_size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* Enter data flash P/E mode. */
+    r_flash_lp_df_enter_pe_mode(p_ctrl);
+
+    /* Select user area. */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    /* Save the current operation parameters. */
+    p_ctrl->source_start_address = block_address + FLASH_LP_DATAFLASH_ADDR_OFFSET;
+    p_ctrl->operations_remaining = num_blocks;
+
+    /* Start the code flash erase operation. */
+    r_flash_lp_process_command(p_ctrl->source_start_address, num_blocks * block_size, FLASH_LP_FCR_ERASE);
+
+    /* If configured for Blocking mode then don't return until the entire operation is complete */
+    if (!p_ctrl->p_cfg->data_flash_bgo)
+    {
+        /* Waits for the erase commands to be completed and verifies the result of the command execution. */
+        err = r_flash_lp_wait_for_ready(p_ctrl,
+                                        p_ctrl->timeout_erase_df_block * num_blocks,
+                                        FLASH_LP_FSTATR2_ERASE_ERROR_BITS,
+                                        FSP_ERR_ERASE_FAILED);
+        FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+        /* Disable P/E mode for data flash. */
+        r_flash_lp_pe_mode_exit(p_ctrl);
+    }
+
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function erases a specified number of Code Flash blocks
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  block_address         The starting address of the first block to erase.
+ * @param[in]  num_blocks            The number of blocks to erase.
+ * @param[in]  block_size            The Flash block size.
+ *
+ * @retval     FSP_SUCCESS           Successfully erased (non-BGO) mode or operation successfully started (BGO).
+ * @retval     FSP_ERR_ERASE_FAILED  Status is indicating a Erase error.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the FCU to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_cf_erase (flash_lp_instance_ctrl_t * const p_ctrl,
+                                      uint32_t                         block_address,
+                                      uint32_t                         num_blocks,
+                                      uint32_t                         block_size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    /* Select User Area */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    /* Start the code flash erase operation. */
+    r_flash_lp_process_command(block_address, num_blocks * block_size, FLASH_LP_FCR_ERASE);
+
+    /* Wait for the operation to complete. */
+    err = r_flash_lp_wait_for_ready(p_ctrl,
+                                    p_ctrl->timeout_erase_cf_block * num_blocks,
+                                    FLASH_LP_FSTATR2_ERASE_ERROR_BITS,
+                                    FSP_ERR_ERASE_FAILED);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    return r_flash_lp_pe_mode_exit(p_ctrl);
+}
+
+#endif
+
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function writes a specified number of bytes to Code or Data Flash.
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  src_start_address     The starting address of the first byte (from source) to write.
+ * @param[in]  dest_start_address    The starting address of the Flash (to destination) to write.
+ * @param[in]  num_bytes             The number of bytes to write.
+ *
+ * @retval     FSP_SUCCESS           Data successfully written (non-BGO) mode or operation successfully started (BGO).
+ * @retval     FSP_ERR_IN_USE        Command still executing.
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation. This may be
+ *                                   returned if the requested Flash area is not blank.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the Flash sequencer to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_df_write (flash_lp_instance_ctrl_t * const p_ctrl,
+                                      uint32_t const                   src_start_address,
+                                      uint32_t                         dest_start_address,
+                                      uint32_t                         num_bytes)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    p_ctrl->dest_end_address     = dest_start_address;
+    p_ctrl->source_start_address = src_start_address;
+    p_ctrl->operations_remaining = num_bytes;
+
+    if (p_ctrl->p_cfg->data_flash_bgo)
+    {
+        p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_WRITE;
+    }
+
+    /* Enter data flash P/E mode. */
+    r_flash_lp_df_enter_pe_mode(p_ctrl);
+
+    /* Select user area. */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    /* Initiate the data flash write operation. */
+    r_flash_lp_df_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address);
+
+    /* If configured for Blocking mode then don't return until the entire operation is complete */
+    if (!p_ctrl->p_cfg->data_flash_bgo)
+    {
+        do
+        {
+            /* Wait for the write commands to be completed and verifies the result of the command execution. */
+            err = r_flash_lp_df_write_monitor(p_ctrl);
+        } while (FSP_ERR_IN_USE == err);
+
+        /* Disable P/E mode for data flash. */
+        if (FSP_SUCCESS == err)
+        {
+            r_flash_lp_pe_mode_exit(p_ctrl);
+        }
+    }
+
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function writes a specified number of bytes to Code Flash.
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  src_start_address     The starting address of the first byte (from source) to write.
+ * @param[in]  dest_start_address    The starting address of the Flash (to destination) to write.
+ * @param[in]  num_bytes             The number of bytes to write.
+ *
+ * @retval     FSP_SUCCESS           Data successfully written (non-BGO) mode or operation successfully started (BGO).
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation. This may be
+ *                                   returned if the requested Flash area is not blank.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the Flash sequencer to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_cf_write (flash_lp_instance_ctrl_t * const p_ctrl,
+                                      uint32_t const                   src_start_address,
+                                      uint32_t                         dest_start_address,
+                                      uint32_t                         num_bytes)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    p_ctrl->dest_end_address     = dest_start_address;
+    p_ctrl->source_start_address = src_start_address;
+
+    /* Calculate the number of writes needed. */
+
+    /* This is done with right shift instead of division to avoid using the division library, which would be in flash
+     * and cause a jump from RAM to flash. */
+    p_ctrl->operations_remaining = num_bytes / BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE;
+
+    /* Select User Area */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    while (p_ctrl->operations_remaining && (FSP_SUCCESS == err))
+    {
+        /* Initiate the code flash write operation. */
+        r_flash_lp_cf_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address);
+
+        /* If there is more data to write then write the next data. */
+        p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE;
+        p_ctrl->dest_end_address     += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE;
+        p_ctrl->operations_remaining--;
+        err = r_flash_lp_wait_for_ready(p_ctrl,
+                                        p_ctrl->timeout_write_cf,
+                                        FLASH_LP_FSTATR2_WRITE_ERROR_BITS,
+                                        FSP_ERR_WRITE_FAILED);
+    }
+
+    /* If successful exit P/E mode. */
+    if (FSP_SUCCESS == err)
+    {
+        r_flash_lp_pe_mode_exit(p_ctrl);
+    }
+
+    return err;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Execute a single Write operation on the Low Power Data Flash data.
+ * MF3: See Figure 10.15 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.12 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  psrc_addr       Source address for data to be written.
+ * @param[in]  dest_addr       End address (read form) for writing.
+ **********************************************************************************************************************/
+static void r_flash_lp_df_write_operation (const uint32_t psrc_addr, uint32_t dest_addr)
+{
+    uint32_t  dest_addr_idx;
+    uint8_t * data8_ptr;
+    data8_ptr = (uint8_t *) psrc_addr;
+
+    dest_addr_idx = dest_addr + FLASH_LP_DATAFLASH_ADDR_OFFSET; /* Conversion to the P/E address from the read address */
+
+    /* Write flash address setting */
+    R_FACI_LP->FSARH = (uint16_t) ((dest_addr_idx >> 16));
+    R_FACI_LP->FSARL = (uint16_t) (dest_addr_idx);
+
+    /* Write data address setting */
+    R_FACI_LP->FWBL0 = *data8_ptr;     // For data flash there are only 8 bits used of the 16 in the reg
+
+    /* Execute Write command */
+    R_FACI_LP->FCR = FLASH_LP_FCR_WRITE;
+}
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Execute a single Write operation on the Low Power Code Flash data.
+ * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.11 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  psrc_addr         Source address for data to be written.
+ * @param[in]  dest_addr         End address (read form) for writing.
+ **********************************************************************************************************************/
+static void r_flash_lp_cf_write_operation (const uint32_t psrc_addr, const uint32_t dest_addr)
+{
+    uint16_t data[BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE / 2];
+
+    /* Write flash address setting */
+    R_FACI_LP->FSARH = (uint16_t) ((dest_addr >> 16));
+    R_FACI_LP->FSARL = (uint16_t) (dest_addr);
+
+    /* Copy the data and write them to the flash write buffers. CM23 parts to not support unaligned access so this
+     * must be done using byte access. */
+    r_flash_lp_memcpy((uint8_t *) data, (uint8_t *) psrc_addr, BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE);
+    R_FACI_LP->FWBL0 = data[0];
+    R_FACI_LP->FWBH0 = data[1];
+ #if BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE == 8
+    R_FACI_LP->FWBL1 = data[2];
+    R_FACI_LP->FWBH1 = data[3];
+ #endif
+
+    /* Execute Write command */
+    R_FACI_LP->FCR = FLASH_LP_FCR_WRITE;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Waits for the write command to be completed and verifies the result of the command execution.
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ *
+ * @retval     FSP_SUCCESS           Write command successfully completed.
+ * @retval     FSP_ERR_IN_USE        Write command still in progress.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for write command completion.
+ * @retval     FSP_ERR_WRITE_FAILED  Write failed. Flash could be locked, area has not been erased, or address could be
+ *                                   under access window control.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_df_write_monitor (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    fsp_err_t status;
+
+    /* Wait for the data to be written. */
+    status =
+        r_flash_lp_wait_for_ready(p_ctrl,
+                                  p_ctrl->timeout_write_df,
+                                  FLASH_LP_FSTATR2_WRITE_ERROR_BITS,
+                                  FSP_ERR_WRITE_FAILED);
+    FSP_ERROR_RETURN(FSP_SUCCESS == status, status);
+
+    /* If there are more blocks to write initiate another write operation. If failure return error. */
+    p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE;
+    p_ctrl->dest_end_address     += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE;
+    p_ctrl->operations_remaining--;
+
+    /* If there is more data to write start the write otherwise return success. */
+    if (p_ctrl->operations_remaining)
+    {
+        r_flash_lp_df_write_operation(p_ctrl->source_start_address, p_ctrl->dest_end_address);
+        status = FSP_ERR_IN_USE;
+    }
+    else
+    {
+        status = FSP_SUCCESS;
+    }
+
+    /* Return status */
+    return status;
+}
+
+#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function checks if the specified Data Flash address range is blank.
+ *
+ * @param[in]  p_ctrl                      Pointer to the Flash control block
+ * @param[in]  start_address               The starting address of the Flash area to blank check.
+ * @param[in]  num_bytes                   Specifies the number of bytes that need to be checked.
+ * @param[out] result                      Pointer that will be populated by the API with the results of the blank check
+ *                                         operation in non-BGO (blocking) mode. In this case the blank check operation
+ *                                         completes here and the result is returned. In Data Flash BGO mode the blank
+ *                                         check operation is only started here and the result obtained later when the
+ *                                         supplied callback routine is called.
+ *
+ * @retval     FSP_SUCCESS                 Blankcheck operation completed with result in result, or blankcheck started
+ *                                         and in-progess (BGO mode).
+ * @retval     FSP_ERR_TIMEOUT             Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_BLANK_CHECK_FAILED  An error occurred during blank checking.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_df_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl,
+                                           uint32_t                         start_address,
+                                           uint32_t                         num_bytes,
+                                           flash_result_t                 * result)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* Enter data flash P/E mode. */
+    r_flash_lp_df_enter_pe_mode(p_ctrl);
+
+    /* Execute blank check command. */
+    r_flash_lp_process_command(start_address + FLASH_LP_DATAFLASH_ADDR_OFFSET, num_bytes, FLASH_LP_FCR_BLANKCHECK);
+
+    /* If in DF BGO mode, exit here; remaining processing if any will be done in ISR */
+    if (p_ctrl->p_cfg->data_flash_bgo)
+    {
+        *result = FLASH_RESULT_BGO_ACTIVE;
+
+        return err;
+    }
+
+    /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check. This is the same as
+     * the wait time for a 1 byte Data Flash blankcheck.*/
+    err =
+        r_flash_lp_wait_for_ready(p_ctrl,
+                                  p_ctrl->timeout_blank_check * num_bytes,
+                                  FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS,
+                                  FSP_ERR_BLANK_CHECK_FAILED);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    /* Check the result of the blank check. */
+    if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank
+    {
+        *result = FLASH_RESULT_NOT_BLANK;
+    }
+    else
+    {
+        *result = FLASH_RESULT_BLANK;
+    }
+
+    /* Return the data flash to P/E mode. */
+    r_flash_lp_pe_mode_exit(p_ctrl);
+
+    /* Return status. Blank status is in result. */
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * This function checks if the specified Data Flash address range is blank.
+ *
+ * @param[in]  p_ctrl                      Pointer to the Flash control block
+ * @param[in]  start_address               The starting address of the Flash area to blank check.
+ * @param[in]  num_bytes                   Specifies the number of bytes that need to be checked.
+ * @param[out] result                      Pointer that will be populated by the API with the results of the blank check
+ *                                         operation in non-BGO (blocking) mode. In this case the blank check operation
+ *                                         completes here and the result is returned. In Data Flash BGO mode the blank
+ *                                         check operation is only started here and the result obtained later when the
+ *                                         supplied callback routine is called.
+ *
+ * @retval     FSP_SUCCESS                 Blankcheck operation completed with result in result, or blankcheck started
+ *                                         and in-progess (BGO mode).
+ * @retval     FSP_ERR_TIMEOUT             Timed out waiting for the FCU to become ready.
+ * @retval     FSP_ERR_BLANK_CHECK_FAILED  An error occurred during blank checking.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_cf_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl,
+                                           uint32_t                         start_address,
+                                           uint32_t                         num_bytes,
+                                           flash_result_t                 * result)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    /* Give the blank check command to the FACI. */
+    r_flash_lp_process_command(start_address, num_bytes, FLASH_LP_FCR_BLANKCHECK);
+
+    /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check.
+     * num_bytes is divided by 4 and then multiplied to calculate the wait time for the entire operation */
+    uint32_t wait_count = p_ctrl->timeout_blank_check * ((num_bytes + 3) / 4);
+
+    /* Wait for the blank check to complete and return result in control block. */
+    err =
+        r_flash_lp_wait_for_ready(p_ctrl, wait_count, FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, FSP_ERR_BLANK_CHECK_FAILED);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
+
+    if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank
+    {
+        /* If the result is already NOT Blank there is no reason to continue with any subsequent checks, simply return */
+        *result = FLASH_RESULT_NOT_BLANK;
+    }
+    else
+    {
+        *result = FLASH_RESULT_BLANK;
+    }
+
+    /* Return the flash to P/E mode. */
+    err = r_flash_lp_pe_mode_exit(p_ctrl);
+
+    /* Return status. Blank status is in result. */
+    return err;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Initiates a flash command.
+ * MF3: See Figures 10.18, 10.19, 10.22 and 10.23 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figures 10.15, 10.16, 10.19 and 10.20 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  start_addr      Start address of the operation.
+ * @param[in]  num_bytes       Number of bytes beginning at start_addr.
+ * @param[in]  command         The flash command
+ **********************************************************************************************************************/
+static void r_flash_lp_process_command (const uint32_t start_addr, uint32_t num_bytes, uint32_t command)
+{
+    uint32_t end_addr_idx = start_addr + (num_bytes - 1U);
+
+    /* Select User Area */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    /* BlankCheck start address setting */
+    R_FACI_LP->FSARH = (uint16_t) ((start_addr >> 16));
+    R_FACI_LP->FSARL = (uint16_t) (start_addr);
+
+    /* BlankCheck end address setting */
+    R_FACI_LP->FEARH = ((end_addr_idx >> 16));
+    R_FACI_LP->FEARL = (uint16_t) (end_addr_idx);
+
+    /* Execute BlankCheck command */
+    R_FACI_LP->FCR = (uint8_t) command;
+}
+
+/*******************************************************************************************************************//**
+ * This function switches the peripheral from P/E mode for Code Flash or Data Flash to Read mode.
+ * MF3: See Figures 10.12 and 10.13 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figures 10.9 and 10.10 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  p_ctrl                    Pointer to the Flash control block
+ * @retval     FSP_SUCCESS               Successfully entered P/E mode.
+ * @retval     FSP_ERR_TIMEOUT           Timed out waiting for confirmation of transition to read mode
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_pe_mode_exit (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE
+    uint32_t flash_pe_mode = FLASH_LP_PRV_FENTRYR;
+#endif
+
+    /* Timeout counter. */
+    volatile uint32_t wait_cnt = FLASH_LP_FRDY_CMD_TIMEOUT;
+
+#if BSP_FEATURE_FLASH_LP_VERSION == 3 && FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE
+    if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE)
+    {
+        r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_2);
+
+        /* Wait for 2us over (tDIS) */
+        r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency);
+
+        r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1);
+    }
+#endif
+    r_flash_lp_write_fpmcr(FLASH_LP_READ_MODE);
+
+    /* Wait for 5us over (tMS) */
+    r_flash_lp_delay_us(FLASH_LP_WAIT_TMS_HIGH, p_ctrl->system_clock_frequency);
+
+    /* Clear the P/E mode register */
+    FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_READ_MODE;
+
+    /* Loop until the Flash P/E mode entry register is cleared or a timeout occurs. If timeout occurs return error. */
+    FLASH_LP_REGISTER_WAIT_TIMEOUT(0, FLASH_LP_PRV_FENTRYR, wait_cnt, FSP_ERR_TIMEOUT);
+
+#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE
+    if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE)
+    {
+ #if BSP_FEATURE_BSP_FLASH_CACHE
+
+        /* Invalidate flash cache. */
+        R_FCACHE->FCACHEIV = 1U;
+        FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
+
+        /* Enable flash cache. */
+        R_FCACHE->FCACHEE = 1U;
+ #endif
+ #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
+        R_FACI_LP->PFBER = 1;
+ #endif
+    }
+#endif
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * This function resets the Flash sequencer.
+ * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.14 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  p_ctrl          Pointer to the Flash control block
+ **********************************************************************************************************************/
+static void r_flash_lp_reset (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    /* Cancel any in progress BGO operation. */
+    p_ctrl->current_operation = FLASH_OPERATION_NON_BGO;
+
+    /* If not currently in PE mode then enter P/E mode. */
+    if (FLASH_LP_PRV_FENTRYR == 0x0000UL)
+    {
+        /* Enter P/E mode so that we can execute some FACI commands. Either Code or Data Flash P/E mode would work
+         * but Code Flash P/E mode requires FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE ==1, which may not be true */
+        r_flash_lp_df_enter_pe_mode(p_ctrl);
+    }
+
+    /* Reset the flash. */
+    R_FACI_LP->FRESETR_b.FRESET = 1U;
+    R_FACI_LP->FRESETR_b.FRESET = 0U;
+
+    /* Transition to Read mode */
+    r_flash_lp_pe_mode_exit(p_ctrl);
+}
+
+/*******************************************************************************************************************//**
+ * Handle the FACI frdyi interrupt when the operation is Data Flash BGO write.
+ *
+ * @param[in]  p_ctrl     Pointer to the Flash control block
+ * @param[in]  p_cb_data  Pointer to the Flash callback event structure.
+ *
+ * @retval     true       When operation is completed or error has occurred.
+ **********************************************************************************************************************/
+static inline bool r_flash_lp_frdyi_df_bgo_write (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data)
+{
+    bool      operation_complete = false;
+    fsp_err_t result             = FSP_SUCCESS;
+
+    /* We are handling the interrupt indicating the last write operation has completed. */
+    /* Whether we are done or not we want to check the status */
+
+    result = r_flash_lp_df_write_monitor(p_ctrl);
+    if ((result != FSP_SUCCESS) && (result != FSP_ERR_IN_USE))
+    {
+        r_flash_lp_reset(p_ctrl);
+        p_cb_data->event   = FLASH_EVENT_ERR_FAILURE; ///< Pass result back to callback
+        operation_complete = true;
+    }
+    else
+    {
+        /* If the operation has completed return write complete. */
+        if (p_ctrl->operations_remaining == (uint32_t) 0)
+        {
+            p_cb_data->event   = FLASH_EVENT_WRITE_COMPLETE;
+            operation_complete = true;
+        }
+    }
+
+    return operation_complete;
+}
+
+/*******************************************************************************************************************//**
+ * Handle the FACI frdyi interrupt when the operation is Data Flash BGO erase.
+ *
+ * @param[in]  p_ctrl     Pointer to the Flash control block
+ * @param[in]  p_cb_data  Pointer to the Flash callback event structure.
+ *
+ * @retval     true       When operation is completed or error has occurred.
+ **********************************************************************************************************************/
+static inline bool r_flash_lp_frdyi_df_bgo_erase (flash_lp_instance_ctrl_t * p_ctrl, flash_callback_args_t * p_cb_data)
+{
+    fsp_err_t result = FSP_SUCCESS;
+
+    /* We are handling the interrupt indicating the last erase operation has completed. Check the status. */
+    result = r_flash_lp_wait_for_ready(p_ctrl,
+                                       p_ctrl->timeout_erase_df_block,
+                                       FLASH_LP_FSTATR2_ERASE_ERROR_BITS,
+                                       FSP_ERR_ERASE_FAILED);
+    if (result != FSP_SUCCESS)
+    {
+        r_flash_lp_reset(p_ctrl);
+
+        /* Pass result back to callback. */
+        p_cb_data->event = FLASH_EVENT_ERR_FAILURE;
+    }
+    else
+    {
+        p_cb_data->event = FLASH_EVENT_ERASE_COMPLETE;
+    }
+
+    return true;
+}
+
+/*******************************************************************************************************************//**
+ * Handle the FACI frdyi interrupt when the operation is Data Flash BGO blankcheck.
+ *
+ * @param[in]  p_ctrl     Pointer to the Flash control block
+ * @param[in]  p_cb_data  Pointer to the Flash callback event structure.
+ *
+ * @retval     true       When operation is completed or error has occurred.
+ **********************************************************************************************************************/
+static inline bool r_flash_lp_frdyi_df_bgo_blankcheck (flash_lp_instance_ctrl_t * p_ctrl,
+                                                       flash_callback_args_t    * p_cb_data)
+{
+    fsp_err_t result = FSP_SUCCESS;
+
+    /* We are handling the interrupt indicating the last blank check operation has completed. */
+    /* Whether we are done or not we want to check the status */
+    result = r_flash_lp_wait_for_ready(p_ctrl,
+                                       p_ctrl->timeout_blank_check,
+                                       FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS,
+                                       FSP_ERR_BLANK_CHECK_FAILED);
+
+    /* If failure reset the flash and return failure */
+    if (result != FSP_SUCCESS)
+    {
+        r_flash_lp_reset(p_ctrl);
+        p_cb_data->event = FLASH_EVENT_ERR_FAILURE;
+    }
+    else
+    {
+        /* Check the result and return it */
+        if (R_FACI_LP->FSTATR00_b.BCERR0 == 1U)
+        {
+            p_cb_data->event = FLASH_EVENT_NOT_BLANK;
+        }
+        else
+        {
+            p_cb_data->event = FLASH_EVENT_BLANK;
+        }
+    }
+
+    return true;
+}
+
+/*******************************************************************************************************************//**
+ * FLASH ready interrupt routine.
+ *
+ * This function implements the FLASH ready isr. The function clears the interrupt request source on entry populates the
+ * callback structure with the relevant event, and providing a callback routine has been provided, calls the callback
+ * function with the event.
+ **********************************************************************************************************************/
+void fcu_frdyi_isr (void)
+{
+    FSP_CONTEXT_SAVE
+    flash_callback_args_t cb_data;
+    bool operation_completed = false;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Continue the current operation. If unknown operation set callback event to failure. */
+    if (FLASH_OPERATION_DF_BGO_WRITE == p_ctrl->current_operation)
+    {
+        operation_completed = r_flash_lp_frdyi_df_bgo_write(p_ctrl, &cb_data);
+    }
+    else if ((FLASH_OPERATION_DF_BGO_ERASE == p_ctrl->current_operation))
+    {
+        operation_completed = r_flash_lp_frdyi_df_bgo_erase(p_ctrl, &cb_data);
+    }
+    else
+    {
+        operation_completed = r_flash_lp_frdyi_df_bgo_blankcheck(p_ctrl, &cb_data);
+    }
+
+    /* If the operation completed exit read mode, release the flash, and call the callback if available. */
+    if (operation_completed == true)
+    {
+        /* finished current operation. Exit P/E mode*/
+        r_flash_lp_pe_mode_exit(p_ctrl);
+
+        if (NULL != p_ctrl->p_cfg->p_callback)
+        {
+            /* Set data to identify callback to user, then call user callback. */
+            p_ctrl->p_cfg->p_callback(&cb_data);
+        }
+    }
+
+    FSP_CONTEXT_RESTORE
+}
+
+/*******************************************************************************************************************//**
+ * Delay for the given number of micro seconds at the given frequency
+ *
+ * @note This is used instead of R_BSP_SoftwareDelay because that may be linked in code flash.
+ *
+ * @param[in]  us              Number of microseconds to delay
+ * @param[in]  mhz             The frequency of the system clock
+ **********************************************************************************************************************/
+static void r_flash_lp_delay_us (uint32_t us, uint32_t mhz)
+{
+    uint32_t loop_cnt;
+
+    // @12 MHz, one loop is 332 ns. A delay of 5 us would require 15 loops. 15 * 332 = 4980 ns or ~ 5us
+
+    /* Calculation of a loop count */
+    loop_cnt = ((us * mhz) / FLASH_LP_DELAY_LOOP_CYCLES);
+
+    if (loop_cnt > 0U)
+    {
+        __asm volatile ("delay_loop:\n"
+#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
+                        "   subs %[loops_remaining], #1         \n"                 ///< 1 cycle
+#elif defined(__GNUC__)
+                        "   sub %[loops_remaining], %[loops_remaining], #1      \n" ///< 1 cycle
+#endif
+                        "cmp %[loops_remaining], #0\n"                              // 1 cycle
+
+/* CM0 and CM23 have different instruction sets */
+#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
+                        "   bne delay_loop   \n"                                    ///< 2 cycles
+#else
+                        "   bne.n delay_loop \n"                                    ///< 2 cycles
+#endif
+                        :                                                           // No outputs
+                        :[loops_remaining] "r" (loop_cnt)
+                        :                                                           // No clobbers
+                        );
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Transition to Data Flash P/E mode.
+ * @param[in]  p_ctrl  Pointer to the Flash control block
+ **********************************************************************************************************************/
+void r_flash_lp_df_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_DATAFLASH_PE_MODE;
+
+    r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency);
+
+    /* See "Procedure for changing from the read mode to the data flash P/E mode": figure 10.11 in
+     * SC32_FlashMemory_supplement(MF3)_20170117 and figure 10.8 in Peaks_FlashMemory_supplement(MF4)_20181105  */
+#if BSP_FEATURE_FLASH_LP_VERSION == 3
+
+    /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */
+    if (R_SYSTEM->OPCCR_b.OPCM == 0U)
+    {
+        r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE);
+    }
+    else
+    {
+        r_flash_lp_write_fpmcr((uint8_t) FLASH_LP_DATAFLASH_PE_MODE | (uint8_t) FLASH_LP_LVPE_MODE);
+    }
+
+#elif BSP_FEATURE_FLASH_LP_VERSION == 4
+    r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE);
+
+    r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency);
+#endif
+
+    /* If BGO mode is enabled and interrupts are being used then enable interrupts. */
+    if (p_ctrl->p_cfg->data_flash_bgo == true)
+    {
+        /* We are supporting Flash Rdy interrupts for Data Flash operations. */
+        R_BSP_IrqEnable(p_ctrl->p_cfg->irq);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Sets the FPMCR register, used to place the Flash sequencer in Code Flash P/E mode.
+ * @param[in]  value   - 8 bit value to be written to the FPMCR register.
+ **********************************************************************************************************************/
+static void r_flash_lp_write_fpmcr (uint8_t value)
+{
+    /* The procedure for writing to FPMCR is documented in section 10.2.3 of SC32_FlashMemory_supplement(MF3)_20170117
+     * and Peaks_FlashMemory_supplement(MF4)_20181105 */
+    R_FACI_LP->FPR = FLASH_LP_FPR_UNLOCK;
+
+    R_FACI_LP->FPMCR = value;
+    R_FACI_LP->FPMCR = (uint8_t) ~value;
+    R_FACI_LP->FPMCR = value;
+
+    if (value == R_FACI_LP->FPMCR)
+    {
+        __NOP();
+    }
+}
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Configure an access window for the Code Flash memory using the provided start and end address. An access window
+ * defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on block boundaries. The
+ * block containing start_addr is the first block. The block containing end_addr is the last block. The access window
+ * then becomes first block - last block inclusive. Anything outside this range of Code Flash is then write protected.
+ * This command DOES modify the configuration via The Configuration Set command to update the FAWS and FAWE.
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  start_addr            Determines the Starting block for the Code Flash access window.
+ * @param[in]  end_addr              Determines the Ending block for the Code Flash access window.
+ *
+ * @retval     FSP_SUCCESS           Access window successfully configured.
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the FCU to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_access_window_set (flash_lp_instance_ctrl_t * const p_ctrl,
+                                               uint32_t const                   start_addr,
+                                               uint32_t const                   end_addr)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* Enter Code Flash P/E mode */
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    /* Select The Extra Area */
+    R_FACI_LP->FASR_b.EXS = 1U;
+
+    /* Set the access window. */
+    r_flash_lp_extra_operation(start_addr, end_addr, FLASH_COMMAND_ACCESSWINDOW);
+
+    /* Wait for the operation to complete or error. */
+    err = r_flash_lp_extra_check(p_ctrl);
+
+    /* Select User Area */
+    R_FACI_LP->FASR_b.EXS = 0U;
+
+    /* Return to read mode. */
+    fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl);
+
+    /* If the previous commands were successful return the result of P/E exit. */
+    if (FSP_SUCCESS == err)
+    {
+        err = temp_err;
+    }
+
+    /* Return status. */
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Set the id code
+ * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param      p_ctrl                Pointer to the instance control block
+ * @param      p_id_code             Pointer to the code to be written
+ * @param[in]  mode                  The id code mode
+ *
+ * @retval     FSP_SUCCESS           The id code have been written.
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for completion of extra command.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_set_id_code (flash_lp_instance_ctrl_t * const p_ctrl,
+                                         uint8_t const * const            p_id_code,
+                                         flash_id_code_mode_t             mode)
+{
+    fsp_err_t err           = FSP_SUCCESS;
+    uint32_t  fexcr_command = FLASH_LP_FEXCR_OCDID1;
+
+    uint16_t mode_mask = (uint16_t) mode;
+
+    /* Update Flash state and enter Code Flash P/E mode */
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    /* For each ID byte register */
+    for (uint32_t i = 0U; i < 16U; i += 4U)
+    {
+        /* Select Extra Area */
+        R_FACI_LP->FASR_b.EXS = 1U;
+
+        /* Write the ID Bytes. If mode is unlocked write all 0xFF. Write the mode mask to the MSB. */
+        if (FLASH_ID_CODE_MODE_UNLOCKED == mode)
+        {
+            R_FACI_LP->FWBL0 = UINT16_MAX;
+            R_FACI_LP->FWBH0 = UINT16_MAX;
+        }
+        else
+        {
+            /* The id code array may be unaligned. Do not attempt to optimize this code to prevent unaligned access. */
+            R_FACI_LP->FWBL0 = (uint16_t) (p_id_code[i] | (p_id_code[i + 1] << 8));
+            if (12U == i)
+            {
+                R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8)) | mode_mask;
+            }
+            else
+            {
+                R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8));
+            }
+        }
+
+        /* Execute OCDID command */
+        R_FACI_LP->FEXCR = fexcr_command;
+
+        /* Increment the command to write to the next OCDID bytes */
+        fexcr_command++;
+
+        /* Wait until the operation is complete or an error. */
+        err = r_flash_lp_extra_check(p_ctrl);
+
+        /* Select User Area */
+        R_FACI_LP->FASR_b.EXS = 0U;
+
+        /* If failure return error */
+        if (FSP_SUCCESS != err)
+        {
+            break;
+        }
+    }
+
+    /* Return to read mode. */
+    fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl);
+
+    /* If the previous commands were successful return the result of P/E exit. */
+    if (FSP_SUCCESS == err)
+    {
+        err = temp_err;
+    }
+
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Modifies the start-up program swap flag (BTFLG) based on the supplied parameters. These changes will take effect on
+ * the next reset. This command DOES modify the configuration via The Configuration Set command to update the BTFLG.
+ *
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @param[in]  swap_type             Specifies the startup area swap being requested.
+ * @param[in]  temporary             Swap blocks temporarily.
+ *
+ * @retval     FSP_SUCCESS           Access window successfully removed.
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for the FCU to become ready.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_set_startup_area_boot (flash_lp_instance_ctrl_t * const p_ctrl,
+                                                   flash_startup_area_swap_t        swap_type,
+                                                   bool                             temporary)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    /* Update Flash state and enter Code Flash P/E mode */
+    r_flash_lp_cf_enter_pe_mode(p_ctrl);
+
+    if (temporary)
+    {
+        /* Set the Flash initial setting startup area select bit as requested. */
+        R_FACI_LP->FISR_b.SAS = swap_type;
+    }
+    else
+    {
+        /* Sets the BTFLG flag where 1 selects block 0 and 0 selects block 1. */
+ #if BSP_FEATURE_FLASH_LP_VERSION == 3
+        uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 8);  // move selection to bit 8
+ #elif BSP_FEATURE_FLASH_LP_VERSION == 4
+        uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 15); // move selection to bit 15
+ #endif
+
+        /* Select Extra Area */
+        R_FACI_LP->FASR_b.EXS = 1U;
+
+        /* Call extra operation to set the startup area. */
+        r_flash_lp_extra_operation(startup_area_mask, 0, FLASH_COMMAND_STARTUPAREA);
+
+        /* Wait until the operation is complete or an error occurs. */
+        err = r_flash_lp_extra_check(p_ctrl);
+
+        /* Select User Area */
+        R_FACI_LP->FASR_b.EXS = 0U;
+    }
+
+    /* Return to read mode. */
+    fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl);
+
+    /* If the previous commands were successful return the result of P/E exit. */
+    if (FSP_SUCCESS == err)
+    {
+        err = temp_err;
+    }
+
+    return err;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Command processing for the extra area.
+ * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  start_addr_startup_value  Determines the Starting block for the Code Flash access window.
+ * @param[in]  end_addr                  Determines the Ending block for the Code Flash access window.
+ * @param[in]  command                   Select from R_FLASH_ACCESSWINDOW or R_FLASH_STARTUPAREA.
+ **********************************************************************************************************************/
+static void r_flash_lp_extra_operation (const uint32_t    start_addr_startup_value,
+                                        const uint32_t    end_addr,
+                                        r_flash_command_t command)
+{
+    /* Per the spec: */
+    /* Setting data to the FWBL0 register, this command is allowed to select the start-up area from the */
+    /* default area (blocks 0-3) to the alternative area (blocks 4-7) and set the security. */
+    /* Bit 8 of the FWBL0 register is 0: the alternative area (blocks 4-7) are selected as the start-up area. */
+    /* Bit 8 of the FWBL0 register is 1: the default area (blocks 0-3) are selected as the start-up area. */
+    /* Bit 14 of the FWBL0 register MUST be 1! Setting this bit to zero will clear the FSPR register and lock the */
+    /* FLASH!!! It is not be possible to unlock it. */
+ #if BSP_FEATURE_FLASH_LP_VERSION == 3
+    if (FLASH_COMMAND_ACCESSWINDOW == command)
+    {
+        /* Set the Access Window start and end addresses. */
+        /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */
+        /* Convert the addresses to their respective block numbers */
+        R_FACI_LP->FWBL0 = (uint16_t) ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT));
+        R_FACI_LP->FWBH0 = (uint16_t) ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT));
+
+        /* Execute Access Window command */
+        R_FACI_LP->FEXCR = FLASH_LP_FEXCR_AW;
+    }
+    else
+    {
+        /* Startup Area Flag value setting */
+        R_FACI_LP->FWBH0 = UINT16_MAX;
+
+        /* FSPR must be set. Unused bits write value should be 1. */
+        R_FACI_LP->FWBL0 = (start_addr_startup_value | FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS);
+
+        /* Execute Startup Area Flag command */
+        R_FACI_LP->FEXCR = FLASH_LP_FEXCR_STARTUP;
+    }
+
+ #elif BSP_FEATURE_FLASH_LP_VERSION == 4
+    if (FLASH_COMMAND_ACCESSWINDOW == command)
+    {
+        uint32_t fawsmr = R_FACI_LP->FAWSMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK;
+        uint32_t fawemr = R_FACI_LP->FAWEMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK;
+
+        /* Set the Access Window start and end addresses. */
+        /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */
+        /* Convert the addresses to their respective block numbers */
+        R_FACI_LP->FWBL0 = ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawsmr);
+        R_FACI_LP->FWBH0 = ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawemr);
+
+        /* Execute Access Window command */
+        R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP;
+    }
+    else
+    {
+        uint32_t fawsmr = R_FACI_LP->FAWSMR;
+        uint32_t fawemr = R_FACI_LP->FAWEMR & ~FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK;
+
+        /* Set the Access Window start and end addresses. */
+        /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */
+        /* Convert the addresses to their respective block numbers */
+
+        /* Set the access window start address to what was in FAWSMR. */
+        R_FACI_LP->FWBL0 = fawsmr;
+
+        /* Set the access window end address to what was in FAWEMR. Set BTFLG according to user input. */
+        R_FACI_LP->FWBH0 = (start_addr_startup_value | fawemr);
+
+        /* Execute Startup Area Flag command */
+        R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP;
+    }
+ #endif
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing
+ * bit before clearing the rest of FCR.
+ * MF3: See Figure 10.24 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figure 10.21 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  timeout         The timeout
+ * @retval     FSP_SUCCESS     The command completed successfully.
+ * @retval     FSP_ERR_TIMEOUT The command timed out.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_extra_command_finish (uint32_t timeout)
+{
+    /* Timeout counter. */
+    volatile uint32_t wait_cnt = timeout;
+
+    /* If the software command of the FEXCR register is not terminated return in use. */
+    FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT);
+
+ #if BSP_FEATURE_FLASH_LP_VERSION == 4
+
+    /* Stop Processing */
+    R_FACI_LP->FEXCR = R_FACI_LP->FEXCR & ((uint8_t) ~FLASH_LP_FEXCR_PROCESSING_MASK);
+ #endif
+
+    /* Clear the Flash Extra Area Control Register. */
+    R_FACI_LP->FEXCR = FLASH_LP_FEXCR_CLEAR;
+
+    wait_cnt = timeout;
+
+    /* Wait until the command has completed or a timeout occurs. If timeout return error. */
+    FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT);
+
+    return FSP_SUCCESS;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Verifying the execution result for the extra area.
+ * @param[in]  p_ctrl                Pointer to the Flash control block
+ * @retval     FSP_SUCCESS           Access window successfully removed.
+ * @retval     FSP_ERR_WRITE_FAILED  Status is indicating a Programming error for the requested operation.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for completion of extra command.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_extra_check (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    fsp_err_t err = r_flash_lp_extra_command_finish(p_ctrl->timeout_write_extra_area);
+
+    /* If a timeout occurs reset the flash and return error. */
+    if (FSP_ERR_TIMEOUT == err)
+    {
+        r_flash_lp_reset(p_ctrl);
+
+        return err;
+    }
+
+    /* If Extra Area Illegal Command Error Flag or Error during programming reset the flash and return error. */
+    if (0 != (FLASH_LP_FSTATR2_WRITE_ERROR_BITS & R_FACI_LP->FSTATR2))
+    {
+        r_flash_lp_reset(p_ctrl);
+
+        return FSP_ERR_WRITE_FAILED;
+    }
+
+    /* Return success. */
+    return FSP_SUCCESS;
+}
+
+#endif
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Transition to Code Flash P/E mode.
+ * @param[in]  p_ctrl  Pointer to the Flash control block
+ **********************************************************************************************************************/
+void r_flash_lp_cf_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    /* While the Flash API is in use we will disable the Flash Cache. */
+ #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER
+    R_FACI_LP->PFBER = 0;
+ #endif
+ #if BSP_FEATURE_BSP_FLASH_CACHE
+    R_FCACHE->FCACHEE = 0U;
+ #endif
+
+    if (p_ctrl->p_cfg->data_flash_bgo)
+    {
+        R_BSP_IrqDisable(p_ctrl->p_cfg->irq); // We are not supporting Flash Rdy interrupts for Code Flash operations
+    }
+
+    FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_CODEFLASH_PE_MODE;
+
+    /* See "Procedure for entering code flash P/E mode": figure 10.10 in SC32_FlashMemory_supplement(MF3)_20170117
+     * and figure 10.7 in Peaks_FlashMemory_supplement(MF4)_20181105. */
+ #if BSP_FEATURE_FLASH_LP_VERSION == 3
+    r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1);
+
+    /* Wait for 2us over (tDIS) */
+    r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency);
+
+    uint32_t fpmcr_command1;
+    uint32_t fpmcr_command2;
+    uint32_t fpmcr_mode_setup_time;
+
+    /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */
+    if (R_SYSTEM->OPCCR_b.OPCM == 0U)
+    {
+        fpmcr_command1        = FLASH_LP_DISCHARGE_2;
+        fpmcr_command2        = FLASH_LP_CODEFLASH_PE_MODE;
+        fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_HIGH;
+    }
+    else
+    {
+        fpmcr_command1        = FLASH_LP_DISCHARGE_2 | FLASH_LP_LVPE_MODE;
+        fpmcr_command2        = FLASH_LP_CODEFLASH_PE_MODE | FLASH_LP_LVPE_MODE;
+        fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_MID;
+    }
+
+    r_flash_lp_write_fpmcr((uint8_t) fpmcr_command1);
+    r_flash_lp_write_fpmcr((uint8_t) fpmcr_command2);
+
+    /* Wait for 5us or 3us depending on current operating mode. (tMS) */
+    r_flash_lp_delay_us(fpmcr_mode_setup_time, p_ctrl->system_clock_frequency);
+ #elif BSP_FEATURE_FLASH_LP_VERSION == 4
+    r_flash_lp_write_fpmcr(0x02);
+
+    /* Wait for 2us over (tDIS) */
+    r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency);
+ #endif
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing
+ * bit before clearing the rest of FCR.
+ * MF3: See Figure 10.14 of MF3 manual SC32_FlashMemory_supplement(MF3)_20170117
+ * MF4: See Figures 10.14 and 10.15 of MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105
+ *
+ * @param[in]  timeout         The timeout
+ * @retval     FSP_SUCCESS     The command completed successfully.
+ * @retval     FSP_ERR_TIMEOUT The command timed out.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_command_finish (uint32_t timeout)
+{
+    /* Worst case timeout */
+    volatile uint32_t wait = timeout;
+
+    /* Check the Flash Ready Flag bit*/
+    FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT);
+
+#if BSP_FEATURE_FLASH_LP_VERSION == 4
+
+    /* Stop Processing */
+    R_FACI_LP->FCR = R_FACI_LP->FCR & ((uint8_t) ~FLASH_LP_FCR_PROCESSING_MASK);
+#endif
+
+    /* Clear FCR register */
+    R_FACI_LP->FCR = FLASH_LP_FCR_CLEAR;
+
+    /* Worst case timeout */
+    wait = timeout;
+
+    /* Wait for the Flash Ready Flag bit to indicate ready or a timeout to occur. If timeout return error. */
+    FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Wait for the current command to finish processing and check for error.
+ *
+ * @param      p_ctrl                Pointer to the control block
+ * @param[in]  timeout               The timeout
+ * @param[in]  error_bits            The error bits related to the current command
+ * @param[in]  return_code           The operation specific error code
+ *
+ * @retval     FSP_SUCCESS           Erase command successfully completed.
+ * @retval     FSP_ERR_TIMEOUT       Timed out waiting for erase command completion.
+ * @return     return_code           The operation specific error code.
+ **********************************************************************************************************************/
+static fsp_err_t r_flash_lp_wait_for_ready (flash_lp_instance_ctrl_t * const p_ctrl,
+                                            uint32_t                         timeout,
+                                            uint32_t                         error_bits,
+                                            fsp_err_t                        return_code)
+{
+    fsp_err_t err = r_flash_lp_command_finish(timeout);
+
+    /* If a timeout occurs reset the flash and return error. */
+    if (FSP_ERR_TIMEOUT == err)
+    {
+        r_flash_lp_reset(p_ctrl);
+
+        return err;
+    }
+
+    /* If an error occurs reset and return error. */
+    if (0U != (R_FACI_LP->FSTATR2 & error_bits))
+    {
+        r_flash_lp_reset(p_ctrl);
+
+        return return_code;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set the flash interface peripheral clock frequency
+ * @param      p_ctrl           Pointer to the interface control block
+ * @retval     FSP_SUCCESS      Flash interface clock frequency succesfully configured.
+ * @retval     FSP_ERR_TIMEOUT  Setting the flash interface clock frequency timed out.
+ **********************************************************************************************************************/
+fsp_err_t r_flash_lp_set_fisr (flash_lp_instance_ctrl_t * const p_ctrl)
+{
+    /* Enter data flash P/E mode to enable writing to FISR. */
+    r_flash_lp_df_enter_pe_mode(p_ctrl);
+
+#if BSP_FEATURE_FLASH_LP_VERSION == 4
+
+    /* If the flash clock is larger than 32 increment FISR_b.PCKA by 1 for every 2MHZ. (See Section 10.2.6 "Flash
+     * Internal Setting Register" of the MF4 manual Peaks_FlashMemory_supplement(MF4)_20181105) */
+    if (p_ctrl->flash_clock_frequency >= FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ)
+    {
+        R_FACI_LP->FISR_b.PCKA =
+            (0x1F + ((p_ctrl->flash_clock_frequency - FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) >> 1)) &
+            FLASH_LP_6BIT_MASK;
+    }
+    else
+#endif
+    {
+        R_FACI_LP->FISR_b.PCKA = (p_ctrl->flash_clock_frequency - 1U) & FLASH_LP_5BIT_MASK;
+    }
+
+    return r_flash_lp_pe_mode_exit(p_ctrl);
+}
+
+#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1)
+
+/*******************************************************************************************************************//**
+ * Local memcpy function to prevent from using memcpy linked in code flash
+ *
+ * @param      dest            The destination
+ * @param      src             The source
+ * @param[in]  len             The length
+ **********************************************************************************************************************/
+__STATIC_INLINE void r_flash_lp_memcpy (uint8_t * const dest, uint8_t * const src, uint32_t len)
+{
+    for (uint32_t i = 0; i < len; i++)
+    {
+        dest[i] = src[i];
+    }
+}
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c
new file mode 100644
index 0000000000..39bc1d9eec
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_gpt/r_gpt.c
@@ -0,0 +1,1367 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_gpt.h"
+#include "r_gpt_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "GPT" in ASCII, used to determine if channel is open. */
+#define GPT_OPEN                                         (0x00475054ULL)
+
+#define GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK               (BSP_FEATURE_GPTEH_CHANNEL_MASK | \
+                                                          BSP_FEATURE_GPTE_CHANNEL_MASK)
+
+#define GPT_PRV_GTWP_RESET_VALUE                         (0xA500U)
+#define GPT_PRV_GTWP_WRITE_PROTECT                       (0xA501U)
+
+#define GPT_PRV_GTIOR_STOP_LEVEL_BIT                     (6)
+#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT                  (4)
+
+#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END    (0x6U)
+#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END    (0x9U)
+
+#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH                (0x3U)
+
+#define GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER       (0x550000U)
+
+#define GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE             (0x80000000U)
+
+#define GPT_PRV_GTCCRA                                   (0U)
+#define GPT_PRV_GTCCRB                                   (1U)
+#define GPT_PRV_GTCCRC                                   (2U)
+#define GPT_PRV_GTCCRD                                   (3U)
+
+/* GPT_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */
+#define GPT_PRV_EXTRA_FEATURES_ENABLED                   (2U)
+
+#define R_GPT0_GTINTAD_ADTRAUEN_Pos                      (16U)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/* Duty cycle mode. */
+typedef enum e_gpt_duty_cycle_mode
+{
+    GPT_DUTY_CYCLE_MODE_REGISTER    = 0, // Duty cycle depends on compare match
+    GPT_DUTY_CYCLE_MODE_0_PERCENT   = 2, // Output low
+    GPT_DUTY_CYCLE_MODE_100_PERCENT = 3, // Output high
+} gpt_duty_cycle_mode_t;
+
+/* Count direction */
+typedef enum e_gpt_dir
+{
+    GPT_DIR_COUNT_DOWN = 0,
+    GPT_DIR_COUNT_UP   = 1
+} gpt_dir_t;
+
+typedef struct st_gpt_prv_duty_registers
+{
+    uint32_t gtccr_buffer;
+    uint32_t omdty;
+} gpt_prv_duty_registers_t;
+
+typedef enum e_gpt_prv_capture_event
+{
+    GPT_PRV_CAPTURE_EVENT_A,
+    GPT_PRV_CAPTURE_EVENT_B,
+} gpt_prv_capture_event_t;
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void gpt_hardware_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static void gpt_common_open(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
+
+static uint32_t gpt_clock_frequency_get(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+static void gpt_hardware_events_disable(gpt_instance_ctrl_t * p_instance_ctrl);
+
+static void r_gpt_disable_irq(IRQn_Type irq);
+
+static inline void r_gpt_write_protect_enable(gpt_instance_ctrl_t * const p_instance_ctrl);
+static inline void r_gpt_write_protect_disable(gpt_instance_ctrl_t * const p_instance_ctrl);
+
+/* Noinline attribute added to reduce code size for CM23 GCC build. */
+static void r_gpt_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context) __attribute__((noinline));
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+static void gpt_calculate_duty_cycle(gpt_instance_ctrl_t * const p_instance_ctrl,
+                                     uint32_t const              duty_cycle_counts,
+                                     gpt_prv_duty_registers_t  * p_duty_reg);
+
+static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level);
+
+#endif
+
+/***********************************************************************************************************************
+ * ISR prototypes
+ **********************************************************************************************************************/
+void gpt_counter_overflow_isr(void);
+void gpt_counter_underflow_isr(void);
+void gpt_capture_a_isr(void);
+void gpt_capture_b_isr(void);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/* Version data structure used by error logger macro. */
+static const fsp_version_t g_gpt_version =
+{
+    .api_version_minor  = TIMER_API_VERSION_MINOR,
+    .api_version_major  = TIMER_API_VERSION_MAJOR,
+    .code_version_major = GPT_CODE_VERSION_MAJOR,
+    .code_version_minor = GPT_CODE_VERSION_MINOR
+};
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* GPT implementation of timer interface  */
+const timer_api_t g_timer_on_gpt =
+{
+    .open         = R_GPT_Open,
+    .stop         = R_GPT_Stop,
+    .start        = R_GPT_Start,
+    .reset        = R_GPT_Reset,
+    .enable       = R_GPT_Enable,
+    .disable      = R_GPT_Disable,
+    .periodSet    = R_GPT_PeriodSet,
+    .dutyCycleSet = R_GPT_DutyCycleSet,
+    .infoGet      = R_GPT_InfoGet,
+    .statusGet    = R_GPT_StatusGet,
+    .close        = R_GPT_Close,
+    .versionGet   = R_GPT_VersionGet
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup GPT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open.
+ *
+ * GPT hardware does not support one-shot functionality natively.  When using one-shot mode, the timer will be stopped
+ * in an ISR after the requested period has elapsed.
+ *
+ * The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_Open
+ *
+ * @retval FSP_SUCCESS                    Initialization was successful and timer has started.
+ * @retval FSP_ERR_ASSERTION              A required input pointer is NULL or the source divider is invalid.
+ * @retval FSP_ERR_ALREADY_OPEN           Module is already open.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED       timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not
+ *                                        NULL, but ISR is not enabled.  ISR must be enabled to use one-shot mode or
+ *                                        callback.
+ * @retval FSP_ERR_INVALID_MODE           Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_extend);
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(0U == (p_cfg->source_div % 2U));
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED != GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_PWM, FSP_ERR_INVALID_MODE);
+ #endif
+    FSP_ERROR_RETURN(GPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#endif
+
+    p_instance_ctrl->channel_mask = 1U << p_cfg->channel;
+
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_VALID_CHANNEL_MASK),
+                     FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+    if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode))
+    {
+        FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+    }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Callback is required if underflow interrupt is enabled. */
+    gpt_extended_cfg_t           * p_extend  = (gpt_extended_cfg_t *) p_cfg->p_extend;
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        if (p_pwm_cfg->trough_irq >= 0)
+        {
+            FSP_ASSERT(NULL != p_cfg->p_callback);
+        }
+    }
+ #endif
+#endif
+
+    /* Initialize control structure based on configurations. */
+    gpt_common_open(p_instance_ctrl, p_cfg);
+
+    gpt_hardware_initialize(p_instance_ctrl, p_cfg);
+
+    p_instance_ctrl->open = GPT_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops timer. Implements @ref timer_api_t::stop.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_Stop
+ *
+ * @retval FSP_SUCCESS                 Timer successfully stopped.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Stop timer */
+    p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Starts timer. Implements @ref timer_api_t::start.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_Start
+ *
+ * @retval FSP_SUCCESS                 Timer successfully started.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Start timer */
+    p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets the counter value to 0. Implements @ref timer_api_t::reset.
+ *
+ * @note This function also updates to the new period if no counter overflow has occurred since the last call to
+ * R_GPT_PeriodSet().
+ *
+ * @retval FSP_SUCCESS                 Counter value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Clear timer counter. */
+    p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_Enable
+ *
+ * @retval FSP_SUCCESS                 External events successfully enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Enable (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    uint32_t             gtssr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    uint32_t             gtpsr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    uint32_t             gtcsr    = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+
+    /* OR with user settings. */
+    gtssr |= p_extend->start_source;
+    gtpsr |= p_extend->stop_source;
+    gtcsr |= p_extend->clear_source;
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set the count sources. Ensure stop and clear sources are set before start source, and capture sources are set
+     * after start source. */
+    p_instance_ctrl->p_reg->GTPSR   = gtpsr;
+    p_instance_ctrl->p_reg->GTCSR   = gtcsr;
+    p_instance_ctrl->p_reg->GTSSR   = gtssr;
+    p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source;
+    p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable.
+ *
+ * @note The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop().
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_Disable
+ *
+ * @retval FSP_SUCCESS                 External events successfully disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Disable (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    gpt_hardware_events_disable(p_instance_ctrl);
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets period value provided. If the timer is running, the period will be updated after the next counter overflow.
+ * If the timer is stopped, this function resets the counter and updates the period.
+ * Implements @ref timer_api_t::periodSet.
+ *
+ * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register.
+ * If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle
+ * will not be the desired 50% duty cycle until the counter overflow after processing completes.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_PeriodSet
+ *
+ * @retval FSP_SUCCESS                 Period value written successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Update period buffer register. The actual period is one cycle longer than the register value for saw waves
+     * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting
+     * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
+     * triangle waves. */
+    uint32_t new_gtpr = period_counts - 1U;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        new_gtpr = period_counts;
+    }
+#endif
+
+    p_instance_ctrl->p_reg->GTPBR = new_gtpr;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Set a 50% duty cycle so the period of the waveform on the output pin matches the requested period. */
+    if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
+    {
+        /* The  GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
+         * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle
+         * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
+        uint32_t duty_cycle_50_percent = (period_counts >> 1) - 1U;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD] = duty_cycle_50_percent;
+    }
+#endif
+
+    /* If the counter is not counting, update period register and reset counter. */
+    if (0U == p_instance_ctrl->p_reg->GTCR_b.CST)
+    {
+        p_instance_ctrl->p_reg->GTPR = new_gtpr;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+        p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
+#endif
+
+        p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+    }
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet.
+ *
+ * Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter
+ * overflow).
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_DutyCycleSet
+ *
+ * @param[in] p_ctrl                   Pointer to instance control block.
+ * @param[in] duty_cycle_counts        Duty cycle to set in counts.
+ * @param[in] pin                      Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA or GPT_IO_PIN_GTIOCB
+ *
+ * @retval FSP_SUCCESS                 Duty cycle updated successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL or the pin is not one of gpt_io_pin_t
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ * @retval FSP_ERR_INVALID_ARGUMENT    Duty cycle is larger than period.
+ * @retval FSP_ERR_UNSUPPORTED         GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
+{
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+ #if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(pin <= GPT_IO_PIN_GTIOCA_AND_GTIOCB);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(duty_cycle_counts <= (p_instance_ctrl->p_reg->GTPR + 1), FSP_ERR_INVALID_ARGUMENT);
+ #endif
+
+    /* Set duty cycle. */
+    gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
+    gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs);
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    p_instance_ctrl->p_reg->GTCCR[pin + 2] = duty_regs.gtccr_buffer;
+
+    /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the
+     * other pin. */
+
+    uint32_t gtuddtyc = p_instance_ctrl->p_reg->GTUDDTYC;
+    if (GPT_IO_PIN_GTIOCB != pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+        gtuddtyc &= ~R_GPT0_GTUDDTYC_OADTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos;
+    }
+
+    if (GPT_IO_PIN_GTIOCA != pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+        gtuddtyc &= ~R_GPT0_GTUDDTYC_OBDTY_Msk;
+        gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos;
+    }
+
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(duty_cycle_counts);
+    FSP_PARAMETER_NOT_USED(pin);
+
+    FSP_RETURN(FSP_ERR_UNSUPPORTED);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_InfoGet
+ *
+ * @retval FSP_SUCCESS                 Period, count direction, frequency, and ELC event written to caller's
+ *                                     structure successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_info was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_info);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get and store period */
+    uint32_t gtpr          = p_instance_ctrl->p_reg->GTPR;
+    uint32_t period_counts = gtpr + 1;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        period_counts = gtpr;
+    }
+#endif
+    p_info->period_counts = period_counts;
+
+    /* Get and store clock frequency */
+    p_info->clock_frequency = gpt_clock_frequency_get(p_instance_ctrl);
+
+    /* Get and store clock counting direction. Read count direction setting */
+    p_info->count_direction = TIMER_DIRECTION_UP;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet.
+ *
+ * Example:
+ * @snippet r_gpt_example.c R_GPT_StatusGet
+ *
+ * @retval FSP_SUCCESS                 Current timer state and counter value set successfully.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_status);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Get counter state. */
+    p_status->state = (timer_state_t) p_instance_ctrl->p_reg->GTCR_b.CST;
+
+    /* Get counter value */
+    p_status->counter = p_instance_ctrl->p_reg->GTCNT;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set counter value.
+ *
+ * @note Do not call this API while the counter is counting.  The counter value can only be updated while the counter
+ * is stopped.
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ * @retval FSP_ERR_IN_USE              The timer is running.  Stop the timer before calling this function.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->GTCR_b.CST, FSP_ERR_IN_USE);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set counter value */
+    p_instance_ctrl->p_reg->GTCNT = counter;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enable output for GTIOCA and/or GTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is enabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_OutputEnable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
+    if (GPT_IO_PIN_GTIOCB != pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+        gtior |= R_GPT0_GTIOR_OAE_Msk;
+    }
+
+    if (GPT_IO_PIN_GTIOCA != pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+        gtior |= R_GPT0_GTIOR_OBE_Msk;
+    }
+
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disable output for GTIOCA and/or GTIOCB.
+ *
+ * @retval FSP_SUCCESS                 Output is disabled.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_OutputDisable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
+    if (GPT_IO_PIN_GTIOCB != pin)
+    {
+        /* GTIOCA or both GTIOCA and GTIOCB. */
+        gtior &= ~R_GPT0_GTIOR_OAE_Msk;
+    }
+
+    if (GPT_IO_PIN_GTIOCA != pin)
+    {
+        /* GTIOCB or both GTIOCA and GTIOCB. */
+        gtior &= ~R_GPT0_GTIOR_OBE_Msk;
+    }
+
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set A/D converter start request compare match value.
+ *
+ * @retval FSP_SUCCESS                 Counter value updated.
+ * @retval FSP_ERR_ASSERTION           p_ctrl or p_status was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const    p_ctrl,
+                               gpt_adc_compare_match_t which_compare_match,
+                               uint32_t                compare_match_value)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Set A/D converter start request compare match value. */
+    volatile uint32_t * p_gtadtr = &p_instance_ctrl->p_reg->GTADTRA;
+    p_gtadtr[which_compare_match] = compare_match_value;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close.
+ *
+ * @retval FSP_SUCCESS                 Successful close.
+ * @retval FSP_ERR_ASSERTION           p_ctrl was NULL.
+ * @retval FSP_ERR_NOT_OPEN            The instance is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl)
+{
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
+    fsp_err_t             err             = FSP_SUCCESS;
+
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Clear open flag. */
+    p_instance_ctrl->open = 0U;
+
+    r_gpt_write_protect_disable(p_instance_ctrl);
+
+    /* Stop counter. */
+    p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+    /* Disable output. */
+    p_instance_ctrl->p_reg->GTIOR = 0U;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    /* Disable interrupts. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+    r_gpt_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq);
+    r_gpt_disable_irq(p_extend->capture_a_irq);
+    r_gpt_disable_irq(p_extend->capture_b_irq);
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        r_gpt_disable_irq(p_pwm_cfg->trough_irq);
+    }
+#endif
+
+    return err;
+}
+
+/*******************************************************************************************************************//**
+ * Sets driver version based on compile time macros. Implements @ref timer_api_t::versionGet.
+ *
+ * @retval FSP_SUCCESS                 Version stored in p_version.
+ * @retval FSP_ERR_ASSERTION           p_version was NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_GPT_VersionGet (fsp_version_t * const p_version)
+{
+#if GPT_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify parameters are valid */
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    p_version->version_id = g_gpt_version.version_id;
+
+    return FSP_SUCCESS;
+}
+
+/** @} (end addtogroup GPT) */
+
+/*******************************************************************************************************************//**
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Enables write protection.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ **********************************************************************************************************************/
+static inline void r_gpt_write_protect_enable (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+#if GPT_CFG_WRITE_PROTECT_ENABLE
+    p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_WRITE_PROTECT;
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Disables write protection.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ **********************************************************************************************************************/
+static inline void r_gpt_write_protect_disable (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+#if GPT_CFG_WRITE_PROTECT_ENABLE
+    p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE;
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Initializes control structure based on configuration.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block.
+ * @param[in]  p_cfg                   Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Initialize control structure.  */
+    p_instance_ctrl->p_cfg = p_cfg;
+
+    /* If callback is not null or timer mode is one shot, make sure the IRQ is enabled and store callback in the
+     *  control block.
+     *  @note The GPT hardware does not support one-shot mode natively.  To support one-shot mode, the timer will be
+     *  stopped and cleared using software in the ISR. *//* Determine if this is a 32-bit or a 16-bit timer. */
+    p_instance_ctrl->variant = TIMER_VARIANT_16_BIT;
+    if (0U != (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_32BIT_CHANNEL_MASK))
+    {
+        p_instance_ctrl->variant = TIMER_VARIANT_32_BIT;
+    }
+
+    /* Save register base address. */
+    uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0));
+    p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address;
+}
+
+/*******************************************************************************************************************//**
+ * Performs hardware initialization of the GPT.
+ *
+ * @param[in]  p_instance_ctrl        Instance control block.
+ * @param[in]  p_cfg                  Pointer to timer configuration.
+ **********************************************************************************************************************/
+static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
+{
+    /* Save pointer to extended configuration structure. */
+    gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
+
+    /* Power on GPT before setting any hardware registers. Make sure the counter is stopped before setting mode
+     * register, PCLK divisor register, and counter register. */
+    R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel);
+
+    /* Initialize all registers that may affect operation of this driver to reset values.  Skip these since they
+     * affect all channels, and are initialized in GTCR and GTCNT: GTSTR, GTSTP, GTCLR. GTCR is set immediately after
+     * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */
+    p_instance_ctrl->p_reg->GTWP  = GPT_PRV_GTWP_RESET_VALUE;
+    p_instance_ctrl->p_reg->GTCR  = 0U;
+    p_instance_ctrl->p_reg->GTST  = 0U;
+    p_instance_ctrl->p_reg->GTCNT = 0U;
+
+    /* GTPR, GTCCRn, GTIOR, GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTPBR, and GTUDDTYC are set by this driver. */
+
+    /* Initialization sets all register required for up counting as described in hardware manual (Figure 23.4 in the
+     * RA6M3 manual R01UH0886EJ0100) and other registers required by the driver. */
+
+    /* Dividers for GPT are half the enum value. */
+    uint32_t gtcr_tpcs = p_cfg->source_div >> 1;
+    uint32_t gtcr      = gtcr_tpcs << R_GPT0_GTCR_TPCS_Pos;
+
+    /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves
+     * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting
+     * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
+     * triangle waves. */
+    uint32_t gtpr = p_cfg->period_counts - 1U;
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* Saw-wave PWM mode is set in GTCR.MD for all modes except TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM and
+     * TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM. */
+    if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        gtcr |= ((uint32_t) p_cfg->mode << R_GPT0_GTCR_MD_Pos);
+        gtpr  = p_cfg->period_counts;
+    }
+#endif
+
+    /* Counter must be stopped to update TPCS. Reference section 23.2.12 "General PWM Timer Control Register (GTCR)"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    p_instance_ctrl->p_reg->GTCR = gtcr;
+
+    gpt_hardware_events_disable(p_instance_ctrl);
+
+    /* Configure the up/down count sources. These are not affected by enable/disable. */
+    p_instance_ctrl->p_reg->GTUPSR = p_extend->count_up_source;
+    p_instance_ctrl->p_reg->GTDNSR = p_extend->count_down_source;
+
+    /* Set period. The actual period is one cycle longer than the register value. Reference section 23.2.21
+     * "General PWM Timer Cycle Setting Register (GTPR)". */
+    p_instance_ctrl->p_reg->GTPBR = gtpr;
+    p_instance_ctrl->p_reg->GTPR  = gtpr;
+
+    uint32_t gtuddtyc = 0U;
+    uint32_t gtior    = 0U;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+    /* For one shot mode, the compare match buffer register must be loaded with a value that exceeds the timer
+     * cycle end value so that second compare match event would never occur and hence there will be only a
+     * single pulse.  Writing to the upper bits is ignored for 16-bit timers. */
+    gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
+
+    if (TIMER_MODE_PERIODIC == p_cfg->mode)
+    {
+        /* The  GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
+         * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle
+         * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
+        uint32_t duty_cycle_50_percent = (p_cfg->period_counts >> 1) - 1U;
+        duty_regs.gtccr_buffer = duty_cycle_50_percent;
+    }
+
+    if (p_cfg->mode >= TIMER_MODE_PWM)
+    {
+        gpt_calculate_duty_cycle(p_instance_ctrl, p_cfg->duty_cycle_counts, &duty_regs);
+    }
+
+    /* Set the compare match and compare match buffer registers based on previously calculated values. */
+    p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_regs.gtccr_buffer;
+    p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD] = duty_regs.gtccr_buffer;
+
+    /* If the requested duty cycle is 0% or 100%, set this in the registers. */
+    gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos;
+    gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos;
+
+    /* Calculate GTIOR. */
+    if (p_extend->gtioca.output_enabled)
+    {
+        uint32_t gtioca_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtioca.stop_level);
+        gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos;
+    }
+
+    if (p_extend->gtiocb.output_enabled)
+    {
+        uint32_t gtiocb_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtiocb.stop_level);
+        gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos;
+    }
+#endif
+
+#if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK
+    if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)
+    {
+        /* This register is available on GPTE and GPTEH only. It must be cleared before setting. When modifying the
+         * IVTT[2:0] bits, first set the IVTC[1:0] bits to 00b.  Reference section 23.2.18 "General PWM Timer Interrupt
+         * and A/D Converter Start Request Skipping Setting Register (GTITC)"" of the RA6M3 manual R01UH0886EJ0100. */
+        p_instance_ctrl->p_reg->GTITC = 0U;
+    }
+#endif
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
+    if (NULL != p_pwm_cfg)
+    {
+        p_instance_ctrl->p_reg->GTINTAD = ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) |
+                                          ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos) |
+                                          ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos);
+        p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up;
+
+        /* Set GTDTCR.TDE only if one of the dead time values is non-zero. */
+        uint32_t gtdtcr = ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0));
+
+ #if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK
+        if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)
+        {
+            /* These registers are only available on GPTE and GPTEH. */
+            p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT0_GTITC_IVTC_Pos) |
+                                            ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT0_GTITC_IVTT_Pos) |
+                                            ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT0_GTITC_ADTAL_Pos);
+            p_instance_ctrl->p_reg->GTDVD   = p_pwm_cfg->dead_time_count_down;
+            p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match;
+            p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match;
+        }
+ #endif
+
+        gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT0_GTIOR_OADF_Pos);
+        gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT0_GTIOR_OBDF_Pos);
+
+        p_instance_ctrl->p_reg->GTDTCR = gtdtcr;
+    }
+    else
+#endif
+    {
+        /* GTADTR* registers are unused if GTINTAD is cleared. */
+        p_instance_ctrl->p_reg->GTINTAD = 0U;
+        p_instance_ctrl->p_reg->GTDTCR  = 0U;
+
+        /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */
+    }
+
+    /* Configure the noise filter for the GTIOC pins. */
+    gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos);
+    gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos);
+
+    /* Enable the compare match buffer. */
+    p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (TIMER_MODE_ONE_SHOT == p_cfg->mode)
+    {
+        /* In one shot mode, the output pin toggles when counting starts, then again when the period expires.
+         * The buffer is enabled to set the compare match to UINT32_MAX after the one shot pulse is output
+         * so that the pin level will not change if the period expires again before the timer is stopped in
+         * the interrupt.*/
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0U;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0U;
+    }
+#endif
+
+    /* Reset counter to 0. */
+    p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
+
+    /* Set the I/O control register. */
+    p_instance_ctrl->p_reg->GTIOR = gtior;
+
+    /* Configure duty cycle and force timer to count up. GTUDDTYC must be set, then cleared to force the count
+     * direction to be reflected when counting starts. Reference section 23.2.13 "General PWM Timer Count Direction
+     * and Duty Setting Register (GTUDDTYC)" in the RA6M3 manual R01UH0886EJ0100. */
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U;
+    p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U;
+
+    r_gpt_write_protect_enable(p_instance_ctrl);
+
+    /* Enable CPU interrupts if callback is not null.  Also enable interrupts for one shot mode.
+     *  @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be
+     *  stopped and cleared using software in the ISR. */
+    r_gpt_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl);
+    r_gpt_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl);
+    r_gpt_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl);
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    if (NULL != p_pwm_cfg)
+    {
+        r_gpt_enable_irq(p_pwm_cfg->trough_irq, p_pwm_cfg->trough_ipl, p_instance_ctrl);
+    }
+#endif
+}
+
+/*******************************************************************************************************************//**
+ * Disables hardware events that would cause the timer to start, stop, clear, or capture.
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ **********************************************************************************************************************/
+static void gpt_hardware_events_disable (gpt_instance_ctrl_t * p_instance_ctrl)
+{
+    /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
+    p_instance_ctrl->p_reg->GTSSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTPSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTCSR   = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
+    p_instance_ctrl->p_reg->GTICASR = GPT_SOURCE_NONE;
+    p_instance_ctrl->p_reg->GTICBSR = GPT_SOURCE_NONE;
+}
+
+/*******************************************************************************************************************//**
+ * Disables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ **********************************************************************************************************************/
+static void r_gpt_disable_irq (IRQn_Type irq)
+{
+    /* Disable interrupts. */
+    if (irq >= 0)
+    {
+        R_BSP_IrqDisable(irq);
+        R_FSP_IsrContextSet(irq, NULL);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * Configures and enables interrupt if it is a valid vector number.
+ *
+ * @param[in]  irq                     Interrupt number
+ * @param[in]  priority                NVIC priority of the interrupt
+ * @param[in]  p_context               The interrupt context is a pointer to data required in the ISR.
+ **********************************************************************************************************************/
+static void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context)
+{
+    if (irq >= 0)
+    {
+        R_BSP_IrqCfgEnable(irq, priority, p_context);
+    }
+}
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Calculates duty cycle register values.  GTPR must be set before entering this function.
+ *
+ * @param[in]  p_instance_ctrl         Instance control structure
+ * @param[in]  duty_cycle_counts       Duty cycle to set
+ * @param[out] p_duty_reg              Duty cycle register values
+ **********************************************************************************************************************/
+static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctrl,
+                                      uint32_t const              duty_cycle_counts,
+                                      gpt_prv_duty_registers_t  * p_duty_reg)
+{
+    /* 0% and 100% duty cycle are supported in OADTY/OBDTY. */
+    uint32_t current_period = p_instance_ctrl->p_reg->GTPR;
+    if (0U == duty_cycle_counts)
+    {
+        p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT;
+    }
+    else if (duty_cycle_counts >= current_period)
+    {
+        p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_100_PERCENT;
+    }
+    else
+    {
+        uint32_t temp_duty_cycle = duty_cycle_counts;
+
+        /* When the GPT_SHORTEST_LEVEL_ON is set, the high part of the PWM wave is at the end of the cycle. */
+        gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
+        if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal)
+        {
+            temp_duty_cycle = current_period - temp_duty_cycle;
+        }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+        if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+        {
+            p_duty_reg->gtccr_buffer = temp_duty_cycle;
+        }
+        else
+ #endif
+        {
+            /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
+             * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. */
+            temp_duty_cycle--;
+            p_duty_reg->gtccr_buffer = temp_duty_cycle;
+        }
+    }
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Calculates clock frequency of GPT counter.  Divides GPT clock by GPT clock divisor.
+ *
+ * @param[in]  p_instance_ctrl           Instance control block
+ *
+ * @return     Clock frequency of the GPT counter.
+ **********************************************************************************************************************/
+static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl)
+{
+    /* Look up PCLKD frequency and divide it by GPT PCLKD divider. */
+    timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS << 1);
+    uint32_t           pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD);
+
+    return pclk_freq_hz >> pclk_divisor;
+}
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Calculates GTIOR settings for given mode and stop level.
+ *
+ * @param[in]  p_instance_ctrl         Instance control block
+ * @param[in]  p_cfg                   Timer configuration
+ * @param[in]  level                   Output level after timer stops
+ **********************************************************************************************************************/
+static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level)
+{
+    /* The stop level is used as both the initial level and the stop level. */
+    uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << GPT_PRV_GTIOR_STOP_LEVEL_BIT) |
+                     ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
+
+    uint32_t        gtion         = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
+    gpt_pin_level_t compare_match = GPT_PIN_LEVEL_LOW;
+
+    if (TIMER_MODE_PWM == p_cfg->mode)
+    {
+        gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
+        if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal)
+        {
+            /* Output high after compare match when GPT_SHORTEST_LEVEL_ON is used to generate the shortest PWM duty cycle. */
+            compare_match = GPT_PIN_LEVEL_HIGH;
+        }
+    }
+
+ #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+    else if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
+    {
+        gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH;
+    }
+ #endif
+    else
+    {
+        /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts counting). */
+        if (GPT_PIN_LEVEL_LOW == stop_level)
+        {
+            compare_match = GPT_PIN_LEVEL_HIGH;
+        }
+    }
+
+    if (compare_match == GPT_PIN_LEVEL_HIGH)
+    {
+        gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END;
+    }
+
+    gtior |= gtion;
+
+    return gtior;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Common processing for input capture interrupt.
+ *
+ * @param[in]  event  Which input capture event occurred
+ **********************************************************************************************************************/
+static void r_gpt_capture_common_isr (gpt_prv_capture_event_t event)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Get captured value. */
+    uint32_t counter = p_instance_ctrl->p_reg->GTCCR[event];
+
+    /* If we captured a one-shot pulse, then disable future captures. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        /* Disable captures. */
+        gpt_hardware_events_disable(p_instance_ctrl);
+
+        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
+        R_BSP_IrqClearPending(irq);
+    }
+
+    /* If a callback is provided, then call it with the captured counter value. */
+    if (NULL != p_instance_ctrl->p_cfg->p_callback)
+    {
+        timer_callback_args_t callback_args;
+        callback_args.event     = (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event);
+        callback_args.capture   = counter;
+        callback_args.p_context = p_instance_ctrl->p_cfg->p_context;
+        p_instance_ctrl->p_cfg->p_callback(&callback_args);
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
+
+/*******************************************************************************************************************//**
+ * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_counter_overflow_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* If one-shot mode is selected, stop the timer since period has expired. */
+    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
+    {
+        r_gpt_write_protect_disable(p_instance_ctrl);
+
+        p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
+
+        /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
+        p_instance_ctrl->p_reg->GTCNT                 = 0;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0;
+        p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0;
+
+        r_gpt_write_protect_enable(p_instance_ctrl);
+
+        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
+        R_BSP_IrqClearPending(irq);
+    }
+
+    if (NULL != p_instance_ctrl->p_cfg->p_callback)
+    {
+        /* Set data to identify callback to user, then call user callback. */
+        timer_callback_args_t callback_args;
+        callback_args.p_context = p_instance_ctrl->p_cfg->p_context;
+        callback_args.event     = TIMER_EVENT_CYCLE_END;
+        p_instance_ctrl->p_cfg->p_callback(&callback_args);
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+}
+
+#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
+
+/*******************************************************************************************************************//**
+ * Only supported for asymmetric triangle-wave PWM. Notifies application of trough event.
+ **********************************************************************************************************************/
+void gpt_counter_underflow_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE;
+
+    IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+    /* Clear pending IRQ to make sure it doesn't fire again after exiting */
+    R_BSP_IrqStatusClear(irq);
+
+    /* Recover ISR context saved in open. */
+    gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    /* Set data to identify callback to user, then call user callback. */
+    timer_callback_args_t callback_args;
+    callback_args.p_context = p_instance_ctrl->p_cfg->p_context;
+    callback_args.event     = TIMER_EVENT_TROUGH;
+    p_instance_ctrl->p_cfg->p_callback(&callback_args);
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE;
+}
+
+#endif
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture A source.
+ *
+ * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_capture_a_isr (void)
+{
+    r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_A);
+}
+
+/*******************************************************************************************************************//**
+ * Interrupt triggered by a capture B source.
+ *
+ * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
+ **********************************************************************************************************************/
+void gpt_capture_b_isr (void)
+{
+    r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_B);
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c
new file mode 100644
index 0000000000..c23457f418
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_icu/r_icu.c
@@ -0,0 +1,301 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include "r_icu.h"
+#include "r_icu_cfg.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "ICU" in ASCII, used to determine if channel is open. */
+#define ICU_OPEN              (0x00494355U)
+
+#define ICU_IRQMD_OFFSET      (0)
+#define ICU_FCLKSEL_OFFSET    (4)
+#define ICU_FLTEN_OFFSET      (7)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+void r_icu_isr(void);
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/** Version data structure used by error logger macro. */
+static const fsp_version_t g_icu_version =
+{
+    .api_version_minor  = EXTERNAL_IRQ_API_VERSION_MINOR,
+    .api_version_major  = EXTERNAL_IRQ_API_VERSION_MAJOR,
+    .code_version_major = ICU_CODE_VERSION_MAJOR,
+    .code_version_minor = ICU_CODE_VERSION_MINOR
+};
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* ICU implementation of External IRQ API. */
+const external_irq_api_t g_external_irq_on_icu =
+{
+    .open       = R_ICU_ExternalIrqOpen,
+    .enable     = R_ICU_ExternalIrqEnable,
+    .disable    = R_ICU_ExternalIrqDisable,
+    .close      = R_ICU_ExternalIrqClose,
+    .versionGet = R_ICU_ExternalIrqVersionGet
+};
+
+/*******************************************************************************************************************//**
+ * @addtogroup ICU
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Configure an IRQ input pin for use with the external interrupt interface.  Implements @ref external_irq_api_t::open.
+ *
+ * The Open function is responsible for preparing an external IRQ pin for operation.
+ *
+ * @retval FSP_SUCCESS                    Open successful.
+ * @retval FSP_ERR_ASSERTION              One of the following is invalid:
+ *                                          - p_ctrl or p_cfg is NULL
+ * @retval FSP_ERR_ALREADY_OPEN           The channel specified has already been opened. No configurations were changed.
+ *                                        Call the associated Close function to reconfigure the channel.
+ * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in
+ *                                        r_bsp_cfg.h.
+ * @retval FSP_ERR_INVALID_ARGUMENT       p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to
+ *                                        use callback function.
+ *
+ * @note This function is reentrant for different channels.  It is not reentrant for the same channel.
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg)
+{
+    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
+
+#if ICU_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_ctrl);
+    FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
+
+    /* Callback must be used with a valid interrupt priority otherwise it will never be called. */
+    if (p_cfg->p_callback)
+    {
+        FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT);
+    }
+#endif
+
+    p_ctrl->irq = p_cfg->irq;
+
+    /* IELSR Must be zero when modifying the IRQCR bits.
+     * (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */
+    uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq];
+    R_ICU->IELSR[p_ctrl->irq] = 0;
+
+    /* Initialize control block. */
+    p_ctrl->p_callback = p_cfg->p_callback;
+    p_ctrl->p_context  = p_cfg->p_context;
+    p_ctrl->channel    = p_cfg->channel;
+
+    /* Disable digital filter */
+    R_ICU->IRQCR[p_ctrl->channel] = 0U;
+
+    /* Set the digital filter divider. */
+    uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET);
+
+    /* Enable/Disable digital filter. */
+    irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET);
+
+    /* Set the IRQ trigger. */
+    irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET);
+
+    /* Write IRQCR */
+    R_ICU->IRQCR[p_ctrl->channel] = irqcr;
+
+    /* Restore IELSR. */
+    R_ICU->IELSR[p_ctrl->irq] = ielsr;
+
+    /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases
+     * where the external IRQ driver is used to generate ELC events only (without CPU interrupts).
+     * In such cases we will not set the IRQ priority but will continue with the processing.
+     */
+    if (p_ctrl->irq >= 0)
+    {
+        R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl);
+    }
+
+    /* Mark the control block as open */
+    p_ctrl->open = ICU_OPEN;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable.
+ *
+ * @retval FSP_SUCCESS                 Interrupt Enabled successfully.
+ * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
+ * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl)
+{
+    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
+
+#if ICU_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_ctrl);
+    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+#endif
+
+    /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */
+    R_BSP_IrqEnable(p_ctrl->irq);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable.
+ *
+ * @retval FSP_SUCCESS                 Interrupt disabled successfully.
+ * @retval FSP_ERR_ASSERTION           The p_ctrl parameter was null.
+ * @retval FSP_ERR_NOT_OPEN            The channel is not opened.
+ * @retval FSP_ERR_IRQ_BSP_DISABLED    Requested IRQ is not defined in this system
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl)
+{
+    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
+
+#if ICU_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_ctrl);
+    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
+#endif
+
+    /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
+    R_BSP_IrqDisable(p_ctrl->irq);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Close the external interrupt channel. Implements @ref external_irq_api_t::close.
+ *
+ * @retval     FSP_SUCCESS          Successfully closed.
+ * @retval     FSP_ERR_ASSERTION    The parameter p_ctrl is NULL.
+ * @retval     FSP_ERR_NOT_OPEN     The channel is not opened.
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl)
+{
+    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl;
+
+#if ICU_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_ctrl);
+    FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /* Cleanup. Disable interrupt */
+    if (p_ctrl->irq >= 0)
+    {
+        /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */
+        R_BSP_IrqDisable(p_ctrl->irq);
+        R_FSP_IsrContextSet(p_ctrl->irq, NULL);
+    }
+
+    p_ctrl->open = 0U;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Set driver version based on compile time macros.  Implements @ref external_irq_api_t::versionGet.
+ *
+ * @retval     FSP_SUCCESS        Successful close.
+ * @retval     FSP_ERR_ASSERTION  The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t R_ICU_ExternalIrqVersionGet (fsp_version_t * const p_version)
+{
+#if ICU_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_version);
+#endif
+
+    p_version->version_id = g_icu_version.version_id;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup ICU)
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * ICU External Interrupt ISR.
+ **********************************************************************************************************************/
+void r_icu_isr (void)
+{
+    /* Save context if RTOS is used */
+    FSP_CONTEXT_SAVE
+
+    IRQn_Type             irq    = R_FSP_CurrentIrqGet();
+    icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
+
+    bool level_irq = false;
+    if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD)
+    {
+        level_irq = true;
+    }
+    else
+    {
+        /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active
+         * it will not be missed. */
+        R_BSP_IrqStatusClear(irq);
+    }
+
+    if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback))
+    {
+        /* Set data to identify callback to user, then call user callback. */
+        external_irq_callback_args_t args;
+        args.channel   = p_ctrl->channel;
+        args.p_context = p_ctrl->p_context;
+        p_ctrl->p_callback(&args);
+    }
+
+    if (level_irq)
+    {
+        /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not
+         * be called again. */
+        R_BSP_IrqStatusClear(irq);
+    }
+
+    /* Restore context if RTOS is used */
+    FSP_CONTEXT_RESTORE
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c
new file mode 100644
index 0000000000..a80edb1b3f
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/r_ioport/r_ioport.c
@@ -0,0 +1,909 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+#include 
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/* "PORT" in ASCII, used to determine if the module is open */
+#define IOPORT_OPEN                       (0x504F5254U)
+#define IOPORT_CLOSED                     (0x00000000U)
+
+/* Mask to get PSEL bitfield from PFS register. */
+#define BSP_PRV_PFS_PSEL_MASK             (0x1F000000UL)
+
+/* Shift to get pin 0 on a package in extended data. */
+#define IOPORT_PRV_EXISTS_B0_SHIFT        (16UL)
+
+/* Mask to determine if any pins on port exist on this package. */
+#define IOPORT_PRV_PORT_EXISTS_MASK       (0xFFFF0000U)
+
+/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
+#define IOPORT_PRV_PORT_OFFSET            (8U)
+
+#ifndef BSP_MCU_VBATT_SUPPORT
+ #define BSP_MCU_VBATT_SUPPORT            (0U)
+#endif
+
+#define IOPORT_PRV_PORT_BITS              (0xFF00U)
+#define IOPORT_PRV_PIN_BITS               (0x00FFU)
+
+#define IOPORT_PRV_PCNTR_OFFSET           0x00000020U
+
+#define IOPORT_PRV_PERIPHERAL_FUNCTION    (1U << 16)
+#define IOPORT_PRV_CLEAR_BITS_MASK        (0x1F01FCD5U) ///< Zero bits in mask must be written as zero to PFS register
+
+#define IOPORT_PRV_8BIT_MASK              (0xFFU)
+#define IOPORT_PRV_16BIT_MASK             (0xFFFFU)
+#define IOPORT_PRV_UPPER_16BIT_MASK       (0xFFFF0000U)
+#define IOPORT_PRV_PFENET_MASK            (0x30U)
+
+#define IOPORT_PRV_SET_PWPR_PFSWE         (0x40U)
+#define IOPORT_PRV_SET_PWPR_BOWI          (0x80U)
+
+#define IOPORT_PRV_PORT_ADDRESS(port_number)    ((uint32_t) (R_PORT1 - R_PORT0) * (port_number) + R_PORT0)
+
+/***********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private function prototypes
+ **********************************************************************************************************************/
+static void r_ioport_pins_config(const ioport_cfg_t * p_cfg);
+
+static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t  port,
+                                                    ioport_size_t  set_value,
+                                                    ioport_size_t  reset_value,
+                                                    bsp_io_level_t pin_level);
+
+static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value);
+
+#if BSP_MCU_VBATT_SUPPORT
+static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP
+
+#endif
+
+/***********************************************************************************************************************
+ * Private global variables
+ **********************************************************************************************************************/
+
+/* Version data structure used by error logger macro. */
+static const fsp_version_t g_ioport_version =
+{
+    .api_version_minor  = IOPORT_API_VERSION_MINOR,
+    .api_version_major  = IOPORT_API_VERSION_MAJOR,
+    .code_version_major = IOPORT_CODE_VERSION_MAJOR,
+    .code_version_minor = IOPORT_CODE_VERSION_MINOR
+};
+
+/***********************************************************************************************************************
+ * Global Variables
+ **********************************************************************************************************************/
+
+/* IOPort Implementation of IOPort Driver  */
+const ioport_api_t g_ioport_on_ioport =
+{
+    .open                 = R_IOPORT_Open,
+    .close                = R_IOPORT_Close,
+    .pinsCfg              = R_IOPORT_PinsCfg,
+    .pinCfg               = R_IOPORT_PinCfg,
+    .pinEventInputRead    = R_IOPORT_PinEventInputRead,
+    .pinEventOutputWrite  = R_IOPORT_PinEventOutputWrite,
+    .pinEthernetModeCfg   = R_IOPORT_EthernetModeCfg,
+    .pinRead              = R_IOPORT_PinRead,
+    .pinWrite             = R_IOPORT_PinWrite,
+    .portDirectionSet     = R_IOPORT_PortDirectionSet,
+    .portEventInputRead   = R_IOPORT_PortEventInputRead,
+    .portEventOutputWrite = R_IOPORT_PortEventOutputWrite,
+    .portRead             = R_IOPORT_PortRead,
+    .portWrite            = R_IOPORT_PortWrite,
+    .versionGet           = R_IOPORT_VersionGet,
+};
+
+#if BSP_MCU_VBATT_SUPPORT
+static const bsp_io_port_pin_t g_vbatt_pins_input[] =
+{
+    BSP_IO_PORT_04_PIN_02,             ///< Associated with VBTICTLR->VCH0INEN
+    BSP_IO_PORT_04_PIN_03,             ///< Associated with VBTICTLR->VCH1INEN
+    BSP_IO_PORT_04_PIN_04              ///< Associated with VBTICTLR->VCH2INEN
+};
+#endif
+
+/*******************************************************************************************************************//**
+ * @addtogroup IOPORT
+ * @{
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Initializes internal driver data, then calls pin configuration function to configure pins.
+ *
+ * @retval FSP_SUCCESS                  Pin configuration data written to PFS register(s)
+ * @retval FSP_ERR_ASSERTION            NULL pointer
+ * @retval FSP_ERR_ALREADY_OPEN         Module is already open.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
+{
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
+    FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Set driver status to open */
+    p_instance_ctrl->open = IOPORT_OPEN;
+
+    r_ioport_pins_config(p_cfg);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Resets IOPORT registers. Implements @ref ioport_api_t::close
+ *
+ * @retval FSP_SUCCESS             The IOPORT was successfully uninitialized
+ * @retval FSP_ERR_ASSERTION       p_ctrl was NULL
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl)
+{
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Set state to closed */
+    p_instance_ctrl->open = IOPORT_CLOSED;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Configures the functions of multiple pins by loading configuration data into pin PFS registers.
+ * Implements @ref ioport_api_t::pinsCfg.
+ *
+ * This function initializes the supplied list of PmnPFS registers with the supplied values. This data can be generated
+ * by the Pins tab of the RA Configuration editor or manually by the developer. Different pin configurations can be
+ * loaded for different situations such as low power modes and testing.
+ *
+ * @retval FSP_SUCCESS             Pin configuration data written to PFS register(s)
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_cfg);
+    FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    r_ioport_pins_config(p_cfg);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg.
+ *
+ * @retval FSP_SUCCESS             Pin configured
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ *
+ * @note This function is re-entrant for different pins.
+ * This function will change the configuration of the pin with the new configuration. For example it is not possible
+ * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To
+ * achieve this the original settings with the required change will need to be written using this function.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+#if BSP_MCU_VBATT_SUPPORT
+
+    /* Create temporary structure for handling VBATT pins. */
+    ioport_cfg_t     temp_cfg;
+    ioport_pin_cfg_t temp_pin_cfg;
+
+    temp_pin_cfg.pin     = pin;
+    temp_pin_cfg.pin_cfg = cfg;
+
+    temp_cfg.number_of_pins = 1U;
+    temp_cfg.p_pin_cfg_data = &temp_pin_cfg;
+
+    /* Handle any VBATT domain pin configuration. */
+    bsp_vbatt_init(&temp_cfg);
+#endif
+
+    R_BSP_PinAccessEnable();
+
+    r_ioport_pfs_write(pin, cfg);
+
+    R_BSP_PinAccessDisable();
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the level on a pin. Implements @ref ioport_api_t::pinRead.
+ *
+ * @retval FSP_SUCCESS             Pin read
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ * @note This function is re-entrant for different pins.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_pin_value);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value on an IO port. Implements @ref ioport_api_t::portRead.
+ *
+ * The specified port will be read, and the levels for all the pins will be returned.
+ * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds
+ * to pin 7, bit 6 to pin 6, and so on.
+ *
+ * @retval FSP_SUCCESS             Port read
+ * @retval FSP_ERR_ASSERTION       NULL pointer
+ * @retval FSP_ERR_NOT_OPEN        The module has not been opened
+ *
+ * @note This function is re-entrant for different ports.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_port_value);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* Read current value of PCNTR2 register for the specified port */
+    *p_port_value = p_ioport_regs->PCNTR2 & IOPORT_PRV_16BIT_MASK;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite.
+ *
+ * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit
+ * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
+ * Each bit in the mask parameter corresponds to a pin on the port.
+ *
+ * Only the bits with the corresponding bit in the mask value set will be updated.
+ * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated.
+ *
+ * @retval FSP_SUCCESS                  Port written to
+ * @retval FSP_ERR_INVALID_ARGUMENT     The port and/or mask not valid
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opened
+ * @retval FSP_ERR_ASSERTION            NULL pointerd
+ *
+ * @note This function is re-entrant for different ports. This function makes use of the PCNTR3 register to atomically
+ * modify the levels on the specified pins on a port.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    ioport_size_t setbits;
+    ioport_size_t clrbits;
+
+    /* High bits */
+    setbits = value & mask;
+
+    /* Low bits */
+    /* Cast to ensure size */
+    clrbits = (ioport_size_t) ((~value) & mask);
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* PCNTR3 register: lower word = set data, upper word = reset_data */
+    p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite.
+ *
+ * @retval FSP_SUCCESS                  Pin written to
+ * @retval FSP_ERR_INVALID_ARGUMENT     The pin and/or level not valid
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opene
+ * @retval FSP_ERR_ASSERTION            NULL pointerd
+ *
+ * @note This function is re-entrant for different pins. This function makes use of the PCNTR3 register to atomically
+ * modify the level on the specified pin on a port.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    ioport_size_t setbits = 0U;
+    ioport_size_t clrbits = 0U;
+    bsp_io_port_t port    = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin);
+
+    ioport_size_t shift    = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin;
+    ioport_size_t pin_mask = (ioport_size_t) (1U << shift);
+
+    if (BSP_IO_LEVEL_LOW == level)
+    {
+        clrbits = pin_mask;
+    }
+    else
+    {
+        setbits = pin_mask;
+    }
+
+    /* PCNTR register is updated instead of using PFS as access is atomic and PFS requires seperate enable/disable
+     * using PWPR register */
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* PCNTR3 register: lower word = set data, upper word = reset_data */
+    p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet().
+ *
+ * Multiple pins on a port can be set to inputs or outputs at once.
+ * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to
+ * pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to
+ * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of
+ * the pin will not be changed.
+ *
+ * @retval FSP_SUCCESS                 Port direction updated
+ * @retval FSP_ERR_INVALID_ARGUMENT    The port and/or mask not valid
+ * @retval FSP_ERR_NOT_OPEN            The module has not been opened
+ * @retval FSP_ERR_ASSERTION           NULL pointer
+ *
+ * @note This function is re-entrant for different ports.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
+                                     bsp_io_port_t         port,
+                                     ioport_size_t         direction_values,
+                                     ioport_size_t         mask)
+{
+    ioport_size_t orig_value;
+    ioport_size_t set_bits;
+    ioport_size_t clr_bits;
+    ioport_size_t write_value;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* Read current value of PCNTR1 register for the specified port */
+    orig_value = p_ioport_regs->PCNTR1 & IOPORT_PRV_16BIT_MASK;
+
+    /* High bits */
+    set_bits = direction_values & mask;
+
+    /*  Low bits */
+    /* Cast to ensure size */
+    clr_bits = (ioport_size_t) ((~direction_values) & mask);
+
+    /* New value to write to port direction register */
+    write_value  = orig_value;
+    write_value |= set_bits;
+
+    /* Cast to ensure size */
+    write_value &= (ioport_size_t) (~clr_bits);
+
+    p_ioport_regs->PCNTR1 = write_value & IOPORT_PRV_16BIT_MASK;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead().
+ *
+ * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port.
+ * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
+ *
+ * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read.
+ * Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
+ *
+ * @retval FSP_SUCCESS              Port read
+ * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port
+ * @retval FSP_ERR_ASSERTION        NULL pointer
+ * @retval FSP_ERR_NOT_OPEN         The module has not been opened
+ *
+ * @note This function is re-entrant for different ports.
+ *
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_event_data);
+    uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(port >> IOPORT_PRV_PORT_OFFSET & IOPORT_PRV_8BIT_MASK);
+
+    /* Read current value of EIDR value from PCNTR2 register for the specified port */
+    *p_event_data = p_ioport_regs->PCNTR2_b.EIDR;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead.
+ *
+ * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read.
+ * Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
+ *
+ * @retval FSP_SUCCESS                  Pin read
+ * @retval FSP_ERR_ASSERTION            NULL pointer
+ * @retval FSP_ERR_NOT_OPEN             The module has not been opened
+ * @retval FSP_ERR_INVALID_ARGUMENT     Port is not valid ELC PORT.
+ *
+ * @note This function is re-entrant.
+ *
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event)
+{
+    ioport_size_t portvalue;
+    ioport_size_t mask;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ASSERT(NULL != p_pin_event);
+    uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((pin >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* Read current value of EIDR value from PCNTR2 register for the specified port */
+    portvalue = p_ioport_regs->PCNTR2_b.EIDR;
+    mask      = (ioport_size_t) (1U << (IOPORT_PRV_PIN_BITS & (bsp_io_port_t) pin));
+
+    if ((portvalue & mask) == mask)
+    {
+        *p_pin_event = BSP_IO_LEVEL_HIGH;
+    }
+    else
+    {
+        *p_pin_event = BSP_IO_LEVEL_LOW;
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * This function writes the set and reset event output data for a port. Implements
+ * @ref ioport_api_t::portEventOutputWrite.
+ *
+ * Using the event system enables a port state to be stored by this function in advance of being output on the port.
+ * The output to the port will occur when the ELC event occurs.
+ *
+ * The input value will be written to the specified port when an ELC event configured for that port occurs.
+ * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7,
+ * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port.
+ *
+ * @retval FSP_SUCCESS                Port event data written
+ * @retval FSP_ERR_INVALID_ARGUMENT   Port or Mask not valid
+ * @retval FSP_ERR_NOT_OPEN           The module has not been opened
+ * @retval FSP_ERR_ASSERTION          NULL pointer
+ *
+ * @note This function is re-entrant for different ports.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl,
+                                         bsp_io_port_t         port,
+                                         ioport_size_t         event_data,
+                                         ioport_size_t         mask_value)
+{
+    ioport_size_t set_bits;
+    ioport_size_t reset_bits;
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
+    uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    set_bits = event_data & mask_value;
+
+    /* Cast to ensure size */
+    reset_bits = (ioport_size_t) ((~event_data) & mask_value);
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* PCNTR4 register: lower word = set data, upper word = reset_data */
+    p_ioport_regs->PCNTR4 = (uint32_t) (((uint32_t) reset_bits << 16) | set_bits);
+
+    return FSP_SUCCESS;
+}
+
+/**********************************************************************************************************************//**
+ * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite.
+ *
+ * Using the event system enables a pin state to be stored by this function in advance of being output on the pin.
+ * The output to the pin will occur when the ELC event occurs.
+ *
+ * @retval FSP_SUCCESS               Pin event data written
+ * @retval FSP_ERR_INVALID_ARGUMENT  Port or Pin or value not valid
+ * @retval FSP_ERR_NOT_OPEN          The module has not been opened
+ * @retval FSP_ERR_ASSERTION         NULL pointer
+ *
+ * @note This function is re-entrant for different ports.
+ *
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT);
+    uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
+    FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+#endif
+
+    ioport_size_t set_bits;
+    ioport_size_t reset_bits;
+    bsp_io_port_t port;
+    uint16_t      pin_to_port;
+
+    /* Cast to ensure correct conversion of parameter. */
+    pin_to_port = (uint16_t) pin;
+    pin_to_port = pin_to_port & (uint16_t) IOPORT_PRV_PORT_BITS;
+    port        = (bsp_io_port_t) pin_to_port;
+    set_bits    = (ioport_size_t) 0;
+    reset_bits  = (ioport_size_t) 0;
+
+    if (BSP_IO_LEVEL_HIGH == pin_value)
+    {
+        /* Cast to ensure size */
+        set_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS));
+    }
+    else
+    {
+        /* Cast to ensure size */
+        reset_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS));
+    }
+
+    r_ioport_hw_pin_event_output_data_write(port, set_bits, reset_bits, pin_value);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ *  Returns IOPort HAL driver version. Implements @ref ioport_api_t::versionGet.
+ *
+ * @retval FSP_SUCCESS        Version information read
+ * @retval FSP_ERR_ASSERTION  The parameter p_data is NULL
+ *
+ * @note This function is reentrant.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_VersionGet (fsp_version_t * p_data)
+{
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+
+    /* Verify parameters are valid */
+    FSP_ASSERT(NULL != p_data);
+#endif
+
+    *p_data = g_ioport_version;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
+ *
+ * @retval FSP_SUCCESS              Ethernet PHY mode set
+ * @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid
+ * @retval FSP_ERR_UNSUPPORTED      Ethernet configuration not supported on this device.
+ * @retval FSP_ERR_NOT_OPEN         The module has not been opened
+ * @retval FSP_ERR_ASSERTION        NULL pointer
+ *
+ * @note This function is not re-entrant.
+ **********************************************************************************************************************/
+fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const     p_ctrl,
+                                    ioport_ethernet_channel_t channel,
+                                    ioport_ethernet_mode_t    mode)
+{
+    FSP_ERROR_RETURN(1U == BSP_FEATURE_IOPORT_HAS_ETHERNET, FSP_ERR_UNSUPPORTED);
+
+#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
+    ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(channel < IOPORT_ETHERNET_CHANNEL_END, FSP_ERR_INVALID_ARGUMENT);
+    FSP_ERROR_RETURN(mode < IOPORT_ETHERNET_MODE_END, FSP_ERR_INVALID_ARGUMENT);
+#else
+    FSP_PARAMETER_NOT_USED(p_ctrl);
+    FSP_PARAMETER_NOT_USED(channel);
+#endif
+
+    R_PMISC->PFENET = (uint8_t) mode;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * @} (end addtogroup IOPORT)
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private Functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Configures pins.
+ *
+ * @param[in]    p_cfg          Pin configuration data
+ **********************************************************************************************************************/
+void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
+{
+#if BSP_MCU_VBATT_SUPPORT
+
+    /* Handle any VBATT domain pin configuration. */
+    bsp_vbatt_init(p_cfg);
+#endif
+
+    uint16_t       pin_count;
+    ioport_cfg_t * p_pin_data;
+
+    p_pin_data = (ioport_cfg_t *) p_cfg;
+
+    R_BSP_PinAccessEnable();           // Protect PWPR from re-entrancy
+
+    for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++)
+    {
+        r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg);
+    }
+
+    R_BSP_PinAccessDisable();
+}
+
+/*******************************************************************************************************************//**
+ * Writes the set and clear values on a pin of the port when an ELC event occurs. This allows accurate timing of
+ * pin output level.
+ *
+ * @param[in]    port           Port to read event data
+ * @param[in]    set_value      Bit in the port to set high (1 = that bit will be set high)
+ * @param[in]    reset_value    Bit in the port to clear low (1 = that bit will be cleared low)
+ * @param[in]    pin_level      Event data for pin
+ **********************************************************************************************************************/
+static void r_ioport_hw_pin_event_output_data_write (bsp_io_port_t  port,
+                                                     ioport_size_t  set_value,
+                                                     ioport_size_t  reset_value,
+                                                     bsp_io_level_t pin_level)
+{
+    uint32_t port_value = 0;
+
+    /* Get the port address */
+    R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
+
+    /* Read current value of PCNTR4 register */
+    port_value = p_ioport_regs->PCNTR4;
+
+    if (BSP_IO_LEVEL_HIGH == pin_level)
+    {
+        /* set value contains the bit to be set high (bit mask) */
+        port_value |= (uint32_t) (set_value);
+
+        /* reset value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR
+         *  bit of a particular pin should not be high at the same time */
+        port_value &= (((uint32_t) reset_value << 16) | IOPORT_PRV_16BIT_MASK);
+    }
+    else
+    {
+        /* reset_value contains the bit to be cleared low */
+        port_value |= (uint32_t) reset_value << 16;
+
+        /* set value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR bit of a
+         *  particular pin should not be high at the same time */
+        port_value &= (uint32_t) ((set_value | IOPORT_PRV_UPPER_16BIT_MASK));
+    }
+
+    p_ioport_regs->PCNTR4 = port_value;
+}
+
+/*******************************************************************************************************************//**
+ * Writes to the specified pin's PFS register
+ *
+ * @param[in]    pin        Pin to write PFS data for
+ * @param[in]    value      Value to be written to the PFS register
+ *
+ **********************************************************************************************************************/
+static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value)
+{
+    /* PMR bits should be cleared before specifying PSEL. Reference section "20.7 Notes on the PmnPFS Register Setting"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0)
+    {
+        /* Clear PMR */
+        R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PMR = 0;
+
+        /* New config with PMR = 0 */
+        R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin &
+                                                       BSP_IO_PRV_8BIT_MASK].PmnPFS =
+            (value & ~((uint32_t) IOPORT_PRV_PERIPHERAL_FUNCTION));
+    }
+
+    /* Write configuration */
+    R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value;
+}
+
+#if BSP_MCU_VBATT_SUPPORT
+
+/*******************************************************************************************************************//**
+ * @brief Initializes VBTICTLR register based on pin configuration.
+ *
+ * The VBTICTLR register may need to be modified based on the project's pin configuration. There is a set of pins that
+ * needs to be checked. If one of these pins is found in the pin configuration table then it will be tested to see if
+ * the appropriate VBTICTLR bit needs to be set or cleared. If one of the pins that is being searched for is not found
+ * then the accompanying VBTICTLR bit is left as-is.
+ **********************************************************************************************************************/
+static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
+{
+    uint32_t pin_index;
+    uint32_t vbatt_index;
+    uint8_t  local_vbtictlr_set;       ///< Will hold bits to set in VBTICTLR
+    uint8_t  local_vbtictlr_clear;     ///< Will hold bits to clear in VBTICTLR
+
+    /* Make no changes unless required. */
+    local_vbtictlr_set   = 0U;
+    local_vbtictlr_clear = 0U;
+
+    /* Must loop over all pins as pin configuration table is unordered. */
+    for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++)
+    {
+        /* Loop over VBATT input pins. */
+        for (vbatt_index = 0U;
+             vbatt_index < (sizeof(g_vbatt_pins_input) / sizeof(g_vbatt_pins_input[0]));
+             vbatt_index++)
+        {
+            if (p_pin_cfg->p_pin_cfg_data[pin_index].pin == g_vbatt_pins_input[vbatt_index])
+            {
+                /* Get PSEL value for pin. */
+                uint32_t pfs_psel_value = p_pin_cfg->p_pin_cfg_data[pin_index].pin_cfg & BSP_PRV_PFS_PSEL_MASK;
+
+                /* Check if pin is being used for RTC or AGT use. */
+                if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value))
+                {
+                    /* Bit should be set to 1. */
+                    local_vbtictlr_set |= (uint8_t) (1U << vbatt_index);
+                }
+                else
+                {
+                    /* Bit should be cleared to 0. */
+                    local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index);
+                }
+            }
+        }
+    }
+
+    /* Disable write protection on VBTICTLR. */
+    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
+
+    /* Read value, set and clear bits as needed and write back. */
+    uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR;
+    local_vbtictlr |= local_vbtictlr_set;              ///< Set appropriate bits
+    local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits
+
+    R_SYSTEM->VBTICTLR = local_vbtictlr;
+
+    /* Enable write protection on VBTICTLR. */
+    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
+}
+
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c
new file mode 100644
index 0000000000..dca675aaf3
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_ble_abs/rm_ble_abs.c
@@ -0,0 +1,4186 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
+ * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
+ * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
+ * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
+ * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
+ * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
+ * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
+ * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
+ * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
+ * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Includes    , "Project Includes"
+ **********************************************************************************************************************/
+#include 
+#include 
+
+#include "rm_ble_abs_api.h"
+#include "rm_ble_abs.h"
+
+#include "fsp_common_api.h"
+
+#if ((BSP_CFG_RTOS == 2))
+ #include "FreeRTOS.h"
+ #include "task.h"
+ #include "event_groups.h"
+ #define BLE_EVENT_PATTERN    (0x0A0A)
+#endif
+
+/***********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+
+/** "BLE_ABS" in ASCII, used to determine if module is open. */
+#define BLE_ABS_OPEN    (0X00424C45ULL)
+
+/**********************************/
+/** Define for advertising handle */
+/**********************************/
+/** Advertising Handle for Legacy Advertising. */
+#define BLE_ABS_LEGACY_HDL      (0x00)
+
+/** Advertising Handle for Extended Advertising. */
+#define BLE_ABS_EXT_HDL         (0x01)
+
+/** Advertising Handle for Non-Connectable Advertising. */
+#define BLE_ABS_NON_CONN_HDL    (0x02)
+
+/** Advertising Handle for Periodic Advertising. */
+#define BLE_ABS_PERD_HDL        (0x03)
+
+/** Advertising Handle for Legacy Advertising */
+#define BLE_ABS_COMMON_HDL      (0x00)
+
+/**********************************/
+/** Define for advertising status */
+/**********************************/
+/** set fast advertising parameters */
+#define BLE_ABS_ADV_STATUS_PARAM_FAST        (0x00000001)
+
+/** set slow advertising parameters */
+#define BLE_ABS_ADV_STATUS_PARAM_SLOW        (0x00000002)
+
+/** set advertising data */
+#define BLE_ABS_ADV_STATUS_ADV_DATA          (0x00000010)
+
+/** set scan response data */
+#define BLE_ABS_ADV_STATUS_SRES_DATA         (0x00000020)
+
+/** set periodic advertising data */
+#define BLE_ABS_ADV_STATUS_PERD_DATA         (0x00000040)
+
+/** start fast advertising */
+#define BLE_ABS_ADV_STATUS_ADV_FAST_START    (0x00000100)
+
+/** start slow advertising */
+#define BLE_ABS_ADV_STATUS_ADV_SLOW_START    (0x00000200)
+
+/** set periodic advertising parameters */
+#define BLE_ABS_ADV_STATUS_PERD_PARAM        (0x00001000)
+
+/** start periodic advertising */
+#define BLE_ABS_ADV_STATUS_PERD_START        (0x00010000)
+
+/** set legacy adv for legacy advertising  */
+#define BLE_ABS_ADV_COMM_LEG                 (0x00100000)
+
+/** set non-connectable adv for legacy advertising  */
+#define BLE_ABS_ADV_COMM_NON                 (0x00200000)
+
+/** set non-connectable adv for legacy advertising  */
+#define BLE_ABS_ADV_COMM_TO                  (0x01000000)
+
+/**********************************/
+/** Define for scan status        */
+/**********************************/
+/** start fast scan */
+#define BLE_ABS_SCAN_STATUS_FAST_START    (0x00000001)
+
+/** start slow scan */
+#define BLE_ABS_SCAN_STATUS_SLOW_START    (0x00000002)
+
+/**********************************/
+/** Define for privacy status     */
+/**********************************/
+/** create irk */
+#define BLE_ABS_PV_STATUS_CREATE_IRK    (0x00000001)
+
+/** add irk to resolving list */
+#define BLE_ABS_PV_STATUS_ADD_RSLV      (0x00000002)
+
+/** set privacy mode */
+#define BLE_ABS_PV_STATUS_SET_MODE      (0x00000004)
+
+/** enable resolvable private address function */
+#define BLE_ABS_PV_STATUS_EN_RPA        (0x00000008)
+
+/**********************************/
+/** Define for create connection  */
+/**********************************/
+/** scan interval for connection request with 1M & 2M PHY */
+#define BLE_ABS_CONN_SC_INTV_FAST                              (0x0060)
+
+/** scan window for connection request with 1M & 2M PHY */
+#define BLE_ABS_CONN_SC_WINDOW_FAST                            (0x0030)
+
+/** scan interval for connection request with coded PHY */
+#define BLE_ABS_CONN_SC_INTV_SLOW                              (0x0180)
+
+/** scan window for connection request with coded PHY */
+#define BLE_ABS_CONN_SC_WINDOW_SLOW                            (0x0090)
+
+/** minimum advertising data length */
+#define BLE_ABS_LEGACY_ADV_DATA_LEN                            (31)
+#define BLE_ABS_CONN_EXT_ADV_DATA_LEN                          (229)
+
+/** add magic number value set */
+#define BLE_ABS_GAP_CONNECTION_CE_LENGTH                       (0xFFFF)
+#define BLE_ABS_SET_PAIRING_MAXIMUM_LTK_SIZE                   (0x10)
+#define BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF                    (0xFF)
+#define BLE_ABS_GAP_REMOTE_IRK_AA                              (0xAA)
+#define BLE_ABS_REMOTE_DEVICE_ADDRESS_55                       (0x55)
+#define BLE_ABS_GAP_EVENT_CONNECTION_TIMEOUT_1000              (1000)
+
+/*** r_ble_sec_data functions added start ***/
+#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1)
+ #define BLE_SECD_UPD_BN_ADD                                   (0x00)
+ #define BLE_SECD_UPD_BN_ADD_OVERWR                            (0x01)
+ #define BLE_SECD_UPD_BN_DEL                                   (0x02)
+ #define BLE_SECD_UPD_BN_ALL_DEL                               (0x03)
+ #define BLE_ABS_SECURE_DATA_DELETE_LOCAL_FF                   (0xFF)
+ #define BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF             (0xFF)
+ #define BLE_ABS_SECURE_DATA_REMOTE_BOND_NUMBER_FF             (0xFF)
+ #define BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF                   (0xFF)
+ #define BLE_ABS_SECURE_DATA_BOND_CHECK_FF                     (0xFF)
+#endif
+
+#if (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE != 0)
+ #define BLE_DEV_DATA_DF_ADDR                                  _BLE_DF_ADDR(BLE_CFG_DEV_DATA_DF_BLOCK)
+ #define BLE_ABS_SECURE_DATA_DF_ADDR                           _BLE_DF_ADDR(BLE_CFG_SECD_DATA_DF_BLOCK)
+#elif (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE != 0)
+ #define BLE_DEV_DATA_DF_ADDR                                  _BLE_DF_ADDR(BLE_CFG_DEV_DATA_DF_BLOCK)
+ #define BLE_ABS_SECURE_DATA_DF_ADDR                           _BLE_DF_ADDR(BLE_CFG_SECD_DATA_DF_BLOCK)
+#endif
+
+/**** RF event notify function pointer ****/
+#define BLE_EVENT_TYPE_CONN                                    (0x0000U)
+#define BLE_EVENT_TYPE_ADV                                     (0x0001U)
+#define BLE_EVENT_TYPE_SCAN                                    (0x0002U)
+#define BLE_EVENT_TYPE_INITIATOR                               (0x0003U)
+
+#define BLE_EVENT_NOTIFY_CONN_START_POS                        (0)
+#define BLE_EVENT_NOTIFY_ADV_START_POS                         (1)
+#define BLE_EVENT_NOTIFY_SCAN_START_POS                        (2)
+#define BLE_EVENT_NOTIFY_INIT_START_POS                        (3)
+#define BLE_EVENT_NOTIFY_CONN_CLOSE_POS                        (4)
+#define BLE_EVENT_NOTIFY_ADV_CLOSE_POS                         (5)
+#define BLE_EVENT_NOTIFY_SCAN_CLOSE_POS                        (6)
+#define BLE_EVENT_NOTIFY_INIT_CLOSE_POS                        (7)
+#define BLE_EVENT_NOTIFY_DS_START_POS                          (8)
+#define BLE_EVENT_NOTIFY_DS_CLOSE_POS                          (9)
+
+#define BLE_EVENT_TYPE_RF_DS_START                             (0x0U)
+#define BLE_EVENT_TYPE_RF_DS_CLOSE                             (0x1U)
+
+#define BLE_EVENT_NOTIFY_CONN_START_BIT                        (0x1U << BLE_EVENT_NOTIFY_CONN_START_POS)
+#define BLE_EVENT_NOTIFY_ADV_START_BIT                         (0x1U << BLE_EVENT_NOTIFY_ADV_START_POS)
+#define BLE_EVENT_NOTIFY_SCAN_START_BIT                        (0x1U << BLE_EVENT_NOTIFY_SCAN_START_POS)
+#define BLE_EVENT_NOTIFY_INIT_START_BIT                        (0x1U << BLE_EVENT_NOTIFY_INIT_START_POS)
+
+#define BLE_EVENT_NOTIFY_CONN_CLOSE_BIT                        (0x1U << BLE_EVENT_NOTIFY_CONN_CLOSE_POS)
+#define BLE_EVENT_NOTIFY_ADV_CLOSE_BIT                         (0x1U << BLE_EVENT_NOTIFY_ADV_CLOSE_POS)
+#define BLE_EVENT_NOTIFY_SCAN_CLOSE_BIT                        (0x1U << BLE_EVENT_NOTIFY_SCAN_CLOSE_POS)
+#define BLE_EVENT_NOTIFY_INIT_CLOSE_BIT                        (0x1U << BLE_EVENT_NOTIFY_INIT_CLOSE_POS)
+
+#define BLE_EVENT_NOTIFY_DS_START_BIT                          (0x1U << BLE_EVENT_NOTIFY_DS_START_POS)
+#define BLE_EVENT_NOTIFY_DS_CLOSE_BIT                          (0x1U << BLE_EVENT_NOTIFY_DS_CLOSE_POS)
+
+#define BLE_EVENT_NOTIFY_START_MASK                            ( \
+        (BLE_EVENT_NOTIFY_CONN_START_BIT) |                      \
+        (BLE_EVENT_NOTIFY_ADV_START_BIT) |                       \
+        (BLE_EVENT_NOTIFY_SCAN_START_BIT) |                      \
+        (BLE_EVENT_NOTIFY_INIT_START_BIT) |                      \
+        (0x0U))
+
+#define BLE_EVENT_NOTIFY_CLOSE_MASK                            ( \
+        (BLE_EVENT_NOTIFY_CONN_CLOSE_BIT) |                      \
+        (BLE_EVENT_NOTIFY_ADV_CLOSE_BIT) |                       \
+        (BLE_EVENT_NOTIFY_SCAN_CLOSE_BIT) |                      \
+        (BLE_EVENT_NOTIFY_INIT_CLOSE_BIT) |                      \
+        (0x0U))
+
+#define BLE_EVENT_NOTIFY_DS_MASK                               ( \
+        (BLE_EVENT_NOTIFY_DS_START_BIT) |                        \
+        (BLE_EVENT_NOTIFY_DS_CLOSE_BIT) |                        \
+        (0x0U))
+
+#define BLE_HOST_TBL_NUM                                       8
+
+#define BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE                  (4)
+#define BLE_ABS_SECURE_DATA_MAGIC_NUMBER                       (0x12345678)
+
+/** Internal data flash base address. */
+#define BLE_ABS_SECURE_DATA_BLOCK_BASE                         (0x40100000)
+
+#if (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE != 0)
+ #define BLE_ABS_SECURE_DATA_BLOCK_SIZE                        (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE)
+#elif (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE != 0)
+ #define BLE_ABS_SECURE_DATA_BLOCK_SIZE                        (BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE)
+#endif
+
+#define BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET              BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE
+#define BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET                 (5)
+#define BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET         (8)
+#define BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET    (12)
+#define BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET               (20)
+#define BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET             (48)
+
+#define BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE                (88)
+#define BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE                    (40)
+#define BLE_ABS_SECURE_DATA_LOCAL_INFOMATION_SIZE              (1)
+#define BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE      (7)
+#define BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE               (8)
+#define BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE          (6)
+#define BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE                   (65)
+#define BLE_ABS_SECURE_DATA_REMOTE_KEYS_INFOMATION_SIZE        (4)
+
+#define BLE_ABS_SECURE_DATA_BASE_ADDR                          (BLE_ABS_SECURE_DATA_BLOCK_BASE +           \
+                                                                (BLE_ABS_CFG_SECURE_DATA_DATAFLASH_BLOCK * \
+                                                                 BLE_ABS_SECURE_DATA_BLOCK_SIZE))
+#define BLE_ABS_SECURE_DATA_ADDR_MGN_DATA                      (BLE_ABS_SECURE_DATA_BASE_ADDR)
+#define BLE_ABS_SECURE_DATA_SEC_BOND_NUM                       (BLE_ABS_SECURE_DATA_ADDR_MGN_DATA + \
+                                                                BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE)
+#define BLE_ABS_SECURE_DATA_ADDR_LOC_AREA                      (BLE_ABS_SECURE_DATA_BASE_ADDR + \
+                                                                BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE)
+#define BLE_ABS_SECURE_DATA_ADDR_LOC_IRK                       (BLE_ABS_SECURE_DATA_ADDR_LOC_AREA)
+#define BLE_ABS_SECURE_DATA_ADDR_LOC_CSRK                      (BLE_ABS_SECURE_DATA_ADDR_LOC_IRK + BLE_GAP_IRK_SIZE)
+#define BLE_ABS_SECURE_DATA_ADDR_LOC_IDADDR                    (BLE_ABS_SECURE_DATA_ADDR_LOC_CSRK + BLE_GAP_CSRK_SIZE)
+#define BLE_ABS_SECURE_DATA_ADDR_LOC_INFO                      (BLE_ABS_SECURE_DATA_ADDR_LOC_IDADDR + \
+                                                                BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE)
+#define BLE_ABS_SECURE_DATA_ADDR_REM_START                     (BLE_ABS_SECURE_DATA_ADDR_LOC_INFO + \
+                                                                BLE_ABS_SECURE_DATA_LOCAL_INFOMATION_SIZE)
+#define BLE_ABS_SECURE_DATA_MAX_SIZE                           (BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + \
+                                                                BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE *    \
+                                                                BLE_ABS_CFG_NUMBER_BONDING)
+#define BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK                    (BLE_ABS_SECURE_DATA_BLOCK_SIZE - 1UL)
+
+/** The invalid timer handle. */
+#define BLE_TIMER_INVALID_HDL                                  (0xFF)
+
+/** add magic number value set */
+#define BLE_ABS_TIMER_REMAIN_TIMESHORTEST                      (0xFFFFFFFF)
+#define BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS                       (1000)
+#define BLE_ABS_TIMER_METRIC_PREFIX                            (1000)
+
+/***********************************************************************************************************************
+ * Local Typedef definitions
+ **********************************************************************************************************************/
+
+/***********************************************************************************************************************
+ * Private global variables and functions
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_set_pairing_parameter(ble_abs_pairing_parameter_t * p_pairing_parameter);
+static fsp_err_t ble_abs_convert_legacy_advertising_parameter(
+    ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter);
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+static fsp_err_t ble_abs_convert_extend_advertising_parameter(
+    ble_abs_extend_advertising_parameter_t * advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter);
+
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+static fsp_err_t ble_abs_convert_non_connectable_advertising_parameter(
+    ble_abs_non_connectable_advertising_parameter_t * p_non_connectable_advertising_parameter,
+    st_ble_gap_adv_param_t                          * p_gap_advertising_parameter,
+    uint8_t                                           advertising_handle);
+static fsp_err_t ble_abs_advertising_report_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                    st_ble_evt_data_t             * p_event_data);
+static fsp_err_t ble_abs_check_scan_phy_parameter(ble_abs_scan_phy_parameter_t * p_scan_phy);
+static fsp_err_t ble_abs_set_scan_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                            ble_abs_scan_parameter_t      * p_scan_parameter);
+
+static void ble_abs_gap_callback(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data);
+static void ble_abs_vendor_specific_callback(uint16_t               event_type,
+                                             ble_status_t           event_result,
+                                             st_ble_vs_evt_data_t * p_event_data);
+static void ble_abs_set_abs_callback(ble_abs_instance_ctrl_t * const            p_instance_ctrl,
+                                     ble_gap_application_callback_t             gap_callback,
+                                     ble_vendor_specific_application_callback_t vendor_specific_callback);
+static void ble_abs_set_advertising_status(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                           uint8_t                         advertising_handle,
+                                           uint32_t                        set,
+                                           uint32_t                        clear);
+static void ble_abs_set_advertising_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                              void                          * p_advertising_parameter,
+                                              uint8_t                         advertising_handle);
+static void ble_abs_cancel_connection_function(void);
+
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+static void ble_abs_advertising_to_function(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_handle);
+
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 0) */
+static void ble_abs_set_scan_status(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t set, uint32_t clear);
+static void ble_abs_update_data_status(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                       uint32_t                        advertising_status,
+                                       uint8_t                       * p_advertising_data,
+                                       uint16_t                        advertising_data_len,
+                                       uint8_t                         advertising_handle);
+static void ble_abs_connection_indication_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void ble_abs_scan_to_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void ble_abs_loc_ver_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl, st_ble_evt_data_t * p_event_data);
+static void ble_abs_advertising_parameter_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                      st_ble_evt_data_t             * p_event_data);
+static void ble_abs_advertising_data_set_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                 st_ble_evt_data_t             * p_event_data);
+static void ble_abs_periodic_parameter_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void ble_abs_advertising_off_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                            st_ble_evt_data_t             * p_event_data);
+static void ble_abs_conflict_resolving_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                               st_ble_evt_data_t             * p_event_data);
+static void ble_abs_random_handler(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                   st_ble_vs_evt_data_t          * p_event_data);
+static void ble_abs_set_irk_to_resolving_list(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t * p_lc_irk);
+static void ble_abs_advertising_start(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle);
+static void ble_abs_advertising_set_data(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                         uint8_t                         advertising_handle,
+                                         uint8_t                         data_type);
+static void ble_abs_set_legacy_scan_response_data(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void ble_abs_convert_scan_phy_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                               ble_abs_scan_phy_parameter_t  * p_abs_phy,
+                                               ble_gap_scan_phy_parameter_t  * p_gap_phy,
+                                               ble_gap_scan_on_t             * p_scan_enable);
+static void ble_abs_set_connection_parameter(ble_abs_connection_phy_parameter_t * p_abs_connection_parameter,
+                                             ble_gap_connection_phy_parameter_t * p_connection_phy_parameter,
+                                             ble_gap_connection_parameter_t     * p_connection_parameter);
+static void ble_abs_convert_scan_parameter(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                           st_ble_gap_scan_param_t       * p_scan_parameter,
+                                           ble_gap_scan_on_t             * p_scan_enable,
+                                           uint32_t                        status);
+static void ble_abs_set_connection_advertising_interval(st_ble_gap_adv_param_t * p_advertising_parameter,
+                                                        uint32_t                 fast_advertising_interval,
+                                                        uint32_t                 slow_advertising_interval,
+                                                        uint16_t                 fast_period);
+
+/*** ble secure data functions start ***/
+
+static fsp_err_t ble_abs_secure_data_writelocinfo(flash_instance_t const * p_instance,
+                                                  ble_device_address_t   * p_lc_id_addr,
+                                                  uint8_t                * p_lc_irk,
+                                                  uint8_t                * p_lc_csrk);
+static fsp_err_t ble_abs_secure_data_readlocinfo(flash_instance_t const * p_instance,
+                                                 ble_device_address_t   * p_lc_id_addr,
+                                                 uint8_t                * p_lc_irk,
+                                                 uint8_t                * p_lc_csrk);
+static void      ble_abs_secure_data_recvremkeys(ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys);
+static fsp_err_t ble_abs_secure_data_writeremkeys(flash_instance_t const * p_instance,
+                                                  ble_device_address_t   * p_addr,
+                                                  st_ble_gap_auth_info_t * p_keyinfo);
+static fsp_err_t ble_abs_secure_data_init(flash_instance_t const * p_instance);
+
+#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1)
+
+static st_ble_gap_key_ex_param_t gs_key_ex_param;
+static st_ble_gap_key_dist_t     gs_key_dist;
+
+static const ble_device_address_t invalid_rem_addr =
+{
+    .addr = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
+    .type = 0xFF
+};
+
+static fsp_err_t ble_abs_secure_data_find_entry(ble_device_address_t * p_dev_addr,
+                                                int32_t              * p_entry,
+                                                uint8_t              * p_sec_data);
+static void      ble_abs_secure_data_find_oldest_entry(flash_instance_t const * p_instance, int32_t * p_entry);
+static fsp_err_t ble_abs_secure_data_update_bond_num(flash_instance_t const * p_instance,
+                                                     int32_t                  entry,
+                                                     int32_t                  op_code,
+                                                     uint8_t                * p_alloc_bond_num,
+                                                     uint8_t                * p_sec_data);
+static void ble_abs_secure_data_update_bond_order(flash_instance_t const * p_instance,
+                                                  int32_t                  entry,
+                                                  uint8_t                * p_sec_data,
+                                                  uint8_t                  bond_order);
+static fsp_err_t ble_abs_secure_data_is_valid_entry(flash_instance_t const * p_instance, int32_t entry);
+static fsp_err_t ble_abs_secure_data_read_bond_info(flash_instance_t const * p_instance,
+                                                    uint8_t                * p_out_bond_num,
+                                                    uint8_t               ** pp_sec_data,
+                                                    st_ble_gap_bond_info_t * p_bond_info);
+static void ble_abs_secure_data_release_bond_info_buf(uint8_t * p_sec_data);
+
+#endif
+static fsp_err_t ble_abs_secure_data_flash_read(flash_instance_t const * p_instance,
+                                                uint32_t                 addr,
+                                                uint8_t                * buff,
+                                                uint16_t                 len);
+static fsp_err_t ble_abs_secure_data_flash_write(flash_instance_t const * p_instance,
+                                                 uint32_t                 addr,
+                                                 uint8_t                * buff,
+                                                 uint16_t                 len);
+
+uint8_t r_dflash_read(uint32_t addr, uint8_t * buff, uint16_t len);
+uint8_t r_dflash_write(uint32_t addr, uint8_t * buff, uint16_t len);
+
+/*** ble secure data functions end ***/
+
+/*** platform control functions added start ***/
+
+void    r_ble_rf_control_error(uint32_t err_no);
+uint8_t r_ble_rf_power_save_mode(void);
+
+#if (BSP_CFG_RTOS == 2)
+void r_ble_wake_up_task(void * EventGroupHandle);
+void r_ble_wake_up_task_from_isr(void * EventGroupHandle);
+
+#endif
+
+/*** platform control functions end ***/
+
+/*** ble timer functions start ***/
+static void      ble_abs_timer_update_remaining_time_ms(ble_abs_instance_ctrl_t * const p_instance_ctrl, bool expired);
+static uint32_t  ble_abs_timer_alloc_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void      ble_abs_timer_free_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl);
+static void      ble_abs_timer_start_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void      ble_abs_timer_stop_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void      ble_abs_timer_add_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl);
+static void      ble_abs_timer_remove_timer(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl);
+static void      ble_abs_timer_event_cb(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+void             ble_abs_timer_process_timer_expire(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void      ble_abs_timer_init(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static void      ble_abs_timer_terminate(ble_abs_instance_ctrl_t * const p_instance_ctrl);
+static fsp_err_t ble_abs_timer_create(ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                      uint32_t                      * p_timer_hdl,
+                                      uint32_t                        timeout_ms,
+                                      uint8_t                         type,
+                                      ble_abs_timer_cb_t              cb);
+static fsp_err_t ble_abs_timer_delete(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t * p_timer_hdl);
+static fsp_err_t ble_abs_timer_start(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl);
+static fsp_err_t ble_abs_timer_stop(ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl);
+static void      ble_abs_init_hw_timer(timer_instance_t const * p_instance);
+static void      ble_abs_terminate_hw_timer(timer_instance_t const * p_instance);
+static void      ble_abs_start_hw_timer(timer_instance_t const * p_instance,
+                                        uint32_t               * current_timeout_ms,
+                                        uint32_t               * elapsed_timeout_ms,
+                                        uint32_t                 timeout_ms);
+static void ble_abs_stop_hw_timer(timer_instance_t const * p_instance,
+                                  uint32_t               * current_timeout_ms,
+                                  uint32_t               * elapsed_timeout_ms);
+static uint32_t ble_abs_get_elapsed_time_ms(timer_instance_t const * p_instance,
+                                            bool                     expired,
+                                            const uint32_t           current_timeout_ms,
+                                            uint32_t               * elapsed_timeout_ms);
+void ble_abs_hw_timer_callback(timer_callback_args_t * callback_args);
+
+/*** ble timer functions end ***/
+
+/* Version data structure. */
+static const fsp_version_t g_ble_abs_version =
+{
+    .api_version_minor  = BLE_ABS_API_VERSION_MINOR,
+    .api_version_major  = BLE_ABS_API_VERSION_MAJOR,
+    .code_version_minor = BLE_ABS_CODE_VERSION_MINOR,
+    .code_version_major = BLE_ABS_CODE_VERSION_MAJOR
+};
+
+/** BLE ABS on BLE HAL API mapping for BLE ABS interface */
+const ble_abs_api_t g_ble_abs_on_ble =
+{
+    .open                           = RM_BLE_ABS_Open,
+    .close                          = RM_BLE_ABS_Close,
+    .reset                          = RM_BLE_ABS_Reset,
+    .versionGet                     = RM_BLE_ABS_VersionGet,
+    .startLegacyAdvertising         = RM_BLE_ABS_StartLegacyAdvertising,
+    .startExtendedAdvertising       = RM_BLE_ABS_StartExtendedAdvertising,
+    .startNonConnectableAdvertising = RM_BLE_ABS_StartNonConnectableAdvertising,
+    .startPeriodicAdvertising       = RM_BLE_ABS_StartPeriodicAdvertising,
+    .startScanning                  = RM_BLE_ABS_StartScanning,
+    .createConnection               = RM_BLE_ABS_CreateConnection,
+    .setLocalPrivacy                = RM_BLE_ABS_SetLocalPrivacy,
+    .startAuthentication            = RM_BLE_ABS_StartAuthentication,
+};
+
+static ble_abs_instance_ctrl_t * gp_instance_ctrl;
+
+/***********************************************************************************************************************
+ * Exported global functions
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * Host stack is initialized with this function. Before using All the R_BLE APIs,
+ * it's necessary to call this function. A callback functions are registered with this function.
+ * In order to receive the GAP, GATT, Vendor specific event,
+ * it's necessary to register a callback function.
+ * The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event.
+ * Implements @ref ble_abs_api_t::open.
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_Open
+ *
+ * @retval FSP_SUCCESS                                 Channel opened successfully.
+ * @retval FSP_ERR_ASSERTION                           Null pointer presented.
+ * @retval FSP_ERR_INVALID_CHANNEL                     The channel number is invalid.
+ * @retval FSP_ERR_ALREADY_OPEN                        Requested channel is already open in a different configuration.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Invalid input parameter.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Open (ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg)
+{
+    int32_t      i;
+    fsp_err_t    err        = FSP_SUCCESS;
+    ble_status_t ble_status = BLE_SUCCESS;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ASSERT(p_cfg);
+
+    FSP_ASSERT(p_cfg->gap_callback);
+    FSP_ERROR_RETURN(0 == p_cfg->channel, FSP_ERR_INVALID_CHANNEL);
+#endif
+    FSP_ERROR_RETURN(BLE_ABS_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
+
+    gp_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    (*p_instance_ctrl).abs_gap_callback             = NULL;
+    (*p_instance_ctrl).abs_vendor_specific_callback = NULL;
+    (*p_instance_ctrl).privacy_mode                 = BLE_GAP_NET_PRIV_MODE;
+    (*p_instance_ctrl).set_privacy_status           = 0;
+    (*p_instance_ctrl).p_cfg = p_cfg;
+
+    R_BLE_Open();
+
+    /* check pairing parameter */
+    err = ble_abs_set_pairing_parameter(p_cfg->p_pairing_parameter);
+    FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_INVALID_ARGUMENT);
+
+    /* initialize GAP layer */
+    ble_status = R_BLE_GAP_Init(ble_abs_gap_callback);
+    FSP_ERROR_RETURN(BLE_SUCCESS == ble_status, FSP_ERR_INVALID_ARGUMENT);
+
+    for (i = 0; i < BLE_MAX_NO_OF_ADV_SETS_SUPPORTED; i++)
+    {
+        p_instance_ctrl->advertising_sets[i].advertising_status = 0;
+    }
+
+    p_instance_ctrl->abs_scan.scan_status      = 0;
+    (*p_instance_ctrl).connection_timer_handle = BLE_TIMER_INVALID_HDL;
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+    (*p_instance_ctrl).advertising_timer_handle = BLE_TIMER_INVALID_HDL;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 0) */
+    (*p_instance_ctrl).set_privacy_status = 0;
+
+    /* set pairing parameter */
+    ble_abs_set_pairing_parameter(p_cfg->p_pairing_parameter);
+    ble_abs_set_abs_callback(p_instance_ctrl, p_cfg->gap_callback, p_cfg->vendor_specific_callback);
+
+    if ((0 < p_cfg->gatt_server_callback_list_number) && (NULL != p_cfg->p_gatt_server_callback_list))
+    {
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTS_Init(p_cfg->gatt_server_callback_list_number),
+                         FSP_ERR_INVALID_ARGUMENT);
+
+        for (i = 0; i < p_cfg->gatt_server_callback_list_number; i++)
+        {
+            if (NULL != p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_function)
+            {
+                FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTS_RegisterCb(
+                                     p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_function,
+                                     p_cfg->p_gatt_server_callback_list[i].gatt_server_callback_priority
+                                     ),
+                                 FSP_ERR_INVALID_ARGUMENT);
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+
+#if (BLE_CFG_LIBRARY_TYPE != 2)
+    if ((0 < p_cfg->gatt_client_callback_list_number) && (NULL != p_cfg->p_gatt_client_callback_list))
+    {
+        FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTC_Init(p_cfg->gatt_client_callback_list_number),
+                         FSP_ERR_INVALID_ARGUMENT);
+
+        for (i = 0; i < p_cfg->gatt_client_callback_list_number; i++)
+        {
+            if (NULL != p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_function)
+            {
+                FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_GATTC_RegisterCb(
+                                     p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_function,
+                                     p_cfg->p_gatt_client_callback_list[i].gatt_client_callback_priority),
+                                 FSP_ERR_INVALID_ARGUMENT);
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 2) */
+
+    FSP_ERROR_RETURN(BLE_SUCCESS == R_BLE_VS_Init(ble_abs_vendor_specific_callback), FSP_ERR_INVALID_ARGUMENT);
+
+    ble_abs_timer_init(p_instance_ctrl);
+
+    p_instance_ctrl->open = BLE_ABS_OPEN;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_Open() */
+
+/*******************************************************************************************************************//**
+ * @brief Close the BLE channel.
+ * Implements @ref ble_abs_api_t::close.
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_Close
+ *
+ * @retval  FSP_SUCCESS              Channel closed successfully.
+ * @retval  FSP_ERR_ASSERTION        Null pointer presented.
+ * @retval  FSP_ERR_NOT_OPEN         Control block not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Close (ble_abs_ctrl_t * const p_ctrl)
+{
+    ble_abs_instance_ctrl_t * p_ble_abs_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ble_abs_ctrl);
+#endif
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_ble_abs_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    R_BLE_Close();
+
+    R_BLE_GAP_Terminate();
+
+    ble_abs_timer_terminate(p_ble_abs_ctrl);
+
+    p_ble_abs_ctrl->open = 0;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_Close() */
+
+/*******************************************************************************************************************//**
+ * BLE is reset with this function.  The process is carried out in the following order.
+ * R_BLE_Close() -> R_BLE_GAP_Terminate() -> R_BLE_Open() -> R_BLE_SetEvent().
+ * The init_cb callback initializes the others (Host Stack, timer, etc...).
+ * Implements @ref ble_abs_api_t::reset.
+ *
+ * @retval  FSP_SUCCESS              Channel closed successfully.
+ * @retval  FSP_ERR_ASSERTION        Null pointer presented.
+ * @retval  FSP_ERR_NOT_OPEN         Control block not open.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_Reset (ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback)
+{
+    ble_abs_instance_ctrl_t * p_ble_abs_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_ble_abs_ctrl);
+#endif
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_ble_abs_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    R_BLE_Close();
+
+    R_BLE_GAP_Terminate();
+
+    R_BLE_Open();
+
+    if (NULL != init_callback)
+    {
+        R_BLE_SetEvent(init_callback);
+    }
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Get BLE module code and API versions.
+ * Implements @ref ble_abs_api_t::versionGet.
+ *
+ * @retval      FSP_SUCCESS            Operation succeeded.
+ * @retval      FSP_ERR_ASSERTION      The parameter p_version is NULL.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_VersionGet (fsp_version_t * const p_version)
+{
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_version);
+#endif
+
+    p_version->version_id = g_ble_abs_version.version_id;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_VersionGet() */
+
+/*******************************************************************************************************************//**
+ * Start Legacy Advertising after setting advertising parameters, advertising data and scan response data.
+ * The legacy advertising uses the advertising set whose advertising handle is 0.
+ * The advertising type is connectable and scannable(ADV_IND).
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Implements @ref ble_abs_api_t::startLegacyAdvertising
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartLegacyAdvertising
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_STATE                       Host stack hasn't been initialized.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartLegacyAdvertising (ble_abs_ctrl_t * const                               p_ctrl,
+                                             ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter)
+{
+    st_ble_gap_adv_param_t    advertising_parameter;
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    uint8_t advertising_handle = BLE_ABS_LEGACY_HDL;
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    uint8_t advertising_handle = BLE_ABS_COMMON_HDL;
+#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+#endif
+
+    /** status check */
+    FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status &
+                           (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)),
+                     FSP_ERR_INVALID_STATE);
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   advertising_handle,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW));
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   advertising_handle,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW |
+                                    BLE_ABS_ADV_COMM_LEG | BLE_ABS_ADV_COMM_NON));
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_convert_legacy_advertising_parameter((ble_abs_legacy_advertising_parameter_t *)
+                                                                  p_advertising_parameter,
+                                                                  &advertising_parameter),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    /** check data length */
+    FSP_ERROR_RETURN((BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->advertising_data_length) &&
+                     (BLE_ABS_LEGACY_ADV_DATA_LEN >= p_advertising_parameter->scan_response_data_length),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    ble_abs_set_connection_advertising_interval(&advertising_parameter,
+                                                p_advertising_parameter->fast_advertising_interval,
+                                                p_advertising_parameter->slow_advertising_interval,
+                                                p_advertising_parameter->fast_advertising_period); ///< check advertising interval
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_ADV_DATA,
+                               p_advertising_parameter->p_advertising_data,
+                               p_advertising_parameter->advertising_data_length,
+                               advertising_handle); ///< advertising data update check
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_SRES_DATA,
+                               p_advertising_parameter->p_scan_response_data,
+                               p_advertising_parameter->scan_response_data_length,
+                               advertising_handle); ///< scan response data update check
+
+    ble_abs_set_advertising_parameter(p_instance_ctrl,
+                                      (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter,
+                                      BLE_ABS_LEGACY_HDL);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    uint32_t status =
+        p_advertising_parameter->fast_advertising_period ? BLE_ABS_ADV_STATUS_PARAM_FAST : BLE_ABS_ADV_STATUS_PARAM_SLOW;
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    uint32_t status =
+        p_advertising_parameter->fast_advertising_period ? (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_COMM_LEG) :
+        (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_COMM_LEG);
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_StartLegacyAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Extended Advertising after setting advertising parameters, advertising data.
+ * The extended advertising uses the advertising set whose advertising handle is 1.
+ * The advertising type is connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Implements @ref ble_abs_api_t::startExtendedAdvertising
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_STATE                       Host stack hasn't been initialized.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ * @retval FSP_ERR_UNSUPPORTED                         Subordinate modules do not support this feature.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartExtendedAdvertising (ble_abs_ctrl_t * const                               p_ctrl,
+                                               ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter)
+{
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    st_ble_gap_adv_param_t advertising_parameter;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+ #if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+ #endif
+
+    /** status check */
+    FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status &
+                           (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)),
+                     FSP_ERR_INVALID_STATE);
+
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   BLE_ABS_EXT_HDL,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW));
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_convert_extend_advertising_parameter((ble_abs_extend_advertising_parameter_t *)
+                                                                  p_advertising_parameter,
+                                                                  &advertising_parameter),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    FSP_ERROR_RETURN(BLE_ABS_CONN_EXT_ADV_DATA_LEN >= p_advertising_parameter->advertising_data_length,
+                     FSP_ERR_INVALID_ARGUMENT); ///< check data length
+
+    ble_abs_set_connection_advertising_interval(&advertising_parameter,
+                                                p_advertising_parameter->fast_advertising_interval,
+                                                p_advertising_parameter->slow_advertising_interval,
+                                                p_advertising_parameter->fast_advertising_period); ///< check advertising interval
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_ADV_DATA,
+                               p_advertising_parameter->p_advertising_data,
+                               p_advertising_parameter->advertising_data_length,
+                               BLE_ABS_EXT_HDL); ///< data update check
+
+    ble_abs_set_advertising_parameter(p_instance_ctrl,
+                                      (ble_abs_extend_advertising_parameter_t *) p_advertising_parameter,
+                                      BLE_ABS_EXT_HDL);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+    uint32_t status =
+        p_advertising_parameter->fast_advertising_period ? BLE_ABS_ADV_STATUS_PARAM_FAST : BLE_ABS_ADV_STATUS_PARAM_SLOW;
+    ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_EXT_HDL, status, 0);
+
+    return FSP_SUCCESS;
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    return FSP_ERR_UNSUPPORTED;
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+}                                      /* End of function RM_BLE_ABS_StartExtendedAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Non-Connectable Advertising after setting advertising parameters, advertising data.
+ * The non-connectable advertising uses the advertising set whose advertising handle is 2.
+ * The advertising type is non-connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Secondary Advertising Max Skip is 0.
+ * Implements @ref ble_abs_api_t::startNonConnectableAdvertising.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_STATE                       Host stack hasn't been initialized.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartNonConnectableAdvertising (
+    ble_abs_ctrl_t * const                                        p_ctrl,
+    ble_abs_non_connectable_advertising_parameter_t const * const p_advertising_parameter)
+{
+    st_ble_gap_adv_param_t advertising_parameter;
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    uint8_t advertising_handle = BLE_ABS_NON_CONN_HDL;
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    uint8_t advertising_handle = BLE_ABS_COMMON_HDL;
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#endif
+
+    /** status check */
+    FSP_ERROR_RETURN(0 == (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status &
+                           (BLE_ABS_ADV_STATUS_ADV_FAST_START | BLE_ABS_ADV_STATUS_ADV_SLOW_START)),
+                     FSP_ERR_INVALID_STATE);
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0, BLE_ABS_ADV_STATUS_PARAM_SLOW);
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   advertising_handle,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_SLOW |
+                                    BLE_ABS_ADV_COMM_LEG | BLE_ABS_ADV_COMM_NON));
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_convert_non_connectable_advertising_parameter((
+                                                                               ble_abs_non_connectable_advertising_parameter_t
+                                                                               *)
+                                                                           p_advertising_parameter,
+                                                                           &advertising_parameter,
+                                                                           advertising_handle),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    advertising_parameter.adv_intv_min = p_advertising_parameter->advertising_interval;
+    advertising_parameter.adv_intv_max = p_advertising_parameter->advertising_interval;
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_ADV_DATA,
+                               p_advertising_parameter->p_advertising_data,
+                               p_advertising_parameter->advertising_data_length,
+                               advertising_handle); ///< data update check
+
+    ble_abs_set_advertising_parameter(p_instance_ctrl,
+                                      (ble_abs_non_connectable_advertising_parameter_t *) p_advertising_parameter,
+                                      BLE_ABS_NON_CONN_HDL);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0);
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   advertising_handle,
+                                   (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_COMM_NON),
+                                   0);
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    return FSP_SUCCESS;
+} /* End of function RM_BLE_ABS_StartNonConnectableAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start Periodic Advertising after setting advertising parameters, periodic advertising parameters,
+ * advertising data and periodic advertising data.
+ * The periodic advertising uses the advertising set whose advertising handle is 3.
+ * The advertising type is non-connectable and non-scannable.
+ * The address type of local device is Public Identity Address or
+ * RPA(If the resolving list contains no matching entry, use the public address.).
+ * Scan request event(BLE_GAP_EVENT_SCAN_REQ_RECV) is not notified.
+ * Secondary Advertising Max Skip is 0.
+ * Implements @ref ble_abs_api_t::startPeriodicAdvertising
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_advertising_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ * @retval FSP_ERR_UNSUPPORTED                         Subordinate modules do not support this feature.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartPeriodicAdvertising (ble_abs_ctrl_t * const                                 p_ctrl,
+                                               ble_abs_periodic_advertising_parameter_t const * const p_advertising_parameter)
+{
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    st_ble_gap_adv_param_t advertising_parameter;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+ #if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(NULL != p_advertising_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+ #endif
+
+    /** status check */
+    FSP_ASSERT(!(p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status &
+                 (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_PERD_START)));
+
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   BLE_ABS_PERD_HDL,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_PARAM_SLOW | BLE_ABS_ADV_STATUS_PERD_PARAM));
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_convert_non_connectable_advertising_parameter((
+                                                                               ble_abs_non_connectable_advertising_parameter_t
+                                                                               *) (&
+                                                                                   p_advertising_parameter
+                                                                                   ->
+                                                                                   advertising_parameter),
+                                                                           &advertising_parameter,
+                                                                           BLE_ABS_PERD_HDL),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    advertising_parameter.adv_intv_min = p_advertising_parameter->advertising_parameter.advertising_interval;
+    advertising_parameter.adv_intv_max = p_advertising_parameter->advertising_parameter.advertising_interval;
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_ADV_DATA,
+                               p_advertising_parameter->advertising_parameter.p_advertising_data,
+                               p_advertising_parameter->advertising_parameter.advertising_data_length,
+                               BLE_ABS_PERD_HDL); ///< advertising data update check
+
+    ble_abs_update_data_status(p_instance_ctrl,
+                               BLE_ABS_ADV_STATUS_PERD_DATA,
+                               p_advertising_parameter->p_periodic_advertising_data,
+                               p_advertising_parameter->periodic_advertising_data_length,
+                               BLE_ABS_PERD_HDL); ///< periodic advertising data update check
+
+    ble_abs_set_advertising_parameter(p_instance_ctrl,
+                                      (ble_abs_periodic_advertising_parameter_t *) p_advertising_parameter,
+                                      BLE_ABS_PERD_HDL);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetAdvParam(&advertising_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+    ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0);
+
+    return FSP_SUCCESS;
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    return FSP_ERR_UNSUPPORTED;
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+}                                      /* End of function RM_BLE_ABS_StartPeriodicAdvertising() */
+
+/*******************************************************************************************************************//**
+ * Start scanning after setting scan parameters.
+ * The scanner address type is Public Identity Address.
+ * Fast scan is followed by slow scan.
+ * The end of fast scan or slow scan is notified with BLE_GAP_EVENT_SCAN_TO event.
+ * If fast_period is 0, only slow scan is carried out.
+ * If scan_period is 0, slow scan continues.
+ * Implements @ref ble_abs_api_t::startScanning.
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartScanning
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_scan_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The scan parameter is out of range.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartScanning (ble_abs_ctrl_t * const                 p_ctrl,
+                                    ble_abs_scan_parameter_t const * const p_scan_parameter)
+{
+    st_ble_gap_scan_param_t     gap_scan_parameter;
+    st_ble_gap_scan_phy_param_t phy_parameter_1M;
+    st_ble_gap_scan_phy_param_t phy_parameter_coded;
+    ble_gap_scan_on_t           gap_scan_enable;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_scan_parameter, FSP_ERR_INVALID_POINTER);
+#endif
+
+    gap_scan_parameter.p_phy_param_1M    = p_scan_parameter->p_phy_parameter_1M ? &phy_parameter_1M : NULL;       ///< set scan phy parameter for 1M
+    gap_scan_parameter.p_phy_param_coded = p_scan_parameter->p_phy_parameter_coded ? &phy_parameter_coded : NULL; ///< set scan phy parameter for coded
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_set_scan_parameter(p_instance_ctrl, (ble_abs_scan_parameter_t *) p_scan_parameter),
+                     FSP_ERR_INVALID_ARGUMENT);                                                                   ///< scan parameter check
+
+    ble_abs_convert_scan_parameter(p_instance_ctrl,
+                                   &gap_scan_parameter,
+                                   &gap_scan_enable,
+                                   BLE_ABS_SCAN_STATUS_FAST_START);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_StartScan(&gap_scan_parameter,
+                                                        (st_ble_gap_scan_on_t *) (&gap_scan_enable)),
+                     FSP_ERR_INVALID_ARGUMENT);
+    if (0 == p_scan_parameter->fast_scan_period)
+    {
+        ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_SLOW_START, 0);
+    }
+    else
+    {
+        ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_FAST_START, 0);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_StartScanning() */
+
+/*******************************************************************************************************************//**
+ * Generate a IRK, add it to the resolving list, set privacy mode and enable RPA function.
+ * Register vendor specific callback function, if IRK is generated by this function.
+ * After configuring local device privacy,
+ * BLE_GAP_ADDR_RPA_ID_PUBLIC is specified as own device address
+ * in theadvertising/scan/create connection API.
+ * Implements @ref ble_abs_api_t::setLocalPrivacy
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_SetLocalPrivacy
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The privacy_mode parameter is out of range.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Host stack hasn't been initialized.
+ *                                                     configuring the resolving list or privacy mode.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_SetLocalPrivacy (ble_abs_ctrl_t * const p_ctrl,
+                                      uint8_t const * const  p_lc_irk,
+                                      uint8_t                privacy_mode)
+{
+    ble_status_t ble_status = BLE_SUCCESS;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(BLE_GAP_DEV_PRIV_MODE >= privacy_mode, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    if (NULL == p_lc_irk)
+    {
+        ble_status = R_BLE_VS_GetRand(BLE_GAP_IRK_SIZE);
+        p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == ble_status) ? BLE_ABS_PV_STATUS_CREATE_IRK : 0;
+    }
+    else
+    {
+        ble_abs_set_irk_to_resolving_list(p_instance_ctrl, (uint8_t *) p_lc_irk);
+        FSP_ERROR_RETURN(0 != p_instance_ctrl->set_privacy_status, FSP_ERR_BLE_ABS_INVALID_OPERATION);
+    }
+
+    p_instance_ctrl->privacy_mode = privacy_mode;
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_SetLocalPrivacy() */
+
+/*******************************************************************************************************************//**
+ * Request create connection.
+ * The initiator address type is Public Identity Address.
+ * The scan interval is 60ms and the scan window is 30ms in case of 1M PHY or 2M PHY.
+ * The scan interval is 180ms and the scan window is 90ms in case of coded PHY.
+ * The Minimum CE Length and the Maximum CE Length are 0xFFFF.
+ * When the request for a connection has been received by the Controller,
+ * BLE_GAP_EVENT_CREATE_CONN_COMP event is notified.
+ * When a link has beens established, BLE_GAP_EVENT_CONN_IND event is notified.
+ * Implements @ref ble_abs_api_t::createConnection.
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_CreateConnection
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl is specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_POINTER                     p_connection_parameter is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The create connection parameter is out of range.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                   Couldn't find a valid timer.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Invalid operation for the selected timer.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_CreateConnection (ble_abs_ctrl_t * const                       p_ctrl,
+                                       ble_abs_connection_parameter_t const * const p_connection_parameter)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+    FSP_ERROR_RETURN(NULL != p_connection_parameter, FSP_ERR_INVALID_POINTER);
+    FSP_ERROR_RETURN(10 >= p_connection_parameter->connection_timeout, FSP_ERR_INVALID_ARGUMENT);
+#endif
+
+    st_ble_gap_create_conn_param_t connection_parameter;
+    fsp_err_t ret = FSP_SUCCESS;
+    connection_parameter.init_filter_policy = p_connection_parameter->filter_parameter;
+    connection_parameter.own_addr_type      = BLE_GAP_ADDR_PUBLIC;
+
+    if (BLE_GAP_INIT_FILT_USE_ADDR == p_connection_parameter->filter_parameter)
+    {
+        memcpy(connection_parameter.remote_bd_addr, p_connection_parameter->p_device_address->addr, BLE_BD_ADDR_LEN);
+        connection_parameter.remote_bd_addr_type = p_connection_parameter->p_device_address->type;
+    }
+    else
+    {
+        connection_parameter.remote_bd_addr_type = BLE_GAP_ADDR_PUBLIC;
+    }
+
+    /** set connection parameters for 1M */
+    ble_gap_connection_parameter_t     connection_parameter_1M;    ///< connection parameter for 1M
+    ble_gap_connection_phy_parameter_t connection_phy_1M;          ///< connection phy for 1M
+    ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_1M,
+                                     &connection_phy_1M,
+                                     &connection_parameter_1M);    ///< select connection parameters for 1M
+    connection_parameter.p_conn_param_1M =
+        p_connection_parameter->p_connection_phy_parameter_1M ? (st_ble_gap_conn_phy_param_t *) (&connection_phy_1M) :
+        NULL;                                                      ///< set connection parameters for 1M
+
+    /** set connection parameters for 2M */
+    ble_gap_connection_parameter_t     connection_parameter_2M;    ///< connection parameter for 2M
+    ble_gap_connection_phy_parameter_t connection_phy_2M;          ///< connection phy for 2M
+    ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_2M,
+                                     &connection_phy_2M,
+                                     &connection_parameter_2M);    ///< select connection parameters for 2M
+    connection_parameter.p_conn_param_2M =
+        p_connection_parameter->p_connection_phy_parameter_2M ? (st_ble_gap_conn_phy_param_t *) (&connection_phy_2M) :
+        NULL;                                                      ///< set connection parameters for 2M
+
+    /** set connection parameters for coded */
+    ble_gap_connection_parameter_t     connection_parameter_coded; ///< connection parameter for coded
+    ble_gap_connection_phy_parameter_t connection_phy_coded;       ///< connection phy for coded
+    ble_abs_set_connection_parameter(p_connection_parameter->p_connection_phy_parameter_coded,
+                                     &connection_phy_coded,
+                                     &connection_parameter_coded); ///< select connection parameters for coded
+    connection_parameter.p_conn_param_coded =
+        p_connection_parameter->p_connection_phy_parameter_coded ? (st_ble_gap_conn_phy_param_t *) (&
+                                                                                                    connection_phy_coded)
+        :
+        NULL;                          ///< set connection parameters for coded
+    if (NULL != p_connection_parameter->p_connection_phy_parameter_coded)
+    {
+        connection_phy_coded.scan_intv   = BLE_ABS_CONN_SC_INTV_SLOW;
+        connection_phy_coded.scan_window = BLE_ABS_CONN_SC_WINDOW_SLOW;
+    }
+
+    /** create timer for cancel */
+    if (0 != p_connection_parameter->connection_timeout)
+    {
+        ble_abs_timer_create(p_instance_ctrl,
+                             &p_instance_ctrl->connection_timer_handle,
+                             (uint32_t) (p_connection_parameter->connection_timeout *
+                                         BLE_ABS_GAP_EVENT_CONNECTION_TIMEOUT_1000),
+                             BLE_TIMER_ONE_SHOT,
+                             (ble_abs_timer_cb_t) ble_abs_cancel_connection_function);
+    }
+
+    ble_status_t retval = BLE_SUCCESS;
+    retval = R_BLE_GAP_CreateConn(&connection_parameter); ///< create connection
+    if (0 != p_connection_parameter->connection_timeout)
+    {
+        if (BLE_SUCCESS == retval)
+        {
+            ret = ble_abs_timer_start(p_instance_ctrl, p_instance_ctrl->connection_timer_handle);
+        }
+        else
+        {
+            ret = ble_abs_timer_delete(p_instance_ctrl, &p_instance_ctrl->connection_timer_handle);
+        }
+    }
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == ret, ret);
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_CreateConnection() */
+
+/*******************************************************************************************************************//**
+ * Start pairing or encryption. If pairing has been done, start encryption.
+ * The pairing parameters are configured by RM_BLE_ABS_Open() or R_BLE_GAP_SetPairingParams().
+ * If the pairing parameters are configure by RM_BLE_ABS_Open(),
+ *    - bonding policy is that bonding information is stored.
+ *    - Key press notification is not supported.
+ * Implements @ref ble_abs_api_t::startAuthentication.
+ *
+ * Example:
+ * @snippet rm_ble_abs_example.c RM_BLE_ABS_StartAuthentication
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           p_instance_ctrl or connection_handle are specified as NULL.
+ * @retval FSP_ERR_NOT_OPEN                            Control block not open.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The connection handle parameter is out of range.
+ **********************************************************************************************************************/
+fsp_err_t RM_BLE_ABS_StartAuthentication (ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle)
+{
+    st_ble_gap_auth_info_t security_information;
+    ble_status_t           retval;
+
+    ble_abs_instance_ctrl_t * p_instance_ctrl = (ble_abs_instance_ctrl_t *) p_ctrl;
+
+    /* Parameter checking */
+#if BLE_ABS_CFG_PARAM_CHECKING_ENABLE
+
+    /* Verify the pointers are valid */
+    FSP_ASSERT(p_instance_ctrl);
+    FSP_ERROR_RETURN(BLE_ABS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+#else
+    FSP_PARAMETER_NOT_USED(p_instance_ctrl);
+#endif
+
+    retval = R_BLE_GAP_GetDevSecInfo(connection_handle, &security_information); ///< check security information
+    if (BLE_SUCCESS == retval)
+    {
+        retval = R_BLE_GAP_StartEnc(connection_handle);
+    }
+    else
+    {
+        retval = R_BLE_GAP_StartPairing(connection_handle);
+    }
+
+    FSP_ERROR_RETURN(BLE_ERR_INVALID_HDL != retval, FSP_ERR_INVALID_ARGUMENT);
+
+    return FSP_SUCCESS;
+}                                      /* End of function RM_BLE_ABS_StartAuthentication() */
+
+/************************************************
+ *   static function definitions                *
+ ***********************************************/
+
+/*******************************************************************************************************************//**
+ * Set Abstraction API connection parameters to GAP connection parameters.
+ **********************************************************************************************************************/
+static void ble_abs_set_connection_parameter (ble_abs_connection_phy_parameter_t * p_abs_connection_parameter,
+                                              ble_gap_connection_phy_parameter_t * p_connection_phy_parameter,
+                                              ble_gap_connection_parameter_t     * p_connection_parameter)
+{
+    if (NULL != p_abs_connection_parameter)
+    {
+        p_connection_parameter->conn_intv_min    = p_abs_connection_parameter->connection_interval;
+        p_connection_parameter->conn_intv_max    = p_abs_connection_parameter->connection_interval;
+        p_connection_parameter->conn_latency     = p_abs_connection_parameter->connection_slave_latency;
+        p_connection_parameter->sup_to           = p_abs_connection_parameter->supervision_timeout;
+        p_connection_parameter->min_ce_length    = BLE_ABS_GAP_CONNECTION_CE_LENGTH;
+        p_connection_parameter->max_ce_length    = BLE_ABS_GAP_CONNECTION_CE_LENGTH;
+        p_connection_phy_parameter->scan_intv    = BLE_ABS_CONN_SC_INTV_FAST;
+        p_connection_phy_parameter->scan_window  = BLE_ABS_CONN_SC_WINDOW_FAST;
+        p_connection_phy_parameter->p_conn_param = p_connection_parameter;
+    }
+}                                      /* End of function ble_abs_set_connection_parameter() */
+
+/*******************************************************************************************************************//**
+ * Set pairing parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_ASSERTION                           parameter is NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The pairing parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_set_pairing_parameter (ble_abs_pairing_parameter_t * p_pairing_parameter)
+{
+    FSP_ASSERT(p_pairing_parameter);
+
+    st_ble_gap_pairing_param_t pairing_parameter;
+
+    pairing_parameter.iocap         = p_pairing_parameter->io_capabilitie_local_device;
+    pairing_parameter.mitm          = p_pairing_parameter->mitm_protection_policy;
+    pairing_parameter.bonding       = BLE_GAP_BONDING;
+    pairing_parameter.max_key_size  = BLE_ABS_SET_PAIRING_MAXIMUM_LTK_SIZE;
+    pairing_parameter.min_key_size  = p_pairing_parameter->maximum_key_size;
+    pairing_parameter.loc_key_dist  = p_pairing_parameter->local_key_distribute;
+    pairing_parameter.rem_key_dist  = p_pairing_parameter->remote_key_distribute;
+    pairing_parameter.key_notf      = BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT;
+    pairing_parameter.sec_conn_only = p_pairing_parameter->secure_connection_only;
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == R_BLE_GAP_SetPairingParams(&pairing_parameter), FSP_ERR_INVALID_ARGUMENT);
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_set_pairing_parameter() */
+
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+
+/*******************************************************************************************************************//**
+ * Advertising timer handler for legacy advertising.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_to_function (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_handle)
+{
+    R_BLE_GAP_StopAdv(BLE_ABS_COMMON_HDL);
+    ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_ABS_ADV_COMM_TO, 0);
+}                                      /* End of function ble_abs_advertising_to_function() */
+
+#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */
+
+/*******************************************************************************************************************//**
+ * Cancel a request for connection.
+ **********************************************************************************************************************/
+static void ble_abs_cancel_connection_function (void)
+{
+    R_BLE_GAP_CancelCreateConn();
+}                                      /* End of function ble_abs_cancel_connection_function() */
+
+/*******************************************************************************************************************//**
+ * Configure scan response data and start legacy advertising.
+ **********************************************************************************************************************/
+static void ble_abs_set_legacy_scan_response_data (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.legacy_advertising_parameter.
+         scan_response_data_length) &&
+        (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.legacy_advertising_parameter.
+         p_scan_response_data))
+    {
+        if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status & BLE_ABS_ADV_STATUS_SRES_DATA)
+        {
+            ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+        }
+        else
+        {
+            ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_SCAN_RSP_DATA_MODE);
+        }
+    }
+    else
+    {
+        ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+    }
+}                                      /* End of function ble_abs_set_legacy_scan_response_data() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_PARAM_SET_COMP event.
+ **********************************************************************************************************************/
+void ble_abs_advertising_parameter_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                st_ble_evt_data_t             * p_event_data)
+{
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    st_ble_gap_adv_set_evt_t * p_advertising_set_parameter;
+    p_advertising_set_parameter = (st_ble_gap_adv_set_evt_t *) p_event_data->p_param;
+
+    switch (p_advertising_set_parameter->adv_hdl)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status &
+                 (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)))
+            {
+                if ((p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                     legacy_advertising_parameter.advertising_data_length) &&
+                    (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                     legacy_advertising_parameter.p_advertising_data))
+                {
+                    if (p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_status &
+                        BLE_ABS_ADV_STATUS_ADV_DATA)
+                    {
+                        ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+                    }
+                    else
+                    {
+                        ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_LEGACY_HDL, BLE_GAP_ADV_DATA_MODE);
+                    }
+                }
+                else
+                {
+                    ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+                }
+            }
+
+            break;
+        }
+
+        case BLE_ABS_EXT_HDL:
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status &
+                 (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)))
+            {
+                if ((p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter.
+                     extend_advertising_parameter.advertising_data_length) &&
+                    (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter.
+                     extend_advertising_parameter.p_advertising_data))
+                {
+                    if (p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_status &
+                        BLE_ABS_ADV_STATUS_ADV_DATA)
+                    {
+                        ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_EXT_HDL);
+                    }
+                    else
+                    {
+                        ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_EXT_HDL, BLE_GAP_ADV_DATA_MODE);
+                    }
+                }
+                else
+                {
+                    ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_EXT_HDL);
+                }
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            if (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_status &
+                BLE_ABS_ADV_STATUS_PARAM_SLOW)
+            {
+                if ((p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                     non_connectable_advertising_parameter.advertising_data_length) &&
+                    (p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                     non_connectable_advertising_parameter.p_advertising_data))
+                {
+                    ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_NON_CONN_HDL, BLE_GAP_ADV_DATA_MODE);
+                }
+                else
+                {
+                    ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_NON_CONN_HDL);
+                }
+            }
+
+            break;
+        }
+
+        default /* BLE_ABS_PERD_HDL */:
+        {
+            if (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW)
+            {
+                st_ble_gap_perd_adv_param_t periodic_parameter;
+                periodic_parameter.adv_hdl       = BLE_ABS_PERD_HDL;
+                periodic_parameter.prop_type     = 0x0000;
+                periodic_parameter.perd_intv_min =
+                    p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                    periodic_advertising_parameter
+                    .periodic_advertising_interval;
+                periodic_parameter.perd_intv_max = periodic_parameter.perd_intv_min;
+                R_BLE_GAP_SetPerdAdvParam(&periodic_parameter);
+                ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_ABS_ADV_STATUS_PERD_PARAM, 0);
+            }
+
+            break;
+        }
+    }
+
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG)
+    {
+        if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status &
+             (BLE_ABS_ADV_STATUS_PARAM_FAST | BLE_ABS_ADV_STATUS_PARAM_SLOW)))
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                 legacy_advertising_parameter.advertising_data_length) &&
+                (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                 legacy_advertising_parameter.p_advertising_data))
+            {
+                if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status &
+                    BLE_ABS_ADV_STATUS_ADV_DATA)
+                {
+                    ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+                }
+                else
+                {
+                    ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_GAP_ADV_DATA_MODE);
+                }
+            }
+            else
+            {
+                ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+            }
+        }
+    }
+    else
+    {
+        if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW)
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                 non_connectable_advertising_parameter.advertising_data_length) &&
+                (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                 non_connectable_advertising_parameter.p_advertising_data))
+            {
+                ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_GAP_ADV_DATA_MODE);
+            }
+            else
+            {
+                ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_NON_CONN_HDL);
+            }
+        }
+    }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+} /* End of function ble_abs_advertising_parameter_set_handler() */
+
+/*******************************************************************************************************************//**
+ * Start advertising.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_start (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t advertising_handle)
+{
+    ble_status_t retval = BLE_SUCCESS;
+
+    uint32_t status = 0;
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    uint16_t fast_period = (uint16_t) ((BLE_ABS_LEGACY_HDL == advertising_handle) ?
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                                       legacy_advertising_parameter.fast_advertising_period :
+                                       (BLE_ABS_EXT_HDL == advertising_handle) ?
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter.
+                                       extend_advertising_parameter.fast_advertising_period :
+                                       0x0000);
+    uint16_t slow_period = (uint16_t) ((BLE_ABS_LEGACY_HDL == advertising_handle) ?
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                                       legacy_advertising_parameter.slow_advertising_period :
+                                       (BLE_ABS_EXT_HDL == advertising_handle) ?
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter.
+                                       extend_advertising_parameter.slow_advertising_period :
+                                       (BLE_ABS_NON_CONN_HDL == advertising_handle) ?
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                                       non_connectable_advertising_parameter.advertising_duration :
+                                       p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                                       periodic_advertising_parameter.advertising_parameter.advertising_duration);
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    uint16_t fast_period =
+        p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.legacy_advertising_parameter.
+        fast_advertising_period;
+    uint16_t slow_period =
+        (uint16_t) ((0 !=
+                     (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status &
+                      BLE_ABS_ADV_COMM_LEG)) ?
+                    p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                    legacy_advertising_parameter.slow_advertising_period :
+                    p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                    non_connectable_advertising_parameter.advertising_duration);
+    uint32_t to = slow_period;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    if (0x0000 == fast_period)
+    {
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+        if ((BLE_ABS_PERD_HDL == advertising_handle) &&
+            (!(p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PERD_START)))
+        {
+            retval = R_BLE_GAP_StartPerdAdv(BLE_ABS_PERD_HDL);
+            status = BLE_ABS_ADV_STATUS_PERD_START;
+        }
+        else
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+        {
+            retval = R_BLE_GAP_StartAdv(advertising_handle, slow_period, 0x0000);
+            status = BLE_ABS_ADV_STATUS_ADV_SLOW_START;
+        }
+    }
+    else
+    {
+        if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & BLE_ABS_ADV_STATUS_PARAM_SLOW)
+        {
+            retval = R_BLE_GAP_StartAdv(advertising_handle, slow_period, 0x0000);
+            status = BLE_ABS_ADV_STATUS_ADV_SLOW_START;
+        }
+        else
+        {
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+            to = fast_period;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 0) */
+            retval = R_BLE_GAP_StartAdv(advertising_handle, fast_period, 0x0000);
+            status = BLE_ABS_ADV_STATUS_ADV_FAST_START;
+        }
+    }
+
+    if (BLE_SUCCESS == retval)
+    {
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+        if (0 != to)
+        {
+            ble_abs_timer_create(p_instance_ctrl,
+                                 &p_instance_ctrl->advertising_timer_handle,
+                                 (to * 10),
+                                 BLE_TIMER_ONE_SHOT,
+                                 ble_abs_advertising_to_function);
+            ble_abs_timer_start(p_instance_ctrl, p_instance_ctrl->advertising_timer_handle);
+        }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE  != 0) */
+        ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+    }
+}                                      /* End of function ble_abs_advertising_start() */
+
+/*******************************************************************************************************************//**
+ * Configure advertising data or scan response data or periodic advertising data.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_set_data (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                          uint8_t                         advertising_handle,
+                                          uint8_t                         data_type)
+{
+    st_ble_gap_adv_data_t advertising_data;
+    ble_status_t          retval = BLE_SUCCESS;
+    uint32_t              status = 0;
+
+    advertising_data.adv_hdl          = advertising_handle;
+    advertising_data.zero_length_flag = BLE_GAP_DATA_0_CLEAR;
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    switch (advertising_handle)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            status = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                     BLE_ABS_ADV_STATUS_ADV_DATA :
+                     BLE_ABS_ADV_STATUS_SRES_DATA;
+            advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                    BLE_GAP_ADV_DATA_MODE :
+                                                    BLE_GAP_SCAN_RSP_DATA_MODE);
+            advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].
+                                                       advertising_parameter.legacy_advertising_parameter.
+                                                       advertising_data_length :
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].
+                                                       advertising_parameter.legacy_advertising_parameter.
+                                                       scan_response_data_length);
+            advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                                      legacy_advertising_parameter.p_advertising_data :
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_LEGACY_HDL].advertising_parameter.
+                                      legacy_advertising_parameter.p_scan_response_data;
+            break;
+        }
+
+        case BLE_ABS_EXT_HDL:
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            status = BLE_ABS_ADV_STATUS_ADV_DATA;
+            advertising_data.data_type   = BLE_GAP_ADV_DATA_MODE;
+            advertising_data.data_length = (uint16_t) ((BLE_ABS_EXT_HDL == advertising_handle) ?
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].
+                                                       advertising_parameter.extend_advertising_parameter.
+                                                       advertising_data_length :
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].
+                                                       advertising_parameter.non_connectable_advertising_parameter.
+                                                       advertising_data_length);
+            advertising_data.p_data = (BLE_ABS_EXT_HDL == advertising_handle) ?
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_EXT_HDL].advertising_parameter.
+                                      extend_advertising_parameter.p_advertising_data :
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_NON_CONN_HDL].advertising_parameter.
+                                      non_connectable_advertising_parameter.p_advertising_data;
+            break;
+        }
+
+        default /* BLE_ABS_PERD_HDL */:
+        {
+            status = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                     BLE_ABS_ADV_STATUS_ADV_DATA :
+                     BLE_ABS_ADV_STATUS_PERD_DATA;
+            advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                    BLE_GAP_ADV_DATA_MODE :
+                                                    BLE_GAP_PERD_ADV_DATA_MODE);
+            advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].
+                                                       advertising_parameter.periodic_advertising_parameter.
+                                                       advertising_parameter.advertising_data_length :
+                                                       p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].
+                                                       advertising_parameter.periodic_advertising_parameter.
+                                                       periodic_advertising_data_length);
+            advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                                      periodic_advertising_parameter.advertising_parameter.p_advertising_data :
+                                      p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                                      periodic_advertising_parameter.p_periodic_advertising_data;
+            break;
+        }
+    }
+
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG)
+    {
+        status = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                 BLE_ABS_ADV_STATUS_ADV_DATA :
+                 BLE_ABS_ADV_STATUS_SRES_DATA;
+        advertising_data.data_type = (uint8_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                BLE_GAP_ADV_DATA_MODE :
+                                                BLE_GAP_SCAN_RSP_DATA_MODE);
+        advertising_data.data_length = (uint16_t) ((BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                                   p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].
+                                                   advertising_parameter.legacy_advertising_parameter.
+                                                   advertising_data_length :
+                                                   p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].
+                                                   advertising_parameter.legacy_advertising_parameter.
+                                                   scan_response_data_length);
+        advertising_data.p_data = (BLE_GAP_ADV_DATA_MODE == data_type) ?
+                                  p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                                  legacy_advertising_parameter.p_advertising_data :
+                                  p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                                  legacy_advertising_parameter.p_scan_response_data;
+    }
+    else
+    {
+        status = BLE_ABS_ADV_STATUS_ADV_DATA;
+        advertising_data.data_type   = BLE_GAP_ADV_DATA_MODE;
+        advertising_data.data_length =
+            p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+            non_connectable_advertising_parameter
+            .advertising_data_length;
+        advertising_data.p_data =
+            p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+            non_connectable_advertising_parameter
+            .p_advertising_data;
+    }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    retval = R_BLE_GAP_SetAdvSresData(&advertising_data);
+    if (BLE_SUCCESS == retval)
+    {
+        ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, status, 0);
+    }
+}                                      /* End of function ble_abs_advertising_set_data() */
+
+/*******************************************************************************************************************//**
+ * Configure advertising data or scan response data or periodic advertising data.
+ **********************************************************************************************************************/
+static void ble_abs_periodic_parameter_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status & BLE_ABS_ADV_STATUS_PERD_PARAM)
+    {
+        if ((p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.periodic_advertising_parameter.
+             advertising_parameter.advertising_data_length) &&
+            (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.periodic_advertising_parameter.
+             advertising_parameter.p_advertising_data))
+        {
+            ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_ADV_DATA_MODE);
+        }
+        else
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                 periodic_advertising_parameter.periodic_advertising_data_length) &&
+                (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_parameter.
+                 periodic_advertising_parameter.p_periodic_advertising_data))
+            {
+                ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_PERD_ADV_DATA_MODE);
+            }
+            else
+            {
+                ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL);
+            }
+        }
+    }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+} /* End of function ble_abs_periodic_parameter_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_DATA_UPD_COMP event.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_data_set_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                  st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_data_evt_t * p_advertising_data_set_parameter;
+
+    p_advertising_data_set_parameter = (st_ble_gap_adv_data_evt_t *) p_event_data->p_param;
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    switch (p_advertising_data_set_parameter->adv_hdl)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type)
+            {
+                ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+            }
+            else
+            {
+                ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_LEGACY_HDL);
+            }
+
+            break;
+        }
+
+        case BLE_ABS_EXT_HDL:
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            ble_abs_advertising_start(p_instance_ctrl, p_advertising_data_set_parameter->adv_hdl);
+            break;
+        }
+
+        default:                       /* BLE_ABS_PERD_HDL */
+        {
+            if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type)
+            {
+                ble_abs_advertising_set_data(p_instance_ctrl, BLE_ABS_PERD_HDL, BLE_GAP_PERD_ADV_DATA_MODE);
+            }
+            else
+            {
+                ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL);
+            }
+
+            break;
+        }
+    }
+
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG)
+    {
+        if (BLE_GAP_ADV_DATA_MODE == p_advertising_data_set_parameter->data_type)
+        {
+            ble_abs_set_legacy_scan_response_data(p_instance_ctrl);
+        }
+        else
+        {
+            ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_COMMON_HDL);
+        }
+    }
+    else
+    {
+        ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_COMMON_HDL);
+    }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+} /* End of function ble_abs_advertising_data_set_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_OFF event.
+ **********************************************************************************************************************/
+static void ble_abs_advertising_off_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                             st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_off_evt_t * p_advertising_off_parameter;
+
+    p_advertising_off_parameter = (st_ble_gap_adv_off_evt_t *) p_event_data->p_param;
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    switch (p_advertising_off_parameter->adv_hdl)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        case BLE_ABS_EXT_HDL:
+        {
+            if (0x02 == p_advertising_off_parameter->reason)
+            {
+                if ((p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].advertising_status &
+                     BLE_ABS_ADV_STATUS_ADV_FAST_START))
+                {
+                    st_ble_gap_adv_param_t advertising_parameter;
+
+                    ble_abs_set_advertising_status(p_instance_ctrl,
+                                                   p_advertising_off_parameter->adv_hdl,
+                                                   0,
+                                                   BLE_ABS_ADV_STATUS_ADV_FAST_START); ///< fast -> slow
+
+                    if (BLE_ABS_LEGACY_HDL == p_advertising_off_parameter->adv_hdl)
+                    {
+                        ble_abs_convert_legacy_advertising_parameter(&p_instance_ctrl->advertising_sets[
+                                                                         p_advertising_off_parameter->adv_hdl].advertising_parameter.legacy_advertising_parameter,
+                                                                     &advertising_parameter);
+                        advertising_parameter.adv_intv_min =
+                            p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].
+                            advertising_parameter.
+                            legacy_advertising_parameter.slow_advertising_interval;
+                        advertising_parameter.adv_intv_max =
+                            p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].
+                            advertising_parameter.
+                            legacy_advertising_parameter.slow_advertising_interval;
+                    }
+                    else
+                    {
+                        ble_abs_convert_extend_advertising_parameter(&p_instance_ctrl->advertising_sets[
+                                                                         p_advertising_off_parameter->adv_hdl].advertising_parameter.extend_advertising_parameter,
+                                                                     &advertising_parameter);
+                        advertising_parameter.adv_intv_min =
+                            p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].
+                            advertising_parameter.
+                            extend_advertising_parameter.slow_advertising_interval;
+                        advertising_parameter.adv_intv_max =
+                            p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].
+                            advertising_parameter.
+                            extend_advertising_parameter.slow_advertising_interval;
+                    }
+
+                    R_BLE_GAP_SetAdvParam(&advertising_parameter);
+                    ble_abs_set_advertising_status(p_instance_ctrl,
+                                                   p_advertising_off_parameter->adv_hdl,
+                                                   BLE_ABS_ADV_STATUS_PARAM_SLOW,
+                                                   0);
+                }
+                else
+                {
+                    if ((p_instance_ctrl->advertising_sets[p_advertising_off_parameter->adv_hdl].advertising_status &
+                         BLE_ABS_ADV_STATUS_ADV_SLOW_START))
+                    {
+                        ble_abs_set_advertising_status(p_instance_ctrl,
+                                                       p_advertising_off_parameter->adv_hdl,
+                                                       0,
+                                                       BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off
+                    }
+                }
+            }
+            else
+            {
+                ble_abs_set_advertising_status(p_instance_ctrl,
+                                               p_advertising_off_parameter->adv_hdl,
+                                               0,
+                                               (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START));
+            }
+
+            break;
+        }
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_NON_CONN_HDL, 0, BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off
+            break;
+        }
+
+        default:                                                                                                         /* BLE_ABS_PERD_HDL */
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, 0, BLE_ABS_ADV_STATUS_ADV_SLOW_START);
+            if (0 !=
+                (p_instance_ctrl->advertising_sets[BLE_ABS_PERD_HDL].advertising_status &
+                 BLE_ABS_ADV_STATUS_PERD_START))
+            {
+                R_BLE_GAP_StopPerdAdv(BLE_ABS_PERD_HDL);
+            }
+
+            break;
+        }
+    }
+
+#else                                  /* (BLE_CFG_LIBRARY_TYPE == 0) */
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_TO)
+    {
+        p_advertising_off_parameter->reason = 0x02;
+        ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, 0, BLE_ABS_ADV_COMM_TO);
+    }
+
+    if (p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status & BLE_ABS_ADV_COMM_LEG)
+    {
+        if (0x02 == p_advertising_off_parameter->reason)
+        {
+            if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status &
+                 BLE_ABS_ADV_STATUS_ADV_FAST_START))
+            {
+                st_ble_gap_adv_param_t advertising_parameter;
+
+                ble_abs_set_advertising_status(p_instance_ctrl,
+                                               BLE_ABS_COMMON_HDL,
+                                               0,
+                                               BLE_ABS_ADV_STATUS_ADV_FAST_START); ///< fast -> slow
+
+                ble_abs_convert_legacy_advertising_parameter(
+                    &p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.legacy_advertising_parameter,
+                    &advertising_parameter);
+                advertising_parameter.adv_intv_min =
+                    p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                    legacy_advertising_parameter
+                    .slow_advertising_interval;
+                advertising_parameter.adv_intv_max =
+                    p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_parameter.
+                    legacy_advertising_parameter
+                    .slow_advertising_interval;
+
+                R_BLE_GAP_SetAdvParam(&advertising_parameter);
+                ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_COMMON_HDL, BLE_ABS_ADV_STATUS_PARAM_SLOW, 0);
+            }
+            else
+            {
+                if ((p_instance_ctrl->advertising_sets[BLE_ABS_COMMON_HDL].advertising_status &
+                     BLE_ABS_ADV_STATUS_ADV_SLOW_START))
+                {
+                    ble_abs_set_advertising_status(p_instance_ctrl,
+                                                   BLE_ABS_COMMON_HDL,
+                                                   0,
+                                                   BLE_ABS_ADV_STATUS_ADV_SLOW_START); ///< slow -> off
+                }
+            }
+        }
+        else
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl,
+                                           BLE_ABS_COMMON_HDL,
+                                           0,
+                                           (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START |
+                                            BLE_ABS_ADV_COMM_LEG));
+        }
+    }
+    else
+    {
+        ble_abs_set_advertising_status(p_instance_ctrl,
+                                       BLE_ABS_COMMON_HDL,
+                                       0,
+                                       (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_COMM_NON)); ///< slow -> off
+    }
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+} /* End of function ble_abs_advertising_off_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_ADV_REPT_IND event.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                   Filtering data is not included in the advertising data.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_advertising_report_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                     st_ble_evt_data_t             * p_event_data)
+{
+    st_ble_gap_adv_rept_evt_t * p_advertising_report_parameter;
+    uint8_t * p_buf  = NULL;
+    uint32_t  len    = 0;
+    fsp_err_t retval = FSP_ERR_BLE_ABS_NOT_FOUND;
+
+    if ((NULL == p_instance_ctrl->abs_scan.scan_parameter.p_filter_data) ||
+        (0 == p_instance_ctrl->abs_scan.scan_parameter.filter_data_length))
+    {
+        retval = FSP_SUCCESS;
+    }
+    else
+    {
+        p_advertising_report_parameter = (st_ble_gap_adv_rept_evt_t *) p_event_data->p_param;
+
+        switch (p_advertising_report_parameter->adv_rpt_type)
+        {
+            /*Legacy Advertising Report.*/
+            case 0x00:
+            {
+                p_buf = p_advertising_report_parameter->param.p_adv_rpt->p_data;
+                len   = p_advertising_report_parameter->param.p_adv_rpt->len;
+
+                break;
+            }
+
+            /*Extended Advertising Report.*/
+            case 0x01:
+            {
+                p_buf = p_advertising_report_parameter->param.p_ext_adv_rpt->p_data;
+                len   = p_advertising_report_parameter->param.p_ext_adv_rpt->len;
+
+                break;
+            }
+
+            /*Periodic Advertising Report.*/
+            case 0x02:
+            {
+                p_buf = p_advertising_report_parameter->param.p_per_adv_rpt->p_data;
+                len   = p_advertising_report_parameter->param.p_per_adv_rpt->len;
+                break;
+            }
+
+            default:
+            {
+                break;
+            }
+        }
+
+        uint32_t cnt = len - (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length + 1;
+
+        if (1 <= cnt)
+        {
+            uint32_t i;
+            uint16_t pos = 0U;
+
+            while (pos < len)
+            {
+                /* Each advertising structure have following constructs.
+                 * - Lenght: 1 byte (The length of AD type + AD data)
+                 * - AD type: 1 byte
+                 * - AD data: variable
+                 */
+                uint8_t ad_len = (uint8_t) (p_buf[pos] - 1);
+                uint8_t type   = p_buf[pos + 1];
+
+                if (type == p_instance_ctrl->abs_scan.scan_parameter.filter_ad_type)
+                {
+                    for (i = 0; i < ad_len; i++)
+                    {
+                        if (0 == memcmp(&p_buf[pos + 2U + i],
+                                        p_instance_ctrl->abs_scan.scan_parameter.p_filter_data,
+                                        (uint32_t) p_instance_ctrl->abs_scan.scan_parameter.filter_data_length))
+                        {
+                            return FSP_SUCCESS;
+                        }
+                    }
+                }
+
+                pos = (uint16_t) (pos + ad_len);
+                pos = (uint16_t) (pos + 2UL);
+            }
+        }
+    }
+
+    return retval;
+}                                      /* End of function ble_abs_advertising_report_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_LOC_VER_INFO event.
+ **********************************************************************************************************************/
+static void ble_abs_loc_ver_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl, st_ble_evt_data_t * p_event_data)
+{
+    st_ble_gap_loc_dev_info_evt_t * event_parameter;
+    event_parameter              = (st_ble_gap_loc_dev_info_evt_t *) p_event_data->p_param;
+    p_instance_ctrl->loc_bd_addr = event_parameter->l_dev_addr;
+}                                      /* End of function ble_abs_loc_ver_handler() */
+
+/*******************************************************************************************************************//**
+ * Convert Abstraction API scan phy parameters to GAP scan phy parameters.
+ **********************************************************************************************************************/
+static void ble_abs_convert_scan_phy_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                ble_abs_scan_phy_parameter_t  * p_abs_phy,
+                                                ble_gap_scan_phy_parameter_t  * p_gap_phy,
+                                                ble_gap_scan_on_t             * p_scan_enable)
+{
+    if ((NULL != p_abs_phy) && (NULL != p_gap_phy))
+    {
+        p_gap_phy->scan_type = p_abs_phy->scan_type;
+
+        if (p_instance_ctrl->abs_scan.scan_parameter.fast_scan_period)
+        {
+            p_gap_phy->scan_intv    = p_abs_phy->fast_scan_interval;
+            p_gap_phy->scan_window  = p_abs_phy->fast_scan_window;
+            p_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.fast_scan_period;
+        }
+        else
+        {
+            p_gap_phy->scan_intv    = p_abs_phy->slow_scan_interval;
+            p_gap_phy->scan_window  = p_abs_phy->slow_scan_window;
+            p_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.slow_scan_period;
+        }
+    }
+}                                      /* End of function ble_abs_convert_scan_phy_parameter() */
+
+/*******************************************************************************************************************//**
+ * Convert Abstraction API scan parameters to GAP scan parameters.
+ **********************************************************************************************************************/
+static void ble_abs_convert_scan_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                            st_ble_gap_scan_param_t       * p_gap_scan_parameter,
+                                            ble_gap_scan_on_t             * p_gap_scan_enable,
+                                            uint32_t                        status)
+{
+    p_gap_scan_parameter->o_addr_type   = BLE_GAP_ADDR_PUBLIC;
+    p_gap_scan_parameter->filter_policy = p_instance_ctrl->abs_scan.scan_parameter.device_scan_filter_policy;
+    p_gap_scan_enable->proc_type        = BLE_GAP_SC_PROC_OBS;
+    p_gap_scan_enable->period           = 0;
+    p_gap_scan_enable->filter_dups      = p_instance_ctrl->abs_scan.scan_parameter.filter_duplicate;
+
+    if (BLE_ABS_SCAN_STATUS_FAST_START == status)
+    {
+        if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M)
+        {
+            ble_abs_convert_scan_phy_parameter(p_instance_ctrl,
+                                               p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M,
+                                               (ble_gap_scan_phy_parameter_t *) p_gap_scan_parameter->p_phy_param_1M,
+                                               p_gap_scan_enable);
+        }
+
+        if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded)
+        {
+            ble_abs_convert_scan_phy_parameter(p_instance_ctrl,
+                                               p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded,
+                                               (ble_gap_scan_phy_parameter_t *) p_gap_scan_parameter->p_phy_param_coded,
+                                               p_gap_scan_enable);
+        }
+    }
+    else
+    {
+        if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M)
+        {
+            p_gap_scan_parameter->p_phy_param_1M->scan_type =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->scan_type;
+            p_gap_scan_parameter->p_phy_param_1M->scan_intv =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->slow_scan_interval;
+            p_gap_scan_parameter->p_phy_param_1M->scan_window =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M->slow_scan_window;
+        }
+
+        if (p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded)
+        {
+            p_gap_scan_parameter->p_phy_param_coded->scan_type =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->scan_type;
+            p_gap_scan_parameter->p_phy_param_coded->scan_intv =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->slow_scan_interval;
+            p_gap_scan_parameter->p_phy_param_coded->scan_window =
+                p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded->slow_scan_window;
+        }
+
+        p_gap_scan_enable->duration = p_instance_ctrl->abs_scan.scan_parameter.slow_scan_period;
+    }
+}                                      /* End of function ble_abs_convert_scan_parameter() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_SCAN_TO event.
+ **********************************************************************************************************************/
+static void ble_abs_scan_to_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    st_ble_gap_scan_param_t      scan_parameter;
+    ble_gap_scan_phy_parameter_t phy_parameter_1M;
+    ble_gap_scan_phy_parameter_t phy_parameter_coded;
+    ble_gap_scan_on_t            scan_enable;
+
+    if (p_instance_ctrl->abs_scan.scan_status & BLE_ABS_SCAN_STATUS_FAST_START)
+    {
+        ble_abs_set_scan_status(p_instance_ctrl, 0, BLE_ABS_SCAN_STATUS_SLOW_START); ///< fast -> slow
+        scan_parameter.p_phy_param_1M =
+            p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M ? (st_ble_gap_scan_phy_param_t *) (&
+                                                                                                           phy_parameter_1M)
+            :
+            NULL;
+        scan_parameter.p_phy_param_coded =
+            p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded ? (st_ble_gap_scan_phy_param_t *) (&
+                                                                                                              phy_parameter_coded)
+            :
+            NULL;
+
+        ble_abs_convert_scan_parameter(p_instance_ctrl, &scan_parameter, &scan_enable, BLE_ABS_SCAN_STATUS_SLOW_START);
+
+        R_BLE_GAP_StartScan(&scan_parameter, (st_ble_gap_scan_on_t *) &scan_enable);
+        ble_abs_set_scan_status(p_instance_ctrl, BLE_ABS_SCAN_STATUS_SLOW_START, BLE_ABS_SCAN_STATUS_FAST_START);
+    }
+    else
+    {
+        if (p_instance_ctrl->abs_scan.scan_status & BLE_ABS_SCAN_STATUS_SLOW_START)
+        {
+            ble_abs_set_scan_status(p_instance_ctrl, 0, BLE_ABS_SCAN_STATUS_SLOW_START); ///< slow -> off
+        }
+    }
+} /* End of function ble_abs_scan_to_handler() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_CONN_IND event.
+ **********************************************************************************************************************/
+static void ble_abs_connection_indication_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    ble_abs_timer_stop(p_instance_ctrl, p_instance_ctrl->connection_timer_handle);
+    ble_abs_timer_delete(p_instance_ctrl, &p_instance_ctrl->connection_timer_handle);
+
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+    ble_abs_timer_stop(p_instance_ctrl, p_instance_ctrl->advertising_timer_handle);
+
+    ble_abs_set_advertising_status(p_instance_ctrl,
+                                   BLE_ABS_COMMON_HDL,
+                                   0,
+                                   (BLE_ABS_ADV_STATUS_ADV_SLOW_START | BLE_ABS_ADV_STATUS_ADV_FAST_START |
+                                    BLE_ABS_ADV_COMM_LEG));
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 0) */
+} /* End of function ble_abs_connection_indication_handler() */
+
+/*******************************************************************************************************************//**
+ * Set gap callback and vendor specific callback function.
+ **********************************************************************************************************************/
+static void ble_abs_set_abs_callback (ble_abs_instance_ctrl_t * const            p_instance_ctrl,
+                                      ble_gap_application_callback_t             gap_callback,
+                                      ble_vendor_specific_application_callback_t vendor_specific_callback)
+{
+    p_instance_ctrl->abs_gap_callback             = gap_callback;
+    p_instance_ctrl->abs_vendor_specific_callback = vendor_specific_callback;
+}                                      /* End of function ble_abs_set_abs_callback() */
+
+/*******************************************************************************************************************//**
+ * Set advertising interval.
+ **********************************************************************************************************************/
+static void ble_abs_set_connection_advertising_interval (st_ble_gap_adv_param_t * p_advertising_parameter,
+                                                         uint32_t                 fast_advertising_interval,
+                                                         uint32_t                 slow_advertising_interval,
+                                                         uint16_t                 fast_period)
+{
+    /** check advertising interval */
+    if (fast_period)
+    {
+        p_advertising_parameter->adv_intv_min = fast_advertising_interval;
+        p_advertising_parameter->adv_intv_max = fast_advertising_interval;
+    }
+    else
+    {
+        p_advertising_parameter->adv_intv_min = slow_advertising_interval;
+        p_advertising_parameter->adv_intv_max = slow_advertising_interval;
+    }
+}                                      /* End of function ble_abs_set_connection_advertising_interval() */
+
+/*******************************************************************************************************************//**
+ * Update advertising data status.
+ **********************************************************************************************************************/
+static void ble_abs_update_data_status (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                        uint32_t                        advertising_status,
+                                        uint8_t                       * p_advertising_data,
+                                        uint16_t                        advertising_data_len,
+                                        uint8_t                         advertising_handle)
+{
+    if (p_instance_ctrl->advertising_sets[advertising_handle].advertising_status & advertising_status)
+    {
+        if ((0 != advertising_data_len) && (NULL != p_advertising_data))
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl, advertising_handle, 0, advertising_status);
+        }
+    }
+}                                      /* End of function ble_abs_update_data_status() */
+
+/*******************************************************************************************************************//**
+ * Convert the legacy advertising parameters to GAP advertising parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_convert_legacy_advertising_parameter (
+    ble_abs_legacy_advertising_parameter_t * p_legacy_advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter)
+{
+    p_gap_advertising_parameter->adv_hdl       = BLE_ABS_LEGACY_HDL;
+    p_gap_advertising_parameter->adv_prop_type = BLE_GAP_LEGACY_PROP_ADV_IND;
+    p_gap_advertising_parameter->adv_ch_map    = p_legacy_advertising_parameter->advertising_channel_map;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_legacy_advertising_parameter->own_bluetooth_address_type),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    memcpy(p_gap_advertising_parameter->o_addr,
+           (void *) p_legacy_advertising_parameter->own_bluetooth_address,
+           BLE_BD_ADDR_LEN);
+
+    p_gap_advertising_parameter->o_addr_type = p_legacy_advertising_parameter->own_bluetooth_address_type;
+
+    if (p_legacy_advertising_parameter->p_peer_address)
+    {
+        memcpy(p_gap_advertising_parameter->p_addr,
+               p_legacy_advertising_parameter->p_peer_address->addr,
+               BLE_BD_ADDR_LEN);
+        p_gap_advertising_parameter->p_addr_type = p_legacy_advertising_parameter->p_peer_address->type;
+    }
+    else
+    {
+        p_gap_advertising_parameter->p_addr_type = BLE_GAP_ADDR_PUBLIC;
+    }
+
+    FSP_ERROR_RETURN(
+        BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST >= p_legacy_advertising_parameter->advertising_filter_policy,
+        FSP_ERR_INVALID_ARGUMENT);
+
+    p_gap_advertising_parameter->filter_policy = p_legacy_advertising_parameter->advertising_filter_policy;
+
+    p_gap_advertising_parameter->adv_phy           = BLE_GAP_ADV_PHY_1M;
+    p_gap_advertising_parameter->sec_adv_max_skip  = 0x00;
+    p_gap_advertising_parameter->sec_adv_phy       = BLE_GAP_ADV_PHY_1M;
+    p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_convert_legacy_advertising_parameter() */
+
+/*******************************************************************************************************************//**
+ * Convert the extended advertising parameters to GAP advertising parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+static fsp_err_t ble_abs_convert_extend_advertising_parameter (
+    ble_abs_extend_advertising_parameter_t * p_extend_advertising_parameter,
+    st_ble_gap_adv_param_t                 * p_gap_advertising_parameter)
+{
+    p_gap_advertising_parameter->adv_hdl    = BLE_ABS_EXT_HDL;
+    p_gap_advertising_parameter->adv_ch_map = p_extend_advertising_parameter->advertising_channel_map;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_extend_advertising_parameter->own_bluetooth_address_type),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    memcpy(p_gap_advertising_parameter->o_addr,
+           (void *) p_extend_advertising_parameter->own_bluetooth_address,
+           BLE_BD_ADDR_LEN);
+
+    p_gap_advertising_parameter->o_addr_type = p_extend_advertising_parameter->own_bluetooth_address_type;
+
+    if (p_extend_advertising_parameter->p_peer_address)
+    {
+        memcpy(p_gap_advertising_parameter->p_addr,
+               p_extend_advertising_parameter->p_peer_address->addr,
+               BLE_BD_ADDR_LEN);
+        p_gap_advertising_parameter->p_addr_type   = p_extend_advertising_parameter->p_peer_address->type;
+        p_gap_advertising_parameter->adv_prop_type = BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT;
+    }
+    else
+    {
+        p_gap_advertising_parameter->p_addr_type   = BLE_GAP_ADDR_PUBLIC;
+        p_gap_advertising_parameter->adv_prop_type = BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT;
+    }
+
+    FSP_ERROR_RETURN(
+        BLE_ABS_ADVERTISING_FILTER_ALLOW_WHITE_LIST >= p_extend_advertising_parameter->advertising_filter_policy,
+        FSP_ERR_INVALID_ARGUMENT);
+
+    p_gap_advertising_parameter->filter_policy = p_extend_advertising_parameter->advertising_filter_policy;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M == p_extend_advertising_parameter->primary_advertising_phy) ||
+                     (BLE_GAP_ADV_PHY_CD == p_extend_advertising_parameter->primary_advertising_phy),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    p_gap_advertising_parameter->adv_phy          = p_extend_advertising_parameter->primary_advertising_phy;
+    p_gap_advertising_parameter->sec_adv_max_skip = 0x00;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M <= p_extend_advertising_parameter->secondary_advertising_phy) &&
+                     (BLE_GAP_ADV_PHY_CD >= p_extend_advertising_parameter->secondary_advertising_phy),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    p_gap_advertising_parameter->sec_adv_phy       = p_extend_advertising_parameter->secondary_advertising_phy;
+    p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_convert_extend_advertising_parameter() */
+
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+/*******************************************************************************************************************//**
+ * Convert the non-connectable advertising parameters to GAP advertising parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_convert_non_connectable_advertising_parameter (
+    ble_abs_non_connectable_advertising_parameter_t * p_non_connectable_advertising_parameter,
+    st_ble_gap_adv_param_t                          * p_gap_advertising_parameter,
+    uint8_t                                           advertising_handle)
+{
+    p_gap_advertising_parameter->adv_hdl    = advertising_handle;
+    p_gap_advertising_parameter->adv_ch_map = p_non_connectable_advertising_parameter->advertising_channel_map;
+
+    FSP_ERROR_RETURN(
+        (BLE_GAP_ADDR_RPA_ID_PUBLIC >= p_non_connectable_advertising_parameter->own_bluetooth_address_type),
+        FSP_ERR_INVALID_ARGUMENT);
+
+    memcpy(p_gap_advertising_parameter->o_addr,
+           (void *) p_non_connectable_advertising_parameter->own_bluetooth_address,
+           BLE_BD_ADDR_LEN);
+
+    p_gap_advertising_parameter->o_addr_type = p_non_connectable_advertising_parameter->own_bluetooth_address_type;
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+    p_non_connectable_advertising_parameter->primary_advertising_phy = BLE_ABS_ADVERTISING_PHY_LEGACY;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE != 0) */
+    FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M >= p_non_connectable_advertising_parameter->primary_advertising_phy) ||
+                     (BLE_GAP_ADV_PHY_CD == p_non_connectable_advertising_parameter->primary_advertising_phy),
+                     FSP_ERR_INVALID_ARGUMENT);
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+    FSP_ERROR_RETURN((BLE_ABS_ADVERTISING_PHY_LEGACY != p_non_connectable_advertising_parameter->primary_advertising_phy) ||
+                     (BLE_ABS_PERD_HDL != advertising_handle),
+                     FSP_ERR_INVALID_ARGUMENT);
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+    p_gap_advertising_parameter->adv_phy =
+        (uint8_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY ==
+                    p_non_connectable_advertising_parameter->primary_advertising_phy) ?
+                   BLE_GAP_ADV_PHY_1M :
+                   p_non_connectable_advertising_parameter->primary_advertising_phy);
+
+    if (p_non_connectable_advertising_parameter->p_peer_address)
+    {
+        memcpy(p_gap_advertising_parameter->p_addr,
+               p_non_connectable_advertising_parameter->p_peer_address->addr,
+               BLE_BD_ADDR_LEN);
+        p_gap_advertising_parameter->p_addr_type   = p_non_connectable_advertising_parameter->p_peer_address->type;
+        p_gap_advertising_parameter->adv_prop_type =
+            (uint16_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY !=
+                         p_non_connectable_advertising_parameter->primary_advertising_phy) ?
+                        BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT :
+                        BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND);
+    }
+    else
+    {
+        p_gap_advertising_parameter->p_addr_type   = BLE_GAP_ADDR_PUBLIC;
+        p_gap_advertising_parameter->adv_prop_type =
+            (uint16_t) ((BLE_ABS_ADVERTISING_PHY_LEGACY !=
+                         p_non_connectable_advertising_parameter->primary_advertising_phy) ?
+                        BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT :
+                        BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND);
+    }
+
+    p_gap_advertising_parameter->filter_policy    = BLE_ABS_ADVERTISING_FILTER_ALLOW_ANY;
+    p_gap_advertising_parameter->sec_adv_max_skip = 0x00;
+
+    FSP_ERROR_RETURN((BLE_GAP_ADV_PHY_1M <= p_non_connectable_advertising_parameter->secondary_advertising_phy) &&
+                     (BLE_GAP_ADV_PHY_CD >= p_non_connectable_advertising_parameter->secondary_advertising_phy),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    p_gap_advertising_parameter->sec_adv_phy       = p_non_connectable_advertising_parameter->secondary_advertising_phy;
+    p_gap_advertising_parameter->scan_req_ntf_flag = BLE_GAP_SCAN_REQ_NTF_DISABLE;
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_convert_non_connectable_advertising_parameter() */
+
+/*******************************************************************************************************************//**
+ * Set advertising status.
+ **********************************************************************************************************************/
+static void ble_abs_set_advertising_status (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                            uint8_t                         advertising_handle,
+                                            uint32_t                        set,
+                                            uint32_t                        clear)
+{
+    p_instance_ctrl->advertising_sets[advertising_handle].advertising_status |= set;
+    p_instance_ctrl->advertising_sets[advertising_handle].advertising_status &= ~clear;
+}                                      /* End of function ble_abs_set_advertising_status() */
+
+/*******************************************************************************************************************//**
+ * Store advertising configuration.
+ **********************************************************************************************************************/
+static void ble_abs_set_advertising_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                               void                          * p_advertising_parameter,
+                                               uint8_t                         advertising_handle)
+{
+    switch (advertising_handle)
+    {
+        case BLE_ABS_LEGACY_HDL:
+        {
+            ble_abs_legacy_advertising_parameter_t * p_abs_legacy;
+            p_abs_legacy = (ble_abs_legacy_advertising_parameter_t *) p_advertising_parameter;
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+            advertising_handle = BLE_ABS_COMMON_HDL;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+            memcpy(
+                &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter,
+                p_abs_legacy,
+                sizeof(ble_abs_legacy_advertising_parameter_t));
+            if (NULL != p_abs_legacy->p_peer_address)
+            {
+                memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                       p_abs_legacy->p_peer_address,
+                       sizeof(ble_device_address_t));
+                p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.legacy_advertising_parameter
+                .p_peer_address = &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+            }
+
+            break;
+        }
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+        case BLE_ABS_EXT_HDL:
+        {
+            ble_abs_extend_advertising_parameter_t * p_abs_ext;
+            p_abs_ext = (ble_abs_extend_advertising_parameter_t *) p_advertising_parameter;
+            memcpy(
+                &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.extend_advertising_parameter,
+                p_abs_ext,
+                sizeof(ble_abs_extend_advertising_parameter_t));
+            if (NULL != p_abs_ext->p_peer_address)
+            {
+                memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                       p_abs_ext->p_peer_address,
+                       sizeof(ble_device_address_t));
+                p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.extend_advertising_parameter
+                .p_peer_address = &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+            }
+
+            break;
+        }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+        case BLE_ABS_NON_CONN_HDL:
+        {
+            ble_abs_non_connectable_advertising_parameter_t * p_abs_non_conn;
+            p_abs_non_conn = (ble_abs_non_connectable_advertising_parameter_t *) p_advertising_parameter;
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+            advertising_handle = BLE_ABS_COMMON_HDL;
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+            memcpy(
+                &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.non_connectable_advertising_parameter,
+                p_abs_non_conn,
+                sizeof(ble_abs_non_connectable_advertising_parameter_t));
+            if (NULL != p_abs_non_conn->p_peer_address)
+            {
+                memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                       p_abs_non_conn->p_peer_address,
+                       sizeof(ble_device_address_t));
+                p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.
+                non_connectable_advertising_parameter.p_peer_address =
+                    &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+            }
+
+            break;
+        }
+
+        default:                       /** BLE_ABS_PERD_HDL */
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+            {
+                ble_abs_periodic_advertising_parameter_t * p_abs_perd;
+                p_abs_perd = (ble_abs_periodic_advertising_parameter_t *) p_advertising_parameter;
+                memcpy(
+                    &p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.periodic_advertising_parameter,
+                    p_abs_perd,
+                    sizeof(ble_abs_periodic_advertising_parameter_t));
+                if (NULL != p_abs_perd->advertising_parameter.p_peer_address)
+                {
+                    memcpy(&p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address,
+                           p_abs_perd->advertising_parameter.p_peer_address,
+                           sizeof(ble_device_address_t));
+                    p_instance_ctrl->advertising_sets[advertising_handle].advertising_parameter.
+                    periodic_advertising_parameter.advertising_parameter.p_peer_address =
+                        &p_instance_ctrl->advertising_sets[advertising_handle].remote_device_address;
+                }
+            }
+#endif                                 /* (BLE_CFG_LIBRARY_TYPE == 0) */
+            break;
+    }
+} /* End of function ble_abs_set_advertising_parameter() */
+
+/*******************************************************************************************************************//**
+ * Check scan phy parameters.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    The advertising parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_check_scan_phy_parameter (ble_abs_scan_phy_parameter_t * p_scan_phy)
+{
+    FSP_ERROR_RETURN((BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->fast_scan_interval) &&
+                     (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->slow_scan_interval) &&
+                     (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->fast_scan_window) &&
+                     (BLE_GAP_SCAN_INTV_MIN <= p_scan_phy->slow_scan_window) &&
+                     (BLE_GAP_SCAN_ACTIVE >= p_scan_phy->scan_type),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Store scan configuration.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Scan phy parameter is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_set_scan_parameter (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                             ble_abs_scan_parameter_t      * p_scan_parameter)
+{
+    if (p_scan_parameter->p_phy_parameter_1M)
+    {
+        FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_check_scan_phy_parameter(p_scan_parameter->p_phy_parameter_1M),
+                         FSP_ERR_INVALID_ARGUMENT); ///< check abs scan parameters 1M
+    }
+
+    if (p_scan_parameter->p_phy_parameter_coded)
+    {
+        FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_check_scan_phy_parameter(p_scan_parameter->p_phy_parameter_coded),
+                         FSP_ERR_INVALID_ARGUMENT); ///< check abs scan parameters coded
+    }
+
+    FSP_ERROR_RETURN(BLE_ABS_CONN_EXT_ADV_DATA_LEN >= p_scan_parameter->filter_data_length, FSP_ERR_INVALID_ARGUMENT);
+
+    memcpy(&p_instance_ctrl->abs_scan.scan_parameter, p_scan_parameter, sizeof(ble_abs_scan_parameter_t));
+    if (p_scan_parameter->p_phy_parameter_1M)
+    {
+        memcpy(&p_instance_ctrl->abs_scan.scan_phy_parameter_1M,
+               p_scan_parameter->p_phy_parameter_1M,
+               sizeof(ble_abs_scan_phy_parameter_t));
+        p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_1M = &p_instance_ctrl->abs_scan.scan_phy_parameter_1M;
+    }
+
+    if (p_scan_parameter->p_phy_parameter_coded)
+    {
+        memcpy(&p_instance_ctrl->abs_scan.scan_phy_parameter_coded,
+               p_scan_parameter->p_phy_parameter_coded,
+               sizeof(ble_abs_scan_phy_parameter_t));
+        p_instance_ctrl->abs_scan.scan_parameter.p_phy_parameter_coded =
+            &p_instance_ctrl->abs_scan.scan_phy_parameter_coded;
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_set_scan_parameter() */
+
+/*******************************************************************************************************************//**
+ * Set scan status.
+ **********************************************************************************************************************/
+static void ble_abs_set_scan_status (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t set, uint32_t clear)
+{
+    p_instance_ctrl->abs_scan.scan_status |= set;
+    p_instance_ctrl->abs_scan.scan_status &= ~clear;
+}                                      /* End of function ble_abs_set_scan_status() */
+
+/*******************************************************************************************************************//**
+ * Register IRK to the Resolving List.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_set_irk_to_resolving_list (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint8_t * p_lc_irk)
+{
+    st_ble_gap_rslv_list_key_set_t peer_irk;
+    ble_device_address_t           remote_device_address;
+    ble_status_t retval = BLE_SUCCESS;
+
+    memset(peer_irk.remote_irk, BLE_ABS_GAP_REMOTE_IRK_AA, BLE_GAP_IRK_SIZE);
+    peer_irk.local_irk_type = BLE_GAP_RL_LOC_KEY_REGISTERED;
+    memset(remote_device_address.addr, BLE_ABS_REMOTE_DEVICE_ADDRESS_55, BLE_BD_ADDR_LEN);
+    remote_device_address.type = BLE_GAP_ADDR_PUBLIC;
+
+    R_BLE_GAP_SetLocIdInfo(&p_instance_ctrl->loc_bd_addr, p_lc_irk);
+
+    /** store local id info */
+    ble_abs_secure_data_writelocinfo(p_instance_ctrl->p_cfg->p_flash_instance,
+                                     (ble_device_address_t *) (&p_instance_ctrl->loc_bd_addr),
+                                     p_lc_irk,
+                                     NULL); ///< store local id info
+
+    retval = R_BLE_GAP_ConfRslvList(BLE_GAP_LIST_ADD_DEV, (st_ble_dev_addr_t *) (&remote_device_address), &peer_irk, 1);
+    p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ? BLE_ABS_PV_STATUS_ADD_RSLV : 0;
+} /* End of function ble_abs_set_irk_to_resolving_list() */
+
+/*******************************************************************************************************************//**
+ * Handler for GAP BLE_GAP_EVENT_RSLV_LIST_CONF_COMP event.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_conflict_resolving_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                                st_ble_evt_data_t             * p_event_data)
+{
+    if (p_instance_ctrl->set_privacy_status)
+    {
+        st_ble_gap_rslv_list_conf_evt_t * p_resolving_list_config;
+        ble_status_t retval = BLE_SUCCESS;
+
+        p_resolving_list_config = (st_ble_gap_rslv_list_conf_evt_t *) p_event_data->p_param;
+        if (BLE_GAP_LIST_ADD_DEV == p_resolving_list_config->op_code)
+        {
+            ble_device_address_t remote_device_address;
+            memset(remote_device_address.addr, BLE_ABS_REMOTE_DEVICE_ADDRESS_55, BLE_BD_ADDR_LEN);
+            remote_device_address.type = 0x00;
+            retval = R_BLE_GAP_SetPrivMode((st_ble_dev_addr_t *) (&remote_device_address),
+                                           &p_instance_ctrl->privacy_mode,
+                                           1);
+            p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ?
+                                                  BLE_ABS_PV_STATUS_SET_MODE :
+                                                  0;
+        }
+    }
+}                                      /* End of function ble_abs_conflict_resolving_handler() */
+
+/*******************************************************************************************************************//**
+ * GAP Event handler.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ **********************************************************************************************************************/
+static void ble_abs_gap_callback (uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = gp_instance_ctrl;
+
+    switch (event_type)
+    {
+        case BLE_GAP_EVENT_STACK_ON:
+        {
+            R_BLE_GAP_GetVerInfo();
+            uint8_t              irk[BLE_GAP_IRK_SIZE];
+            ble_device_address_t identity_address;
+            fsp_err_t            retval;
+
+            ble_abs_secure_data_init(p_instance_ctrl->p_cfg->p_flash_instance);
+            retval = ble_abs_secure_data_readlocinfo(p_instance_ctrl->p_cfg->p_flash_instance,
+                                                     &identity_address,
+                                                     irk,
+                                                     NULL);
+            if (FSP_SUCCESS == retval)
+            {
+                R_BLE_GAP_SetLocIdInfo((st_ble_dev_addr_t *) (&identity_address), irk);
+            }
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_LOC_VER_INFO:
+        {
+            ble_abs_loc_ver_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_REPT_IND:
+        {
+            if (FSP_SUCCESS != ble_abs_advertising_report_handler(p_instance_ctrl, p_event_data))
+            {
+                return;
+            }
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_PARAM_SET_COMP:
+        {
+            ble_abs_advertising_parameter_set_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_DATA_UPD_COMP:
+        {
+            ble_abs_advertising_data_set_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP:
+        {
+            ble_abs_periodic_parameter_handler(p_instance_ctrl);
+            break;
+        }
+
+        case BLE_GAP_EVENT_PERD_ADV_ON:
+        {
+            ble_abs_advertising_start(p_instance_ctrl, BLE_ABS_PERD_HDL);
+            break;
+        }
+
+        case BLE_GAP_EVENT_PERD_ADV_OFF:
+        {
+            ble_abs_set_advertising_status(p_instance_ctrl, BLE_ABS_PERD_HDL, 0, BLE_ABS_ADV_STATUS_PERD_START);
+            break;
+        }
+
+        case BLE_GAP_EVENT_ADV_OFF:
+        {
+            ble_abs_advertising_off_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_SCAN_TO:
+        {
+            ble_abs_scan_to_handler(p_instance_ctrl);
+            break;
+        }
+
+        case BLE_GAP_EVENT_CONN_IND:
+        {
+            ble_abs_connection_indication_handler(p_instance_ctrl);
+            break;
+        }
+
+        case BLE_GAP_EVENT_CONN_PARAM_UPD_REQ:
+        {
+            st_ble_gap_conn_upd_req_evt_t * p_conn_upd_req_evt_param =
+                (st_ble_gap_conn_upd_req_evt_t *) p_event_data->p_param;
+
+            st_ble_gap_conn_param_t conn_updt_param =
+            {
+                .conn_intv_min = p_conn_upd_req_evt_param->conn_intv_min,
+                .conn_intv_max = p_conn_upd_req_evt_param->conn_intv_max,
+                .conn_latency  = p_conn_upd_req_evt_param->conn_latency,
+                .sup_to        = p_conn_upd_req_evt_param->sup_to,
+            };
+
+            R_BLE_GAP_UpdConn(p_conn_upd_req_evt_param->conn_hdl,
+                              BLE_GAP_CONN_UPD_MODE_RSP,
+                              BLE_GAP_CONN_UPD_ACCEPT,
+                              &conn_updt_param);
+            break;
+        }
+
+        case BLE_GAP_EVENT_RSLV_LIST_CONF_COMP:
+        {
+            ble_abs_conflict_resolving_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        case BLE_GAP_EVENT_RPA_EN_COMP:
+        {
+            p_instance_ctrl->set_privacy_status = 0;
+            break;
+        }
+
+        case BLE_GAP_EVENT_PRIV_MODE_SET_COMP:
+        {
+            if (BLE_ABS_PV_STATUS_SET_MODE == p_instance_ctrl->set_privacy_status)
+            {
+                ble_status_t retval = BLE_SUCCESS;
+                retval = R_BLE_GAP_EnableRpa(BLE_GAP_RPA_ENABLED);
+                p_instance_ctrl->set_privacy_status = (BLE_SUCCESS == retval) ?
+                                                      BLE_ABS_PV_STATUS_EN_RPA :
+                                                      0;
+            }
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_PAIRING_REQ:
+        {
+            st_ble_gap_pairing_info_evt_t * p_param;
+            p_param = (st_ble_gap_pairing_info_evt_t *) p_event_data->p_param;
+            R_BLE_GAP_ReplyPairing(p_param->conn_hdl, BLE_GAP_PAIRING_ACCEPT);
+            break;
+        }
+
+        case BLE_GAP_EVENT_PAIRING_COMP:
+        {
+            if (FSP_SUCCESS == event_result)
+            {
+                st_ble_gap_pairing_info_evt_t * p_param;
+                p_param = (st_ble_gap_pairing_info_evt_t *) p_event_data->p_param;
+                ble_abs_secure_data_writeremkeys(p_instance_ctrl->p_cfg->p_flash_instance,
+                                                 (ble_device_address_t *) (&p_param->bd_addr),
+                                                 &p_param->auth_info);
+            }
+
+            break;
+        }
+
+        case BLE_GAP_EVENT_PEER_KEY_INFO:
+        {
+            st_ble_gap_peer_key_info_evt_t * p_param;
+            p_param = (st_ble_gap_peer_key_info_evt_t *) p_event_data->p_param;
+            ble_abs_secure_data_recvremkeys((ble_device_address_t *) (&p_param->bd_addr), &p_param->key_ex_param);
+            break;
+        }
+
+        case BLE_GAP_EVENT_EX_KEY_REQ:
+        {
+            st_ble_gap_conn_hdl_evt_t * p_param;
+            p_param = (st_ble_gap_conn_hdl_evt_t *) p_event_data->p_param;
+            R_BLE_GAP_ReplyExKeyInfoReq(p_param->conn_hdl);
+            break;
+        }
+
+        case BLE_GAP_EVENT_LTK_REQ:
+        {
+            st_ble_gap_ltk_req_evt_t * p_param;
+            p_param = (st_ble_gap_ltk_req_evt_t *) p_event_data->p_param;
+            R_BLE_GAP_ReplyLtkReq(p_param->conn_hdl, p_param->ediv, p_param->p_peer_rand, BLE_GAP_LTK_REQ_ACCEPT);
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    (*p_instance_ctrl).abs_gap_callback(event_type, event_result, p_event_data);
+}                                      /* End of function ble_abs_gap_callback() */
+
+/*******************************************************************************************************************//**
+ * Handler for Vendor Specific BLE_VS_EVENT_GET_RAND event.
+ **********************************************************************************************************************/
+static void ble_abs_random_handler (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                    st_ble_vs_evt_data_t          * p_event_data)
+{
+    if (p_instance_ctrl->set_privacy_status)
+    {
+        st_ble_vs_get_rand_comp_evt_t * p_random_parameter;
+        p_random_parameter = (st_ble_vs_get_rand_comp_evt_t *) p_event_data->p_param;
+        ble_abs_set_irk_to_resolving_list(p_instance_ctrl, p_random_parameter->p_rand);
+    }
+}                                      /* End of function ble_abs_random_handler() */
+
+/*******************************************************************************************************************//**
+ * Vendor Specific Event handler.
+ **********************************************************************************************************************/
+static void ble_abs_vendor_specific_callback (uint16_t               event_type,
+                                              ble_status_t           event_result,
+                                              st_ble_vs_evt_data_t * p_event_data)
+{
+    ble_abs_instance_ctrl_t * p_instance_ctrl = gp_instance_ctrl;
+
+    switch (event_type)
+    {
+        case BLE_VS_EVENT_GET_RAND:
+        {
+            ble_abs_random_handler(p_instance_ctrl, p_event_data);
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    if (p_instance_ctrl->abs_vendor_specific_callback)
+    {
+        p_instance_ctrl->abs_vendor_specific_callback(event_type, event_result, p_event_data);
+    }
+}                                      /* End of function ble_abs_vendor_specific_callback() */
+
+/*** platform control functions added start ***/
+
+void r_ble_rf_control_error (uint32_t err_no)
+{
+    FSP_PARAMETER_NOT_USED(err_no);
+}
+
+uint8_t r_ble_rf_power_save_mode (void)
+{
+    uint8_t ret = BLE_ABS_CFG_RF_DEEP_SLEEP_EN;
+
+    return ret;
+}
+
+#if (BSP_CFG_RTOS == 2)
+void r_ble_wake_up_task (void * EventGroupHandle)
+{
+    EventGroupHandle_t event_group_handle = (EventGroupHandle_t) EventGroupHandle;
+
+    if (event_group_handle != NULL)
+    {
+        xEventGroupSetBits(event_group_handle, (EventBits_t) BLE_EVENT_PATTERN);
+        portYIELD();
+    }
+}
+
+void r_ble_wake_up_task_from_isr (void * EventGroupHandle)
+{
+    BaseType_t xHigherPriorityTaskWoken;
+    xHigherPriorityTaskWoken = pdFALSE;
+    EventGroupHandle_t event_group_handle = (EventGroupHandle_t) EventGroupHandle;
+
+    if (event_group_handle != NULL)
+    {
+        xEventGroupSetBitsFromISR(event_group_handle,
+                                  (EventBits_t) BLE_EVENT_PATTERN,
+                                  &xHigherPriorityTaskWoken);
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+}
+
+#endif
+
+/*** platform control functions end ***/
+
+/*** r_ble_sec_data functions added start ***/
+#if (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1)
+
+/*******************************************************************************************************************//**
+ * Write Local device Identity Address, IRK and/or CSRK in DataFlash.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_POINTER                     IRK(p_lc_id_addr or p_lc_irk) or CSRK(p_lc_csrk)
+ *                                                     is specified and as NULL.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Write to DataFlash is failed.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_writelocinfo (flash_instance_t const * p_instance,
+                                                   ble_device_address_t   * p_lc_id_addr,
+                                                   uint8_t                * p_lc_irk,
+                                                   uint8_t                * p_lc_csrk)
+{
+    uint32_t local_tmp_data[(BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + 3) / 4];
+
+    FSP_ASSERT(p_lc_id_addr);
+    FSP_ASSERT(p_lc_irk);
+    FSP_ASSERT(p_lc_csrk);
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_secure_data_flash_read(p_instance,
+                                                                   BLE_ABS_SECURE_DATA_BASE_ADDR,
+                                                                   (uint8_t *) local_tmp_data,
+                                                                   BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE +
+                                                                   BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE),
+                     FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    if (NULL != p_lc_irk)
+    {
+        memcpy((uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE, p_lc_irk, BLE_GAP_IRK_SIZE);
+        memcpy(
+            (uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE + BLE_GAP_CSRK_SIZE,
+            p_lc_id_addr,
+            BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE);
+    }
+
+    if (NULL != p_lc_csrk)
+    {
+        memcpy((uint8_t *) local_tmp_data + BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE,
+               p_lc_csrk,
+               BLE_GAP_CSRK_SIZE);
+    }
+
+    local_tmp_data[0] = BLE_ABS_SECURE_DATA_MAGIC_NUMBER;
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == ble_abs_secure_data_flash_write(p_instance,
+                                                                    BLE_ABS_SECURE_DATA_BASE_ADDR,
+                                                                    (uint8_t *) local_tmp_data,
+                                                                    BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE +
+                                                                    BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE),
+                     FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_secure_data_writelocinfo() */
+
+/*******************************************************************************************************************//**
+ * Read Local device Identity Address and IRK and/or CSRK in DataFlash.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_POINTER                     IRK(p_lc_id_addr or p_lc_irk) or CSRK(p_lc_csrk)
+ *                                                     is specified and as NULL.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Read to DataFlash is failed.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                           IRK and Identity Address not found.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_readlocinfo (flash_instance_t const * p_instance,
+                                                  ble_device_address_t   * p_lc_id_addr,
+                                                  uint8_t                * p_lc_irk,
+                                                  uint8_t                * p_lc_csrk)
+{
+    fsp_err_t retval;
+    uint8_t * p_loc_area;
+    uint32_t  mgc_num;
+
+    p_loc_area = malloc(BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE);
+    FSP_ERROR_RETURN(NULL != p_loc_area, FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    retval = ble_abs_secure_data_flash_read(p_instance,
+                                            BLE_ABS_SECURE_DATA_ADDR_MGN_DATA,
+                                            p_loc_area,
+                                            BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE +
+                                            BLE_ABS_SECURE_DATA_LOCAL_AREA_SIZE);
+    if (FSP_SUCCESS != retval)
+    {
+        free(p_loc_area);
+        p_loc_area = NULL;
+    }
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == retval, FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    memcpy(&mgc_num, p_loc_area, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE);
+    if ((BLE_ABS_SECURE_DATA_MAGIC_NUMBER != mgc_num) && (NULL == p_loc_area))
+    {
+        free(p_loc_area);
+        p_loc_area = NULL;
+    }
+
+    FSP_ERROR_RETURN(BLE_ABS_SECURE_DATA_MAGIC_NUMBER != mgc_num, FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    if ((NULL != p_lc_irk) && (NULL != p_lc_id_addr))
+    {
+        memcpy(p_lc_irk, &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE], BLE_GAP_IRK_SIZE);
+        memcpy(p_lc_id_addr,
+               &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE + BLE_GAP_CSRK_SIZE],
+               BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE);
+    }
+
+    if (NULL != p_lc_csrk)
+    {
+        memcpy(p_lc_csrk, &p_loc_area[BLE_ABS_SECURE_DATA_MANEGEMENT_DATA_SIZE + BLE_GAP_IRK_SIZE], BLE_GAP_CSRK_SIZE);
+    }
+
+    if (NULL == p_loc_area)
+    {
+        free(p_loc_area);
+    }
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_secure_data_readlocinfo() */
+
+/*******************************************************************************************************************//**
+ * Receive remote keys for write in DataFlash.
+ **********************************************************************************************************************/
+static void ble_abs_secure_data_recvremkeys (ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys)
+{
+    if ((NULL == p_addr) || (NULL == p_keys))
+    {
+        return;
+    }
+
+    (void) p_addr;
+
+    memcpy((uint8_t *) &gs_key_ex_param, (uint8_t *) p_keys, BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE); ///< key_ex_parma
+
+    memcpy((uint8_t *) &gs_key_dist, (uint8_t *) p_keys->p_keys_info, BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE); ///< keys
+} /* End of function ble_abs_secure_data_recvremkeys() */
+
+/*******************************************************************************************************************//**
+ * Write Remote Keys in DataFlash.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_POINTER                     p_addr or p_keyinfo is specified as NULL.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Write to DataFlash is failed.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND              Memory allocation is failed.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_writeremkeys (flash_instance_t const * p_instance,
+                                                   ble_device_address_t   * p_addr,
+                                                   st_ble_gap_auth_info_t * p_keyinfo)
+{
+    fsp_err_t retval = FSP_SUCCESS;
+    int32_t   entry;
+    int32_t   op_code = BLE_SECD_UPD_BN_ADD;
+    uint32_t  start_addr;
+    uint8_t   bond_num;
+    uint8_t * p_sec_data;
+
+    FSP_ASSERT(p_addr);
+    FSP_ASSERT(p_keyinfo);
+
+    p_sec_data = malloc(BLE_ABS_SECURE_DATA_MAX_SIZE); ///< memory allocation
+    FSP_ERROR_RETURN(NULL != p_sec_data, FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    retval = ble_abs_secure_data_flash_read(p_instance,
+                                            BLE_ABS_SECURE_DATA_BASE_ADDR,
+                                            p_sec_data,
+                                            BLE_ABS_SECURE_DATA_MAX_SIZE); ///< read remote area
+    if (FSP_SUCCESS != retval)
+    {
+        free(p_sec_data);
+    }
+
+    FSP_ERROR_RETURN(FSP_SUCCESS == retval, FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    retval = ble_abs_secure_data_find_entry(p_addr, &entry, p_sec_data);   ///< find entry with p_addr
+    if (FSP_SUCCESS != retval)
+    {
+        retval = ble_abs_secure_data_find_entry(NULL, &entry, p_sec_data); ///< find empty entry
+        if (FSP_SUCCESS != retval)
+        {
+            ble_abs_secure_data_find_oldest_entry(p_instance, &entry);     ///< find oldest entry
+
+            op_code = BLE_SECD_UPD_BN_ADD_OVERWR;                          ///< found the entry for overwrite
+        }
+    }
+
+    start_addr = BLE_ABS_SECURE_DATA_ADDR_REM_START + (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE;
+
+    memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE],
+           (uint8_t *) p_addr,
+           BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE);                                                       ///< addr
+
+    gs_key_ex_param.p_keys_info = (st_ble_gap_key_dist_t *) (start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET); ///< ex_key_param
+    memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                       BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET],
+           (uint8_t *) &gs_key_ex_param,
+           BLE_ABS_SECURE_DATA_REMOTE_KEY_ATTRIBUTE_SIZE);
+
+    memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                       BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET],
+           (uint8_t *) &gs_key_dist,
+           BLE_ABS_SECURE_DATA_REMOTE_KEYS_SIZE); ///< keys
+
+    memcpy(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                       BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET],
+           (uint8_t *) p_keyinfo,
+           BLE_ABS_SECURE_DATA_REMOTE_KEYS_INFOMATION_SIZE);                                ///< keyinfo
+
+    ble_abs_secure_data_update_bond_num(p_instance, entry, op_code, &bond_num, p_sec_data); ///< update bond order and the number of bonds.
+
+    p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+               BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE] = bond_num;
+
+    retval = ble_abs_secure_data_flash_write(p_instance,
+                                             BLE_ABS_SECURE_DATA_BASE_ADDR,
+                                             p_sec_data,
+                                             BLE_ABS_SECURE_DATA_MAX_SIZE); ///< write to DataFlash
+    free(p_sec_data);
+
+    return retval;
+} /* End of function ble_abs_secure_data_writeremkeys() */
+
+/*******************************************************************************************************************//**
+ * Set bonding information in DataFlash to Host Stack.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_POINTER                     p_addr or p_keys is specified as NULL.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Number of bonding information is out of range.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_init (flash_instance_t const * p_instance)
+{
+    uint8_t                in_bond_num = 0;
+    uint8_t                out_bond_num;
+    fsp_err_t              ret = FSP_SUCCESS;
+    uint8_t              * p_sec_data;
+    st_ble_gap_bond_info_t bond_info[BLE_ABS_CFG_NUMBER_BONDING] = {0};
+
+    ret = ble_abs_secure_data_read_bond_info(p_instance, &in_bond_num, &p_sec_data, bond_info);
+    FSP_ERROR_RETURN((FSP_SUCCESS == ret) || (FSP_ERR_BLE_ABS_NOT_FOUND == ret), ret); ///< Read bonding information from DataFlash.
+
+    FSP_ERROR_RETURN(0 != in_bond_num, FSP_SUCCESS);                                   ///< No bonding information is written in DataFlash.
+
+    R_BLE_GAP_SetBondInfo(bond_info, in_bond_num, &out_bond_num);                      ///< Set bonding information in DataFlash to Host Stack.
+
+    /** bonding info buffer release */
+    ble_abs_secure_data_release_bond_info_buf(p_sec_data);                             ///< bonding info buffer release
+
+    return ret;
+} /* End of function ble_abs_secure_data_init() */
+
+/*******************************************************************************************************************//**
+ * Find entry.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                           Empty entry is not found.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_find_entry (ble_device_address_t * p_dev_addr,
+                                                 int32_t              * p_entry,
+                                                 uint8_t              * p_sec_data)
+{
+    ble_device_address_t * p_addr;
+    int32_t                i;
+    uint32_t               mgc_num = BLE_ABS_SECURE_DATA_MAGIC_NUMBER;
+    fsp_err_t              retval  = FSP_ERR_BLE_ABS_NOT_FOUND;
+
+    FSP_ERROR_RETURN((NULL == p_dev_addr) ||
+                     (0 == memcmp(p_sec_data, (uint8_t *) &mgc_num, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE)),
+                     FSP_ERR_BLE_ABS_NOT_FOUND); ///< check magic number
+
+    p_addr = (NULL == p_dev_addr) ? (ble_device_address_t *) &invalid_rem_addr : p_dev_addr;
+
+    for (i = 0; i < BLE_ABS_CFG_NUMBER_BONDING; i++)
+    {
+        if (0 ==
+            memcmp(&p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i *
+                               BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE],
+                   p_addr,
+                   BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE))
+        {
+            *p_entry = i;
+            retval   = FSP_SUCCESS;
+        }
+    }
+
+    return retval;
+}                                      /* End of function ble_abs_secure_data_find_entry() */
+
+/*******************************************************************************************************************//**
+ * Find the oldest entry.
+ **********************************************************************************************************************/
+static void ble_abs_secure_data_find_oldest_entry (flash_instance_t const * p_instance, int32_t * p_entry)
+{
+    uint8_t bond_order;
+    int32_t out_bond;
+
+    ble_abs_secure_data_flash_read(p_instance,
+                                   BLE_ABS_SECURE_DATA_ADDR_MGN_DATA + BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET,
+                                   &bond_order,
+                                   1);
+    out_bond = (int32_t) bond_order;
+    *p_entry = out_bond;
+}                                      /* End of function ble_abs_secure_data_find_oldest_entry() */
+
+/*******************************************************************************************************************//**
+ * Update Bond Number
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Magic Numver read or write failuire.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_update_bond_num (flash_instance_t const * p_instance,
+                                                      int32_t                  entry,
+                                                      int32_t                  op_code,
+                                                      uint8_t                * p_alloc_bond_num,
+                                                      uint8_t                * p_sec_data)
+{
+    fsp_err_t retval = FSP_ERR_BLE_ABS_INVALID_OPERATION;
+    uint8_t   bond_num;
+    uint8_t   bond_order;
+
+    bond_num = p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE];
+
+    switch (op_code)
+    {
+        case BLE_SECD_UPD_BN_ADD:
+        case BLE_SECD_UPD_BN_ADD_OVERWR:
+        {
+            /* update bond_num */
+            if (BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF == bond_num)
+            {
+                bond_num = 1;
+                p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = 0;
+                uint32_t mgc_num = BLE_ABS_SECURE_DATA_MAGIC_NUMBER;
+                memcpy(p_sec_data, (uint8_t *) &mgc_num, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE);
+            }
+            else if (BLE_ABS_CFG_NUMBER_BONDING <= bond_num)
+            {
+                bond_num = BLE_ABS_CFG_NUMBER_BONDING;
+            }
+            else
+            {
+                bond_num++;
+            }
+
+            p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE] = bond_num;
+
+            /* update bond order */
+            if (BLE_SECD_UPD_BN_ADD_OVERWR == op_code)
+            {
+                ble_abs_secure_data_update_bond_order(p_instance, entry, p_sec_data, 1);
+            }
+
+            *p_alloc_bond_num = bond_num;
+            retval            = FSP_SUCCESS;
+            break;
+        }
+
+        default:                       /* BLE_SECD_UPD_BN_DEL & BLE_SECD_UPD_BN_ALL_DEL */
+        {
+            if (BLE_ABS_CFG_NUMBER_BONDING >= bond_num)
+            {
+                /* update bond_num */
+                if ((BLE_SECD_UPD_BN_ALL_DEL == op_code) || (0 == bond_num - 1))
+                {
+                    bond_num = BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF;
+                    p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF;
+                }
+                else
+                {
+                    bond_num = (uint8_t) (bond_num - 1);
+                }
+
+                p_sec_data[BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE] = bond_num;
+
+                if (BLE_ABS_SECURE_DATA_UPDATE_BOND_NUMBER_FF != bond_num)
+                {
+                    bond_order = p_sec_data[BLE_ABS_SECURE_DATA_ADDR_REM_START +
+                                            (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                                            BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE];
+                    ble_abs_secure_data_update_bond_order(p_instance, entry, p_sec_data, bond_order);
+                }
+
+                retval = FSP_SUCCESS;
+            }
+
+            break;
+        }
+    }
+
+    return retval;
+}                                      /* End of function ble_abs_secure_data_update_bond_num() */
+
+/*******************************************************************************************************************//**
+ * Check entry validation
+ **********************************************************************************************************************/
+static void ble_abs_secure_data_update_bond_order (flash_instance_t const * p_instance,
+                                                   int32_t                  entry,
+                                                   uint8_t                * p_sec_data,
+                                                   uint8_t                  bond_order)
+{
+    fsp_err_t retval = FSP_ERR_BLE_ABS_INVALID_OPERATION;
+    int32_t   i;
+
+    for (i = 0; i < BLE_ABS_CFG_NUMBER_BONDING; i++)
+    {
+        if (entry != i)
+        {
+            retval = ble_abs_secure_data_is_valid_entry(p_instance, i);
+            if (FSP_SUCCESS != retval)
+            {
+                continue;
+            }
+
+            uint8_t tmp_order;
+            tmp_order =
+                p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                           BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE];
+
+            if (bond_order < tmp_order)
+            {
+                tmp_order = (uint8_t) (tmp_order - 1);
+                p_sec_data[BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + i * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE +
+                           BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE] = tmp_order;
+                if (1 == tmp_order)
+                {
+                    p_sec_data[BLE_ABS_SECURE_DATA_OUT_BONDING_OFFSET] = (uint8_t) i;
+                }
+            }
+        }
+    }
+}                                      /* End of function ble_abs_secure_data_update_bond_order() */
+
+/*******************************************************************************************************************//**
+ * Check entry validation
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Read BD_ADDR is failed.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                           invalid entry
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_is_valid_entry (flash_instance_t const * p_instance, int32_t entry)
+{
+    uint8_t  bd_addr[BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE];
+    uint8_t  invalid_bd_addr[BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE];
+    uint32_t start_addr;
+
+    start_addr = BLE_ABS_SECURE_DATA_ADDR_REM_START + (uint32_t) entry * BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE;
+
+    FSP_ERROR_RETURN(FSP_SUCCESS ==
+                     ble_abs_secure_data_flash_read(p_instance,
+                                                    start_addr,
+                                                    bd_addr,
+                                                    BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE),
+                     FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    memset(invalid_bd_addr, BLE_ABS_SECURE_DATA_BOND_ADDRESS_FF, BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE);
+    FSP_ERROR_RETURN(0 != memcmp(bd_addr, invalid_bd_addr, BLE_ABS_SECURE_DATA_BLUETOOTH_DEVICE_ADDRESS_SIZE),
+                     FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    return FSP_SUCCESS;
+}                                      /* End of function ble_abs_secure_data_is_valid_entry() */
+
+/*******************************************************************************************************************//**
+ * Read Remote bonding information in DataFlash.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND              Memory allocation is failed.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                           No security data is stored in DataFlash.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_read_bond_info (flash_instance_t const * p_instance,
+                                                     uint8_t                * p_out_bond_num,
+                                                     uint8_t               ** pp_sec_data,
+                                                     st_ble_gap_bond_info_t * p_bond_info)
+{
+    fsp_err_t retval = FSP_SUCCESS;
+    int32_t   i;
+    uint32_t  start_addr;
+    uint8_t * p_bonds;
+    uint32_t  magic_num;
+
+    *pp_sec_data = malloc(BLE_ABS_SECURE_DATA_MAX_SIZE);
+    p_bonds      = *pp_sec_data;
+    FSP_ERROR_RETURN(NULL != p_bonds, FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    ble_abs_secure_data_flash_read(p_instance,
+                                   (uint32_t) BLE_ABS_SECURE_DATA_BASE_ADDR,
+                                   p_bonds,
+                                   BLE_ABS_SECURE_DATA_MAX_SIZE);
+
+    /** check magic number and bond number */
+    *p_out_bond_num = 0;
+    memcpy((uint8_t *) &magic_num, p_bonds, BLE_ABS_SECURE_DATA_MAGIC_NUMBER_SIZE);
+    if ((BLE_ABS_SECURE_DATA_MAGIC_NUMBER != magic_num) ||
+        (BLE_ABS_SECURE_DATA_BOND_CHECK_FF == p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]) ||
+        (0x00 == p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]))
+    {
+        free(p_bonds);
+        retval = FSP_ERR_BLE_ABS_NOT_FOUND;
+    }
+
+    FSP_ERROR_RETURN((retval != FSP_ERR_BLE_ABS_NOT_FOUND), FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    if (BLE_ABS_CFG_NUMBER_BONDING < p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET])
+    {
+        free(p_bonds);
+        retval = FSP_ERR_BLE_ABS_NOT_FOUND;
+    }
+
+    FSP_ERROR_RETURN((retval != FSP_ERR_BLE_ABS_NOT_FOUND), FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    for (i = 0; i < p_bonds[BLE_ABS_SECURE_DATA_BONDING_NUMBER_OFFSET]; i++)
+    {
+        start_addr = BLE_ABS_SECURE_DATA_SECURITY_REMOTE_OFFSET + (uint32_t) i *
+                     BLE_ABS_SECURE_DATA_REMOTE_BONDING_SIZE;
+        p_bond_info[i].p_addr      = (st_ble_dev_addr_t *) (p_bonds + start_addr);
+        p_bond_info[i].p_auth_info =
+            (st_ble_gap_auth_info_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_INFOMATION_OFFSET);
+        p_bond_info[i].p_keys =
+            (st_ble_gap_key_ex_param_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_INFOMATION_OFFSET);
+        p_bond_info[i].p_keys->p_keys_info =
+            (st_ble_gap_key_dist_t *) (p_bonds + start_addr + BLE_ABS_SECURE_DATA_SECURITY_KEYS_OFFSET);
+        (*p_out_bond_num)++;
+    }
+
+    return retval;
+}                                      /* End of function ble_abs_secure_data_read_bond_info() */
+
+/*******************************************************************************************************************//**
+ * Release bonding information buffer.
+ **********************************************************************************************************************/
+static void ble_abs_secure_data_release_bond_info_buf (uint8_t * p_sec_data)
+{
+    free(p_sec_data);
+}                                      /* End of function ble_abs_secure_data_release_bond_info_buf() */
+
+#else                                  /* (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) */
+
+/*******************************************************************************************************************//**
+ * Write Local device Identity Address, IRK and/or CSRK in DataFlash.
+ * @retval FSP_ERR_UNSUPPORTED                                 This feature is not supported in this configuration.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_writelocinfo (flash_instance_t const * p_instance,
+                                                   ble_device_address_t   * p_lc_id_addr,
+                                                   uint8_t                * p_lc_irk,
+                                                   uint8_t                * p_lc_csrk)
+{
+    (void) p_instance;
+    (void) p_lc_id_addr;
+    (void) p_lc_irk;
+    (void) p_lc_csrk;
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+/*******************************************************************************************************************//**
+ * Read Local device Identity Address and IRK and/or CSRK in DataFlash.
+ * @retval FSP_ERR_UNSUPPORTED                                 This feature is not supported in this configuration.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_readlocinfo (flash_instance_t const * p_instance,
+                                                  ble_device_address_t   * p_lc_id_addr,
+                                                  uint8_t                * p_lc_irk,
+                                                  uint8_t                * p_lc_csrk)
+{
+    (void) p_instance;
+    (void) p_lc_id_addr;
+    (void) p_lc_irk;
+    (void) p_lc_csrk;
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+static void ble_abs_secure_data_recvremkeys (ble_device_address_t * p_addr, st_ble_gap_key_ex_param_t * p_keys)
+{
+    (void) p_addr;
+    (void) p_keys;
+}
+
+/*******************************************************************************************************************//**
+ * Write Remote Keys in DataFlash.
+ * @retval FSP_ERR_UNSUPPORTED                                 This feature is not supported in this configuration.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_writeremkeys (flash_instance_t const * p_instance,
+                                                   ble_device_address_t   * p_addr,
+                                                   st_ble_gap_auth_info_t * p_keyinfo)
+{
+    (void) p_instance;
+    (void) p_addr;
+    (void) p_keyinfo;
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+/*******************************************************************************************************************//**
+ * Set bonding information in DataFlash to Host Stack.
+ * @retval FSP_ERR_UNSUPPORTED                                 This feature is not supported in this configuration.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_secure_data_init (flash_instance_t const * p_instance)
+{
+    (void) p_instance;
+
+    return FSP_ERR_UNSUPPORTED;
+}
+
+#endif                                 /* (BLE_ABS_CFG_ENABLE_SECURE_DATA == 1) */
+
+/**************************************************************************************//**
+ * Read the value of the specified data flash
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    parameter is invalid.
+ *****************************************************************************************/
+static fsp_err_t ble_abs_secure_data_flash_read (flash_instance_t const * p_instance,
+                                                 uint32_t                 addr,
+                                                 uint8_t                * buff,
+                                                 uint16_t                 len)
+{
+    fsp_err_t    err       = FSP_SUCCESS;
+    uint8_t    * p_address = (uint8_t *) addr;
+    flash_info_t info;
+
+    /* Open driver */
+    err = p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg);
+
+    /* Check for a valid address. */
+    if (FSP_SUCCESS != err)
+    {
+        err = p_instance->p_api->infoGet(p_instance->p_ctrl, &info);
+
+        if (((addr) < info.data_flash.p_block_array->block_section_st_addr) ||
+            ((addr + len) >= info.data_flash.p_block_array->block_section_end_addr))
+        {
+            err = FSP_ERR_INVALID_ARGUMENT;
+        }
+    }
+
+    /* Directly read data flush*/
+    while ((len--) && (FSP_SUCCESS == err))
+    {
+        *buff++ = *p_address++;
+    }
+
+    /* Close driver */
+    p_instance->p_api->close(p_instance->p_ctrl);
+
+    return err;
+}
+
+/**************************************************************************************//**
+ * Write data flash and Read data that has already been written and overwrite the value.
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    parameter is invalid.
+ *****************************************************************************************/
+static fsp_err_t ble_abs_secure_data_flash_write (flash_instance_t const * p_instance,
+                                                  uint32_t                 addr,
+                                                  uint8_t                * buff,
+                                                  uint16_t                 len)
+{
+    fsp_err_t    err        = FSP_SUCCESS;
+    uint8_t    * block_addr = (uint8_t *) (addr & ~BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK);
+    uint16_t     offset     = (uint16_t) (addr & BLE_ABS_SECURE_DATA_BLOCK_SIZE_MASK);
+    uint32_t     i;
+    flash_info_t info;
+    uint8_t      temporary_buffer[BLE_ABS_SECURE_DATA_BLOCK_SIZE];
+
+    /* Open driver */
+    if (FSP_SUCCESS != err)
+    {
+        err = p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg);
+    }
+
+    /* Check for a valid address. */
+    if (FSP_SUCCESS != err)
+    {
+        err = p_instance->p_api->infoGet(p_instance->p_ctrl, &info);
+
+        if (((addr) < info.data_flash.p_block_array->block_section_st_addr) ||
+            ((addr + len) >= info.data_flash.p_block_array->block_section_end_addr))
+        {
+            err = FSP_ERR_INVALID_ARGUMENT;
+        }
+    }
+
+    while (FSP_SUCCESS != err)
+    {
+        /* set write data */
+        for (i = 0; i < BLE_ABS_SECURE_DATA_BLOCK_SIZE; i++)
+        {
+            if ((i >= offset) && (i < (offset + len)))
+            {
+                temporary_buffer[i] = *buff++;
+            }
+            else
+            {
+                temporary_buffer[i] = block_addr[i];
+            }
+        }
+
+        /* Erase data block */
+        err = p_instance->p_api->erase(p_instance->p_ctrl, (uint32_t) block_addr, 1);
+
+        /* Write data flash */
+        if (FSP_SUCCESS != err)
+        {
+            err = p_instance->p_api->write(p_instance->p_ctrl,
+                                           (uint32_t) temporary_buffer,
+                                           (uint32_t) block_addr,
+                                           BLE_ABS_SECURE_DATA_BLOCK_SIZE);
+        }
+    }
+
+    /* Close driver */
+    p_instance->p_api->close(p_instance->p_ctrl);
+
+    return err;
+}
+
+uint8_t r_dflash_read (uint32_t addr, uint8_t * buff, uint16_t len) {
+    ble_abs_secure_data_flash_read(gp_instance_ctrl->p_cfg->p_flash_instance, addr, buff, len);
+
+    return FSP_SUCCESS;
+}
+
+uint8_t r_dflash_write (uint32_t addr, uint8_t * buff, uint16_t len) {
+    ble_abs_secure_data_flash_write(gp_instance_ctrl->p_cfg->p_flash_instance, addr, buff, len);
+
+    return FSP_SUCCESS;
+}
+
+/*** r_ble_sec_data functions added end ***/
+
+static void ble_abs_timer_update_remaining_time_ms (ble_abs_instance_ctrl_t * const p_instance_ctrl, bool expired)
+{
+    uint32_t elapsed_time_ms = ble_abs_get_elapsed_time_ms(p_instance_ctrl->p_cfg->p_timer_instance,
+                                                           expired,
+                                                           p_instance_ctrl->current_timeout_ms,
+                                                           &p_instance_ctrl->elapsed_timeout_ms);
+
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        if (BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status)
+        {
+            p_instance_ctrl->timer[i].remaining_time_ms -= elapsed_time_ms;
+        }
+    }
+}
+
+static uint32_t ble_abs_timer_alloc_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        if (p_instance_ctrl->timer[i].status == BLE_TIMER_STATUS_FREE)
+        {
+            p_instance_ctrl->timer[i].status = BLE_TIMER_STATUS_IDLE;
+
+            return i;
+        }
+    }
+
+    return BLE_TIMER_INVALID_HDL;
+}
+
+static void ble_abs_timer_free_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl)
+{
+    p_instance_ctrl->timer[timer_hdl].status     = BLE_TIMER_STATUS_FREE;
+    p_instance_ctrl->timer[timer_hdl].timer_hdl  = BLE_TIMER_INVALID_HDL;
+    p_instance_ctrl->timer[timer_hdl].timeout_ms = 0;
+    p_instance_ctrl->timer[timer_hdl].type       = BLE_TIMER_ONE_SHOT;
+    p_instance_ctrl->timer[timer_hdl].cb         = NULL;
+}
+
+static void ble_abs_timer_start_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    uint32_t next_hdl = BLE_TIMER_INVALID_HDL;
+    uint32_t shortest = BLE_ABS_TIMER_REMAIN_TIMESHORTEST;
+
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        if ((BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status) &&
+            (shortest > p_instance_ctrl->timer[i].remaining_time_ms))
+        {
+            shortest = p_instance_ctrl->timer[i].remaining_time_ms;
+            next_hdl = i;
+        }
+    }
+
+    if (BLE_TIMER_INVALID_HDL != next_hdl)
+    {
+        ble_abs_start_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance,
+                               &p_instance_ctrl->current_timeout_ms,
+                               &p_instance_ctrl->elapsed_timeout_ms,
+                               p_instance_ctrl->timer[next_hdl].remaining_time_ms);
+    }
+}
+
+static void ble_abs_timer_stop_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    ble_abs_stop_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance,
+                          &p_instance_ctrl->current_timeout_ms,
+                          &p_instance_ctrl->elapsed_timeout_ms);
+}
+
+static void ble_abs_timer_add_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl)
+{
+    p_instance_ctrl->timer[timer_hdl].status            = BLE_TIMER_STATUS_STARTED;
+    p_instance_ctrl->timer[timer_hdl].remaining_time_ms = p_instance_ctrl->timer[timer_hdl].timeout_ms;
+}
+
+static void ble_abs_timer_remove_timer (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl)
+{
+    p_instance_ctrl->timer[timer_hdl].status = BLE_TIMER_STATUS_IDLE;
+}
+
+static void ble_abs_timer_event_cb (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        if (BLE_TIMER_STATUS_EXPIRED == p_instance_ctrl->timer[i].status)
+        {
+            p_instance_ctrl->timer[i].cb(i);
+
+            if (BLE_TIMER_PERIODIC == p_instance_ctrl->timer[i].type)
+            {
+                ble_abs_timer_add_timer(p_instance_ctrl, i);
+            }
+            else
+            {
+                ble_abs_timer_remove_timer(p_instance_ctrl, i);
+            }
+        }
+    }
+
+    ble_abs_timer_stop_timer(p_instance_ctrl);
+    ble_abs_timer_start_timer(p_instance_ctrl);
+}
+
+void ble_abs_timer_process_timer_expire (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, true);
+
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        if ((BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[i].status) &&
+            (0 == p_instance_ctrl->timer[i].remaining_time_ms))
+        {
+            p_instance_ctrl->timer[i].status = BLE_TIMER_STATUS_EXPIRED;
+            ble_abs_timer_event_cb(p_instance_ctrl);
+        }
+    }
+
+    ble_abs_timer_start_timer(p_instance_ctrl);
+}
+
+static void ble_abs_timer_init (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        ble_abs_timer_free_timer(p_instance_ctrl, i);
+    }
+
+    ble_abs_init_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance);
+}
+
+static void ble_abs_timer_terminate (ble_abs_instance_ctrl_t * const p_instance_ctrl)
+{
+    for (uint32_t i = 0; i < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT; i++)
+    {
+        ble_abs_timer_free_timer(p_instance_ctrl, i);
+    }
+
+    ble_abs_terminate_hw_timer(p_instance_ctrl->p_cfg->p_timer_instance);
+}
+
+/*******************************************************************************************************************//**
+ * Create timer for communication.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_NOT_FOUND                   Couldn't find a valid timer.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Invalid parameter is given.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_timer_create (ble_abs_instance_ctrl_t * const p_instance_ctrl,
+                                       uint32_t                      * p_timer_hdl,
+                                       uint32_t                        timeout_ms,
+                                       uint8_t                         type,
+                                       ble_abs_timer_cb_t              cb)
+{
+    uint32_t timer_hdl;
+
+    FSP_ERROR_RETURN((NULL != p_timer_hdl) && (timeout_ms != 0) && (NULL != cb) &&
+                     ((type == BLE_TIMER_ONE_SHOT) || (type == BLE_TIMER_PERIODIC)),
+                     FSP_ERR_INVALID_ARGUMENT);
+
+    timer_hdl = ble_abs_timer_alloc_timer(p_instance_ctrl);
+
+    FSP_ERROR_RETURN((timer_hdl != BLE_TIMER_INVALID_HDL), FSP_ERR_BLE_ABS_NOT_FOUND);
+
+    *p_timer_hdl = timer_hdl;
+
+    p_instance_ctrl->timer[timer_hdl].timeout_ms = timeout_ms;
+    p_instance_ctrl->timer[timer_hdl].type       = type;
+    p_instance_ctrl->timer[timer_hdl].cb         = cb;
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Delete timer for communication.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Invalid operation for the selected timer.
+ * @retval FSP_ERR_INVALID_ARGUMENT                    Invalid timer handle.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_timer_delete (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t * p_timer_hdl)
+{
+    FSP_ERROR_RETURN((NULL != p_timer_hdl), FSP_ERR_INVALID_ARGUMENT);
+
+    uint32_t timer_hdl = *p_timer_hdl;
+    FSP_ERROR_RETURN((BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT > timer_hdl), FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    *p_timer_hdl = BLE_TIMER_INVALID_HDL;
+
+    if (BLE_TIMER_STATUS_STARTED == p_instance_ctrl->timer[timer_hdl].status)
+    {
+        ble_abs_timer_stop(p_instance_ctrl, timer_hdl);
+    }
+
+    ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false);
+    ble_abs_timer_stop_timer(p_instance_ctrl);
+    ble_abs_timer_remove_timer(p_instance_ctrl, timer_hdl);
+    ble_abs_timer_free_timer(p_instance_ctrl, timer_hdl);
+    ble_abs_timer_start_timer(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Start timer for communication.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Invalid operation for the selected timer.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_timer_start (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl)
+{
+    FSP_ERROR_RETURN((timer_hdl < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT), FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    FSP_ERROR_RETURN((BLE_TIMER_STATUS_FREE != p_instance_ctrl->timer[timer_hdl].status) &&
+                     (BLE_TIMER_STATUS_EXPIRED != p_instance_ctrl->timer[timer_hdl].status),
+                     FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false);
+    ble_abs_timer_stop_timer(p_instance_ctrl);
+    ble_abs_timer_add_timer(p_instance_ctrl, timer_hdl);
+    ble_abs_timer_start_timer(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+/*******************************************************************************************************************//**
+ * Stop timer for communication.
+ *
+ * @retval FSP_SUCCESS                                 Operation succeeded.
+ * @retval FSP_ERR_BLE_ABS_INVALID_OPERATION           Invalid operation for the selected timer.
+ **********************************************************************************************************************/
+static fsp_err_t ble_abs_timer_stop (ble_abs_instance_ctrl_t * const p_instance_ctrl, uint32_t timer_hdl)
+{
+    FSP_ERROR_RETURN((timer_hdl < BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT), FSP_ERR_BLE_ABS_INVALID_OPERATION);
+
+    ble_abs_timer_update_remaining_time_ms(p_instance_ctrl, false);
+    ble_abs_timer_stop_timer(p_instance_ctrl);
+    ble_abs_timer_remove_timer(p_instance_ctrl, timer_hdl);
+    ble_abs_timer_start_timer(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+static void ble_abs_init_hw_timer (timer_instance_t const * p_instance)
+{
+    p_instance->p_api->open(p_instance->p_ctrl, p_instance->p_cfg);
+}
+
+static void ble_abs_terminate_hw_timer (timer_instance_t const * p_instance)
+{
+    p_instance->p_api->stop(p_instance->p_ctrl);
+    p_instance->p_api->close(p_instance->p_ctrl);
+}
+
+static void ble_abs_start_hw_timer (timer_instance_t const * p_instance,
+                                    uint32_t               * current_timeout_ms,
+                                    uint32_t               * elapsed_timeout_ms,
+                                    uint32_t                 timeout_ms)
+{
+    uint32_t     timer_count;
+    timer_info_t timer_info;
+
+    if (timeout_ms > BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS)
+    {
+        *current_timeout_ms = BLE_ABS_TIMER_DEFAULT_TIMEOUT_MS;
+    }
+    else
+    {
+        *current_timeout_ms = timeout_ms;
+    }
+
+    *elapsed_timeout_ms = 0;
+
+    p_instance->p_api->infoGet(p_instance->p_ctrl, &timer_info);
+
+    timer_count = *current_timeout_ms * (timer_info.clock_frequency / BLE_ABS_TIMER_METRIC_PREFIX);
+    p_instance->p_api->periodSet(p_instance->p_ctrl, timer_count);
+    p_instance->p_api->start(p_instance->p_ctrl);
+}
+
+static void ble_abs_stop_hw_timer (timer_instance_t const * p_instance,
+                                   uint32_t               * current_timeout_ms,
+                                   uint32_t               * elapsed_timeout_ms)
+{
+    *current_timeout_ms = 0;
+    *elapsed_timeout_ms = 0;
+    p_instance->p_api->stop(p_instance->p_ctrl);
+}
+
+void ble_abs_hw_timer_callback (timer_callback_args_t * callback_args)
+{
+    ble_abs_instance_t * p_instance = (ble_abs_instance_t *) callback_args->p_context;
+    ble_abs_timer_process_timer_expire(p_instance->p_ctrl);
+}
+
+static uint32_t ble_abs_get_elapsed_time_ms (timer_instance_t const * p_instance,
+                                             bool                     expired,
+                                             const uint32_t           current_timeout_ms,
+                                             uint32_t               * elapsed_timeout_ms)
+{
+    uint32_t elapsed_time_from_prev_update_ms = 0;
+    uint32_t total_elapsed_timeout_ms;
+
+    timer_status_t status;
+    timer_info_t   info;
+
+    p_instance->p_api->statusGet(p_instance->p_ctrl, &status);
+    p_instance->p_api->infoGet(p_instance->p_ctrl, &info);
+
+    if (expired)
+    {
+        elapsed_time_from_prev_update_ms = current_timeout_ms - *elapsed_timeout_ms;
+        *elapsed_timeout_ms              = current_timeout_ms;
+    }
+    else if (status.state == TIMER_STATE_COUNTING)
+    {
+        total_elapsed_timeout_ms         = (status.counter / info.clock_frequency) / BLE_ABS_TIMER_METRIC_PREFIX;
+        elapsed_time_from_prev_update_ms = total_elapsed_timeout_ms - *elapsed_timeout_ms;
+        *elapsed_timeout_ms              = total_elapsed_timeout_ms;
+    }
+    else if (0 == current_timeout_ms)
+    {
+        elapsed_time_from_prev_update_ms = 0;
+    }
+    else
+    {
+    }
+
+    return elapsed_time_from_prev_update_ms;
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/port.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/port.c
new file mode 100644
index 0000000000..0ce4cc3cdc
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/port.c
@@ -0,0 +1,1090 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for RA MCUs
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOSConfig.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "bsp_api.h"
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+
+/* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT    (SysTick_CTRL_CLKSOURCE_Msk)
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT    (0)
+#endif
+
+/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#if 0U == configMAX_SYSCALL_INTERRUPT_PRIORITY
+ #error "configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0"
+#endif
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER    (16)
+#define portTOP_BIT_OF_BYTE                ((uint8_t) 0x80)
+#define portMAX_PRIGROUP_BITS              ((uint8_t) 7)
+#define portPRIORITY_GROUP_MASK            (0x07UL << 8UL)
+#define portPRIGROUP_SHIFT                 (8UL)
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                   (0x01000000)
+#define portINITIAL_EXC_RETURN             (0xfffffffd)
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER              (0xffffffUL)
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK             ((StackType_t) 0xfffffffeUL)
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS           configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS           prvTaskExitError
+#endif
+
+/* Used to convert an evaluated macro into a string. */
+#define RM_FREERTOS_PORT_STRINGIFY_EXPANDED(s)    RM_FREERTOS_PORT_STRINGIFY(s)
+
+/* Used to convert text into a string. */
+#define RM_FREERTOS_PORT_STRINGIFY(s)             #s
+
+/* The maximum allowed end address of the process stack monitor. */
+#define RM_FREERTOS_PORT_MAX_SPMON_EA                  (0x200FFFFFU)
+
+/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
+#define RM_FREERTOS_PORT_SPMON_NMI_ON_DETECTION        (0xA500U)
+
+#define RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS    (0xA502U)
+#define RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS      (0xA500U)
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__clang__)
+ #define RM_FREERTOS_PORT_NAKED_FUNCTION               __attribute__((naked, no_instrument_function, \
+                                                                      no_profile_instrument_function))
+#else
+ #define RM_FREERTOS_PORT_NAKED_FUNCTION               __attribute__((naked))
+#endif
+
+/*-----------------------------------------------------------*/
+
+extern volatile uint32_t pxCurrentTCB;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt(void);
+
+/*
+ * Exception handlers.
+ */
+void PendSV_Handler(void) RM_FREERTOS_PORT_NAKED_FUNCTION;
+void SysTick_Handler(void);
+void SVC_Handler(void) RM_FREERTOS_PORT_NAKED_FUNCTION;
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask(void);
+
+#ifndef configTASK_RETURN_ADDRESS
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError(void);
+
+#endif
+
+/*
+ * Subroutines used by the RA port. See comment header above implementation
+ * for details. These functions cannot be static because they are called
+ * from inline assembly.
+ */
+void rm_freertos_port_restore_task_stackless(void) RM_FREERTOS_PORT_NAKED_FUNCTION;
+void rm_freertos_port_stack_monitor_cfg(uint32_t psp);
+void rm_freertos_port_sleep_preserving_lpm(uint32_t xExpectedIdleTime);
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0U;
+
+/* The mask level is saved before disabling interrupts so it can be restored
+ * when the critical section exits. */
+static uint32_t g_mask_level_before_disable = 0U;
+
+/* This stores the reload value calculated for the SysTick when tickless idle
+ * is used. */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t g_reset_systick = 0U;
+#endif
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t ulTimerCountsForOneTick = 0;
+#endif                                 /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif                                 /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if (configASSERT_DEFINED == 1)
+static uint8_t ucMaxSysCallPriority = 0;
+ #ifdef __ARM_ARCH_7EM__
+static uint32_t ulMaxPRIGROUPValue = 0;
+ #endif
+#endif                                 /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/***********************************************************************************************************************
+ * This interrupt is called to start the first task.
+ **********************************************************************************************************************/
+void SVC_Handler (void)
+{
+    /* This is a naked/stackless function. Do not pass arguments to the inline assembly when the GCC compiler is
+     * used. */
+    __asm volatile (
+#if defined(__GNUC__)
+        ".syntax unified                         \n"
+#endif
+
+        /* Restore the first task from the saved state created during pxPortInitialiseStack(). */
+        "B       rm_freertos_port_restore_task_stackless  \n"
+        );
+}
+
+/***********************************************************************************************************************
+ * Resets the FPU lazy stacking, configures the hardware stack monitor, enables interrupts, and requests an SVC
+ * interrupt. The first task is started in the SVC interrupt.
+ **********************************************************************************************************************/
+static void prvPortStartFirstTask (void)
+{
+    /* Start the first task.  This also clears the bit that indicates the FPU is in use in case the FPU was used before
+     * the scheduler was started - which would otherwise result in the unnecessary leaving of space in the main stack
+     * for saving FPU registers. */
+
+#if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+
+    /* Configure the PSP stack monitor.  */
+
+    /* Disable PSP monitoring  */
+    R_MPU_SPMON->SP[1].CTL = 0;
+
+    /* Setup NMI interrupt  */
+    R_MPU_SPMON->SP[1].OAD = RM_FREERTOS_PORT_SPMON_NMI_ON_DETECTION;
+
+    /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need
+     * to read-modify-write. */
+    R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;
+
+ #if !configRECORD_STACK_HIGH_ADDRESS
+
+    /* If the end address is not stored in the TCB, the PSP stack monitor end address is set to the maximum value.
+     * A stack underflow cannot be detected by the hardware stack monitor in this case. */
+    R_MPU_SPMON->SP[1].EA = RM_FREERTOS_PORT_MAX_SPMON_EA;
+ #endif
+#endif
+
+    /** Enable interrupts */
+
+    /* CPSIE that performs interrupt enabling is not guaranteed to be self synchronizing, with the architecture
+     * guaranteeing the recognition of the change only following an ISB. The same is true for MSR to CONTROL for
+     * stack-pointer selection and privilege level.
+     * Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHHFHJB.html */
+    __enable_irq();
+    __ISB();
+
+    __asm volatile (
+
+#if __FPU_USED
+
+        /* Reset lazy stacking if the MCU has an FPU by clearing the FPCA bit in CONTROL. */
+
+        /* The ISB instruction flushes the pipeline in Cortex-M processors and ensures effects of all context altering
+         * operations prior to the ISB are recognized by subsequent operations. It should be used after the CONTROL
+         * register is updated. Source:
+         * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/index.html&_ga=2.198390767.1711886109.1566228944-1408114765.1566228570 */
+        "MRS    R12, CONTROL                     \n"
+        "BIC    R12, R12, #4                     \n"
+        "MSR    CONTROL, R12                     \n"
+        "ISB                                     \n"
+#endif
+
+        /* Supervisor call to start first task. This pends the SVC_Handler. */
+        "SVC    0                                \n"
+        );
+
+    /* FreeRTOS never exits, so this should be unreachable.  */
+    while (1)
+    {
+        __BKPT(0);
+    }
+}
+
+/***********************************************************************************************************************
+ * This interrupt is called to execute a context switch.
+ **********************************************************************************************************************/
+void PendSV_Handler (void)
+{
+    /* This function is assembly only to meet the requirements for naked/stackless functions. For GCC, only basic
+     * assembly is allowed. */
+
+    /* Before entry into this exception handler, the hardware stacks XPSR, PC, LR, R12, R3, R2, R1, and R0 onto the
+     * stack (typically the process stack of the executing task). When the FPU is in use, the FPSCR and S0-S15
+     * registers are also stored on the stack. All other registers are stored by software in this function. */
+
+    /* Only R0-R3 and R12 can be used before stack preservation is complete. */
+
+    /* R0-R3 and R12 are not guaranteed to retain their values after C functions are called. The main stack is used
+     * when C functions are called. */
+
+    __asm volatile (
+#if defined(__GNUC__)
+        ".syntax unified                         \n"
+#endif
+
+        /* Store the address of pxCurrentTCB in R0. */
+        /* R0 = &pxCurrentTCB */
+        /* R1 = pxCurrentTCB */
+        "LDR     R0, =pxCurrentTCB               \n"
+        "LDR     R1, [R0]                        \n"
+
+        /* Store PSP in R2 so it can be used with STM instructions.  */
+        /* R2 = PSP */
+        "MRS     R2,  PSP                        \n"
+#if __FPU_USED
+
+        /* Check to see if the current thread is using the FPU. If so, stack S16-S31. */
+        "TST     LR, #0x10                       \n"
+        "BNE     _skip_vfp_save                  \n"
+        "VSTMDB  R2!,{S16-S31}                   \n"
+        "_skip_vfp_save:                         \n"
+
+        /* Stack R4-R11 on the process stack. Also stack LR since the FPU is supported. */
+        "STMDB   R2!, {R4-R11, LR}               \n"
+
+        /* Save the new top of the stack into the first member of the TCB. */
+        "STR R2, [R1]                            \n"
+
+ #if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+
+        /* If the stack monitor is used, also update PSP  to the new top of the stack. If a stack overflow has
+         * occurred during this context switch, it is detected by the hardware stack monitor here. */
+        "MSR     PSP, R2                         \n"
+ #endif
+#else                                  /* __FPU_USED */
+
+        /* Currently, all RA MCUs that do not have an FPU also do not support the DB (decrement before) instruction suffix
+         * of STM. Because the register pointing to the top of the stack is incremented after each store in STMIA, we
+         * must allocate space prior to saving registers. */
+
+        /* Allocate 32 bytes of stack space to stack R4-R11. */
+        "SUBS    R2, R2, #32                     \n"
+
+        /* Save the new top of the stack into the first member of the TCB. */
+        "STR R2, [R1]                            \n"
+ #if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+
+        /* If the stack monitor is used, also update PSP  to the new top of the stack. If a stack overflow has
+         * occurred during this context switch, it is detected by the hardware stack monitor here. */
+        "MSR     PSP, R2                         \n"
+ #endif
+
+        /* CM23 stack frame (higher addresses on top):
+         * Task saved R2/PSP ->  R11
+         *                       R10
+         *                       R9
+         *                       R8
+         *                       R7
+         *                       R6
+         *                       R5
+         *                       R4
+         * Task return R2/PSP ->
+         *//* Stack R4-R7, then move R8-R11 into R4-R7 and stack them again. */
+        "STMIA   R2!, {R4-R7}                    \n"
+        "MOV     R4, R8                          \n"
+        "MOV     R5, R9                          \n"
+        "MOV     R6, R10                         \n"
+        "MOV     R7, R11                         \n"
+        "STMIA   R2!, {R4-R7}                    \n"
+#endif                                 /* __FPU_USED */
+
+        /* Stack preservation is complete. */
+
+        /* Disable interrupts that could interfere with FreeRTOS during vTaskSwitchContext(). This is done by
+         * setting BASEPRI to configMAX_SYSCALL_INTERRUPT_PRIORITY on MCUs that have BASEPRI to mask interrupts
+         * of equal or lower priority than configMAX_SYSCALL_INTERRUPT_PRIORITY. On MCUs that do not have BASEPRI,
+         * this is done by disabling interrupts globally. *//* If BASEPRI is set in the application code we won't end up here because PendSV is the lowest priority. */
+#if RM_FREERTOS_PORT_HAS_BASEPRI
+        "LDR     R0, = "RM_FREERTOS_PORT_STRINGIFY_EXPANDED (configMAX_SYSCALL_INTERRUPT_PRIORITY)
+        "                                        \n"
+        "MSR     BASEPRI, R0                     \n"
+        "DSB                                     \n"
+        "ISB                                     \n"
+#else                                  /* RM_FREERTOS_PORT_HAS_BASEPRI */
+        "CPSID   i                               \n"
+#endif /* RM_FREERTOS_PORT_HAS_BASEPRI */
+
+        /* Call vTaskSwitchContext(). In this function, pxCurrentTCB is updated to the next task to run. */
+        "BL      vTaskSwitchContext              \n"
+
+        /* Restore interrupts. This is done by unmasking all interrupts in BASEPRI if the MCU has BASEPRI,
+         * or by reenabling interrupts globally if the MCU does not have BASEPRI. */
+#if RM_FREERTOS_PORT_HAS_BASEPRI
+        "MOV     R0, #0                          \n"
+        "MSR     BASEPRI, R0                     \n"
+#else
+        "CPSIE   i                               \n"
+#endif
+
+        /* Restore the task. This function does not return. */
+        "B rm_freertos_port_restore_task_stackless \n"
+        );
+}
+
+#if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+
+/***********************************************************************************************************************
+ * Disables the process stack monitor, configures the stack start and end address for the new task and sets the PSP for
+ * the new task, then reenables the process stack monitor.
+ *
+ * @param[in]  psp  PSP for the new task
+ **********************************************************************************************************************/
+void rm_freertos_port_stack_monitor_cfg (uint32_t psp)
+{
+    /* Setup the Hardware Stack Monitor for next task.  */
+
+    /* Disable PSP monitoring  */
+    R_MPU_SPMON->SP[1].CTL = 0;
+
+    /* Setup start address  */
+
+    /* Bits 0 and 1 of pxCurrentTCB->pxStack are always 0 since the stack must be aligned on an 8 byte boundary. */
+    StaticTask_t * p_current_task = (StaticTask_t *) pxCurrentTCB;
+ #define pxStack    pxDummy6
+    R_MPU_SPMON->SP[1].SA = (uint32_t) p_current_task->pxStack;
+ #undef pxStack
+
+ #if configRECORD_STACK_HIGH_ADDRESS
+
+    /* Setup end address if it is available. If it is not stored in the TCB, the end address was configured
+     * earlier in prvPortStartFirstTask(). */
+
+    /* Bits 0 and 1 of pxCurrentTCB->pxEndOfStack are always 0 since the stack must be aligned on an 8 byte
+     * boundary and a multiple of 8 bytes. Or with 3 to ensure they are set. */
+  #define pxEndOfStack    pxDummy8
+    R_MPU_SPMON->SP[1].EA = (uint32_t) p_current_task->pxEndOfStack | 3U;
+  #undef pxEndOfStack
+ #endif
+
+    /* Set the new PSP. */
+    __set_PSP(psp);
+
+    /* Enable PSP monitoring after configuring the start and end addresses and the PSP for the new thread. */
+    R_MPU_SPMON->SP[1].CTL = 1;
+}
+
+#endif
+
+/***********************************************************************************************************************
+ * Subroutine to restore a task.
+ *
+ * @note This function does not return to the calling function. It returns to the task being restored. Branch to this
+ * function without link (B instruction, not BL).
+ **********************************************************************************************************************/
+void rm_freertos_port_restore_task_stackless (void)
+{
+    /* This is a naked/stackless function. Do not pass arguments to the inline assembly when the GCC compiler is
+     * used. */
+
+    __asm volatile (
+#if defined(__GNUC__)
+        ".syntax unified                         \n"
+#endif
+
+        /* Restore the thread context and PSP.  */
+
+        /* The first item in pxCurrentTCB is the task top of stack. */
+        /* R0 = &pxCurrentTCB */
+        /* R1 = pxCurrentTCB */
+        /* R2 = pxCurrentTCB[0] = pxCurrentTCB->pxStack */
+        "LDR     R0, =pxCurrentTCB               \n"
+        "LDR     R1, [R0]                        \n"
+        "LDR     R2, [R1]                        \n"
+
+#if __FPU_USED
+
+        /* Restore R4-R11 and LR from the process stack. */
+        "LDMIA   R2!, {R4-R11, LR}               \n"
+
+        /* Check to see if the thread being restored is using the FPU. If so, restore S16-S31. */
+        "TST     LR, #0x10                       \n"
+        "BNE     _skip_vfp_restore               \n"
+        "VLDMIA  R2!, {S16-S31}                  \n"
+        "_skip_vfp_restore:                      \n"
+
+        /* Set the new thread's stack top in PSP unless the stack monitor is used. If the stack monitor is used, save
+         * the new PSP in R0 and it will be set in rm_freertos_port_stack_monitor_cfg(). */
+ #if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+        "MOV     R0, R2                          \n"
+ #else
+        "MSR     PSP, R2                         \n"
+ #endif
+#else                                  /* __FPU_USED */
+
+        /* Move R2 up past where R4-R7 are stored to where R8-R11 are stored and pop them to R4-R7, then move them to
+         * R8-R11. */
+        "ADDS    R2, R2, #16                     \n"
+        "LDMIA   R2!, {R4-R7}                    \n"
+        "MOV     R8, R4                          \n"
+        "MOV     R9, R5                          \n"
+        "MOV     R10, R6                         \n"
+        "MOV     R11, R7                         \n"
+
+        /* Set the new thread's stack top in PSP unless the stack monitor is used. If the stack monitor is used, save
+         * the new PSP in R0 and it will be set in rm_freertos_port_stack_monitor_cfg(). */
+ #if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+        "MOV     R0, R2                          \n"
+ #else
+        "MSR     PSP, R2                         \n"
+ #endif
+
+        /* Move R2 back to where R4-R7 are stored and restore R4-R7. */
+        "SUBS    R2, R2, #32                     \n"
+        "LDMIA   R2!, {R4-R7}                    \n"
+#endif                                 /* __FPU_USED */
+
+#if RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+
+        /* If the hardware stack monitor is used, configure the process stack monitor and update PSP while the
+         * process stack monitor is disabled. The new PSP value is in R0 from earlier calculations, and R0 contains
+         * the first argument to a function. */
+
+        /* Save and restore LR if the MCU has an FPU since LR is clobbered by the BL instruction and we need LR
+         * to return to the thread. */
+ #if __FPU_USED
+        "PUSH    {LR}                            \n"
+ #endif
+        "BL      rm_freertos_port_stack_monitor_cfg \n"
+ #if __FPU_USED
+        "POP     {LR}                            \n"
+ #endif
+#endif
+
+#if __FPU_USED
+
+        /** Return to the thread using the process stack and saved FPU setting. */
+        "BX     LR                               \n"
+#else
+
+        /* Set (EXC_RETURN) to 0xFFFFFFFD. Return to Thread mode, exception return uses non-floating-point state
+         * from the PSP and execution uses PSP after return. */
+
+        /* Using the LDR = syntax may use another register (R0-R3) as a scratch register.  This is alright because we
+         * are done with all other registers. */
+        "LDR    R1, =0xFFFFFFFD                  \n"
+        "BX     R1                               \n"
+#endif
+        );
+}
+
+#if configUSE_TICKLESS_IDLE
+
+/***********************************************************************************************************************
+ * Subroutine to reset the SysTick. It first sets the SysTick to the tick fraction remaining, then restores the load
+ * value to the tick frequency. It also increments the system time to account for ticks elapsed during tickless idle.
+ *
+ * @param[in]  tick_fraction_remaining  Number of counts remaining in the current tick.
+ * @param[in]  completed_ticks          Number of ticks completed during tickless idle.
+ **********************************************************************************************************************/
+static void rm_freertos_port_reset_systick (uint32_t tick_fraction_remaining, uint32_t completed_ticks)
+{
+    /* Reload the SysTick to the fraction remaining of the current tick. Setting VAL to 0 resets the LOAD value without
+     * pending a SysTick interrupt. */
+    SysTick->LOAD = tick_fraction_remaining;
+    SysTick->VAL  = 0U;
+
+    /* Set the reload value back to the default reload value. */
+    SysTick->LOAD = ulTimerCountsForOneTick - 1UL;
+
+    /* Increment the system time to account for ticks elapsed during tickless idle. */
+    vTaskStepTick(completed_ticks);
+
+    /* Clear variable requesting SysTick reset. */
+    g_reset_systick = 0U;
+}
+
+#endif
+
+/***********************************************************************************************************************
+ * Increments system time.
+ **********************************************************************************************************************/
+void SysTick_Handler (void)
+{
+#if configUSE_TICKLESS_IDLE
+
+    /* Reset the SysTick reload value if it was reconfigured for a long sleep in tickless idle. */
+    if (g_reset_systick)
+    {
+        /* Subtract one because we are in the SysTick_Handler already and one will be added in xTaskIncrementTick. */
+        uint32_t completed_ticks         = (g_reset_systick / ulTimerCountsForOneTick) - 1U;
+        uint32_t tick_fraction_remaining = g_reset_systick - SysTick->VAL;
+        rm_freertos_port_reset_systick(tick_fraction_remaining, completed_ticks);
+    }
+#endif
+
+    /* Increment the RTOS tick. */
+    if (xTaskIncrementTick() != pdFALSE)
+    {
+        /* A context switch is required.  Context switching is performed in
+         * the PendSV interrupt.  Pend the PendSV interrupt. */
+        SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+    }
+}
+
+/***********************************************************************************************************************
+ * Setup the stack of a new task so it is ready to be placed under the scheduler control.  The registers have to be
+ * placed on the stack in the order that the port expects to find them.
+ *
+ * @param[in]  pxTopOfStack  Pointer to top of this task's stack
+ * @param[in]  pxCode        Task function, stored as initial PC for the task
+ * @param[in]  pvParameters  Parameters for task
+ **********************************************************************************************************************/
+StackType_t * pxPortInitialiseStack (StackType_t * pxTopOfStack, TaskFunction_t pxCode, void * pvParameters)
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ((StackType_t) pxCode) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;           /* LR */
+
+    /* Save code space by skipping register initialization. */
+    pxTopOfStack -= 5;                                               /* R12, R3, R2 and R1. */
+    *pxTopOfStack = (StackType_t) pvParameters;                      /* R0 */
+
+#if __FPU_USED
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+#endif
+
+    pxTopOfStack -= 8;                 /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+
+#ifndef configTASK_RETURN_ADDRESS
+
+/***********************************************************************************************************************
+ * Execution only ends up here if a task exits without deleting itself and configTASK_RETURN_ADDRESS is not defined.
+ **********************************************************************************************************************/
+static void prvTaskExitError (void)
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
+
+    while (1)
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being defined
+         * but never called.  ulDummy is used purely to quieten other warnings
+         * about code appearing after this function is called - making ulDummy
+         * volatile makes the compiler think the function could return and
+         * therefore not output an 'unreachable code' warning for code that appears
+         * after it. */
+    }
+}
+
+#endif
+
+/***********************************************************************************************************************
+ * Setup the hardware for the scheduler to take control. Configures the SysTick frequency and starts the first task.
+ **********************************************************************************************************************/
+BaseType_t xPortStartScheduler (void)
+{
+#if (configASSERT_DEFINED == 1)
+ #ifdef __ARM_ARCH_7EM__               // CM4
+    {
+  #ifdef __ARM_ARCH_7EM__              // CM4
+        volatile uint8_t         ulOriginalPriority;
+        volatile uint8_t * const pucFirstUserPriorityRegister = &NVIC->IP[0];
+  #else
+        volatile uint32_t         ulOriginalPriority;
+        volatile uint32_t * const pucFirstUserPriorityRegister = &NVIC->IPR[0];
+  #endif
+        volatile uint32_t ucMaxPriorityValue;
+
+        /* Determine the maximum priority from which ISR safe FreeRTOS API
+         * functions can be called.  ISR safe functions are those that end in
+         * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+         * ensure interrupt entry is as fast and simple as possible.
+         *
+         * Save the interrupt priority value that is about to be clobbered. */
+        ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+        /* Determine the number of priority bits available.  First write to all
+         * possible bits. */
+        *pucFirstUserPriorityRegister = UINT8_MAX;
+
+        /* Read the value back to see how many bits stuck. */
+        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+        /* Use the same mask on the maximum system call priority. */
+        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+        /* Calculate the maximum acceptable priority group value for the number
+         * of bits read back. */
+        ulMaxPRIGROUPValue = SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;
+        while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE)
+        {
+            ulMaxPRIGROUPValue--;
+            ucMaxPriorityValue <<= 1U;
+        }
+
+  #ifdef __NVIC_PRIO_BITS
+        {
+            /* Check the CMSIS configuration that defines the number of
+             * priority bits matches the number of priority bits actually queried
+             * from the hardware. */
+            configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS);
+        }
+  #endif
+
+  #ifdef configPRIO_BITS
+        {
+            /* Check the FreeRTOS configuration that defines the number of
+             * priority bits matches the number of priority bits actually queried
+             * from the hardware. */
+            configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS);
+        }
+  #endif
+
+        /* Shift the priority group value back to its position within the AIRCR
+         * register. */
+        ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+        ulMaxPRIGROUPValue  &= portPRIORITY_GROUP_MASK;
+
+        /* Restore the clobbered interrupt priority register to its original
+         * value. */
+        *pucFirstUserPriorityRegister = ulOriginalPriority;
+    }
+ #endif
+#endif                                 /* conifgASSERT_DEFINED */
+
+    /* Make PendSV the lowest priority interrupt. */
+    NVIC_SetPriority(PendSV_IRQn, UINT8_MAX);
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* VFP is enabled in SystemInit(), so no need to enable it here. */
+
+#if __FPU_USED
+
+    /* Lazy save always. */
+    FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
+#endif
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();              // TODO keep
+
+    /* Should not get here! */
+    return 0;
+}
+
+/***********************************************************************************************************************
+ * Execution should never get here.
+ **********************************************************************************************************************/
+void vPortEndScheduler (void)
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
+}
+
+/***********************************************************************************************************************
+ * Enter a critical section.
+ **********************************************************************************************************************/
+void vPortEnterCritical (void)
+{
+    uint32_t old_mask_level = portSET_INTERRUPT_MASK();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if (uxCriticalNesting == 1)
+    {
+        g_mask_level_before_disable = old_mask_level;
+        configASSERT((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0);
+    }
+}
+
+/***********************************************************************************************************************
+ * Exit a critical section.
+ **********************************************************************************************************************/
+void vPortExitCritical (void)
+{
+    configASSERT(uxCriticalNesting);
+    uxCriticalNesting--;
+    if (uxCriticalNesting == 0)
+    {
+        portCLEAR_INTERRUPT_MASK(g_mask_level_before_disable);
+    }
+}
+
+/*-----------------------------------------------------------*/
+
+#if configUSE_IDLE_HOOK || configUSE_TICKLESS_IDLE
+
+/***********************************************************************************************************************
+ * Saves the LPM state, then enters sleep mode. After waking, reenables interrupts briefly to allow any pending
+ * interrupts to run.
+ *
+ * @pre Disable interrupts an suspend all tasks before calling this function.
+ *
+ * @param[in] xExpectedIdleTime Expected idle time in ticks
+ **********************************************************************************************************************/
+void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
+{
+    uint32_t saved_sbycr = 0U;
+
+    /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+     * set its parameter to 0 to indicate that its implementation contains
+     * its own wait for interrupt or wait for event instruction, and so wfi
+     * should not be executed again. The original expected idle
+     * time variable must remain unmodified, so this is done in a subroutine. */
+    configPRE_SLEEP_PROCESSING(xExpectedIdleTime);
+    if (xExpectedIdleTime > 0)
+    {
+        /* Save LPM Mode */
+        saved_sbycr = R_SYSTEM->SBYCR;
+
+        /** Check if the LPM peripheral is set to go to Software Standby mode with WFI instruction.
+         *  If so, change the LPM peripheral to go to Sleep mode. */
+        if (R_SYSTEM_SBYCR_SSBY_Msk & saved_sbycr)
+        {
+            /* Save register protect value */
+            uint32_t saved_prcr = R_SYSTEM->PRCR;
+
+            /* Unlock LPM peripheral registers */
+            R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
+
+            /* Clear to set to sleep low power mode (not standby or deep standby) */
+            R_SYSTEM->SBYCR = 0U;
+
+            /* Restore register lock */
+            R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
+        }
+
+        /**
+         * DSB should be last instruction executed before WFI
+         * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html
+         */
+        __DSB();
+
+        /* If there is a pending interrupt (wake up condition for WFI is true), the MCU does not enter low power mode:
+         * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABHHGEB.html
+         * Note that interrupt will bring the CPU out of the low power mode.  After exiting from low power mode,
+         * interrupt will be re-enabled. */
+        __WFI();
+
+        /* Instruction Synchronization Barrier. */
+        __ISB();
+
+        /* Re-enable interrupts to allow the interrupt that brought the MCU
+         * out of sleep mode to execute immediately. This will not cause a
+         * context switch because all tasks are currently suspended. */
+        __enable_irq();
+        __ISB();
+
+        /* Disable interrupts again to restore the LPM state. */
+        __disable_irq();
+    }
+
+    configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
+
+    /** Check if the LPM peripheral was supposed to go to Software Standby mode with WFI instruction.
+     *  If yes, restore the LPM peripheral setting. */
+    if (R_SYSTEM_SBYCR_SSBY_Msk & saved_sbycr)
+    {
+        /* Save register protect value */
+        uint32_t saved_prcr = R_SYSTEM->PRCR;
+
+        /* Unlock LPM peripheral registers */
+        R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
+
+        /* Restore LPM Mode */
+        R_SYSTEM->SBYCR = (uint16_t) saved_sbycr;
+
+        /* Restore register lock */
+        R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
+    }
+}
+
+#endif
+
+#if configUSE_IDLE_HOOK
+
+/***********************************************************************************************************************
+ * Suspends tasks and sleeps, waking for each interrupt.
+ *
+ * @note This is a weak function. It can be overridden by an application specific implementation if desired.
+ **********************************************************************************************************************/
+__attribute__((weak)) void vApplicationIdleHook (void)
+{
+    /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should
+     * exit sleep mode. This must be done before suspending tasks because a pending interrupt will prevent sleep from
+     * WFI, but a task ready to run will not. If a task becomes ready to run before disabling interrupts, a context
+     * switch will happen. */
+    __disable_irq();
+
+    /* Don't allow a context switch during sleep processing to ensure the LPM state is restored
+     * before switching from idle to the next ready task. This is done in the idle task
+     * before vPortSuppressTicksAndSleep when configUSE_TICKLESS_IDLE is used. */
+    vTaskSuspendAll();
+
+    /* Save current LPM state, then sleep. */
+    rm_freertos_port_sleep_preserving_lpm(1);
+
+    /* Exit with interrupts enabled. */
+    __enable_irq();
+
+    /* Allow context switches again. No need to yield here since the idle task yields when it loops around. */
+    (void) xTaskResumeAll();
+}
+
+#endif
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+/***********************************************************************************************************************
+ * Configures the SysTick for the maximum possible sleep given the expected idle time, then sleeps. Restores Systick
+ * settings after waking.
+ *
+ * @note Tasks are already suspended when this function is called.
+ *
+ * @note This is a weak function. It can be overridden by an application specific implementation if desired.
+ **********************************************************************************************************************/
+__attribute__((weak)) void vPortSuppressTicksAndSleep (TickType_t xExpectedIdleTime)
+{
+    uint32_t ulReloadValue;
+    uint32_t ulCompleteTickPeriods;
+    uint32_t ulCompletedSysTickDecrements;
+
+    /* Make sure the SysTick reload value does not overflow the counter. */
+    if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks)
+    {
+        xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+    }
+
+    /* Calculate the reload value required to wait xExpectedIdleTime
+     * tick periods.  -1 is used because this code will execute part way
+     * through one of the tick periods. */
+    ulReloadValue = ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL);
+
+    /* Enter a critical section but don't use the taskENTER_CRITICAL()
+     * method as that will mask interrupts that should exit sleep mode. */
+    __disable_irq();
+
+    /* Set the new reload value. */
+    ulReloadValue += SysTick->VAL;
+    SysTick->LOAD  = ulReloadValue;
+
+    /* Clear the SysTick count flag and set the count value back to
+     * zero. */
+    SysTick->VAL = 0UL;
+
+    /* Reset the SysTick to the default in the next SysTick interrupt. */
+    g_reset_systick = ulReloadValue;
+
+    /* If an interrupt was processed while tasks were suspended, another task may be ready to run. If so, don't
+     * sleep. */
+    if (eTaskConfirmSleepModeStatus() != eAbortSleep)
+    {
+        /* This function sleeps if no interrupt is pending, and enables
+         * interrupts briefly after waking to allow any pending interrupt
+         * to be serviced. */
+        rm_freertos_port_sleep_preserving_lpm(xExpectedIdleTime);
+    }
+
+    /* If the SysTick has not yet counted to zero, an interrupt other than
+     * the SysTick must have brought the system out of sleep mode). */
+    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
+    {
+        /* Something other than the tick interrupt ended the sleep.
+         * Work out how long the sleep lasted rounded to complete tick
+         * periods. */
+        ulCompletedSysTickDecrements = ulReloadValue - SysTick->VAL;
+
+        /* How many complete tick periods passed while the processor
+         * was waiting? */
+        ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+        /* The reload value is set to whatever fraction of a single tick
+         * period remains. */
+        uint32_t tick_fraction_remaining = ulCompletedSysTickDecrements % ulTimerCountsForOneTick;
+
+        rm_freertos_port_reset_systick(tick_fraction_remaining, ulCompleteTickPeriods);
+    }
+
+    /* Exit with interrupts enabled. */
+    __enable_irq();
+}
+
+#endif                                 /* #if configUSE_TICKLESS_IDLE */
+
+/***********************************************************************************************************************
+ * Setup the systick timer to generate the tick interrupts at the required frequency.
+ **********************************************************************************************************************/
+__attribute__((weak)) void vPortSetupTimerInterrupt (void)
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+#if (configUSE_TICKLESS_IDLE == 1)
+    {
+        ulTimerCountsForOneTick         = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ);
+        xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+    }
+#endif                                 /* configUSE_TICKLESS_IDLE */
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    SysTick_Config(SystemCoreClock / configTICK_RATE_HZ);
+}
+
+#if (configASSERT_DEFINED == 1)
+
+void vPortValidateInterruptPriority (void)
+{
+    IRQn_Type ulCurrentInterrupt;
+    uint32_t  ulCurrentPriority;
+
+    /* Obtain the number of the currently executing interrupt. */
+    ulCurrentInterrupt = R_FSP_CurrentIrqGet();
+
+    /* Is the interrupt number a user defined interrupt? */
+    if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER)
+    {
+        /* Look up the interrupt's priority. */
+        ulCurrentPriority = NVIC_GetPriority(ulCurrentInterrupt);
+
+        /* The following assertion will fail if a service routine (ISR) for
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Interrupts that  use the FreeRTOS API must not be left at their
+         * default priority of  zero as that is the highest possible priority,
+         * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+         * and  therefore also guaranteed to be invalid.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible.
+         *
+         * The following links provide detailed information:
+         * http://www.freertos.org/RTOS-Cortex-M3-M4.html
+         * http://www.freertos.org/FAQHelp.html */
+        configASSERT(ulCurrentPriority >= ucMaxSysCallPriority);
+    }
+
+ #ifdef __ARM_ARCH_7EM__
+
+    /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+     * that define each interrupt's priority to be split between bits that
+     * define the interrupt's pre-emption priority bits and bits that define
+     * the interrupt's sub-priority.  For simplicity all bits must be defined
+     * to be pre-emption priority bits.  The following assertion will fail if
+     * this is not the case (if some bits represent a sub-priority).
+     *
+     * If the application only uses CMSIS libraries for interrupt
+     * configuration then the correct setting can be achieved on all Cortex-M
+     * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+     * scheduler.  Note however that some vendor specific peripheral libraries
+     * assume a non-zero priority group setting, in which cases using a value
+     * of zero will result in unpredictable behaviour. */
+    configASSERT(NVIC_GetPriorityGrouping() <= ulMaxPRIGROUPValue);
+ #endif
+}
+
+#endif                                 /* configASSERT_DEFINED */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/portmacro.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/portmacro.h
new file mode 100644
index 0000000000..c77b371300
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra/fsp/src/rm_freertos_port/portmacro.h
@@ -0,0 +1,241 @@
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ */
+
+#ifndef PORTMACRO_H
+ #define PORTMACRO_H
+
+ #ifdef __cplusplus
+extern "C" {
+ #endif
+
+ #include "bsp_api.h"
+
+/* Needed for definitions of pdFALSE and pdTRUE. */
+ #include "projdefs.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+ #define portCHAR          char
+ #define portFLOAT         float
+ #define portDOUBLE        double
+ #define portLONG          long
+ #define portSHORT         short
+ #define portSTACK_TYPE    uint32_t
+ #define portBASE_TYPE     long
+
+/* Structure passed to pvParameters when task creation code is generated. */
+typedef struct st_rm_freertos_port_parameters
+{
+    void * p_context;                  // Pointer to user data
+} rm_freertos_port_parameters_t;
+
+typedef portSTACK_TYPE StackType_t;
+typedef long           BaseType_t;
+typedef unsigned long  UBaseType_t;
+
+ #if (configUSE_16_BIT_TICKS == 1)
+typedef uint16_t TickType_t;
+  #define portMAX_DELAY              (TickType_t) 0xffff
+ #else
+typedef uint32_t TickType_t;
+  #define portMAX_DELAY              (TickType_t) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+  #define portTICK_TYPE_IS_ATOMIC    1
+ #endif
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+ #define portSTACK_GROWTH      (-1)
+ #define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
+ #define portBYTE_ALIGNMENT    8
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+ #define portYIELD()                                    \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;             \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __DSB();                                                   \
+        __ISB();                                                   \
+    }
+ #define portEND_SWITCHING_ISR(xSwitchRequired)    if (xSwitchRequired != pdFALSE) \
+        portYIELD()
+ #define portYIELD_FROM_ISR(x)                     portEND_SWITCHING_ISR(x)
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+
+ #ifdef __ARM_ARCH_7EM__               // CM4
+  #define RM_FREERTOS_PORT_HAS_BASEPRI    (1)
+ #else
+  #define RM_FREERTOS_PORT_HAS_BASEPRI    (0)
+ #endif
+
+ #if RM_FREERTOS_PORT_HAS_BASEPRI && configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY > 0
+
+/* Set the interrupt mask and return the previous value. */
+  #define portSET_INTERRUPT_MASK()                           __get_BASEPRI(); \
+    __set_BASEPRI(configMAX_SYSCALL_INTERRUPT_PRIORITY); // configMAX_SYSCALL_INTERRUPT_PRIORITY is already shifted to the appropriate place for BASEPRI
+
+/* Restore the interrupt mask to the previous value (x). */
+  #define portCLEAR_INTERRUPT_MASK(x)                        __set_BASEPRI(x)
+
+ #else
+
+/* Set the interrupt mask and return the previous value. */
+  #define portSET_INTERRUPT_MASK()                           __get_PRIMASK(); \
+    __set_PRIMASK(1);
+
+/* Restore the interrupt mask to the previous value (x). */
+  #define portCLEAR_INTERRUPT_MASK(x)                        __set_PRIMASK(x)
+ #endif
+
+ #define portENTER_CRITICAL()                                vPortEnterCritical()
+ #define portEXIT_CRITICAL()                                 vPortExitCritical()
+
+ #define portDISABLE_INTERRUPTS()                            __set_PRIMASK(1)
+ #define portENABLE_INTERRUPTS()                             __set_PRIMASK(0)
+
+ #define portSET_INTERRUPT_MASK_FROM_ISR()                   portSET_INTERRUPT_MASK()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)                portCLEAR_INTERRUPT_MASK(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+ #define portTASK_FUNCTION_PROTO(vFunction, pvParameters)    void vFunction(void * pvParameters)
+ #define portTASK_FUNCTION(vFunction, pvParameters)          void vFunction(void * pvParameters)
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
+
+  #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime)    vPortSuppressTicksAndSleep(xExpectedIdleTime)
+ #endif
+
+/* Idle hook, weak implementation. */
+void vApplicationIdleHook(void);
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+  #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+ #endif
+
+ #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+__attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros (uint32_t ulBitmap)
+{
+    return __CLZ(ulBitmap);
+}
+
+/* Check the configuration. */
+  #if (configMAX_PRIORITIES > 32)
+   #error \
+    configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+  #endif
+
+/* Store/clear the ready priorities in a bit map. */
+  #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities)    (uxReadyPriorities) |= (1UL << (uxPriority))
+  #define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities)     (uxReadyPriorities) &= ~(1UL << (uxPriority))
+
+/*-----------------------------------------------------------*/
+
+  #define portGET_HIGHEST_PRIORITY(uxTopPriority,                                     \
+                                   uxReadyPriorities)                 uxTopPriority = \
+    (31UL - (uint32_t) ucPortCountLeadingZeros((uxReadyPriorities)))
+
+ #endif                                /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+ #ifdef configASSERT
+void vPortValidateInterruptPriority(void);
+
+  #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+ #endif
+
+/* portNOP() is not required by this port. */
+ #define portNOP()
+
+ #if defined(__GNUC__) || defined(__ARMCC_VERSION)
+  #define portINLINE          __inline
+ #elif defined(__ICCARM__)
+  #define portINLINE          inline
+ #endif
+
+ #ifndef portFORCE_INLINE
+  #define portFORCE_INLINE    BSP_FORCE_INLINE
+ #endif
+
+portFORCE_INLINE static inline BaseType_t xPortIsInsideInterrupt (void)
+{
+    uint32_t   ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    ulCurrentInterrupt = __get_IPSR();
+
+    if (ulCurrentInterrupt == 0)
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
+ #ifdef __cplusplus
+}
+ #endif
+
+#endif                                 /* PORTMACRO_H */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg.txt b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg.txt
new file mode 100644
index 0000000000..6190f26807
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg.txt
@@ -0,0 +1,395 @@
+RA Configuration
+  Board "EK-RA4W1"
+  R7FA4W1AD2CNG
+    part_number: R7FA4W1AD2CNG
+    rom_size_bytes: 524288
+    ram_size_bytes: 98304
+    data_flash_size_bytes: 8192
+    package_style: QFN
+    package_pins: 56
+    
+  RA4W1
+    series: 4
+    
+  RA4W1 Family
+    OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled
+    OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles
+    OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
+    OFS0 register settings: Independent WDT: Window End Position:  0% (no window end position)
+    OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position)
+    OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
+    OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby
+    OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
+    OFS0 register settings: WDT: Timeout Period: 16384 cycles
+    OFS0 register settings: WDT: Clock Frequency Division Ratio: 128
+    OFS0 register settings: WDT: Window End Position:  0% (no window end position)
+    OFS0 register settings: WDT: Window Start Position: 100% (no window start position)
+    OFS0 register settings: WDT: Reset Interrupt Request: Reset
+    OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode
+    OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
+    OFS1 register settings: Voltage Detection 0 Level: 1.90 V
+    OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
+    Use Low Voltage Mode: Disable
+    MPU: Enable or disable PC Region 0: Disabled
+    MPU: PC0 Start: 0x00FFFFFC
+    MPU: PC0 End: 0x00FFFFFF
+    MPU: Enable or disable PC Region 1: Disabled
+    MPU: PC1 Start: 0x00FFFFFC
+    MPU: PC1 End: 0x00FFFFFF
+    MPU: Enable or disable Memory Region 0: Disabled
+    MPU: Memory Region 0 Start: 0x00FFFFFC
+    MPU: Memory Region 0 End: 0x00FFFFFF
+    MPU: Enable or disable Memory Region 1: Disabled
+    MPU: Memory Region 1 Start: 0x200FFFFC
+    MPU: Memory Region 1 End: 0x200FFFFF
+    MPU: Enable or disable Memory Region 2: Disabled
+    MPU: Memory Region 2 Start: 0x407FFFFC
+    MPU: Memory Region 2 End: 0x407FFFFF
+    MPU: Enable or disable Memory Region 3: Disabled
+    MPU: Memory Region 3 Start: 0x400DFFFC
+    MPU: Memory Region 3 End: 0x400DFFFF
+    
+  RA Common
+    Main stack size (bytes): 0x2000
+    Heap size (bytes): 0x2000
+    MCU Vcc (mV): 3300
+    Parameter checking: Disabled
+    Assert Failures: Return FSP_ERR_ASSERTION
+    Error Log: No Error Log
+    ID Code Mode: Unlocked (Ignore ID)
+    ID Code (32 Hex Characters): FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+    Soft Reset: Disabled
+    Main Oscillator Populated: Populated
+    PFS Protect: Enabled
+    Main Oscillator Wait Time: 32768 us
+    Main Oscillator Clock Source: Crystal or Resonator
+    Subclock Populated: Populated
+    Subclock Drive: Standard
+    Subclock Stabilization Time (ms): 1000
+    
+  Clocks
+    XTAL 8000000Hz
+    HOCO 32MHz
+    PLL Div /2
+    PLL Mul x12
+    Clock Src: HOCO
+    ICLK Div /1
+    PCLKA Div /1
+    PCLKB Div /1
+    PCLKC Div /1
+    PCLKD Div /1
+    BCLK Div /2
+    BCK/2
+    FCLK Div /2
+    CLKOUT Disabled
+    CLKOUT Div /1
+    UCLK Src: PLL
+    
+  Pin Configurations
+    RA4W1-EK.pincfg -> g_bsp_pin_cfg
+      ANT 30 RADIO0_ANT - - - - - - 
+      AVCC0 35 ANALOG0_AVCC0 - - - - - - 
+      AVDDRF 39 RADIO0_AVDDRF - - - - - - 
+      AVSS0 36 ANALOG0_AVSS0 - - - - - - 
+      FBIN 45 RADIO0_FBIN - - - - - - 
+      LX 41 RADIO0_LX - - - - - - 
+      P004 40 - - - Disabled - - "ADC0: AN04; ICU0: IRQ03; OPAMP2: AMPO" 
+      P010 38 - - - Disabled - - "ADC0: AN05; CTSU0: TS30; ICU0: IRQ14; OPAMP2: AMP-" 
+      P011 37 - - - Disabled - - "ADC0: AN06; CTSU0: TS31; ICU0: IRQ15; OPAMP2: AMP+" 
+      P014 32 - - - Disabled - - "ADC0: AN09; DAC0: DA" 
+      P015 31 - - - Disabled - - "ADC0: AN10; CTSU0: TS28; ICU0: IRQ07" 
+      P100 27 SPI0_MISO Low None "Peripheral mode" CMOS None "ACMPLP0: CMPIN; AGT0: AGTIO; BUS_ASYNCH0: D00; GPT_POEG0: GTETRG; GPT5: GTIOCB; ICU0: IRQ02; IIC1: SCL; KINT0: KRM0; SCI0: RXD; SCI0: SCL; SCI1: SCK; SLCDC0: VL1; SPI0: MISO" 
+      P101 26 SPI0_MOSI Low None "Peripheral mode" CMOS None "ACMPLP0: CMPREF; AGT0: AGTEE; BUS_ASYNCH0: D01; GPT_POEG1: GTETRG; GPT5: GTIOCA; ICU0: IRQ01; IIC1: SDA; KINT0: KRM1; SCI0: SDA; SCI0: TXD; SCI1: CTS; SLCDC0: VL2; SPI0: MOSI" 
+      P102 25 SPI0_RSPCK Low - "Peripheral mode" CMOS None "ACMPLP1: CMPIN; ADC0: ADTRG; ADC0: AN20; AGT0: AGTO; BUS_ASYNCH0: D02; CAN0: CRX; GPT_OPS0: GTOWLO; GPT2: GTIOCB; KINT0: KRM2; SCI0: SCK; SLCDC0: VL3; SPI0: RSPCK" 
+      P103 24 SPI0_SSL0 Low - "Peripheral mode" CMOS None "ACMPLP1: CMPREF; ADC0: AN19; BUS_ASYNCH0: D03; CAN0: CTX; GPT_OPS0: GTOWUP; GPT2: GTIOCA; KINT0: KRM3; SCI0: CTS; SLCDC0: VL4; SPI0: SSL0" 
+      P104 23 - - - Disabled - - "BUS_ASYNCH0: D04; CTSU0: TS13; GPT_POEG1: GTETRG; GPT1: GTIOCB; ICU0: IRQ01; KINT0: KRM4; SCI0: RXD; SCI0: SCL; SLCDC0: COM0; SPI0: SSL1" 
+      P105 22 - - - Disabled - - "BUS_ASYNCH0: D05; CTSU0: TS34; GPT_POEG0: GTETRG; GPT1: GTIOCA; ICU0: IRQ00; KINT0: KRM5; SLCDC0: COM1; SPI0: SSL2" 
+      P106 21 GPIO Low - "Output mode (Initial High)" CMOS - "BUS_ASYNCH0: D06; GPT8: GTIOCB; KINT0: KRM6; SLCDC0: COM2; SPI0: SSL3" 
+      P107 20 - - - Disabled - - "BUS_ASYNCH0: D07; GPT8: GTIOCA; KINT0: KRM7; SLCDC0: COM3" 
+      P108 14 DEBUG0_TMS Low - "Peripheral mode" CMOS None "DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOCB; SCI9: CTS; SPI1: SSL0" 
+      P109 15 DEBUG0_TDO Low - "Peripheral mode" CMOS None "CAN0: CTX; CGC0: CLKOUT; CTSU0: TS10; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOCA; SCI1: SCK; SCI9: SDA; SCI9: TXD; SLCDC0: SEG52; SPI1: MOSI" 
+      P110 16 DEBUG0_TDI Low None "Peripheral mode" CMOS None "ACMP(0-1): VCOUT; CAN0: CRX; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOCB; ICU0: IRQ03; SCI9: RXD; SCI9: SCL; SLCDC0: SEG53; SPI1: MISO" 
+      P111 17 - - - Disabled - - "BUS_ASYNCH0: A05; CTSU0: TS12; GPT3: GTIOCA; ICU0: IRQ04; SCI9: SCK; SLCDC0: CAPH; SPI1: RSPCK" 
+      P200 12 - - - Disabled - - "ICU0: NMI" 
+      P201 11 - - - Disabled - - "SYSTEM0: MD; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC; SYSTEM0: VCC" 
+      P204 9 IIC0_SCL Medium - "Peripheral mode" CMOS None "AGT1: AGTIO; BUS_ASYNCH0: A18; CAC0: CACREF; CTSU0: TS00; GPT_OPS0: GTIW; GPT4: GTIOCB; IIC0: SCL; SCI4: SCK; SCI9: SCK; SDHI0: DAT4; SLCDC0: SEG23; SPI1: RSPCK; USB_FS0: OVRCURB" 
+      P205 8 SCI4_TXD Low None "Peripheral mode" CMOS None "AGT1: AGTO; BUS_ASYNCH0: A16; CGC0: CLKOUT; CTSU0: TSCAP; GPT_OPS0: GTIV; GPT4: GTIOCA; ICU0: IRQ01; IIC1: SCL; SCI4: SDA; SCI4: TXD; SCI9: CTS; SDHI0: DAT3; SLCDC0: SEG20; SPI1: SSL0; USB_FS0: OVRCURA" 
+      P206 7 SCI4_RXD Low None "Peripheral mode" CMOS None "BUS_ASYNCH0: WAIT; CTSU0: TS01; GPT_OPS0: GTIU; ICU0: IRQ00; IIC1: SDA; SCI4: RXD; SCI4: SCL; SDHI0: DAT2; SLCDC0: SEG12; SPI1: SSL1; USB_FS0: VBUSEN" 
+      P212 53 - - - Disabled - - "AGT1: AGTEE; CGC0: EXTAL; GPT_POEG1: GTETRG; GPT0: GTIOCB; ICU0: IRQ03; SCI1: RXD; SCI1: SCL" 
+      P213 52 - - - Disabled - - "CGC0: XTAL; GPT_POEG0: GTETRG; GPT0: GTIOCA; ICU0: IRQ02; SCI1: SDA; SCI1: TXD" 
+      P214 50 - - - Disabled - - "CGC0: XCOUT" 
+      P215 49 - - - Disabled - - "CGC0: XCIN" 
+      P300 13 DEBUG0_TCK Low - "Peripheral mode" CMOS None "DEBUG0: SWCLK; DEBUG0: TCK; GPT_OPS0: GTOUUP; GPT0: GTIOCA; SPI1: SSL1" 
+      P305 - - - - Disabled - - - 
+      P402 44 IRQ0_IRQ04 - IRQ04 "IRQ mode" - - "AGT0: AGTIO; AGT1: AGTIO; CAN0: CRX; CTSU0: TS18; ICU0: IRQ04; RTC0: RTCIC0; SCI1: RXD; SCI1: SCL; SLCDC0: SEG06" 
+      P404 46 GPIO Low - "Output mode (Initial High)" CMOS - "GPT3: GTIOCB; RTC0: RTCIC2; SSI0: SSIWS" 
+      P407 1 IIC0_SDA Medium - "Peripheral mode" CMOS None "ADC0: ADTRG; AGT0: AGTIO; CTSU0: TS03; IIC0: SDA; RTC0: RTCOUT; SCI4: CTS; SLCDC0: SEG11; SPI1: SSL3" 
+      P409 56 - - - Disabled - - "GPT_OPS0: GTOWUP; GPT5: GTIOCA; ICU0: IRQ06; SLCDC0: SEG09; USB_FS0: EXICEN" 
+      P414 55 - - - Disabled - - "GPT0: GTIOCB; ICU0: IRQ09; SDHI0: WP; SPI0: SSL1" 
+      P501 29 - - - Disabled - - "ACMPLP1: CMPIN; ADC0: AN17; AGT0: AGTOB; GPT_OPS0: GTIV; GPT2: GTIOCB; ICU0: IRQ11; QSPI0: QSSL; SLCDC0: SEG49; USB_FS0: OVRCURA" 
+      P914 4 - - - Disabled - - "USB_FS0: DP" 
+      P915 3 - - - Disabled - - "USB_FS0: DM" 
+      Q1 34 RADIO0_Q1 - - - - - - 
+      Q2 33 RADIO0_Q2 - - - - - - 
+      RES# 10 SYSTEM0_RES - - - - - - 
+      TEST0 28 RADIO0_TEST0 - - - - - - 
+      VBATT 47 SYSTEM0_VBATT - - - - - - 
+      VCC 18 SYSTEM0_VCC - - - - - - 
+      VCC 54 SYSTEM0_VCC - - - - - - 
+      VCCUSB 5 USBFS0_VCC - - - - - - 
+      VCCUSBLDO 6 USBFS0_VCCLDO - - - - - - 
+      VCL 48 SYSTEM0_VCL - - - - - - 
+      VDDDIG 43 RADIO0_VDDDIG - - - - - - 
+      VDDRF 42 RADIO0_VDDRF - - - - - - 
+      VSS 19 SYSTEM0_VSS - - - - - - 
+      VSS 51 SYSTEM0_VSS - - - - - - 
+      VSSUSB 2 USBFS0_VSS - - - - - - 
+      
+  User Events
+    
+  User Event Links
+    
+  Module "I/O Port Driver on r_ioport"
+    Parameter Checking: Default (BSP)
+    
+  Module "BLE Abstraction Driver on rm_ble_abs"
+    Debug Public Address: {0xFF,0xFF,0xFF,0x50,0x90,0x74}
+    Debug Random Address: {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}
+    Maximum number of connections: 7
+    Maximum connection data length: 251
+    Maximum advertising data length: 1650
+    Maximum advertising set number: 4
+    Maximum periodic sync set number.: 2
+    Store Security Data: Disable
+    Data Flash Block for Security Data: 0
+    Remote Device Bonding Number: 7
+    Connection Event Start Notify: Disable notify
+    Connection Event Close Notify: Disable notify
+    Advertising Event Start Notify: Disable notify
+    Advertising Event Close Notify: Disable notify
+    Scanning Event Start Notify: Disable notify
+    Scanning Event Close Notify: Disable notify
+    Initiating Event Start Notify: Disable notify
+    Initiating Event Close Notify: Disable notify
+    RF Deep Sleep Start Notify: Disable notify
+    RF Deep Sleep Wakeup Notify: Disable notify
+    Bluetooth dedicated clock: 6
+    DC-DC Converter: Disable DC-DC Converter
+    Slow Clock Source: Use RF_LOCO
+    MCU CLKOUT Port: P109
+    MCU CLKOUT Frequency Output: MCU CLKOUT frequency 32.768kHz
+    Sleep Clock Accuracy(SCA): 250
+    Transmission Power Maximum Value: max +4dBm
+    Transmission Power Default Value: High  0dBm(Transmission Power Maximum Value = +0dBm)  /  +4dBm(Transmission Power Maximum Value = +4dBm)
+    CLKOUT_RF Output: No output
+    RF_DEEP_SLEEP Transition: Enable
+    MCU Main Clock Frequency: 8000
+    Code Flash(ROM) Device Data Block: 255
+    Device Specific Data Flash Block: -1
+    MTU Size Configured: 247
+    Timer Slot Maximum Number: 10
+    Parameter Checking: Default (BSP)
+    
+  Module "Timer Driver on r_agt"
+    Parameter Checking: Default (BSP)
+    Pin Output Support: Disabled
+    Pin Input Support: Disabled
+    
+  Module "Network Driver on r_ble_all_freertos"
+  Module "Flash Driver on r_flash_lp"
+    Parameter Checking: Default (BSP)
+    Code Flash Programming: Disabled
+    Data Flash Programming: Enabled
+    
+  Module "External IRQ Driver on r_icu"
+    Parameter Checking: Default (BSP)
+    
+  Module "Timer Driver on r_gpt"
+    Parameter Checking: Default (BSP)
+    Pin Output Support: Disabled
+    Write Protect Enable: Disabled
+    
+  Module "Heap 4"
+  FreeRTOS
+    General: Custom FreeRTOSConfig.h: 
+    General: Use Preemption: Enabled
+    General: Use Port Optimised Task Selection: Disabled
+    General: Use Tickless Idle: Disabled
+    Hooks: Use Idle Hook: Enabled
+    Hooks: Use Malloc Failed Hook: Disabled
+    Hooks: Use Daemon Task Startup Hook: Disabled
+    Hooks: Use Tick Hook: Disabled
+    General: Cpu Clock Hz: SystemCoreClock
+    General: Tick Rate Hz: 1000
+    General: Max Priorities: 5
+    General: Minimal Stack Size: 128
+    General: Max Task Name Len: 16
+    Stats: Use Trace Facility: Disabled
+    Stats: Use Stats Formatting Functions: Disabled
+    General: Use 16-bit Ticks: Disabled
+    General: Idle Should Yield: Enabled
+    General: Use Task Notifications: Enabled
+    General: Use Mutexes: Enabled
+    General: Use Recursive Mutexes: Enabled
+    General: Use Counting Semaphores: Enabled
+    Hooks: Check For Stack Overflow: Disabled
+    General: Queue Registry Size: 10
+    General: Use Queue Sets: Disabled
+    General: Use Time Slicing: Disabled
+    General: Use Newlib Reentrant: Disabled
+    General: Enable Backward Compatibility: Disabled
+    General: Num Thread Local Storage Pointers: 5
+    General: Stack Depth Type: uint32_t
+    General: Message Buffer Length Type: size_t
+    Memory Allocation: Support Static Allocation: Enabled
+    Memory Allocation: Support Dynamic Allocation: Enabled
+    Memory Allocation: Total Heap Size: 0x4000
+    Memory Allocation: Application Allocated Heap: Disabled
+    Stats: Generate Run Time Stats: Disabled
+    Timers: Use Timers: Enabled
+    Timers: Timer Task Priority: 3
+    Timers: Timer Queue Length: 10
+    Timers: Timer Task Stack Depth: 128
+    General: Library Max Syscall Interrupt Priority: Priority 1
+    General: Assert: assert ( x )
+    General: Include Application Defined Privileged Functions: Disabled
+    Optional Functions: vTaskPrioritySet() Function: Enabled
+    Optional Functions: uxTaskPriorityGet() Function: Enabled
+    Optional Functions: vTaskDelete() Function: Enabled
+    Optional Functions: vTaskSuspend() Function: Enabled
+    Optional Functions: xResumeFromISR() Function: Enabled
+    Optional Functions: vTaskDelayUntil() Function: Enabled
+    Optional Functions: vTaskDelay() Function: Enabled
+    Optional Functions: xTaskGetSchedulerState() Function: Enabled
+    Optional Functions: xTaskGetCurrentTaskHandle() Function: Enabled
+    Optional Functions: uxTaskGetStackHighWaterMark() Function: Disabled
+    Optional Functions: xTaskGetIdleTaskHandle() Function: Disabled
+    Optional Functions: eTaskGetState() Function: Disabled
+    Optional Functions: xEventGroupSetBitFromISR() Function: Enabled
+    Optional Functions: xTimerPendFunctionCall() Function: Enabled
+    Optional Functions: xTaskAbortDelay() Function: Disabled
+    Optional Functions: xTaskGetHandle() Function: Disabled
+    Optional Functions: xTaskResumeFromISR() Function: Enabled
+    RA: Hardware Stack Monitor: Disabled
+    Logging: Print String Function: printf(x)
+    Logging: Logging Max Message Length: 192
+    Logging: Logging Include Time and Task Name: Disabled
+    
+  HAL
+    Instance "g_ioport I/O Port Driver on r_ioport"
+      Name: g_ioport
+      Port 1 ELC Trigger Source: Disabled
+      Port 2 ELC Trigger Source: Disabled
+      Port 3 ELC Trigger Source: Disabled
+      Port 4 ELC Trigger Source: Disabled
+      
+    Instance "BLE Abstraction Driver on rm_ble_abs"
+      Name: g_ble_abs0
+      Gap callback: gap_cb
+      Vendor specific callback: vs_cb
+      Pairing parameters: gs_abs_pairing_param
+      GATT server callback parameter: gs_abs_gatts_cb_param
+      GATT server callback number: 2
+      GATT client callback parameter: gs_abs_gattc_cb_param
+      GATT client callback number: 2
+      Interrupts: Callback provided when an ISR occurs: NULL
+      IO capabilities of local device.: BLE_GAP_IOCAP_NOINPUT_NOOUTPUT
+      MITM protection policy.: BLE_GAP_SEC_MITM_BEST_EFFORT
+      Determine whether to accept only Secure Connections or not.: BLE_GAP_SC_BEST_EFFORT
+      Type of keys to be distributed from local device.: BLE_GAP_KEY_DIST_ENCKEY
+      Type of keys which local device requests a remote device to distribute.: 0
+      Maximum LTK size.: 16
+      
+      Instance "Network Driver on r_ble_all_freertos"
+        
+        Instance "g_flash0 Flash Driver on r_flash_lp"
+          Name: g_flash0
+          Data Flash Background Operation: Disabled
+          Callback: NULL
+          Flash Ready Interrupt Priority: Disabled
+          
+        Instance "g_external_irq0 External IRQ Driver on r_icu"
+          Name: g_external_irq0
+          Channel: 8
+          Trigger: Falling
+          Digital Filtering: Disabled
+          Digital Filtering Sample Clock (Only valid when Digital Filtering is Enabled): PCLK / 64
+          Callback: r_rf_ble_interrupt
+          Pin Interrupt Priority: Priority 1
+          
+        Instance "g_timer1 Timer Driver on r_gpt"
+          General: Name: g_timer1
+          General: Channel: 1
+          General: Mode: Periodic
+          General: Period: 10
+          General: Period Unit: Milliseconds
+          Output: Duty Cycle Percent (only applicable in PWM mode): 50
+          Output: Duty Cycle Range (only applicable in PWM mode): Shortest: 2 PCLK, Longest: (Period - 1) PCLK
+          Output: GTIOCA Output Enabled: False
+          Output: GTIOCA Stop Level: Pin Level Low
+          Output: GTIOCB Output Enabled: False
+          Output: GTIOCB Stop Level: Pin Level Low
+          Input: Count Up Source: 
+          Input: Count Down Source: 
+          Input: Start Source: 
+          Input: Stop Source: 
+          Input: Clear Source: 
+          Input: Capture A Source: 
+          Input: Capture B Source: 
+          Input: Noise Filter A Sampling Clock Select: No Filter
+          Input: Noise Filter B Sampling Clock Select: No Filter
+          Interrupts: Callback: r_rf_host_timer_interrupt
+          Interrupts: Overflow/Crest Interrupt Priority: Priority 2
+          Interrupts: Capture A Interrupt Priority: Disabled
+          Interrupts: Capture B Interrupt Priority: Disabled
+          Interrupts: Trough Interrupt Priority: Disabled
+          Extra Features: Extra Features: Disabled
+          Extra Features: Output Disable: POEG Link: POEG Channel 0
+          Extra Features: Output Disable: Output Disable POEG Trigger: 
+          Extra Features: ADC Trigger: Start Event Trigger (GPTE/GPTEH only): 
+          Extra Features: Dead Time: Dead Time Count Up (Raw Counts): 0
+          Extra Features: Dead Time: Dead Time Count Down (Raw Counts) (GPTE/GPTEH only): 0
+          Extra Features: ADC Trigger (GPTE/GPTEH only): ADC A Compare Match (Raw Counts): 0
+          Extra Features: ADC Trigger (GPTE/GPTEH only): ADC B Compare Match (Raw Counts): 0
+          Extra Features: Interrupt Skipping (GPTE/GPTEH only): Interrupt to Count: None
+          Extra Features: Interrupt Skipping (GPTE/GPTEH only): Interrupt Skip Count: 0
+          Extra Features: Interrupt Skipping (GPTE/GPTEH only): Skip ADC Events: None
+          Extra Features: Output Disable: GTIOCA Disable Setting: Disable Prohibited
+          Extra Features: Output Disable: GTIOCB Disable Setting: Disable Prohibited
+          
+      Instance "g_timer0 Timer Driver on r_agt"
+        General: Name: g_timer0
+        General: Channel: 0
+        General: Mode: Periodic
+        General: Period: 0x10000
+        General: Period Unit: Raw Counts
+        Output: Duty Cycle Percent (only applicable in PWM mode): 50
+        General: Count Source: LOCO
+        Output: AGTOA Output: Disabled
+        Output: AGTOB Output: Disabled
+        Output: AGTO Output: Disabled
+        Input: Measurement Mode: Measure Disabled
+        Input: AGTIO Filter: No Filter
+        Input: Enable Pin: Enable Pin Not Used
+        Input: Trigger Edge: Trigger Edge Rising
+        Interrupts: Callback: ble_abs_hw_timer_callback
+        Interrupts: Underflow Interrupt Priority: Priority 3
+        
+    Instance "g_ble_sw_irq External IRQ Driver on r_icu"
+      Name: g_ble_sw_irq
+      Channel: 4
+      Trigger: Falling
+      Digital Filtering: Disabled
+      Digital Filtering Sample Clock (Only valid when Digital Filtering is Enabled): PCLK / 64
+      Callback: Callback_ble_sw_irq
+      Pin Interrupt Priority: Priority 4
+      
+  Thread "New Thread"
+    Symbol: new_thread0
+    Name: New Thread
+    Stack size (bytes): 0x2000
+    Priority: 1
+    Thread Context: NULL
+    Memory Allocation: Static
+    
+    Instance "Heap 4"
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/aws/FreeRTOSConfig.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/aws/FreeRTOSConfig.h
new file mode 100644
index 0000000000..d4f6da87a8
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/aws/FreeRTOSConfig.h
@@ -0,0 +1,218 @@
+/* generated configuration header file - do not edit */
+#ifndef FREERTOSCONFIG_H_
+#define FREERTOSCONFIG_H_
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+#include "bsp_api.h"
+
+#ifndef configUSE_PREEMPTION
+#define configUSE_PREEMPTION (1)
+#endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION (0)
+#endif
+#ifndef configUSE_TICKLESS_IDLE
+#define configUSE_TICKLESS_IDLE (0)
+#endif
+#ifndef configUSE_IDLE_HOOK
+#define configUSE_IDLE_HOOK (1)
+#endif
+#ifndef configUSE_MALLOC_FAILED_HOOK
+#define configUSE_MALLOC_FAILED_HOOK (0)
+#endif
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
+#endif
+#ifndef configUSE_TICK_HOOK
+#define configUSE_TICK_HOOK (0)
+#endif
+#ifndef configCPU_CLOCK_HZ
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#endif
+#ifndef configTICK_RATE_HZ
+#define configTICK_RATE_HZ (1000)
+#endif
+#ifndef configMAX_PRIORITIES
+#define configMAX_PRIORITIES (5)
+#endif
+#ifndef configMINIMAL_STACK_SIZE
+#define configMINIMAL_STACK_SIZE (128)
+#endif
+#ifndef configMAX_TASK_NAME_LEN
+#define configMAX_TASK_NAME_LEN (16)
+#endif
+#ifndef configUSE_TRACE_FACILITY
+#define configUSE_TRACE_FACILITY (0)
+#endif
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
+#endif
+#ifndef configUSE_16_BIT_TICKS
+#define configUSE_16_BIT_TICKS (0)
+#endif
+#ifndef configIDLE_SHOULD_YIELD
+#define configIDLE_SHOULD_YIELD (1)
+#endif
+#ifndef configUSE_TASK_NOTIFICATIONS
+#define configUSE_TASK_NOTIFICATIONS (1)
+#endif
+#ifndef configUSE_MUTEXES
+#define configUSE_MUTEXES (1)
+#endif
+#ifndef configUSE_RECURSIVE_MUTEXES
+#define configUSE_RECURSIVE_MUTEXES (1)
+#endif
+#ifndef configUSE_COUNTING_SEMAPHORES
+#define configUSE_COUNTING_SEMAPHORES (1)
+#endif
+#ifndef configUSE_ALTERNATIVE_API
+#define configUSE_ALTERNATIVE_API (0U)
+#endif
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+#define configCHECK_FOR_STACK_OVERFLOW (0)
+#endif
+#ifndef configQUEUE_REGISTRY_SIZE
+#define configQUEUE_REGISTRY_SIZE (10)
+#endif
+#ifndef configUSE_QUEUE_SETS
+#define configUSE_QUEUE_SETS (0)
+#endif
+#ifndef configUSE_TIME_SLICING
+#define configUSE_TIME_SLICING (0)
+#endif
+#ifndef configUSE_NEWLIB_REENTRANT
+#define configUSE_NEWLIB_REENTRANT (0)
+#endif
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+#define configENABLE_BACKWARD_COMPATIBILITY (0)
+#endif
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (5)
+#endif
+#ifndef configSTACK_DEPTH_TYPE
+#define configSTACK_DEPTH_TYPE uint32_t
+#endif
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+#ifndef configSUPPORT_STATIC_ALLOCATION
+#define configSUPPORT_STATIC_ALLOCATION (1)
+#endif
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+#define configSUPPORT_DYNAMIC_ALLOCATION (1)
+#endif
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE (0x4000)
+#endif
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+#define configAPPLICATION_ALLOCATED_HEAP (0)
+#endif
+#ifndef configGENERATE_RUN_TIME_STATS
+#define configGENERATE_RUN_TIME_STATS (0)
+#endif
+#ifndef configUSE_CO_ROUTINES
+#define configUSE_CO_ROUTINES (0)
+#endif
+#ifndef configUSE_TIMERS
+#define configUSE_TIMERS (1)
+#endif
+#ifndef configTIMER_TASK_PRIORITY
+#define configTIMER_TASK_PRIORITY (3)
+#endif
+#ifndef configTIMER_QUEUE_LENGTH
+#define configTIMER_QUEUE_LENGTH (10)
+#endif
+#ifndef configTIMER_TASK_STACK_DEPTH
+#define configTIMER_TASK_STACK_DEPTH (128)
+#endif
+#ifndef configLIBRARY_LOWEST_INTERRUPT_PRIORITY
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1 << __NVIC_PRIO_BITS) - 1)
+#endif
+#ifndef configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ((1))
+#endif
+#ifndef configMAX_SYSCALL_INTERRUPT_PRIORITY
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - __NVIC_PRIO_BITS))
+#endif
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
+#endif
+#ifndef configASSERT
+#define configASSERT( x ) (assert ( x ))
+#endif
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
+#endif
+#ifndef INCLUDE_vTaskPrioritySet
+#define INCLUDE_vTaskPrioritySet (1)
+#endif
+#ifndef INCLUDE_uxTaskPriorityGet
+#define INCLUDE_uxTaskPriorityGet (1)
+#endif
+#ifndef INCLUDE_vTaskDelete
+#define INCLUDE_vTaskDelete (1)
+#endif
+#ifndef INCLUDE_vTaskSuspend
+#define INCLUDE_vTaskSuspend (1)
+#endif
+#ifndef INCLUDE_xResumeFromISR
+#define INCLUDE_xResumeFromISR (1)
+#endif
+#ifndef INCLUDE_vTaskDelayUntil
+#define INCLUDE_vTaskDelayUntil (1)
+#endif
+#ifndef INCLUDE_vTaskDelay
+#define INCLUDE_vTaskDelay (1)
+#endif
+#ifndef INCLUDE_xTaskGetSchedulerState
+#define INCLUDE_xTaskGetSchedulerState (1)
+#endif
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+#define INCLUDE_xTaskGetCurrentTaskHandle (1)
+#endif
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+#define INCLUDE_uxTaskGetStackHighWaterMark (0)
+#endif
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+#define INCLUDE_xTaskGetIdleTaskHandle (0)
+#endif
+#ifndef INCLUDE_eTaskGetState
+#define INCLUDE_eTaskGetState (0)
+#endif
+#ifndef INCLUDE_xEventGroupSetBitFromISR
+#define INCLUDE_xEventGroupSetBitFromISR (1)
+#endif
+#ifndef INCLUDE_xTimerPendFunctionCall
+#define INCLUDE_xTimerPendFunctionCall (1)
+#endif
+#ifndef INCLUDE_xTaskAbortDelay
+#define INCLUDE_xTaskAbortDelay (0)
+#endif
+#ifndef INCLUDE_xTaskGetHandle
+#define INCLUDE_xTaskGetHandle (0)
+#endif
+#ifndef INCLUDE_xTaskResumeFromISR
+#define INCLUDE_xTaskResumeFromISR (1)
+#endif
+#ifndef RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE
+#define RM_FREERTOS_PORT_CFG_HW_STACK_MONITOR_ENABLE  (0)
+#endif
+#ifndef configPRINT_STRING
+#define configPRINT_STRING(x)                      (printf(x))
+#endif
+#ifndef configLOGGING_INCLUDE_TIME_AND_TASK_NAME
+#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME   (0)
+#endif
+#ifndef configLOGGING_MAX_MESSAGE_LENGTH
+#define configLOGGING_MAX_MESSAGE_LENGTH           (192)
+#endif
+#endif /* FREERTOSCONFIG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h
new file mode 100644
index 0000000000..fd7b0ccb8f
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/board_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+#include "../../../ra/board/ra4w1_ek/board.h"
+#endif /* BOARD_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..4851e5afe1
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,65 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (1)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (1)
+#define BSP_CFG_RTOS (1)
+#else
+#define BSP_CFG_RTOS (0)
+#endif
+#endif
+#undef RA_NOT_DEFINED
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x2000)
+#define BSP_CFG_HEAP_BYTES (0x2000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+#else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 0000000000..444d32e560
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..70984c8ef6
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,10 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4W1AD2CNG
+#define BSP_ROM_SIZE_BYTES (524288)
+#define BSP_RAM_SIZE_BYTES (98304)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_QFN
+#define BSP_PACKAGE_PINS (56)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..2a6d96b63d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,56 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+#define BSP_MCU_GROUP_RA4W1 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ             (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+#define BSP_HOCO_HZ             (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+#define BSP_HOCO_HZ             (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+#define BSP_HOCO_HZ             (64000000)
+#else
+#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+#define BSP_MCU_VBATT_SUPPORT       (1)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (1 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h
new file mode 100644
index 0000000000..d3ab559238
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_agt_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_AGT_CFG_H_
+#define R_AGT_CFG_H_
+#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
+#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
+#endif /* R_AGT_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h
new file mode 100644
index 0000000000..ae35f40541
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ble_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_BLE_CFG_H_
+#define R_BLE_CFG_H_
+#define BLE_CFG_LIBRARY_TYPE 0
+#endif /* R_BLE_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h
new file mode 100644
index 0000000000..4aa033e167
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_FLASH_LP_CFG_H_
+#define R_FLASH_LP_CFG_H_
+#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (0)
+#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1)
+#endif /* R_FLASH_LP_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h
new file mode 100644
index 0000000000..0c7c1bc78a
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_gpt_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_GPT_CFG_H_
+#define R_GPT_CFG_H_
+#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (0)
+#define GPT_CFG_WRITE_PROTECT_ENABLE (0)
+#endif /* R_GPT_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h
new file mode 100644
index 0000000000..5e77b6980f
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_icu_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_ICU_CFG_H_
+#define R_ICU_CFG_H_
+#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* R_ICU_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..6b4353d238
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h
new file mode 100644
index 0000000000..b43a884c06
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_cfg/fsp_cfg/rm_ble_abs_cfg.h
@@ -0,0 +1,40 @@
+/* generated configuration header file - do not edit */
+#ifndef RM_BLE_ABS_CFG_H_
+#define RM_BLE_ABS_CFG_H_
+#define BLE_ABS_CFG_RF_DEBUG_PUBLIC_ADDRESS {0xFF,0xFF,0xFF,0x50,0x90,0x74}
+#define BLE_ABS_CFG_RF_DEBUG_RANDOM_ADDRESS {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}
+#define BLE_ABS_CFG_RF_CONNECTION_MAXIMUM (7)
+#define BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM (251)
+#define BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM (1650)
+#define BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM (4)
+#define BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM (2)
+#define BLE_ABS_CFG_ENABLE_SECURE_DATA (0)
+#define BLE_ABS_CFG_SECURE_DATA_DATAFLASH_BLOCK (0)
+#define BLE_ABS_CFG_NUMBER_BONDING (7)
+#define BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_START (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_CONNECTION_CLOSE (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_START (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_ADVERTISING_CLOSE (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_START (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_SCANNING_CLOSE (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_START (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_INITIATING_CLOSE (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_START (0)
+#define BLE_ABS_CFG_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP (0)
+#define BLE_ABS_CFG_RF_CLVAL (6)
+#define BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE (0)
+#define BLE_ABS_CFG_RF_EXT32K_EN (0)
+#define BLE_ABS_CFG_RF_MCU_CLKOUT_PORT (0)
+#define BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ (0)
+#define BLE_ABS_CFG_RF_SCA (250)
+#define BLE_ABS_CFG_RF_MAX_TX_POW (1)
+#define BLE_ABS_CFG_RF_DEF_TX_POW (0)
+#define BLE_ABS_CFG_RF_CLKOUT_EN (0)
+#define BLE_ABS_CFG_RF_DEEP_SLEEP_EN (1)
+#define BLE_ABS_CFG_MCU_MAIN_CLK_KHZ (8000)
+#define BLE_ABS_CFG_DEV_DATA_CF_BLOCK (255)
+#define BLE_ABS_CFG_DEV_DATA_DF_BLOCK (-1)
+#define BLE_ABS_CFG_GATT_MTU_SIZE (247)
+#define BLE_ABS_CFG_TIMER_NUMBER_OF_SLOT (10)
+#define BLE_ABS_CFG_PARAMETER_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* RM_BLE_ABS_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/RA4W1-EK.csv b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/RA4W1-EK.csv
new file mode 100644
index 0000000000..46a0534438
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/RA4W1-EK.csv
@@ -0,0 +1,257 @@
+"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities"
+"ANT","30","RADIO0_ANT","","","","","",""
+"AVCC0","35","ANALOG0_AVCC0","","","","","",""
+"AVDDRF","39","RADIO0_AVDDRF","","","","","",""
+"AVSS0","36","ANALOG0_AVSS0","","","","","",""
+"FBIN","45","RADIO0_FBIN","","","","","",""
+"LX","41","RADIO0_LX","","","","","",""
+"P004","40","","","","Disabled","","","ADC0: AN04
+ICU0: IRQ03
+OPAMP2: AMPO"
+"P010","38","","","","Disabled","","","ADC0: AN05
+CTSU0: TS30
+ICU0: IRQ14
+OPAMP2: AMP-"
+"P011","37","","","","Disabled","","","ADC0: AN06
+CTSU0: TS31
+ICU0: IRQ15
+OPAMP2: AMP+"
+"P014","32","","","","Disabled","","","ADC0: AN09
+DAC0: DA"
+"P015","31","","","","Disabled","","","ADC0: AN10
+CTSU0: TS28
+ICU0: IRQ07"
+"P100","27","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPIN
+AGT0: AGTIO
+BUS_ASYNCH0: D00
+GPT_POEG0: GTETRG
+GPT5: GTIOCB
+ICU0: IRQ02
+IIC1: SCL
+KINT0: KRM0
+SCI0: RXD
+SCI0: SCL
+SCI1: SCK
+SLCDC0: VL1
+SPI0: MISO"
+"P101","26","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPREF
+AGT0: AGTEE
+BUS_ASYNCH0: D01
+GPT_POEG1: GTETRG
+GPT5: GTIOCA
+ICU0: IRQ01
+IIC1: SDA
+KINT0: KRM1
+SCI0: SDA
+SCI0: TXD
+SCI1: CTS
+SLCDC0: VL2
+SPI0: MOSI"
+"P102","25","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPIN
+ADC0: ADTRG
+ADC0: AN20
+AGT0: AGTO
+BUS_ASYNCH0: D02
+CAN0: CRX
+GPT_OPS0: GTOWLO
+GPT2: GTIOCB
+KINT0: KRM2
+SCI0: SCK
+SLCDC0: VL3
+SPI0: RSPCK"
+"P103","24","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPREF
+ADC0: AN19
+BUS_ASYNCH0: D03
+CAN0: CTX
+GPT_OPS0: GTOWUP
+GPT2: GTIOCA
+KINT0: KRM3
+SCI0: CTS
+SLCDC0: VL4
+SPI0: SSL0"
+"P104","23","","","","Disabled","","","BUS_ASYNCH0: D04
+CTSU0: TS13
+GPT_POEG1: GTETRG
+GPT1: GTIOCB
+ICU0: IRQ01
+KINT0: KRM4
+SCI0: RXD
+SCI0: SCL
+SLCDC0: COM0
+SPI0: SSL1"
+"P105","22","","","","Disabled","","","BUS_ASYNCH0: D05
+CTSU0: TS34
+GPT_POEG0: GTETRG
+GPT1: GTIOCA
+ICU0: IRQ00
+KINT0: KRM5
+SLCDC0: COM1
+SPI0: SSL2"
+"P106","21","","","","Disabled","","","BUS_ASYNCH0: D06
+GPT8: GTIOCB
+KINT0: KRM6
+SLCDC0: COM2
+SPI0: SSL3"
+"P107","20","","","","Disabled","","","BUS_ASYNCH0: D07
+GPT8: GTIOCA
+KINT0: KRM7
+SLCDC0: COM3"
+"P108","14","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO
+DEBUG0: TMS
+GPT_OPS0: GTOULO
+GPT0: GTIOCB
+SCI9: CTS
+SPI1: SSL0"
+"P109","15","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX
+CGC0: CLKOUT
+CTSU0: TS10
+DEBUG0: TDO
+DEBUG0: TRACESWO
+GPT_OPS0: GTOVUP
+GPT1: GTIOCA
+SCI1: SCK
+SCI9: SDA
+SCI9: TXD
+SLCDC0: SEG52
+SPI1: MOSI"
+"P110","16","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","ACMP(0-1): VCOUT
+CAN0: CRX
+DEBUG0: TDI
+GPT_OPS0: GTOVLO
+GPT1: GTIOCB
+ICU0: IRQ03
+SCI9: RXD
+SCI9: SCL
+SLCDC0: SEG53
+SPI1: MISO"
+"P111","17","","","","Disabled","","","BUS_ASYNCH0: A05
+CTSU0: TS12
+GPT3: GTIOCA
+ICU0: IRQ04
+SCI9: SCK
+SLCDC0: CAPH
+SPI1: RSPCK"
+"P200","12","","","","Disabled","","","ICU0: NMI"
+"P201","11","","","","Disabled","","","SYSTEM0: MD
+SYSTEM0: VCC
+SYSTEM0: VCC
+SYSTEM0: VCC
+SYSTEM0: VCC
+SYSTEM0: VCC
+SYSTEM0: VCC
+SYSTEM0: VCC"
+"P204","9","IIC0_SCL","Medium","","Peripheral mode","CMOS","None","AGT1: AGTIO
+BUS_ASYNCH0: A18
+CAC0: CACREF
+CTSU0: TS00
+GPT_OPS0: GTIW
+GPT4: GTIOCB
+IIC0: SCL
+SCI4: SCK
+SCI9: SCK
+SDHI0: DAT4
+SLCDC0: SEG23
+SPI1: RSPCK
+USB_FS0: OVRCURB"
+"P205","8","SCI4_TXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO
+BUS_ASYNCH0: A16
+CGC0: CLKOUT
+CTSU0: TSCAP
+GPT_OPS0: GTIV
+GPT4: GTIOCA
+ICU0: IRQ01
+IIC1: SCL
+SCI4: SDA
+SCI4: TXD
+SCI9: CTS
+SDHI0: DAT3
+SLCDC0: SEG20
+SPI1: SSL0
+USB_FS0: OVRCURA"
+"P206","7","SCI4_RXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: WAIT
+CTSU0: TS01
+GPT_OPS0: GTIU
+ICU0: IRQ00
+IIC1: SDA
+SCI4: RXD
+SCI4: SCL
+SDHI0: DAT2
+SLCDC0: SEG12
+SPI1: SSL1
+USB_FS0: VBUSEN"
+"P212","53","","","","Disabled","","","AGT1: AGTEE
+CGC0: EXTAL
+GPT_POEG1: GTETRG
+GPT0: GTIOCB
+ICU0: IRQ03
+SCI1: RXD
+SCI1: SCL"
+"P213","52","","","","Disabled","","","CGC0: XTAL
+GPT_POEG0: GTETRG
+GPT0: GTIOCA
+ICU0: IRQ02
+SCI1: SDA
+SCI1: TXD"
+"P214","50","","","","Disabled","","","CGC0: XCOUT"
+"P215","49","","","","Disabled","","","CGC0: XCIN"
+"P300","13","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK
+DEBUG0: TCK
+GPT_OPS0: GTOUUP
+GPT0: GTIOCA
+SPI1: SSL1"
+"P305","","","","","Disabled","","",""
+"P402","44","IRQ0_IRQ04","","IRQ04","IRQ mode","","","AGT0: AGTIO
+AGT1: AGTIO
+CAN0: CRX
+CTSU0: TS18
+ICU0: IRQ04
+RTC0: RTCIC0
+SCI1: RXD
+SCI1: SCL
+SLCDC0: SEG06"
+"P404","46","GPIO","Low","","Output mode (Initial High)","CMOS","","GPT3: GTIOCB
+RTC0: RTCIC2
+SSI0: SSIWS"
+"P407","1","IIC0_SDA","Medium","","Peripheral mode","CMOS","None","ADC0: ADTRG
+AGT0: AGTIO
+CTSU0: TS03
+IIC0: SDA
+RTC0: RTCOUT
+SCI4: CTS
+SLCDC0: SEG11
+SPI1: SSL3"
+"P409","56","","","","Disabled","","","GPT_OPS0: GTOWUP
+GPT5: GTIOCA
+ICU0: IRQ06
+SLCDC0: SEG09
+USB_FS0: EXICEN"
+"P414","55","","","","Disabled","","","GPT0: GTIOCB
+ICU0: IRQ09
+SDHI0: WP
+SPI0: SSL1"
+"P501","29","","","","Disabled","","","ACMPLP1: CMPIN
+ADC0: AN17
+AGT0: AGTOB
+GPT_OPS0: GTIV
+GPT2: GTIOCB
+ICU0: IRQ11
+QSPI0: QSSL
+SLCDC0: SEG49
+USB_FS0: OVRCURA"
+"P914","4","","","","Disabled","","","USB_FS0: DP"
+"P915","3","","","","Disabled","","","USB_FS0: DM"
+"Q1","34","RADIO0_Q1","","","","","",""
+"Q2","33","RADIO0_Q2","","","","","",""
+"RES#","10","SYSTEM0_RES","","","","","",""
+"TEST0","28","RADIO0_TEST0","","","","","",""
+"VBATT","47","SYSTEM0_VBATT","","","","","",""
+"VCC","18","SYSTEM0_VCC","","","","","",""
+"VCC","54","SYSTEM0_VCC","","","","","",""
+"VCCUSB","5","USBFS0_VCC","","","","","",""
+"VCCUSBLDO","6","USBFS0_VCCLDO","","","","","",""
+"VCL","48","SYSTEM0_VCL","","","","","",""
+"VDDDIG","43","RADIO0_VDDDIG","","","","","",""
+"VDDRF","42","RADIO0_VDDRF","","","","","",""
+"VSS","19","SYSTEM0_VSS","","","","","",""
+"VSS","51","SYSTEM0_VSS","","","","","",""
+"VSSUSB","2","USBFS0_VSS","","","","","",""
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_clock_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 0000000000..870acfa350
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_XTAL_HZ (8000000) /* XTAL 8000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 32MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_12_0) /* PLL Mul x12 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKB Div /1 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLKOUT_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_pin_cfg.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_pin_cfg.h
new file mode 100644
index 0000000000..497c92d06e
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/bsp_pin_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "bsp_api.h"
+#include "r_ioport_api.h"
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4W1-EK.pincfg */
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.c
new file mode 100644
index 0000000000..5a5bbae8b5
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.c
@@ -0,0 +1,8 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
+void g_common_init(void)
+{
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.h
new file mode 100644
index 0000000000..e2eb70836b
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/common_data.h
@@ -0,0 +1,16 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include 
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.c
new file mode 100644
index 0000000000..b2cbd8c29d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.c
@@ -0,0 +1,493 @@
+/* generated HAL source file - do not edit */
+#include "hal_data.h"
+
+icu_instance_ctrl_t g_ble_sw_irq_ctrl;
+const external_irq_cfg_t g_ble_sw_irq_cfg =
+{ .channel = 4,
+  .trigger = EXTERNAL_IRQ_TRIG_FALLING,
+  .filter_enable = false,
+  .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
+  .p_callback = Callback_ble_sw_irq,
+  .p_context = NULL,
+  .p_extend = NULL,
+  .ipl = (4),
+#if defined(VECTOR_NUMBER_ICU_IRQ4)
+  .irq = VECTOR_NUMBER_ICU_IRQ4,
+#else
+  .irq = FSP_INVALID_VECTOR,
+#endif
+        };
+/* Instance structure to use this module. */
+const external_irq_instance_t g_ble_sw_irq =
+{ .p_ctrl = &g_ble_sw_irq_ctrl, .p_cfg = &g_ble_sw_irq_cfg, .p_api = &g_external_irq_on_icu };
+agt_instance_ctrl_t g_timer0_ctrl;
+const agt_extended_cfg_t g_timer0_extend =
+{ .count_source = AGT_CLOCK_LOCO,
+  .agto = AGT_PIN_CFG_DISABLED,
+  .agtoa = AGT_PIN_CFG_DISABLED,
+  .agtob = AGT_PIN_CFG_DISABLED,
+  .measurement_mode = AGT_MEASURE_DISABLED,
+  .agtio_filter = AGT_AGTIO_FILTER_NONE,
+  .enable_pin = AGT_ENABLE_PIN_NOT_USED,
+  .trigger_edge = AGT_TRIGGER_EDGE_RISING, };
+const timer_cfg_t g_timer0_cfg =
+{ .mode = TIMER_MODE_PERIODIC,
+/* Actual period: 2 seconds. Actual duty: 50%. */.period_counts = 0x10000,
+  .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t) 0, .channel = 0, .p_callback =
+          ble_abs_hw_timer_callback,
+  /** If NULL then do not add & */
+#if defined(g_ble_abs0)
+  .p_context = g_ble_abs0,
+#else
+  .p_context = &g_ble_abs0,
+#endif
+  .p_extend = &g_timer0_extend,
+  .cycle_end_ipl = (3),
+#if defined(VECTOR_NUMBER_AGT0_INT)
+  .cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
+#else
+  .cycle_end_irq = FSP_INVALID_VECTOR,
+#endif
+        };
+/* Instance structure to use this module. */
+const timer_instance_t g_timer0 =
+{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
+gpt_instance_ctrl_t g_timer1_ctrl;
+#if 0
+const gpt_extended_pwm_cfg_t g_timer1_pwm_extend =
+{
+    .trough_ipl = (BSP_IRQ_DISABLED),
+#if defined(VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW)
+    .trough_irq = VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW,
+#else
+    .trough_irq = FSP_INVALID_VECTOR,
+#endif
+    .poeg_link = GPT_POEG_LINK_POEG0,
+    .output_disable = GPT_OUTPUT_DISABLE_NONE,
+    .adc_trigger = GPT_ADC_TRIGGER_NONE,
+    .dead_time_count_up = 0,
+    .dead_time_count_down = 0,
+    .adc_a_compare_match = 0,
+    .adc_b_compare_match = 0,
+    .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
+    .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
+    .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
+    .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
+    .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
+};
+#endif
+const gpt_extended_cfg_t g_timer1_extend =
+        { .gtioca =
+        { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW },
+          .gtiocb =
+          { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW },
+          .shortest_pwm_signal = GPT_SHORTEST_LEVEL_OFF, .start_source = GPT_SOURCE_NONE, .stop_source = GPT_SOURCE_NONE, .clear_source =
+                  GPT_SOURCE_NONE,
+          .count_up_source = GPT_SOURCE_NONE, .count_down_source = GPT_SOURCE_NONE, .capture_a_source = GPT_SOURCE_NONE, .capture_b_source =
+                  GPT_SOURCE_NONE,
+          .capture_a_ipl = (BSP_IRQ_DISABLED), .capture_b_ipl = (BSP_IRQ_DISABLED),
+#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A)
+          .capture_a_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A,
+#else
+          .capture_a_irq = FSP_INVALID_VECTOR,
+#endif
+#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B)
+          .capture_b_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B,
+#else
+          .capture_b_irq = FSP_INVALID_VECTOR,
+#endif
+          .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
+          .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
+#if 0
+          .p_pwm_cfg = &g_timer1_pwm_extend,
+#else
+          .p_pwm_cfg = NULL,
+#endif
+        };
+const timer_cfg_t g_timer1_cfg =
+{ .mode = TIMER_MODE_PERIODIC,
+/* Actual period: 0.01 seconds. Actual duty: 50%. */.period_counts = (uint32_t) 0x4e200,
+  .duty_cycle_counts = 0x27100, .source_div = (timer_source_div_t) 0, .channel = 1, .p_callback =
+          r_rf_host_timer_interrupt,
+  .p_context = NULL, .p_extend = &g_timer1_extend, .cycle_end_ipl = (2),
+#if defined(VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW)
+  .cycle_end_irq = VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW,
+#else
+  .cycle_end_irq = FSP_INVALID_VECTOR,
+#endif
+        };
+/* Instance structure to use this module. */
+const timer_instance_t g_timer1 =
+{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_gpt };
+icu_instance_ctrl_t g_external_irq0_ctrl;
+const external_irq_cfg_t g_external_irq0_cfg =
+{ .channel = 8,
+  .trigger = EXTERNAL_IRQ_TRIG_FALLING,
+  .filter_enable = false,
+  .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
+  .p_callback = r_rf_ble_interrupt,
+  .p_context = NULL,
+  .p_extend = NULL,
+  .ipl = (1),
+#if defined(VECTOR_NUMBER_ICU_IRQ8)
+  .irq = VECTOR_NUMBER_ICU_IRQ8,
+#else
+  .irq = FSP_INVALID_VECTOR,
+#endif
+        };
+/* Instance structure to use this module. */
+const external_irq_instance_t g_external_irq0 =
+{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
+flash_lp_instance_ctrl_t g_flash0_ctrl;
+const flash_cfg_t g_flash0_cfg =
+{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED),
+#if defined(VECTOR_NUMBER_FCU_FRDYI)
+  .irq = VECTOR_NUMBER_FCU_FRDYI,
+#else
+  .irq = FSP_INVALID_VECTOR,
+#endif
+        };
+/* Instance structure to use this module. */
+const flash_instance_t g_flash0 =
+{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp };
+external_irq_instance_t const *g_ble_external_irq = &g_external_irq0;
+flash_instance_t const *g_ble_flash = &g_flash0;
+
+#ifndef ENABLE_HCI_MODE
+timer_instance_t const *g_ble_pl_timer = &g_timer1;
+#endif
+static ble_abs_pairing_parameter_t gs_abs_pairing_param =
+{ .io_capabilitie_local_device = BLE_GAP_IOCAP_NOINPUT_NOOUTPUT,
+  .mitm_protection_policy = BLE_GAP_SEC_MITM_BEST_EFFORT,
+  .secure_connection_only = BLE_GAP_SC_BEST_EFFORT,
+  .local_key_distribute = BLE_GAP_KEY_DIST_ENCKEY,
+  .remote_key_distribute = 0,
+  .maximum_key_size = 16, };
+
+ble_abs_instance_ctrl_t g_ble_abs0_ctrl;
+
+const ble_abs_cfg_t g_ble_abs0_cfg =
+{ .gap_callback = gap_cb,
+  .vendor_specific_callback = vs_cb,
+  .p_pairing_parameter = &gs_abs_pairing_param,
+  .p_gatt_server_callback_list = gs_abs_gatts_cb_param,
+  .gatt_server_callback_list_number = 2,
+  .p_gatt_client_callback_list = gs_abs_gattc_cb_param,
+  .gatt_client_callback_list_number = 2,
+  .p_flash_instance = &g_flash0,
+  .p_timer_instance = &g_timer0,
+  .p_callback = NULL,
+  .p_context = NULL,
+  .p_extend = NULL, };
+
+/* Instance structure to use this module. */
+const ble_abs_instance_t g_ble_abs0 =
+{ .p_ctrl = &g_ble_abs0_ctrl, .p_cfg = &g_ble_abs0_cfg, .p_api = &g_ble_abs_on_ble };
+
+const st_ble_rf_notify_t g_ble_rf_notify =
+{ .enable = BLE_EVENT_NOTIFY_ENABLE_VAL,
+
+#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_START_MASK) != 0)
+        .start_cb = r_ble_rf_notify_event_start,
+#endif /* ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_START_MASK) != 0) */
+#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_CLOSE_MASK) != 0)
+        .close_cb = r_ble_rf_notify_event_close,
+#endif
+#if ((BLE_EVENT_NOTIFY_ENABLE_VAL & BLE_EVENT_NOTIFY_DS_MASK) != 0)
+        .dsleep_cb = r_ble_rf_notify_deep_sleep,
+#endif
+    };
+
+const uint8_t g_ble_dbg_pub_addr[6] = BLE_ABS_CFG_RF_DEBUG_PUBLIC_ADDRESS;
+const uint8_t g_ble_dbg_rand_addr[6] = BLE_ABS_CFG_RF_DEBUG_RANDOM_ADDRESS;
+
+void ble_host_conn_config(uint32_t **pp_host_conn_config_table);
+
+/****************************/
+/*** Memory customization ***/
+/****************************/
+#if (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_CONNECTION_MAXIMUM <= 7)
+const uint16_t g_ble_conn_max = BLE_ABS_CFG_RF_CONNECTION_MAXIMUM;
+#endif
+
+#if (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM >= 27) && (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM <= 251)
+const uint16_t g_ble_conn_data_max = BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM;
+#endif
+
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+#if (BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM >= 31) && (BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM <= 1650)
+const uint16_t g_ble_adv_data_max = BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM;
+#endif
+
+#if (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM <= 4)
+const uint16_t g_ble_adv_set_max = BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM;
+#endif
+
+#if (BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM >= 1) && (BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM <= 2)
+const uint16_t g_ble_sync_set_max = BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM;
+#endif
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+/******************************************/
+/**** LL management data area (2bytes) ****/
+/******************************************/
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+#define BLE_CNTL_DATA_MIN           (392)
+#define BLE_CNTL_DATA_CONN          (65)
+#define BLE_CNTL_DATA_ADV           (0)
+#define BLE_CNTL_DATA_SYNC          (0)
+#else /* (BLE_CFG_LIBRARY_TYPE != 0) */
+#define BLE_CNTL_DATA_MIN           (279)
+#define BLE_CNTL_DATA_CONN          (65)
+#define BLE_CNTL_DATA_ADV           (78)
+#define BLE_CNTL_DATA_SYNC          (33)
+#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */
+#define BLE_CNTL_DATA_MAX                           \
+(                                                   \
+    (BLE_CNTL_DATA_MIN) +                           \
+    (BLE_CNTL_DATA_CONN * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) +    \
+    (BLE_CNTL_DATA_ADV  * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) + \
+    (BLE_CNTL_DATA_SYNC * BLE_ABS_CFG_RF_SYNC_SET_MAXIMUM) +\
+    (0)                                             \
+)
+
+/******************************************/
+/**** BLE stack event heap area (1byte)****/
+/******************************************/
+#ifdef ENABLE_HCI_MODE
+#define BLE_HOST_HEAP_MIN         (0)
+#else /* ENABLE_HCI_MODE */
+#define BLE_HOST_HEAP_MIN         (3032)
+#endif /* ENABLE_HCI_MODE */
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+#define BLE_CNTL_HEAP_MIN         (88)
+#define BLE_CNTL_HEAP_EVENT       (720)
+#else /* (BLE_CFG_LIBRARY_TYPE != 0) */
+#define BLE_CNTL_HEAP_MIN         (280)
+#define BLE_CNTL_HEAP_EVENT       (3784)
+#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */
+#define BLE_CNTL_HEAP_CONN        (388)
+#define _ALIGN_4BYTE(base)        ((((base)+3)>>2)<<2)
+#define BLE_CNTL_HEAP_TX_DATA     (_ALIGN_4BYTE(BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+4)+20)
+#define BLE_CNTL_HEAP_RX_DATA     (_ALIGN_4BYTE(BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+8)+4)
+#define BLE_CNTL_HEAP_TX2_DATA    (BLE_ABS_CFG_RF_CONNECTION_DATA_MAXIMUM+8)
+#define BLE_CNTL_TXRX_MAX         (4)
+
+#if (BLE_CFG_LIBRARY_TYPE != 0)
+#define BLE_CNTL_ADV_DATA_MAX     (0)
+#else /* (BLE_CFG_LIBRARY_TYPE != 0) */
+#define BLE_ADV_DATA_BLOCKS_LIMIT (36)
+#define BLE_ADV_DATA_BLOCKS       ((((BLE_ABS_CFG_RF_ADVERTISING_DATA_MAXIMUM + 251)/252) * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) * 2)
+#if (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT)
+#define BLE_CNTL_ADV_DATA_MAX     (BLE_ADV_DATA_BLOCKS_LIMIT * 256)
+#else /* (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT) */
+#define BLE_CNTL_ADV_DATA_MAX     (BLE_ADV_DATA_BLOCKS * 256)
+#endif /* (BLE_ADV_DATA_BLOCKS > BLE_ADV_DATA_BLOCKS_LIMIT) */
+#endif /* (BLE_CFG_LIBRARY_TYPE != 0) */
+
+#define BLE_CNTL_HEAP_MAX                           \
+(                                                   \
+    (BLE_CNTL_HEAP_MIN) +                           \
+    (BLE_HOST_HEAP_MIN) +                           \
+    (BLE_CNTL_HEAP_EVENT) +                         \
+    (BLE_CNTL_HEAP_CONN * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) +    \
+    (BLE_CNTL_HEAP_TX_DATA * BLE_CNTL_TXRX_MAX) +   \
+    (BLE_CNTL_HEAP_RX_DATA * BLE_CNTL_TXRX_MAX) +   \
+    (BLE_CNTL_ADV_DATA_MAX) +                       \
+    (0)                                             \
+)
+
+/******************************************/
+/**** LL connection entry area (1byte) ****/
+/******************************************/
+#if (BLE_CFG_LIBRARY_TYPE == 1)
+#define BLE_CNTL_CONN_ENT         (328)
+#elif (BLE_CFG_LIBRARY_TYPE == 2)
+#define BLE_CNTL_CONN_ENT         (316)
+#else /* (BLE_CFG_LIBRARY_TYPE == x) */
+#define BLE_CNTL_CONN_ENT         (336)
+#endif /* (BLE_CFG_LIBRARY_TYPE == x) */
+#define BLE_CNTL_CONN_ENT_MAX                       \
+(                                                   \
+    (BLE_CNTL_CONN_ENT * BLE_ABS_CFG_RF_CONNECTION_MAXIMUM) +     \
+    (0)                                             \
+)
+
+/******************************************/
+/**** LL Advertising set area (1byte)  ****/
+/******************************************/
+#define BLE_CNTL_ADV_SET          (152)
+#define BLE_CNTL_ADV_SET_MAX                        \
+(                                                   \
+    (BLE_CNTL_ADV_SET * BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) +   \
+    (0)                                             \
+)
+
+uint16_t g_ble_cntl_data[BLE_CNTL_DATA_MAX];
+uint32_t g_ble_cntl_heap[(BLE_CNTL_HEAP_MAX + 3) / 4];
+uint32_t g_ble_cntl_heap2[(BLE_CNTL_HEAP_TX2_DATA + 3) / 4];
+uint32_t g_ble_cntl_conn_ent[(BLE_CNTL_CONN_ENT_MAX + 3) / 4];
+#if (BLE_CFG_LIBRARY_TYPE == 0)
+uint32_t g_ble_cntl_adv_set[(BLE_CNTL_ADV_SET_MAX + 3) / 4];
+const uint16_t g_ble_adv_block = (uint16_t) (BLE_CNTL_ADV_DATA_MAX / 256);
+#endif /* (BLE_CFG_LIBRARY_TYPE == 0) */
+
+#ifdef NO_USE_BSP
+const uint16_t g_ble_main_clk_khz = (uint16_t)BLE_ABS_CFG_MCU_MAIN_CLK_KHZ;
+const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = NULL;
+#else /* NO_USE_BSP */
+
+#include "bsp_cfg.h"
+#if (BSP_CFG_CLKOUT_RF_MAIN == 1) && (BSP_CFG_XTAL_HZ == 4000000) && (BLE_ABS_CFG_RF_CLKOUT_EN == 5)
+extern void R_BSP_ConfigClockSetting(void);
+const uint16_t g_ble_main_clk_khz = (uint16_t)(BSP_CFG_XTAL_HZ/1000);
+const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = R_BSP_ConfigClockSetting;
+#elif (BSP_CFG_CLKOUT_RF_MAIN == 0)
+const uint16_t g_ble_main_clk_khz = (uint16_t) BLE_ABS_CFG_MCU_MAIN_CLK_KHZ;
+const ble_mcu_clock_change_cb_t g_ble_mcu_clock_change_fp = NULL;
+
+#endif /* (BSP_CFG_CLKOUT_RF_MAIN == 1) && (BSP_CFG_XTAL_HZ == 4000000) && (BLE_ABS_CFG_RF_CLKOUT_EN == 5)  */
+#endif /* NO_USE_BSP */
+
+#if (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255)
+const uint32_t g_ble_dev_data_cf_addr = BLE_ABS_CFG_DEV_DATA_CF_BLOCK;
+#else /* (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255) */
+const uint32_t g_ble_dev_data_cf_addr = 0U;
+#endif /* (BLE_ABS_CFG_DEV_DATA_CF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_CF_BLOCK <= 255) */
+
+#if (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7)
+const uint32_t g_ble_dev_data_df_addr = BLE_ABS_CFG_DEV_DATA_DF_BLOCK;
+#else /* (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7) */
+const uint32_t g_ble_dev_data_df_addr = 0U;
+#endif /* (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) && (BLE_ABS_CFG_DEV_DATA_DF_BLOCK <= 7) */
+
+const uint8_t g_ble_rf_config[] =
+{
+/***************************************/
+/**** CLVAL setting                 ****/
+/***************************************/
+#if (BLE_ABS_CFG_RF_CLVAL >= 0) && (BLE_ABS_CFG_RF_CLVAL <= 15)
+  (BLE_ABS_CFG_RF_CLVAL << 0) |
+#endif /* BLE_ABS_CFG_RF_CLVAL */
+          0x00, /* base value */
+
+  /***************************************/
+  /**** RF Slow Clock setting         ****/
+  /***************************************/
+#if (BLE_ABS_CFG_RF_EXT32K_EN >= 0) && (BLE_ABS_CFG_RF_EXT32K_EN <= 1)
+  /**** External 32kHz setting ****/
+  (BLE_ABS_CFG_RF_EXT32K_EN << 0) |
+#endif /* BLE_ABS_CFG_RF_EXT32K_EN */
+
+#if (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ >= 0) && (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ <= 1)
+          /**** MCU CLKOUT setting ****/
+          (BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ << 1) |
+#endif /* BLE_ABS_CFG_RF_MCU_CLKOUT_FREQ */
+
+#if (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT >= 0) && (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT <= 1)
+          /**** RF_LOCO setting ****/
+          (BLE_ABS_CFG_RF_MCU_CLKOUT_PORT << 2) |
+#endif /* BLE_RF_CONF_RF_LOCO */
+
+          /**** Sleep Clock Accuracy (SCA) setting ****/
+#if   (BLE_ABS_CFG_RF_SCA>=251) && (BLE_ABS_CFG_RF_SCA<=500)
+          (0x00 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=151) && (BLE_ABS_CFG_RF_SCA<=250)
+          (0x01 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=101) && (BLE_ABS_CFG_RF_SCA<=150)
+          (0x02 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=76 ) && (BLE_ABS_CFG_RF_SCA<=100)
+          (0x03 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=51 ) && (BLE_ABS_CFG_RF_SCA<=75 )
+          (0x04 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=31 ) && (BLE_ABS_CFG_RF_SCA<=50 )
+          (0x05 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=21 ) && (BLE_ABS_CFG_RF_SCA<=30 )
+          (0x06 << 4) |
+#elif (BLE_ABS_CFG_RF_SCA>=0  ) && (BLE_ABS_CFG_RF_SCA<=20 )
+          (0x07 << 4) |
+#endif /* BLE_ABS_CFG_RF_SCA */
+          0x00, /* base value */
+
+  /***************************************/
+  /**** Tx Power setting              ****/
+  /***************************************/
+#if (BLE_ABS_CFG_RF_MAX_TX_POW >= 0) && (BLE_ABS_CFG_RF_MAX_TX_POW <= 2)
+  /**** Defalut Tx Power Setting ****/
+  (BLE_ABS_CFG_RF_MAX_TX_POW << 0) |
+#endif /* BLE_ABS_CFG_RF_MAX_TX_POW */
+          0x00, /* base value */
+
+  /***************************************/
+  /**** RF option setting             ****/
+  /***************************************/
+#if (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE >= 0) && (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE <= 1 )
+
+  /**** DC-DC converter setting ****/
+  (BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE << 0) |
+
+#endif /* BLE_ABS_CFG_RF_DCDC_CONVERTER_ENABLE */
+#if (BLE_ABS_CFG_RF_DEF_TX_POW >= 0) && (BLE_ABS_CFG_RF_DEF_TX_POW <= 1)
+          /**** Max Tx Power Setting ****/
+          (BLE_ABS_CFG_RF_DEF_TX_POW << 1) |
+#endif /* BLE_ABS_CFG_RF_DEF_TX_POW */
+#if (BLE_ABS_CFG_RF_CLKOUT_EN >= 0) && (BLE_ABS_CFG_RF_CLKOUT_EN <= 7)
+          /**** RF clock output settng ****/
+          (BLE_ABS_CFG_RF_CLKOUT_EN << 4) |
+#endif /* BLE_ABS_CFG_RF_CLKOUT_EN */
+
+          0x00 /* base value */
+};
+
+/***************************************/
+/**** Host Stack settings           ****/
+/***************************************/
+#ifndef ENABLE_HCI_MODE
+#define BLE_HOST_L2_SIG_TBL_LEN                  24
+#define BLE_HOST_L2_CH_PARAM_TBL_LEN              2
+#define BLE_HOST_HCI_REM_TBL_LEN                  6
+#define BLE_HOST_SMP_CONFIG_LEN                 108
+#define BLE_HOST_GAP_CONN_TBL_LEN                12
+#define BLE_HOST_DEV_Q_TBL_LEN                   14
+#define BLE_HOST_ATT_CONN_TBL_LEN                16
+#define BLE_HOST_GATTS_CNF_TBL_LEN                2
+
+uint32_t g_ble_host_dev_q_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_DEV_Q_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_hci_rem_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_HCI_REM_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_l2_sig_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_L2_SIG_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_l2_ch_param_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_L2_CH_PARAM_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_smp_config_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_SMP_CONFIG_LEN + 3) / 4];
+uint32_t g_ble_host_att_conn_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_ATT_CONN_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_gap_conn_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_GAP_CONN_TBL_LEN + 3) / 4];
+uint32_t g_ble_host_gatts_cnf_tbl[(BLE_ABS_CFG_RF_CONNECTION_MAXIMUM * BLE_HOST_GATTS_CNF_TBL_LEN + 3) / 4];
+
+const uint32_t g_p_ble_host_config_tbls[] =
+{ (uint32_t) g_ble_host_dev_q_tbl,
+  (uint32_t) g_ble_host_hci_rem_tbl,
+  (uint32_t) g_ble_host_l2_sig_tbl,
+  (uint32_t) g_ble_host_l2_ch_param_tbl,
+  (uint32_t) g_ble_host_smp_config_tbl,
+  (uint32_t) g_ble_host_att_conn_tbl,
+  (uint32_t) g_ble_host_gap_conn_tbl,
+  (uint32_t) g_ble_host_gatts_cnf_tbl };
+
+void ble_host_conn_config(uint32_t **pp_host_conn_config_table)
+{
+    *pp_host_conn_config_table = (uint32_t *) g_p_ble_host_config_tbls;
+}
+#endif /* !ENABLE_HCI_MODE */
+
+/***************************************/
+/**** Data Flash Usage              ****/
+/***************************************/
+
+#if (BLE_ABS_CFG_DEV_DATA_DF_BLOCK >= 0) || \
+    ( (BLE_ABS_CFG_EN_SEC_DATA != 0) && (BLE_ABS_CFG_SECD_DATA_DF_BLOCK >= 0) )
+uint32_t g_ble_flash_enable = 1;
+#else
+uint32_t g_ble_flash_enable = 0;
+#endif
+void g_hal_init(void)
+{
+    g_common_init ();
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.h
new file mode 100644
index 0000000000..f1f15e512a
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/hal_data.h
@@ -0,0 +1,108 @@
+/* generated HAL header file - do not edit */
+#ifndef HAL_DATA_H_
+#define HAL_DATA_H_
+#include 
+#include "bsp_api.h"
+#include "common_data.h"
+#include "r_icu.h"
+#include "r_external_irq_api.h"
+#include "r_agt.h"
+#include "r_timer_api.h"
+#include "r_gpt.h"
+#include "r_timer_api.h"
+#include "r_flash_lp.h"
+#include "r_flash_api.h"
+
+#include "rm_ble_abs.h"
+#include "rm_ble_abs_api.h"
+FSP_HEADER
+/** External IRQ on ICU Instance. */
+extern const external_irq_instance_t g_ble_sw_irq;
+
+/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
+extern icu_instance_ctrl_t g_ble_sw_irq_ctrl;
+extern const external_irq_cfg_t g_ble_sw_irq_cfg;
+
+#ifndef Callback_ble_sw_irq
+void Callback_ble_sw_irq(external_irq_callback_args_t *p_args);
+#endif
+/** AGT Timer Instance */
+extern const timer_instance_t g_timer0;
+
+/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
+extern agt_instance_ctrl_t g_timer0_ctrl;
+extern const timer_cfg_t g_timer0_cfg;
+
+#ifndef ble_abs_hw_timer_callback
+void ble_abs_hw_timer_callback(timer_callback_args_t *p_args);
+#endif
+/** Timer on GPT Instance. */
+extern const timer_instance_t g_timer1;
+
+/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
+extern gpt_instance_ctrl_t g_timer1_ctrl;
+extern const timer_cfg_t g_timer1_cfg;
+
+#ifndef r_rf_host_timer_interrupt
+void r_rf_host_timer_interrupt(timer_callback_args_t *p_args);
+#endif
+/** External IRQ on ICU Instance. */
+extern const external_irq_instance_t g_external_irq0;
+
+/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
+extern icu_instance_ctrl_t g_external_irq0_ctrl;
+extern const external_irq_cfg_t g_external_irq0_cfg;
+
+#ifndef r_rf_ble_interrupt
+void r_rf_ble_interrupt(external_irq_callback_args_t *p_args);
+#endif
+/* Flash on Flash LP Instance. */
+extern const flash_instance_t g_flash0;
+
+/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */
+extern flash_lp_instance_ctrl_t g_flash0_ctrl;
+extern const flash_cfg_t g_flash0_cfg;
+
+#ifndef NULL
+void NULL(flash_callback_args_t *p_args);
+#endif
+
+void r_ble_rf_notify_event_start(uint32_t param);
+void r_ble_rf_notify_event_close(uint32_t param);
+void r_ble_rf_notify_deep_sleep(uint32_t param);
+
+/** BLE_ABS on BLE Instance. */
+extern const ble_abs_instance_t g_ble_abs0;
+
+/** Access the BLE_ABS instance using these structures when calling API functions directly (::p_api is not used). */
+extern ble_abs_instance_ctrl_t g_ble_abs0_ctrl;
+extern const ble_abs_cfg_t g_ble_abs0_cfg;
+
+/** Callback used by ble_abs Instance. */
+#ifndef gap_cb
+void gap_cb(uint16_t type, ble_status_t result, st_ble_evt_data_t *p_data);
+#endif
+
+#ifndef vs_cb
+void vs_cb(uint16_t type, ble_status_t result, st_ble_vs_evt_data_t *p_data);
+#endif
+
+#ifndef gs_abs_gatts_cb_param
+extern ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[];
+#else
+ble_abs_gatt_server_callback_set_t gs_abs_gatts_cb_param[];
+#endif
+
+#ifndef gs_abs_gattc_cb_param
+extern ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[];
+#else
+ble_abs_gatt_client_callback_set_t gs_abs_gattc_cb_param[];
+#endif
+
+#ifndef NULL
+void NULL(ble_abs_callback_args_t *p_args);
+#endif
+void hal_entry(void);
+void g_hal_init(void);
+FSP_FOOTER
+#endif /* HAL_DATA_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/main.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/main.c
new file mode 100644
index 0000000000..c32228b06d
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/main.c
@@ -0,0 +1,169 @@
+/* generated main source file - do not edit */
+#include "bsp_api.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+extern void new_thread0_create(void);
+extern TaskHandle_t new_thread0;
+uint32_t g_fsp_common_thread_count;
+bool g_fsp_common_initialized;
+SemaphoreHandle_t g_fsp_common_initialized_semaphore;
+#if configSUPPORT_STATIC_ALLOCATION
+StaticSemaphore_t g_fsp_common_initialized_semaphore_memory;
+#endif
+void g_hal_init(void);
+/** Weak reference for tx_err_callback */
+#if defined(__ICCARM__)
+#define rtos_startup_err_callback_WEAK_ATTRIBUTE
+#pragma weak rtos_startup_err_callback = rtos_startup_err_callback_internal
+#elif defined(__GNUC__)
+#define rtos_startup_err_callback_WEAK_ATTRIBUTE __attribute__ ((weak, alias("rtos_startup_err_callback_internal")))
+#endif
+void rtos_startup_err_callback_internal(void *p_instance, void *p_data);
+void rtos_startup_err_callback(void *p_instance, void *p_data)
+rtos_startup_err_callback_WEAK_ATTRIBUTE;
+/*********************************************************************************************************************
+ * @brief This is a weak example initialization error function. It should be overridden by defining a user function
+ * with the prototype below.
+ * - void rtos_startup_err_callback(void * p_instance, void * p_data)
+ *
+ * @param[in] p_instance arguments used to identify which instance caused the error and p_data Callback arguments used to identify what error caused the callback.
+ **********************************************************************************************************************/
+void rtos_startup_err_callback_internal(void *p_instance, void *p_data);
+void rtos_startup_err_callback_internal(void *p_instance, void *p_data)
+{
+    /** Suppress compiler warning for not using parameters. */
+    FSP_PARAMETER_NOT_USED (p_instance);
+    FSP_PARAMETER_NOT_USED (p_data);
+
+    /** An error has occurred. Please check function arguments for more information. */
+    BSP_CFG_HANDLE_UNRECOVERABLE_ERROR (0);
+}
+
+void rtos_startup_common_init(void);
+void rtos_startup_common_init(void)
+{
+    /* First thread will take care of common initialization. */
+    BaseType_t err;
+    err = xSemaphoreTake (g_fsp_common_initialized_semaphore, portMAX_DELAY);
+    if (pdPASS != err)
+    {
+        /* Check err, problem occurred. */
+        rtos_startup_err_callback (g_fsp_common_initialized_semaphore, 0);
+    }
+
+    /* Only perform common initialization if this is the first thread to execute. */
+    if (false == g_fsp_common_initialized)
+    {
+        /* Later threads will not run this code. */
+        g_fsp_common_initialized = true;
+
+        /* Perform common module initialization. */
+        g_hal_init ();
+
+        /* Now that common initialization is done, let other threads through. */
+        /* First decrement by 1 since 1 thread has already come through. */
+        g_fsp_common_thread_count--;
+        while (g_fsp_common_thread_count > 0)
+        {
+            err = xSemaphoreGive (g_fsp_common_initialized_semaphore);
+            if (pdPASS != err)
+            {
+                /* Check err, problem occurred. */
+                rtos_startup_err_callback (g_fsp_common_initialized_semaphore, 0);
+            }
+            g_fsp_common_thread_count--;
+        }
+    }
+}
+
+int main(void)
+{
+    g_fsp_common_thread_count = 0;
+    g_fsp_common_initialized = false;
+
+    /* Create semaphore to make sure common init is done before threads start running. */
+    g_fsp_common_initialized_semaphore =
+#if configSUPPORT_STATIC_ALLOCATION
+            xSemaphoreCreateCountingStatic(
+#else
+            xSemaphoreCreateCounting (
+#endif
+                                      256,
+                                      1
+#if configSUPPORT_STATIC_ALLOCATION
+                                      , &g_fsp_common_initialized_semaphore_memory
+#endif
+                                      );
+
+    if (NULL == g_fsp_common_initialized_semaphore)
+    {
+        rtos_startup_err_callback (g_fsp_common_initialized_semaphore, 0);
+    }
+
+    /* Init RTOS tasks. */
+    new_thread0_create ();
+
+    /* Start the scheduler. */
+    vTaskStartScheduler ();
+    return 0;
+}
+
+#if configSUPPORT_STATIC_ALLOCATION
+void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer,
+        uint32_t *pulIdleTaskStackSize) BSP_WEAK_REFERENCE;
+void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer,
+        uint32_t *pulTimerTaskStackSize) BSP_WEAK_REFERENCE;
+
+/* If configSUPPORT_STATIC_ALLOCATION is set to 1, the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+        StackType_t ** ppxIdleTaskStackBuffer,
+        uint32_t * pulIdleTaskStackSize )
+{
+    /* If the buffers to be provided to the Idle task are declared inside this
+     * function then they must be declared static - otherwise they will be allocated on
+     * the stack and so not exists after this function exits. */
+    static StaticTask_t xIdleTaskTCB;
+    static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+    /* Pass out a pointer to the StaticTask_t structure in which the Idle
+     * task's state will be stored. */
+    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+    /* Pass out the array that will be used as the Idle task's stack. */
+    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+     * Note that, as the array is necessarily of type StackType_t,
+     * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* If configSUPPORT_STATIC_ALLOCATION is set to 1, the application must provide an
+ * implementation of vApplicationGetTimerTaskMemory() to provide the memory that is
+ * used by the RTOS daemon/time task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+        StackType_t ** ppxTimerTaskStackBuffer,
+        uint32_t * pulTimerTaskStackSize )
+{
+    /* If the buffers to be provided to the Timer task are declared inside this
+     * function then they must be declared static - otherwise they will be allocated on
+     * the stack and so not exists after this function exits. */
+    static StaticTask_t xTimerTaskTCB;
+    static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ];
+
+    /* Pass out a pointer to the StaticTask_t structure in which the Idle
+     * task's state will be stored. */
+    *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+    /* Pass out the array that will be used as the Timer task's stack. */
+    *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+    /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+     * Note that, as the array is necessarily of type StackType_t,
+     * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+    *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.c
new file mode 100644
index 0000000000..778f6ff16c
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.c
@@ -0,0 +1,63 @@
+/* generated thread source file - do not edit */
+#include "new_thread0.h"
+
+#if 1
+static StaticTask_t new_thread0_memory;
+static uint8_t new_thread0_stack[0x2000] BSP_PLACE_IN_SECTION(".stack.new_thread0") BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT);
+#endif
+TaskHandle_t new_thread0;
+void new_thread0_create(void);
+static void new_thread0_func(void *pvParameters);
+void rtos_startup_err_callback(void *p_instance, void *p_data);
+void rtos_startup_common_init(void);
+extern uint32_t g_fsp_common_thread_count;
+
+const rm_freertos_port_parameters_t new_thread0_parameters =
+{ .p_context = (void *) NULL, };
+
+void new_thread0_create(void)
+{
+    /* Increment count so we will know the number of threads created in the RA Configuration editor. */
+    g_fsp_common_thread_count++;
+
+    /* Initialize each kernel object. */
+
+#if 1
+    new_thread0 = xTaskCreateStatic (
+#else
+                                     BaseType_t new_thread0_create_err = xTaskCreate(
+#endif
+                                     new_thread0_func,
+                                     (const char *) "New Thread", 0x2000 / 4, // In words, not bytes
+                                     (void *) &new_thread0_parameters, //pvParameters
+                                     1,
+#if 1
+                                     (StackType_t *) &new_thread0_stack,
+                                     (StaticTask_t *) &new_thread0_memory
+#else
+                                     & new_thread0
+#endif
+                                     );
+
+#if 1
+    if (NULL == new_thread0)
+    {
+        rtos_startup_err_callback (new_thread0, 0);
+    }
+#else
+    if (pdPASS != new_thread0_create_err)
+    {
+        rtos_startup_err_callback(new_thread0, 0);
+    }
+#endif
+}
+static void new_thread0_func(void *pvParameters)
+{
+    /* Initialize common components */
+    rtos_startup_common_init ();
+
+    /* Initialize each module instance. */
+
+    /* Enter user code for this thread. Pass task handle. */
+    new_thread0_entry (pvParameters);
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.h
new file mode 100644
index 0000000000..ec24504585
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/new_thread0.h
@@ -0,0 +1,16 @@
+/* generated thread header file - do not edit */
+#ifndef NEW_THREAD0_H_
+#define NEW_THREAD0_H_
+#include "bsp_api.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" void new_thread0_entry(void * pvParameters);
+#else
+extern void new_thread0_entry(void *pvParameters);
+#endif
+FSP_HEADER
+FSP_FOOTER
+#endif /* NEW_THREAD0_H_ */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/pin_data.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/pin_data.c
new file mode 100644
index 0000000000..3c0c8bcf72
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/pin_data.c
@@ -0,0 +1,65 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport_api.h"
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+	{
+		.pin = BSP_IO_PORT_01_PIN_00,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_01,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_02,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_03,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_08,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_09,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG),
+	},
+	{
+		.pin = BSP_IO_PORT_01_PIN_10,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG),
+	},
+	{
+		.pin = BSP_IO_PORT_02_PIN_04,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC),
+	},
+	{
+		.pin = BSP_IO_PORT_02_PIN_05,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8),
+	},
+	{
+		.pin = BSP_IO_PORT_02_PIN_06,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8),
+	},
+	{
+		.pin = BSP_IO_PORT_03_PIN_00,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG),
+	},
+	{
+		.pin = BSP_IO_PORT_04_PIN_02,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT),
+	},
+	{
+		.pin = BSP_IO_PORT_04_PIN_04,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH),
+	},
+	{
+		.pin = BSP_IO_PORT_04_PIN_07,
+		.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC),
+	},
+};
+const ioport_cfg_t g_bsp_pin_cfg = {
+	.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+	.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.c
new file mode 100644
index 0000000000..2c412c6b36
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.c
@@ -0,0 +1,19 @@
+/* generated vector source file - do not edit */
+#include "bsp_api.h"
+/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
+#if VECTOR_DATA_IRQ_COUNT > 0
+BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
+{
+    [0] = r_icu_isr, /* BLEIRQ (Only for BLE middleware use) */
+    [1] = gpt_counter_overflow_isr, /* GPT1 COUNTER OVERFLOW (Overflow) */
+    [2] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
+    [3] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
+};
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
+{
+    [0] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* BLEIRQ (Only for BLE middleware use) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_GPT1_COUNTER_OVERFLOW), /* GPT1 COUNTER OVERFLOW (Overflow) */
+    [2] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */
+};
+#endif
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.h b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.h
new file mode 100644
index 0000000000..e0e4dec7d6
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/ra_gen/vector_data.h
@@ -0,0 +1,35 @@
+/* generated vector header file - do not edit */
+#ifndef VECTOR_DATA_H
+#define VECTOR_DATA_H
+/* Number of interrupts allocated */
+#ifndef VECTOR_DATA_IRQ_COUNT
+#define VECTOR_DATA_IRQ_COUNT    (4)
+#endif
+/* ISR prototypes */
+void r_icu_isr(void);
+void gpt_counter_overflow_isr(void);
+void agt_int_isr(void);
+
+/* Vector table allocations */
+#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type) 0) /* BLEIRQ (Only for BLE middleware use) */
+#define VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */
+#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type) 2) /* AGT0 INT (AGT interrupt) */
+#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type) 3) /* ICU IRQ4 (External pin interrupt 4) */
+typedef enum IRQn
+{
+    Reset_IRQn = -15,
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
+    MemoryManagement_IRQn = -12,
+    BusFault_IRQn = -11,
+    UsageFault_IRQn = -10,
+    SVCall_IRQn = -5,
+    DebugMonitor_IRQn = -4,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
+    ICU_IRQ8_IRQn = 0, /* BLEIRQ (Only for BLE middleware use) */
+    GPT1_COUNTER_OVERFLOW_IRQn = 1, /* GPT1 COUNTER OVERFLOW (Overflow) */
+    AGT0_INT_IRQn = 2, /* AGT0 INT (AGT interrupt) */
+    ICU_IRQ4_IRQn = 3, /* ICU IRQ4 (External pin interrupt 4) */
+} IRQn_Type;
+#endif /* VECTOR_DATA_H */
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/script/ra4w1.ld b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/script/ra4w1.ld
new file mode 100644
index 0000000000..6b8e553975
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/script/ra4w1.ld
@@ -0,0 +1,280 @@
+/*
+                  Linker File for RA4W1 MCU
+*/
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)         : ORIGIN = 0x00000000, LENGTH = 0x0080000  /* 512K */
+  RAM (rwx)          : ORIGIN = 0x20000000, LENGTH = 0x0018000  /* 96K */
+  DATA_FLASH (rx)    : ORIGIN = 0x40100000, LENGTH = 0x0002000  /*  8K */
+
+  ID_CODE (rx)       : ORIGIN = 0x01010018, LENGTH = 0x20      /* 32 bytes */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+        __end__ = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+         *crtbegin.o(.dtors)
+         *crtbegin?.o(.dtors)
+         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+         *(SORT(.dtors.*))
+         *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* Data flash. */
+    .data_flash :
+    {
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+    } > DATA_FLASH
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/hal_entry.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/hal_entry.c
new file mode 100644
index 0000000000..a68077faf6
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/hal_entry.c
@@ -0,0 +1,39 @@
+#include "hal_data.h"
+
+FSP_CPP_HEADER
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+FSP_CPP_FOOTER
+
+/*******************************************************************************************************************//**
+ * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used.  This function
+ * is called by main() when no RTOS is used.
+ **********************************************************************************************************************/
+void hal_entry(void) {
+	/* TODO: add your own code here */
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart(bsp_warm_start_event_t event) {
+	if (BSP_WARM_START_RESET == event) {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+		/* Enable reading from data flash. */
+		R_FACI_LP->DFLCTL = 1U;
+
+		/* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+		 * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+	}
+
+	if (BSP_WARM_START_POST_C == event) {
+		/* C runtime environment and system clocks are setup. */
+
+		/* Configure pins. */
+		R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+	}
+}
diff --git a/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/new_thread0_entry.c b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/new_thread0_entry.c
new file mode 100644
index 0000000000..c035421661
--- /dev/null
+++ b/application_projects/ble_sample_application/ble_freertos_ek_ra4w1/src/new_thread0_entry.c
@@ -0,0 +1,15 @@
+#include "new_thread0.h"
+/* New Thread entry function */
+extern void app_main(void);
+/* pvParameters contains TaskHandle_t */
+void new_thread0_entry(void *pvParameters)
+{
+    FSP_PARAMETER_NOT_USED (pvParameters);
+
+    /* TODO: add your own code here */
+    app_main();
+    while (1)
+    {
+        vTaskDelay (1);
+    }
+}
diff --git a/application_projects/ble_sample_application/r01an5402ej0100-ra4w1-ble-sample-application.pdf b/application_projects/ble_sample_application/r01an5402ej0100-ra4w1-ble-sample-application.pdf
new file mode 100644
index 0000000000..73fbc1645d
Binary files /dev/null and b/application_projects/ble_sample_application/r01an5402ej0100-ra4w1-ble-sample-application.pdf differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/dependency/requirements.txt b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/dependency/requirements.txt
new file mode 100644
index 0000000000..28479d9056
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/dependency/requirements.txt
@@ -0,0 +1,5 @@
+cryptography>=2.6
+intelhex
+click
+pyasn1
+cbor
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/BL2_download.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/BL2_download.bat
new file mode 100644
index 0000000000..9833537a99
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/BL2_download.bat
@@ -0,0 +1 @@
+start "J-Link" "JLink\JLink.exe" -commanderscript s1.jlink
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLink.exe b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLink.exe
new file mode 100644
index 0000000000..bc6c2bc06f
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLink.exe differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLinkARM.dll b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLinkARM.dll
new file mode 100644
index 0000000000..3244fd253a
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/JLink/JLinkARM.dll differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/Secureboot_EK_RA6M3.bin b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/Secureboot_EK_RA6M3.bin
new file mode 100644
index 0000000000..ae28bf5d52
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/Secureboot_EK_RA6M3.bin differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/s1.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/s1.jlink
new file mode 100644
index 0000000000..1614d75af7
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/BL2_download/s1.jlink
@@ -0,0 +1,6 @@
+device R7FA6M3AH
+speed 12000
+if swd
+loadfile "Secureboot_EK_RA6M3.bin" 0x0
+rx 100
+g
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/EKRA6M3_App_primary.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/EKRA6M3_App_primary.bat
new file mode 100644
index 0000000000..9833537a99
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/EKRA6M3_App_primary.bat
@@ -0,0 +1 @@
+start "J-Link" "JLink\JLink.exe" -commanderscript s1.jlink
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLink.exe b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLink.exe
new file mode 100644
index 0000000000..bc6c2bc06f
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLink.exe differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLinkARM.dll b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLinkARM.dll
new file mode 100644
index 0000000000..3244fd253a
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/JLink/JLinkARM.dll differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/blinky_red_led_image.bin b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/blinky_red_led_image.bin
new file mode 100644
index 0000000000..08c3901ee1
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/blinky_red_led_image.bin differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/s1.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/s1.jlink
new file mode 100644
index 0000000000..e213145734
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_primary/s1.jlink
@@ -0,0 +1,6 @@
+device R7FA6M3AH
+speed 12000
+if swd
+loadfile "blinky_red_led_image.bin" 0x10000
+rx 100
+g
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/EKRA6M3_App_upgrade_3leds.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/EKRA6M3_App_upgrade_3leds.bat
new file mode 100644
index 0000000000..9833537a99
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/EKRA6M3_App_upgrade_3leds.bat
@@ -0,0 +1 @@
+start "J-Link" "JLink\JLink.exe" -commanderscript s1.jlink
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLink.exe b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLink.exe
new file mode 100644
index 0000000000..bc6c2bc06f
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLink.exe differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLinkARM.dll b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLinkARM.dll
new file mode 100644
index 0000000000..3244fd253a
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/JLink/JLinkARM.dll differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/blinky_allleds.bin b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/blinky_allleds.bin
new file mode 100644
index 0000000000..e87d293900
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/blinky_allleds.bin differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/s1.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/s1.jlink
new file mode 100644
index 0000000000..eb57014264
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade1/s1.jlink
@@ -0,0 +1,6 @@
+device R7FA6M3AH
+speed 12000
+if swd
+loadfile "blinky_allleds.bin" 0x100000
+rx 100
+g
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/EKRA6M3_App_upgrade_blueled.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/EKRA6M3_App_upgrade_blueled.bat
new file mode 100644
index 0000000000..9833537a99
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/EKRA6M3_App_upgrade_blueled.bat
@@ -0,0 +1 @@
+start "J-Link" "JLink\JLink.exe" -commanderscript s1.jlink
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLink.exe b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLink.exe
new file mode 100644
index 0000000000..bc6c2bc06f
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLink.exe differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLinkARM.dll b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLinkARM.dll
new file mode 100644
index 0000000000..3244fd253a
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/JLink/JLinkARM.dll differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/blinky_blue_led_image.bin b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/blinky_blue_led_image.bin
new file mode 100644
index 0000000000..e3bdf23819
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/blinky_blue_led_image.bin differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/s1.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/s1.jlink
new file mode 100644
index 0000000000..61141472a7
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/downloader/EKRA6M3_App_upgrade2/s1.jlink
@@ -0,0 +1,6 @@
+device R7FA6M3AH
+speed 12000
+if swd
+loadfile "blinky_blue_led_image.bin" 0x100000
+rx 100
+g
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/flash_layout/flash_layout.h b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/flash_layout/flash_layout.h
new file mode 100644
index 0000000000..a89a5c1ed5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/flash_layout/flash_layout.h
@@ -0,0 +1,136 @@
+/***********************************************************************************************************************
+* File Name    : flash_layout.h
+* Description  : Memory partition related macro definition file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/*
+ *   Flash layout on Renesas RA6M3 devices in case of MCUBOOT_OVERWRITE_ONLY use case:
+ *
+ *   Section                            Offset              Size
+ *
+ *   BL2                                0x0000_0000          64KB
+ *   Primary Image Area                 0x0001_0000         960KB
+ *   Secondary Image Area               0x0010_0000         960KB
+ *   Scratch Area                       0x001F_0000          32KB
+ */
+
+#define MAX(X,Y)                       ((X) > (Y) ? (X) : (Y))
+
+/* Size of a Secure and of a Non-secure image */
+#define FLASH_S_PARTITION_SIZE              (0)
+#define FLASH_NS_PARTITION_SIZE             (0xF0000) /* 30 * 32KB block = 960KB */
+#define FLASH_MAX_PARTITION_SIZE            ((FLASH_S_PARTITION_SIZE >   \
+                                             FLASH_NS_PARTITION_SIZE) ? \
+                                             FLASH_S_PARTITION_SIZE :    \
+                                             FLASH_NS_PARTITION_SIZE)
+
+#define FLASH_TOTAL_SIZE                    (0x00200000)    /*  2MB  */
+
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE        (0x8000)    /* 32 KB */
+
+/* Sector size of the flash hardware */
+#define FLASH_BOOT_SECTOR_SIZE              (0x2000)    /* 8 KB */
+
+/* Flash layout info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS                  (0)
+
+/* Offset and size definitions of the flash partitions that are handled by the
+ * bootloader. The image swapping is done between IMAGE_PRIMARY and
+ * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image
+ * swapping.
+ */
+#define FLASH_AREA_BL2_OFFSET               (0x0)
+#define FLASH_AREA_BL2_SIZE                 (8 * FLASH_BOOT_SECTOR_SIZE)
+
+#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
+#define FLASH_AREA_0_ID                     (1)
+#define FLASH_AREA_0_OFFSET                 (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_0_SIZE                   (FLASH_NS_PARTITION_SIZE)
+
+#define FLASH_AREA_2_ID                     (FLASH_AREA_0_ID + 1)
+#define FLASH_AREA_2_OFFSET                 (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
+#define FLASH_AREA_2_SIZE                   (FLASH_NS_PARTITION_SIZE)
+
+/* Scratch area */
+#define FLASH_AREA_SCRATCH_ID               (FLASH_AREA_2_ID + 1)
+#define FLASH_AREA_SCRATCH_OFFSET           (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+#define FLASH_AREA_SCRATCH_SIZE             (FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+/* The maximum number of status entries supported by the bootloader. */
+/* The maximum number of status entries must be at least 2. For more
+ * information see the MCUBoot issue:
+ * https://github.com/JuulLabs-OSS/mcuboot/issues/427.
+ */
+#define BOOT_STATUS_MAX_ENTRIES             ((FLASH_S_PARTITION_SIZE + \
+                                             FLASH_NS_PARTITION_SIZE) / \
+                                             FLASH_AREA_SCRATCH_SIZE)
+
+#else
+#define FLASH_AREA_SCRATCH_SIZE             (0)
+
+/* The maximum number of status entries supported by the bootloader. */
+/* The maximum number of status entries must be at least 2. For more
+ * information see the MCUBoot issue:
+ * https://github.com/JuulLabs-OSS/mcuboot/issues/427.
+ */
+#define MCUBOOT_STATUS_MAX_ENTRIES             (0)
+
+#endif
+
+
+/* Maximum number of image sectors supported by the bootloader. */
+#define MCUBOOT_MAX_IMG_SECTORS       (( FLASH_S_PARTITION_SIZE +  \
+                                      FLASH_NS_PARTITION_SIZE) / \
+                                      FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+
+#elif (MCUBOOT_IMAGE_NUMBER == 2)
+
+#else
+#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
+#endif
+
+/*  NV Counters definitions */
+#define FLASH_NV_COUNTERS_AREA_OFFSET       (0x40100000)
+#define FLASH_NV_COUNTERS_AREA_SIZE         (0x40)   /* 64 bytes */
+
+/* Flash device name used by BL2
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME               Driver_FLASH0
+
+/* NV Counters definitions */
+#define TFM_NV_COUNTERS_AREA_ADDR    FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_AREA_SIZE    (0x40) /* 64 bytes */
+#define TFM_NV_COUNTERS_SECTOR_ADDR  FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_SECTOR_SIZE  FLASH_NV_COUNTERS_AREA_SIZE
+
+#define TOTAL_ROM_SIZE               FLASH_TOTAL_SIZE
+#define TOTAL_RAM_SIZE               (0xA0000)      /* 640 KB */
+
+
+#endif /* __FLASH_LAYOUT_H__ */
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Sign.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Sign.bat
new file mode 100644
index 0000000000..45bd0ca76f
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Sign.bat
@@ -0,0 +1,18 @@
+@echo off
+rem update the path of the application project binary file in your PC.
+
+set infile=../blinky_red/Debug/blinky_red_led.bin
+
+set key=Signing_Key/signingkey.pem
+set flash_layout=../flash_layout/flash_layout.h
+set version=1.0.1+0
+set dependencies="(1,1.0.0+0)"
+
+rem update the python_path variable to the python path in your workstation.
+set python_path="C:\python_3_7_4"
+
+rem Uncomment (remove rem) from the line below to use the path set in python_path
+rem set path=%path%;%python_path%
+
+python.exe imgtool.py sign --layout %flash_layout% -k %key% --public-key-format hash --align 1 -v %version% -d %dependencies% -s 42 -H 0x400 %infile% %infile:~0,-4%_image.bin
+pause
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Signing_Key/signingkey.pem b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Signing_Key/signingkey.pem
new file mode 100644
index 0000000000..78c0c34194
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/Signing_Key/signingkey.pem
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEowIBAAKCAQEA0QYIGhhELBjo+/33DaNPH7vuXvmq0ksY01rpbRiAGfnwnDQb
+y/O8dNtC54x/EFN+Q14NVyxE0WcIDw27XO7ss5nf4E2EC6p3QWDtFShJpwG0PBDm
+aYwvX6xBTZ5cFN/y+M89Hm/nW7q0qciIfkc8lMN3Z1RLqo04NcpiYX634RXbd3PU
+vntyIYlpJPv4ZW5kPsgO14XVXErkUw0v/7f98xM5gz+jrtIPp2qd+f64zvoqvq+4
+4PqCN1T0PuEr0NMIWBj2XkzIiIExrV+wghfyimknI/Orhz6TGh3+6PgaJGZZ+Byr
+3M5oG2ZkNez6DRGdr1w6p9FnxkfvsUssYuHRyQIDAQABAoIBAEahFCHFK1v/OtLT
+eSSZl0Xw2dYr5QXULFpWsOOVUMv2QdB2ZyIehQKziEL3nYPlwpd+82EOa16awwVb
+LYF0lnUFvLltV/4dJtjnqJTqnSCamc1mJIVrwiJA8XwJ07GWDuL2G//p7jJ3v05T
+nZOV/KmD9xfqSvshZun+LgolqHqcrAa1f4cmuP9C9oqenZryljyfj7piaIZGI0JR
+PrJJ5kImYJqRcMgKTyHP4L8nwQ4moMJr6zbfbWxxb5TC7KVZSQ9UKZZ+ZLuy/pkU
+Qe4G8XSE0r+R9u4JCg87I1vgHhn8WJSxVX027OVUq5HfOzg2skQBTcExph5V9B2b
+onNxd8UCgYEA/32PW+ZwRcdKXMj+QVkxXUd6xkXy7mTXPEaQuOLWZQgrSqAFH1l4
+5/6d099KAJrjM6kR8pKXtz72IIyMHTPm332ghymjKvaEl2XP9sF+f6FmYURar4y6
+8Zh3eivP86+Q/YzOGKwtRSziBMzrAfoIXgtwH8pwIPYLP3zBV4449ZsCgYEA0XC/
+gu2ub5M6EXBnjq9K2d4LlTyAPsIbAcMSwkhOUH4YJFS22qXLYQUA9zM+DUyLCrl/
+PKN2G0HQVgMb4DIbeHv8kXB5oGm5zfbWorWqOomXB3AsI7X8YDMtf/PsZV2amBei
+qVskmPJQV21qFyeOcHlT+dHuRb0O0un3dK8RHmsCgYEApDCH4dJ80osZoflVVJ/C
+VqTqJOOtFEFgBQ+AUCEPEQyn7aRaxmPUjJsXyKJVx3/ChV+g9hf5Qj1HJXHNVbMW
+KwhsEpDSmHimizlV5clBxzntNpMcCHdTaJHILo5bbMqmThugE0ELMsp+UgFzAeky
+WWXWX8fUOYqFff5prh/rQQMCgYBQQ8FhT+113Rp37HgDerJY5HvT6afMZV8sQbJC
+uqsotepSohShnsBeoihIlF7HgfoXVhepCYwNzh8ll3NrbEiS2BFnO4+hJmOKx3pi
+SPTAElLLCvYfiXL6+yII01ZZUpIYj5ZLCR7xbovTtZ7e2M4B1L2WFBoYp+eydO/c
+y+rnmQKBgCh0gfyBT/OKPkfKv+Bbt8HcoxgEj+TyH+vYdeTbP9ZSJ6y5utMbPg7z
+iLLbJ+9IcSwPCwJSmI+I0Om4xEp4ZblCrzAG7hWvG2NNzxQjmoOOrAANyTvJR/ap
+N+UkQA4WrMSKEYyBlRS/hR9Unz31vMc2k9Re0ukWhWh/QksQGDfJ
+-----END RSA PRIVATE KEY-----
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/__pycache__/macro_parser.cpython-37.pyc b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/__pycache__/macro_parser.cpython-37.pyc
new file mode 100644
index 0000000000..651a09f046
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/__pycache__/macro_parser.cpython-37.pyc differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/assemble.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/assemble.py
new file mode 100644
index 0000000000..5a75424699
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/assemble.py
@@ -0,0 +1,93 @@
+#! /usr/bin/env python3
+#
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2017-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Assemble multiple images into a single image that can be flashed on the device.
+"""
+
+import argparse
+import errno
+import io
+import re
+import os
+import shutil
+import macro_parser
+
+offset_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_OFFSET\s*=\s*(.*)")
+size_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_MAX_SIZE\s*=\s*(.*)")
+
+class Assembly():
+    def __init__(self, layout_path, output):
+        self.output = output
+        self.layout_path = layout_path
+        self.find_slots()
+        try:
+            os.unlink(output)
+        except OSError as e:
+            if e.errno != errno.ENOENT:
+                raise
+
+    def find_slots(self):
+        offsets = {}
+        sizes = {}
+
+        offsets = macro_parser.evaluate_macro(self.layout_path, offset_re, 1, 2)
+        sizes = macro_parser.evaluate_macro(self.layout_path, size_re, 1, 2)
+
+        if 'SECURE' not in offsets:
+            raise Exception("Image config does not have secure partition")
+
+        if 'NON_SECURE' not in offsets:
+            raise Exception("Image config does not have non-secure partition")
+
+        self.offsets = offsets
+        self.sizes = sizes
+
+    def add_image(self, source, partition):
+        with open(self.output, 'ab') as ofd:
+            ofd.seek(0, os.SEEK_END)
+            pos = ofd.tell()
+            if pos > self.offsets[partition]:
+                raise Exception("Partitions not in order, unsupported")
+            if pos < self.offsets[partition]:
+                ofd.write(b'\xFF' * (self.offsets[partition] - pos))
+            statinfo = os.stat(source)
+            if statinfo.st_size > self.sizes[partition]:
+                raise Exception("Image {} is too large for partition".format(source))
+            with open(source, 'rb') as rfd:
+                shutil.copyfileobj(rfd, ofd, 0x10000)
+
+def main():
+    parser = argparse.ArgumentParser()
+
+    parser.add_argument('-l', '--layout', required=True,
+            help='Location of the file that contains preprocessed macros')
+    parser.add_argument('-s', '--secure', required=True,
+            help='Unsigned secure image')
+    parser.add_argument('-n', '--non_secure',
+            help='Unsigned non-secure image')
+    parser.add_argument('-o', '--output', required=True,
+            help='Filename to write full image to')
+
+    args = parser.parse_args()
+    output = Assembly(args.layout, args.output)
+
+    output.add_image(args.secure, "SECURE")
+    output.add_image(args.non_secure, "NON_SECURE")
+
+if __name__ == '__main__':
+    main()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool.py
new file mode 100644
index 0000000000..2d1d97bbb9
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool.py
@@ -0,0 +1,216 @@
+#! /usr/bin/env python3
+#
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function
+import os
+import re
+import argparse
+from imgtool_lib import keys
+from imgtool_lib import image
+from imgtool_lib import version
+import sys
+import macro_parser
+
+sign_bin_size_re = re.compile(r"^\s*RE_SIGN_BIN_SIZE\s*=\s*(.*)")
+image_load_address_re = re.compile(r"^\s*RE_IMAGE_LOAD_ADDRESS\s*=\s*(.*)")
+
+# Returns the last version number if present, or None if not
+def get_last_version(path):
+    if (os.path.isfile(path) == False): # Version file not present
+        return None
+    else: # Version file is present, check it has a valid number inside it
+        with open(path, "r") as oldFile:
+            fileContents = oldFile.read()
+            if version.version_re.match(fileContents): # number is valid
+                return version.decode_version(fileContents)
+            else:
+                return None
+
+def next_version_number(args, defaultVersion, path):
+    newVersion = None
+    versionProvided = False
+    if (version.compare(args.version, defaultVersion) == 0): # Default version
+        lastVersion = get_last_version(path)
+        if (lastVersion is not None):
+            newVersion = version.increment_build_num(lastVersion)
+        else:
+            newVersion = version.increment_build_num(defaultVersion)
+    else: # Version number has been explicitly provided (not using the default)
+        versionProvided = True
+        newVersion = args.version
+    versionString = "{a}.{b}.{c}+{d}".format(
+                    a=str(newVersion.major),
+                    b=str(newVersion.minor),
+                    c=str(newVersion.revision),
+                    d=str(newVersion.build)
+    )
+    if not versionProvided:
+        with open(path, "w") as newFile:
+            newFile.write(versionString)
+    print("**[INFO]** Image version number set to " + versionString)
+    return newVersion
+
+def gen_rsa2048(args):
+    keys.RSAutil.generate().export_private(args.key)
+
+def gen_rsa3072(args):
+    keys.RSAutil.generate(key_size=3072).export_private(args.key)
+
+keygens = {
+        'rsa-2048': gen_rsa2048,
+        'rsa-3072': gen_rsa3072, }
+
+def do_keygen(args):
+    if args.type not in keygens:
+        msg = "Unexpected key type: {}".format(args.type)
+        raise argparse.ArgumentTypeError(msg)
+    keygens[args.type](args)
+
+def do_getpub(args):
+    key = keys.load(args.key)
+    if args.lang == 'c':
+        key.emit_c()
+    else:
+        msg = "Unsupported language, valid are: c"
+        raise argparse.ArgumentTypeError(msg)
+
+def do_sign(args):
+    if args.rsa_pkcs1_15:
+        keys.sign_rsa_pss = False
+
+    version_num = next_version_number(args,
+                                      version.decode_version("0"),
+                                      "lastVerNum.txt")
+
+    if args.security_counter is None:
+        # Security counter has not been explicitly provided,
+        # generate it from the version number
+        args.security_counter = ((version_num.major << 24)
+                                 + (version_num.minor << 16)
+                                 + version_num.revision)
+
+    if "_s.c" in args.layout:
+        sw_type = "SPE"
+    elif "_ns.c" in args.layout:
+        sw_type = "NSPE"
+    else:
+        sw_type = "NSPE_SPE"
+
+    pad_size = macro_parser.evaluate_macro(args.layout, sign_bin_size_re, 0, 1)
+    img = image.Image.load(args.infile,
+                           version=version_num,
+                           header_size=args.header_size,
+                           security_cnt=args.security_counter,
+                           included_header=args.included_header,
+                           pad=pad_size)
+    key = keys.load(args.key, args.public_key_format) if args.key else None
+    ram_load_address = macro_parser.evaluate_macro(args.layout, image_load_address_re, 0, 1)
+    img.sign(sw_type, key, ram_load_address, args.dependencies)
+
+    if pad_size:
+        img.pad_to(pad_size, args.align)
+
+    img.save(args.outfile)
+
+subcmds = {
+        'keygen': do_keygen,
+        'getpub': do_getpub,
+        'sign': do_sign, }
+
+
+def get_dependencies(text):
+    if text is not None:
+        versions = []
+        images = re.findall(r"\((\d+)", text)
+        if len(images) == 0:
+            msg = "Image dependency format is invalid: {}".format(text)
+            raise argparse.ArgumentTypeError(msg)
+        raw_versions = re.findall(r",\s*([0-9.+]+)\)", text)
+        if len(images) != len(raw_versions):
+            msg = '''There's a mismatch between the number of dependency images
+            and versions in: {}'''.format(text)
+            raise argparse.ArgumentTypeError(msg)
+        for raw_version in raw_versions:
+            try:
+                versions.append(version.decode_version(raw_version))
+            except ValueError as e:
+                print(e)
+        dependencies = dict()
+        dependencies[image.DEP_IMAGES_KEY] = images
+        dependencies[image.DEP_VERSIONS_KEY] = versions
+        return dependencies
+
+
+def alignment_value(text):
+    value = int(text)
+    if value not in [1, 2, 4, 8]:
+        msg = "{} must be one of 1, 2, 4 or 8".format(value)
+        raise argparse.ArgumentTypeError(msg)
+    return value
+
+def intparse(text):
+    """Parse a command line argument as an integer.
+
+    Accepts 0x and other prefixes to allow other bases to be used."""
+    return int(text, 0)
+
+def args():
+    parser = argparse.ArgumentParser()
+    subs = parser.add_subparsers(help='subcommand help', dest='subcmd')
+
+    keygenp = subs.add_parser('keygen', help='Generate pub/private keypair')
+    keygenp.add_argument('-k', '--key', metavar='filename', required=True)
+    keygenp.add_argument('-t', '--type', metavar='type',
+                         choices=keygens.keys(), required=True)
+
+    getpub = subs.add_parser('getpub', help='Get public key from keypair')
+    getpub.add_argument('-k', '--key', metavar='filename', required=True)
+    getpub.add_argument('-l', '--lang', metavar='lang', default='c')
+
+    sign = subs.add_parser('sign', help='Sign an image with a private key')
+    sign.add_argument('-l', '--layout', required=True,
+                      help='Location of the file that contains preprocessed macros')
+    sign.add_argument('-k', '--key', metavar='filename')
+    sign.add_argument("-K", "--public-key-format",
+                      help='In what format to add the public key to the image manifest: full or hash',
+                      metavar='pub_key_format', choices=['full', 'hash'], default='hash')
+    sign.add_argument("--align", type=alignment_value, required=True)
+    sign.add_argument("-v", "--version", type=version.decode_version,
+                      default="0.0.0+0")
+    sign.add_argument("-d", "--dependencies", type=get_dependencies,
+                      required=False, help='''Add dependence on another image,
+                      format: "(,), ... "''')
+    sign.add_argument("-s", "--security-counter", type=intparse,
+                      help='Specify explicitly the security counter value')
+    sign.add_argument("-H", "--header-size", type=intparse, required=True)
+    sign.add_argument("--included-header", default=False, action='store_true',
+                      help='Image has gap for header')
+    sign.add_argument("--rsa-pkcs1-15",
+                      help='Use old PKCS#1 v1.5 signature algorithm',
+                      default=False, action='store_true')
+    sign.add_argument("infile")
+    sign.add_argument("outfile")
+
+    args = parser.parse_args()
+    if args.subcmd is None:
+        print('Must specify a subcommand', file=sys.stderr)
+        sys.exit(1)
+
+    subcmds[args.subcmd](args)
+
+if __name__ == '__main__':
+    args()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/__init__.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/__init__.py
new file mode 100644
index 0000000000..fd240440dc
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/__init__.py
@@ -0,0 +1,18 @@
+# Copyright 2017 Linaro Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# This file is intentionally empty.
+#
+# The __init__.py files are required to make Python treat the directories as
+# containing packages.
\ No newline at end of file
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diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/boot_record.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/boot_record.py
new file mode 100644
index 0000000000..41887bb5f0
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/boot_record.py
@@ -0,0 +1,77 @@
+
+# Copyright (c) 2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import cbor
+
+
+# SW component IDs
+SW_COMPONENT_RANGE = 0
+SW_COMPONENT_TYPE = SW_COMPONENT_RANGE + 1
+MEASUREMENT_VALUE = SW_COMPONENT_RANGE + 2
+SW_COMPONENT_VERSION = SW_COMPONENT_RANGE + 4
+SIGNER_ID = SW_COMPONENT_RANGE + 5
+MEASUREMENT_DESCRIPTION = SW_COMPONENT_RANGE + 6
+
+
+def create_sw_component_data(sw_type, sw_version, sw_measurement_type,
+                             sw_measurement_value, sw_signer_id):
+
+    # List of SW component claims (key ID + value)
+    key_value_list = [
+        SW_COMPONENT_TYPE, sw_type,
+        SW_COMPONENT_VERSION, sw_version,
+        SIGNER_ID, sw_signer_id,
+        MEASUREMENT_DESCRIPTION, sw_measurement_type,
+        MEASUREMENT_VALUE, sw_measurement_value
+    ]
+    # The measurement value should be the last item (key + value) in the list
+    # to make it easier to modify its value later in the bootloader.
+    # A dictionary would be the best suited data structure to store these
+    # key-value pairs (claims), however dictionaries are not sorted, but for
+    # example the lists do keep to order of items which we care about now.
+    # An ordered dictionary could be used instead, but it would be converted
+    # to a dict before the encoding and this conversion may not keep the order
+    # of the items.
+
+    if (len(key_value_list) % 2) != 0:
+        print('Error: The length of the sw component claim list must '
+              'be even (key + value).', file=sys.stderr)
+        sys.exit(1)
+    else:
+        claim_number = (int)(len(key_value_list) / 2)
+
+    # The output of this function must be a CBOR encoded map (dictionary) of
+    # the SW component claims. The CBOR representation of an array and a map
+    # (dictionary) is quite similar. To convert the encoded list to a map, it
+    # is enough to modify the first byte (CBOR data item header) of the
+    # data. This applies up to 23 items (11 claims in this case) - until the 5
+    # lower bits of the item header are used as an item count specifier.
+
+    if claim_number > 11:
+        print('Error: There are more than 11 claims in the '
+              'list of sw component claims.', file=sys.stderr)
+        sys.exit(1)
+
+    record_array = bytearray(cbor.dumps(key_value_list))
+    # Modify the CBOR data item header (from array to map)
+    # 7..5 bits : Major type
+    #             Array - 0x80
+    #             Map   - 0xA0
+    # 4..0 bits : Number of items
+    record_array[0] = 0xA0 + claim_number
+
+    return bytes(record_array)
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/image.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/image.py
new file mode 100644
index 0000000000..d790a75f7e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/image.py
@@ -0,0 +1,267 @@
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Image signing and management.
+"""
+
+from . import version as versmod
+from . import boot_record as br
+import hashlib
+import struct
+
+IMAGE_MAGIC = 0x96f3b83d
+IMAGE_HEADER_SIZE = 32
+TLV_HEADER_SIZE = 4
+PAYLOAD_DIGEST_SIZE = 32  # SHA256 hash
+KEYHASH_SIZE = 32
+DEP_IMAGES_KEY = "images"
+DEP_VERSIONS_KEY = "versions"
+
+# Image header flags.
+IMAGE_F = {
+        'PIC':                   0x0000001,
+        'NON_BOOTABLE':          0x0000010,
+        'RAM_LOAD':              0x0000020, }
+TLV_VALUES = {
+        'KEYHASH': 0x01,
+        'KEY'    : 0x02,
+        'SHA256' : 0x10,
+        'RSA2048': 0x20,
+        'RSA3072': 0x23,
+        'DEPENDENCY': 0x40,
+        'SEC_CNT': 0x50,
+        'BOOT_RECORD': 0x60, }
+
+TLV_INFO_SIZE = 4
+TLV_INFO_MAGIC = 0x6907
+TLV_PROT_INFO_MAGIC = 0x6908
+
+# Sizes of the image trailer, depending on flash write size.
+trailer_sizes = {
+    write_size: 128 * 3 * write_size + 8 * 2 + 16
+    for write_size in [1, 2, 4, 8]
+}
+
+boot_magic = bytearray([
+    0x77, 0xc2, 0x95, 0xf3,
+    0x60, 0xd2, 0xef, 0x7f,
+    0x35, 0x52, 0x50, 0x0f,
+    0x2c, 0xb6, 0x79, 0x80, ])
+
+class TLV():
+    def __init__(self, magic=TLV_INFO_MAGIC):
+        self.magic = magic
+        self.buf = bytearray()
+
+    def __len__(self):
+        return TLV_INFO_SIZE + len(self.buf)
+
+    def add(self, kind, payload):
+        """
+        Add a TLV record.  Kind should be a string found in TLV_VALUES above.
+        """
+        buf = struct.pack(' 0:
+            obj.payload = (b'\000' * obj.header_size) + obj.payload
+
+        obj.check()
+        return obj
+
+    def __init__(self, version, header_size=IMAGE_HEADER_SIZE, security_cnt=0,
+                 pad=0):
+        self.version = version
+        self.header_size = header_size or IMAGE_HEADER_SIZE
+        self.security_cnt = security_cnt
+        self.pad = pad
+
+    def __repr__(self):
+        return "".format(
+                self.version,
+                self.header_size,
+                self.security_cnt,
+                self.pad,
+                len(self.payload))
+
+    def save(self, path):
+        with open(path, 'wb') as f:
+            f.write(self.payload)
+
+    def check(self):
+        """Perform some sanity checking of the image."""
+        # If there is a header requested, make sure that the image
+        # starts with all zeros.
+        if self.header_size > 0:
+            if any(v != 0 and v != b'\000' for v in self.payload[0:self.header_size]):
+                raise Exception("Padding requested, but image does not start with zeros")
+
+    def sign(self, sw_type, key, ramLoadAddress, dependencies=None):
+        image_version = (str(self.version.major) + '.'
+                      + str(self.version.minor) + '.'
+                      + str(self.version.revision))
+
+        # Calculate the hash of the public key
+        if key is not None:
+            pub = key.get_public_bytes()
+            sha = hashlib.sha256()
+            sha.update(pub)
+            pubbytes = sha.digest()
+        else:
+            pubbytes = bytes(KEYHASH_SIZE)
+
+        # The image hash is computed over the image header, the image itself
+        # and the protected TLV area. However, the boot record TLV (which is
+        # part of the protected area) should contain this hash before it is
+        # even calculated. For this reason the script fills this field with
+        # zeros and the bootloader will insert the right value later.
+        image_hash = bytes(PAYLOAD_DIGEST_SIZE)
+
+        # Create CBOR encoded boot record
+        boot_record = br.create_sw_component_data(sw_type, image_version,
+                                                  "SHA256", image_hash,
+                                                  pubbytes)
+
+        # Mandatory protected TLV area: TLV info header
+        #                               + security counter TLV
+        #                               + boot record TLV
+        # Size of the security counter TLV: header ('BBH') + payload ('I')
+        #                                   = 8 Bytes
+        protected_tlv_size = TLV_INFO_SIZE + 8 + TLV_HEADER_SIZE \
+                           + len(boot_record)
+
+        if dependencies is None:
+            dependencies_num = 0
+        else:
+            # Size of a dependency TLV:
+            # header ('BBH') + payload('IBBHI') = 16 Bytes
+            dependencies_num = len(dependencies[DEP_IMAGES_KEY])
+            protected_tlv_size += (dependencies_num * 16)
+
+        # At this point the image is already on the payload, this adds
+        # the header to the payload as well
+        self.add_header(key, protected_tlv_size, ramLoadAddress)
+
+        prot_tlv = TLV(TLV_PROT_INFO_MAGIC)
+
+        # Protected TLVs must be added first, because they are also included
+        # in the hash calculation
+        payload = struct.pack('I', self.security_cnt)
+        prot_tlv.add('SEC_CNT', payload)
+        prot_tlv.add('BOOT_RECORD', boot_record)
+
+        if dependencies_num != 0:
+            for i in range(dependencies_num):
+                payload = struct.pack(
+                                '<'+'B3x'+'BBHI',
+                                int(dependencies[DEP_IMAGES_KEY][i]),
+                                dependencies[DEP_VERSIONS_KEY][i].major,
+                                dependencies[DEP_VERSIONS_KEY][i].minor,
+                                dependencies[DEP_VERSIONS_KEY][i].revision,
+                                dependencies[DEP_VERSIONS_KEY][i].build
+                                )
+                prot_tlv.add('DEPENDENCY', payload)
+
+        self.payload += prot_tlv.get()
+
+        sha = hashlib.sha256()
+        sha.update(self.payload)
+        image_hash = sha.digest()
+
+        tlv = TLV()
+
+        tlv.add('SHA256', image_hash)
+
+        if key is not None:
+            if key.get_public_key_format() == 'hash':
+                tlv.add('KEYHASH', pubbytes)
+            else:
+                tlv.add('KEY', pub)
+
+            sig = key.sign(self.payload)
+            tlv.add(key.sig_tlv(), sig)
+
+        self.payload += tlv.get()
+
+    def add_header(self, key, protected_tlv_size, ramLoadAddress):
+        """Install the image header.
+
+        The key is needed to know the type of signature, and
+        approximate the size of the signature."""
+
+        flags = 0
+        if ramLoadAddress is not None:
+            # add the load address flag to the header to indicate that an SRAM
+            # load address macro has been defined
+            flags |= IMAGE_F["RAM_LOAD"]
+
+        fmt = ('<' +
+            # type ImageHdr struct {
+            'I' +    # Magic    uint32
+            'I' +    # LoadAddr uint32
+            'H' +    # HdrSz    uint16
+            'H' +    # PTLVSz   uint16
+            'I' +    # ImgSz    uint32
+            'I' +    # Flags    uint32
+            'BBHI' + # Vers     ImageVersion
+            'I'      # Pad1     uint32
+            ) # }
+        assert struct.calcsize(fmt) == IMAGE_HEADER_SIZE
+        header = struct.pack(fmt,
+                IMAGE_MAGIC,
+                0 if (ramLoadAddress is None) else ramLoadAddress, # LoadAddr
+                self.header_size,
+                protected_tlv_size,  # TLV info header + Protected TLVs
+                len(self.payload) - self.header_size,  # ImageSz
+                flags,
+                self.version.major,
+                self.version.minor or 0,
+                self.version.revision or 0,
+                self.version.build or 0,
+                0)  # Pad1
+        self.payload = bytearray(self.payload)
+        self.payload[:len(header)] = header
+
+    def pad_to(self, size, align):
+        """Pad the image to the given size, with the given flash alignment."""
+        tsize = trailer_sizes[align]
+        padding = size - (len(self.payload) + tsize)
+        if padding < 0:
+            msg = "Image size (0x{:x}) + trailer (0x{:x}) exceeds requested size 0x{:x}".format(
+                    len(self.payload), tsize, size)
+            raise Exception(msg)
+        pbytes  = b'\xff' * padding
+        pbytes += b'\xff' * (tsize - len(boot_magic))
+        pbytes += boot_magic
+        self.payload += pbytes
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/keys.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/keys.py
new file mode 100644
index 0000000000..7ee9671bd5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/keys.py
@@ -0,0 +1,136 @@
+# Copyright (c) 2017,2019 Linaro Limited.
+# Copyright (c) 2017-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Cryptographic key management for imgtool.
+"""
+
+from __future__ import print_function
+from cryptography.hazmat.backends import default_backend
+from cryptography.hazmat.primitives import serialization
+from cryptography.hazmat.primitives.hashes import SHA256
+from cryptography.hazmat.primitives.asymmetric import rsa
+from cryptography.hazmat.primitives.asymmetric.padding import PSS, PKCS1v15
+from cryptography.hazmat.primitives.asymmetric.padding import MGF1
+import hashlib
+from pyasn1.type import namedtype, univ
+from pyasn1.codec.der.encoder import encode
+
+# Sizes that bootutil will recognize
+RSA_KEY_SIZES = [2048, 3072]
+
+# Public exponent
+PUBLIC_EXPONENT = 65537
+
+# By default, we use RSA-PSS (PKCS 2.1).  That can be overridden on
+# the command line to support the older (less secure) PKCS1.5
+sign_rsa_pss = True
+
+AUTOGEN_MESSAGE = "/* Autogenerated by imgtool.py, do not edit. */"
+
+class RSAUsageError(Exception):
+    pass
+
+class RSAutil():
+    def __init__(self, key, public_key_format='hash'):
+        """Construct an RSA key with the given key data"""
+        self.key = key
+        self.public_key_format = public_key_format
+
+    def key_size(self):
+        return self.key.key_size
+
+    def get_public_key_format(self):
+        return self.public_key_format
+
+    @staticmethod
+    def generate(key_size=2048):
+        if key_size not in RSA_KEY_SIZES:
+            raise RSAUsageError("Key size {} is not supported by MCUboot"
+                                .format(key_size))
+        return RSAutil(rsa.generate_private_key(
+                public_exponent=PUBLIC_EXPONENT,
+                key_size=key_size,
+                backend=default_backend()))
+
+    def export_private(self, path):
+        with open(path, 'wb') as f:
+            f.write(self.key.private_bytes(
+                    encoding=serialization.Encoding.PEM,
+                    format=serialization.PrivateFormat.TraditionalOpenSSL,
+                    encryption_algorithm=serialization.NoEncryption()))
+
+    def get_public_bytes(self):
+        return self.key.public_key().public_bytes(
+                encoding=serialization.Encoding.DER,
+                format=serialization.PublicFormat.PKCS1)
+
+    def emit_c(self):
+        print(AUTOGEN_MESSAGE)
+        print("const unsigned char rsa_pub_key[] = {", end='')
+        encoded = self.get_public_bytes()
+        for count, b in enumerate(encoded):
+            if count % 8 == 0:
+                print("\n\t", end='')
+            else:
+                print(" ", end='')
+            print("0x{:02x},".format(b), end='')
+        print("\n};")
+        print("const unsigned int rsa_pub_key_len = {};".format(len(encoded)))
+
+    def sig_type(self):
+        """Return the type of this signature (as a string)"""
+        if sign_rsa_pss:
+            return "PKCS1_PSS_RSA{}_SHA256".format(self.key_size())
+        else:
+            return "PKCS15_RSA{}_SHA256".format(self.key_size())
+
+    def sig_len(self):
+        return 256 if self.key_size() == 2048 else 384
+
+    def sig_tlv(self):
+        return "RSA2048" if self.key_size() == 2048 else "RSA3072"
+
+    def sign(self, payload):
+        if sign_rsa_pss:
+            signature = self.key.sign(
+                data=payload,
+                padding=PSS(
+                    mgf=MGF1(SHA256()),
+                    salt_length=32
+                ),
+                algorithm=SHA256()
+            )
+        else:
+            signature = self.key.sign(
+                data=payload,
+                padding=PKCS1v15(),
+                algorithm=SHA256()
+            )
+        assert len(signature) == self.sig_len()
+        return signature
+
+def load(path, public_key_format='hash'):
+    with open(path, 'rb') as f:
+        pem = f.read()
+    try:
+        key = serialization.load_pem_private_key(
+            pem,
+            password=None,
+            backend=default_backend()
+        )
+        return RSAutil(key, public_key_format)
+    except ValueError:
+        raise Exception("Unsupported RSA key file")
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/version.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/version.py
new file mode 100644
index 0000000000..d1d45f0385
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/imgtool_lib/version.py
@@ -0,0 +1,66 @@
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Semi Semantic Versioning
+
+Implements a subset of semantic versioning that is supportable by the image header.
+"""
+
+import argparse
+from collections import namedtuple
+import re
+
+SemiSemVersion = namedtuple('SemiSemVersion', ['major', 'minor', 'revision', 'build'])
+
+def increment_build_num(lastVer):
+    newVer = SemiSemVersion(lastVer.major, lastVer.minor, lastVer.revision, lastVer.build + 1)
+    return newVer
+
+# -1 if a is older than b; 0 if they're the same version; 1 if a is newer than b
+def compare(a, b):
+    if (a.major > b.major): return 1
+    elif (a.major < b.major): return -1
+    else:
+        if (a.minor > b.minor): return 1
+        elif (a.minor < b.minor): return -1
+        else:
+            if (a.revision > b.revision): return 1
+            elif (a.revision < b.revision): return -1
+            else:
+                if (a.build > b.build): return 1
+                elif (a.build < b.build): return -1
+                else: return 0
+
+version_re = re.compile(r"""^([1-9]\d*|0)(\.([1-9]\d*|0)(\.([1-9]\d*|0)(\+([1-9]\d*|0))?)?)?$""")
+def decode_version(text):
+    """Decode the version string, which should be of the form maj.min.rev+build"""
+    m = version_re.match(text)
+    if m:
+        result = SemiSemVersion(
+                int(m.group(1)) if m.group(1) else 0,
+                int(m.group(3)) if m.group(3) else 0,
+                int(m.group(5)) if m.group(5) else 0,
+                int(m.group(7)) if m.group(7) else 0)
+        return result
+    else:
+        msg = "Invalid version number, should be maj.min.rev+build with later parts optional"
+        raise argparse.ArgumentTypeError(msg)
+
+if __name__ == '__main__':
+    print(decode_version("1.2"))
+    print(decode_version("1.0"))
+    print(decode_version("0.0.2+75"))
+    print(decode_version("0.0.0+00"))
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/macro_parser.py b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/macro_parser.py
new file mode 100644
index 0000000000..5e489a9c57
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/image_creation/macro_parser.py
@@ -0,0 +1,70 @@
+#! /usr/bin/env python3
+#
+# -----------------------------------------------------------------------------
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# -----------------------------------------------------------------------------
+
+
+import re
+import os
+
+expression_re = re.compile(r"[(]?(([(]?(((0x)[0-9a-fA-F]+)|([0-9]+))[)]?)\s*([\+\-]\s*([(]?(((0x)[0-9a-fA-F]+)|([0-9]+))[)]?)\s*)*)[)]?")
+
+# Simple parser that takes a string and evaluates an expression from it.
+# The expression might contain additions and subtractions amongst numbers that
+# are written in decimal or hexadecimal form.
+# The parses can process expressions in which the parentheses does not change
+# the sign of the following number or numbers in an expression.
+# Thus the parser can process the following expression: (x + y)
+# However it will not calculate the correct sum for the expression below:
+# (x - (y + z))
+def parse_and_sum(text):
+    m = expression_re.match(text)
+    if m is None:
+        msg = "The script was probably invoked manually"
+        msg += " with having certain macros nested in flash_layouts.h.\n"
+        msg += "Please revisit the flash_layout.h file and hardcode values"
+        msg += " for the (NON-)SECURE_IMAGE_OFFSET and"
+        msg += " (NON-)SECURE_IMAGE_MAX_SIZE macros"
+        raise Exception(msg)
+
+    nums = re.findall(r'(0x[A-Fa-f0-9]+)|[\d]+', m.group(0))
+    for i in range(len(nums)):
+        nums[i] = int(nums[i], 0)
+    ops = re.findall(r'\+|\-', m.group(0))
+    sum = nums[0]
+    for i in range(len(ops)):
+        if ops[i] == '+':
+            sum += nums[i+1]
+        else:
+            sum -= nums[i+1]
+    return sum
+
+
+# Opens a file that contains the macro of interest, then finds the macro with
+# a regular expression, parses the expression that is defined for the given
+# macro. Lastly it evaluates the expression with the parse_and_sum function
+def evaluate_macro(file, regexp, matchGroupKey, matchGroupData):
+    regexp_compiled = re.compile(regexp)
+
+    if os.path.isabs(file):
+        configFile = file
+    else:
+        scriptsDir = os.path.dirname(os.path.abspath(__file__))
+        configFile = os.path.join(scriptsDir, file)
+
+    macroValue = {}
+    with open(configFile, 'r') as macros_preprocessed_file:
+        for line in macros_preprocessed_file:
+            m = regexp_compiled.match(line)
+            if m is not None:
+                macroValue[m.group(matchGroupKey)] = \
+                parse_and_sum(m.group(matchGroupData))
+
+    if (matchGroupKey == 0 and not macroValue):
+        macroValue["None"] = None
+
+    return list(macroValue.values())[0] if (matchGroupKey == 0) else macroValue
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLink.exe b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLink.exe
new file mode 100644
index 0000000000..bc6c2bc06f
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLink.exe differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLinkARM.dll b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLinkARM.dll
new file mode 100644
index 0000000000..3244fd253a
Binary files /dev/null and b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/JLink/JLinkARM.dll differ
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_ERASE_SMPU.bat b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_ERASE_SMPU.bat
new file mode 100644
index 0000000000..14b8fd8040
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_ERASE_SMPU.bat
@@ -0,0 +1 @@
+start "J-Link" "JLink\JLink.exe" -commanderscript RA6M3_Erase_SMPU.jlink
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_Erase_SMPU.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_Erase_SMPU.jlink
new file mode 100644
index 0000000000..0089050619
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/scripts/reset_kit/SMPU_Reset/RA6M3_Erase_SMPU.jlink
@@ -0,0 +1,135 @@
+Device R7FA6M3AH
+si SWD
+speed 2000
+connect
+
+
+/* Reset the device */
+r
+
+/* Enable CGC register write */
+w2 0x4001E3FE, 0xA501
+
+/* write SCKDIVCR ICK and FCLK /1, so 8MHz*/
+w4 0x4001E020, 0x00000000
+
+/* Read SCKDIVCR */
+mem32 0x4001E020, 1
+
+/* Sleep for 10ms to allow things to settle */
+sleep 10
+
+
+/***** Clear out the AWS bits ***************/
+
+/* FPCKAR PCKA for default of 2MHz PCKA (MOCO/4) as set by default values of SCKSCR and SCKDIVCR after reset*/
+w2 0x407FE0E4, 0x1E02 
+
+/*FWEPROP set to 1, Allow access to the flash registers */
+w1 0x4001E416, 0x01 
+
+/* FENTRYR = 0xAA01, code flash, RV40 Phase 2 */
+w2 0x407FE084, 0xAA01
+
+/* FSADDR = 0x0000A160U, RV40 Phase 2 */
+w4 0x407FE030, 0x0000A160
+
+/* Write 40h to the FACI command issuing area */
+w1 0x407E0000, 0x40
+
+/* Write 08h to the FACI command issuing area */
+w1 0x407E0000, 0x08
+
+/* Write WD0 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD1 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD2 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD3 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD4 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD5 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD6 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write WD7 to the FACI command issuing area */
+w2 0x407E0000, 0xffff
+
+/* Write D0h to the FACI command issuing area - final access, start FACI processing the command */
+w1 0x407E0000, 0xD0
+
+/* Read the FSTATR Reg, is FRDY bit 1 yet (probably not) */
+ mem32 0x407FE080, 1
+
+/* wait for 1sec, more than enough time for the operation! */
+sleep 1000
+
+/* Read the FSTATR Reg, FRDY bit should be 1 by now (register should read 0x00008000) */
+ mem32 0x407FE080, 1
+
+/* FENTRYR = AA01H - return to ROM read mode */
+w2 0x407FE084, 0xAA00
+
+/* Read the AWS area*/
+mem32 0x0010A160,16
+
+/***** Erase first block to clear out the SecureMPU bits ***************/
+* Reset the device */
+r
+
+/* Sleep for 10ms to allow things to settle */
+sleep 10
+
+/* FPCKAR PCKA for FCLK of 8Mhz */
+w2 0x407FE0E4, 0x1E08 
+
+/*FWEPROP set to 1, Allow access to the flash registers */
+w1 0x4001E416, 0x01 
+
+/* FENTRYR = 0xAA01, code flash, RV40 Phase 2 */
+w2 0x407FE084, 0xAA01
+
+/* FSADDR = Start address of the flash block */
+w4 0x407FE030, 0x00000000
+
+/* Write 20h to the FACI command issuing area */
+w1 0x407E0000, 0x20
+
+/* Write D0h to the FACI command issuing area - final access, start FACI processing the command */
+w1 0x407E0000, 0xD0
+
+/* Read the FSTATR Reg, is FRDY bit 1 yet (probably not) */
+ mem32 0x407FE080, 1
+
+/* wait for 1sec, more than enough time for the operation! */
+sleep 1000
+
+/* Read the FSTATR Reg, FRDY bit should be 1 by now (register should read 0x00008000) */
+ mem32 0x407FE080, 1
+
+/* FENTRYR = AA01H - return to ROM read mode */
+w2 0x407FE084, 0xAA00
+
+/* Read the security MPU area*/
+mem32 0x00000000,16
+
+/* wait for 100ms */
+sleep 100
+
+/* Erase the device */
+erase
+
+/* Reset the device */
+r
+
+q
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.cproject b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.cproject
new file mode 100644
index 0000000000..ec059529d3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.cproject
@@ -0,0 +1,300 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.project b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.project
new file mode 100644
index 0000000000..891f656435
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.project
@@ -0,0 +1,38 @@
+
+
+	blinky_all_leds
+	
+	
+	
+	
+		
+			org.eclipse.xtext.ui.shared.xtextBuilder
+			
+			
+		
+		
+			com.renesas.cdt.ra.contentgen.raBuilder
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		com.renesas.cdt.ra.contentgen.raNature
+		org.eclipse.xtext.ui.shared.xtextNature
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
new file mode 100644
index 0000000000..450a47cf61
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=9.2.1.20191025
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.content.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.ra.content.prefs
similarity index 100%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.content.prefs
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.ra.content.prefs
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
new file mode 100644
index 0000000000..18ff7aecb7
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
@@ -0,0 +1,16 @@
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/all=984407218,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2182658037,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3831616655,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2924246150,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3047267965,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1395162982,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1383382254,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3528041316,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3679261956,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|498646134,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2506583203,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|4111916304,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|4163895945,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2220305532,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|12129667,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|490858859,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4214990036,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|979987894,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|373608954,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2262931981,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2083176475,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries=
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/all=1308072519,ra/board/ra6m3_ek/board_ethernet_phy.h|3753099063,ra/board/ra6m3_ek/board_leds.c|270190773,ra/board/ra6m3_ek/board_init.c|2171210938,ra/board/ra6m3_ek/board_init.h|667942982,ra/board/ra6m3_ek/board.h|547978938,ra/board/ra6m3_ek/board_leds.h
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/all=3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/all=1084997943,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|507755270,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h|1951380226,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/libraries=
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/all=2227745288,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3823484035,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|128613077,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3066705100,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|3883901804,ra/fsp/inc/fsp_common_api.h|3928045063,ra/fsp/inc/api/r_ioport_api.h|149297868,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|3442079740,ra/fsp/src/bsp/mcu/all/bsp_delay.h|620302993,ra/fsp/src/bsp/mcu/all/bsp_io.c|908333377,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2978769036,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1233273129,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3381132971,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2781595274,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|38790958,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|313932228,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1560597783,ra/fsp/inc/fsp_version.h|4241733658,ra/fsp/src/bsp/mcu/all/bsp_irq.h|416740758,ra/fsp/src/bsp/mcu/all/bsp_io.h|2288673548,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3844564780,ra/fsp/src/bsp/mcu/all/bsp_common.c|309120448,ra/fsp/inc/fsp_features.h|839014393,ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd|2707126025,ra/fsp/inc/instances/r_ioport.h|3662298291,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3680385993,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|986415386,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1876286481,ra/fsp/src/bsp/mcu/all/bsp_common.h|3753872052,ra/fsp/inc/api/bsp_api.h
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/all=1807239902,ra/fsp/src/r_ioport/r_ioport.c|2707126025,ra/fsp/inc/instances/r_ioport.h|3928045063,ra/fsp/inc/api/r_ioport_api.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/libraries=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/all=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/libraries=
+eclipse.preferences.version=1
diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/language.settings.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/language.settings.xml
similarity index 90%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/language.settings.xml
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/language.settings.xml
index 7c8c5a3701..e84527b482 100644
--- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/language.settings.xml
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/language.settings.xml
@@ -1,22 +1,22 @@
 
 
-	
+	
 		
 			
 			
 			
-			
+			
 				
 				
 			
 		
 	
-	
+	
 		
 			
 			
 			
-			
+			
 				
 				
 			
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/org.eclipse.cdt.core.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000..253f23cad3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,172 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.core.formatter.align_composite_type_declarators=false
+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
+org.eclipse.cdt.core.formatter.alignment_for_assignment=16
+org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=82
+org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16
+org.eclipse.cdt.core.formatter.alignment_for_compact_if=0
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=82
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18
+org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0
+org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
+org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
+org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
+org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=82
+org.eclipse.cdt.core.formatter.alignment_for_member_access=0
+org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16
+org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16
+org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16
+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
+org.eclipse.cdt.core.formatter.comment.line_up_line_comment_in_blocks_on_first_column=false
+org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1
+org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true
+org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=true
+org.eclipse.cdt.core.formatter.compact_else_if=true
+org.eclipse.cdt.core.formatter.continuation_indentation=2
+org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2
+org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false
+org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=false
+org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false
+org.eclipse.cdt.core.formatter.indent_empty_lines=false
+org.eclipse.cdt.core.formatter.indent_preprocessor_directives=false
+org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true
+org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true
+org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true
+org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=true
+org.eclipse.cdt.core.formatter.indentation.size=4
+org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_after_template_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_at_end_of_file_if_missing=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_catch_in_try_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_closing_brace_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_colon_in_constructor_initializer_list=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_else_in_if_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_identifier_in_function_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_while_in_do_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block=insert
+org.eclipse.cdt.core.formatter.insert_space_after_assignment_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_after_binary_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_brace_in_block=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_paren_in_cast=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_base_clause=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_labeled_statement=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_expression_list=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_throws=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_bracket=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_cast=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_catch=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_parenthesized_expression=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_switch=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_while=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_postfix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_prefix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_question_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_after_semicolon_in_for=insert
+org.eclipse.cdt.core.formatter.insert_space_after_unary_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_assignment_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_before_binary_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_brace_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_bracket=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_cast=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_catch=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_for=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_if=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_switch=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_while=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_colon_in_base_clause=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_colon_in_case=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_colon_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_before_colon_in_default=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_colon_in_labeled_statement=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_declarator_list=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_enum_declarations=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_expression_list=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_throws=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_invocation_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_cast=insert
+org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_method_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_declarator_list=insert
+org.eclipse.cdt.core.formatter.insert_space_before_identifier_in_declarator_list=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_namespace_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_switch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_type_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_bracket=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_catch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_exception_specification=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_for=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_if=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_switch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_while=insert
+org.eclipse.cdt.core.formatter.insert_space_before_postfix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_prefix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_before_semicolon=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_semicolon_in_for=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_unary_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_expression=do not insert
+org.eclipse.cdt.core.formatter.join_wrapped_lines=true
+org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.lineSplit=120
+org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1
+org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true
+org.eclipse.cdt.core.formatter.tabulation.char=space
+org.eclipse.cdt.core.formatter.tabulation.size=4
+org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/R7FA6M3AH3CFC.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/R7FA6M3AH3CFC.pincfg
similarity index 100%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/R7FA6M3AH3CFC.pincfg
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/R7FA6M3AH3CFC.pincfg
diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/RA6M3-EK.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/RA6M3-EK.pincfg
similarity index 99%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/RA6M3-EK.pincfg
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/RA6M3-EK.pincfg
index a602f204f5..c2b5eee06e 100644
--- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/RA6M3-EK.pincfg
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/RA6M3-EK.pincfg
@@ -549,14 +549,12 @@
     
   
   
-  
-    
-  
+  
   
     
   
   
-  
+  
   
   
     
@@ -852,9 +850,6 @@
   
   
   
-  
-    
-  
-  
+  
   
 
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/configuration.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/configuration.xml
new file mode 100644
index 0000000000..374ce40f08
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/configuration.xml
@@ -0,0 +1,174 @@
+
+
+  
+    
+  
+    
+      
+      
+      
+      
+      
+      
+    
+    
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+      Board support package for R7FA6M3AH3CFC
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3 - FSP Data
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Simple application that blinks an LED. No RTOS included.
+      Renesas.RA_baremetal_blinky.1.0.0.pack
+    
+    
+      Arm CMSIS Version 5 - Core (M)
+      Arm.CMSIS5.5.6.0.pack
+    
+    
+      RA6M3-EK Board Support Files
+      Renesas.RA_board_ra6m3_ek.1.0.0.pack
+    
+    
+      Board Support Package Common Files
+      Renesas.RA.1.0.0.pack
+    
+    
+      I/O Port
+      Renesas.RA.1.0.0.pack
+    
+  
+  
+  
+  
+    
+      
+    
+    
+      
+    
+  
+
+    
+  
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/script/ra6m3.ld b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/script/ra6m3.ld
new file mode 100644
index 0000000000..ac251c435c
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/script/ra6m3.ld
@@ -0,0 +1,324 @@
+/*
+                  Linker File for RA6M3 MCU
+*/
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)         : ORIGIN = 0x00010400, LENGTH = 0x00F0000  /* 960K */
+  RAM (rwx)          : ORIGIN = 0x1FFE0000, LENGTH = 0x00A0000  /* 640K */
+  DATA_FLASH (rx)    : ORIGIN = 0x40100000, LENGTH = 0x0010000  /*  64K */
+  QSPI_FLASH (rx)    : ORIGIN = 0x60000000, LENGTH = 0x4000000  /*  64M, Change in QSPI section below also */
+  SDRAM (rwx)        : ORIGIN = 0x90000000, LENGTH = 0x2000000  /*  32M */
+  ID_CODE (rx)       : ORIGIN = 0x0100A150, LENGTH = 0x10    /* 16 bytes */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+        __end__ = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* Data flash. */
+    .data_flash :
+    {
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+    } > DATA_FLASH
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    .id_code (NOLOAD):
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+}
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/src/hal_entry.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/src/hal_entry.c
new file mode 100644
index 0000000000..c0660832f1
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_all_leds/src/hal_entry.c
@@ -0,0 +1,117 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software is supplied by Renesas Electronics America Inc. and may only be used with products of Renesas
+ * Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  This software is protected under
+ * all applicable laws, including copyright laws. Renesas reserves the right to change or discontinue this software.
+ * THE SOFTWARE IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST
+ * EXTENT PERMISSIBLE UNDER APPLICABLE LAW,DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE.
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#include "hal_data.h"
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+extern bsp_leds_t g_bsp_leds;
+
+/*******************************************************************************************************************//**
+ * @brief  Blinky example application
+ *
+ * Blinks all leds at a rate of 1 second using the software delay function provided by the BSP.
+ *
+ **********************************************************************************************************************/
+void hal_entry (void)
+{
+    /* Define the units to be used with the software delay function */
+    const bsp_delay_units_t bsp_delay_units = BSP_DELAY_UNITS_MILLISECONDS;
+
+    /* Set the blink frequency (must be <= bsp_delay_units */
+    const uint32_t freq_in_hz = 2;
+
+    /* Calculate the delay in terms of bsp_delay_units */
+    const uint32_t delay = bsp_delay_units / freq_in_hz;
+
+    /* LED type structure */
+    bsp_leds_t leds = g_bsp_leds;
+
+    /* If this board has no LEDs then trap here */
+    if (0 == leds.led_count)
+    {
+        while (1)
+        {
+            ;                          // There are no LEDs on this board
+        }
+    }
+
+    /* Holds level to set for pins */
+    bsp_io_level_t pin_level = BSP_IO_LEVEL_LOW;
+
+    while (1)
+    {
+        /* Enable access to the PFS registers. If using r_ioport module then register protection is automatically
+         * handled. This code uses BSP IO functions to show how it is used.
+         */
+        R_BSP_PinAccessEnable();
+
+        /* Update all board LEDs */
+        for (uint32_t i = 0; i < leds.led_count; i++)
+        {
+            /* Get pin to toggle */
+            uint32_t pin = leds.p_leds[i];
+
+            /* Write to this pin */
+            R_BSP_PinWrite((bsp_io_port_pin_t) pin, pin_level);
+        }
+
+        /* Protect PFS registers */
+        R_BSP_PinAccessDisable();
+
+        /* Toggle level for next write */
+        if (BSP_IO_LEVEL_LOW == pin_level)
+        {
+            pin_level = BSP_IO_LEVEL_HIGH;
+        }
+        else
+        {
+            pin_level = BSP_IO_LEVEL_LOW;
+        }
+
+        /* Delay */
+        R_BSP_SoftwareDelay(delay, bsp_delay_units);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+        /* Enable reading from data flash. */
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+         * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+    }
+
+    if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment and system clocks are setup. */
+
+        /* Configure pins. */
+        R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+    }
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.cproject b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.cproject
new file mode 100644
index 0000000000..df1f1e76eb
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.cproject
@@ -0,0 +1,300 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.project b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.project
new file mode 100644
index 0000000000..f2fa8816cf
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.project
@@ -0,0 +1,38 @@
+
+
+	blinky_blue_led
+	
+	
+	
+	
+		
+			org.eclipse.xtext.ui.shared.xtextBuilder
+			
+			
+		
+		
+			com.renesas.cdt.ra.contentgen.raBuilder
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		com.renesas.cdt.ra.contentgen.raNature
+		org.eclipse.xtext.ui.shared.xtextNature
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
new file mode 100644
index 0000000000..450a47cf61
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=9.2.1.20191025
diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.content.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.ra.content.prefs
similarity index 100%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.content.prefs
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.ra.content.prefs
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
new file mode 100644
index 0000000000..1e87114048
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
@@ -0,0 +1,16 @@
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/all=12129667,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1395162982,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|498646134,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|979987894,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2506583203,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2083176475,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3679261956,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|4214990036,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|490858859,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4163895945,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|4111916304,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2924246150,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|2182658037,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3831616655,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|3047267965,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1383382254,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2262931981,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3528041316,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|373608954,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2220305532,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|984407218,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries=
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/all=1308072519,ra/board/ra6m3_ek/board_ethernet_phy.h|3753099063,ra/board/ra6m3_ek/board_leds.c|547978938,ra/board/ra6m3_ek/board_leds.h|667942982,ra/board/ra6m3_ek/board.h|270190773,ra/board/ra6m3_ek/board_init.c|2171210938,ra/board/ra6m3_ek/board_init.h
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/all=3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/all=507755270,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h|1084997943,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|1951380226,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/libraries=
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/all=908333377,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|313932228,ra/fsp/src/bsp/mcu/all/bsp_irq.c|149297868,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|620302993,ra/fsp/src/bsp/mcu/all/bsp_io.c|3066705100,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1876286481,ra/fsp/src/bsp/mcu/all/bsp_common.h|3928045063,ra/fsp/inc/api/r_ioport_api.h|1233273129,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1560597783,ra/fsp/inc/fsp_version.h|2227745288,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3844564780,ra/fsp/src/bsp/mcu/all/bsp_common.c|3883901804,ra/fsp/inc/fsp_common_api.h|128613077,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|38790958,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2978769036,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3753872052,ra/fsp/inc/api/bsp_api.h|3823484035,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2288673548,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3680385993,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|309120448,ra/fsp/inc/fsp_features.h|416740758,ra/fsp/src/bsp/mcu/all/bsp_io.h|3442079740,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2781595274,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|986415386,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3662298291,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|839014393,ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd|3381132971,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4241733658,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2707126025,ra/fsp/inc/instances/r_ioport.h
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/all=3928045063,ra/fsp/inc/api/r_ioport_api.h|1807239902,ra/fsp/src/r_ioport/r_ioport.c|2707126025,ra/fsp/inc/instances/r_ioport.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/libraries=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/all=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/libraries=
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/language.settings.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/language.settings.xml
new file mode 100644
index 0000000000..4afa0f3f93
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/org.eclipse.cdt.core.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000..253f23cad3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,172 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.core.formatter.align_composite_type_declarators=false
+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
+org.eclipse.cdt.core.formatter.alignment_for_assignment=16
+org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=82
+org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16
+org.eclipse.cdt.core.formatter.alignment_for_compact_if=0
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=82
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18
+org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0
+org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
+org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
+org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
+org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=82
+org.eclipse.cdt.core.formatter.alignment_for_member_access=0
+org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16
+org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16
+org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16
+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
+org.eclipse.cdt.core.formatter.comment.line_up_line_comment_in_blocks_on_first_column=false
+org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1
+org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true
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diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/R7FA6M3AH3CFC.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/R7FA6M3AH3CFC.pincfg
similarity index 100%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/R7FA6M3AH3CFC.pincfg
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/R7FA6M3AH3CFC.pincfg
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/RA6M3-EK.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/RA6M3-EK.pincfg
new file mode 100644
index 0000000000..c2b5eee06e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/RA6M3-EK.pincfg
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+  
+    
+  
+  
+  
+  
+  
+  
+
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/blinky_blue_led Debug.launch b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/blinky_blue_led Debug.launch
new file mode 100644
index 0000000000..568fd2f76f
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/blinky_blue_led Debug.launch	
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/configuration.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/configuration.xml
new file mode 100644
index 0000000000..374ce40f08
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/configuration.xml
@@ -0,0 +1,174 @@
+
+
+  
+    
+  
+    
+      
+      
+      
+      
+      
+      
+    
+    
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+      Board support package for R7FA6M3AH3CFC
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3 - FSP Data
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Simple application that blinks an LED. No RTOS included.
+      Renesas.RA_baremetal_blinky.1.0.0.pack
+    
+    
+      Arm CMSIS Version 5 - Core (M)
+      Arm.CMSIS5.5.6.0.pack
+    
+    
+      RA6M3-EK Board Support Files
+      Renesas.RA_board_ra6m3_ek.1.0.0.pack
+    
+    
+      Board Support Package Common Files
+      Renesas.RA.1.0.0.pack
+    
+    
+      I/O Port
+      Renesas.RA.1.0.0.pack
+    
+  
+  
+  
+  
+    
+      
+    
+    
+      
+    
+  
+
+    
+  
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/script/ra6m3.ld b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/script/ra6m3.ld
new file mode 100644
index 0000000000..ac251c435c
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/script/ra6m3.ld
@@ -0,0 +1,324 @@
+/*
+                  Linker File for RA6M3 MCU
+*/
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)         : ORIGIN = 0x00010400, LENGTH = 0x00F0000  /* 960K */
+  RAM (rwx)          : ORIGIN = 0x1FFE0000, LENGTH = 0x00A0000  /* 640K */
+  DATA_FLASH (rx)    : ORIGIN = 0x40100000, LENGTH = 0x0010000  /*  64K */
+  QSPI_FLASH (rx)    : ORIGIN = 0x60000000, LENGTH = 0x4000000  /*  64M, Change in QSPI section below also */
+  SDRAM (rwx)        : ORIGIN = 0x90000000, LENGTH = 0x2000000  /*  32M */
+  ID_CODE (rx)       : ORIGIN = 0x0100A150, LENGTH = 0x10    /* 16 bytes */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+        __end__ = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* Data flash. */
+    .data_flash :
+    {
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+    } > DATA_FLASH
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    .id_code (NOLOAD):
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+}
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/src/hal_entry.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/src/hal_entry.c
new file mode 100644
index 0000000000..c76d37b2fe
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_blue_led/src/hal_entry.c
@@ -0,0 +1,117 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software is supplied by Renesas Electronics America Inc. and may only be used with products of Renesas
+ * Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  This software is protected under
+ * all applicable laws, including copyright laws. Renesas reserves the right to change or discontinue this software.
+ * THE SOFTWARE IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST
+ * EXTENT PERMISSIBLE UNDER APPLICABLE LAW,DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE.
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#include "hal_data.h"
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+extern bsp_leds_t g_bsp_leds;
+
+/*******************************************************************************************************************//**
+ * @brief  Blinky example application
+ *
+ * Blinks all leds at a rate of 1 second using the software delay function provided by the BSP.
+ *
+ **********************************************************************************************************************/
+void hal_entry (void)
+{
+    /* Define the units to be used with the software delay function */
+    const bsp_delay_units_t bsp_delay_units = BSP_DELAY_UNITS_MILLISECONDS;
+
+    /* Set the blink frequency (must be <= bsp_delay_units */
+    const uint32_t freq_in_hz = 2;
+
+    /* Calculate the delay in terms of bsp_delay_units */
+    const uint32_t delay = bsp_delay_units / freq_in_hz;
+
+    /* LED type structure */
+    bsp_leds_t leds = g_bsp_leds;
+
+    /* If this board has no LEDs then trap here */
+    if (0 == leds.led_count)
+    {
+        while (1)
+        {
+            ;                          // There are no LEDs on this board
+        }
+    }
+
+    /* Holds level to set for pins */
+    bsp_io_level_t pin_level = BSP_IO_LEVEL_LOW;
+
+    while (1)
+    {
+        /* Enable access to the PFS registers. If using r_ioport module then register protection is automatically
+         * handled. This code uses BSP IO functions to show how it is used.
+         */
+        R_BSP_PinAccessEnable();
+
+        /* Update all board LEDs */
+        for (uint32_t i = 0; i < 1 /*leds.led_count*/; i++)
+        {
+            /* Get pin to toggle */
+            uint32_t pin = leds.p_leds[i];
+
+            /* Write to this pin */
+            R_BSP_PinWrite((bsp_io_port_pin_t) pin, pin_level);
+        }
+
+        /* Protect PFS registers */
+        R_BSP_PinAccessDisable();
+
+        /* Toggle level for next write */
+        if (BSP_IO_LEVEL_LOW == pin_level)
+        {
+            pin_level = BSP_IO_LEVEL_HIGH;
+        }
+        else
+        {
+            pin_level = BSP_IO_LEVEL_LOW;
+        }
+
+        /* Delay */
+        R_BSP_SoftwareDelay(delay, bsp_delay_units);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+        /* Enable reading from data flash. */
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+         * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+    }
+
+    if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment and system clocks are setup. */
+
+        /* Configure pins. */
+        R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+    }
+}
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.cproject b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.cproject
similarity index 64%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.cproject
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.cproject
index c8b99a76a3..fee89fe15e 100644
--- a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.cproject
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.cproject
@@ -1,8 +1,8 @@
 
 
 	
-		
-			
+		
+			
 				
 				
 					
@@ -14,118 +14,121 @@
 				
 			
 			
-				
-					
-						
-							
 			
 		
-		
-			
+		
+			
 				
 				
 					
@@ -151,118 +154,121 @@
 				
 			
 			
-				
-					
-						
-							
 	
 	
-		
+		
 	
 	
 		
-		
+		
 			
 		
-		
+		
 			
 		
 	
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.project b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.project
new file mode 100644
index 0000000000..6588e61c5b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.project
@@ -0,0 +1,38 @@
+
+
+	blinky_red_led
+	
+	
+	
+	
+		
+			org.eclipse.xtext.ui.shared.xtextBuilder
+			
+			
+		
+		
+			com.renesas.cdt.ra.contentgen.raBuilder
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		com.renesas.cdt.ra.contentgen.raNature
+		org.eclipse.xtext.ui.shared.xtextNature
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
new file mode 100644
index 0000000000..450a47cf61
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=9.2.1.20191025
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.content.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.content.prefs
new file mode 100644
index 0000000000..f77288b8f3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.content.prefs
@@ -0,0 +1,2 @@
+com.renesas.cdt.ra.content.defaultlinkerscript=script/ra6m3.ld
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
new file mode 100644
index 0000000000..7bfcca4b68
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
@@ -0,0 +1,16 @@
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+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries=
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+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/all=3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/all=1084997943,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|1951380226,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|507755270,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/libraries=
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+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/all=1807239902,ra/fsp/src/r_ioport/r_ioport.c|2707126025,ra/fsp/inc/instances/r_ioport.h|3928045063,ra/fsp/inc/api/r_ioport_api.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/libraries=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/all=
+Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#1.0.0/libraries=
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/language.settings.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/language.settings.xml
new file mode 100644
index 0000000000..16c67a9c86
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
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diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/org.eclipse.cdt.core.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000..253f23cad3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,172 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.core.formatter.align_composite_type_declarators=false
+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
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+org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_expression=do not insert
+org.eclipse.cdt.core.formatter.join_wrapped_lines=true
+org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.lineSplit=120
+org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1
+org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true
+org.eclipse.cdt.core.formatter.tabulation.char=space
+org.eclipse.cdt.core.formatter.tabulation.size=4
+org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/R7FA6M3AH3CFC.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/R7FA6M3AH3CFC.pincfg
new file mode 100644
index 0000000000..5d97f4831e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/R7FA6M3AH3CFC.pincfg
@@ -0,0 +1,36 @@
+
+
+  
+  
+    
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/RA6M3-EK.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/RA6M3-EK.pincfg
new file mode 100644
index 0000000000..c2b5eee06e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/RA6M3-EK.pincfg
@@ -0,0 +1,855 @@
+
+  
+  
+    
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
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+  
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+  
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+  
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+  
+  
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+  
+    
+  
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+    
+  
+  
+    
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+  
+  
+  
+  
+  
+  
+    
+  
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+    
+  
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+  
+  
+  
+    
+  
+  
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+  
+  
+    
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
+  
+  
+  
+    
+  
+  
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+    
+  
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+  
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+    
+  
+  
+    
+  
+  
+  
+  
+    
+  
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+    
+  
+  
+  
+  
+    
+  
+  
+  
+    
+  
+  
+  
+  
+  
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
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+  
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+    
+  
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+  
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
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+  
+  
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+  
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+  
+    
+  
+  
+    
+  
+  
+  
+  
+  
+  
+
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/blinky_red_led Debug.launch b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/blinky_red_led Debug.launch
new file mode 100644
index 0000000000..bf682db560
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/blinky_red_led Debug.launch	
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/configuration.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/configuration.xml
new file mode 100644
index 0000000000..374ce40f08
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/configuration.xml
@@ -0,0 +1,174 @@
+
+
+  
+    
+  
+    
+      
+      
+      
+      
+      
+      
+    
+    
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+      Board support package for R7FA6M3AH3CFC
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3 - FSP Data
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Simple application that blinks an LED. No RTOS included.
+      Renesas.RA_baremetal_blinky.1.0.0.pack
+    
+    
+      Arm CMSIS Version 5 - Core (M)
+      Arm.CMSIS5.5.6.0.pack
+    
+    
+      RA6M3-EK Board Support Files
+      Renesas.RA_board_ra6m3_ek.1.0.0.pack
+    
+    
+      Board Support Package Common Files
+      Renesas.RA.1.0.0.pack
+    
+    
+      I/O Port
+      Renesas.RA.1.0.0.pack
+    
+  
+  
+  
+  
+    
+      
+    
+    
+      
+    
+  
+
+    
+  
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/script/ra6m3.ld b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/script/ra6m3.ld
new file mode 100644
index 0000000000..ac251c435c
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/script/ra6m3.ld
@@ -0,0 +1,324 @@
+/*
+                  Linker File for RA6M3 MCU
+*/
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)         : ORIGIN = 0x00010400, LENGTH = 0x00F0000  /* 960K */
+  RAM (rwx)          : ORIGIN = 0x1FFE0000, LENGTH = 0x00A0000  /* 640K */
+  DATA_FLASH (rx)    : ORIGIN = 0x40100000, LENGTH = 0x0010000  /*  64K */
+  QSPI_FLASH (rx)    : ORIGIN = 0x60000000, LENGTH = 0x4000000  /*  64M, Change in QSPI section below also */
+  SDRAM (rwx)        : ORIGIN = 0x90000000, LENGTH = 0x2000000  /*  32M */
+  ID_CODE (rx)       : ORIGIN = 0x0100A150, LENGTH = 0x10    /* 16 bytes */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+        __end__ = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* Data flash. */
+    .data_flash :
+    {
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+    } > DATA_FLASH
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    .id_code (NOLOAD):
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+}
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/src/hal_entry.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/src/hal_entry.c
new file mode 100644
index 0000000000..768b62b9ee
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/Sample_Applications/blinky_red_led/src/hal_entry.c
@@ -0,0 +1,117 @@
+/***********************************************************************************************************************
+ * Copyright [2020] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
+ *
+ * This software is supplied by Renesas Electronics America Inc. and may only be used with products of Renesas
+ * Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  This software is protected under
+ * all applicable laws, including copyright laws. Renesas reserves the right to change or discontinue this software.
+ * THE SOFTWARE IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST
+ * EXTENT PERMISSIBLE UNDER APPLICABLE LAW,DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE.
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE
+ * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
+ * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
+ * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
+ **********************************************************************************************************************/
+
+#include "hal_data.h"
+
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+
+extern bsp_leds_t g_bsp_leds;
+
+/*******************************************************************************************************************//**
+ * @brief  Blinky example application
+ *
+ * Blinks all leds at a rate of 1 second using the software delay function provided by the BSP.
+ *
+ **********************************************************************************************************************/
+void hal_entry (void)
+{
+    /* Define the units to be used with the software delay function */
+    const bsp_delay_units_t bsp_delay_units = BSP_DELAY_UNITS_MILLISECONDS;
+
+    /* Set the blink frequency (must be <= bsp_delay_units */
+    const uint32_t freq_in_hz = 2;
+
+    /* Calculate the delay in terms of bsp_delay_units */
+    const uint32_t delay = bsp_delay_units / freq_in_hz;
+
+    /* LED type structure */
+    bsp_leds_t leds = g_bsp_leds;
+
+    /* If this board has no LEDs then trap here */
+    if (0 == leds.led_count)
+    {
+        while (1)
+        {
+            ;                          // There are no LEDs on this board
+        }
+    }
+
+    /* Holds level to set for pins */
+    bsp_io_level_t pin_level = BSP_IO_LEVEL_LOW;
+
+    while (1)
+    {
+        /* Enable access to the PFS registers. If using r_ioport module then register protection is automatically
+         * handled. This code uses BSP IO functions to show how it is used.
+         */
+        R_BSP_PinAccessEnable();
+
+        /* Update all board LEDs */
+        for (uint32_t i = 2; i <= leds.led_count; i++)
+        {
+            /* Get pin to toggle */
+            uint32_t pin = leds.p_leds[i];
+
+            /* Write to this pin */
+            R_BSP_PinWrite((bsp_io_port_pin_t) pin, pin_level);
+        }
+
+        /* Protect PFS registers */
+        R_BSP_PinAccessDisable();
+
+        /* Toggle level for next write */
+        if (BSP_IO_LEVEL_LOW == pin_level)
+        {
+            pin_level = BSP_IO_LEVEL_HIGH;
+        }
+        else
+        {
+            pin_level = BSP_IO_LEVEL_LOW;
+        }
+
+        /* Delay */
+        R_BSP_SoftwareDelay(delay, bsp_delay_units);
+    }
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+        /* Enable reading from data flash. */
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+         * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+    }
+
+    if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment and system clocks are setup. */
+
+        /* Configure pins. */
+        R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+    }
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.cproject b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.cproject
new file mode 100644
index 0000000000..9c428bbd06
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.cproject
@@ -0,0 +1,354 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.project b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.project
new file mode 100644
index 0000000000..23bb885021
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.project
@@ -0,0 +1,38 @@
+
+
+	Secureboot_EK_RA6M3
+	
+	
+	
+	
+		
+			org.eclipse.xtext.ui.shared.xtextBuilder
+			
+			
+		
+		
+			com.renesas.cdt.ra.contentgen.raBuilder
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		com.renesas.cdt.ra.contentgen.raNature
+		org.eclipse.xtext.ui.shared.xtextNature
+	
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/CoverageSetting.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/CoverageSetting.xml
new file mode 100644
index 0000000000..9554acb752
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/CoverageSetting.xml
@@ -0,0 +1,7 @@
+
+
+    1.0
+    
+        
+    
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/DebugVirtualConsoleSetting.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/DebugVirtualConsoleSetting.xml
new file mode 100644
index 0000000000..098c55d872
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/DebugVirtualConsoleSetting.xml
@@ -0,0 +1,12 @@
+
+
+
+        true
+        
+        false
+        
+        0
+        true
+        false
+    
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
new file mode 100644
index 0000000000..450a47cf61
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=9.2.1.20191025
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.content.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.content.prefs
new file mode 100644
index 0000000000..f77288b8f3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.content.prefs
@@ -0,0 +1,2 @@
+com.renesas.cdt.ra.content.defaultlinkerscript=script/ra6m3.ld
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
new file mode 100644
index 0000000000..14eff0f9f6
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
@@ -0,0 +1,24 @@
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/all=3831616655,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|979987894,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|12129667,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|3679261956,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1383382254,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|4163895945,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|490858859,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2924246150,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3047267965,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2262931981,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3528041316,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2220305532,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|2506583203,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|2083176475,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|373608954,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1395162982,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|984407218,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4214990036,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|4111916304,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|498646134,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2182658037,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries=
+Arm\#\#PSA\#\#Crypto\#\#mbedCrypto\#\#\#\#3.1.0+renesas.1/all=16572071,ra/arm/mbed-crypto/include/psa/crypto_entropy_driver.h|3730686416,ra/arm/mbed-crypto/include/mbedtls/timing.h|3601193190,ra/arm/mbed-crypto/library/ccm.c|1436364607,ra/arm/mbed-crypto/include/mbedtls/sha256.h|720190709,ra/arm/mbed-crypto/library/pkwrite.c|3751578559,ra/arm/mbed-crypto/library/rsa_internal.c|2012312432,ra/arm/mbed-crypto/include/mbedtls/bignum.h|3741301434,ra/arm/mbed-crypto/library/psa_crypto_slot_management.h|3275364291,ra/arm/mbed-crypto/include/psa/crypto_se_driver.h|627770456,ra/arm/mbed-crypto/include/mbedtls/ctr_drbg.h|4154857905,ra/arm/mbed-crypto/include/mbedtls/aes.h|325580153,ra/arm/mbed-crypto/include/mbedtls/memory_buffer_alloc.h|2766614274,ra/arm/mbed-crypto/include/mbedtls/psa_util.h|4061030449,ra/arm/mbed-crypto/include/mbedtls/rsa.h|3300379921,ra/arm/mbed-crypto/library/md4.c|3685052255,ra/arm/mbed-crypto/library/timing.c|73040575,ra/arm/mbed-crypto/include/mbedtls/base64.h|2123046382,ra/arm/mbed-crypto/library/hmac_drbg.c|4056712330,ra/arm/mbed-crypto/library/ecp.c|1329775443,ra/arm/mbed-crypto/library/CMakeLists.txt|1884876105,ra/arm/mbed-crypto/include/psa/crypto_types.h|2230179464,ra/arm/mbed-crypto/library/padlock.c|3128628304,ra/arm/mbed-crypto/library/aesni.c|362655468,ra/arm/mbed-crypto/library/psa_crypto_slot_management.c|1248814450,ra/arm/mbed-crypto/library/bignum.c|36725325,ra/arm/mbed-crypto/library/chachapoly.c|1274860295,ra/arm/mbed-crypto/include/mbedtls/camellia.h|724935132,ra/arm/mbed-crypto/library/error.c|1343376783,ra/arm/mbed-crypto/library/pkcs5.c|1447684538,ra/arm/mbed-crypto/include/mbedtls/xtea.h|2710643250,ra/arm/mbed-crypto/include/mbedtls/md5.h|3857289096,ra/arm/mbed-crypto/library/chacha20.c|2168552123,ra/arm/mbed-crypto/library/arc4.c|3987850215,ra/arm/mbed-crypto/include/mbedtls/ecp_internal.h|1947790776,ra/arm/mbed-crypto/library/platform.c|684772620,ra/arm/mbed-crypto/library/blowfish.c|3232468017,ra/arm/mbed-crypto/library/asn1write.c|3156723606,ra/arm/mbed-crypto/include/mbedtls/bn_mul.h|2524709294,ra/arm/mbed-crypto/library/nist_kw.c|3642199573,ra/arm/mbed-crypto/include/mbedtls/pkcs5.h|1867161518,ra/arm/mbed-crypto/library/camellia.c|582495309,ra/arm/mbed-crypto/include/mbedtls/des.h|3960870849,ra/arm/mbed-crypto/library/des.c|3750217592,ra/arm/mbed-crypto/include/mbedtls/oid.h|3280803923,ra/arm/mbed-crypto/library/poly1305.c|2242094330,ra/arm/mbed-crypto/include/mbedtls/chacha20.h|600851858,ra/arm/mbed-crypto/include/mbedtls/platform_time.h|645044877,ra/arm/mbed-crypto/library/md5.c|1259837210,ra/arm/mbed-crypto/library/entropy.c|411160786,ra/arm/mbed-crypto/library/sha256.c|2486967980,ra/arm/mbed-crypto/include/mbedtls/havege.h|3453818506,ra/arm/mbed-crypto/include/psa/crypto_extra.h|632005311,ra/arm/mbed-crypto/include/mbedtls/md4.h|2942320029,ra/arm/mbed-crypto/include/mbedtls/cipher_internal.h|2315972906,ra/arm/mbed-crypto/include/mbedtls/pk_internal.h|4185175463,ra/arm/mbed-crypto/library/psa_crypto_invasive.h|399213377,ra/arm/mbed-crypto/include/mbedtls/chachapoly.h|3226488737,ra/arm/mbed-crypto/include/mbedtls/compat-1.3.h|1285103021,ra/arm/mbed-crypto/include/mbedtls/arc4.h|4024414388,ra/arm/mbed-crypto/include/mbedtls/sha512.h|3074776150,ra/arm/mbed-crypto/include/mbedtls/pem.h|3144623575,ra/arm/mbed-crypto/include/mbedtls/threading.h|947383659,ra/arm/mbed-crypto/include/mbedtls/poly1305.h|3411153162,ra/arm/mbed-crypto/library/ripemd160.c|3691958033,ra/arm/mbed-crypto/library/asn1parse.c|1919884190,ra/arm/mbed-crypto/library/psa_its_file.c|2133375777,ra/arm/mbed-crypto/include/mbedtls/aesni.h|878683045,ra/arm/mbed-crypto/include/mbedtls/error.h|2582543926,ra/arm/mbed-crypto/include/mbedtls/nist_kw.h|1607549868,ra/arm/mbed-crypto/library/psa_crypto_se.h|3537226388,ra/arm/mbed-crypto/library/pkcs12.c|3930657195,ra/arm/mbed-crypto/library/havege.c|3763804350,ra/arm/mbed-crypto/include/mbedtls/ccm.h|3335173973,ra/arm/mbed-crypto/library/cipher_wrap.c|3067915675,ra/arm/mbed-crypto/library/psa_crypto_se.c|3758660953,ra/arm/mbed-crypto/library/psa_crypto_service_integration.h|1895555674,ra/arm/mbed-crypto/include/mbedtls/check_config.h|655002952,ra/arm/mbed-crypto/library/psa_crypto.c|550444300,ra/arm/mbed-crypto/library/pk.c|2641370884,ra/arm/mbed-crypto/include/mbedtls/asn1.h|4053819529,ra/arm/mbed-crypto/library/cmac.c|2080346530,ra/arm/mbed-crypto/library/rsa.c|1859812040,ra/arm/mbed-crypto/include/psa/crypto_compat.h|1387141511,ra/arm/mbed-crypto/include/mbedtls/platform.h|1480609888,ra/arm/mbed-crypto/library/pk_wrap.c|3103380084,ra/arm/mbed-crypto/include/psa/crypto_sizes.h|2483408132,ra/arm/mbed-crypto/library/platform_util.c|3227535561,ra/arm/mbed-crypto/include/psa/crypto.h|1317926781,ra/arm/mbed-crypto/include/mbedtls/aria.h|2967938808,ra/arm/mbed-crypto/library/entropy_poll.c|1468614726,ra/arm/mbed-crypto/include/psa/crypto_struct.h|948921409,ra/arm/mbed-crypto/library/md2.c|2470992779,ra/arm/mbed-crypto/library/threading.c|1632401988,ra/arm/mbed-crypto/include/mbedtls/platform_util.h|2183256390,ra/arm/mbed-crypto/include/mbedtls/cipher.h|633436618,ra/arm/mbed-crypto/library/ecdh.c|2557962617,ra/arm/mbed-crypto/include/psa/crypto_driver_common.h|746451078,ra/arm/mbed-crypto/include/mbedtls/padlock.h|1924522657,ra/arm/mbed-crypto/library/ecjpake.c|3746221733,ra/arm/mbed-crypto/library/pkparse.c|2106285641,ra/arm/mbed-crypto/include/mbedtls/ecjpake.h|2633194362,ra/arm/mbed-crypto/include/psa/crypto_platform.h|2586429603,ra/arm/mbed-crypto/library/ctr_drbg.c|2291290750,ra/arm/mbed-crypto/include/mbedtls/md.h|850230075,ra/arm/mbed-crypto/library/.gitignore|2855205189,ra/arm/mbed-crypto/include/mbedtls/gcm.h|176202710,ra/arm/mbed-crypto/include/mbedtls/ripemd160.h|2292481707,ra/arm/mbed-crypto/library/pem.c|1108707896,ra/arm/mbed-crypto/library/version.c|1794065230,ra/arm/mbed-crypto/library/ecdsa.c|3145114589,ra/arm/mbed-crypto/include/psa/crypto_values.h|692841579,ra/arm/mbed-crypto/include/mbedtls/asn1write.h|628047853,ra/arm/mbed-crypto/library/hkdf.c|2552627743,ra/arm/mbed-crypto/include/mbedtls/sha1.h|3268304942,ra/arm/mbed-crypto/library/sha512.c|3558439454,ra/arm/mbed-crypto/include/mbedtls/version.h|1437251914,ra/arm/mbed-crypto/library/psa_crypto_its.h|4028111196,ra/arm/mbed-crypto/library/version_features.c|2311789980,ra/arm/mbed-crypto/library/xtea.c|336211907,ra/arm/mbed-crypto/library/base64.c|374318794,ra/arm/mbed-crypto/library/dhm.c|3570129502,ra/arm/mbed-crypto/include/mbedtls/entropy_poll.h|2097659515,ra/arm/mbed-crypto/library/oid.c|3235021125,ra/arm/mbed-crypto/library/aria.c|2888091008,ra/arm/mbed-crypto/library/ecp_curves.c|2433021678,ra/arm/mbed-crypto/include/mbedtls/ecp.h|1313367344,ra/arm/mbed-crypto/include/mbedtls/hmac_drbg.h|3660219752,ra/arm/mbed-crypto/include/mbedtls/dhm.h|1744927996,ra/arm/mbed-crypto/library/md.c|4155536045,ra/arm/mbed-crypto/include/psa/crypto_accel_driver.h|3615642779,ra/arm/mbed-crypto/include/mbedtls/pk.h|3601247511,ra/arm/mbed-crypto/include/mbedtls/blowfish.h|3115292023,ra/arm/mbed-crypto/include/mbedtls/ecdsa.h|2600411043,ra/arm/mbed-crypto/include/mbedtls/rsa_internal.h|4163595217,ra/arm/mbed-crypto/library/memory_buffer_alloc.c|3799218973,ra/arm/mbed-crypto/include/mbedtls/entropy.h|3435430997,ra/arm/mbed-crypto/library/psa_crypto_storage.h|1531373315,ra/arm/mbed-crypto/library/psa_crypto_core.h|3807226030,ra/arm/mbed-crypto/include/mbedtls/md_internal.h|155320149,ra/arm/mbed-crypto/library/sha1.c|1330428817,ra/arm/mbed-crypto/include/mbedtls/hkdf.h|958304444,ra/arm/mbed-crypto/include/mbedtls/md2.h|3934918793,ra/arm/mbed-crypto/library/psa_crypto_storage.c|1346271390,ra/arm/mbed-crypto/library/aes.c|1641132796,ra/arm/mbed-crypto/library/Makefile|896473772,ra/arm/mbed-crypto/library/cipher.c|3956827355,ra/arm/mbed-crypto/include/mbedtls/ecdh.h|1730617002,ra/arm/mbed-crypto/library/gcm.c|1378409679,ra/arm/mbed-crypto/include/mbedtls/pkcs12.h|309042507,ra/arm/mbed-crypto/include/mbedtls/cmac.h
+Arm\#\#PSA\#\#Crypto\#\#mbedCrypto\#\#\#\#3.1.0+renesas.1/libraries=
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/all=547978938,ra/board/ra6m3_ek/board_leds.h|270190773,ra/board/ra6m3_ek/board_init.c|1308072519,ra/board/ra6m3_ek/board_ethernet_phy.h|667942982,ra/board/ra6m3_ek/board.h|2171210938,ra/board/ra6m3_ek/board_init.h|3753099063,ra/board/ra6m3_ek/board_leds.c
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/all=3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#1.0.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/all=1951380226,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|1084997943,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|507755270,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.0.0/libraries=
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/all=1233273129,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3753872052,ra/fsp/inc/api/bsp_api.h|3490908869,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|416740758,ra/fsp/src/bsp/mcu/all/bsp_io.h|3680385993,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3844564780,ra/fsp/src/bsp/mcu/all/bsp_common.c|3066705100,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1876286481,ra/fsp/src/bsp/mcu/all/bsp_common.h|3662298291,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3823484035,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|986415386,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2227745288,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2707126025,ra/fsp/inc/instances/r_ioport.h|1560597783,ra/fsp/inc/fsp_version.h|128613077,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|908333377,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3928045063,ra/fsp/inc/api/r_ioport_api.h|839014393,ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd|620302993,ra/fsp/src/bsp/mcu/all/bsp_io.c|3442079740,ra/fsp/src/bsp/mcu/all/bsp_delay.h|149297868,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|313932228,ra/fsp/src/bsp/mcu/all/bsp_irq.c|38790958,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2781595274,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2288673548,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2978769036,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3381132971,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4241733658,ra/fsp/src/bsp/mcu/all/bsp_irq.h|309120448,ra/fsp/inc/fsp_features.h|3883901804,ra/fsp/inc/fsp_common_api.h
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#1.0.0/all=632596074,ra/fsp/inc/api/r_flash_api.h|3362782697,ra/fsp/src/r_flash_hp/r_flash_hp.c|3183493539,ra/fsp/inc/instances/r_flash_hp.h|2119913014,ra/fsp/inc/api/r_cgc_api.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/all=3928045063,ra/fsp/inc/api/r_ioport_api.h|2707126025,ra/fsp/inc/instances/r_ioport.h|1807239902,ra/fsp/src/r_ioport/r_ioport.c
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_sce_ra6\#\#\#\#1.0.0/all=1520529653,ra/fsp/src/r_sce/hw_sce_rsa_private.h|1338568192,ra/fsp/src/r_sce/hw_sce_private.h|763531004,ra/fsp/src/r_sce/hw_sce_ecc_private.h|2575449991,ra/fsp/src/r_sce/ra6_sce7/SC32_p26.prc.c|1943992726,ra/fsp/src/r_sce/ra6_sce7/SC32_pc6L_r1.prc.c|568872819,ra/fsp/src/r_sce/ra6_sce7/SC32_p06.prc.c|2471458050,ra/fsp/src/r_sce/ra6_sce7/SC32_p53.prc.c|4162044190,ra/fsp/src/r_sce/ra6_sce7/SC32_pa7L_r1.prc.c|515989659,ra/fsp/src/r_sce/ra6_sce7/SC32_p43.prc.c|4148556532,ra/fsp/src/r_sce/ra6_sce7/SC32_subprc03.prc.c|337740821,ra/fsp/src/r_sce/ra6_sce7/SC32_p23.prc.c|831077281,ra/fsp/src/r_sce/ra6_sce7/SC32_p20.prc.c|332561889,ra/fsp/src/r_sce/ra6_sce7/SC32_pc3L_r1.prc.c|26946258,ra/fsp/src/r_sce/ra6_sce7/SC32_p10.prc.c|3727979111,ra/fsp/src/r_sce/ra6_sce7/SC32_function002.prc.c|2966068618,ra/fsp/src/r_sce/hw_sce_trng_private.h|3360675154,ra/fsp/src/r_sce/hw_sce_aes_private.h|2055774354,ra/fsp/src/r_sce/ra6_sce7/SC32_pe2L.prc.c|3426712171,ra/fsp/src/r_sce/ra6_sce7/SC32_p07.prc.c|113838307,ra/fsp/src/r_sce/ra6_sce7/SC32_p51L_r1.prc.c|3356083510,ra/fsp/src/r_sce/ra6_sce7/SC32_p52.prc.c|3137304709,ra/fsp/src/r_sce/ra6_sce7/SC32_subprc04.prc.c|739052239,ra/fsp/src/r_sce/ra6_sce7/SC32_pe5L_r2.prc.c|3100821254,ra/fsp/src/r_sce/ra6_sce7/SC32_pe6L_r1.prc.c|362172769,ra/fsp/src/r_sce/ra6_sce7/SC32_function001.prc.c|2462790568,ra/fsp/src/r_sce/ra6_sce7/SC32_pc4L_r1.prc.c|2877801762,ra/fsp/src/r_sce/ra6_sce7/SC32_p99.prc.c|3698205358,ra/fsp/src/r_sce/ra6_sce7/SC32_SoftReset.prc.c|2104590117,ra/fsp/src/r_sce/ra6_sce7/SC32_p04.prc.c|3998802145,ra/fsp/src/r_sce/SCE_ProcCommon.h|2957211850,ra/fsp/src/r_sce/ra6_sce7/SC32_pd7L_r1.prc.c|2476653363,ra/fsp/src/r_sce/ra6_sce7/SC32_p41L_r1.prc.c|353395144,ra/fsp/src/r_sce/ra6_sce7/SC32_p24.prc.c|3489338136,ra/fsp/src/r_sce/ra6_sce7/SC32_p66L.prc.c|3926430669,ra/fsp/src/r_sce/ra6_sce7/SC32_p21.prc.c|1857553401,ra/fsp/src/r_sce/ra6_sce7/SC32_p38L_r1.prc.c|4177676332,ra/fsp/src/r_sce/ra6_sce7/SC32_p69L.prc.c|3788931306,ra/fsp/src/r_sce/ra6_sce7/SC32_subprc05.prc.c|3754973998,ra/fsp/src/r_sce/ra6_sce7/SC32_p02_r1.prc.c|527308651,ra/fsp/src/r_sce/common/hw_sce_common.h|880762109,ra/fsp/src/r_sce/ra6_sce7/SC32_pe0L_r1.prc.c|2037572838,ra/fsp/src/r_sce/ra6_sce7/SC329_subprc01.prc.c|3214668637,ra/fsp/src/r_sce/ra6_sce7/SC32_pc5L_r1.prc.c|1721433062,ra/fsp/src/r_sce/ra6_sce7/SC32_pa6L_r1.prc.c|1223831091,ra/fsp/src/r_sce/ra6_sce7/SC32_p35.prc.c|3241613872,ra/fsp/src/r_sce/hw_sce_hash_private.h|2154312563,ra/fsp/src/r_sce/ra6_sce7/SC32_pe3L_r2.prc.c|1140603247,ra/fsp/src/r_sce/ra6_sce7/SC32_p05.prc.c|2406956049,ra/fsp/src/r_sce/ra6_sce7/SC32_p25.prc.c|4217390015,ra/fsp/src/r_sce/ra6_sce7/SC32_endian.c|2327567471,ra/fsp/src/r_sce/ra6_sce7/SC32_p08.prc.c|697938282,ra/fsp/src/r_sce/ra6_sce7/SC32_pd6L_r1.prc.c|3544953822,ra/fsp/src/r_sce/ra6_sce7/SC32_p22.prc.c|2537930560,ra/fsp/src/r_sce/ra6_sce7/SC32_pd8L.prc.c|1855191979,ra/fsp/src/r_sce/ra6_sce7/SC32_p09.prc.c|3657641003,ra/fsp/src/r_sce/ra6_sce7/SC32_p37L_r1.prc.c|2704354520,ra/fsp/src/r_sce/ra6_sce7/SC32_pe1L_r1.prc.c|162760621,ra/fsp/src/r_sce/ra6_sce7/SC32_p42.prc.c|3354163684,ra/fsp/src/r_sce/ra6_sce7/SC329_p01.prc.c|1158150439,ra/fsp/src/r_sce/ra6_sce7/SC32_p03_r1.prc.c|3579738391,ra/fsp/src/r_sce/ra6_sce7/SC32_subprc02.prc.c|3838204775,ra/fsp/src/r_sce/ra6_sce7/SC32_function003.prc.c
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_sce_ra6\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#1.0.0/all=571529510,ra/fsp/src/r_sci_uart/r_sci_uart.c|2792511208,ra/fsp/inc/api/r_uart_api.h|844992591,ra/fsp/inc/instances/r_sci_uart.h|3587430582,ra/fsp/inc/api/r_transfer_api.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#1.0.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#rm_psa_crypto\#\#\#\#1.0.0/all=310185955,ra/fsp/src/rm_psa_crypto/inc/aes_alt.h|879981984,ra/fsp/src/rm_psa_crypto/aes_alt_process.c|4241193998,ra/fsp/src/rm_psa_crypto/sha256_alt.c|1619824261,ra/fsp/src/rm_psa_crypto/vendor.c|3011574811,ra/fsp/src/rm_psa_crypto/inc/rm_psa_crypto.h|1681689737,ra/fsp/src/rm_psa_crypto/platform_alt.c|1869479850,ra/fsp/src/rm_psa_crypto/aes_vendor.c|946558788,ra/fsp/src/rm_psa_crypto/ecp_alt_process.c|1918513866,ra/fsp/src/rm_psa_crypto/sha256_alt_process.c|851720141,ra/fsp/src/rm_psa_crypto/inc/aes_vendor.h|524224670,ra/fsp/src/rm_psa_crypto/rsa_alt.c|175178314,ra/fsp/src/rm_psa_crypto/ecp_alt.c|1375032557,ra/fsp/src/rm_psa_crypto/ecdsa_alt.c|3487884885,ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h|2684408090,ra/fsp/src/rm_psa_crypto/rm_psa_crypto.c|2686433921,ra/fsp/src/rm_psa_crypto/asymmetric_vendor.c|2997010153,ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h|3344592599,ra/fsp/src/rm_psa_crypto/ecp_curves_alt.c|105318780,ra/fsp/src/rm_psa_crypto/inc/vendor.h|24486682,ra/fsp/src/rm_psa_crypto/trng_entropy.c|2182797932,ra/fsp/src/rm_psa_crypto/rsa_alt_process.c|4056307652,ra/fsp/src/rm_psa_crypto/inc/platform_alt.h|1205739545,ra/fsp/src/rm_psa_crypto/inc/asymmetric_vendor.h|760233223,ra/fsp/src/rm_psa_crypto/aes_alt.c|2956658151,ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#rm_psa_crypto\#\#\#\#1.0.0/libraries=
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.settingseditor.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.settingseditor.prefs
new file mode 100644
index 0000000000..d122a58017
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.settingseditor.prefs
@@ -0,0 +1,2 @@
+com.renesas.cdt.ra.settingseditor.active_page=DeviceAndToolSelection
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.threads.configurator.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.threads.configurator.prefs
new file mode 100644
index 0000000000..683507d2fa
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/com.renesas.cdt.ra.threads.configurator.prefs
@@ -0,0 +1,4 @@
+collapse/module.driver.psa_crypto.1153134270=false
+collapse/module.driver.rm_psa_crypto.1417887177=false
+collapse/module.driver.uart_on_sci_uart.1199375292=false
+eclipse.preferences.version=1
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/language.settings.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/language.settings.xml
new file mode 100644
index 0000000000..d1a81c1b94
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
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diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/org.eclipse.cdt.core.prefs b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000..253f23cad3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,172 @@
+eclipse.preferences.version=1
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+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
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+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18
+org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0
+org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
+org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
+org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
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+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
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+org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
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+org.eclipse.cdt.core.formatter.insert_space_before_identifier_in_declarator_list=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_namespace_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_switch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_type_declaration=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_bracket=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_catch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_exception_specification=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_for=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_if=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_switch=insert
+org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_while=insert
+org.eclipse.cdt.core.formatter.insert_space_before_postfix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_prefix_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_before_semicolon=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_semicolon_in_for=do not insert
+org.eclipse.cdt.core.formatter.insert_space_before_unary_operator=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_expression=do not insert
+org.eclipse.cdt.core.formatter.join_wrapped_lines=true
+org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.lineSplit=120
+org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1
+org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true
+org.eclipse.cdt.core.formatter.tabulation.char=space
+org.eclipse.cdt.core.formatter.tabulation.size=4
+org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/R7FA6M3AH3CFC.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/R7FA6M3AH3CFC.pincfg
new file mode 100644
index 0000000000..5d97f4831e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/R7FA6M3AH3CFC.pincfg
@@ -0,0 +1,36 @@
+
+
+  
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+
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/RA6M3-EK.pincfg b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/RA6M3-EK.pincfg
new file mode 100644
index 0000000000..c2b5eee06e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/RA6M3-EK.pincfg
@@ -0,0 +1,855 @@
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+
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.jlink b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.jlink
new file mode 100644
index 0000000000..39b6d054aa
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.jlink	
@@ -0,0 +1,39 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+MonModeVTableAddr = 0xFFFFFFFF
+MonModeDebug = 0
+MaxNumAPs = 0
+LowPowerHandlingMode = 0
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="ARM7"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.launch b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.launch
new file mode 100644
index 0000000000..5ef4eabd0b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/Secureboot_EK_RA6M3 Debug.launch	
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/configuration.xml b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/configuration.xml
new file mode 100644
index 0000000000..fd95351cad
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/configuration.xml
@@ -0,0 +1,522 @@
+
+
+  
+    
+  
+    
+      
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+  
+  
+    
+      Board support package for R7FA6M3AH3CFC
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Board support package for RA6M3 - FSP Data
+      Renesas.RA_mcu_ra6m3.1.0.0.pack
+    
+    
+      Arm CMSIS Version 5 - Core (M)
+      Arm.CMSIS5.5.6.0.pack
+    
+    
+      RA6M3-EK Board Support Files
+      Renesas.RA_board_ra6m3_ek.1.0.0.pack
+    
+    
+      Board Support Package Common Files
+      Renesas.RA.1.0.0.pack
+    
+    
+      I/O Port
+      Renesas.RA.1.0.0.pack
+    
+    
+      Arm PSA Crypto Implementation
+      Arm.MbedCrypto.3.1.0+renesas.1.pack
+    
+    
+      Flash Memory High Performance
+      Renesas.RA.1.0.0.pack
+    
+    
+      Secure Cryptography Engine on RA6
+      Renesas.RA.1.0.0.pack
+    
+    
+      SCI UART
+      Renesas.RA.1.0.0.pack
+    
+    
+      MbedCrypto H/W Acceleration
+      Renesas.RA.1.0.0.pack
+    
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+  
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diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/ra_cfg.txt b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/ra_cfg.txt
new file mode 100644
index 0000000000..4e100acac8
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/ra_cfg.txt
@@ -0,0 +1,602 @@
+RA Configuration
+  Board "EK-RA6M3"
+  R7FA6M3AH3CFC
+    part_number: R7FA6M3AH3CFC
+    rom_size_bytes: 2097152
+    ram_size_bytes: 655360
+    data_flash_size_bytes: 65536
+    package_style: LQFP
+    package_pins: 176
+    
+  RA6M3
+    series: 6
+    
+  RA6M3 Family
+    OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled
+    OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles
+    OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
+    OFS0 register settings: Independent WDT: Window End Position:  0% (no window end position)
+    OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position)
+    OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
+    OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby
+    OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
+    OFS0 register settings: WDT: Timeout Period: 16384 cycles
+    OFS0 register settings: WDT: Clock Frequency Division Ratio: 128
+    OFS0 register settings: WDT: Window End Position:  0% (no window end position)
+    OFS0 register settings: WDT: Window Start Position: 100% (no window start position)
+    OFS0 register settings: WDT: Reset Interrupt Request: Reset
+    OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode
+    OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
+    OFS1 register settings: Voltage Detection 0 Level: 2.80 V
+    OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
+    MPU: Enable or disable PC Region 0: Enabled
+    MPU: PC0 Start: 0x500
+    MPU: PC0 End: 0xFFFC
+    MPU: Enable or disable PC Region 1: Disabled
+    MPU: PC1 Start: 0xFFFFFFFC
+    MPU: PC1 End: 0xFFFFFFFF
+    MPU: Enable or disable Memory Region 0: Enabled
+    MPU: Memory Region 0 Start: 0x400
+    MPU: Memory Region 0 End: 0xFFFC
+    MPU: Enable or disable Memory Region 1: Disabled
+    MPU: Memory Region 1 Start: 0x200FFFFC
+    MPU: Memory Region 1 End: 0x200FFFFF
+    MPU: Enable or disable Memory Region 2: Disabled
+    MPU: Memory Region 2 Start: 0x407FFFFC
+    MPU: Memory Region 2 End: 0x407FFFFF
+    MPU: Enable or disable Memory Region 3: Disabled
+    MPU: Memory Region 3 Start: 0x400DFFFC
+    MPU: Memory Region 3 End: 0x400DFFFF
+    
+  RA Common
+    Main stack size (bytes): 0x1000
+    Heap size (bytes): 0x1500
+    MCU Vcc (mV): 3300
+    Parameter checking: Disabled
+    Assert Failures: Return FSP_ERR_ASSERTION
+    Error Log: No Error Log
+    ID Code Mode: Unlocked (Ignore ID)
+    ID Code (32 Hex Characters): FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+    Soft Reset: Disabled
+    Main Oscillator Populated: Populated
+    PFS Protect: Enabled
+    Main Oscillator Wait Time: 32768 us
+    Main Oscillator Clock Source: Crystal or Resonator
+    Subclock Populated: Populated
+    Subclock Drive: Standard (12.5pf)
+    Subclock Stabilization Time (ms): 1000
+    
+  Clocks
+    XTAL 24000000Hz
+    PLL Src: XTAL
+    HOCO 20MHz
+    PLL Div /2
+    PLL Mul x20.0
+    Clock Src: PLL
+    ICLK Div /2
+    PCLKA Div /2
+    PCLKB Div /4
+    PCLKC Div /4
+    PCLKD Div /2
+    SDCLKout On
+    BCLK Div /2
+    BCLK/2
+    UCLK Div /5
+    FCLK Div /4
+    CLKOUT Disabled
+    CLKOUT Div /1
+    
+  Pin Configurations
+    RA6M3-EK.pincfg -> g_bsp_pin_cfg
+      AVCC0 155 ADC_AVCC0 - - - - - - - 
+      AVCCUSBHS 26 USBHS0_AVCCUSBHS - - - - - - - 
+      AVSS0 156 ADC_AVSS0 - - - - - - - 
+      AVSSUSBHS 28 USBHS0_AVSSUSBHS - - - - - - - 
+      P000 169 ADC0_AN00 - - - "Analog mode" - - "ADC0: AN00; CMP0: IVCMP2; IRQ0: IRQ06" 
+      P001 168 ADC0_AN01 - - - "Analog mode" - - "ADC0: AN01; CMP0: IVCMP2; IRQ0: IRQ07" 
+      P002 167 ADC0_AN02 - - - "Analog mode" - - "ADC0: AN02; CMP0: IVCMP2; IRQ0: IRQ08" 
+      P003 166 - - - - Disabled - - "ADC0: AN07; ADC0: PGAVSS0" 
+      P004 165 IRQ0_IRQ09 - - IRQ9-DS "IRQ mode" - - "ADC1: AN00; CMP0: IVCMP2; IRQ0: IRQ09" 
+      P005 164 - - - - Disabled - - "ADC1: AN01; CMP0: IVCMP2; IRQ0: IRQ10" 
+      P006 163 - - - - Disabled - - "ADC1: AN02; CMP0: IVCMP2; IRQ0: IRQ11" 
+      P007 162 - - - - Disabled - - "ADC1: AN07; ADC1: PGAVSS0" 
+      P008 161 IRQ0_IRQ12 - - IRQ12-DS "IRQ mode" - - "ADC0: AN03; IRQ0: IRQ12" 
+      P009 160 IRQ0_IRQ13 - - IRQ13-DS "IRQ mode" - - "ADC0: AN04; IRQ0: IRQ13" 
+      P010 159 - - - - Disabled - - "ADC1: AN03; IRQ0: IRQ14" 
+      P014 152 ADC0_AN05 - - - "Analog mode" - - "ADC0: AN05; ADC1: AN05; CMP0: IVREF3; DAC120: DA" 
+      P015 151 - - - - Disabled - - "ADC0: AN06; ADC1: AN06; CMP0: IVCMP1; DAC121: DA; IRQ0: IRQ13" 
+      P100 132 GPIO - Low None "Output mode (Initial Low)" CMOS None "AGT0: AGTIO; BUS0: D0_DQ0; GLCDC0: LCD_EXTCLK; GPT5: GTIOCB; IIC1: SCL; IRQ0: IRQ02; KINT0: KRM0; POEG0: GTETRG; SCI0: RXD_MISO; SCI0: SCL; SCI1: SCK; SPI0: MISO" 
+      P101 131 GLCDC0_LCD_CLK - High None "Peripheral mode" CMOS None "AGT0: AGTEE; BUS0: D1_DQ1; GLCDC0: LCD_CLK; GPT5: GTIOCA; IIC1: SDA; IRQ0: IRQ01; KINT0: KRM1; POEG1: GTETRG; SCI0: SDA; SCI0: TXD_MOSI; SCI1: CTS_RTS_SS; SPI0: MOSI" 
+      P102 130 GLCDC0_LCD_TCON0 - High - "Peripheral mode" CMOS None "ADC0: ADTRG; AGT0: AGTO; BUS0: D2_DQ2; CAN0: CRX; GLCDC0: LCD_TCON0; GPT2: GTIOCB; KINT0: KRM2; OPS0: GTOWLO; SCI0: SCK; SPI0: RSPCK" 
+      P103 129 GLCDC0_LCD_TCON1 - High - "Peripheral mode" CMOS None "BUS0: D3_DQ3; CAN0: CTX; GLCDC0: LCD_TCON1; GPT2: GTIOCA; KINT0: KRM3; OPS0: GTOWUP; SCI0: CTS_RTS_SS; SPI0: SSL0" 
+      P104 128 GLCDC0_LCD_TCON2 - High None "Peripheral mode" CMOS None "BUS0: D4_DQ4; GLCDC0: LCD_TCON2; GPT1: GTIOCB; IRQ0: IRQ01; KINT0: KRM4; POEG1: GTETRG; SCI8: RXD_MISO; SCI8: SCL; SPI0: SSL1" 
+      P105 127 - - - - Disabled - - "BUS0: D5_DQ5; GLCDC0: LCD_TCON3; GPT1: GTIOCA; IRQ0: IRQ00; KINT0: KRM5; POEG0: GTETRG; SCI8: SDA; SCI8: TXD_MOSI; SPI0: SSL2" 
+      P106 126 GLCDC0_LCD_DATA00 - High - "Peripheral mode" CMOS None "AGT0: AGTOB; BUS0: D6_DQ6; GLCDC0: LCD_DATA00; GPT8: GTIOCB; KINT0: KRM6; SCI8: SCK; SPI0: SSL3" 
+      P107 125 GLCDC0_LCD_DATA01 - High - "Peripheral mode" CMOS None "AGT0: AGTOA; BUS0: D7_DQ7; GLCDC0: LCD_DATA01; GPT8: GTIOCA; KINT0: KRM7; SCI8: CTS_RTS_SS" 
+      P108 89 DEBUG0_TMS - Low - "Peripheral mode" CMOS None "DEBUG0: SWDIO; DEBUG0: TMS; GPT0: GTIOCB; OPS0: GTOULO; SCI9: CTS_RTS_SS; SPI1: SSL0" 
+      P109 90 DEBUG0_TDO - Low - "Peripheral mode" CMOS None "CAN1: CTX; CGC0: CLKOUT; DEBUG0: SWO; DEBUG0: TDO; GPT1: GTIOCA; OPS0: GTOVUP; SCI9: SDA; SCI9: TXD_MOSI; SPI1: MOSI" 
+      P110 91 DEBUG0_TDI - Low None "Peripheral mode" CMOS None "CAN1: CRX; CMP0: VCOUT; DEBUG0: TDI; GPT1: GTIOCB; IRQ0: IRQ03; OPS0: GTOVLO; SCI2: CTS_RTS_SS; SCI9: RXD_MISO; SCI9: SCL; SPI1: MISO" 
+      P111 92 GLCDC0_LCD_DATA12 - High None "Peripheral mode" CMOS None "BUS0: A05; GLCDC0: LCD_DATA12; GPT3: GTIOCA; IRQ0: IRQ04; SCI2: SCK; SCI9: SCK; SPI1: RSPCK" 
+      P112 93 GLCDC0_LCD_DATA11 - High - "Peripheral mode" CMOS None "BUS0: A04; GLCDC0: LCD_DATA11; GPT3: GTIOCB; SCI1: SCK; SCI2: SDA; SCI2: TXD_MOSI; SPI1: SSL0; SSI0: SSISCK" 
+      P113 94 GLCDC0_LCD_DATA10 - High - "Peripheral mode" CMOS None "BUS0: A03; GLCDC0: LCD_DATA10; GPT2: GTIOCA; SCI2: RXD_MISO; SCI2: SCL; SSI0: SSIWS" 
+      P114 95 GLCDC0_LCD_DATA09 - High - "Peripheral mode" CMOS None "BUS0: A02; GLCDC0: LCD_DATA09; GPT2: GTIOCB; SSI0: SSIRXD" 
+      P115 96 GLCDC0_LCD_DATA08 - High - "Peripheral mode" CMOS None "BUS0: A01; GLCDC0: LCD_DATA08; GPT4: GTIOCA; SSI0: SSITXD" 
+      P200 69 - - - - Disabled - - "IRQ0: NMI" 
+      P201 68 - - - - Disabled - - - 
+      P202 54 SPI1_MISO - Low None "Peripheral mode" CMOS None "BUS0: WR1_BC1; CAN0: CRX; GLCDC0: LCD_TCON3; GPT5: GTIOCB; IRQ0: IRQ03; SCI2: SCK; SCI9: RXD_MISO; SCI9: SCL; SDHI0: DAT6; SPI1: MISO" 
+      P203 53 SPI1_MOSI - Low None "Peripheral mode" CMOS None "BUS0: A19; CAN0: CTX; CTSU0: TSCAP; GPT5: GTIOCA; IRQ0: IRQ02; SCI2: CTS_RTS_SS; SCI9: SDA; SCI9: TXD_MOSI; SDHI0: DAT5; SPI1: MOSI" 
+      P204 52 SPI1_RSPCK - Low - "Peripheral mode" CMOS None "AGT1: AGTIO; BUS0: A18; CAC0: CACREF; CTSU0: TS00; GPT4: GTIOCB; IIC0: SCL; OPS0: GTIW; SCI4: SCK; SCI9: SCK; SDHI0: DAT4; SPI1: RSPCK; SSI1: SSISCK; USBFS0: OVRCURB" 
+      P205 51 SPI1_SSL0 - Low None "Peripheral mode" CMOS None "AGT1: AGTO; BUS0: A16; CGC0: CLKOUT; CTSU0: TSCAP; ETHERC0: WOL; GPT4: GTIOCA; IIC1: SCL; IRQ0: IRQ01; OPS0: GTIV; SCI4: SDA; SCI4: TXD_MOSI; SCI9: CTS_RTS_SS; SDHI0: DAT3; SPI1: SSL0; SSI1: SSIWS; USBFS0: OVRCURA" 
+      P206 50 GPIO - - IRQ0-DS "Input mode" - "input pull-up" "BUS0: WAIT; CTSU0: TS01; ETHERC0: LINKSTA; IIC1: SDA; IRQ0: IRQ00; OPS0: GTIU; SCI4: RXD_MISO; SCI4: SCL; SDHI0: DAT2; SPI1: SSL1; SSI1: SSIDATA; USBFS0: VBUSEN" 
+      P207 49 - - - - Disabled - - "BUS0: A17; CTSU0: TS02; GLCDC0: LCD_DATA23; QSPI0: QSSL; SPI1: SSL2" 
+      P208 66 TRACE0_TDATA3 - High - "Peripheral mode" CMOS None "ETHERC0: LINKSTA; GLCDC0: LCD_DATA18; OPS0: GTOVLO; QSPI0: QIO3; SDHI0: DAT0; TRACE0: TDATA3" 
+      P209 65 TRACE0_TDATA2 - High - "Peripheral mode" CMOS None "ETHERC0: EXOUT; GLCDC0: LCD_DATA19; OPS0: GTOVUP; QSPI0: QIO2; SDHI0: WP; TRACE0: TDATA2" 
+      P210 64 TRACE0_TDATA1 - High - "Peripheral mode" CMOS None "ETHERC0: WOL; GLCDC0: LCD_DATA20; OPS0: GTIW; QSPI0: QIO1; SDHI0: CD; TRACE0: TDATA1" 
+      P211 63 TRACE0_TDATA0 - High - "Peripheral mode" CMOS None "ETHERC0: MDIO; GLCDC0: LCD_DATA21; OPS0: GTIV; QSPI0: QIO0; SDHI0: CMD; TRACE0: TDATA0" 
+      P212 24 CGC0_EXTAL - Low None "Peripheral mode" CMOS None "AGT1: AGTEE; CGC0: EXTAL; GPT0: GTIOCB; IRQ0: IRQ03; POEG3: GTETRG; SCI1: RXD_MISO; SCI1: SCL" 
+      P213 23 CGC0_XTAL - Low None "Peripheral mode" CMOS None "ADC1: ADTRG; CGC0: XTAL; GPT0: GTIOCA; IRQ0: IRQ02; POEG2: GTETRG; SCI1: SDA; SCI1: TXD_MOSI" 
+      P214 62 TRACE0_TCLK - High - "Peripheral mode" CMOS None "ETHERC0: MDC; GLCDC0: LCD_DATA22; OPS0: GTIU; QSPI0: QSPCLK; SDHI0: CLK; TRACE0: TCLK" 
+      P300 88 DEBUG0_TCK - Low - "Peripheral mode" CMOS None "DEBUG0: SWCLK; DEBUG0: TCK; GPT0: GTIOCA; OPS0: GTOUUP; SPI1: SSL1" 
+      P301 87 GLCDC0_LCD_DATA13 - High None "Peripheral mode" CMOS None "AGT0: AGTIO; BUS0: A06; GLCDC0: LCD_DATA13; GPT4: GTIOCB; IRQ0: IRQ06; OPS0: GTOULO; SCI2: RXD_MISO; SCI2: SCL; SCI9: CTS_RTS_SS; SPI1: SSL2" 
+      P302 86 GLCDC0_LCD_DATA14 - High None "Peripheral mode" CMOS None "BUS0: A07; GLCDC0: LCD_DATA14; GPT4: GTIOCA; IRQ0: IRQ05; OPS0: GTOUUP; SCI2: SDA; SCI2: TXD_MOSI; SPI1: SSL3" 
+      P303 85 GLCDC0_LCD_DATA15 - High - "Peripheral mode" CMOS None "BUS0: A08; GLCDC0: LCD_DATA15; GPT7: GTIOCB" 
+      P304 82 GPIO - Low None "Output mode (Initial High)" CMOS None "BUS0: A09; GLCDC0: LCD_DATA16; GPT7: GTIOCA; IRQ0: IRQ09; OPS0: GTOWLO; SCI6: RXD_MISO; SCI6: SCL" 
+      P305 81 QSPI0_QSPCLK - High None "Peripheral mode" CMOS None "BUS0: A10; GLCDC0: LCD_DATA17; IRQ0: IRQ08; OPS0: GTOWUP; QSPI0: QSPCLK; SCI6: SDA; SCI6: TXD_MOSI" 
+      P306 80 QSPI0_QSSL - High - "Peripheral mode" CMOS None "BUS0: A11; GLCDC0: LCD_DATA18; OPS0: GTOULO; QSPI0: QSSL; SCI6: SCK" 
+      P307 79 QSPI0_QIO0 - High - "Peripheral mode" CMOS None "BUS0: A12; GLCDC0: LCD_DATA19; OPS0: GTOUUP; QSPI0: QIO0; SCI6: CTS_RTS_SS" 
+      P308 78 QSPI0_QIO1 - High - "Peripheral mode" CMOS None "BUS0: A13; GLCDC0: LCD_DATA20; QSPI0: QIO1" 
+      P309 77 QSPI0_QIO2 - High - "Peripheral mode" CMOS None "BUS0: A14; GLCDC0: LCD_DATA21; QSPI0: QIO2; SCI3: RXD_MISO; SCI3: SCL" 
+      P310 76 QSPI0_QIO3 - High - "Peripheral mode" CMOS None "AGT1: AGTEE; BUS0: A15; GLCDC0: LCD_DATA22; QSPI0: QIO3; SCI3: SDA; SCI3: TXD_MOSI" 
+      P311 75 - - - - Disabled - - "AGT1: AGTOB; BUS0: CS2_RAS; GLCDC0: LCD_DATA23; SCI3: SCK" 
+      P312 74 - - - - Disabled - - "AGT1: AGTOA; BUS0: CS3_CAS; SCI3: CTS_RTS_SS" 
+      P313 55 - - - - Disabled - - "BUS0: A20; GLCDC0: LCD_TCON2; SDHI0: DAT7" 
+      P314 56 - - - - Disabled - - "ADC0: ADTRG; BUS0: A21; GLCDC0: LCD_TCON1" 
+      P315 57 - - - - Disabled - - "BUS0: A22; GLCDC0: LCD_TCON0; SCI4: RXD_MISO; SCI4: SCL" 
+      P400 1 GPIO IRQ0 Low None "Output mode (Initial Low)" CMOS None "ADC1: ADTRG; AGT1: AGTIO; ETHERC0: WOL; GPT6: GTIOCA; IIC0: SCL; IRQ0: IRQ00; SCI4: SCK; SCI7: SCK; SSI: AUDIO_CLK" 
+      P401 2 RMII_MDC - High None "Peripheral mode" CMOS None "CAN0: CTX; ETHERC0: MDC; GPT6: GTIOCB; IIC0: SDA; IRQ0: IRQ05; POEG0: GTETRG; SCI4: CTS_RTS_SS; SCI7: SDA; SCI7: TXD_MOSI" 
+      P402 3 RMII_MDIO - High None "Peripheral mode" CMOS None "AGT0: AGTIO; AGT1: AGTIO; CAC0: CACREF; CAN0: CRX; ETHERC0: MDIO; IRQ0: IRQ04; PDC0: VSYNC; RTC0: RTCIC0; SCI7: RXD_MISO; SCI7: SCL; SSI: AUDIO_CLK" 
+      P403 4 GPIO - Low - "Output mode (Initial Low)" CMOS None "AGT0: AGTIO; AGT1: AGTIO; ETHERC0: LINKSTA; GPT3: GTIOCA; PDC0: PIXD7; RTC0: RTCIC1; SCI7: CTS_RTS_SS; SDHI1: DAT7; SSI0: SSISCK" 
+      P404 5 GPIO - Low - "Output mode (Initial High)" CMOS None "ETHERC0: EXOUT; GPT3: GTIOCB; PDC0: PIXD6; RTC0: RTCIC2; SDHI1: DAT6; SSI0: SSIWS" 
+      P405 6 RMII_TXD_EN - High - "Peripheral mode" CMOS None "ETHERC0: TXD_EN; GPT1: GTIOCA; PDC0: PIXD5; SDHI1: DAT5; SSI0: SSITXD" 
+      P406 7 RMII_TXD1 - High - "Peripheral mode" CMOS None "ETHERC0: TXD1; GPT1: GTIOCB; PDC0: PIXD4; SDHI1: DAT4; SPI1: SSL3; SSI0: SSIRXD" 
+      P407 44 USBFS0_VBUS - Low - "Peripheral mode" CMOS None "ADC0: ADTRG; AGT0: AGTIO; CTSU0: TS03; ETHERC0: EXOUT; IIC0: SDA; RTC0: RTCOUT; SCI4: CTS_RTS_SS; SPI1: SSL3; USBFS0: VBUS" 
+      P408 43 SCI3_SCL - Low None "Peripheral mode" "n-ch open drain" None "CTSU0: TS04; ETHERC0: CRS_DV; GPT10: GTIOCB; IIC0: SCL; IRQ0: IRQ07; OPS0: GTOWLO; PDC0: PIXCLK; SCI3: RXD_MISO; SCI3: SCL; USBFS0: ID; USBHS0: ID" 
+      P409 42 SCI3_SDA - Low None "Peripheral mode" "n-ch open drain" None "CTSU0: TS05; ETHERC0: RX_ER; GPT10: GTIOCA; IRQ0: IRQ06; OPS0: GTOWUP; PDC0: HSYNC; SCI3: SDA; SCI3: TXD_MOSI; USBFS0: EXICEN; USBHS0: EXICEN" 
+      P410 41 SPI0_MISO - Low None "Peripheral mode" CMOS None "AGT1: AGTOB; CTSU0: TS06; ETHERC0: RXD1; GPT9: GTIOCB; IRQ0: IRQ05; OPS0: GTOVLO; PDC0: PIXD0; SCI0: RXD_MISO; SCI0: SCL; SCI3: SCK; SDHI0: DAT1; SPI0: MISO" 
+      P411 40 SPI0_MOSI - Low None "Peripheral mode" CMOS None "AGT1: AGTOA; CTSU0: TS07; ETHERC0: RXD0; GPT9: GTIOCA; IRQ0: IRQ04; OPS0: GTOVUP; PDC0: PIXD1; SCI0: SDA; SCI0: TXD_MOSI; SCI3: CTS_RTS_SS; SDHI0: DAT0; SPI0: MOSI" 
+      P412 39 SPI0_RSPCK - Low - "Peripheral mode" CMOS None "AGT1: AGTEE; CTSU0: TS08; ETHERC0: REF50CK; OPS0: GTOULO; PDC0: PIXD2; SCI0: SCK; SDHI0: CMD; SPI0: RSPCK" 
+      P413 38 GPIO - Low - "Output mode (Initial Low)" CMOS None "CTSU0: TS09; ETHERC0: TXD0; OPS0: GTOUUP; PDC0: PIXD3; SCI0: CTS_RTS_SS; SDHI0: CLK; SPI0: SSL0" 
+      P414 37 SPI0_SSL1 - Low None "Peripheral mode" CMOS None "CTSU0: TS10; ETHERC0: TXD1; GPT0: GTIOCB; IRQ0: IRQ09; PDC0: PIXD4; SDHI0: WP; SPI0: SSL1" 
+      P415 36 GPT0_GTIOCA - Low None "Peripheral mode" CMOS None "CTSU0: TS11; ETHERC0: TXD_EN; GPT0: GTIOCA; IRQ0: IRQ08; PDC0: PIXD5; SDHI0: CD; SPI0: SSL2; USBFS0: VBUSEN" 
+      P500 140 USBFS0_VBUSEN - Low - "Peripheral mode" CMOS None "ADC0: AN16; AGT0: AGTOA; CMP0: IVREF0; GPT11: GTIOCA; OPS0: GTIU; QSPI0: QSPCLK; SDHI1: CLK; USBFS0: VBUSEN" 
+      P501 141 USBFS0_OVRCURA - Low None "Peripheral mode" CMOS None "ADC1: AN16; AGT0: AGTOB; CMP0: IVREF1; GPT11: GTIOCB; IRQ0: IRQ11; OPS0: GTIV; QSPI0: QSSL; SCI5: SDA; SCI5: TXD_MOSI; SDHI1: CMD; USBFS0: OVRCURA" 
+      P502 142 - - - - Disabled - - "ADC0: AN17; CMP0: IVCMP0; GPT12: GTIOCA; IRQ0: IRQ12; OPS0: GTIW; QSPI0: QIO0; SCI5: RXD_MISO; SCI5: SCL; SDHI1: DAT0; USBFS0: OVRCURB" 
+      P503 143 GPIO - Low - "Output mode (Initial Low)" CMOS None "ADC1: AN17; GPT12: GTIOCB; POEG2: GTETRG; QSPI0: QIO1; SCI5: SCK; SCI6: CTS_RTS_SS; SDHI1: DAT1; USBFS0: EXICEN" 
+      P504 144 GPIO - Low - "Output mode (Initial Low)" CMOS None "ADC0: AN18; BUS0: ALE; GPT13: GTIOCA; POEG3: GTETRG; QSPI0: QIO2; SCI5: CTS_RTS_SS; SCI6: SCK; SDHI1: DAT2; USBFS0: ID" 
+      P505 145 IRQ0_IRQ14 - - IRQ14 "IRQ mode" - - "ADC1: AN18; GPT13: GTIOCB; IRQ0: IRQ14; QSPI0: QIO3; SCI6: RXD_MISO; SCI6: SCL; SDHI1: DAT3" 
+      P506 146 IRQ0_IRQ15 - - IRQ15 "IRQ mode" - - "ADC0: AN19; IRQ0: IRQ15; SCI6: SDA; SCI6: TXD_MOSI; SDHI1: CD" 
+      P507 147 ADC1_AN19 - - - "Analog mode" - - "ADC1: AN19; SCI5: CTS_RTS_SS; SDHI1: WP" 
+      P508 148 ADC0_AN20 - - - "Analog mode" - - "ADC0: AN20; SCI5: SCK; SCI6: SCK" 
+      P511 176 IIC2_SDA - Medium None "Peripheral mode" CMOS None "CAN1: CRX; GPT0: GTIOCB; IIC2: SDA; IRQ0: IRQ15; PDC0: PCKO; SCI4: RXD_MISO; SCI4: SCL" 
+      P512 175 IIC2_SCL - Medium None "Peripheral mode" CMOS None "CAN1: CTX; GPT0: GTIOCA; IIC2: SCL; IRQ0: IRQ14; PDC0: VSYNC; SCI4: SDA; SCI4: TXD_MOSI" 
+      P513 174 - - - - Disabled - - "GLCDC0: LCD_DATA16; SCI5: RXD_MISO; SCI5: SCL" 
+      P600 122 GLCDC0_LCD_DATA02 - High - "Peripheral mode" CMOS None "BUS0: RD; CAC0: CACREF; CGC0: CLKOUT; GLCDC0: LCD_DATA02; GPT6: GTIOCB; SCI9: SCK" 
+      P601 121 GLCDC0_LCD_DATA03 - High - "Peripheral mode" CMOS None "BUS0: WR_WR0_DQM0; GLCDC0: LCD_DATA03; GPT6: GTIOCA; SCI9: RXD_MISO; SCI9: SCL" 
+      P602 120 GLCDC0_LCD_DATA04 - High - "Peripheral mode" CMOS None "BUS0: BCLK_SDCLK; GLCDC0: LCD_DATA04; GPT7: GTIOCB; SCI9: SDA; SCI9: TXD_MOSI" 
+      P603 119 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: D13_DQ13; GPT7: GTIOCA; SCI9: CTS_RTS_SS" 
+      P604 118 - - - - Disabled - - "BUS0: D12_DQ12; GPT8: GTIOCB" 
+      P605 117 - - - - Disabled - - "BUS0: D11_DQ11; GPT8: GTIOCA" 
+      P606 116 - - - - Disabled - - "GLCDC0: LCD_DATA03; RTC0: RTCOUT; SCI8: CTS_RTS_SS" 
+      P607 115 - - - - Disabled - - "GLCDC0: LCD_DATA04; SCI8: RXD_MISO; SCI8: SCL" 
+      P608 99 GLCDC0_LCD_DATA07 - High - "Peripheral mode" CMOS None "BUS0: A00_BC0_DQM1; GLCDC0: LCD_DATA07; GPT4: GTIOCB" 
+      P609 100 GLCDC0_LCD_DATA06 - High - "Peripheral mode" CMOS None "BUS0: CS1_CKE; CAN1: CTX; GLCDC0: LCD_DATA06; GPT5: GTIOCA" 
+      P610 101 GLCDC0_LCD_DATA05 - High - "Peripheral mode" CMOS None "BUS0: CS0_WE; CAN1: CRX; GLCDC0: LCD_DATA05; GPT5: GTIOCB" 
+      P611 102 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: SDCS; CAC0: CACREF; CGC0: CLKOUT; SCI7: CTS_RTS_SS" 
+      P612 103 - - - - Disabled - - "BUS0: D8_DQ8; SCI7: SCK" 
+      P613 104 SCI7_TXD_MOSI - Low - "Peripheral mode" CMOS None "BUS0: D9_DQ9; SCI7: SDA; SCI7: TXD_MOSI" 
+      P614 105 SCI7_RXD_MISO - Low - "Peripheral mode" CMOS None "BUS0: D10_DQ10; SCI7: RXD_MISO; SCI7: SCL" 
+      P615 106 - - - - Disabled - - "GLCDC0: LCD_DATA10" 
+      P700 8 RMII_TXD0 - High - "Peripheral mode" CMOS None "ETHERC0: TXD0; GPT5: GTIOCA; PDC0: PIXD3; SDHI1: DAT3; SPI1: MISO" 
+      P701 9 RMII_REF50CK - High - "Peripheral mode" CMOS None "ETHERC0: REF50CK; GPT5: GTIOCB; PDC0: PIXD2; SDHI1: DAT2; SPI1: MOSI" 
+      P702 10 RMII_RXD0 - High - "Peripheral mode" CMOS None "ETHERC0: RXD0; GPT6: GTIOCA; PDC0: PIXD1; SDHI1: DAT1; SPI1: RSPCK" 
+      P703 11 RMII_RXD1 - High - "Peripheral mode" CMOS None "CMP0: VCOUT; ETHERC0: RXD1; GPT6: GTIOCB; PDC0: PIXD0; SDHI1: DAT0; SPI1: SSL0" 
+      P704 12 RMII_RX_ER - High - "Peripheral mode" CMOS None "AGT0: AGTO; CAN0: CTX; ETHERC0: RX_ER; PDC0: HSYNC; SDHI1: CLK; SPI1: SSL1" 
+      P705 13 RMII_CRS_DV - High - "Peripheral mode" CMOS None "AGT0: AGTIO; CAN0: CRX; ETHERC0: CRS_DV; PDC0: PIXCLK; SDHI1: CMD; SPI1: SSL2" 
+      P706 14 IRQ0_IRQ07 - - IRQ7 "IRQ mode" - - "IRQ0: IRQ07; SCI3: RXD_MISO; SCI3: SCL; SDHI1: CD; USBHS0: OVRCURB" 
+      P707 15 USBHS0_OVRCURA - Low None "Peripheral mode" CMOS None "IRQ0: IRQ08; SCI3: SDA; SCI3: TXD_MOSI; SDHI1: WP; USBHS0: OVRCURA" 
+      P708 35 IRQ0_IRQ11 - - IRQ11 "IRQ mode" - - "CAC0: CACREF; CTSU0: TS12; IRQ0: IRQ11; PDC0: PCKO; SCI1: RXD_MISO; SCI1: SCL; SPI0: SSL3; SSI: AUDIO_CLK" 
+      P800 133 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: D14_DQ14" 
+      P801 134 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: D15_DQ15; SDHI1: DAT4" 
+      P802 135 GPIO - Low - "Output mode (Initial Low)" CMOS None "GLCDC0: LCD_DATA02; SDHI1: DAT5" 
+      P803 136 GPIO - Low - "Output mode (Initial Low)" CMOS None "GLCDC0: LCD_DATA01; SDHI1: DAT6" 
+      P804 137 GPIO - Low - "Output mode (Initial Low)" CMOS None "GLCDC0: LCD_DATA00; SDHI1: DAT7" 
+      P805 173 GPIO - Low - "Output mode (Initial Low)" CMOS None "GLCDC0: LCD_DATA17; SCI5: SDA; SCI5: TXD_MOSI" 
+      P806 172 - - - - Disabled - - "GLCDC0: LCD_EXTCLK" 
+      P900 58 - - - - Disabled - - "BUS0: A23; GLCDC0: LCD_CLK; SCI4: SDA; SCI4: TXD_MOSI" 
+      P901 59 - - - - Disabled - - "AGT1: AGTIO; GLCDC0: LCD_DATA15; SCI4: SCK" 
+      P905 73 - - - - Disabled - - "BUS0: CS4; GLCDC0: LCD_DATA11; GPT13: GTIOCB" 
+      P906 72 - - - - Disabled - - "BUS0: CS5; GLCDC0: LCD_DATA12; GPT13: GTIOCA" 
+      P907 71 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: CS6; GLCDC0: LCD_DATA13; GPT12: GTIOCB" 
+      P908 70 GPIO - Low - "Output mode (Initial Low)" CMOS None "BUS0: CS7; GLCDC0: LCD_DATA14; GPT12: GTIOCA" 
+      PA00 114 - - - - Disabled - - "GLCDC0: LCD_DATA05; SCI8: SDA; SCI8: TXD_MOSI" 
+      PA01 113 - - - - Disabled - - "GLCDC0: LCD_DATA06; SCI8: SCK" 
+      PA08 107 - - - - Disabled - - "GLCDC0: LCD_DATA09" 
+      PA09 108 - - - - Disabled - - "GLCDC0: LCD_DATA08" 
+      PA10 109 - - - - Disabled - - "GLCDC0: LCD_DATA07" 
+      PB00 16 USBHS0_VBUSEN - Low - "Peripheral mode" CMOS None "SCI3: SCK; USBHS0: VBUSEN" 
+      PB01 17 USBHS0_VBUS - Low - "Peripheral mode" CMOS None "SCI3: CTS_RTS_SS; USBHS0: VBUS" 
+      PVSSUSBHS 29 USBHS0_PVSSUSBHS - - - - - - - 
+      RES 67 - - - - - - - - 
+      USBDM 46 USBFS0_USBDM - - - - - - - 
+      USBDP 47 USBFS0_USBDP - - - - - - - 
+      USBHSDM 31 USBHS0_USBHSDM - - - - - - - 
+      USBHSDP 32 USBHS0_USBHSDP - - - - - - - 
+      USBHSRREF 27 USBHS0_USBHSRREF - - - - - - - 
+      VBAT 18 - - - - - - - - 
+      VCC 110 - - - - - - - - 
+      VCC 123 - - - - - - - - 
+      VCC 25 - - - - - - - - 
+      VCC 138 - - - - - - - - 
+      VCC 149 - - - - - - - - 
+      VCC 61 - - - - - - - - 
+      VCC 171 - - - - - - - - 
+      VCC 84 - - - - - - - - 
+      VCC 97 - - - - - - - - 
+      VCCUSB 48 USBFS0_VCCUSB - - - - - - - 
+      VCCUSBHS 34 USBHS0_VCCUSBHS - - - - - - - 
+      VCL 19 - - - - - - - - 
+      VCL1 112 - - - - - - - - 
+      VREFH 154 ADC_VREFH - - - - - - - 
+      VREFH0 158 ADC_VREFH0 - - - - - - - 
+      VREFL 153 ADC_VREFL - - - - - - - 
+      VREFL0 157 ADC_VREFL0 - - - - - - - 
+      VSS 22 - - - - - - - - 
+      VSS 111 - - - - - - - - 
+      VSS 124 - - - - - - - - 
+      VSS 139 - - - - - - - - 
+      VSS 60 - - - - - - - - 
+      VSS 170 - - - - - - - - 
+      VSS 83 - - - - - - - - 
+      VSS 150 - - - - - - - - 
+      VSS 98 - - - - - - - - 
+      VSS1USBHS 33 USBHS0_VSS1USBHS - - - - - - - 
+      VSS2USBHS 30 USBHS0_VSS2USBHS - - - - - - - 
+      VSSUSB 45 USBFS0_VSSUSB - - - - - - - 
+      XCIN 20 CGC0_XCIN - - - - - - - 
+      XCOUT 21 CGC0_XCOUT - - - - - - - 
+      
+  User Events
+    
+  User Event Links
+    
+  Module "I/O Port Driver on r_ioport"
+    Parameter Checking: Default (BSP)
+    
+  Module "Flash Driver on r_flash_hp"
+    Parameter Checking: Default (BSP)
+    Code Flash Programming Enable: Enabled
+    Data Flash Programming Enable: Enabled
+    
+  Module "Mbed Crypto"
+    Hardware Acceleration: TRNG: Enabled
+    Hardware Acceleration: Key Format: AES: Plaintext Only
+    Hardware Acceleration: Key Format: ECC: Plaintext Only
+    Hardware Acceleration: Key Format: RSA: Plaintext Only
+    Hardware Acceleration: Hash: SHA256/224: Use Hardware
+    Hardware Acceleration: Cipher: AES: Use Hardware
+    Hardware Acceleration: Public Key Cryptography (PKC): ECC: Use Hardware
+    Hardware Acceleration: Public Key Cryptography (PKC): ECDSA : Use Hardware
+    Hardware Acceleration: Public Key Cryptography (PKC): RSA: Use Hardware
+    Hardware Acceleration: Secure Crypto Engine Initialization: Enabled
+    Platform: MBEDTLS_HAVE_ASM: Undefine
+    Platform: MBEDTLS_NO_UDBL_DIVISION: Undefine
+    Platform: MBEDTLS_NO_64BIT_MULTIPLICATION: Undefine
+    Platform: MBEDTLS_HAVE_SSE2: Undefine
+    Platform: MBEDTLS_HAVE_TIME: Undefine
+    Platform: MBEDTLS_HAVE_TIME_DATE: Undefine
+    Platform: MBEDTLS_PLATFORM_MEMORY: Define
+    Platform: MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_EXIT_ALT: Define
+    Platform: Alternate: MBEDTLS_PLATFORM_TIME_ALT: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_FPRINTF_ALT: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_PRINTF_ALT: Define
+    Platform: Alternate: MBEDTLS_PLATFORM_SNPRINTF_ALT: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_VSNPRINTF_ALT: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_NV_SEED_ALT: Undefine
+    General: MBEDTLS_DEPRECATED_WARNING: Undefine
+    General: MBEDTLS_DEPRECATED_REMOVED: Define
+    General: MBEDTLS_CHECK_PARAMS: Define
+    General: MBEDTLS_CHECK_PARAMS_ASSERT: Undefine
+    Platform: MBEDTLS_TIMING_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_ARC4_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_ARIA_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_BLOWFISH_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_CAMELLIA_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_CCM_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_CHACHA20_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_CHACHAPOLY_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_CMAC_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_DES_ALT: Undefine
+    Public Key Cryptography (PKC): DHM: Alternate: MBEDTLS_DHM_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECJPAKE_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_GCM_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_NIST_KW_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD2_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD4_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD5_ALT: Undefine
+    Message Authentication Code (MAC): Alternate: MBEDTLS_POLY1305_ALT: Undefine
+    Hash: Alternate: MBEDTLS_RIPEMD160_ALT: Undefine
+    Hash: Alternate: MBEDTLS_SHA1_ALT: Undefine
+    Hash: Alternate: MBEDTLS_SHA512_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_XTEA_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD2_PROCESS_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD4_PROCESS_ALT: Undefine
+    Hash: Alternate: MBEDTLS_MD5_PROCESS_ALT: Undefine
+    Hash: Alternate: MBEDTLS_RIPEMD160_PROCESS_ALT: Undefine
+    Hash: Alternate: MBEDTLS_SHA1_PROCESS_ALT: Undefine
+    Hash: Alternate: MBEDTLS_SHA512_PROCESS_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_DES_SETKEY_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_DES_CRYPT_ECB_ALT: Undefine
+    Cipher: Alternate: MBEDTLS_DES3_CRYPT_ECB_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDH_GEN_PUBLIC_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDH_COMPUTE_SHARED_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECDSA_GENKEY_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_INTERNAL_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_RANDOMIZE_JAC_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_ADD_MIXED_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_DOUBLE_JAC_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_NORMALIZE_JAC_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_RANDOMIZE_MXZ_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: Alternate: MBEDTLS_ECP_NORMALIZE_MXZ_ALT: Undefine
+    RNG: MBEDTLS_TEST_NULL_ENTROPY: Undefine
+    Cipher: AES: MBEDTLS_AES_ROM_TABLES: Undefine
+    Cipher: AES: MBEDTLS_AES_FEWER_TABLES: Undefine
+    Cipher: MBEDTLS_CAMELLIA_SMALL_MEMORY: Undefine
+    Cipher: MBEDTLS_CIPHER_MODE_CBC: Define
+    Cipher: MBEDTLS_CIPHER_MODE_CFB: Define
+    Cipher: MBEDTLS_CIPHER_MODE_CTR: Define
+    Cipher: MBEDTLS_CIPHER_MODE_OFB: Undefine
+    Cipher: MBEDTLS_CIPHER_MODE_XTS: Undefine
+    Cipher: MBEDTLS_CIPHER_NULL_CIPHER: Undefine
+    Cipher: MBEDTLS_CIPHER_PADDING_PKCS7: Define
+    Cipher: MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS: Define
+    Cipher: MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN: Define
+    Cipher: MBEDTLS_CIPHER_PADDING_ZEROS: Define
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP192R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP224R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP256R1_ENABLED: Define
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP384R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP521R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP192K1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP224K1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_SECP256K1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_BP256R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_BP384R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_BP512R1_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_CURVE25519_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: Curves: MBEDTLS_ECP_DP_CURVE448_ENABLED: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_NIST_OPTIM: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_RESTARTABLE: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDH_LEGACY_CONTEXT: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDSA_DETERMINISTIC: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_PK_PARSE_EC_EXTENDED: Undefine
+    General: MBEDTLS_ERROR_STRERROR_DUMMY: Define
+    Public Key Cryptography (PKC): MBEDTLS_GENPRIME: Define
+    Storage: MBEDTLS_FS_IO: Undefine
+    RNG: MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES: Undefine
+    Platform: MBEDTLS_NO_PLATFORM_ENTROPY: Define
+    RNG: MBEDTLS_ENTROPY_FORCE_SHA256: Undefine
+    RNG: MBEDTLS_ENTROPY_NV_SEED: Undefine
+    Storage: MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER: Undefine
+    General: MBEDTLS_MEMORY_DEBUG: Undefine
+    General: MBEDTLS_MEMORY_BACKTRACE: Undefine
+    Public Key Cryptography (PKC): RSA: MBEDTLS_PK_RSA_ALT_SUPPORT: Undefine
+    Public Key Cryptography (PKC): MBEDTLS_PKCS1_V15: Define
+    Public Key Cryptography (PKC): MBEDTLS_PKCS1_V21: Define
+    General: MBEDTLS_PSA_CRYPTO_SPM: Undefine
+    RNG: MBEDTLS_PSA_INJECT_ENTROPY: Undefine
+    Public Key Cryptography (PKC): RSA: MBEDTLS_RSA_NO_CRT: Define
+    General: MBEDTLS_SELF_TEST: Undefine
+    Hash: MBEDTLS_SHA256_SMALLER: Undefine
+    Hash: MBEDTLS_SHA512_SMALLER: Undefine
+    Hash: MBEDTLS_SHA512_NO_SHA384: Undefine
+    General: MBEDTLS_THREADING_ALT: Undefine
+    General: MBEDTLS_THREADING_PTHREAD: Undefine
+    General: MBEDTLS_USE_PSA_CRYPTO: Undefine
+    General: MBEDTLS_VERSION_FEATURES: Define
+    Cipher: MBEDTLS_AES_C: Define
+    Cipher: MBEDTLS_ARC4_C: Undefine
+    Public Key Cryptography (PKC): MBEDTLS_ASN1_PARSE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_ASN1_WRITE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_BASE64_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_BIGNUM_C: Define
+    Cipher: MBEDTLS_BLOWFISH_C: Undefine
+    Cipher: MBEDTLS_CAMELLIA_C: Undefine
+    Cipher: MBEDTLS_ARIA_C: Undefine
+    Cipher: MBEDTLS_CCM_C: Define
+    Cipher: MBEDTLS_CHACHA20_C: Undefine
+    Cipher: MBEDTLS_CHACHAPOLY_C: Undefine
+    Cipher: MBEDTLS_CIPHER_C: Define
+    Message Authentication Code (MAC): MBEDTLS_CMAC_C: Undefine
+    RNG: MBEDTLS_CTR_DRBG_C: Define
+    Cipher: MBEDTLS_DES_C: Undefine
+    Public Key Cryptography (PKC): DHM: MBEDTLS_DHM_C: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDH_C: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDSA_C: Define
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_C: Define
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECJPAKE_C: Undefine
+    Platform: MBEDTLS_ENTROPY_C: Define
+    General: MBEDTLS_ERROR_C: Define
+    Cipher: MBEDTLS_GCM_C: Define
+    RNG: MBEDTLS_HAVEGE_C: Undefine
+    Message Authentication Code (MAC): MBEDTLS_HKDF_C: Define
+    Message Authentication Code (MAC): MBEDTLS_HMAC_DRBG_C: Undefine
+    Cipher: MBEDTLS_NIST_KW_C: Undefine
+    Hash: MBEDTLS_MD_C: Define
+    Hash: MBEDTLS_MD2_C: Undefine
+    Hash: MBEDTLS_MD4_C: Undefine
+    Hash: MBEDTLS_MD5_C: Define
+    General: MBEDTLS_MEMORY_BUFFER_ALLOC_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_OID_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PEM_PARSE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PEM_WRITE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PK_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PK_PARSE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PK_WRITE_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PKCS5_C: Define
+    Public Key Cryptography (PKC): MBEDTLS_PKCS12_C: Define
+    Platform: MBEDTLS_PLATFORM_C: Define
+    Message Authentication Code (MAC): MBEDTLS_POLY1305_C: Undefine
+    General: MBEDTLS_PSA_CRYPTO_C: Define
+    General: MBEDTLS_PSA_CRYPTO_SE_C: Undefine
+    Storage: MBEDTLS_PSA_CRYPTO_STORAGE_C: Undefine
+    Storage: MBEDTLS_PSA_ITS_FILE_C: Undefine
+    Hash: MBEDTLS_RIPEMD160_C: Define
+    Public Key Cryptography (PKC): RSA: MBEDTLS_RSA_C: Define
+    Hash: MBEDTLS_SHA1_C: Undefine
+    Hash: MBEDTLS_SHA256_C: Define
+    Hash: MBEDTLS_SHA512_C: Undefine
+    General: MBEDTLS_THREADING_C: Undefine
+    General: MBEDTLS_TIMING_C: Undefine
+    General: MBEDTLS_VERSION_C: Define
+    Cipher: MBEDTLS_XTEA_C: Undefine
+    Public Key Cryptography (PKC): MBEDTLS_MPI_WINDOW_SIZE: Undefine
+    Public Key Cryptography (PKC): MBEDTLS_MPI_WINDOW_SIZE value: 6
+    Public Key Cryptography (PKC): MBEDTLS_MPI_MAX_SIZE: Undefine
+    Public Key Cryptography (PKC): MBEDTLS_MPI_MAX_SIZE value: 1024
+    RNG: MBEDTLS_CTR_DRBG_ENTROPY_LEN: Undefine
+    RNG: MBEDTLS_CTR_DRBG_ENTROPY_LEN value: 48
+    RNG: MBEDTLS_CTR_DRBG_RESEED_INTERVAL: Undefine
+    RNG: MBEDTLS_CTR_DRBG_RESEED_INTERVAL value: 10000
+    RNG: MBEDTLS_CTR_DRBG_MAX_INPUT: Undefine
+    RNG: MBEDTLS_CTR_DRBG_MAX_INPUT value: 256
+    RNG: MBEDTLS_CTR_DRBG_MAX_REQUEST: Undefine
+    RNG: MBEDTLS_CTR_DRBG_MAX_REQUEST value: 1024
+    RNG: MBEDTLS_CTR_DRBG_MAX_SEED_INPUT: Undefine
+    RNG: MBEDTLS_CTR_DRBG_MAX_SEED_INPUT value: 384
+    RNG: MBEDTLS_CTR_DRBG_USE_128_BIT_KEY: Undefine
+    RNG: MBEDTLS_HMAC_DRBG_RESEED_INTERVAL: Undefine
+    RNG: MBEDTLS_HMAC_DRBG_RESEED_INTERVAL value: 10000
+    RNG: MBEDTLS_HMAC_DRBG_MAX_INPUT: Undefine
+    RNG: MBEDTLS_HMAC_DRBG_MAX_INPUT value: 256
+    RNG: MBEDTLS_HMAC_DRBG_MAX_REQUEST: Undefine
+    RNG: MBEDTLS_HMAC_DRBG_MAX_REQUEST value: 1024
+    RNG: MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT: Undefine
+    RNG: MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT value: 384
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_MAX_BITS: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_MAX_BITS value: 521
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_WINDOW_SIZE: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_WINDOW_SIZE value: 6
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_FIXED_POINT_OPTIM: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECP_FIXED_POINT_OPTIM value: 1
+    RNG: MBEDTLS_ENTROPY_MAX_SOURCES: Undefine
+    RNG: MBEDTLS_ENTROPY_MAX_SOURCES value: 20
+    RNG: MBEDTLS_ENTROPY_MAX_GATHER: Undefine
+    RNG: MBEDTLS_ENTROPY_MAX_GATHER value: 128
+    RNG: MBEDTLS_ENTROPY_MIN_HARDWARE: Undefine
+    RNG: MBEDTLS_ENTROPY_MIN_HARDWARE value: 32
+    General: MBEDTLS_MEMORY_ALIGN_MULTIPLE: Undefine
+    General: MBEDTLS_MEMORY_ALIGN_MULTIPLE value: 4
+    Platform: MBEDTLS_PLATFORM_STD_CALLOC: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_CALLOC value: calloc
+    Platform: MBEDTLS_PLATFORM_STD_FREE: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_FREE value: free
+    Platform: MBEDTLS_PLATFORM_STD_EXIT: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_EXIT value: exit
+    Platform: MBEDTLS_PLATFORM_STD_TIME: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_TIME value: time
+    Platform: MBEDTLS_PLATFORM_STD_FPRINTF: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_FPRINTF value: fprintf
+    Platform: MBEDTLS_PLATFORM_STD_PRINTF: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_PRINTF value: printf
+    Platform: MBEDTLS_PLATFORM_STD_SNPRINTF: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_SNPRINTF value: snprintf
+    Platform: MBEDTLS_PLATFORM_STD_EXIT_SUCCESS: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_EXIT_SUCCESS value: 0
+    Platform: MBEDTLS_PLATFORM_STD_EXIT_FAILURE: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_EXIT_FAILURE value: 1
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_READ: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_READ value: mbedtls_platform_std_nv_seed_read
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_WRITE: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_WRITE value: mbedtls_platform_std_nv_seed_write
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_FILE: Undefine
+    Platform: MBEDTLS_PLATFORM_STD_NV_SEED_FILE value: 
+    Platform: MBEDTLS_PLATFORM_CALLOC_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_CALLOC_MACRO value: calloc
+    Platform: MBEDTLS_PLATFORM_FREE_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_FREE_MACRO value: free
+    Platform: MBEDTLS_PLATFORM_EXIT_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_EXIT_MACRO value: exit
+    Platform: MBEDTLS_PLATFORM_TIME_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_TIME_MACRO value: time
+    Platform: MBEDTLS_PLATFORM_TIME_TYPE_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_TIME_TYPE_MACRO value: time_t
+    Platform: MBEDTLS_PLATFORM_FPRINTF_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_FPRINTF_MACRO value: fprintf
+    Platform: MBEDTLS_PLATFORM_PRINTF_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_PRINTF_MACRO value: printf
+    Platform: MBEDTLS_PLATFORM_SNPRINTF_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_SNPRINTF_MACRO value: snprintf
+    Platform: MBEDTLS_PLATFORM_VSNPRINTF_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_VSNPRINTF_MACRO value: vsnprintf
+    Platform: MBEDTLS_PLATFORM_NV_SEED_READ_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_NV_SEED_READ_MACRO value: mbedtls_platform_std_nv_seed_read
+    Platform: MBEDTLS_PARAM_FAILED: Undefine
+    Platform: MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO: Undefine
+    Platform: MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO value: mbedtls_platform_std_nv_seed_write
+    Platform: Alternate: MBEDTLS_PLATFORM_ZEROIZE_ALT: Undefine
+    Platform: Alternate: MBEDTLS_PLATFORM_GMTIME_R_ALT: Undefine
+    Public Key Cryptography (PKC): ECC: MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED: Undefine
+    
+  Module "Mbed Crypto HW Acceleration"
+  Module "SCE7"
+  Module "UART Driver on r_sci_uart"
+    Parameter Checking: Default (BSP)
+    FIFO Support: Disable
+    DTC Support: Disable
+    RS232/RS485 Flow Control Support: Disable
+    
+  HAL
+    Instance "g_ioport I/O Port Driver on r_ioport"
+      Name: g_ioport
+      Port 1 ELC Trigger Source: Disabled
+      Port 2 ELC Trigger Source: Disabled
+      Port 3 ELC Trigger Source: Disabled
+      Port 4 ELC Trigger Source: Disabled
+      
+    Instance "g_flash Flash Driver on r_flash_hp"
+      Name: g_flash
+      Data Flash Background Operation: Disabled
+      Callback: NULL
+      Flash Ready Interrupt Priority: Disabled
+      Flash Error Interrupt Priority: Disabled
+      
+    Instance "Mbed Crypto"
+      Instance "Mbed Crypto HW Acceleration"
+        Instance "SCE7"
+    Instance "g_uart UART Driver on r_sci_uart"
+      General: Name: g_uart
+      General: Channel: 7
+      General: Data Bits: 8bits
+      General: Parity: None
+      General: Stop Bits: 1bit
+      Baud: Baud Rate: 115200
+      Baud: Baud Rate Modulation: Disabled
+      Baud: Max Error (%): 5
+      Flow Control: CTS/RTS Selection: RTS (CTS is disabled)
+      Flow Control: UART Communication Mode: RS232
+      Flow Control: Pin Control: Disabled
+      Flow Control: RTS Port: Disabled
+      Flow Control: RTS Pin: Disabled
+      Extra: Clock Source: Internal Clock
+      Extra: Start bit detection: Falling Edge
+      Extra: Noise Filter: Disable
+      Extra: Receive FIFO Trigger Level: Max
+      Interrupts: Callback: user_uart_callback
+      Interrupts: Receive Interrupt Priority: Priority 12
+      Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
+      Interrupts: Transmit End Interrupt Priority: Priority 12
+      Interrupts: Error Interrupt Priority: Priority 12
+      
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/script/ra6m3.ld b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/script/ra6m3.ld
similarity index 94%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/script/ra6m3.ld
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/script/ra6m3.ld
index b1fe0436f2..becf829b13 100644
--- a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/script/ra6m3.ld
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/script/ra6m3.ld
@@ -5,8 +5,8 @@
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx)         : ORIGIN = 0x20030500, LENGTH = 0x0010000  /*   2M */
-  RAM (rwx)          : ORIGIN = 0x20040500, LENGTH = 0x0030000  /* 640K */
+  FLASH (rx)         : ORIGIN = 0x00000000, LENGTH = 0x0200000  /*   2M */
+  RAM (rwx)          : ORIGIN = 0x1FFE0000, LENGTH = 0x00A0000  /* 640K */
   DATA_FLASH (rx)    : ORIGIN = 0x40100000, LENGTH = 0x0010000  /*  64K */
   QSPI_FLASH (rx)    : ORIGIN = 0x60000000, LENGTH = 0x4000000  /*  64M, Change in QSPI section below also */
   SDRAM (rwx)        : ORIGIN = 0x90000000, LENGTH = 0x2000000  /*  32M */
@@ -188,7 +188,9 @@ SECTIONS
         __Code_In_RAM_End = .;
 
         *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
         *(.data.*)
+        *(.data)
 
         . = ALIGN(4);
         /* preinit data */
@@ -225,6 +227,7 @@ SECTIONS
     {
         __qspi_flash_start__ = .;
         KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
         __qspi_flash_end__ = .;
     } > QSPI_FLASH
     __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
@@ -248,6 +251,9 @@ SECTIONS
         . = ALIGN(4);
         __noinit_start = .;
         KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
         __noinit_end = .;
     } > RAM
 
@@ -263,13 +269,12 @@ SECTIONS
 
     .heap (NOLOAD):
     {
-        . = ALIGN(8);
-        KEEP(*(.heap_d1))
         . = ALIGN(8);
         __HeapBase = .;
         __end__ = .;
         end = __end__;
-        KEEP(*(.heap*))
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
         __HeapLimit = .;
     } > RAM
 
@@ -309,7 +314,7 @@ SECTIONS
         __SDRAM_End = .;
     } > SDRAM
 
-    .id_code :
+    .id_code (NOLOAD):
     {
         __ID_Code_Start = .;
         KEEP(*(.id_code*))
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/CMakeLists.txt b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/CMakeLists.txt
new file mode 100644
index 0000000000..d8a14cbe86
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/CMakeLists.txt
@@ -0,0 +1,248 @@
+#------------------------------------------------------------------------------
+# Copyright (c) 2017-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#------------------------------------------------------------------------------
+
+cmake_minimum_required(VERSION 3.7)
+
+set(TFM_BUILD_IN_SPE ON)
+
+#Tell cmake where our modules can be found
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/../../../cmake)
+
+#Include common stuff to control cmake.
+include("Common/BuildSys")
+
+#Start an embedded project.
+get_filename_component(TFM_ROOT_DIR "${CMAKE_CURRENT_LIST_DIR}/../../.." ABSOLUTE)
+embedded_project_start(CONFIG "${TFM_ROOT_DIR}/configs/ConfigDefault.cmake")
+project(mcuboot LANGUAGES ASM C)
+embedded_project_fixup()
+
+#Set the appropriate MCUBoot path
+if (MCUBOOT_REPO STREQUAL "TF-M")
+	get_filename_component(MCUBOOT_DIR ${CMAKE_CURRENT_LIST_DIR} ABSOLUTE)
+else()
+	get_filename_component(MCUBOOT_DIR "${TFM_ROOT_DIR}/../mcuboot/boot" ABSOLUTE)
+	if (NOT EXISTS ${MCUBOOT_DIR})
+		message(FATAL_ERROR "Missing MCUBoot. Please clone the MCUBoot repo to directory \"${MCUBOOT_DIR}\".")
+	endif()
+endif()
+
+#Check input variables
+if (NOT DEFINED BL2)
+   message(FATAL ERROR "Incomplete build configuration: BL2 is undefined.")
+elseif(NOT BL2)
+    #If mcuboot is not need to be built then stop further processing.
+    return()
+endif()
+
+if (NOT DEFINED MBEDCRYPTO_C_FLAGS_BL2)
+	message(FATAL_ERROR "Incomplete build configuration: MBEDCRYPTO_C_FLAGS_BL2 is undefined.")
+endif()
+
+set(BUILD_CMSIS_CORE On)
+set(BUILD_RETARGET On)
+set(BUILD_NATIVE_DRIVERS On)
+set(BUILD_STARTUP On)
+set(BUILD_TARGET_CFG Off)
+set(BUILD_TARGET_NV_COUNTERS On)
+set(BUILD_CMSIS_DRIVERS On)
+set(BUILD_TIME Off)
+set(BUILD_UART_STDOUT On)
+set(BUILD_FLASH On)
+set(BUILD_PLAT_TEST Off)
+set(BUILD_BOOT_HAL On)
+
+if (MCUBOOT_HW_KEY)
+	set(BUILD_TARGET_HARDWARE_KEYS On)
+else()
+	set(BUILD_TARGET_HARDWARE_KEYS Off)
+endif()
+
+if(NOT DEFINED PLATFORM_CMAKE_FILE)
+	message (FATAL_ERROR "Platform specific CMake is not defined. Please set PLATFORM_CMAKE_FILE.")
+elseif(NOT EXISTS ${PLATFORM_CMAKE_FILE})
+	message (FATAL_ERROR "Platform specific CMake \"${PLATFORM_CMAKE_FILE}\" file does not exist. Please fix value of PLATFORM_CMAKE_FILE.")
+else()
+	include(${PLATFORM_CMAKE_FILE})
+endif()
+
+#Add platform specific definitions in SPE
+if (DEFINED TFM_PLATFORM_SECURE_DEFS)
+	embedded_set_target_compile_defines(TARGET ${PROJECT_NAME} LANGUAGE C DEFINES ${TFM_PLATFORM_SECURE_DEFS} APPEND)
+	embedded_set_target_compile_defines(TARGET ${PROJECT_NAME} LANGUAGE ASM DEFINES ${TFM_PLATFORM_SECURE_DEFS} APPEND)
+endif()
+
+#Append all our source files to global lists.
+list(APPEND ALL_SRC_C
+		"${TFM_ROOT_DIR}/bl2/ext/mcuboot/bl2_main.c"
+		"${TFM_ROOT_DIR}/bl2/ext/mcuboot/flash_map_extended.c"
+		"${TFM_ROOT_DIR}/bl2/ext/mcuboot/flash_map_legacy.c"
+		"${TFM_ROOT_DIR}/bl2/ext/mcuboot/keys.c"
+		"${TFM_ROOT_DIR}/bl2/src/flash_map.c"
+		"${MCUBOOT_DIR}/bootutil/src/loader.c"
+		"${MCUBOOT_DIR}/bootutil/src/bootutil_misc.c"
+		"${MCUBOOT_DIR}/bootutil/src/image_validate.c"
+		"${MCUBOOT_DIR}/bootutil/src/image_rsa.c"
+		"${MCUBOOT_DIR}/bootutil/src/tlv.c"
+	)
+
+if (MCUBOOT_REPO STREQUAL "TF-M")
+	list(APPEND ALL_SRC_C
+			"${TFM_ROOT_DIR}/bl2/src/boot_record.c"
+			"${TFM_ROOT_DIR}/bl2/src/security_cnt.c"
+		)
+endif()
+
+#Define location of Mbed Crypto source, build, and installation directory.
+set(MBEDTLS_CONFIG_FILE "config-rsa.h")
+set(MBEDTLS_CONFIG_PATH "${TFM_ROOT_DIR}/bl2/ext/mcuboot/include")
+get_filename_component(MBEDCRYPTO_SOURCE_DIR "${TFM_ROOT_DIR}/../mbed-crypto" ABSOLUTE)
+if(NOT EXISTS ${MBEDCRYPTO_SOURCE_DIR})
+    message(FATAL_ERROR "Missing mbed-crypto. Please clone the mbed-crypto repo to directory \"${MBEDCRYPTO_SOURCE_DIR}\".")
+endif()
+set (MBEDCRYPTO_BINARY_DIR "${CMAKE_CURRENT_BINARY_DIR}/mbed-crypto/build")
+set (MBEDCRYPTO_INSTALL_DIR ${MBEDCRYPTO_BINARY_DIR}/../install)
+
+if (CRYPTO_HW_ACCELERATOR OR CRYPTO_HW_ACCELERATOR_OTP_STATE STREQUAL "PROVISIONING")
+	if(NOT DEFINED CRYPTO_HW_ACCELERATOR_CMAKE_BUILD)
+		message(FATAL_ERROR "CRYPTO_HW_ACCELERATOR_CMAKE_BUILD not defined.")
+	endif()
+	include(${CRYPTO_HW_ACCELERATOR_CMAKE_BUILD})
+endif()
+
+#Build Mbed Crypto as external project.
+#This ensures Mbed Crypto is built with exactly defined settings.
+#Mbed Crypto will be used from its install location
+string(APPEND MBEDCRYPTO_C_FLAGS " ${MBEDCRYPTO_C_FLAGS_BL2}")
+set(MBEDCRYPTO_TARGET_NAME "mbedcrypto_mcuboot_lib")
+include(${TFM_ROOT_DIR}/BuildMbedCrypto.cmake)
+
+#Setting include directories
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${TFM_ROOT_DIR} ABSOLUTE APPEND)
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${TFM_ROOT_DIR}/interface/include ABSOLUTE APPEND)
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${TFM_ROOT_DIR}/bl2/include ABSOLUTE APPEND)
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${TFM_ROOT_DIR}/bl2/ext/mcuboot/include ABSOLUTE APPEND)
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${MCUBOOT_DIR}/bootutil/include ABSOLUTE APPEND)
+embedded_target_include_directories(TARGET ${PROJECT_NAME} PATH ${MBEDCRYPTO_INSTALL_DIR}/include ABSOLUTE APPEND)
+
+#Define linker file
+if(NOT DEFINED BL2_LINKER_CONFIG)
+	message(FATAL_ERROR "ERROR: Incomplete Configuration: BL2_LINKER_CONFIG is not defined.")
+endif()
+embedded_set_target_linker_file(TARGET ${PROJECT_NAME} PATH "${BL2_LINKER_CONFIG}")
+
+if(NOT DEFINED PLATFORM_LINK_INCLUDES)
+	message(FATAL_ERROR "ERROR: Incomplete Configuration: PLATFORM_LINK_INCLUDES is not defined.")
+endif()
+embedded_set_target_link_includes(TARGET ${PROJECT_NAME} INCLUDES "${PLATFORM_LINK_INCLUDES}")
+
+add_executable(${PROJECT_NAME} ${ALL_SRC_ASM} ${ALL_SRC_C_BL2} ${ALL_SRC_ASM_BL2} ${ALL_SRC_C} ${ALL_SRC_CXX})
+
+#Set common compiler and linker flags
+config_setting_shared_compiler_flags(${PROJECT_NAME})
+config_setting_shared_linker_flags(${PROJECT_NAME})
+
+#Add BL2 and MCUBOOT_IMAGE_NUMBER defines to linker to resolve symbols in region_defs.h and flash_layout.h
+embedded_set_target_link_defines(TARGET ${PROJECT_NAME} DEFINES "BL2" "MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}")
+
+if(NOT DEFINED TEST_FRAMEWORK_S)
+	message(FATAL_ERROR "Incomplete build configuration: TEST_FRAMEWORK_S is undefined.")
+elseif(TEST_FRAMEWORK_S)
+	embedded_set_target_link_defines(TARGET ${PROJECT_NAME} DEFINES "TEST_FRAMEWORK_S")
+endif()
+
+if(NOT DEFINED TEST_FRAMEWORK_NS)
+	message(FATAL_ERROR "Incomplete build configuration: TEST_FRAMEWORK_NS is undefined.")
+elseif(TEST_FRAMEWORK_NS)
+	embedded_set_target_link_defines(TARGET ${PROJECT_NAME} DEFINES "TEST_FRAMEWORK_NS")
+endif()
+
+#Link mbedcrypto library to project
+target_link_libraries(${PROJECT_NAME} "${MBEDCRYPTO_INSTALL_DIR}/lib/${CMAKE_STATIC_LIBRARY_PREFIX_C}mbedcrypto${CMAKE_STATIC_LIBRARY_SUFFIX_C}")
+add_dependencies(${PROJECT_NAME} ${MBEDCRYPTO_TARGET_NAME}_install)
+
+#Link crypto accelerator libraries if applicable
+if (CRYPTO_HW_ACCELERATOR OR CRYPTO_HW_ACCELERATOR_OTP_STATE STREQUAL "PROVISIONING")
+	if(NOT DEFINED CRYPTO_HW_ACCELERATOR_CMAKE_LINK)
+		message(FATAL_ERROR "CRYPTO_HW_ACCELERATOR_CMAKE_LINK not defined.")
+	endif()
+	include(${CRYPTO_HW_ACCELERATOR_CMAKE_LINK})
+endif()
+
+#Generate binary file from axf
+compiler_generate_binary_output(${PROJECT_NAME})
+
+message("- MCUBOOT_REPO: '${MCUBOOT_REPO}'.")
+message("- MCUBOOT_IMAGE_NUMBER: '${MCUBOOT_IMAGE_NUMBER}'.")
+message("- MCUBOOT_UPGRADE_STRATEGY: '${MCUBOOT_UPGRADE_STRATEGY}'.")
+message("- MCUBOOT_SIGNATURE_TYPE: '${MCUBOOT_SIGNATURE_TYPE}'.")
+message("- MCUBOOT_HW_KEY: '${MCUBOOT_HW_KEY}'.")
+message("- MCUBOOT_LOG_LEVEL: '${MCUBOOT_LOG_LEVEL}'.")
+
+#Set macro definitions for the project.
+target_compile_definitions(${PROJECT_NAME} PRIVATE
+							MCUBOOT_VALIDATE_PRIMARY_SLOT
+							MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+							MBEDTLS_CONFIG_FILE="${MBEDTLS_CONFIG_FILE}"
+							MCUBOOT_TARGET_CONFIG="flash_layout.h")
+
+if (MCUBOOT_REPO STREQUAL "UPSTREAM")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_USE_UPSTREAM)
+endif()
+
+if (MCUBOOT_SIGNATURE_TYPE STREQUAL "RSA-3072")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_SIGN_RSA MCUBOOT_SIGN_RSA_LEN=3072)
+elseif(MCUBOOT_SIGNATURE_TYPE STREQUAL "RSA-2048")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_SIGN_RSA MCUBOOT_SIGN_RSA_LEN=2048)
+else()
+	message(FATAL_ERROR "${MCUBOOT_SIGNATURE_TYPE} is not supported as firmware signing algorithm")
+endif()
+
+if (${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "OVERWRITE_ONLY")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_OVERWRITE_ONLY)
+elseif (${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "NO_SWAP")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_NO_SWAP)
+elseif (${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "RAM_LOADING")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_RAM_LOADING)
+elseif (${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "SWAP")
+	#No compile definition needs to be specified for this upgrade strategy
+else()
+	get_property(_upgrade_strategies CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS)
+	message(FATAL_ERROR "ERROR: MCUBoot supports the ${_upgrade_strategies} upgrade strategies only.")
+endif()
+
+if (MCUBOOT_HW_KEY)
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_HW_KEY)
+endif()
+
+if (ATTEST_BOOT_INTERFACE STREQUAL "INDIVIDUAL_CLAIMS")
+	target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_INDIVIDUAL_CLAIMS)
+	message(WARNING "ATTEST_BOOT_INTERFACE was set to ${ATTEST_BOOT_INTERFACE}. This configuration is "
+			"deprecated and this feature will probably be removed from MCUBoot in the future.")
+endif()
+
+#Configure log level for MCUBoot.
+get_property(_log_levels CACHE MCUBOOT_LOG_LEVEL PROPERTY STRINGS)
+list(FIND _log_levels ${MCUBOOT_LOG_LEVEL} LOG_LEVEL_ID)
+target_compile_definitions(${PROJECT_NAME} PRIVATE MCUBOOT_LOG_LEVEL=${LOG_LEVEL_ID})
+
+#Set install location. Keep original value to avoid overriding command line settings.
+if(CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT)
+	set(CMAKE_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/install" CACHE PATH "Default install location for MCUBoot." FORCE)
+endif()
+
+#Collect executables to common location: build/install/outputs/
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.axf
+			  ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.bin
+		DESTINATION outputs/${TARGET_PLATFORM}/)
+
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.axf
+			  ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.bin
+		DESTINATION outputs/fvp/)
+
+#Finally let cmake system apply changes after the whole project is defined.
+embedded_project_end(${PROJECT_NAME})
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBoot.cmake b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBoot.cmake
new file mode 100644
index 0000000000..e344e3e636
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBoot.cmake
@@ -0,0 +1,340 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+cmake_minimum_required(VERSION 3.7)
+
+function(mcuboot_create_boot_payload)
+	set( _OPTIONS_ARGS)										  #Option (on/off) arguments (e.g. IGNORE_CASE)
+	set( _ONE_VALUE_ARGS S_BIN NS_BIN FULL_BIN SIGN_BIN POSTFIX) #Single option arguments (e.g. PATH "./foo/bar")
+	set( _MULTI_VALUE_ARGS)									  #List arguments (e.g. LANGUAGES C ASM CXX)
+	cmake_parse_arguments(_MY_PARAMS "${_OPTIONS_ARGS}" "${_ONE_VALUE_ARGS}" "${_MULTI_VALUE_ARGS}" ${ARGN})
+
+	if (NOT DEFINED _MY_PARAMS_S_BIN)
+		message(FATAL_ERROR "mcuboot_create_boot_payload(): mandatory parameter 'S_BIN' missing.")
+	endif()
+
+	if (NOT DEFINED _MY_PARAMS_NS_BIN)
+		message(FATAL_ERROR "mcuboot_create_boot_payload(): mandatory parameter 'NS_BIN' missing.")
+	endif()
+
+	if (NOT DEFINED _MY_PARAMS_FULL_BIN)
+		message(FATAL_ERROR "mcuboot_create_boot_payload(): mandatory parameter 'FULL_BIN' missing.")
+	endif()
+
+	if (NOT DEFINED _MY_PARAMS_SIGN_BIN)
+		message(FATAL_ERROR "mcuboot_create_boot_payload(): mandatory parameter 'SIGN_BIN' missing.")
+	endif()
+
+	if (DEFINED _MY_PARAMS_POSTFIX)
+		if (${_MY_PARAMS_POSTFIX} STREQUAL "_1")
+			set(MY_POSTFIX "1")
+		else()
+			message(FATAL_ERROR "Unknown artefacts postfix: ${_MY_PARAMS_POSTFIX}")
+		endif()
+	endif()
+
+	#Find Python3.x interpreter
+	find_package(PythonInterp 3)
+	if (NOT PYTHONINTERP_FOUND)
+		message(FATAL_ERROR "Failed to find Python3.x interpreter. Pyhton3 must be installed and available on the PATH.")
+	endif()
+
+	if(NOT DEFINED FLASH_LAYOUT)
+		message(FATAL_ERROR "ERROR: Incomplete Configuration: FLASH_LAYOUT is not defined.")
+	endif()
+
+	if (MCUBOOT_SIGNATURE_TYPE STREQUAL "RSA-3072")
+		set(KEY_FILE    "${MCUBOOT_DIR}/root-rsa-3072.pem")
+		set(KEY_FILE_S  "${MCUBOOT_DIR}/root-rsa-3072.pem")
+		set(KEY_FILE_NS "${MCUBOOT_DIR}/root-rsa-3072_1.pem")
+	elseif(MCUBOOT_SIGNATURE_TYPE STREQUAL "RSA-2048")
+		set(KEY_FILE    "${MCUBOOT_DIR}/root-rsa-2048.pem")
+		set(KEY_FILE_S  "${MCUBOOT_DIR}/root-rsa-2048.pem")
+		set(KEY_FILE_NS "${MCUBOOT_DIR}/root-rsa-2048_1.pem")
+	else()
+		message(FATAL_ERROR "${MCUBOOT_SIGNATURE_TYPE} is not supported as firmware signing algorithm")
+	endif()
+
+	#Configure in which format (full or hash) include the public key to the image manifest
+	#
+	#|-----------------------|-----------------------|-------------------|--------------------|
+	#|                       |Key format in manifest |Key in MCUBoot code|     Key in HW      |
+	#|-----------------------|-----------------------|-------------------|--------------------|
+	#|MCUBOOT_HW_KEY ==  On  |    Full public key    |  No key embedded  | Hash of public key |
+	#|-----------------------|-----------------------|-------------------|--------------------|
+	#|MCUBOOT_HW_KEY ==  Off |   Hash of public key  |  Full public key  |   No key in HW     |
+	#|-----------------------|-----------------------|-------------------|--------------------|
+	if (MCUBOOT_HW_KEY)
+		set(PUBLIC_KEY_FORMAT "full")
+	else()
+		set(PUBLIC_KEY_FORMAT "hash")
+	endif()
+
+	set(PARTIAL_CONTENT_FOR_PREPROCESSING "#include \"${FLASH_LAYOUT}\"\n\n"
+		"/* Enumeration that is used by the assemble.py and imgtool.py scripts\n"
+		" * for correct binary generation when nested macros are used\n"
+		" */\n"
+		"enum image_attributes {\n"
+		"\tRE_SECURE_IMAGE_OFFSET = SECURE_IMAGE_OFFSET,\n"
+		"\tRE_SECURE_IMAGE_MAX_SIZE = SECURE_IMAGE_MAX_SIZE,\n"
+		"\tRE_NON_SECURE_IMAGE_OFFSET = NON_SECURE_IMAGE_OFFSET,\n"
+		"\tRE_NON_SECURE_IMAGE_MAX_SIZE = NON_SECURE_IMAGE_MAX_SIZE,\n"
+		"#ifdef IMAGE_LOAD_ADDRESS\n"
+		"\tRE_IMAGE_LOAD_ADDRESS = IMAGE_LOAD_ADDRESS,\n"
+		"#endif\n"
+	)
+
+if (MCUBOOT_IMAGE_NUMBER GREATER 1)
+	if (SECURITY_COUNTER_S)
+		set(ADD_SECURITY_COUNTER_S "-s ${SECURITY_COUNTER_S}")
+	else()
+		set(ADD_SECURITY_COUNTER_S "")
+	endif()
+	if (SECURITY_COUNTER_NS)
+		set(ADD_SECURITY_COUNTER_NS "-s ${SECURITY_COUNTER_NS}")
+	else()
+		set(ADD_SECURITY_COUNTER_NS "")
+	endif()
+	if (DEFINED SECURITY_COUNTER)
+		message(WARNING "In case of multiple updatable images the security counter value can be specified"
+			" for the Secure and Non-secure images separately with the SECURITY_COUNTER_S and SECURITY_COUNTER_NS"
+			" defines. The value of SECURITY_COUNTER was ignored.")
+		set(SECURITY_COUNTER "")
+	endif()
+
+	if (NOT IMAGE_VERSION_S)
+		set(IMAGE_VERSION_S 0.0.0+0)
+	endif()
+	if (NOT IMAGE_VERSION_NS)
+		set(IMAGE_VERSION_NS 0.0.0+0)
+	endif()
+	if (DEFINED IMAGE_VERSION)
+		message(WARNING "In case of multiple updatable images the image version can be specified"
+			" for the Secure and Non-secure images separately with the IMAGE_VERSION_S and IMAGE_VERSION_NS"
+			" defines. The value of IMAGE_VERSION was ignored.")
+		set(IMAGE_VERSION "")
+	endif()
+
+	if (S_IMAGE_MIN_VER)
+		set(ADD_S_IMAGE_MIN_VER "-d \"(0,${S_IMAGE_MIN_VER})\"")
+	else()
+		set(ADD_S_IMAGE_MIN_VER "")
+	endif()
+	if (NS_IMAGE_MIN_VER)
+		set(ADD_NS_IMAGE_MIN_VER "-d \"(1,${NS_IMAGE_MIN_VER})\"")
+	else()
+		set(ADD_NS_IMAGE_MIN_VER "")
+	endif()
+
+	set(FILE_TO_PREPROCESS ${CMAKE_BINARY_DIR}/image_macros_to_preprocess)
+	set(PREPROCESSED_FILE ${CMAKE_BINARY_DIR}/image_macros_preprocessed)
+
+	#Create files that will be preprocessed later in order to be able to handle
+	# nested macros in header files for certain macros
+	string(CONCAT CONTENT_FOR_PREPROCESSING ${PARTIAL_CONTENT_FOR_PREPROCESSING}
+			"\tRE_SIGN_BIN_SIZE = FLASH_AREA_0_SIZE,\n}\;")
+	file(WRITE ${FILE_TO_PREPROCESS}_s.c ${CONTENT_FOR_PREPROCESSING})
+	string(CONCAT CONTENT_FOR_PREPROCESSING ${PARTIAL_CONTENT_FOR_PREPROCESSING}
+			"\tRE_SIGN_BIN_SIZE = FLASH_AREA_1_SIZE,\n}\;")
+	file(WRITE ${FILE_TO_PREPROCESS}_ns.c ${CONTENT_FOR_PREPROCESSING})
+
+	#Preprocess the _s.c file that contains the secure image related macros
+	compiler_preprocess_file(SRC ${FILE_TO_PREPROCESS}_s.c
+							DST ${PREPROCESSED_FILE}_s.c
+							BEFORE_TARGET ${_MY_PARAMS_S_BIN}
+							TARGET_PREFIX ${_MY_PARAMS_S_BIN}
+							DEFINES "MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}")
+
+	#Preprocess the _ns.c file that contains the non-secure image related macros
+	compiler_preprocess_file(SRC ${FILE_TO_PREPROCESS}_ns.c
+							DST ${PREPROCESSED_FILE}_ns.c
+							BEFORE_TARGET ${_MY_PARAMS_NS_BIN}
+							TARGET_PREFIX ${_MY_PARAMS_NS_BIN}
+							DEFINES "MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}")
+
+	add_custom_command(TARGET ${_MY_PARAMS_NS_BIN}
+						POST_BUILD
+
+						#Sign secure binary image with default public key in mcuboot folder
+						COMMAND ${PYTHON_EXECUTABLE} ${MCUBOOT_DIR}/scripts/imgtool.py
+						ARGS sign
+							 --layout ${PREPROCESSED_FILE}_s.c
+							 -k ${KEY_FILE_S}
+							 --public-key-format ${PUBLIC_KEY_FORMAT}
+							 --align 1
+							 -v ${IMAGE_VERSION_S}
+							 ${ADD_NS_IMAGE_MIN_VER}
+							 ${ADD_SECURITY_COUNTER_S}
+							 -H 0x400
+							 $/${_MY_PARAMS_S_BIN}.bin
+							 ${CMAKE_BINARY_DIR}/${_MY_PARAMS_S_BIN}_signed.bin
+
+						#Sign non-secure binary image with default public key in mcuboot folder
+						COMMAND ${PYTHON_EXECUTABLE} ${MCUBOOT_DIR}/scripts/imgtool.py
+						ARGS sign
+							 --layout ${PREPROCESSED_FILE}_ns.c
+							 -k ${KEY_FILE_NS}
+							 --public-key-format ${PUBLIC_KEY_FORMAT}
+							 --align 1
+							 -v ${IMAGE_VERSION_NS}
+							 ${ADD_S_IMAGE_MIN_VER}
+							 ${ADD_SECURITY_COUNTER_NS}
+							 -H 0x400
+							 $/${_MY_PARAMS_NS_BIN}.bin
+							 ${CMAKE_BINARY_DIR}/${_MY_PARAMS_NS_BIN}_signed.bin
+
+						#Create concatenated binary image from the two independently signed binary file
+						COMMAND ${PYTHON_EXECUTABLE} ${MCUBOOT_DIR}/scripts/assemble.py
+						ARGS --layout ${PREPROCESSED_FILE}_s.c
+							 -s ${CMAKE_BINARY_DIR}/${_MY_PARAMS_S_BIN}_signed.bin
+							 -n ${CMAKE_BINARY_DIR}/${_MY_PARAMS_NS_BIN}_signed.bin
+							 -o ${CMAKE_BINARY_DIR}/${_MY_PARAMS_SIGN_BIN}.bin)
+
+else() # MCUBOOT_IMAGE_NUMBER = 1
+	if (SECURITY_COUNTER)
+		set(ADD_SECURITY_COUNTER "-s ${SECURITY_COUNTER}")
+	else()
+		set(ADD_SECURITY_COUNTER "")
+	endif()
+	if (DEFINED SECURITY_COUNTER_S OR
+		DEFINED SECURITY_COUNTER_NS)
+		message(WARNING "In case of a single updatable image the security counter value can be specified with"
+			" the SECURITY_COUNTER define. The values of SECURITY_COUNTER_S and/or SECURITY_COUNTER_NS were ignored.")
+		set(SECURITY_COUNTER_S "")
+		set(SECURITY_COUNTER_NS "")
+	endif()
+
+	if (NOT IMAGE_VERSION)
+		set(IMAGE_VERSION 0.0.0+0)
+	endif()
+	if (DEFINED IMAGE_VERSION_S OR
+		DEFINED IMAGE_VERSION_NS)
+		message(WARNING "In case of a single updatable image the image version can be specified with"
+			" the IMAGE_VERSION define. The values of IMAGE_VERSION_S and/or IMAGE_VERSION_NS were ignored.")
+		set(IMAGE_VERSION_S "")
+		set(IMAGE_VERSION_NS "")
+	endif()
+
+	if (DEFINED S_IMAGE_MIN_VER OR
+		DEFINED NS_IMAGE_MIN_VER)
+		message(WARNING "WARNING: In case of a single updatable image a dependency cannot be specified between"
+			" the S and NS images. The S_IMAGE_MIN_VER and/or NS_IMAGE_MIN_VER defines were ignored.")
+		set(S_IMAGE_MIN_VER "")
+		set(NS_IMAGE_MIN_VER "")
+	endif()
+
+	set(FILE_TO_PREPROCESS ${CMAKE_BINARY_DIR}/image_macros_to_preprocess.c)
+	set(PREPROCESSED_FILE ${CMAKE_BINARY_DIR}/image_macros_preprocessed.c)
+	string(CONCAT CONTENT_FOR_PREPROCESSING ${PARTIAL_CONTENT_FOR_PREPROCESSING}
+			"\tRE_SIGN_BIN_SIZE = FLASH_AREA_0_SIZE,\n}\;")
+
+	#Create a file that will be preprocessed later in order to be able to handle nested macros
+	#in header files for certain macros
+	file(WRITE ${FILE_TO_PREPROCESS} ${CONTENT_FOR_PREPROCESSING})
+
+	#Preprocess the .c file that contains the image related macros
+	compiler_preprocess_file(SRC ${FILE_TO_PREPROCESS}
+							DST ${PREPROCESSED_FILE}
+							BEFORE_TARGET ${_MY_PARAMS_NS_BIN}
+							TARGET_PREFIX ${_MY_PARAMS_NS_BIN}
+							DEFINES "MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}")
+
+	add_custom_command(TARGET ${_MY_PARAMS_NS_BIN}
+						POST_BUILD
+						#Create concatenated binary image from the two binary file
+						COMMAND ${PYTHON_EXECUTABLE} ${MCUBOOT_DIR}/scripts/assemble.py
+						ARGS --layout ${PREPROCESSED_FILE}
+							 -s $/${_MY_PARAMS_S_BIN}.bin
+							 -n $/${_MY_PARAMS_NS_BIN}.bin
+							 -o ${CMAKE_BINARY_DIR}/${_MY_PARAMS_FULL_BIN}.bin
+
+						#Sign concatenated binary image with default public key in mcuboot folder
+						COMMAND ${PYTHON_EXECUTABLE} ${MCUBOOT_DIR}/scripts/imgtool.py
+						ARGS sign
+							 --layout ${PREPROCESSED_FILE}
+							 -k ${KEY_FILE}
+							 --public-key-format ${PUBLIC_KEY_FORMAT}
+							 --align 1
+							 -v ${IMAGE_VERSION}
+							 ${ADD_SECURITY_COUNTER}
+							 -H 0x400
+							 ${CMAKE_BINARY_DIR}/${_MY_PARAMS_FULL_BIN}.bin
+							 ${CMAKE_BINARY_DIR}/${_MY_PARAMS_SIGN_BIN}.bin)
+endif()
+
+	#Collect executables to common location: build/install/outputs/
+	set(TFM_SIGN_NAME tfm_s_ns_signed)
+
+	if (DEFINED MY_POSTFIX)
+		install(FILES  ${CMAKE_BINARY_DIR}/${_MY_PARAMS_SIGN_BIN}.bin
+				RENAME tfm_sig${MY_POSTFIX}.bin
+				DESTINATION outputs/${TARGET_PLATFORM}/)
+	else()
+		install(FILES ${CMAKE_BINARY_DIR}/${_MY_PARAMS_SIGN_BIN}.bin
+				DESTINATION outputs/${TARGET_PLATFORM}/)
+	endif()
+
+	install(FILES  ${CMAKE_BINARY_DIR}/${_MY_PARAMS_SIGN_BIN}.bin
+			RENAME ${TFM_SIGN_NAME}${_MY_PARAMS_POSTFIX}.bin
+			DESTINATION outputs/fvp/)
+
+if (MCUBOOT_IMAGE_NUMBER GREATER 1)
+	install(FILES ${CMAKE_BINARY_DIR}/${_MY_PARAMS_S_BIN}_signed.bin
+			${CMAKE_BINARY_DIR}/${_MY_PARAMS_NS_BIN}_signed.bin
+			DESTINATION outputs/${TARGET_PLATFORM}/)
+	install(FILES ${CMAKE_BINARY_DIR}/${_MY_PARAMS_S_BIN}_signed.bin
+			${CMAKE_BINARY_DIR}/${_MY_PARAMS_NS_BIN}_signed.bin
+			DESTINATION outputs/fvp/)
+
+else() # MCUBOOT_IMAGE_NUMBER = 1
+	set(TFM_FULL_NAME tfm_s_ns_concatenated)
+
+	install(FILES  ${CMAKE_BINARY_DIR}/${_MY_PARAMS_FULL_BIN}.bin
+			DESTINATION outputs/${TARGET_PLATFORM}/)
+	install(FILES  ${CMAKE_BINARY_DIR}/${_MY_PARAMS_FULL_BIN}.bin
+			RENAME ${TFM_FULL_NAME}${_MY_PARAMS_POSTFIX}.bin
+			DESTINATION outputs/fvp/)
+endif()
+endfunction()
+
+#Validate and override the upgrade strategy to be used by the bootloader.
+#
+# If the given upgrade strategy is not supported with the current value
+# of the MCUBOOT_IMAGE_NUMBER variable then the function will override its
+# previously set value.
+#
+#Examples:
+#  mcuboot_override_upgrade_strategy("SWAP")
+#
+#INPUTS:
+#  strategy - (mandatory) - Upgrade strategy to be used.
+#
+#OUTPUTS:
+#  MCUBOOT_UPGRADE_STRATEGY variable is set to the new strategy.
+#
+function(mcuboot_override_upgrade_strategy strategy)
+	if ((${strategy} STREQUAL "NO_SWAP" OR
+		 ${strategy} STREQUAL "RAM_LOADING") AND
+		NOT (MCUBOOT_IMAGE_NUMBER EQUAL 1))
+		message(WARNING "The number of separately updatable images with the NO_SWAP or the RAM_LOADING"
+			" upgrade strategy can be only '1'. Your choice was overriden.")
+		set(MCUBOOT_IMAGE_NUMBER 1 PARENT_SCOPE)
+	endif()
+	get_property(_validation_list CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS)
+	#Check if validation list is set.
+	if (NOT _validation_list)
+		#Set the default upgrade strategy if the CACHE variable has not been set yet.
+		set(MCUBOOT_UPGRADE_STRATEGY "OVERWRITE_ONLY" CACHE STRING "Configure BL2 which upgrade strategy to use")
+		if (MCUBOOT_REPO STREQUAL "TF-M")
+			set_property(CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS "OVERWRITE_ONLY;SWAP;NO_SWAP;RAM_LOADING")
+		else()
+			set_property(CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS "OVERWRITE_ONLY;SWAP")
+		endif()
+	endif()
+	set(MCUBOOT_UPGRADE_STRATEGY ${strategy} PARENT_SCOPE)
+	validate_cache_value(MCUBOOT_UPGRADE_STRATEGY STRINGS)
+endfunction()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBootConfig.cmake b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBootConfig.cmake
new file mode 100644
index 0000000000..f421ee6944
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/MCUBootConfig.cmake
@@ -0,0 +1,116 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#Include BL2 bootloader related functions
+include("${CMAKE_CURRENT_LIST_DIR}/MCUBoot.cmake")
+
+set(BL2 True CACHE BOOL "Configure TF-M to use BL2 and enable building BL2")
+
+if (BL2)
+	add_definitions(-DBL2)
+
+	set(MCUBOOT_REPO "TF-M" CACHE STRING "Configure which repository use the MCUBoot from")
+	set_property(CACHE MCUBOOT_REPO PROPERTY STRINGS "TF-M;UPSTREAM")
+	validate_cache_value(MCUBOOT_REPO)
+
+	set(MCUBOOT_IMAGE_NUMBER 2 CACHE STRING "Configure the number of separately updatable firmware images")
+	set_property(CACHE MCUBOOT_IMAGE_NUMBER PROPERTY STRINGS "1;2")
+	validate_cache_value(MCUBOOT_IMAGE_NUMBER STRINGS)
+
+	set(MCUBOOT_UPGRADE_STRATEGY "OVERWRITE_ONLY" CACHE STRING "Configure BL2 which upgrade strategy to use")
+	set_property(CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS "OVERWRITE_ONLY;SWAP;NO_SWAP;RAM_LOADING")
+	validate_cache_value(MCUBOOT_UPGRADE_STRATEGY)
+
+	set(MCUBOOT_SIGNATURE_TYPE "RSA-3072" CACHE STRING "Algorithm used by MCUBoot to validate signatures.")
+	set_property(CACHE MCUBOOT_SIGNATURE_TYPE PROPERTY STRINGS "RSA-3072;RSA-2048")
+	validate_cache_value(MCUBOOT_SIGNATURE_TYPE)
+
+	if (MCUBOOT_REPO STREQUAL "TF-M")
+		set(MCUBOOT_HW_KEY On CACHE BOOL "Configure to use HW key for image verification. Otherwise key is embedded in MCUBoot image.")
+	else() #Using upstream MCUBoot
+		if (MCUBOOT_HW_KEY)
+			message(WARNING "Cannot use HW key for image verification when building against upstream MCUBoot."
+				" Your choice was overriden (MCUBOOT_HW_KEY=Off).")
+		endif()
+		set(MCUBOOT_HW_KEY Off)
+	endif()
+
+	set(MCUBOOT_LOG_LEVEL "LOG_LEVEL_INFO" CACHE STRING "Configure the level of logging in MCUBoot.")
+	set_property(CACHE MCUBOOT_LOG_LEVEL PROPERTY STRINGS "LOG_LEVEL_OFF;LOG_LEVEL_ERROR;LOG_LEVEL_WARNING;LOG_LEVEL_INFO;LOG_LEVEL_DEBUG")
+	if (NOT CMAKE_BUILD_TYPE STREQUAL "debug")
+		set(MCUBOOT_LOG_LEVEL "LOG_LEVEL_OFF")
+	endif()
+	validate_cache_value(MCUBOOT_LOG_LEVEL)
+
+	if ((${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "NO_SWAP" OR
+		 ${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "RAM_LOADING") AND
+		NOT (MCUBOOT_IMAGE_NUMBER EQUAL 1))
+		message(WARNING "The number of separately updatable images with the NO_SWAP or the RAM_LOADING"
+			" upgrade strategy can be only '1'. Your choice was overriden.")
+		set(MCUBOOT_IMAGE_NUMBER 1)
+	endif()
+
+	if (MCUBOOT_REPO STREQUAL "UPSTREAM")
+		set_property(CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS "OVERWRITE_ONLY;SWAP")
+		if (${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "NO_SWAP" OR
+			${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "RAM_LOADING")
+			message(WARNING "The ${MCUBOOT_UPGRADE_STRATEGY} upgrade strategy cannot be used when building against"
+				" upstream MCUBoot. Your choice was overriden.")
+			mcuboot_override_upgrade_strategy("OVERWRITE_ONLY")
+		endif()
+
+		if (DEFINED SECURITY_COUNTER OR
+			DEFINED SECURITY_COUNTER_S OR
+			DEFINED SECURITY_COUNTER_NS)
+				message(WARNING "Ignoring the values of SECURITY_COUNTER and/or SECURITY_COUNTER_* variables as"
+					" upstream MCUBoot does not support rollback protection.")
+				set(SECURITY_COUNTER "")
+				set(SECURITY_COUNTER_S "")
+				set(SECURITY_COUNTER_NS "")
+		endif()
+
+	endif()
+
+else() #BL2 is turned off
+
+	if (DEFINED MCUBOOT_IMAGE_NUMBER OR
+		DEFINED MCUBOOT_UPGRADE_STRATEGY OR
+		DEFINED MCUBOOT_SIGNATURE_TYPE OR
+		DEFINED MCUBOOT_HW_KEY OR
+		DEFINED MCUBOOT_LOG_LEVEL)
+			message(WARNING "Ignoring the values of MCUBOOT_* variables as BL2 option is set to False.")
+			set(MCUBOOT_IMAGE_NUMBER "")
+			set(MCUBOOT_UPGRADE_STRATEGY "")
+			set(MCUBOOT_SIGNATURE_TYPE "")
+			set(MCUBOOT_HW_KEY "")
+			set(MCUBOOT_LOG_LEVEL "")
+	endif()
+
+	if (DEFINED SECURITY_COUNTER OR
+		DEFINED SECURITY_COUNTER_S OR
+		DEFINED SECURITY_COUNTER_NS)
+			message(WARNING "Ignoring the values of SECURITY_COUNTER and/or SECURITY_COUNTER_* variables as BL2 option is set to False.")
+			set(SECURITY_COUNTER "")
+			set(SECURITY_COUNTER_S "")
+			set(SECURITY_COUNTER_NS "")
+	endif()
+
+	if (DEFINED IMAGE_VERSION OR
+		DEFINED IMAGE_VERSION_S OR
+		DEFINED IMAGE_VERSION_NS)
+			message(WARNING "Ignoring the values of IMAGE_VERSION and/or IMAGE_VERSION_* variables as BL2 option is set to False.")
+			set(IMAGE_VERSION "")
+			set(IMAGE_VERSION_S "")
+			set(IMAGE_VERSION_NS "")
+	endif()
+	if (DEFINED S_IMAGE_MIN_VER OR
+		DEFINED NS_IMAGE_MIN_VER)
+			message(WARNING "Ignoring the values of *_IMAGE_MIN_VER variables as BL2 option is set to False.")
+			set(S_IMAGE_MIN_VER "")
+			set(NS_IMAGE_MIN_VER "")
+	endif()
+endif()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bl2_main.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bl2_main.c
new file mode 100644
index 0000000000..b7d911c73b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bl2_main.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2012-2014 Wind River Systems, Inc.
+ * Copyright (c) 2017-2020 Arm Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include 
+#include "bl2_util.h"
+#include "target.h"
+//#include "tfm_hal_device_header.h"
+#include "Driver_Flash.h"
+#include "mbedtls/memory_buffer_alloc.h"
+#include "bootutil/bootutil_log.h"
+#include "bootutil/image.h"
+#include "bootutil/bootutil.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "boot_record.h"
+#include "security_cnt.h"
+#include "boot_hal.h"
+#include "memory_buffer_alloc.h"
+#if MCUBOOT_LOG_LEVEL > MCUBOOT_LOG_LEVEL_OFF
+#include "uart_stdout.h"
+#endif
+#if defined(CRYPTO_HW_ACCELERATOR) || \
+    defined(CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING)
+#include "crypto_hw.h"
+#endif
+
+/* Avoids the semihosting issue */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+__asm("  .global __ARM_use_no_argv\n");
+#endif
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+/* Macros to pick linker symbols */
+#define REGION(a, b, c) a##b##c
+#define REGION_NAME(a, b, c) REGION(a, b, c)
+#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
+
+REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+#endif
+
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+#define BL2_MBEDTLS_MEM_BUF_LEN 0x2000
+/* Static buffer to be used by mbedtls for memory allocation */
+static uint8_t mbedtls_mem_buf[BL2_MBEDTLS_MEM_BUF_LEN];
+
+struct arm_vector_table {
+    uint32_t msp;
+    uint32_t reset;
+};
+
+/*!
+ * \brief Chain-loading the next image in the boot sequence.
+ *
+ * This function calls the Reset_Handler of the next image in the boot sequence,
+ * usually it is the secure firmware. Before passing the execution to next image
+ * there is conditional rule to remove the secrets from the memory. This must be
+ * done if the following conditions are satisfied:
+ *  - Memory is shared between SW components at different stages of the trusted
+ *    boot process.
+ *  - There are secrets in the memory: KDF parameter, symmetric key,
+ *    manufacturer sensitive code/data, etc.
+ */
+__attribute__((naked)) void boot_jump_to_next_image(uint32_t reset_handler_addr)
+{
+    __ASM volatile(
+        ".syntax unified                 \n"
+        "mov     r7, r0                  \n"
+        "bl      boot_clear_bl2_ram_area \n" /* Clear RAM before jump */
+        "movs    r0, #0                  \n" /* Clear registers: R0-R12, */
+        "mov     r1, r0                  \n" /* except R7 */
+        "mov     r2, r0                  \n"
+        "mov     r3, r0                  \n"
+        "mov     r4, r0                  \n"
+        "mov     r5, r0                  \n"
+        "mov     r6, r0                  \n"
+        "mov     r8, r0                  \n"
+        "mov     r9, r0                  \n"
+        "mov     r10, r0                 \n"
+        "mov     r11, r0                 \n"
+        "mov     r12, r0                 \n"
+        "mov     lr,  r0                 \n"
+        "bx      r7                      \n" /* Jump to Reset_handler */
+    );
+}
+
+static void do_boot(struct boot_rsp *rsp)
+{
+    /* Clang at O0, stores variables on the stack with SP relative addressing.
+     * When manually set the SP then the place of reset vector is lost.
+     * Static variables are stored in 'data' or 'bss' section, change of SP has
+     * no effect on them.
+     */
+    static struct arm_vector_table *vt;
+    uintptr_t flash_base;
+    int rc;
+
+    /* The beginning of the image is the ARM vector table, containing
+     * the initial stack pointer address and the reset vector
+     * consecutively. Manually set the stack pointer and jump into the
+     * reset vector
+     */
+    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
+    assert(rc == 0);
+
+    if (rsp->br_hdr->ih_flags & IMAGE_F_RAM_LOAD) {
+       /* The image has been copied to SRAM, find the vector table
+        * at the load address instead of image's address in flash
+        */
+        vt = (struct arm_vector_table *)(rsp->br_hdr->ih_load_addr +
+                                         rsp->br_hdr->ih_hdr_size);
+    } else {
+        /* Using the flash address as not executing in SRAM */
+        vt = (struct arm_vector_table *)(flash_base +
+                                         rsp->br_image_off +
+                                         rsp->br_hdr->ih_hdr_size);
+    }
+
+    rc = FLASH_DEV_NAME.Uninitialize();
+    if(rc != ARM_DRIVER_OK) {
+        BOOT_LOG_ERR("Error while uninitializing Flash Interface");
+    }
+
+#if MCUBOOT_LOG_LEVEL > MCUBOOT_LOG_LEVEL_OFF
+    stdio_uninit();
+#endif
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+    /* Restore the Main Stack Pointer Limit register's reset value
+     * before passing execution to runtime firmware to make the
+     * bootloader transparent to it.
+     */
+    __set_MSPLIM(0);
+#endif
+#if defined(__ARMCC_VERSION)
+    __set_MSP(vt->msp);
+    __DSB();
+    __ISB();
+
+    boot_jump_to_next_image(vt->reset);
+#else
+    SCB->VTOR = ((int)(&(vt->msp)) & 0x1FFFFF80);
+    __DSB();
+
+    /* Disable MSP monitoring  */
+    R_MPU_SPMON->SP[0].CTL = 0;
+    while(R_MPU_SPMON->SP[0].CTL != 0);
+
+    __set_MSP(vt->msp);
+
+    ((void (*)()) vt->reset)();
+#endif
+}
+
+int bl2_main(void)
+{
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+    uint32_t msp_stack_bottom =
+            (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+#endif
+    struct boot_rsp rsp;
+    int rc = ARM_DRIVER_OK;;
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+    __set_MSPLIM(msp_stack_bottom);
+#endif
+
+#if MCUBOOT_LOG_LEVEL > MCUBOOT_LOG_LEVEL_OFF
+    stdio_init();
+#endif
+
+    BOOT_LOG_INF("Starting bootloader");
+
+    /* Perform platform specific initialization */
+    if (boot_platform_init() != 0) {
+        while (1)
+            ;
+    }
+    /* Initialise the mbedtls static memory allocator so that mbedtls allocates
+     * memory from the provided static buffer instead of from the heap.
+     */
+    mbedtls_memory_buffer_alloc_init(mbedtls_mem_buf, BL2_MBEDTLS_MEM_BUF_LEN);
+
+#ifdef CRYPTO_HW_ACCELERATOR
+    rc = crypto_hw_accelerator_init();
+    if (rc) {
+        BOOT_LOG_ERR("Error while initializing cryptographic accelerator.");
+        while (1);
+    }
+#endif /* CRYPTO_HW_ACCELERATOR */
+
+#ifndef MCUBOOT_USE_UPSTREAM
+    rc = boot_nv_security_counter_init();
+    if (rc != 0) {
+        BOOT_LOG_ERR("Error while initializing the security counter");
+        while (1)
+            ;
+    }
+#endif /* !MCUBOOT_USE_UPSTREAM */
+
+    rc = boot_go(&rsp);
+    if (rc != 0) {
+        BOOT_LOG_ERR("Unable to find bootable image");
+        while (1)
+            ;
+    }
+
+#ifdef CRYPTO_HW_ACCELERATOR
+    rc = crypto_hw_accelerator_finish();
+    if (rc) {
+        BOOT_LOG_ERR("Error while uninitializing cryptographic accelerator.");
+        while (1);
+    }
+#endif /* CRYPTO_HW_ACCELERATOR */
+
+/* This is a workaround to program the TF-M related cryptographic keys
+ * to CC312 OTP memory. This functionality is independent from secure boot,
+ * this is usually done in the factory floor during chip manufacturing.
+ */
+#ifdef CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING
+    BOOT_LOG_INF("OTP provisioning started.");
+    rc = crypto_hw_accelerator_otp_provisioning();
+    if (rc) {
+        BOOT_LOG_ERR("OTP provisioning FAILED: 0x%X", rc);
+        while (1);
+    } else {
+        BOOT_LOG_INF("OTP provisioning succeeded. TF-M won't be loaded.");
+
+        /* We don't need to boot - the only aim is provisioning. */
+        while (1);
+    }
+#endif /* CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING */
+
+    BOOT_LOG_INF("Bootloader chainload address offset: 0x%x",
+                 rsp.br_image_off);
+    BOOT_LOG_INF("Jumping to the first image slot");
+    do_boot(&rsp);
+
+    BOOT_LOG_ERR("Never should get here");
+    while (1)
+        ;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil.h
new file mode 100644
index 0000000000..92a9efc1da
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil.h
@@ -0,0 +1,107 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BOOTUTIL_
+#define H_BOOTUTIL_
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Attempt to boot the contents of the primary slot. */
+#define BOOT_SWAP_TYPE_NONE     1
+
+/**
+ * Swap to the secondary slot.
+ * Absent a confirm command, revert back on next boot.
+ */
+#define BOOT_SWAP_TYPE_TEST     2
+
+/**
+ * Swap to the secondary slot,
+ * and permanently switch to booting its contents.
+ */
+#define BOOT_SWAP_TYPE_PERM     3
+
+/** Swap back to alternate slot.  A confirm changes this state to NONE. */
+#define BOOT_SWAP_TYPE_REVERT   4
+
+/** Swap failed because image to be run is not valid */
+#define BOOT_SWAP_TYPE_FAIL     5
+
+/** Swapping encountered an unrecoverable error */
+#define BOOT_SWAP_TYPE_PANIC    0xff
+
+#define BOOT_MAX_ALIGN          8
+
+struct image_header;
+/**
+ * A response object provided by the boot loader code; indicates where to jump
+ * to execute the main image.
+ */
+struct boot_rsp {
+    /** A pointer to the header of the image to be executed. */
+    const struct image_header *br_hdr;
+
+    /**
+     * The flash offset of the image to execute.  Indicates the position of
+     * the image header within its flash device.
+     */
+    uint8_t br_flash_dev_id;
+    uint32_t br_image_off;
+};
+
+/* This is not actually used by mcuboot's code but can be used by apps
+ * when attempting to read/write a trailer.
+ */
+struct image_trailer {
+    uint8_t swap_type;
+    uint8_t pad1[BOOT_MAX_ALIGN - 1];
+    uint8_t copy_done;
+    uint8_t pad2[BOOT_MAX_ALIGN - 1];
+    uint8_t image_ok;
+    uint8_t pad3[BOOT_MAX_ALIGN - 1];
+    uint8_t magic[16];
+};
+
+/* you must have pre-allocated all the entries within this structure */
+int boot_go(struct boot_rsp *rsp);
+
+struct boot_loader_state;
+int context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp);
+
+int boot_swap_type_multi(int image_index);
+int boot_swap_type(void);
+
+int boot_set_pending(int permanent);
+int boot_set_confirmed(void);
+
+#define SPLIT_GO_OK                 (0)
+#define SPLIT_GO_NON_MATCHING       (-1)
+#define SPLIT_GO_ERR                (-2)
+int
+split_go(int loader_slot, int split_slot, void **entry);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_log.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_log.h
new file mode 100644
index 0000000000..c7bb70f318
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_log.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef H_BOOTUTIL_LOG_H_
+#define H_BOOTUTIL_LOG_H_
+
+#include "ignore.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+#ifdef MCUBOOT_HAVE_LOGGING
+
+#define BOOT_LOG_ERR(...) MCUBOOT_LOG_ERR(__VA_ARGS__)
+#define BOOT_LOG_WRN(...) MCUBOOT_LOG_WRN(__VA_ARGS__)
+#define BOOT_LOG_INF(...) MCUBOOT_LOG_INF(__VA_ARGS__)
+#define BOOT_LOG_DBG(...) MCUBOOT_LOG_DBG(__VA_ARGS__)
+
+#else
+
+#define BOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
+#define BOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
+#define BOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
+#define BOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
+
+#endif /* MCUBOOT_HAVE_LOGGING */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_test.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_test.h
new file mode 100644
index 0000000000..4188bb1c51
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/bootutil_test.h
@@ -0,0 +1,33 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ * 
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BOOTUTIL_TEST_
+#define H_BOOTUTIL_TEST_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int boot_test_all(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/ignore.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/ignore.h
new file mode 100644
index 0000000000..4cc5430e26
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/ignore.h
@@ -0,0 +1,64 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_IGNORE_
+#define H_IGNORE_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * These macros prevent the "set but not used" warnings for log writes below
+ * the log level.
+ */
+
+#define IGN_1(X) ((void)(X))
+#define IGN_2(X, ...)  ((void)(X)); IGN_1(__VA_ARGS__)
+#define IGN_3(X, ...)  ((void)(X)); IGN_2(__VA_ARGS__)
+#define IGN_4(X, ...)  ((void)(X)); IGN_3(__VA_ARGS__)
+#define IGN_5(X, ...)  ((void)(X)); IGN_4(__VA_ARGS__)
+#define IGN_6(X, ...)  ((void)(X)); IGN_5(__VA_ARGS__)
+#define IGN_7(X, ...)  ((void)(X)); IGN_6(__VA_ARGS__)
+#define IGN_8(X, ...)  ((void)(X)); IGN_7(__VA_ARGS__)
+#define IGN_9(X, ...)  ((void)(X)); IGN_8(__VA_ARGS__)
+#define IGN_10(X, ...) ((void)(X)); IGN_9(__VA_ARGS__)
+#define IGN_11(X, ...) ((void)(X)); IGN_10(__VA_ARGS__)
+#define IGN_12(X, ...) ((void)(X)); IGN_11(__VA_ARGS__)
+#define IGN_13(X, ...) ((void)(X)); IGN_12(__VA_ARGS__)
+#define IGN_14(X, ...) ((void)(X)); IGN_13(__VA_ARGS__)
+#define IGN_15(X, ...) ((void)(X)); IGN_14(__VA_ARGS__)
+#define IGN_16(X, ...) ((void)(X)); IGN_15(__VA_ARGS__)
+#define IGN_17(X, ...) ((void)(X)); IGN_16(__VA_ARGS__)
+#define IGN_18(X, ...) ((void)(X)); IGN_17(__VA_ARGS__)
+#define IGN_19(X, ...) ((void)(X)); IGN_18(__VA_ARGS__)
+#define IGN_20(X, ...) ((void)(X)); IGN_19(__VA_ARGS__)
+
+#define GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, \
+                  _13, _14, _15, _16, _17, _18, _19, _20, NAME, ...) NAME
+#define IGNORE(...) \
+    GET_MACRO(__VA_ARGS__, IGN_20, IGN_19, IGN_18, IGN_17, IGN_16, IGN_15, \
+              IGN_14, IGN_13, IGN_12, IGN_11, IGN_10, IGN_9, IGN_8, IGN_7, \
+              IGN_6, IGN_5, IGN_4, IGN_3, IGN_2, IGN_1)(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/image.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/image.h
new file mode 100644
index 0000000000..a3ebf915c3
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/image.h
@@ -0,0 +1,160 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2019 Arm Limited.
+ */
+
+#ifndef H_IMAGE_
+#define H_IMAGE_
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct flash_area;
+
+#define IMAGE_MAGIC                 0x96f3b83d
+#define IMAGE_MAGIC_V1              0x96f3b83c
+#define IMAGE_MAGIC_NONE            0xffffffff
+#define IMAGE_TLV_INFO_MAGIC        0x6907
+#define IMAGE_TLV_PROT_INFO_MAGIC   0x6908
+
+#define IMAGE_HEADER_SIZE           32
+
+/*
+ * Image header flags.
+ */
+#define IMAGE_F_PIC                      0x00000001 /* Not supported. */
+#define IMAGE_F_NON_BOOTABLE             0x00000010 /* Split image app. */
+/*
+ * Indicates that this image should be loaded into RAM instead of run
+ * directly from flash.  The address to load should be in the
+ * ih_load_addr field of the header.
+ */
+#define IMAGE_F_RAM_LOAD                 0x00000020
+
+/*
+ * Image trailer TLV types.
+ *
+ * Signature is generated by computing signature over the image hash.
+ * Currently the only image hash type is SHA256.
+ *
+ * Signature comes in the form of 2 TLVs.
+ *   1st on identifies the public key which should be used to verify it.
+ *   2nd one is the actual signature.
+ */
+#define IMAGE_TLV_KEYHASH           0x01   /* hash of the public key */
+#define IMAGE_TLV_KEY               0x02   /* public key */
+#define IMAGE_TLV_SHA256            0x10   /* SHA256 of image hdr and body */
+#define IMAGE_TLV_RSA2048_PSS       0x20   /* RSA2048 of hash output */
+#define IMAGE_TLV_RSA3072_PSS       0x23   /* RSA3072 of hash output */
+#define IMAGE_TLV_DEPENDENCY        0x40   /* Image depends on other image */
+#define IMAGE_TLV_SEC_CNT           0x50   /* security counter */
+#define IMAGE_TLV_BOOT_RECORD       0x60   /* measured boot record */
+#define IMAGE_TLV_ANY               0xff   /* Used to iterate over all TLV */
+
+#define IMAGE_VER_MAJOR_LENGTH      8
+#define IMAGE_VER_MINOR_LENGTH      8
+#define IMAGE_VER_REVISION_LENGTH   16
+#define IMAGE_VER_BUILD_NUM_LENGTH  32
+
+struct image_version {
+    uint8_t iv_major;
+    uint8_t iv_minor;
+    uint16_t iv_revision;
+    uint32_t iv_build_num;
+};
+
+struct image_dependency {
+    uint8_t image_id;                       /* Image index (from 0) */
+    uint8_t _pad1;
+    uint16_t _pad2;
+    struct image_version image_min_version; /* Indicates at minimum which
+                                             * version of firmware must be
+                                             * available to satisfy compliance
+                                             */
+};
+
+/** Image header.  All fields are in little endian byte order. */
+struct image_header {
+    uint32_t ih_magic;
+    uint32_t ih_load_addr;
+    uint16_t ih_hdr_size;           /* Size of image header (bytes). */
+    uint16_t ih_protect_tlv_size;   /* Size of protected TLV area (bytes). */
+    uint32_t ih_img_size;           /* Does not include header. */
+    uint32_t ih_flags;              /* IMAGE_F_[...]. */
+    struct image_version ih_ver;
+    uint32_t _pad1;
+};
+
+/** Image TLV header.  All fields in little endian. */
+struct image_tlv_info {
+    uint16_t it_magic;
+    uint16_t it_tlv_tot;  /* size of TLV area (including tlv_info header) */
+};
+
+/** Image trailer TLV format. All fields in little endian. */
+struct image_tlv {
+    uint8_t  it_type;   /* IMAGE_TLV_[...]. */
+    uint8_t  _pad;
+    uint16_t it_len;    /* Data length (not including TLV header). */
+};
+
+_Static_assert(sizeof(struct image_header) == IMAGE_HEADER_SIZE,
+               "struct image_header not required size");
+
+int bootutil_img_validate(int image_index,
+                          struct image_header *hdr,
+                          const struct flash_area *fap,
+                          uint8_t *tmp_buf, uint32_t tmp_buf_sz,
+                          uint8_t *seed, int seed_len, uint8_t *out_hash);
+
+struct image_tlv_iter {
+    const struct image_header *hdr;
+    const struct flash_area *fap;
+    uint8_t type;
+    bool prot;
+    uint32_t prot_end;
+    uint32_t tlv_off;
+    uint32_t tlv_end;
+};
+
+int bootutil_tlv_iter_begin(struct image_tlv_iter *it,
+                            const struct image_header *hdr,
+                            const struct flash_area *fap, uint8_t type,
+                            bool prot);
+int bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off,
+                           uint16_t *len, uint8_t *type);
+
+int32_t bootutil_get_img_security_cnt(struct image_header *hdr,
+                                      const struct flash_area *fap,
+                                      uint32_t *security_cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sha256.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sha256.h
new file mode 100644
index 0000000000..545621e94e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sha256.h
@@ -0,0 +1,70 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * This module provides a thin abstraction over some of the crypto
+ * primitives to make it easier to swap out the used crypto library.
+ *
+ * At this point, only Mbed Crypto is supported.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2019 Arm Limited.
+ */
+
+#ifndef __BOOTUTIL_CRYPTO_H_
+#define __BOOTUTIL_CRYPTO_H_
+
+#include "mbedtls/sha256.h"
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef mbedtls_sha256_context bootutil_sha256_context;
+
+static inline void bootutil_sha256_init(bootutil_sha256_context *ctx)
+{
+    mbedtls_sha256_init(ctx);
+    (void)mbedtls_sha256_starts_ret(ctx, 0);
+}
+
+static inline void bootutil_sha256_update(bootutil_sha256_context *ctx,
+                                          const void *data,
+                                          uint32_t data_len)
+{
+    (void)mbedtls_sha256_update_ret(ctx, data, data_len);
+}
+
+static inline void bootutil_sha256_finish(bootutil_sha256_context *ctx,
+                                          uint8_t *output)
+{
+    (void)mbedtls_sha256_finish_ret(ctx, output);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOTUTIL_SIGN_KEY_H_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sign_key.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sign_key.h
new file mode 100644
index 0000000000..b0c1f2133f
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/include/bootutil/sign_key.h
@@ -0,0 +1,51 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __BOOTUTIL_SIGN_KEY_H_
+#define __BOOTUTIL_SIGN_KEY_H_
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef MCUBOOT_HW_KEY
+struct bootutil_key {
+    uint8_t *key;
+    unsigned int *len;
+};
+
+extern struct bootutil_key bootutil_keys[];
+#else
+struct bootutil_key {
+    const uint8_t *key;
+    const unsigned int *len;
+};
+
+extern const struct bootutil_key bootutil_keys[];
+#endif
+
+extern const int bootutil_key_cnt;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOTUTIL_SIGN_KEY_H_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_misc.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_misc.c
new file mode 100644
index 0000000000..812443aa3e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_misc.c
@@ -0,0 +1,701 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2019-2020 Arm Limited.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "flash_map_backend/flash_map_backend.h"
+
+#include "bootutil/image.h"
+#include "bootutil/bootutil.h"
+#include "bootutil_priv.h"
+#include "bootutil/bootutil_log.h"
+
+/* Currently only used by imgmgr */
+int boot_current_slot;
+
+const uint32_t boot_img_magic[] = {
+    0xf395c277,
+    0x7fefd260,
+    0x0f505235,
+    0x8079b62c,
+};
+
+#define BOOT_MAGIC_ARR_SZ \
+    (sizeof boot_img_magic / sizeof boot_img_magic[0])
+
+struct boot_swap_table {
+    uint8_t magic_primary_slot;
+    uint8_t magic_secondary_slot;
+    uint8_t image_ok_primary_slot;
+    uint8_t image_ok_secondary_slot;
+    uint8_t copy_done_primary_slot;
+
+    uint8_t swap_type;
+};
+
+/**
+ * This set of tables maps image trailer contents to swap operation type.
+ * When searching for a match, these tables must be iterated sequentially.
+ *
+ * NOTE: the table order is very important. The settings in the secondary
+ * slot always are priority to the primary slot and should be located
+ * earlier in the table.
+ *
+ * The table lists only states where there is action needs to be taken by
+ * the bootloader, as in starting/finishing a swap operation.
+ */
+static const struct boot_swap_table boot_swap_tables[] = {
+    {
+        .magic_primary_slot =       BOOT_MAGIC_ANY,
+        .magic_secondary_slot =     BOOT_MAGIC_GOOD,
+        .image_ok_primary_slot =    BOOT_FLAG_ANY,
+        .image_ok_secondary_slot =  BOOT_FLAG_UNSET,
+        .copy_done_primary_slot =   BOOT_FLAG_ANY,
+        .swap_type =                BOOT_SWAP_TYPE_TEST,
+    },
+    {
+        .magic_primary_slot =       BOOT_MAGIC_ANY,
+        .magic_secondary_slot =     BOOT_MAGIC_GOOD,
+        .image_ok_primary_slot =    BOOT_FLAG_ANY,
+        .image_ok_secondary_slot =  BOOT_FLAG_SET,
+        .copy_done_primary_slot =   BOOT_FLAG_ANY,
+        .swap_type =                BOOT_SWAP_TYPE_PERM,
+    },
+    {
+        .magic_primary_slot =       BOOT_MAGIC_GOOD,
+        .magic_secondary_slot =     BOOT_MAGIC_UNSET,
+        .image_ok_primary_slot =    BOOT_FLAG_UNSET,
+        .image_ok_secondary_slot =  BOOT_FLAG_ANY,
+        .copy_done_primary_slot =   BOOT_FLAG_SET,
+        .swap_type =                BOOT_SWAP_TYPE_REVERT,
+    },
+};
+
+#define BOOT_SWAP_TABLES_COUNT \
+    (sizeof(boot_swap_tables) / sizeof(boot_swap_tables[0]))
+
+/**
+ * @brief Determine if the data at two memory addresses is equal
+ *
+ * @param s1    The first memory region to compare.
+ * @param s2    The second memory region to compare.
+ * @param n     The amount of bytes to compare.
+ *
+ * @note        This function does not comply with the specification of memcmp,
+ *              so should not be considered a drop-in replacement.
+ *
+ * @return      0 if memory regions are equal.
+ */
+uint32_t boot_secure_memequal(const void *s1, const void *s2, size_t n)
+{
+    size_t i;
+    uint8_t *s1_p = (uint8_t*) s1;
+    uint8_t *s2_p = (uint8_t*) s2;
+    uint32_t ret = 0;
+
+    for (i = 0; i < n; i++) {
+        ret |= (s1_p[i] ^ s2_p[i]);
+    }
+
+    return ret;
+}
+
+static int
+boot_magic_decode(const uint32_t *magic)
+{
+    if (boot_secure_memequal(magic, boot_img_magic, BOOT_MAGIC_SZ) == 0) {
+        return BOOT_MAGIC_GOOD;
+    }
+    return BOOT_MAGIC_BAD;
+}
+
+static int
+boot_flag_decode(uint8_t flag)
+{
+    if (flag != BOOT_FLAG_SET) {
+        return BOOT_FLAG_BAD;
+    }
+    return BOOT_FLAG_SET;
+}
+
+/**
+ * Determines if a status source table is satisfied by the specified magic
+ * code.
+ *
+ * @param tbl_val               A magic field from a status source table.
+ * @param val                   The magic value in a trailer, encoded as a
+ *                                  BOOT_MAGIC_[...].
+ *
+ * @return                      1 if the two values are compatible;
+ *                              0 otherwise.
+ */
+int
+boot_magic_compatible_check(uint8_t tbl_val, uint8_t val)
+{
+    switch (tbl_val) {
+    case BOOT_MAGIC_ANY:
+        return 1;
+
+    case BOOT_MAGIC_NOTGOOD:
+        return val != BOOT_MAGIC_GOOD;
+
+    default:
+        return tbl_val == val;
+    }
+}
+
+uint32_t
+boot_trailer_sz(uint32_t min_write_sz)
+{
+    return /* state for all sectors */
+           BOOT_STATUS_MAX_ENTRIES * BOOT_STATUS_STATE_COUNT * min_write_sz +
+           /* swap_type + copy_done + image_ok + swap_size */
+           BOOT_MAX_ALIGN * 4 +
+           BOOT_MAGIC_SZ;
+}
+
+int
+boot_status_entries(int image_index, const struct flash_area *fap)
+{
+    if (fap->fa_id == FLASH_AREA_IMAGE_SCRATCH) {
+        return BOOT_STATUS_STATE_COUNT;
+    } else if ((fap->fa_id == FLASH_AREA_IMAGE_PRIMARY(image_index)) ||
+               (fap->fa_id == FLASH_AREA_IMAGE_SECONDARY(image_index))) {
+        return BOOT_STATUS_STATE_COUNT * BOOT_STATUS_MAX_ENTRIES;
+    }
+    return -1;
+}
+
+uint32_t
+boot_status_off(const struct flash_area *fap)
+{
+    uint32_t off_from_end;
+    uint32_t elem_sz;
+
+    elem_sz = flash_area_align(fap);
+
+    off_from_end = boot_trailer_sz(elem_sz);
+
+    assert(off_from_end <= fap->fa_size);
+    return fap->fa_size - off_from_end;
+}
+
+static inline uint32_t
+boot_magic_off(const struct flash_area *fap)
+{
+    return fap->fa_size - BOOT_MAGIC_SZ;
+}
+
+static inline uint32_t
+boot_image_ok_off(const struct flash_area *fap)
+{
+    return boot_magic_off(fap) - BOOT_MAX_ALIGN;
+}
+
+static inline uint32_t
+boot_copy_done_off(const struct flash_area *fap)
+{
+    return boot_image_ok_off(fap) - BOOT_MAX_ALIGN;
+}
+
+uint32_t
+boot_swap_info_off(const struct flash_area *fap)
+{
+    return boot_copy_done_off(fap) - BOOT_MAX_ALIGN;
+}
+
+static inline uint32_t
+boot_swap_size_off(const struct flash_area *fap)
+{
+    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
+}
+
+int
+boot_read_swap_state(const struct flash_area *fap,
+                     struct boot_swap_state *state)
+{
+    uint32_t magic[BOOT_MAGIC_ARR_SZ];
+    uint32_t off;
+    uint8_t swap_info;
+    int rc;
+
+    off = boot_magic_off(fap);
+    rc = flash_area_read_is_empty(fap, off, magic, BOOT_MAGIC_SZ);
+    if (rc < 0) {
+        return BOOT_EFLASH;
+    }
+    if (rc == 1) {
+        state->magic = BOOT_MAGIC_UNSET;
+    } else {
+        state->magic = boot_magic_decode(magic);
+    }
+
+    off = boot_swap_info_off(fap);
+    rc = flash_area_read_is_empty(fap, off, &swap_info, sizeof swap_info);
+    if (rc < 0) {
+        return BOOT_EFLASH;
+    }
+
+    /* Extract the swap type and image number */
+    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
+    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
+
+    if (rc == 1 || state->swap_type > BOOT_SWAP_TYPE_REVERT) {
+        state->swap_type = BOOT_SWAP_TYPE_NONE;
+        state->image_num = 0;
+    }
+
+    off = boot_copy_done_off(fap);
+    rc = flash_area_read_is_empty(fap, off, &state->copy_done,
+            sizeof state->copy_done);
+    if (rc < 0) {
+        return BOOT_EFLASH;
+    }
+    if (rc == 1) {
+        state->copy_done = BOOT_FLAG_UNSET;
+    } else {
+        state->copy_done = boot_flag_decode(state->copy_done);
+    }
+
+    off = boot_image_ok_off(fap);
+    rc = flash_area_read_is_empty(fap, off, &state->image_ok,
+                                  sizeof state->image_ok);
+    if (rc < 0) {
+        return BOOT_EFLASH;
+    }
+    if (rc == 1) {
+        state->image_ok = BOOT_FLAG_UNSET;
+    } else {
+        state->image_ok = boot_flag_decode(state->image_ok);
+    }
+
+    return 0;
+}
+
+/**
+ * Reads the image trailer from the scratch area.
+ */
+int
+boot_read_swap_state_by_id(int flash_area_id, struct boot_swap_state *state)
+{
+    const struct flash_area *fap;
+    int rc;
+
+    rc = flash_area_open(flash_area_id, &fap);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_read_swap_state(fap, state);
+    flash_area_close(fap);
+    return rc;
+}
+
+/**
+ * This functions tries to locate the status area after an aborted swap,
+ * by looking for the magic in the possible locations.
+ *
+ * If the magic is sucessfully found, a flash_area * is returned and it
+ * is the responsibility of the called to close it.
+ *
+ * @returns 0 on success, -1 on errors
+ */
+static int
+boot_find_status(int image_index, const struct flash_area **fap)
+{
+    uint32_t magic[BOOT_MAGIC_ARR_SZ];
+    uint32_t off;
+    uint8_t areas[2] = {
+        FLASH_AREA_IMAGE_PRIMARY(image_index),
+        FLASH_AREA_IMAGE_SCRATCH,
+    };
+    unsigned int i;
+    int rc;
+
+    /*
+     * In the middle a swap, tries to locate the area that is currently
+     * storing a valid magic, first on the primary slot, then on scratch.
+     * Both "slots" can end up being temporary storage for a swap and it
+     * is assumed that if magic is valid then other metadata is too,
+     * because magic is always written in the last step.
+     */
+
+    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
+        rc = flash_area_open(areas[i], fap);
+        if (rc != 0) {
+            return rc;
+        }
+
+        off = boot_magic_off(*fap);
+        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
+        if (rc != 0) {
+            flash_area_close(*fap);
+            return rc;
+        }
+
+        if (boot_secure_memequal(magic, boot_img_magic, BOOT_MAGIC_SZ) == 0) {
+            return 0;
+        }
+
+        flash_area_close(*fap);
+    }
+
+    /* If we got here, no magic was found */
+    return -1;
+}
+
+int
+boot_read_swap_size(int image_index, uint32_t *swap_size)
+{
+    uint32_t off;
+    const struct flash_area *fap;
+    int rc;
+
+    rc = boot_find_status(image_index, &fap);
+    if (rc == 0) {
+        off = boot_swap_size_off(fap);
+        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
+        flash_area_close(fap);
+    }
+
+    return rc;
+}
+
+int
+boot_write_magic(const struct flash_area *fap)
+{
+    uint32_t off;
+    int rc;
+
+    off = boot_magic_off(fap);
+
+    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
+                 fap->fa_id, (unsigned long)off,
+                 (unsigned long)(fap->fa_off + off));
+    rc = flash_area_write(fap, off, boot_img_magic, BOOT_MAGIC_SZ);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    return 0;
+}
+
+/**
+ * Write trailer data; status bytes, swap_size, etc
+ *
+ * @returns 0 on success, != 0 on error.
+ */
+static int
+boot_write_trailer(const struct flash_area *fap, uint32_t off,
+        const uint8_t *inbuf, uint8_t inlen)
+{
+    uint8_t buf[BOOT_MAX_ALIGN];
+    uint8_t align;
+    uint8_t erased_val;
+    int rc;
+
+    align = flash_area_align(fap);
+    if (inlen > BOOT_MAX_ALIGN || align > BOOT_MAX_ALIGN) {
+        return -1;
+    }
+    erased_val = flash_area_erased_val(fap);
+    if (align < inlen) {
+        align = inlen;
+    }
+    memcpy(buf, inbuf, inlen);
+    memset(&buf[inlen], erased_val, align - inlen);
+
+    rc = flash_area_write(fap, off, buf, align);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    return 0;
+}
+
+static int
+boot_write_trailer_flag(const struct flash_area *fap, uint32_t off,
+        uint8_t flag_val)
+{
+    const uint8_t buf[1] = { flag_val };
+    return boot_write_trailer(fap, off, buf, 1);
+}
+
+int
+boot_write_copy_done(const struct flash_area *fap)
+{
+    uint32_t off;
+
+    off = boot_copy_done_off(fap);
+    BOOT_LOG_DBG("writing copy_done; fa_id=%d off=0x%lx (0x%lx)",
+                 fap->fa_id, (unsigned long)off,
+                 (unsigned long)(fap->fa_off + off));
+    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
+}
+
+int
+boot_write_image_ok(const struct flash_area *fap)
+{
+    uint32_t off;
+
+    off = boot_image_ok_off(fap);
+    BOOT_LOG_DBG("writing image_ok; fa_id=%d off=0x%lx (0x%lx)",
+                 fap->fa_id, (unsigned long)off,
+                 (unsigned long)(fap->fa_off + off));
+    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
+}
+
+/**
+ * Writes the specified value to the `swap-type` field of an image trailer.
+ * This value is persisted so that the boot loader knows what swap operation to
+ * resume in case of an unexpected reset.
+ */
+int
+boot_write_swap_info(const struct flash_area *fap, uint8_t swap_type,
+                     uint8_t image_num)
+{
+    uint32_t off;
+    uint8_t swap_info;
+
+    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
+    off = boot_swap_info_off(fap);
+    BOOT_LOG_DBG("writing swap_info; fa_id=%d off=0x%lx (0x%lx), swap_type=0x%x"
+                 " image_num=0x%x",
+                 fap->fa_id, (unsigned long)off,
+                 (unsigned long)(fap->fa_off + off), swap_type, image_num);
+    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
+}
+
+int
+boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size)
+{
+    uint32_t off;
+
+    off = boot_swap_size_off(fap);
+    BOOT_LOG_DBG("writing swap_size; fa_id=%d off=0x%lx (0x%lx)",
+                 fap->fa_id, (unsigned long)off,
+                 (unsigned long)fap->fa_off + off);
+    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
+}
+
+int
+boot_swap_type_multi(int image_index)
+{
+    const struct boot_swap_table *table;
+    struct boot_swap_state primary_slot;
+    struct boot_swap_state secondary_slot;
+    int rc;
+    size_t i;
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
+                                    &primary_slot);
+    if (rc) {
+        return BOOT_SWAP_TYPE_PANIC;
+    }
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
+                                    &secondary_slot);
+    if (rc) {
+        return BOOT_SWAP_TYPE_PANIC;
+    }
+
+    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
+        table = boot_swap_tables + i;
+
+        if (boot_magic_compatible_check(table->magic_primary_slot,
+                                        primary_slot.magic) &&
+            boot_magic_compatible_check(table->magic_secondary_slot,
+                                        secondary_slot.magic) &&
+            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
+                table->image_ok_primary_slot == primary_slot.image_ok) &&
+            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
+                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
+            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
+                table->copy_done_primary_slot == primary_slot.copy_done)) {
+            BOOT_LOG_INF("Swap type: %s",
+                         table->swap_type == BOOT_SWAP_TYPE_TEST   ? "test"   :
+                         table->swap_type == BOOT_SWAP_TYPE_PERM   ? "perm"   :
+                         table->swap_type == BOOT_SWAP_TYPE_REVERT ? "revert" :
+                         "BUG; can't happen");
+            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
+                    table->swap_type != BOOT_SWAP_TYPE_PERM &&
+                    table->swap_type != BOOT_SWAP_TYPE_REVERT) {
+                return BOOT_SWAP_TYPE_PANIC;
+            }
+            return table->swap_type;
+        }
+    }
+
+    BOOT_LOG_INF("Swap type: none");
+    return BOOT_SWAP_TYPE_NONE;
+}
+
+/*
+ * This function is not used by the bootloader itself, but its required API
+ * by external tooling like mcumgr.
+ */
+int
+boot_swap_type(void)
+{
+    return boot_swap_type_multi(0);
+}
+
+/**
+ * Marks the image in the secondary slot as pending.  On the next reboot,
+ * the system will perform a one-time boot of the the secondary slot image.
+ *
+ * @param permanent         Whether the image should be used permanently or
+ *                              only tested once:
+ *                                  0=run image once, then confirm or revert.
+ *                                  1=run image forever.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+int
+boot_set_pending(int permanent)
+{
+    const struct flash_area *fap = NULL;
+    struct boot_swap_state state_secondary_slot;
+    uint8_t swap_type;
+    int rc;
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(0),
+                                    &state_secondary_slot);
+    if (rc != 0) {
+        return rc;
+    }
+
+    switch (state_secondary_slot.magic) {
+    case BOOT_MAGIC_GOOD:
+        /* Swap already scheduled. */
+        return 0;
+
+    case BOOT_MAGIC_UNSET:
+        rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(0), &fap);
+        if (rc != 0) {
+            rc = BOOT_EFLASH;
+        } else {
+            rc = boot_write_magic(fap);
+        }
+
+        if (rc == 0 && permanent) {
+            rc = boot_write_image_ok(fap);
+        }
+
+        if (rc == 0) {
+            if (permanent) {
+                swap_type = BOOT_SWAP_TYPE_PERM;
+            } else {
+                swap_type = BOOT_SWAP_TYPE_TEST;
+            }
+            rc = boot_write_swap_info(fap, swap_type, 0);
+        }
+
+        flash_area_close(fap);
+        return rc;
+
+    case BOOT_MAGIC_BAD:
+        /* The image slot is corrupt.  There is no way to recover, so erase the
+         * slot to allow future upgrades.
+         */
+        rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(0), &fap);
+        if (rc != 0) {
+            return BOOT_EFLASH;
+        }
+
+        flash_area_erase(fap, 0, fap->fa_size);
+        flash_area_close(fap);
+        return BOOT_EBADIMAGE;
+
+    default:
+        assert(0);
+        return BOOT_EBADIMAGE;
+    }
+}
+
+/**
+ * Marks the image in the primary slot as confirmed.  The system will continue
+ * booting into the image in the primary slot until told to boot from a
+ * different slot.
+ *
+ * @return  0 on success; non-zero on failure.
+ */
+int
+boot_set_confirmed(void)
+{
+    const struct flash_area *fap = NULL;
+    struct boot_swap_state state_primary_slot;
+    int rc;
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(0),
+                                    &state_primary_slot);
+    if (rc != 0) {
+        return rc;
+    }
+
+    switch (state_primary_slot.magic) {
+    case BOOT_MAGIC_GOOD:
+        /* Confirm needed; proceed. */
+        break;
+
+    case BOOT_MAGIC_UNSET:
+        /* Already confirmed. */
+        return 0;
+
+    case BOOT_MAGIC_BAD:
+        /* Unexpected state. */
+        return BOOT_EBADVECT;
+    }
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(0), &fap);
+    if (rc) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    if (state_primary_slot.copy_done == BOOT_FLAG_UNSET) {
+        /* Swap never completed.  This is unexpected. */
+        rc = BOOT_EBADVECT;
+        goto done;
+    }
+
+    if (state_primary_slot.image_ok != BOOT_FLAG_UNSET) {
+        /* Already confirmed. */
+        goto done;
+    }
+
+    rc = boot_write_image_ok(fap);
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_priv.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_priv.h
new file mode 100644
index 0000000000..af9e93e868
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/bootutil_priv.h
@@ -0,0 +1,383 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2020 Arm Limited.
+ */
+
+#ifndef H_BOOTUTIL_PRIV_
+#define H_BOOTUTIL_PRIV_
+
+#include 
+#include "flash_map/flash_map.h"
+#include "bootutil/bootutil.h"
+#include "bootutil/image.h"
+#include "flash_layout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef MCUBOOT_HAVE_ASSERT_H
+#include "mcuboot_config/mcuboot_assert.h"
+#else
+#define ASSERT assert
+#endif
+
+struct flash_area;
+
+#define BOOT_EFLASH      1
+#define BOOT_EFILE       2
+#define BOOT_EBADIMAGE   3
+#define BOOT_EBADVECT    4
+#define BOOT_EBADSTATUS  5
+#define BOOT_ENOMEM      6
+#define BOOT_EBADARGS    7
+#define BOOT_EBADVERSION 8
+#define BOOT_EBADMAGIC   9
+
+#define BOOT_TMPBUF_SZ  256
+
+/*
+ * Maintain state of copy progress.
+ */
+struct boot_status {
+    uint32_t idx;         /* Which area we're operating on */
+    uint8_t state;        /* Which part of the swapping process are we at */
+    uint8_t use_scratch;  /* Are status bytes ever written to scratch? */
+    uint8_t swap_type;    /* The type of swap in effect */
+    uint32_t swap_size;   /* Total size of swapped image */
+};
+
+#define BOOT_MAGIC_GOOD     1
+#define BOOT_MAGIC_BAD      2
+#define BOOT_MAGIC_UNSET    3
+#define BOOT_MAGIC_ANY      4  /* NOTE: control only, not dependent on sector */
+#define BOOT_MAGIC_NOTGOOD  5  /* NOTE: control only, not dependent on sector */
+
+/*
+ * NOTE: leave BOOT_FLAG_SET equal to one, this is written to flash!
+ */
+#define BOOT_FLAG_SET       1
+#define BOOT_FLAG_BAD       2
+#define BOOT_FLAG_UNSET     3
+#define BOOT_FLAG_ANY       4  /* NOTE: control only, not dependent on sector */
+
+#define BOOT_STATUS_IDX_0   1
+
+#define BOOT_STATUS_STATE_0 1
+#define BOOT_STATUS_STATE_1 2
+#define BOOT_STATUS_STATE_2 3
+
+/**
+ * End-of-image slot structure.
+ *
+ *   0                   1                   2                   3
+ *   0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  ~                                                               ~
+ *  ~    Swap status (BOOT_MAX_IMG_SECTORS * min-write-size * 3)    ~
+ *  ~                                                               ~
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  |                      Swap size (4 octets)                     |
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  |   Swap info   |           0xff padding (7 octets)             |
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  |   Copy done   |           0xff padding (7 octets)             |
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  |   Image OK    |           0xff padding (7 octets)             |
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *  |                       MAGIC (16 octets)                       |
+ *  |                                                               |
+ *  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+extern const uint32_t boot_img_magic[4];
+
+struct boot_swap_state {
+    uint8_t magic;      /* One of the BOOT_MAGIC_[...] values. */
+    uint8_t swap_type;  /* One of the BOOT_SWAP_TYPE_[...] values. */
+    uint8_t copy_done;  /* One of the BOOT_FLAG_[...] values. */
+    uint8_t image_ok;   /* One of the BOOT_FLAG_[...] values. */
+    uint8_t image_num;  /* Boot status belongs to this image */
+};
+
+#ifdef MCUBOOT_IMAGE_NUMBER
+#define BOOT_IMAGE_NUMBER          MCUBOOT_IMAGE_NUMBER
+#else
+#define BOOT_IMAGE_NUMBER          1
+#endif
+
+_Static_assert(BOOT_IMAGE_NUMBER > 0, "Invalid value for BOOT_IMAGE_NUMBER");
+
+#define BOOT_MAX_IMG_SECTORS       MCUBOOT_MAX_IMG_SECTORS
+
+/*
+ * Extract the swap type and image number from image trailers's swap_info
+ * field.
+ */
+#define SWAP_INFO_SWAP_TYPE_MASK        (0x0Fu)
+#define SWAP_INFO_SWAP_TYPE_POS         (0)
+#define SWAP_INFO_IMAGE_NUM_MASK        (0xF0u)
+#define SWAP_INFO_IMAGE_NUM_POS         (4)
+
+#define BOOT_GET_SWAP_TYPE(swap_info)   ((swap_info) & SWAP_INFO_SWAP_TYPE_MASK)
+#define BOOT_GET_IMAGE_NUM(swap_info)   ((swap_info) >> SWAP_INFO_IMAGE_NUM_POS)
+
+/* Construct the swap_info field from swap type and image number */
+#define BOOT_SET_SWAP_INFO(swap_info, image, type)  {                          \
+                     assert(((image) & (SWAP_INFO_IMAGE_NUM_MASK >>            \
+                                        SWAP_INFO_IMAGE_NUM_POS)) == (image)); \
+                     assert(((type) & SWAP_INFO_SWAP_TYPE_MASK) == (type));    \
+                     (swap_info) = (image) << SWAP_INFO_IMAGE_NUM_POS          \
+                                 | (type);                                     \
+                     }
+#if 0
+/*
+ * The current flashmap API does not check the amount of space allocated when
+ * loading sector data from the flash device, allowing for smaller counts here
+ * would most surely incur in overruns.
+ *
+ * TODO: make flashmap API receive the current sector array size.
+ */
+#if BOOT_MAX_IMG_SECTORS < 32
+#error "Too few sectors, please increase BOOT_MAX_IMG_SECTORS to at least 32"
+#endif
+#endif
+/** Number of image slots in flash; currently limited to two. */
+#define BOOT_NUM_SLOTS                  2
+
+/** Maximum number of image sectors supported by the bootloader. */
+#define BOOT_STATUS_STATE_COUNT         3
+#define BOOT_STATUS_MAX_ENTRIES         MCUBOOT_STATUS_MAX_ENTRIES
+
+#define BOOT_PRIMARY_SLOT               0
+#define BOOT_SECONDARY_SLOT             1
+
+#define BOOT_STATUS_SOURCE_NONE         0
+#define BOOT_STATUS_SOURCE_SCRATCH      1
+#define BOOT_STATUS_SOURCE_PRIMARY_SLOT 2
+
+#define BOOT_MAGIC_SZ (sizeof boot_img_magic)
+
+/**
+ * Compatibility shim for flash sector type.
+ *
+ * This can be deleted when flash_area_to_sectors() is removed.
+ */
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+typedef struct flash_sector boot_sector_t;
+#else
+typedef struct flash_area boot_sector_t;
+#endif
+
+/** Private state maintained during boot. */
+struct boot_loader_state {
+    struct {
+        struct image_header hdr;
+        const struct flash_area *area;
+        boot_sector_t *sectors;
+        size_t num_sectors;
+        bool is_hdr_valid;
+    } imgs[BOOT_IMAGE_NUMBER][BOOT_NUM_SLOTS];
+
+    struct {
+        const struct flash_area *area;
+        boot_sector_t *sectors;
+        size_t num_sectors;
+    } scratch;
+
+    uint8_t swap_type[BOOT_IMAGE_NUMBER];
+    uint32_t write_sz;
+
+#if (BOOT_IMAGE_NUMBER > 1)
+    uint8_t curr_img_idx;
+#endif
+};
+
+uint32_t boot_secure_memequal(const void *s1, const void *s2, size_t n);
+int bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig,
+                        size_t slen, uint8_t key_id);
+
+int boot_magic_compatible_check(uint8_t tbl_val, uint8_t val);
+uint32_t boot_trailer_sz(uint32_t min_write_sz);
+int boot_status_entries(int image_index, const struct flash_area *fap);
+uint32_t boot_status_off(const struct flash_area *fap);
+uint32_t boot_swap_info_off(const struct flash_area *fap);
+int boot_read_swap_state(const struct flash_area *fap,
+                         struct boot_swap_state *state);
+int boot_read_swap_state_by_id(int flash_area_id,
+                               struct boot_swap_state *state);
+int boot_write_magic(const struct flash_area *fap);
+int boot_write_status(struct boot_loader_state *state, struct boot_status *bs);
+int boot_schedule_test_swap(void);
+int boot_write_copy_done(const struct flash_area *fap);
+int boot_write_image_ok(const struct flash_area *fap);
+int boot_write_swap_info(const struct flash_area *fap, uint8_t swap_type,
+                         uint8_t image_num);
+int boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size);
+int boot_read_swap_size(int image_index, uint32_t *swap_size);
+
+/**
+ * Safe (non-overflowing) uint32_t addition.  Returns true, and stores
+ * the result in *dest if it can be done without overflow.  Otherwise,
+ * returns false.
+ */
+static inline bool boot_u32_safe_add(uint32_t *dest, uint32_t a, uint32_t b)
+{
+    /*
+     * "a + b <= UINT32_MAX", subtract 'b' from both sides to avoid
+     * the overflow.
+     */
+    if (a > UINT32_MAX - b) {
+        return false;
+    } else {
+        *dest = a + b;
+        return true;
+    }
+}
+
+/**
+ * Safe (non-overflowing) uint16_t addition.  Returns true, and stores
+ * the result in *dest if it can be done without overflow.  Otherwise,
+ * returns false.
+ */
+static inline bool boot_u16_safe_add(uint16_t *dest, uint16_t a, uint16_t b)
+{
+    uint32_t tmp = a + b;
+    if (tmp > UINT16_MAX) {
+        return false;
+    } else {
+        *dest = tmp;
+        return true;
+    }
+}
+
+/*
+ * Accessors for the contents of struct boot_loader_state.
+ */
+
+/* These are macros so they can be used as lvalues. */
+#if (BOOT_IMAGE_NUMBER > 1)
+#define BOOT_CURR_IMG(state) ((state)->curr_img_idx)
+#else
+#define BOOT_CURR_IMG(state) 0
+#endif
+#define BOOT_IMG(state, slot) ((state)->imgs[BOOT_CURR_IMG(state)][(slot)])
+#define BOOT_IMG_AREA(state, slot) (BOOT_IMG(state, slot).area)
+#define BOOT_IMG_HDR_IS_VALID(state, slot) (BOOT_IMG(state, slot).is_hdr_valid)
+#define BOOT_SCRATCH_AREA(state) ((state)->scratch.area)
+#define BOOT_WRITE_SZ(state) ((state)->write_sz)
+#define BOOT_SWAP_TYPE(state) ((state)->swap_type[BOOT_CURR_IMG(state)])
+#define BOOT_TLV_OFF(hdr) ((hdr)->ih_hdr_size + (hdr)->ih_img_size)
+
+#define BOOT_IS_UPGRADE(swap_type)             \
+    (((swap_type) == BOOT_SWAP_TYPE_TEST) ||   \
+     ((swap_type) == BOOT_SWAP_TYPE_REVERT) || \
+     ((swap_type) == BOOT_SWAP_TYPE_PERM))
+
+static inline struct image_header*
+boot_img_hdr(struct boot_loader_state *state, size_t slot)
+{
+    return &BOOT_IMG(state, slot).hdr;
+}
+
+static inline size_t
+boot_img_num_sectors(const struct boot_loader_state *state, size_t slot)
+{
+    return BOOT_IMG(state, slot).num_sectors;
+}
+
+static inline size_t
+boot_scratch_num_sectors(struct boot_loader_state *state)
+{
+    return state->scratch.num_sectors;
+}
+
+/*
+ * Offset of the slot from the beginning of the flash device.
+ */
+static inline uint32_t
+boot_img_slot_off(struct boot_loader_state *state, size_t slot)
+{
+    return BOOT_IMG(state, slot).area->fa_off;
+}
+
+static inline size_t boot_scratch_area_size(struct boot_loader_state *state)
+{
+    return BOOT_SCRATCH_AREA(state)->fa_size;
+}
+
+#ifndef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+
+static inline size_t
+boot_img_sector_size(const struct boot_loader_state *state,
+                     size_t slot, size_t sector)
+{
+    return BOOT_IMG(state, slot).sectors[sector].fa_size;
+}
+
+/*
+ * Offset of the sector from the beginning of the image, NOT the flash
+ * device.
+ */
+static inline uint32_t
+boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
+                    size_t sector)
+{
+    return BOOT_IMG(state, slot).sectors[sector].fa_off -
+           BOOT_IMG(state, slot).sectors[0].fa_off;
+}
+
+#else  /* defined(MCUBOOT_USE_FLASH_AREA_GET_SECTORS) */
+
+static inline size_t
+boot_img_sector_size(const struct boot_loader_state *state,
+                     size_t slot, size_t sector)
+{
+    return BOOT_IMG(state, slot).sectors[sector].fs_size;
+}
+
+static inline uint32_t
+boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
+                    size_t sector)
+{
+    return BOOT_IMG(state, slot).sectors[sector].fs_off -
+           BOOT_IMG(state, slot).sectors[0].fs_off;
+}
+
+#endif  /* !defined(MCUBOOT_USE_FLASH_AREA_GET_SECTORS) */
+
+#ifdef MCUBOOT_RAM_LOADING
+#define LOAD_IMAGE_DATA(hdr, fap, start, output, size)       \
+    (memcpy((output),(void*)((hdr)->ih_load_addr + (start)), \
+    (size)) != (output))
+#else
+#define LOAD_IMAGE_DATA(hdr, fap, start, output, size)       \
+    (flash_area_read((fap), (start), (output), (size)))
+#endif /* MCUBOOT_RAM_LOADING */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_rsa.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_rsa.c
new file mode 100644
index 0000000000..ea7c78fd9b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_rsa.c
@@ -0,0 +1,297 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2019 Arm Limited.
+ */
+
+#include 
+
+#ifdef MCUBOOT_SIGN_RSA
+#include "bootutil/sign_key.h"
+#include "bootutil/sha256.h"
+
+#include "mbedtls/rsa.h"
+#include "mbedtls/asn1.h"
+#include "mbedtls/version.h"
+
+#include "bootutil_priv.h"
+
+/*
+ * Constants for this particular constrained implementation of
+ * RSA-PSS.  In particular, we support RSA 2048 and RSA 3072, with a SHA256
+ * hash, and a 32-byte salt.  A signature with different parameters will be
+ * rejected as invalid.
+ */
+
+/* The size, in octets, of the message. */
+#define PSS_EMLEN (MCUBOOT_SIGN_RSA_LEN / 8)
+
+/* The size of the hash function.  For SHA256, this is 32 bytes. */
+#define PSS_HLEN 32
+
+/* Size of the salt, should be fixed. */
+#define PSS_SLEN 32
+
+/* The length of the mask: emLen - hLen - 1. */
+#define PSS_MASK_LEN (PSS_EMLEN - PSS_HLEN - 1)
+
+#define PSS_HASH_OFFSET PSS_MASK_LEN
+
+/* For the mask itself, how many bytes should be all zeros. */
+#define PSS_MASK_ZERO_COUNT (PSS_MASK_LEN - PSS_SLEN - 1)
+#define PSS_MASK_ONE_POS   PSS_MASK_ZERO_COUNT
+
+/* Where the salt starts. */
+#define PSS_MASK_SALT_POS   (PSS_MASK_ONE_POS + 1)
+
+static const uint8_t pss_zeros[8] = {0};
+
+/*
+ * Parse the public key used for signing. Simple RSA format.
+ */
+static int
+bootutil_parse_rsakey(mbedtls_rsa_context *ctx, uint8_t **p, uint8_t *end)
+{
+    int rc, rc2;
+    size_t len;
+
+    rc = mbedtls_asn1_get_tag(p, end, &len,
+                            MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE);
+    if (rc != 0) {
+        return -1;
+    }
+
+    if (*p + len != end) {
+        return -2;
+    }
+
+    rc  = mbedtls_asn1_get_mpi(p, end, &ctx->N);
+    rc2 = mbedtls_asn1_get_mpi(p, end, &ctx->E);
+    if ((rc != 0) || (rc2 != 0)) {
+        return -3;
+    }
+
+    ctx->len = mbedtls_mpi_size(&ctx->N);
+
+    if (*p != end) {
+        return -4;
+    }
+
+    /* The mbedtls version is more than 2.6.1 */
+#if MBEDTLS_VERSION_NUMBER > 0x02060100
+    rc = mbedtls_rsa_import(ctx, &ctx->N, NULL, NULL, NULL, &ctx->E);
+    if (rc != 0) {
+        return -5;
+    }
+#endif
+
+    rc = mbedtls_rsa_check_pubkey(ctx);
+    if (rc != 0) {
+        return -6;
+    }
+
+    ctx->len = mbedtls_mpi_size(&ctx->N);
+
+    return 0;
+}
+
+/*
+ * Compute the RSA-PSS mask-generation function, MGF1.  Assumptions
+ * are that the mask length will be less than 256 * PSS_HLEN, and
+ * therefore we never need to increment anything other than the low
+ * byte of the counter.
+ *
+ * This is described in PKCS#1, B.2.1.
+ */
+static void
+pss_mgf1(uint8_t *mask, const uint8_t *hash)
+{
+    bootutil_sha256_context ctx;
+    uint8_t counter[4] = { 0, 0, 0, 0 };
+    uint8_t htmp[PSS_HLEN];
+    int count = PSS_MASK_LEN;
+    int bytes;
+
+    while (count > 0) {
+        bootutil_sha256_init(&ctx);
+        bootutil_sha256_update(&ctx, hash, PSS_HLEN);
+        bootutil_sha256_update(&ctx, counter, 4);
+        bootutil_sha256_finish(&ctx, htmp);
+
+        counter[3]++;
+
+        bytes = PSS_HLEN;
+        if (bytes > count)
+            bytes = count;
+
+        memcpy(mask, htmp, bytes);
+        mask += bytes;
+        count -= bytes;
+    }
+}
+
+/*
+ * Validate an RSA signature, using RSA-PSS, as described in PKCS #1
+ * v2.2, section 9.1.2, with many parameters required to have fixed
+ * values.
+ */
+static int
+bootutil_cmp_rsasig(mbedtls_rsa_context *ctx, uint8_t *hash, uint32_t hlen,
+  uint8_t *sig)
+{
+    bootutil_sha256_context shactx;
+    uint8_t em[MBEDTLS_MPI_MAX_SIZE];
+    uint8_t db_mask[PSS_MASK_LEN];
+    uint8_t h2[PSS_HLEN];
+    int i;
+
+    if (ctx->len != PSS_EMLEN || PSS_EMLEN > MBEDTLS_MPI_MAX_SIZE) {
+        return -1;
+    }
+
+    if (hlen != PSS_HLEN) {
+        return -1;
+    }
+
+    if (mbedtls_rsa_public(ctx, sig, em)) {
+        return -1;
+    }
+
+    /*
+     * PKCS #1 v2.2, 9.1.2 EMSA-PSS-Verify
+     *
+     * emBits is 2048
+     * emLen = ceil(emBits/8) = 256
+     *
+     * The salt length is not known at the beginning.
+     */
+
+    /* Step 1.  The message is constrained by the address space of a
+     * 32-bit processor, which is far less than the 2^61-1 limit of
+     * SHA-256.
+     */
+
+    /* Step 2.  mHash is passed in as 'hash', with hLen the hlen
+     * argument. */
+
+    /* Step 3.  if emLen < hLen + sLen + 2, inconsistent and stop.
+     * The salt length is not known at this point.
+     */
+
+    /* Step 4.  If the rightmost octect of EM does have the value
+     * 0xbc, output inconsistent and stop.
+     */
+    if (em[PSS_EMLEN - 1] != 0xbc) {
+        return -1;
+    }
+
+    /* Step 5.  Let maskedDB be the leftmost emLen - hLen - 1 octets
+     * of EM, and H be the next hLen octets.
+     *
+     * maskedDB is then the first 256 - 32 - 1 = 0-222
+     * H is 32 bytes 223-254
+     */
+
+    /* Step 6.  If the leftmost 8emLen - emBits bits of the leftmost
+     * octet in maskedDB are not all equal to zero, output
+     * inconsistent and stop.
+     *
+     * 8emLen - emBits is zero, so there is nothing to test here.
+     */
+
+    /* Step 7.  let dbMask = MGF(H, emLen - hLen - 1). */
+    pss_mgf1(db_mask, &em[PSS_HASH_OFFSET]);
+
+    /* Step 8.  let DB = maskedDB xor dbMask.
+     * To avoid needing an additional buffer, store the 'db' in the
+     * same buffer as db_mask.  From now, to the end of this function,
+     * db_mask refers to the unmasked 'db'. */
+    for (i = 0; i < PSS_MASK_LEN; i++) {
+        db_mask[i] ^= em[i];
+    }
+
+    /* Step 9.  Set the leftmost 8emLen - emBits bits of the leftmost
+     * octet in DB to zero.
+     * pycrypto seems to always make the emBits 2047, so we need to
+     * clear the top bit. */
+    db_mask[0] &= 0x7F;
+
+    /* Step 10.  If the emLen - hLen - sLen - 2 leftmost octets of DB
+     * are not zero or if the octet at position emLen - hLen - sLen -
+     * 1 (the leftmost position is "position 1") does not have
+     * hexadecimal value 0x01, output "inconsistent" and stop. */
+    for (i = 0; i < PSS_MASK_ZERO_COUNT; i++) {
+        if (db_mask[i] != 0) {
+            return -1;
+        }
+    }
+
+    if (db_mask[PSS_MASK_ONE_POS] != 1) {
+        return -1;
+    }
+
+    /* Step 11. Let salt be the last sLen octets of DB */
+
+    /* Step 12.  Let M' = 0x00 00 00 00 00 00 00 00 || mHash || salt; */
+
+    /* Step 13.  Let H' = Hash(M') */
+    bootutil_sha256_init(&shactx);
+    bootutil_sha256_update(&shactx, pss_zeros, 8);
+    bootutil_sha256_update(&shactx, hash, PSS_HLEN);
+    bootutil_sha256_update(&shactx, &db_mask[PSS_MASK_SALT_POS], PSS_SLEN);
+    bootutil_sha256_finish(&shactx, h2);
+
+    /* Step 14.  If H = H', output "consistent".  Otherwise, output
+     * "inconsistent". */
+    if (boot_secure_memequal(h2, &em[PSS_HASH_OFFSET], PSS_HLEN) != 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int
+bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
+  uint8_t key_id)
+{
+    mbedtls_rsa_context ctx;
+    int rc;
+    uint8_t *cp;
+    uint8_t *end;
+
+    mbedtls_rsa_init(&ctx, 0, 0);
+
+    cp = (uint8_t *)bootutil_keys[key_id].key;
+    end = cp + *bootutil_keys[key_id].len;
+
+    rc = bootutil_parse_rsakey(&ctx, &cp, end);
+    if (rc || slen != ctx.len) {
+        mbedtls_rsa_free(&ctx);
+        return rc;
+    }
+    rc = bootutil_cmp_rsasig(&ctx, hash, hlen, sig);
+    mbedtls_rsa_free(&ctx);
+
+    return rc;
+}
+#endif /* MCUBOOT_SIGN_RSA */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_validate.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_validate.c
new file mode 100644
index 0000000000..db9d5410a6
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/image_validate.c
@@ -0,0 +1,411 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2020 Arm Limited.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "flash_map/flash_map.h"
+#include "bootutil/image.h"
+#include "bootutil/sha256.h"
+#include "bootutil/sign_key.h"
+#include "security_cnt.h"
+
+#if defined(MCUBOOT_SIGN_RSA)
+#include "mbedtls/rsa.h"
+#endif
+
+#include "mbedtls/asn1.h"
+
+#include "bootutil_priv.h"
+
+#ifdef MCUBOOT_HW_KEY
+#include "platform/include/tfm_plat_crypto_keys.h"
+#endif
+
+/*
+ * Compute SHA256 over the image.
+ */
+static int
+bootutil_img_hash(int image_index,
+                  struct image_header *hdr, const struct flash_area *fap,
+                  uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *hash_result,
+                  uint8_t *seed, int seed_len)
+{
+    bootutil_sha256_context sha256_ctx;
+    uint32_t size;
+#ifndef MCUBOOT_RAM_LOADING
+    uint32_t blk_sz;
+    uint32_t off;
+    int rc;
+#endif /* MCUBOOT_RAM_LOADING */
+
+    (void)image_index;
+
+    bootutil_sha256_init(&sha256_ctx);
+
+    /* in some cases (split image) the hash is seeded with data from
+     * the loader image */
+    if (seed && (seed_len > 0)) {
+        bootutil_sha256_update(&sha256_ctx, seed, seed_len);
+    }
+
+    /* Hash is computed over image header and image itself. */
+    size = BOOT_TLV_OFF(hdr);
+
+    /* If protected TLVs are present they are also hashed. */
+    size += hdr->ih_protect_tlv_size;
+
+#ifdef MCUBOOT_RAM_LOADING
+    bootutil_sha256_update(&sha256_ctx,(void*)(hdr->ih_load_addr), size);
+#else
+    for (off = 0; off < size; off += blk_sz) {
+        blk_sz = size - off;
+        if (blk_sz > tmp_buf_sz) {
+            blk_sz = tmp_buf_sz;
+        }
+        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
+        if (rc) {
+            return rc;
+        }
+        bootutil_sha256_update(&sha256_ctx, tmp_buf, blk_sz);
+    }
+#endif
+    bootutil_sha256_finish(&sha256_ctx, hash_result);
+
+    return 0;
+}
+
+/*
+ * Currently, we only support being able to verify one type of
+ * signature, because there is a single verification function that we
+ * call.  List the type of TLV we are expecting.  If we aren't
+ * configured for any signature, don't define this macro.
+ */
+
+#if defined(MCUBOOT_SIGN_RSA)
+#    if MCUBOOT_SIGN_RSA_LEN == 2048
+#        define EXPECTED_SIG_TLV IMAGE_TLV_RSA2048_PSS
+#    elif MCUBOOT_SIGN_RSA_LEN == 3072
+#        define EXPECTED_SIG_TLV IMAGE_TLV_RSA3072_PSS
+#    else
+#        error "Unsupported RSA signature length"
+#    endif
+#    define SIG_BUF_SIZE (MCUBOOT_SIGN_RSA_LEN / 8)
+#    define EXPECTED_SIG_LEN(x) ((x) == SIG_BUF_SIZE)
+#else
+#    define SIG_BUF_SIZE 32 /* no signing, sha256 digest only */
+#endif
+
+#ifdef EXPECTED_SIG_TLV
+#ifdef MCUBOOT_HW_KEY
+extern unsigned int pub_key_len;
+static int
+bootutil_find_key(uint8_t image_id, uint8_t *key, uint16_t key_len)
+{
+    bootutil_sha256_context sha256_ctx;
+    uint8_t hash[32];
+    uint8_t key_hash[32];
+    uint32_t key_hash_size= sizeof(key_hash);
+    enum tfm_plat_err_t plat_err;
+
+    bootutil_sha256_init(&sha256_ctx);
+    bootutil_sha256_update(&sha256_ctx, key, key_len);
+    bootutil_sha256_finish(&sha256_ctx, hash);
+
+    plat_err = tfm_plat_get_rotpk_hash(image_id, key_hash, &key_hash_size);
+    if (plat_err != TFM_PLAT_ERR_SUCCESS) {
+        return -1;
+    }
+    if (!boot_secure_memequal(hash, key_hash, key_hash_size)) {
+        bootutil_keys[0].key = key;
+        pub_key_len = key_len;
+        return 0;
+    }
+    return -1;
+}
+#else /* !MCUBOOT_HW_KEY */
+static int
+bootutil_find_key(uint8_t *keyhash, uint8_t keyhash_len)
+{
+    bootutil_sha256_context sha256_ctx;
+    int i;
+    const struct bootutil_key *key;
+    uint8_t hash[32];
+
+    if (keyhash_len > 32) {
+        return -1;
+    }
+
+    for (i = 0; i < bootutil_key_cnt; i++) {
+        key = &bootutil_keys[i];
+        bootutil_sha256_init(&sha256_ctx);
+        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
+        bootutil_sha256_finish(&sha256_ctx, hash);
+        if (!boot_secure_memequal(hash, keyhash, keyhash_len)) {
+            return i;
+        }
+    }
+    return -1;
+}
+#endif
+#endif
+
+/**
+ * Reads the value of an image's security counter.
+ *
+ * @param hdr           Pointer to the image header structure.
+ * @param fap           Pointer to a description structure of the image's
+ *                      flash area.
+ * @param security_cnt  Pointer to store the security counter value.
+ *
+ * @return              0 on success; nonzero on failure.
+ */
+int32_t
+bootutil_get_img_security_cnt(struct image_header *hdr,
+                              const struct flash_area *fap,
+                              uint32_t *img_security_cnt)
+{
+    struct image_tlv_iter it;
+    uint32_t off;
+    uint16_t len;
+    int32_t rc;
+
+    if ((hdr == NULL) ||
+        (fap == NULL) ||
+        (img_security_cnt == NULL)) {
+        /* Invalid parameter. */
+        return BOOT_EBADARGS;
+    }
+
+    /* The security counter TLV is in the protected part of the TLV area. */
+    if (hdr->ih_protect_tlv_size == 0) {
+        return BOOT_EBADIMAGE;
+    }
+
+    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_SEC_CNT, true);
+    if (rc) {
+        return rc;
+    }
+
+    /* Traverse through the protected TLV area to find
+     * the security counter TLV.
+     */
+
+    rc = bootutil_tlv_iter_next(&it, &off, &len, NULL);
+    if (rc != 0) {
+        /* Security counter TLV has not been found. */
+        return -1;
+    }
+
+    if (len != sizeof(*img_security_cnt)) {
+        /* Security counter is not valid. */
+        return BOOT_EBADIMAGE;
+    }
+
+    rc = LOAD_IMAGE_DATA(hdr, fap, off, img_security_cnt, len);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    return 0;
+}
+
+/*
+ * Verify the integrity of the image.
+ * Return non-zero if image could not be validated/does not validate.
+ */
+int
+bootutil_img_validate(int image_index,
+                      struct image_header *hdr, const struct flash_area *fap,
+                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
+                      int seed_len, uint8_t *out_hash)
+{
+    uint32_t off;
+    uint16_t len;
+    uint8_t type;
+    int sha256_valid = 0;
+#ifdef EXPECTED_SIG_TLV
+    int valid_signature = 0;
+    int key_id = -1;
+#ifdef MCUBOOT_HW_KEY
+    /* Few extra bytes for encoding and for public exponent */
+    uint8_t key_buf[SIG_BUF_SIZE + 24];
+#endif
+#endif
+    struct image_tlv_iter it;
+    uint8_t buf[SIG_BUF_SIZE];
+    uint8_t hash[32] = {0};
+    uint32_t security_cnt;
+    uint32_t img_security_cnt;
+    int32_t security_counter_valid = 0;
+    int rc;
+
+    rc = bootutil_img_hash(image_index, hdr, fap, tmp_buf,
+            tmp_buf_sz, hash, seed, seed_len);
+    if (rc) {
+        return rc;
+    }
+
+    if (out_hash) {
+        memcpy(out_hash, hash, 32);
+    }
+
+    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
+    if (rc) {
+        return rc;
+    }
+
+    /*
+     * Traverse through all of the TLVs, performing any checks we know
+     * and are able to do.
+     */
+    while (true) {
+        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
+        if (rc < 0) {
+            return -1;
+        } else if (rc > 0) {
+            break;
+        }
+
+        if (type == IMAGE_TLV_SHA256) {
+            /*
+             * Verify the SHA256 image hash.  This must always be
+             * present.
+             */
+            if (len != sizeof(hash)) {
+                return -1;
+            }
+            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
+            if (rc) {
+                return rc;
+            }
+            if (boot_secure_memequal(hash, buf, sizeof(hash))) {
+                return -1;
+            }
+
+            sha256_valid = 1;
+#ifdef EXPECTED_SIG_TLV
+#ifndef MCUBOOT_HW_KEY
+        } else if (type == IMAGE_TLV_KEYHASH) {
+            /*
+             * Determine which key we should be checking.
+             */
+            if (len > 32) {
+                return -1;
+            }
+            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
+            if (rc) {
+                return rc;
+            }
+            key_id = bootutil_find_key(buf, len);
+            /*
+             * The key may not be found, which is acceptable.  There
+             * can be multiple signatures, each preceded by a key.
+             */
+#else /* MCUBOOT_HW_KEY */
+        } else if (type == IMAGE_TLV_KEY) {
+            /*
+             * Determine which key we should be checking.
+             */
+            if (len > sizeof(key_buf)) {
+                return -1;
+            }
+            rc = LOAD_IMAGE_DATA(hdr, fap, off, key_buf, len);
+            if (rc) {
+                return rc;
+            }
+            key_id = bootutil_find_key(image_index, key_buf, len);
+            /*
+             * The key may not be found, which is acceptable.  There
+             * can be multiple signatures, each preceded by a key.
+             */
+#endif /* MCUBOOT_HW_KEY */
+        } else if (type == EXPECTED_SIG_TLV) {
+            /* Ignore this signature if it is out of bounds. */
+            if (key_id < 0 || key_id >= bootutil_key_cnt) {
+                key_id = -1;
+                continue;
+            }
+            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
+                return -1;
+            }
+            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
+            if (rc) {
+                return -1;
+            }
+            rc = bootutil_verify_sig(hash, sizeof(hash), buf, len, key_id);
+            if (rc == 0) {
+                valid_signature = 1;
+            }
+            key_id = -1;
+#endif
+        } else if (type == IMAGE_TLV_SEC_CNT) {
+            /*
+             * Verify the image's security counter.
+             * This must always be present.
+             */
+            if (len != sizeof(img_security_cnt)) {
+                /* Security counter is not valid. */
+                return -1;
+            }
+
+            rc = LOAD_IMAGE_DATA(hdr, fap, off, &img_security_cnt, len);
+            if (rc) {
+                return rc;
+            }
+
+            rc = boot_nv_security_counter_get(0, &security_cnt);
+            if (rc) {
+                return rc;
+            }
+
+            /* Compare the new image's security counter value against the
+             * stored security counter value.
+             */
+            if (img_security_cnt < security_cnt) {
+                /* The image's security counter is not accepted. */
+                return -1;
+            }
+
+            /* The image's security counter has been successfully verified. */
+            security_counter_valid = 1;
+        }
+    }
+
+    if (!sha256_valid || !security_counter_valid) {
+        return -1;
+    }
+
+#ifdef EXPECTED_SIG_TLV
+    if (!valid_signature) {
+        return -1;
+    }
+#endif
+
+    return 0;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/loader.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/loader.c
new file mode 100644
index 0000000000..0c27b382d4
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/loader.c
@@ -0,0 +1,2844 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2020 Arm Limited.
+ */
+
+/**
+ * This file provides an interface to the boot loader.  Functions defined in
+ * this file should only be called while the boot loader is running.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "bootutil/bootutil.h"
+#include "bootutil/image.h"
+#include "bootutil_priv.h"
+#include "bootutil/bootutil_log.h"
+#include "bl2/include/tfm_boot_status.h"
+#include "bl2/include/boot_record.h"
+#include "security_cnt.h"
+
+static struct boot_loader_state boot_data;
+
+#if (BOOT_IMAGE_NUMBER > 1)
+#define IMAGES_ITER(x) for ((x) = 0; (x) < BOOT_IMAGE_NUMBER; ++(x))
+#else
+#define IMAGES_ITER(x)
+#endif
+
+#if !defined(MCUBOOT_NO_SWAP) && !defined(MCUBOOT_RAM_LOADING)
+
+#if defined(MCUBOOT_VALIDATE_PRIMARY_SLOT) && !defined(MCUBOOT_OVERWRITE_ONLY)
+static int boot_status_fails = 0;
+#define BOOT_STATUS_ASSERT(x)                \
+    do {                                     \
+        if (!(x)) {                          \
+            boot_status_fails++;             \
+        }                                    \
+    } while (0)
+#else
+#define BOOT_STATUS_ASSERT(x) ASSERT(x)
+#endif
+
+struct boot_status_table {
+    uint8_t bst_magic_primary_slot;
+    uint8_t bst_magic_scratch;
+    uint8_t bst_copy_done_primary_slot;
+    uint8_t bst_status_source;
+};
+
+/**
+ * This set of tables maps swap state contents to boot status location.
+ * When searching for a match, these tables must be iterated in order.
+ */
+static const struct boot_status_table boot_status_tables[] = {
+    {
+        /*           | primary slot | scratch      |
+         * ----------+--------------+--------------|
+         *     magic | Good         | Any          |
+         * copy-done | Set          | N/A          |
+         * ----------+--------------+--------------'
+         * source: none                            |
+         * ----------------------------------------'
+         */
+        .bst_magic_primary_slot =     BOOT_MAGIC_GOOD,
+        .bst_magic_scratch =          BOOT_MAGIC_NOTGOOD,
+        .bst_copy_done_primary_slot = BOOT_FLAG_SET,
+        .bst_status_source =          BOOT_STATUS_SOURCE_NONE,
+    },
+
+    {
+        /*           | primary slot | scratch      |
+         * ----------+--------------+--------------|
+         *     magic | Good         | Any          |
+         * copy-done | Unset        | N/A          |
+         * ----------+--------------+--------------'
+         * source: primary slot                    |
+         * ----------------------------------------'
+         */
+        .bst_magic_primary_slot =     BOOT_MAGIC_GOOD,
+        .bst_magic_scratch =          BOOT_MAGIC_NOTGOOD,
+        .bst_copy_done_primary_slot = BOOT_FLAG_UNSET,
+        .bst_status_source =          BOOT_STATUS_SOURCE_PRIMARY_SLOT,
+    },
+
+    {
+        /*           | primary slot | scratch      |
+         * ----------+--------------+--------------|
+         *     magic | Any          | Good         |
+         * copy-done | Any          | N/A          |
+         * ----------+--------------+--------------'
+         * source: scratch                         |
+         * ----------------------------------------'
+         */
+        .bst_magic_primary_slot =     BOOT_MAGIC_ANY,
+        .bst_magic_scratch =          BOOT_MAGIC_GOOD,
+        .bst_copy_done_primary_slot = BOOT_FLAG_ANY,
+        .bst_status_source =          BOOT_STATUS_SOURCE_SCRATCH,
+    },
+
+    {
+        /*           | primary slot | scratch      |
+         * ----------+--------------+--------------|
+         *     magic | Unset        | Any          |
+         * copy-done | Unset        | N/A          |
+         * ----------+--------------+--------------|
+         * source: varies                          |
+         * ----------------------------------------+--------------------------+
+         * This represents one of two cases:                                  |
+         * o No swaps ever (no status to read, so no harm in checking).       |
+         * o Mid-revert; status in the primary slot.                          |
+         * -------------------------------------------------------------------'
+         */
+        .bst_magic_primary_slot =     BOOT_MAGIC_UNSET,
+        .bst_magic_scratch =          BOOT_MAGIC_ANY,
+        .bst_copy_done_primary_slot = BOOT_FLAG_UNSET,
+        .bst_status_source =          BOOT_STATUS_SOURCE_PRIMARY_SLOT,
+    },
+};
+
+#define BOOT_STATUS_TABLES_COUNT \
+    (sizeof(boot_status_tables) / sizeof(boot_status_tables[0]))
+
+#define BOOT_LOG_SWAP_STATE(area, state)                            \
+    BOOT_LOG_INF("%s: magic=%5s, swap_type=0x%x, copy_done=0x%x, "  \
+                 "image_ok=0x%x",                                   \
+                 (area),                                            \
+                 ((state)->magic == BOOT_MAGIC_GOOD ? "good" :      \
+                  (state)->magic == BOOT_MAGIC_UNSET ? "unset" :    \
+                  "bad"),                                           \
+                 (state)->swap_type,                                \
+                 (state)->copy_done,                                \
+                 (state)->image_ok)
+#endif /* !MCUBOOT_NO_SWAP && !MCUBOOT_RAM_LOADING */
+
+/*
+ * \brief Verifies the image header: magic value, flags, integer overflow.
+ *
+ * \retval 0
+ * \retval BOOT_EBADIMAGE
+ */
+static int
+boot_verify_image_header(struct image_header *hdr)
+{
+    uint32_t image_end;
+    uint32_t x;
+
+    if (hdr->ih_magic != IMAGE_MAGIC) {
+        return BOOT_EBADIMAGE;
+    }
+
+    /* Check input parameters against integer overflow */
+    if (!boot_u32_safe_add(&image_end, hdr->ih_hdr_size, hdr->ih_img_size)) {
+        return BOOT_EBADIMAGE;
+    }
+
+    if (!boot_u32_safe_add(&x, image_end, hdr->ih_protect_tlv_size)) {
+        return BOOT_EBADIMAGE;
+    }
+
+#if MCUBOOT_RAM_LOADING
+    if (!(hdr->ih_flags & IMAGE_F_RAM_LOAD)) {
+        return BOOT_EBADIMAGE;
+    }
+
+    /* Check input parameters against integer overflow */
+    if (!boot_u32_safe_add(&x, image_end, hdr->ih_load_addr)) {
+        return BOOT_EBADIMAGE;
+    }
+#endif
+
+    return 0;
+}
+
+static int
+boot_read_image_header(struct boot_loader_state *state, int slot,
+                       struct image_header *out_hdr)
+{
+    const struct flash_area *fap = NULL;
+    int area_id;
+    int rc;
+
+#if (BOOT_IMAGE_NUMBER == 1)
+    (void)state;
+#endif
+
+    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    rc = flash_area_read(fap, 0, out_hdr, sizeof(*out_hdr));
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    rc = boot_verify_image_header(out_hdr);
+    BOOT_IMG_HDR_IS_VALID(state, slot) = (rc == 0);
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
+
+static int
+boot_read_image_headers(struct boot_loader_state *state, bool require_all)
+{
+    int rc;
+    int i;
+
+    for (i = 0; i < BOOT_NUM_SLOTS; i++) {
+        rc = boot_read_image_header(state, i, boot_img_hdr(state, i));
+        if (rc != 0) {
+            /* If `require_all` is set, fail on any single fail, otherwise
+             * if at least the first slot's header was read successfully,
+             * then the boot loader can attempt a boot.
+             *
+             * Failure to read any headers is a fatal error.
+             */
+            if (i > 0 && !require_all) {
+                return 0;
+            } else {
+                return rc;
+            }
+        }
+    }
+
+    return 0;
+}
+
+static uint32_t
+boot_write_sz(struct boot_loader_state *state)
+{
+    uint32_t elem_sz;
+    uint32_t align;
+
+    /* Figure out what size to write update status update as.  The size depends
+     * on what the minimum write size is for scratch area, active image slot.
+     * We need to use the bigger of those 2 values.
+     */
+    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
+    align = flash_area_align(BOOT_SCRATCH_AREA(state));
+    if (align > elem_sz) {
+        elem_sz = align;
+    }
+
+    return elem_sz;
+}
+
+#ifndef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+static int
+boot_initialize_area(struct boot_loader_state *state, int flash_area)
+{
+    int num_sectors = BOOT_MAX_IMG_SECTORS;
+    int rc;
+
+    if (flash_area == FLASH_AREA_IMAGE_PRIMARY(BOOT_CURR_IMG(state))) {
+        rc = flash_area_to_sectors(flash_area, &num_sectors,
+                                   BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors);
+        BOOT_IMG(state, BOOT_PRIMARY_SLOT).num_sectors = (size_t)num_sectors;
+
+    } else if (flash_area == FLASH_AREA_IMAGE_SECONDARY(BOOT_CURR_IMG(state))) {
+        rc = flash_area_to_sectors(flash_area, &num_sectors,
+                                 BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors);
+        BOOT_IMG(state, BOOT_SECONDARY_SLOT).num_sectors = (size_t)num_sectors;
+
+    } else if (flash_area == FLASH_AREA_IMAGE_SCRATCH) {
+        rc = flash_area_to_sectors(flash_area, &num_sectors,
+                                   state->scratch.sectors);
+        state->scratch.num_sectors = (size_t)num_sectors;
+    } else {
+        return BOOT_EFLASH;
+    }
+
+    return rc;
+}
+#else  /* defined(MCUBOOT_USE_FLASH_AREA_GET_SECTORS) */
+static int
+boot_initialize_area(struct boot_loader_state *state, int flash_area)
+{
+    uint32_t num_sectors;
+    struct flash_sector *out_sectors;
+    size_t *out_num_sectors;
+    int rc;
+
+    num_sectors = BOOT_MAX_IMG_SECTORS;
+
+    if (flash_area == FLASH_AREA_IMAGE_PRIMARY(BOOT_CURR_IMG(state))) {
+        out_sectors = BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors;
+        out_num_sectors = &BOOT_IMG(state, BOOT_PRIMARY_SLOT).num_sectors;
+    } else if (flash_area == FLASH_AREA_IMAGE_SECONDARY(BOOT_CURR_IMG(state))) {
+        out_sectors = BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors;
+        out_num_sectors = &BOOT_IMG(state, BOOT_SECONDARY_SLOT).num_sectors;
+    } else if (flash_area == FLASH_AREA_IMAGE_SCRATCH) {
+        out_sectors = state->scratch.sectors;
+        out_num_sectors = &state->scratch.num_sectors;
+    } else {
+        return BOOT_EFLASH;
+    }
+
+    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
+    if (rc != 0) {
+        return rc;
+    }
+    *out_num_sectors = num_sectors;
+    return 0;
+}
+#endif  /* !defined(MCUBOOT_USE_FLASH_AREA_GET_SECTORS) */
+
+/**
+ * Determines the sector layout of both image slots and the scratch area.
+ * This information is necessary for calculating the number of bytes to erase
+ * and copy during an image swap.  The information collected during this
+ * function is used to populate the state.
+ */
+static int
+boot_read_sectors(struct boot_loader_state *state)
+{
+    uint8_t image_index;
+    int rc;
+
+    image_index = BOOT_CURR_IMG(state);
+
+    rc = boot_initialize_area(state, FLASH_AREA_IMAGE_PRIMARY(image_index));
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_initialize_area(state, FLASH_AREA_IMAGE_SECONDARY(image_index));
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_initialize_area(state, FLASH_AREA_IMAGE_SCRATCH);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    BOOT_WRITE_SZ(state) = boot_write_sz(state);
+
+    return 0;
+}
+
+/**
+ * Validate image hash/signature and security counter in a slot.
+ */
+static int
+boot_image_check(struct boot_loader_state *state, struct image_header *hdr,
+                 const struct flash_area *fap, struct boot_status *bs)
+{
+    static uint8_t tmpbuf[BOOT_TMPBUF_SZ];
+    uint8_t image_index;
+
+#if (BOOT_IMAGE_NUMBER == 1)
+    (void)state;
+#endif
+
+    (void)bs;
+
+    image_index = BOOT_CURR_IMG(state);
+
+    if (bootutil_img_validate(image_index, hdr, fap, tmpbuf,
+                              BOOT_TMPBUF_SZ, NULL, 0, NULL)) {
+        return BOOT_EBADIMAGE;
+    }
+
+    return 0;
+}
+
+/*
+ * Check that a memory area consists of a given value.
+ */
+static inline bool
+boot_data_is_set_to(uint8_t val, void *data, size_t len)
+{
+    uint8_t i;
+    uint8_t *p = (uint8_t *)data;
+    for (i = 0; i < len; i++) {
+        if (val != p[i]) {
+            return false;
+        }
+    }
+    return true;
+}
+
+static int
+boot_check_header_erased(struct boot_loader_state *state, int slot)
+{
+    const struct flash_area *fap;
+    struct image_header *hdr;
+    uint8_t erased_val;
+    int area_id;
+    int rc;
+
+    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        return -1;
+    }
+
+    erased_val = flash_area_erased_val(fap);
+    flash_area_close(fap);
+
+    hdr = boot_img_hdr(state, slot);
+    if (!boot_data_is_set_to(erased_val, &hdr->ih_magic,
+                             sizeof(hdr->ih_magic))) {
+        return -1;
+    }
+
+    return 0;
+}
+
+/*
+ * Check that there is a valid image in a slot
+ *
+ * @returns
+ *         0 if image was succesfully validated
+ *         1 if no bootloable image was found
+ *         -1 on any errors
+ */
+static int
+boot_validate_slot(struct boot_loader_state *state, int slot,
+                   struct boot_status *bs)
+{
+    const struct flash_area *fap;
+    struct image_header *hdr;
+    int area_id;
+    int rc;
+
+    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        return -1;
+    }
+
+    hdr = boot_img_hdr(state, slot);
+    if ((boot_check_header_erased(state, slot) == 0) ||
+        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
+        /* No bootable image in slot; continue booting from the primary slot. */
+        rc = 1;
+        goto out;
+    }
+
+    if ((!BOOT_IMG_HDR_IS_VALID(state, slot)) ||
+         (boot_image_check(state, hdr, fap, bs) != 0)) {
+        if (slot != BOOT_PRIMARY_SLOT) {
+            flash_area_erase(fap, 0, fap->fa_size);
+            /* Image in the secondary slot is invalid. Erase the image and
+             * continue booting from the primary slot.
+             */
+        }
+        BOOT_LOG_ERR("Image in the %s slot is not valid!",
+                     (slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
+        rc = -1;
+        goto out;
+    }
+
+    /* Image in the secondary slot is valid. */
+    rc = 0;
+
+out:
+    flash_area_close(fap);
+    return rc;
+}
+
+/**
+ * Updates the stored security counter value with the image's security counter
+ * value which resides in the given slot if it's greater than the stored value.
+ *
+ * @param image_index   Index of the image to determine which security
+ *                      counter to update.
+ * @param slot          Slot number of the image.
+ * @param hdr           Pointer to the image header structure of the image
+ *                      that is currently stored in the given slot.
+ *
+ * @return              0 on success; nonzero on failure.
+ */
+static int
+boot_update_security_counter(uint8_t image_index, int slot,
+                             struct image_header *hdr)
+{
+    const struct flash_area *fap = NULL;
+    uint32_t img_security_cnt;
+    int rc;
+
+    rc = flash_area_open(flash_area_id_from_multi_image_slot(image_index, slot),
+                         &fap);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    rc = bootutil_get_img_security_cnt(hdr, fap, &img_security_cnt);
+    if (rc != 0) {
+        goto done;
+    }
+
+    rc = boot_nv_security_counter_update(image_index, img_security_cnt);
+    if (rc != 0) {
+        goto done;
+    }
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
+
+#if !defined(MCUBOOT_NO_SWAP) && !defined(MCUBOOT_OVERWRITE_ONLY)
+/*
+ * Compute the total size of the given image.  Includes the size of
+ * the TLVs.
+ */
+static int
+boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
+{
+    const struct flash_area *fap = NULL;
+    struct image_tlv_info info;
+    uint32_t off;
+    uint32_t protect_tlv_size;
+    int area_id;
+    int rc;
+
+#if (BOOT_IMAGE_NUMBER == 1)
+    (void)state;
+#endif
+
+    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
+
+    if (flash_area_read(fap, off, &info, sizeof(info))) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
+    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
+        if (protect_tlv_size != info.it_tlv_tot) {
+            rc = BOOT_EBADIMAGE;
+            goto done;
+        }
+
+        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
+            rc = BOOT_EFLASH;
+            goto done;
+        }
+    } else if (protect_tlv_size != 0) {
+        rc = BOOT_EBADIMAGE;
+        goto done;
+    }
+
+    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
+        rc = BOOT_EBADIMAGE;
+        goto done;
+    }
+
+    *size = off + protect_tlv_size + info.it_tlv_tot;
+    rc = 0;
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
+#endif /* !MCUBOOT_NO_SWAP && !MCUBOOT_OVERWRITE_ONLY */
+
+#if !defined(MCUBOOT_NO_SWAP) && !defined(MCUBOOT_RAM_LOADING)
+/**
+ * Determines where in flash the most recent boot status is stored. The boot
+ * status is necessary for completing a swap that was interrupted by a boot
+ * loader reset.
+ *
+ * @return      A BOOT_STATUS_SOURCE_[...] code indicating where status should
+ *              be read from.
+ */
+static int
+boot_status_source(struct boot_loader_state *state)
+{
+    const struct boot_status_table *table;
+    struct boot_swap_state state_scratch;
+    struct boot_swap_state state_primary_slot;
+    int rc;
+    size_t i;
+    uint8_t source;
+    uint8_t image_index;
+
+#if (BOOT_IMAGE_NUMBER == 1)
+    (void)state;
+#endif
+
+    image_index = BOOT_CURR_IMG(state);
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
+            &state_primary_slot);
+    assert(rc == 0);
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SCRATCH, &state_scratch);
+    assert(rc == 0);
+
+    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
+    BOOT_LOG_SWAP_STATE("Scratch", &state_scratch);
+
+    for (i = 0; i < BOOT_STATUS_TABLES_COUNT; i++) {
+        table = &boot_status_tables[i];
+
+        if (boot_magic_compatible_check(table->bst_magic_primary_slot,
+                          state_primary_slot.magic) &&
+            boot_magic_compatible_check(table->bst_magic_scratch,
+                          state_scratch.magic) &&
+            (table->bst_copy_done_primary_slot == BOOT_FLAG_ANY ||
+             table->bst_copy_done_primary_slot == state_primary_slot.copy_done))
+        {
+            source = table->bst_status_source;
+
+#if (BOOT_IMAGE_NUMBER > 1)
+            /* In case of multi-image boot it can happen that if boot status
+             * info is found on scratch area then it does not belong to the
+             * currently examined image.
+             */
+            if (source == BOOT_STATUS_SOURCE_SCRATCH &&
+                state_scratch.image_num != BOOT_CURR_IMG(state)) {
+                source = BOOT_STATUS_SOURCE_NONE;
+            }
+#endif
+
+            BOOT_LOG_INF("Boot source: %s",
+                         source == BOOT_STATUS_SOURCE_NONE ? "none" :
+                         source == BOOT_STATUS_SOURCE_SCRATCH ? "scratch" :
+                         source == BOOT_STATUS_SOURCE_PRIMARY_SLOT ?
+                                   "primary slot" : "BUG; can't happen");
+            return source;
+        }
+    }
+
+    BOOT_LOG_INF("Boot source: none");
+    return BOOT_STATUS_SOURCE_NONE;
+}
+
+/*
+ * Slots are compatible when all sectors that store up to to size of the image
+ * round up to sector size, in both slot's are able to fit in the scratch
+ * area, and have sizes that are a multiple of each other (powers of two
+ * presumably!).
+ */
+static int
+boot_slots_compatible(struct boot_loader_state *state)
+{
+    size_t num_sectors_primary;
+    size_t num_sectors_secondary;
+    size_t sz0, sz1;
+    size_t primary_slot_sz, secondary_slot_sz;
+#ifndef MCUBOOT_OVERWRITE_ONLY
+    size_t scratch_sz;
+#endif
+    size_t i, j;
+    int8_t smaller;
+
+    num_sectors_primary = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
+    num_sectors_secondary = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT);
+    if ((num_sectors_primary > BOOT_MAX_IMG_SECTORS) ||
+        (num_sectors_secondary > BOOT_MAX_IMG_SECTORS)) {
+        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
+        return 0;
+    }
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+    scratch_sz = boot_scratch_area_size(state);
+#endif
+
+    /*
+     * The following loop scans all sectors in a linear fashion, assuring that
+     * for each possible sector in each slot, it is able to fit in the other
+     * slot's sector or sectors. Slot's should be compatible as long as any
+     * number of a slot's sectors are able to fit into another, which only
+     * excludes cases where sector sizes are not a multiple of each other.
+     */
+    i = sz0 = primary_slot_sz = 0;
+    j = sz1 = secondary_slot_sz = 0;
+    smaller = 0;
+    while (i < num_sectors_primary || j < num_sectors_secondary) {
+        if (sz0 == sz1) {
+            sz0 += boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i);
+            sz1 += boot_img_sector_size(state, BOOT_SECONDARY_SLOT, j);
+            i++;
+            j++;
+        } else if (sz0 < sz1) {
+            sz0 += boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i);
+            /* Guarantee that multiple sectors of the secondary slot
+             * fit into the primary slot.
+             */
+            if (smaller == 2) {
+                BOOT_LOG_WRN("Cannot upgrade: slots have non-compatible"
+                             " sectors");
+                return 0;
+            }
+            smaller = 1;
+            i++;
+        } else {
+            sz1 += boot_img_sector_size(state, BOOT_SECONDARY_SLOT, j);
+            /* Guarantee that multiple sectors of the primary slot
+             * fit into the secondary slot.
+             */
+            if (smaller == 1) {
+                BOOT_LOG_WRN("Cannot upgrade: slots have non-compatible"
+                             " sectors");
+                return 0;
+            }
+            smaller = 2;
+            j++;
+        }
+#ifndef MCUBOOT_OVERWRITE_ONLY
+        if (sz0 == sz1) {
+            primary_slot_sz += sz0;
+            secondary_slot_sz += sz1;
+            /* Scratch has to fit each swap operation to the size of the larger
+             * sector among the primary slot and the secondary slot.
+             */
+            if (sz0 > scratch_sz || sz1 > scratch_sz) {
+                BOOT_LOG_WRN("Cannot upgrade: not all sectors fit inside"
+                             " scratch");
+                return 0;
+            }
+            smaller = sz0 = sz1 = 0;
+        }
+#endif
+    }
+
+    if ((i != num_sectors_primary) ||
+        (j != num_sectors_secondary) ||
+        (primary_slot_sz != secondary_slot_sz)) {
+        BOOT_LOG_WRN("Cannot upgrade: slots are not compatible");
+        return 0;
+    }
+
+    return 1;
+}
+
+static uint32_t
+boot_status_internal_off(int idx, int state, int elem_sz)
+{
+    int idx_sz;
+
+    idx_sz = elem_sz * BOOT_STATUS_STATE_COUNT;
+
+    return (idx - BOOT_STATUS_IDX_0) * idx_sz +
+           (state - BOOT_STATUS_STATE_0) * elem_sz;
+}
+
+/**
+ * Reads the status of a partially-completed swap, if any.  This is necessary
+ * to recover in case the boot lodaer was reset in the middle of a swap
+ * operation.
+ */
+static int
+boot_read_status_bytes(const struct flash_area *fap,
+        struct boot_loader_state *state, struct boot_status *bs)
+{
+    uint32_t off;
+    uint8_t status;
+    int max_entries;
+    int found;
+    int found_idx;
+    int invalid;
+    int rc;
+    int i;
+
+    off = boot_status_off(fap);
+    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
+    if (max_entries < 0) {
+        return BOOT_EBADARGS;
+    }
+
+    found = 0;
+    found_idx = 0;
+    invalid = 0;
+    for (i = 0; i < max_entries; i++) {
+        rc = flash_area_read_is_empty(fap, off + i * BOOT_WRITE_SZ(state),
+                &status, 1);
+        if (rc < 0) {
+            return BOOT_EFLASH;
+        }
+
+        if (rc == 1) {
+            if (found && !found_idx) {
+                found_idx = i;
+            }
+        } else if (!found) {
+            found = 1;
+        } else if (found_idx) {
+            invalid = 1;
+            break;
+        }
+    }
+
+    if (invalid) {
+        /* This means there was an error writing status on the last
+         * swap. Tell user and move on to validation!
+         */
+        BOOT_LOG_ERR("Detected inconsistent status!");
+
+#if !defined(MCUBOOT_VALIDATE_PRIMARY_SLOT)
+        /* With validation of the primary slot disabled, there is no way
+         * to be sure the swapped primary slot is OK, so abort!
+         */
+        assert(0);
+#endif
+    }
+
+    if (found) {
+        if (!found_idx) {
+            found_idx = i;
+        }
+        bs->idx = (found_idx / BOOT_STATUS_STATE_COUNT) + 1;
+        bs->state = (found_idx % BOOT_STATUS_STATE_COUNT) + 1;
+    }
+
+    return 0;
+}
+
+/**
+ * Reads the boot status from the flash.  The boot status contains
+ * the current state of an interrupted image copy operation.  If the boot
+ * status is not present, or it indicates that previous copy finished,
+ * there is no operation in progress.
+ */
+static int
+boot_read_status(struct boot_loader_state *state, struct boot_status *bs)
+{
+    const struct flash_area *fap;
+    uint32_t off;
+    uint8_t swap_info;
+    int status_loc;
+    int area_id;
+    int rc;
+
+    memset(bs, 0, sizeof *bs);
+    bs->idx = BOOT_STATUS_IDX_0;
+    bs->state = BOOT_STATUS_STATE_0;
+    bs->swap_type = BOOT_SWAP_TYPE_NONE;
+
+#ifdef MCUBOOT_OVERWRITE_ONLY
+    //hack
+    if(boot_data.imgs[0][BOOT_SECONDARY_SLOT].is_hdr_valid == true)
+        bs->swap_type = BOOT_SWAP_TYPE_PERM;
+    /* Overwrite-only doesn't make use of the swap status area. */
+    return 0;
+#endif
+
+    status_loc = boot_status_source(state);
+    switch (status_loc) {
+    case BOOT_STATUS_SOURCE_NONE:
+        return 0;
+
+    case BOOT_STATUS_SOURCE_SCRATCH:
+        area_id = FLASH_AREA_IMAGE_SCRATCH;
+        break;
+
+    case BOOT_STATUS_SOURCE_PRIMARY_SLOT:
+        area_id = FLASH_AREA_IMAGE_PRIMARY(BOOT_CURR_IMG(state));
+        break;
+
+    default:
+        assert(0);
+        return BOOT_EBADARGS;
+    }
+
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_read_status_bytes(fap, state, bs);
+    if (rc == 0) {
+        off = boot_swap_info_off(fap);
+        rc = flash_area_read_is_empty(fap, off, &swap_info, sizeof swap_info);
+        if (rc == 1) {
+            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
+            rc = 0;
+        }
+
+        /* Extract the swap type info */
+        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
+    }
+
+    flash_area_close(fap);
+
+    return rc;
+}
+
+/**
+ * Writes the supplied boot status to the flash file system.  The boot status
+ * contains the current state of an in-progress image copy operation.
+ *
+ * @param bs                    The boot status to write.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+int
+boot_write_status(struct boot_loader_state *state, struct boot_status *bs)
+{
+    const struct flash_area *fap = NULL;
+    uint32_t off;
+    int area_id;
+    int rc;
+    uint8_t buf[BOOT_MAX_ALIGN];
+    uint32_t align;
+    uint8_t erased_val;
+
+    /* NOTE: The first sector copied (that is the last sector on slot) contains
+     *       the trailer. Since in the last step the primary slot is erased, the
+     *       first two status writes go to the scratch which will be copied to
+     *       the primary slot!
+     */
+
+    if (bs->use_scratch) {
+        /* Write to scratch. */
+        area_id = FLASH_AREA_IMAGE_SCRATCH;
+    } else {
+        /* Write to the primary slot. */
+        area_id = FLASH_AREA_IMAGE_PRIMARY(BOOT_CURR_IMG(state));
+    }
+
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    off = boot_status_off(fap) +
+          boot_status_internal_off(bs->idx, bs->state, BOOT_WRITE_SZ(state));
+    align = flash_area_align(fap);
+    erased_val = flash_area_erased_val(fap);
+    memset(buf, erased_val, BOOT_MAX_ALIGN);
+    buf[0] = bs->state;
+
+    rc = flash_area_write(fap, off, buf, align);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    rc = 0;
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
+
+/**
+ * Determines which swap operation to perform, if any.  If it is determined
+ * that a swap operation is required, the image in the secondary slot is checked
+ * for validity.  If the image in the secondary slot is invalid, it is erased,
+ * and a swap type of "none" is indicated.
+ *
+ * @return                      The type of swap to perform (BOOT_SWAP_TYPE...)
+ */
+static int
+boot_validated_swap_type(struct boot_loader_state *state,
+                         struct boot_status *bs)
+{
+    int swap_type;
+    int rc;
+
+    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
+    if (BOOT_IS_UPGRADE(swap_type)) {
+        /* Boot loader wants to switch to the secondary slot.
+         * Ensure image is valid.
+         */
+        rc = boot_validate_slot(state, BOOT_SECONDARY_SLOT, bs);
+        if (rc == 1) {
+            swap_type = BOOT_SWAP_TYPE_NONE;
+        } else if (rc != 0) {
+            swap_type = BOOT_SWAP_TYPE_FAIL;
+        }
+    }
+
+    return swap_type;
+}
+
+/**
+ * Calculates the number of sectors the scratch area can contain.  A "last"
+ * source sector is specified because images are copied backwards in flash
+ * (final index to index number 0).
+ *
+ * @param last_sector_idx       The index of the last source sector
+ *                                  (inclusive).
+ * @param out_first_sector_idx  The index of the first source sector
+ *                                  (inclusive) gets written here.
+ *
+ * @return                      The number of bytes comprised by the
+ *                                  [first-sector, last-sector] range.
+ */
+#ifndef MCUBOOT_OVERWRITE_ONLY
+static uint32_t
+boot_copy_sz(struct boot_loader_state *state, int last_sector_idx,
+             int *out_first_sector_idx)
+{
+    size_t scratch_sz;
+    uint32_t new_sz;
+    uint32_t sz;
+    int i;
+
+    sz = 0;
+
+    scratch_sz = boot_scratch_area_size(state);
+    for (i = last_sector_idx; i >= 0; i--) {
+        new_sz = sz + boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i);
+        /*
+         * The secondary slot is not being checked here, because
+         * `boot_slots_compatible` already provides assurance that the copy size
+         * will be compatible with the primary slot and scratch.
+         */
+        if (new_sz > scratch_sz) {
+            break;
+        }
+        sz = new_sz;
+    }
+
+    /* i currently refers to a sector that doesn't fit or it is -1 because all
+     * sectors have been processed.  In both cases, exclude sector i.
+     */
+    *out_first_sector_idx = i + 1;
+    return sz;
+}
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+
+/**
+ * Erases a region of flash.
+ *
+ * @param flash_area            The flash_area containing the region to erase.
+ * @param off                   The offset within the flash area to start the
+ *                                  erase.
+ * @param sz                    The number of bytes to erase.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+static inline int
+boot_erase_region(const struct flash_area *fap, uint32_t off, uint32_t sz)
+{
+    return flash_area_erase(fap, off, sz);
+}
+
+/**
+ * Copies the contents of one flash region to another.  You must erase the
+ * destination region prior to calling this function.
+ *
+ * @param flash_area_id_src     The ID of the source flash area.
+ * @param flash_area_id_dst     The ID of the destination flash area.
+ * @param off_src               The offset within the source flash area to
+ *                                  copy from.
+ * @param off_dst               The offset within the destination flash area to
+ *                                  copy to.
+ * @param sz                    The number of bytes to copy.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+static int
+boot_copy_region(struct boot_loader_state *state,
+                 const struct flash_area *fap_src,
+                 const struct flash_area *fap_dst,
+                 uint32_t off_src, uint32_t off_dst, uint32_t sz)
+{
+    uint32_t bytes_copied;
+    int chunk_sz;
+    int rc;
+
+    static uint8_t buf[1024];
+
+    (void)state;
+
+    bytes_copied = 0;
+    while (bytes_copied < sz) {
+        if (sz - bytes_copied > sizeof(buf)) {
+            chunk_sz = sizeof(buf);
+        } else {
+            chunk_sz = sz - bytes_copied;
+        }
+
+        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
+        if (rc != 0) {
+            return BOOT_EFLASH;
+        }
+
+        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
+        if (rc != 0) {
+            return BOOT_EFLASH;
+        }
+
+        bytes_copied += chunk_sz;
+    }
+
+    return 0;
+}
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+static inline int
+boot_status_init(const struct boot_loader_state *state,
+                 const struct flash_area *fap,
+                 const struct boot_status *bs)
+{
+    struct boot_swap_state swap_state;
+    uint8_t image_index;
+    int rc;
+
+#if (BOOT_IMAGE_NUMBER == 1)
+    (void)state;
+#endif
+
+    image_index = BOOT_CURR_IMG(state);
+
+    BOOT_LOG_DBG("initializing status; fa_id=%d", fap->fa_id);
+
+    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
+            &swap_state);
+    assert(rc == 0);
+
+    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
+        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
+        assert(rc == 0);
+    }
+
+    if (swap_state.image_ok == BOOT_FLAG_SET) {
+        rc = boot_write_image_ok(fap);
+        assert(rc == 0);
+    }
+
+    rc = boot_write_swap_size(fap, bs->swap_size);
+    assert(rc == 0);
+
+    rc = boot_write_magic(fap);
+    assert(rc == 0);
+
+    return 0;
+}
+
+static int
+boot_erase_trailer_sectors(const struct boot_loader_state *state,
+                           const struct flash_area *fap)
+{
+    uint8_t slot;
+    uint32_t sector;
+    uint32_t trailer_sz;
+    uint32_t total_sz;
+    uint32_t off;
+    uint32_t sz;
+    int fa_id_primary;
+    int fa_id_secondary;
+    uint8_t image_index;
+    int rc;
+
+    BOOT_LOG_DBG("erasing trailer; fa_id=%d", fap->fa_id);
+
+    image_index = BOOT_CURR_IMG(state);
+    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
+            BOOT_PRIMARY_SLOT);
+    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
+            BOOT_SECONDARY_SLOT);
+
+    if (fap->fa_id == fa_id_primary) {
+        slot = BOOT_PRIMARY_SLOT;
+    } else if (fap->fa_id == fa_id_secondary) {
+        slot = BOOT_SECONDARY_SLOT;
+    } else {
+        return BOOT_EFLASH;
+    }
+
+    /* delete starting from last sector and moving to beginning */
+    sector = boot_img_num_sectors(state, slot) - 1;
+    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
+    total_sz = 0;
+    do {
+        sz = boot_img_sector_size(state, slot, sector);
+        off = boot_img_sector_off(state, slot, sector);
+        rc = boot_erase_region(fap, off, sz);
+        assert(rc == 0);
+
+        sector--;
+        total_sz += sz;
+    } while (total_sz < trailer_sz);
+
+    return rc;
+}
+
+/**
+ * Swaps the contents of two flash regions within the two image slots.
+ *
+ * @param idx                   The index of the first sector in the range of
+ *                                  sectors being swapped.
+ * @param sz                    The number of bytes to swap.
+ * @param bs                    The current boot status.  This struct gets
+ *                                  updated according to the outcome.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+static void
+boot_swap_sectors(int idx, uint32_t sz, struct boot_loader_state *state,
+        struct boot_status *bs)
+{
+    const struct flash_area *fap_primary_slot;
+    const struct flash_area *fap_secondary_slot;
+    const struct flash_area *fap_scratch;
+    uint32_t copy_sz;
+    uint32_t trailer_sz;
+    uint32_t img_off;
+    uint32_t scratch_trailer_off;
+    struct boot_swap_state swap_state;
+    size_t last_sector;
+    bool erase_scratch;
+    uint8_t image_index;
+    int rc;
+
+    /* Calculate offset from start of image area. */
+    img_off = boot_img_sector_off(state, BOOT_PRIMARY_SLOT, idx);
+
+    copy_sz = sz;
+    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
+
+    /* sz in this function is always sized on a multiple of the sector size.
+     * The check against the start offset of the last sector
+     * is to determine if we're swapping the last sector. The last sector
+     * needs special handling because it's where the trailer lives. If we're
+     * copying it, we need to use scratch to write the trailer temporarily.
+     *
+     * NOTE: `use_scratch` is a temporary flag (never written to flash) which
+     * controls if special handling is needed (swapping last sector).
+     */
+    last_sector = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
+    if ((img_off + sz) >
+        boot_img_sector_off(state, BOOT_PRIMARY_SLOT, last_sector)) {
+        copy_sz -= trailer_sz;
+    }
+
+    bs->use_scratch = (bs->idx == BOOT_STATUS_IDX_0 && copy_sz != sz);
+
+    image_index = BOOT_CURR_IMG(state);
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
+            &fap_primary_slot);
+    assert (rc == 0);
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index),
+            &fap_secondary_slot);
+    assert (rc == 0);
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_SCRATCH, &fap_scratch);
+    assert (rc == 0);
+
+    if (bs->state == BOOT_STATUS_STATE_0) {
+        BOOT_LOG_DBG("erasing scratch area");
+        rc = boot_erase_region(fap_scratch, 0, fap_scratch->fa_size);
+        assert(rc == 0);
+
+        if (bs->idx == BOOT_STATUS_IDX_0) {
+            /* Write a trailer to the scratch area, even if we don't need the
+             * scratch area for status.  We need a temporary place to store the
+             * `swap-type` while we erase the primary trailer.
+             */
+            rc = boot_status_init(state, fap_scratch, bs);
+            assert(rc == 0);
+
+            if (!bs->use_scratch) {
+                /* Prepare the primary status area... here it is known that the
+                 * last sector is not being used by the image data so it's safe
+                 * to erase.
+                 */
+                rc = boot_erase_trailer_sectors(state, fap_primary_slot);
+                assert(rc == 0);
+
+                rc = boot_status_init(state, fap_primary_slot, bs);
+                assert(rc == 0);
+
+                /* Erase the temporary trailer from the scratch area. */
+                rc = boot_erase_region(fap_scratch, 0, fap_scratch->fa_size);
+                assert(rc == 0);
+            }
+        }
+
+        rc = boot_copy_region(state, fap_secondary_slot, fap_scratch,
+                              img_off, 0, copy_sz);
+        assert(rc == 0);
+
+        rc = boot_write_status(state, bs);
+        bs->state = BOOT_STATUS_STATE_1;
+        BOOT_STATUS_ASSERT(rc == 0);
+    }
+
+    if (bs->state == BOOT_STATUS_STATE_1) {
+        rc = boot_erase_region(fap_secondary_slot, img_off, sz);
+        assert(rc == 0);
+
+        rc = boot_copy_region(state, fap_primary_slot, fap_secondary_slot,
+                              img_off, img_off, copy_sz);
+        assert(rc == 0);
+
+        if (bs->idx == BOOT_STATUS_IDX_0 && !bs->use_scratch) {
+            /* If not all sectors of the slot are being swapped,
+             * guarantee here that only the primary slot will have the state.
+             */
+            rc = boot_erase_trailer_sectors(state, fap_secondary_slot);
+            assert(rc == 0);
+        }
+
+        rc = boot_write_status(state, bs);
+        bs->state = BOOT_STATUS_STATE_2;
+        BOOT_STATUS_ASSERT(rc == 0);
+    }
+
+    if (bs->state == BOOT_STATUS_STATE_2) {
+        rc = boot_erase_region(fap_primary_slot, img_off, sz);
+        assert(rc == 0);
+
+        /* NOTE: If this is the final sector, we exclude the image trailer from
+         * this copy (copy_sz was truncated earlier).
+         */
+        rc = boot_copy_region(state, fap_scratch, fap_primary_slot,
+                              0, img_off, copy_sz);
+        assert(rc == 0);
+
+        if (bs->use_scratch) {
+            scratch_trailer_off = boot_status_off(fap_scratch);
+
+            /* copy current status that is being maintained in scratch */
+            rc = boot_copy_region(state, fap_scratch, fap_primary_slot,
+                        scratch_trailer_off, img_off + copy_sz,
+                        (BOOT_STATUS_STATE_COUNT - 1) * BOOT_WRITE_SZ(state));
+            BOOT_STATUS_ASSERT(rc == 0);
+
+            rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SCRATCH,
+                                            &swap_state);
+            assert(rc == 0);
+
+            if (swap_state.image_ok == BOOT_FLAG_SET) {
+                rc = boot_write_image_ok(fap_primary_slot);
+                assert(rc == 0);
+            }
+
+            if (swap_state.swap_type != BOOT_SWAP_TYPE_NONE) {
+                rc = boot_write_swap_info(fap_primary_slot,
+                                          swap_state.swap_type,
+                                          image_index);
+                assert(rc == 0);
+            }
+
+            rc = boot_write_swap_size(fap_primary_slot, bs->swap_size);
+            assert(rc == 0);
+
+            rc = boot_write_magic(fap_primary_slot);
+            assert(rc == 0);
+        }
+
+        /* If we wrote a trailer to the scratch area, erase it after we persist
+         * a trailer to the primary slot.  We do this to prevent mcuboot from
+         * reading a stale status from the scratch area in case of immediate
+         * reset.
+         */
+        erase_scratch = bs->use_scratch;
+        bs->use_scratch = 0;
+
+        rc = boot_write_status(state, bs);
+        bs->idx++;
+        bs->state = BOOT_STATUS_STATE_0;
+        BOOT_STATUS_ASSERT(rc == 0);
+
+        if (erase_scratch) {
+            rc = boot_erase_region(fap_scratch, 0, sz);
+            assert(rc == 0);
+        }
+    }
+
+    flash_area_close(fap_primary_slot);
+    flash_area_close(fap_secondary_slot);
+    flash_area_close(fap_scratch);
+}
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+
+/**
+ * Overwrite primary slot with the image contained in the secondary slot.
+ * If a prior copy operation was interrupted by a system reset, this function
+ * redos the copy.
+ *
+ * @param bs                    The current boot status.  This function reads
+ *                                  this struct to determine if it is resuming
+ *                                  an interrupted swap operation.  This
+ *                                  function writes the updated status to this
+ *                                  function on return.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+#ifdef MCUBOOT_OVERWRITE_ONLY
+static int
+boot_copy_image(struct boot_loader_state *state, struct boot_status *bs)
+{
+    size_t sect_count;
+    size_t sect;
+    int rc;
+    size_t size;
+    size_t this_size;
+    size_t last_sector;
+    const struct flash_area *fap_primary_slot;
+    const struct flash_area *fap_secondary_slot;
+    uint8_t image_index;
+
+    (void)bs;
+
+    BOOT_LOG_INF("Image upgrade secondary slot -> primary slot");
+    BOOT_LOG_INF("Erasing the primary slot");
+
+    image_index = BOOT_CURR_IMG(state);
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
+            &fap_primary_slot);
+    assert (rc == 0);
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index),
+            &fap_secondary_slot);
+    assert (rc == 0);
+
+    sect_count = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
+    for (sect = 0, size = 0; sect < sect_count; sect++) {
+        this_size = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, sect);
+        rc = boot_erase_region(fap_primary_slot, size, this_size);
+        assert(rc == 0);
+
+        size += this_size;
+    }
+
+    BOOT_LOG_INF("Copying the secondary slot to the primary slot: 0x%zx bytes",
+                 size);
+    rc = boot_copy_region(state, fap_secondary_slot, fap_primary_slot,
+                          0, 0, size);
+
+    /* Update the stored security counter with the new image's security counter
+     * value. Both slots hold the new image at this point, but the secondary
+     * slot's image header must be passed because the read image headers in the
+     * boot_data structure have not been updated yet.
+     */
+    rc = boot_update_security_counter(BOOT_CURR_IMG(state), BOOT_PRIMARY_SLOT,
+                                boot_img_hdr(state, BOOT_SECONDARY_SLOT));
+    if (rc != 0) {
+        BOOT_LOG_ERR("Security counter update failed after image upgrade.");
+        return rc;
+    }
+
+    /*
+     * Erases header and trailer. The trailer is erased because when a new
+     * image is written without a trailer as is the case when using newt, the
+     * trailer that was left might trigger a new upgrade.
+     */
+    BOOT_LOG_DBG("erasing secondary header");
+    rc = boot_erase_region(fap_secondary_slot,
+                           boot_img_sector_off(state, BOOT_SECONDARY_SLOT, 0),
+                           boot_img_sector_size(state, BOOT_SECONDARY_SLOT, 0));
+    assert(rc == 0);
+    last_sector = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT) - 1;
+    BOOT_LOG_DBG("erasing secondary trailer");
+    rc = boot_erase_region(fap_secondary_slot,
+                           boot_img_sector_off(state, BOOT_SECONDARY_SLOT,
+                               last_sector),
+                           boot_img_sector_size(state, BOOT_SECONDARY_SLOT,
+                               last_sector));
+    assert(rc == 0);
+
+    flash_area_close(fap_primary_slot);
+    flash_area_close(fap_secondary_slot);
+
+    /* TODO: Perhaps verify the primary slot's signature again? */
+
+    return 0;
+}
+#else
+/**
+ * Swaps the two images in flash.  If a prior copy operation was interrupted
+ * by a system reset, this function completes that operation.
+ *
+ * @param bs                    The current boot status.  This function reads
+ *                                  this struct to determine if it is resuming
+ *                                  an interrupted swap operation.  This
+ *                                  function writes the updated status to this
+ *                                  function on return.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+static int
+boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
+{
+    uint32_t sz;
+    int first_sector_idx;
+    int last_sector_idx;
+    int last_idx_secondary_slot;
+    uint32_t swap_idx;
+    struct image_header *hdr;
+    uint32_t size;
+    uint32_t copy_size;
+    uint32_t primary_slot_size;
+    uint32_t secondary_slot_size;
+    uint8_t image_index;
+    int rc;
+
+    /* FIXME: just do this if asked by user? */
+
+    size = copy_size = 0;
+    image_index = BOOT_CURR_IMG(state);
+
+    if (bs->idx == BOOT_STATUS_IDX_0 && bs->state == BOOT_STATUS_STATE_0) {
+        /*
+         * No swap ever happened, so need to find the largest image which
+         * will be used to determine the amount of sectors to swap.
+         */
+        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
+        if (hdr->ih_magic == IMAGE_MAGIC) {
+            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, ©_size);
+            assert(rc == 0);
+        }
+
+        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
+        if (hdr->ih_magic == IMAGE_MAGIC) {
+            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
+            assert(rc == 0);
+        }
+
+        if (size > copy_size) {
+            copy_size = size;
+        }
+
+        bs->swap_size = copy_size;
+    } else {
+        /*
+         * If a swap was under way, the swap_size should already be present
+         * in the trailer...
+         */
+        rc = boot_read_swap_size(image_index, &bs->swap_size);
+        assert(rc == 0);
+
+        copy_size = bs->swap_size;
+    }
+
+    primary_slot_size = 0;
+    secondary_slot_size = 0;
+    last_sector_idx = 0;
+    last_idx_secondary_slot = 0;
+
+    /*
+     * Knowing the size of the largest image between both slots, here we
+     * find what is the last sector in the primary slot that needs swapping.
+     * Since we already know that both slots are compatible, the secondary
+     * slot's last sector is not really required after this check is finished.
+     */
+    while (1) {
+        if ((primary_slot_size < copy_size) ||
+            (primary_slot_size < secondary_slot_size)) {
+           primary_slot_size += boot_img_sector_size(state,
+                                                     BOOT_PRIMARY_SLOT,
+                                                     last_sector_idx);
+        }
+        if ((secondary_slot_size < copy_size) ||
+            (secondary_slot_size < primary_slot_size)) {
+           secondary_slot_size += boot_img_sector_size(state,
+                                                       BOOT_SECONDARY_SLOT,
+                                                       last_idx_secondary_slot);
+        }
+        if (primary_slot_size >= copy_size &&
+                secondary_slot_size >= copy_size &&
+                primary_slot_size == secondary_slot_size) {
+            break;
+        }
+        last_sector_idx++;
+        last_idx_secondary_slot++;
+    }
+
+    swap_idx = 0;
+    while (last_sector_idx >= 0) {
+        sz = boot_copy_sz(state, last_sector_idx, &first_sector_idx);
+        if (swap_idx >= (bs->idx - BOOT_STATUS_IDX_0)) {
+            boot_swap_sectors(first_sector_idx, sz, state, bs);
+        }
+
+        last_sector_idx = first_sector_idx - 1;
+        swap_idx++;
+    }
+
+#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
+    if (boot_status_fails > 0) {
+        BOOT_LOG_WRN("%d status write fails performing the swap",
+                     boot_status_fails);
+    }
+#endif
+
+    return 0;
+}
+#endif
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+/**
+ * Marks the image in the primary slot as fully copied.
+ */
+static int
+boot_set_copy_done(uint8_t image_index)
+{
+    const struct flash_area *fap;
+    int rc;
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
+            &fap);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_write_copy_done(fap);
+    flash_area_close(fap);
+    return rc;
+}
+
+/**
+ * Marks a reverted image in the primary slot as confirmed. This is necessary to
+ * ensure the status bytes from the image revert operation don't get processed
+ * on a subsequent boot.
+ *
+ * NOTE: image_ok is tested before writing because if there's a valid permanent
+ * image installed on the primary slot and the new image to be upgrade to has a
+ * bad sig, image_ok would be overwritten.
+ */
+static int
+boot_set_image_ok(uint8_t image_index)
+{
+    const struct flash_area *fap;
+    struct boot_swap_state state;
+    int rc;
+
+    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
+            &fap);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    rc = boot_read_swap_state(fap, &state);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto out;
+    }
+
+    if (state.image_ok == BOOT_FLAG_UNSET) {
+        rc = boot_write_image_ok(fap);
+    }
+
+out:
+    flash_area_close(fap);
+    return rc;
+}
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+
+#if (BOOT_IMAGE_NUMBER > 1)
+/**
+ * Check if the version of the image is not older than required.
+ *
+ * @param req         Required minimal image version.
+ * @param ver         Version of the image to be checked.
+ *
+ * @return            0 if the version is sufficient, nonzero otherwise.
+ */
+static int
+boot_is_version_sufficient(struct image_version *req,
+                           struct image_version *ver)
+{
+    if (ver->iv_major > req->iv_major) {
+        return 0;
+    }
+    if (ver->iv_major < req->iv_major) {
+        return BOOT_EBADVERSION;
+    }
+    /* The major version numbers are equal. */
+    if (ver->iv_minor > req->iv_minor) {
+        return 0;
+    }
+    if (ver->iv_minor < req->iv_minor) {
+        return BOOT_EBADVERSION;
+    }
+    /* The minor version numbers are equal. */
+    if (ver->iv_revision < req->iv_revision) {
+        return BOOT_EBADVERSION;
+    }
+
+    return 0;
+}
+
+/**
+ * Check the image dependency whether it is satisfied and modify
+ * the swap type if necessary.
+ *
+ * @param dep               Image dependency which has to be verified.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+static int
+boot_verify_slot_dependency(struct boot_loader_state *state,
+                            struct image_dependency *dep)
+{
+    struct image_version *dep_version;
+    size_t dep_slot;
+    int rc;
+    uint8_t swap_type;
+
+    /* Determine the source of the image which is the subject of
+     * the dependency and get it's version. */
+    swap_type = state->swap_type[dep->image_id];
+    dep_slot = (swap_type != BOOT_SWAP_TYPE_NONE) ?
+                BOOT_SECONDARY_SLOT : BOOT_PRIMARY_SLOT;
+    dep_version = &state->imgs[dep->image_id][dep_slot].hdr.ih_ver;
+
+    rc = boot_is_version_sufficient(&dep->image_min_version, dep_version);
+    if (rc != 0) {
+        /* Dependency not satisfied.
+         * Modify the swap type to decrease the version number of the image
+         * (which will be located in the primary slot after the boot process),
+         * consequently the number of unsatisfied dependencies will be
+         * decreased or remain the same.
+         */
+        switch (BOOT_SWAP_TYPE(state)) {
+        case BOOT_SWAP_TYPE_TEST:
+        case BOOT_SWAP_TYPE_PERM:
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+            break;
+        case BOOT_SWAP_TYPE_NONE:
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_REVERT;
+            break;
+        default:
+            break;
+        }
+    }
+
+    return rc;
+}
+
+/**
+ * Read all dependency TLVs of an image from the flash and verify
+ * one after another to see if they are all satisfied.
+ *
+ * @param slot              Image slot number.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+static int
+boot_verify_slot_dependencies(struct boot_loader_state *state, uint32_t slot)
+{
+    const struct flash_area *fap;
+    struct image_tlv_iter it;
+    struct image_dependency dep;
+    uint32_t off;
+    uint16_t len;
+    int area_id;
+    int rc;
+
+    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+    rc = flash_area_open(area_id, &fap);
+    if (rc != 0) {
+        rc = BOOT_EFLASH;
+        goto done;
+    }
+
+    rc = bootutil_tlv_iter_begin(&it, boot_img_hdr(state, slot), fap,
+            IMAGE_TLV_DEPENDENCY, true);
+    if (rc != 0) {
+        goto done;
+    }
+
+    while (true) {
+        rc = bootutil_tlv_iter_next(&it, &off, &len, NULL);
+        if (rc < 0) {
+            return -1;
+        } else if (rc > 0) {
+            rc = 0;
+            break;
+        }
+
+        if (len != sizeof(dep)) {
+            rc = BOOT_EBADIMAGE;
+            goto done;
+        }
+
+        rc = flash_area_read(fap, off, &dep, len);
+        if (rc != 0) {
+            rc = BOOT_EFLASH;
+            goto done;
+        }
+
+        if (dep.image_id >= BOOT_IMAGE_NUMBER) {
+            rc = BOOT_EBADARGS;
+            goto done;
+        }
+
+        /* Verify dependency and modify the swap type if not satisfied. */
+        rc = boot_verify_slot_dependency(state, &dep);
+        if (rc != 0) {
+            /* Dependency not satisfied. */
+            goto done;
+        }
+    }
+
+done:
+    flash_area_close(fap);
+    return rc;
+}
+
+/**
+ * Iterate over all the images and verify whether the image dependencies in the
+ * TLV area are all satisfied and update the related swap type if necessary.
+ */
+static int
+boot_verify_dependencies(struct boot_loader_state *state)
+{
+    int rc;
+    uint8_t slot;
+
+    BOOT_CURR_IMG(state) = 0;
+    while (BOOT_CURR_IMG(state) < BOOT_IMAGE_NUMBER) {
+        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE &&
+            BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_FAIL) {
+            slot = BOOT_SECONDARY_SLOT;
+        } else {
+            slot = BOOT_PRIMARY_SLOT;
+        }
+
+        rc = boot_verify_slot_dependencies(state, slot);
+        if (rc == 0) {
+            /* All dependencies've been satisfied, continue with next image. */
+            BOOT_CURR_IMG(state)++;
+        } else if (rc == BOOT_EBADVERSION) {
+            /* Cannot upgrade due to non-met dependencies, so disable all
+             * image upgrades.
+             */
+            for (int idx = 0; idx < BOOT_IMAGE_NUMBER; idx++) {
+                BOOT_CURR_IMG(state) = idx;
+                BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+            }
+            break;
+        } else {
+            /* Other error happened, images are inconsistent */
+            return rc;
+        }
+    }
+    return rc;
+}
+#endif /* (BOOT_IMAGE_NUMBER > 1) */
+
+/**
+ * Performs a clean (not aborted) image update.
+ *
+ * @param bs                    The current boot status.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+static int
+boot_perform_update(struct boot_loader_state *state, struct boot_status *bs)
+{
+    int rc;
+#ifndef MCUBOOT_OVERWRITE_ONLY
+    uint8_t swap_type;
+#endif
+
+    /* At this point there are no aborted swaps. */
+#if defined(MCUBOOT_OVERWRITE_ONLY)
+    rc = boot_copy_image(state, bs);
+#else
+    rc = boot_swap_image(state, bs);
+#endif
+    assert(rc == 0);
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+    /* The following state needs image_ok be explicitly set after the
+     * swap was finished to avoid a new revert.
+     */
+    swap_type = BOOT_SWAP_TYPE(state);
+    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
+        swap_type == BOOT_SWAP_TYPE_PERM) {
+        rc = boot_set_image_ok(BOOT_CURR_IMG(state));
+        if (rc != 0) {
+            BOOT_SWAP_TYPE(state) = swap_type = BOOT_SWAP_TYPE_PANIC;
+        }
+    }
+
+    if (swap_type == BOOT_SWAP_TYPE_PERM) {
+        /* Update the stored security counter with the new image's security
+         * counter value. The primary slot holds the new image at this
+         * point, but the secondary slot's image header must be passed
+         * because the read image headers in the boot_data structure have
+         * not been updated yet.
+         *
+         * In case of a permanent image swap mcuboot will never attempt to
+         * revert the images on the next reboot. Therefore, the security
+         * counter must be increased right after the image upgrade.
+         */
+        rc = boot_update_security_counter(
+                                    BOOT_CURR_IMG(state),
+                                    BOOT_PRIMARY_SLOT,
+                                    boot_img_hdr(state, BOOT_SECONDARY_SLOT));
+        if (rc != 0) {
+            BOOT_LOG_ERR("Security counter update failed after "
+                         "image upgrade.");
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+        }
+    }
+
+    if (BOOT_IS_UPGRADE(swap_type)) {
+        rc = boot_set_copy_done(BOOT_CURR_IMG(state));
+        if (rc != 0) {
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+        }
+    }
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+
+    return rc;
+}
+
+/**
+ * Completes a previously aborted image swap.
+ *
+ * @param bs                    The current boot status.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+#if !defined(MCUBOOT_OVERWRITE_ONLY)
+static int
+boot_complete_partial_swap(struct boot_loader_state *state,
+        struct boot_status *bs)
+{
+    int rc;
+
+    /* Determine the type of swap operation being resumed from the
+     * `swap-type` trailer field.
+     */
+    rc = boot_swap_image(state, bs);
+    assert(rc == 0);
+
+    BOOT_SWAP_TYPE(state) = bs->swap_type;
+
+    /* The following states need image_ok be explicitly set after the
+     * swap was finished to avoid a new revert.
+     */
+    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
+        bs->swap_type == BOOT_SWAP_TYPE_PERM) {
+        rc = boot_set_image_ok(BOOT_CURR_IMG(state));
+        if (rc != 0) {
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+        }
+    }
+
+    if (BOOT_IS_UPGRADE(bs->swap_type)) {
+        rc = boot_set_copy_done(BOOT_CURR_IMG(state));
+        if (rc != 0) {
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+        }
+    }
+
+    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
+        BOOT_LOG_ERR("panic!");
+        assert(0);
+
+        /* Loop forever... */
+        while (1) {}
+    }
+
+    return rc;
+}
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+
+#if (BOOT_IMAGE_NUMBER > 1)
+/**
+ * Review the validity of previously determined swap types of other images.
+ *
+ * @param aborted_swap          The current image upgrade is a
+ *                              partial/aborted swap.
+ */
+static void
+boot_review_image_swap_types(struct boot_loader_state *state,
+                             bool aborted_swap)
+{
+    /* In that case if we rebooted in the middle of an image upgrade process, we
+     * must review the validity of swap types, that were previously determined
+     * for other images. The image_ok flag had not been set before the reboot
+     * for any of the updated images (only the copy_done flag) and thus falsely
+     * the REVERT swap type has been determined for the previous images that had
+     * been updated before the reboot.
+     *
+     * There are two separate scenarios that we have to deal with:
+     *
+     * 1. The reboot has happened during swapping an image:
+     *      The current image upgrade has been determined as a
+     *      partial/aborted swap.
+     * 2. The reboot has happened between two separate image upgrades:
+     *      In this scenario we must check the swap type of the current image.
+     *      In those cases if it is NONE or REVERT we cannot certainly determine
+     *      the fact of a reboot. In a consistent state images must move in the
+     *      same direction or stay in place, e.g. in practice REVERT and TEST
+     *      swap types cannot be present at the same time. If the swap type of
+     *      the current image is either TEST, PERM or FAIL we must review the
+     *      already determined swap types of other images and set each false
+     *      REVERT swap types to NONE (these images had been successfully
+     *      updated before the system rebooted between two separate image
+     *      upgrades).
+     */
+
+    if (BOOT_CURR_IMG(state) == 0) {
+        /* Nothing to do */
+        return;
+    }
+
+    if (!aborted_swap) {
+        if ((BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_NONE) ||
+            (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_REVERT)) {
+            /* Nothing to do */
+            return;
+        }
+    }
+
+    for (uint8_t i = 0; i < BOOT_CURR_IMG(state); i++) {
+        if (state->swap_type[i] == BOOT_SWAP_TYPE_REVERT) {
+            state->swap_type[i] = BOOT_SWAP_TYPE_NONE;
+        }
+    }
+}
+#endif
+
+/**
+ * Prepare image to be updated if required.
+ *
+ * Prepare image to be updated if required with completing an image swap
+ * operation if one was aborted and/or determining the type of the
+ * swap operation. In case of any error set the swap type to NONE.
+ *
+ * @param state                 Boot loader status information.
+ * @param bs                    Pointer where the read and possibly updated
+ *                              boot status can be written to.
+ */
+static void
+boot_prepare_image_for_update(struct boot_loader_state *state,
+                              struct boot_status *bs)
+{
+    int rc;
+
+    /* Determine the sector layout of the image slots and scratch area. */
+    rc = boot_read_sectors(state);
+    if (rc != 0) {
+        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d"
+                     " - too small?", BOOT_MAX_IMG_SECTORS);
+        /* Unable to determine sector layout, continue with next image
+         * if there is one.
+         */
+        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+        return;
+    }
+
+    /* Attempt to read an image header from each slot. */
+    rc = boot_read_image_headers(state, false);
+    if (rc != 0) {
+        /* Continue with next image if there is one. */
+        BOOT_LOG_WRN("Failed reading image headers; Image=%u",
+                BOOT_CURR_IMG(state));
+        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+        return;
+    }
+
+    /* If the current image's slots aren't compatible, no swap is possible.
+     * Just boot into primary slot.
+     */
+    if (boot_slots_compatible(state)) {
+        rc = boot_read_status(state, bs);
+        if (rc != 0) {
+            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
+                    BOOT_CURR_IMG(state));
+            /* Continue with next image if there is one. */
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+            return;
+        }
+
+        /* Determine if we rebooted in the middle of an image swap
+         * operation. If a partial swap was detected, complete it.
+         */
+        if (bs->idx != BOOT_STATUS_IDX_0 || bs->state != BOOT_STATUS_STATE_0) {
+
+#if (BOOT_IMAGE_NUMBER > 1)
+            boot_review_image_swap_types(state, true);
+#endif
+
+#ifdef MCUBOOT_OVERWRITE_ONLY
+            /* Should never arrive here, overwrite-only mode has
+             * no swap state.
+             */
+            assert(0);
+#else
+            /* Determine the type of swap operation being resumed from the
+             * `swap-type` trailer field.
+             */
+            rc = boot_complete_partial_swap(state, bs);
+            assert(rc == 0);
+#endif
+            /* Attempt to read an image header from each slot. Ensure that
+             * image headers in slots are aligned with headers in boot_data.
+             */
+            rc = boot_read_image_headers(state, false);
+            assert(rc == 0);
+
+            /* Swap has finished set to NONE */
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+        } else {
+            /* There was no partial swap, determine swap type. */
+            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
+                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
+            } else if (boot_validate_slot(state,
+                                          BOOT_SECONDARY_SLOT, bs) != 0) {
+                BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
+            } else {
+                BOOT_SWAP_TYPE(state) = bs->swap_type;
+            }
+
+#if (BOOT_IMAGE_NUMBER > 1)
+            boot_review_image_swap_types(state, false);
+#endif
+        }
+    } else {
+        /* In that case if slots are not compatible. */
+        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
+    }
+}
+
+/**
+ * Prepares the booting process.  This function moves images around in flash as
+ * appropriate, and tells you what address to boot from.
+ *
+ * @param state                 Boot loader status information.
+ * @param rsp                   On success, indicates how booting should occur.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+int
+context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
+{
+    size_t slot;
+    struct boot_status bs;
+    int rc = 0;
+    int fa_id;
+    int image_index;
+    bool has_upgrade;
+
+    /* The array of slot sectors are defined here (as opposed to file scope) so
+     * that they don't get allocated for non-boot-loader apps.  This is
+     * necessary because the gcc option "-fdata-sections" doesn't seem to have
+     * any effect in older gcc versions (e.g., 4.8.4).
+     */
+    static boot_sector_t
+        primary_slot_sectors[BOOT_IMAGE_NUMBER][BOOT_MAX_IMG_SECTORS];
+    static boot_sector_t
+        secondary_slot_sectors[BOOT_IMAGE_NUMBER][BOOT_MAX_IMG_SECTORS];
+    static boot_sector_t scratch_sectors[BOOT_MAX_IMG_SECTORS];
+
+    /* Iterate over all the images. By the end of the loop the swap type has
+     * to be determined for each image and all aborted swaps have to be
+     * completed.
+     */
+    IMAGES_ITER(BOOT_CURR_IMG(state)) {
+
+        image_index = BOOT_CURR_IMG(state);
+
+        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
+            primary_slot_sectors[image_index];
+        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
+            secondary_slot_sectors[image_index];
+        state->scratch.sectors = scratch_sectors;
+
+        /* Open primary and secondary image areas for the duration
+         * of this call.
+         */
+        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
+            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
+            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
+            assert(rc == 0);
+        }
+        rc = flash_area_open(FLASH_AREA_IMAGE_SCRATCH,
+                             &BOOT_SCRATCH_AREA(state));
+        assert(rc == 0);
+
+        /* Determine swap type and complete swap if it has been aborted. */
+        boot_prepare_image_for_update(state, &bs);
+
+        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
+            has_upgrade = true;
+        }
+    }
+
+#if (BOOT_IMAGE_NUMBER > 1)
+    if (has_upgrade) {
+        /* Iterate over all the images and verify whether the image dependencies
+         * are all satisfied and update swap type if necessary.
+         */
+        rc = boot_verify_dependencies(state);
+        if (rc == BOOT_EBADVERSION) {
+            /*
+             * It was impossible to upgrade because the expected dependency
+             * version was not available. Here we already changed the swap_type
+             * so that instead of asserting the bootloader, we continue and no
+             * upgrade is performed.
+             */
+            rc = 0;
+        }
+    }
+#endif
+
+    /* Iterate over all the images. At this point there are no aborted swaps
+     * and the swap types are determined for each image. By the end of the loop
+     * all required update operations will have been finished.
+     */
+    IMAGES_ITER(BOOT_CURR_IMG(state)) {
+
+#if (BOOT_IMAGE_NUMBER > 1)
+        /* Indicate that swap is not aborted */
+        memset(&bs, 0, sizeof bs);
+        bs.idx = BOOT_STATUS_IDX_0;
+        bs.state = BOOT_STATUS_STATE_0;
+#endif /* (BOOT_IMAGE_NUMBER > 1) */
+
+        /* Set the previously determined swap type */
+        bs.swap_type = BOOT_SWAP_TYPE(state);
+
+        switch (BOOT_SWAP_TYPE(state)) {
+        case BOOT_SWAP_TYPE_NONE:
+            break;
+
+        case BOOT_SWAP_TYPE_TEST:          /* fallthrough */
+        case BOOT_SWAP_TYPE_PERM:          /* fallthrough */
+        case BOOT_SWAP_TYPE_REVERT:
+            rc = boot_perform_update(state, &bs);
+            assert(rc == 0);
+            break;
+
+        case BOOT_SWAP_TYPE_FAIL:
+            /* The image in secondary slot was invalid and is now erased. Ensure
+             * we don't try to boot into it again on the next reboot. Do this by
+             * pretending we just reverted back to primary slot.
+             */
+#ifndef MCUBOOT_OVERWRITE_ONLY
+            /* image_ok needs to be explicitly set to avoid a new revert. */
+            rc = boot_set_image_ok(BOOT_CURR_IMG(state));
+            if (rc != 0) {
+                BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+            }
+#endif /* !MCUBOOT_OVERWRITE_ONLY */
+            break;
+
+        default:
+            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
+        }
+
+        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
+            BOOT_LOG_ERR("panic!");
+            assert(0);
+
+            /* Loop forever... */
+            while (1) {}
+        }
+    }
+
+    /* Iterate over all the images. At this point all required update operations
+     * have finished. By the end of the loop each image in the primary slot will
+     * have been re-validated.
+     */
+    IMAGES_ITER(BOOT_CURR_IMG(state)) {
+        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
+            /* Attempt to read an image header from each slot. Ensure that image
+             * headers in slots are aligned with headers in boot_data.
+             */
+            rc = boot_read_image_headers(state, false);
+            if (rc != 0) {
+                goto out;
+            }
+            /* Since headers were reloaded, it can be assumed we just performed
+             * a swap or overwrite. Now the header info that should be used to
+             * provide the data for the bootstrap, which previously was at
+             * secondary slot, was updated to primary slot.
+             */
+        }
+
+#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
+        rc = boot_validate_slot(state, BOOT_PRIMARY_SLOT, NULL);
+        if (rc != 0) {
+            rc = BOOT_EBADIMAGE;
+            goto out;
+        }
+#else
+        /* Even if we're not re-validating the primary slot, we could be booting
+         * onto an empty flash chip. At least do a basic sanity check that
+         * the magic number on the image is OK.
+         */
+        if (!BOOT_IMG_HDR_IS_VALID(state, BOOT_PRIMARY_SLOT)) {
+            BOOT_LOG_ERR("bad image magic 0x%lx; Image=%u", (unsigned long)
+                         &boot_img_hdr(state, BOOT_PRIMARY_SLOT)->ih_magic,
+                         BOOT_CURR_IMG(state));
+            rc = BOOT_EBADIMAGE;
+            goto out;
+        }
+#endif /* MCUBOOT_VALIDATE_PRIMARY_SLOT */
+
+        /* Update the stored security counter with the active image's security
+         * counter value. It will be updated only if the new security counter is
+         * greater than the stored value.
+         *
+         * In case of a successful image swapping when the swap type is TEST the
+         * security counter can be increased only after a reset, when the swap
+         * type is NONE and the image has marked itself "OK" (the image_ok flag
+         * has been set). This way a "revert" swap can be performed if it's
+         * necessary.
+         */
+        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_NONE) {
+            rc = boot_update_security_counter(
+                                    BOOT_CURR_IMG(state),
+                                    BOOT_PRIMARY_SLOT,
+                                    boot_img_hdr(state, BOOT_PRIMARY_SLOT));
+            if (rc != 0) {
+                BOOT_LOG_ERR("Security counter update failed after image "
+                             "validation.");
+                goto out;
+            }
+        }
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+        /* Save boot status to shared memory area */
+#if (BOOT_IMAGE_NUMBER > 1)
+        rc = boot_save_boot_status((BOOT_CURR_IMG(state) == 0) ?
+                                   SW_SPE : SW_NSPE,
+                                   boot_img_hdr(state, BOOT_PRIMARY_SLOT),
+                                   BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT)
+                                  );
+#else
+        rc = boot_save_boot_status(SW_S_NS,
+                                   boot_img_hdr(state, BOOT_PRIMARY_SLOT),
+                                   BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT)
+                                  );
+#endif
+        if (rc) {
+            BOOT_LOG_ERR("Failed to add Image %u data to shared area",
+                         BOOT_CURR_IMG(state));
+        }
+#endif
+    }
+
+#if (BOOT_IMAGE_NUMBER > 1)
+    /* Always boot from the primary slot of Image 0. */
+    BOOT_CURR_IMG(state) = 0;
+#endif
+
+    rsp->br_flash_dev_id =
+            BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT)->fa_device_id;
+    rsp->br_image_off =
+            boot_img_slot_off(state, BOOT_PRIMARY_SLOT);
+    rsp->br_hdr =
+            boot_img_hdr(state, BOOT_PRIMARY_SLOT);
+
+out:
+    IMAGES_ITER(BOOT_CURR_IMG(state)) {
+        flash_area_close(BOOT_SCRATCH_AREA(state));
+        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
+            flash_area_close(BOOT_IMG_AREA(state,
+                                           BOOT_NUM_SLOTS - 1 - slot));
+        }
+    }
+    return rc;
+}
+
+#else /* MCUBOOT_NO_SWAP || MCUBOOT_RAM_LOADING */
+
+#define BOOT_LOG_IMAGE_INFO(area, hdr, state)                               \
+    BOOT_LOG_INF("Image %u: version=%u.%u.%u+%u, magic=%5s, image_ok=0x%x", \
+                 (area),                                                    \
+                 (hdr)->ih_ver.iv_major,                                    \
+                 (hdr)->ih_ver.iv_minor,                                    \
+                 (hdr)->ih_ver.iv_revision,                                 \
+                 (hdr)->ih_ver.iv_build_num,                                \
+                 ((state)->magic == BOOT_MAGIC_GOOD  ? "good"  :            \
+                  (state)->magic == BOOT_MAGIC_UNSET ? "unset" :            \
+                  "bad"),                                                   \
+                 (state)->image_ok)
+
+struct image_slot_version {
+    uint64_t version;
+    uint32_t slot_number;
+};
+
+/**
+ * Extract the version number from the image header. This function must be
+ * ported if version number format has changed in the image header.
+ *
+ * @param hdr  Pointer to an image header structure
+ *
+ * @return     Version number casted to uint64_t
+ */
+static uint64_t
+boot_get_version_number(struct image_header *hdr)
+{
+    uint64_t version = 0;
+    version |= (uint64_t)hdr->ih_ver.iv_major << (IMAGE_VER_MINOR_LENGTH
+                                                + IMAGE_VER_REVISION_LENGTH
+                                                + IMAGE_VER_BUILD_NUM_LENGTH);
+    version |= (uint64_t)hdr->ih_ver.iv_minor << (IMAGE_VER_REVISION_LENGTH
+                                                + IMAGE_VER_BUILD_NUM_LENGTH);
+    version |= (uint64_t)hdr->ih_ver.iv_revision << IMAGE_VER_BUILD_NUM_LENGTH;
+    version |= hdr->ih_ver.iv_build_num;
+    return version;
+}
+
+/**
+ * Comparator function for `qsort` to compare version numbers. This function
+ * must be ported if version number format has changed in the image header.
+ *
+ * @param ver1  Pointer to an array element which holds the version number
+ * @param ver2  Pointer to another array element which holds the version
+ *              number
+ *
+ * @return      if version1 >  version2  -1
+ *              if version1 == version2   0
+ *              if version1 <  version2   1
+ */
+static int
+boot_compare_version_numbers(const void *ver1, const void *ver2)
+{
+    if (((struct image_slot_version *)ver1)->version <
+        ((struct image_slot_version *)ver2)->version) {
+        return 1;
+    }
+
+    if (((struct image_slot_version *)ver1)->version ==
+        ((struct image_slot_version *)ver2)->version) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/**
+ * Sort the available images based on the version number and puts them in
+ * a list.
+ *
+ * @param state          Boot loader status information.
+ * @param boot_sequence  A pointer to an array, whose aim is to carry
+ *                       the boot order of candidate images.
+ * @param slot_cnt       The number of flash areas, which can contains firmware
+ *                       images.
+ *
+ * @return               The number of valid images.
+ */
+uint32_t
+boot_get_boot_sequence(struct boot_loader_state *state,
+                       uint32_t *boot_sequence, uint32_t slot_cnt)
+{
+    struct boot_swap_state slot_state;
+    struct image_header *hdr;
+    struct image_slot_version image_versions[BOOT_NUM_SLOTS] = {{0}};
+    uint32_t image_cnt = 0;
+    uint32_t slot;
+    int32_t rc;
+    int32_t fa_id;
+
+    for (slot = 0; slot < slot_cnt; slot++) {
+        hdr = boot_img_hdr(state, slot);
+        fa_id = flash_area_id_from_image_slot(slot);
+        rc = boot_read_swap_state_by_id(fa_id, &slot_state);
+        if (rc != 0) {
+            BOOT_LOG_ERR("Error during reading image trailer from slot: %u",
+                         slot);
+            continue;
+        }
+
+        if (BOOT_IMG_HDR_IS_VALID(state, slot)) {
+            if (slot_state.magic    == BOOT_MAGIC_GOOD ||
+                slot_state.image_ok == BOOT_FLAG_SET) {
+                /* Valid cases:
+                 *  - Test mode:      magic is OK in image trailer
+                 *  - Permanent mode: image_ok flag has previously set
+                 */
+                image_versions[slot].slot_number = slot;
+                image_versions[slot].version = boot_get_version_number(hdr);
+                image_cnt++;
+            }
+
+            BOOT_LOG_IMAGE_INFO(slot, hdr, &slot_state);
+        } else {
+            BOOT_LOG_INF("Image %u: No valid image", slot);
+        }
+    }
+
+    /* Sort the images based on version number */
+    qsort(&image_versions[0],
+          slot_cnt,
+          sizeof(struct image_slot_version),
+          boot_compare_version_numbers);
+
+    /* Copy the calculated boot sequence to boot_sequence array */
+    for (slot = 0; slot < slot_cnt; slot++) {
+        boot_sequence[slot] = image_versions[slot].slot_number;
+    }
+
+    return image_cnt;
+}
+
+#ifdef MCUBOOT_RAM_LOADING
+
+/**
+ * Verifies that the image in a slot lies within the predefined bounds that are
+ * allowed to be used by executable images.
+ *
+ * @param img_dst         The address to which the image is going to be copied.
+ *
+ * @param img_sz          The size of the image.
+ *
+ * @return                0 on success; nonzero on failure.
+ */
+static int
+boot_verify_ram_loading_address(uint32_t img_dst, uint32_t img_sz)
+{
+    uint32_t img_end_addr;
+
+    if (img_dst < IMAGE_EXECUTABLE_RAM_START) {
+        return BOOT_EBADIMAGE;
+    }
+
+    if (!boot_u32_safe_add(&img_end_addr, img_dst, img_sz)) {
+        return BOOT_EBADIMAGE;
+    }
+
+    if (img_end_addr > (IMAGE_EXECUTABLE_RAM_START +
+                        IMAGE_EXECUTABLE_RAM_SIZE)) {
+        return BOOT_EBADIMAGE;
+    }
+
+    return 0;
+}
+
+/**
+ * Copies an image from a slot in the flash to an SRAM address, where the load
+ * address has already been inserted into the image header by this point and is
+ * extracted from it within this method. The copying is done sector-by-sector.
+ *
+ * @param state           Boot loader status information.
+ * @param slot            The flash slot of the image to be copied to SRAM.
+ *
+ * @param hdr             Pointer to the image header structure of the image
+ *
+ * @param img_dst         The address at which the image needs to be copied to
+ *                        SRAM.
+ *
+ * @param img_sz          The size of the image that needs to be copied to SRAM.
+ *
+ * @return                0 on success; nonzero on failure.
+ */
+static int
+boot_copy_image_to_sram(struct boot_loader_state *state, int slot,
+                        struct image_header *hdr,
+                        uint32_t img_dst, uint32_t img_sz)
+{
+    int rc;
+    uint32_t sect_sz;
+    uint32_t sect = 0;
+    uint32_t bytes_copied = 0;
+    const struct flash_area *fap_src = NULL;
+
+    if (img_dst % 4 != 0) {
+        BOOT_LOG_INF("Cannot copy the image to the SRAM address 0x%x "
+        "- the load address must be aligned with 4 bytes due to SRAM "
+        "restrictions", img_dst);
+        return BOOT_EBADARGS;
+    }
+
+    rc = flash_area_open(flash_area_id_from_image_slot(slot), &fap_src);
+    if (rc != 0) {
+        return BOOT_EFLASH;
+    }
+
+    while (bytes_copied < img_sz) {
+        sect_sz = boot_img_sector_size(state, slot, sect);
+        /*
+         * Direct copy from where the image sector resides in flash to its new
+         * location in SRAM
+         */
+        rc = flash_area_read(fap_src,
+                             bytes_copied,
+                             (void *)(img_dst + bytes_copied),
+                             sect_sz);
+        if (rc != 0) {
+            BOOT_LOG_INF("Error whilst copying image from Flash to SRAM");
+            break;
+        } else {
+            bytes_copied += sect_sz;
+        }
+        sect++;
+    }
+
+    if (fap_src) {
+        flash_area_close(fap_src);
+    }
+    return rc;
+}
+
+/**
+ * Removes an image from SRAM, by overwriting it with zeros.
+ *
+ * @param img_dst         The address of the image that needs to be removed from
+ *                        SRAM.
+ *
+ * @param img_sz          The size of the image that needs to be removed from
+ *                        SRAM.
+ *
+ * @return                0 on success; nonzero on failure.
+ */
+static int
+boot_remove_image_from_sram(uint32_t img_dst, uint32_t img_sz)
+{
+    BOOT_LOG_INF("Removing image from SRAM at address 0x%x", img_dst);
+    memset((void*)img_dst, 0, img_sz);
+
+    return 0;
+}
+#endif /* MCUBOOT_RAM_LOADING */
+
+/**
+ * Prepares the booting process. This function choose the newer image in flash
+ * as appropriate, and tells you what address to boot from.
+ *
+ * @param state                 Boot loader status information.
+ * @param rsp                   On success, indicates how booting should occur.
+ *
+ * @return                      0 on success; nonzero on failure.
+ */
+int
+context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
+{
+    size_t slot = 0;
+    int32_t i;
+    int rc;
+    int fa_id;
+    uint32_t boot_sequence[BOOT_NUM_SLOTS];
+    uint32_t img_cnt;
+    struct image_header *selected_image_header;
+#ifdef MCUBOOT_RAM_LOADING
+    int image_copied = 0;
+    uint32_t img_dst = 0;
+    uint32_t img_sz  = 0;
+#endif /* MCUBOOT_RAM_LOADING */
+
+    static boot_sector_t primary_slot_sectors[BOOT_MAX_IMG_SECTORS];
+    static boot_sector_t secondary_slot_sectors[BOOT_MAX_IMG_SECTORS];
+    static boot_sector_t scratch_sectors[BOOT_MAX_IMG_SECTORS];
+
+    BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors = primary_slot_sectors;
+    BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors = secondary_slot_sectors;
+    state->scratch.sectors = scratch_sectors;
+
+    /* Open boot_data image areas for the duration of this call. */
+    for (i = 0; i < BOOT_NUM_SLOTS; i++) {
+        fa_id = flash_area_id_from_image_slot(i);
+        rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, i));
+        assert(rc == 0);
+    }
+
+    /* Determine the sector layout of the image slots. */
+    rc = boot_read_sectors(state);
+    if (rc != 0) {
+        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d - "
+                     "too small?", BOOT_MAX_IMG_SECTORS);
+        goto out;
+    }
+
+    /* Attempt to read an image header from each slot. */
+    rc = boot_read_image_headers(state, false);
+    if (rc != 0) {
+        goto out;
+    }
+
+    img_cnt = boot_get_boot_sequence(state, boot_sequence, BOOT_NUM_SLOTS);
+    if (img_cnt) {
+        /* Authenticate images */
+        for (i = 0; i < img_cnt; i++) {
+
+            slot = boot_sequence[i];
+            selected_image_header = boot_img_hdr(state, slot);
+
+#ifdef MCUBOOT_RAM_LOADING
+            if (selected_image_header->ih_flags & IMAGE_F_RAM_LOAD) {
+
+                img_dst = selected_image_header->ih_load_addr;
+
+                rc = boot_read_image_size(state, slot, &img_sz);
+                if (rc != 0) {
+                    rc = BOOT_EFLASH;
+                    BOOT_LOG_INF("Could not load image headers from the image"
+                                 "in the %s slot.",
+                                 (slot == BOOT_PRIMARY_SLOT) ?
+                                 "primary" : "secondary");
+                    continue;
+                }
+
+                rc = boot_verify_ram_loading_address(img_dst, img_sz);
+                if (rc != 0) {
+                    BOOT_LOG_INF("Could not copy image from the %s slot in "
+                                 "the Flash to load address 0x%x in SRAM as"
+                                 " the image would overlap memory outside"
+                                 " the defined executable region.",
+                                 (slot == BOOT_PRIMARY_SLOT) ?
+                                 "primary" : "secondary",
+                                 selected_image_header->ih_load_addr);
+                    continue;
+                }
+
+                /* Copy image to the load address from where it
+                 * currently resides in flash
+                 */
+                rc = boot_copy_image_to_sram(state, slot, selected_image_header,
+                                             img_dst, img_sz);
+                if (rc != 0) {
+                    rc = BOOT_EBADIMAGE;
+                    BOOT_LOG_INF("Could not copy image from the %s slot in "
+                                 "the Flash to load address 0x%x in SRAM, "
+                                 "aborting..", (slot == BOOT_PRIMARY_SLOT) ?
+                                 "primary" : "secondary",
+                                 selected_image_header->ih_load_addr);
+                    continue;
+                } else {
+                    BOOT_LOG_INF("Image has been copied from the %s slot in "
+                                 "the flash to SRAM address 0x%x",
+                                 (slot == BOOT_PRIMARY_SLOT) ?
+                                 "primary" : "secondary",
+                                 selected_image_header->ih_load_addr);
+                    image_copied = 1;
+                }
+            } else {
+                /* Only images that support IMAGE_F_RAM_LOAD are allowed if
+                 * MCUBOOT_RAM_LOADING is set.
+                 */
+                rc = BOOT_EBADIMAGE;
+                continue;
+            }
+#endif /* MCUBOOT_RAM_LOADING */
+            rc = boot_validate_slot(state, slot, NULL);
+            if (rc == 0) {
+                /* If a valid image is found then there is no reason to check
+                 * the rest of the images, as they were already ordered by
+                 * preference.
+                 */
+                break;
+            }
+#ifdef MCUBOOT_RAM_LOADING
+            else if (image_copied) {
+                /* If an image is found to be invalid then it is removed from
+                 * RAM to prevent it being a shellcode vector.
+                 */
+                boot_remove_image_from_sram(img_dst, img_sz);
+                image_copied = 0;
+            }
+#endif /* MCUBOOT_RAM_LOADING */
+        }
+        if (rc) {
+            /* If there was no valid image at all */
+            rc = BOOT_EBADIMAGE;
+            goto out;
+        }
+
+        /* Update the security counter with the newest image's security
+         * counter value.
+         */
+        rc = boot_update_security_counter(BOOT_CURR_IMG(state), slot,
+                                          selected_image_header);
+        if (rc != 0) {
+            BOOT_LOG_ERR("Security counter update failed after image "
+                         "validation.");
+            goto out;
+        }
+
+
+#ifdef MCUBOOT_RAM_LOADING
+        BOOT_LOG_INF("Booting image from SRAM at address 0x%x",
+                     selected_image_header->ih_load_addr);
+#else
+        BOOT_LOG_INF("Booting image from the %s slot",
+                    (slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
+#endif /* MCUBOOT_RAM_LOADING */
+
+        rsp->br_hdr = selected_image_header;
+        rsp->br_image_off = boot_img_slot_off(state, slot);
+        rsp->br_flash_dev_id = BOOT_IMG_AREA(state, slot)->fa_device_id;
+    } else {
+        /* No candidate image available */
+        rc = BOOT_EBADIMAGE;
+        goto out;
+    }
+
+    /* Save boot status to shared memory area */
+    rc = boot_save_boot_status(SW_S_NS,
+                               rsp->br_hdr,
+                               BOOT_IMG_AREA(state, slot));
+    if (rc) {
+        BOOT_LOG_ERR("Failed to add data to shared area");
+    }
+
+out:
+   for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
+       flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
+   }
+   return rc;
+}
+#endif /* MCUBOOT_NO_SWAP || MCUBOOT_RAM_LOADING */
+
+int
+boot_go(struct boot_rsp *rsp)
+{
+    return context_boot_go(&boot_data, rsp);
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/tlv.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/tlv.c
new file mode 100644
index 0000000000..742c930017
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/bootutil/src/tlv.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2019 JUUL Labs
+ * Copyright (c) 2019 Arm Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+#include 
+#include 
+
+#include "bootutil/bootutil.h"
+#include "bootutil/image.h"
+#include "bootutil_priv.h"
+
+/*
+ * Initialize a TLV iterator.
+ *
+ * @param it An iterator struct
+ * @param hdr image_header of the slot's image
+ * @param fap flash_area of the slot which is storing the image
+ * @param type Type of TLV to look for
+ * @param prot true if TLV has to be stored in the protected area, false otherwise
+ *
+ * @returns 0 if the TLV iterator was succesfully started
+ *          -1 on errors
+ */
+int
+bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
+                        const struct flash_area *fap, uint8_t type, bool prot)
+{
+    uint32_t off_;
+    struct image_tlv_info info;
+
+    if (it == NULL || hdr == NULL || fap == NULL) {
+        return -1;
+    }
+
+    off_ = BOOT_TLV_OFF(hdr);
+    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
+        return -1;
+    }
+
+    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
+        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
+            return -1;
+        }
+
+        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
+                            &info, sizeof(info))) {
+            return -1;
+        }
+    } else if (hdr->ih_protect_tlv_size != 0) {
+        return -1;
+    }
+
+    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
+        return -1;
+    }
+
+    it->hdr = hdr;
+    it->fap = fap;
+    it->type = type;
+    it->prot = prot;
+    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
+    if (!boot_u32_safe_add(&(it->tlv_end), it->prot_end, info.it_tlv_tot)) {
+        return -1;
+    }
+    // position on first TLV
+    it->tlv_off = off_ + sizeof(info);
+    return 0;
+}
+
+/*
+ * Find next TLV
+ *
+ * @param it The image TLV iterator struct
+ * @param off The offset of the TLV's payload in flash
+ * @param len The length of the TLV's payload
+ * @param type If not NULL returns the type of TLV found
+ *
+ * @returns 0 if a TLV with with matching type was found
+ *          1 if no more TLVs with matching type are available
+ *          -1 on errors
+ */
+int
+bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
+                       uint8_t *type)
+{
+    struct image_tlv tlv;
+    int rc;
+
+    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
+        return -1;
+    }
+
+    while (it->tlv_off < it->tlv_end) {
+        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
+            it->tlv_off += sizeof(struct image_tlv_info);
+        }
+
+        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
+        if (rc) {
+            return -1;
+        }
+
+        /* No more TLVs in the protected area */
+        if (it->prot && it->tlv_off >= it->prot_end) {
+            return 1;
+        }
+
+        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
+            if (type != NULL) {
+                *type = tlv.it_type;
+            }
+            *off = it->tlv_off + sizeof(tlv);
+            *len = tlv.it_len;
+
+            if (!boot_u32_safe_add(&(it->tlv_off), *off, *len)) {
+                return -1;
+            }
+
+            return 0;
+        }
+
+        if (!boot_u32_safe_add(&(it->tlv_off), it->tlv_off,
+                               sizeof(tlv) + tlv.it_len)) {
+            return -1;
+        }
+    }
+
+    return 1;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_extended.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_extended.c
new file mode 100644
index 0000000000..887f89be15
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_extended.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2019-2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+#include 
+#include "target.h"
+#include "Driver_Flash.h"
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "bootutil/bootutil_log.h"
+
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+int flash_device_base(uint8_t fd_id, uintptr_t *ret)
+{
+    if (fd_id != FLASH_DEVICE_ID) {
+        BOOT_LOG_ERR("invalid flash ID %d; expected %d",
+                     fd_id, FLASH_DEVICE_ID);
+        return -EINVAL;
+    }
+    *ret = FLASH_DEVICE_BASE;
+    return 0;
+}
+
+/*
+ * This depends on the mappings defined in flash_map.h.
+ * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
+ * and the scratch while TF-M might number it differently.
+ */
+int flash_area_id_from_multi_image_slot(int image_index, int slot)
+{
+    switch (slot) {
+    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
+    case 1: return FLASH_AREA_IMAGE_SECONDARY(image_index);
+    case 2: return FLASH_AREA_IMAGE_SCRATCH;
+    }
+
+    return -EINVAL; /* flash_area_open will fail on that */
+}
+
+int flash_area_id_from_image_slot(int slot)
+{
+    return flash_area_id_from_multi_image_slot(0, slot);
+}
+
+int flash_area_id_to_multi_image_slot(int image_index, int area_id)
+{
+    if (area_id == FLASH_AREA_IMAGE_PRIMARY(image_index)) {
+        return 0;
+    }
+    if (area_id == FLASH_AREA_IMAGE_SECONDARY(image_index)) {
+        return 1;
+    }
+
+    BOOT_LOG_ERR("invalid flash area ID");
+    return -1;
+}
+
+int flash_area_id_to_image_slot(int area_id)
+{
+    return flash_area_id_to_multi_image_slot(0, area_id);
+}
+
+uint8_t flash_area_erased_val(const struct flash_area *fap)
+{
+    (void)fap;
+
+    return FLASH_DEV_NAME.GetInfo()->erased_value;
+}
+
+int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
+        void *dst, uint32_t len)
+{
+    uint32_t i;
+    uint8_t *u8dst;
+    int rc;
+
+    BOOT_LOG_DBG("read_is_empty area=%d, off=%#x, len=%#x",
+                 fa->fa_id, off, len);
+
+    rc = FLASH_DEV_NAME.ReadData(fa->fa_off + off, dst, len);
+    if (rc) {
+        return -1;
+    }
+
+    u8dst = (uint8_t*)dst;
+
+    for (i = 0; i < len; i++) {
+        if (u8dst[i] != flash_area_erased_val(fa)) {
+            return 0;
+        }
+    }
+
+    return 1;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_legacy.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_legacy.c
new file mode 100644
index 0000000000..6ea65fea44
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/flash_map_legacy.c
@@ -0,0 +1,82 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2019 Arm Limited.
+ */
+
+#include "bootutil/bootutil_log.h"
+#include "flash_map/flash_map.h"
+#include 
+#include 
+
+/*
+ * Lookup the sector map for a given flash area.  This should fill in
+ * `ret` with all of the sectors in the area.  `*cnt` will be set to
+ * the storage at `ret` and should be set to the final number of
+ * sectors in this area.
+ */
+int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
+{
+    const struct flash_area *fa;
+    uint32_t max_cnt = *cnt;
+    uint32_t rem_len;
+    int rc = -1;
+
+    if (flash_area_open(idx, &fa)) {
+        goto out;
+    }
+
+    BOOT_LOG_DBG("area %d: offset=0x%x, length=0x%x", idx, fa->fa_off,
+                 fa->fa_size);
+
+    if (*cnt < 1) {
+        goto fa_close_out;
+    }
+
+    rem_len = fa->fa_size;
+    *cnt = 0;
+    while (rem_len > 0 && *cnt < max_cnt) {
+        if (rem_len < FLASH_AREA_IMAGE_SECTOR_SIZE) {
+            BOOT_LOG_ERR("area %d size 0x%x not divisible by sector size 0x%x",
+                         idx, fa->fa_size, FLASH_AREA_IMAGE_SECTOR_SIZE);
+            goto fa_close_out;
+        }
+
+        ret[*cnt].fs_off = FLASH_AREA_IMAGE_SECTOR_SIZE * (*cnt);
+        ret[*cnt].fs_size = FLASH_AREA_IMAGE_SECTOR_SIZE;
+        *cnt = *cnt + 1;
+        rem_len -= FLASH_AREA_IMAGE_SECTOR_SIZE;
+    }
+
+    if (*cnt > max_cnt) {
+        BOOT_LOG_ERR("flash area %d sector count overflow", idx);
+        goto fa_close_out;
+    }
+
+    rc = 0;
+
+fa_close_out:
+    flash_area_close(fa);
+out:
+    return rc;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/bl2_util.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/bl2_util.h
new file mode 100644
index 0000000000..ea8df98880
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/bl2_util.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __BL2_UTIL_H__
+#define __BL2_UTIL_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include 
+
+    /* Evaluates to 0 if cond is true-ish; compile error otherwise */
+#define ZERO_OR_COMPILE_ERROR(cond) ((int) sizeof(char[1 - 2 * !(cond)]) - 1)
+
+    /* Evaluates to 0 if array is an array; compile error if not array (e.g.
+     * pointer)
+     */
+#if defined(NO_TYPEOF)
+    /* __typeof__ is a non-standard gcc extension, not universally available.
+     * As this is just compile time data type test, assume things are ok for
+     * tool chains missing this feature.
+     */
+#define IS_ARRAY(array) 0
+#else
+#define IS_ARRAY(array) \
+        ZERO_OR_COMPILE_ERROR(!__builtin_types_compatible_p(__typeof__(array), \
+                              __typeof__(&(array)[0])))
+#endif
+
+#define ARRAY_SIZE(array) \
+    ((unsigned long) (IS_ARRAY(array) + \
+        (sizeof(array) / sizeof((array)[0]))))
+
+#define CONTAINER_OF(ptr, type, field) \
+        ((type *)(((char *)(ptr)) - offsetof(type, field)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BL2_UTIL_H__ */
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/config-rsa.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/config-rsa.h
new file mode 100644
index 0000000000..b721953a63
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/config-rsa.h
@@ -0,0 +1,88 @@
+/*
+ *  Minimal configuration for using TLS in the bootloader
+ *
+ *  Copyright (C) 2006-2019, Arm Limited. All rights reserved.
+ *  Copyright (C) 2016, Linaro Ltd
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+/*
+ * Minimal configuration for using TLS in the bootloader
+ *
+ * - RSA signature verification
+ */
+
+#ifndef MCUBOOT_MBEDTLS_CONFIG_RSA
+#define MCUBOOT_MBEDTLS_CONFIG_RSA
+
+/* System support */
+#define MBEDTLS_PLATFORM_C
+#define MBEDTLS_PLATFORM_MEMORY
+#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+
+#define MBEDTLS_PLATFORM_EXIT_ALT
+#define MBEDTLS_PLATFORM_PRINTF_ALT
+
+#define MBEDTLS_RSA_C
+#define MBEDTLS_PKCS1_V15
+
+/* mbed TLS modules */
+#define MBEDTLS_ASN1_PARSE_C
+#define MBEDTLS_ASN1_WRITE_C
+#define MBEDTLS_BIGNUM_C
+#define MBEDTLS_MD_C
+#define MBEDTLS_OID_C
+#define MBEDTLS_SHA256_C
+
+/* Save RAM by adjusting to our exact needs */
+#if MCUBOOT_SIGN_RSA_LEN == 3072
+#define MBEDTLS_MPI_MAX_SIZE 384
+#else /* RSA2048 */
+#define MBEDTLS_MPI_MAX_SIZE 256
+#endif
+
+#define MBEDTLS_SSL_MAX_CONTENT_LEN 1024
+
+/* Save ROM and a few bytes of RAM by specifying our own ciphersuite list */
+#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
+
+#ifdef CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING
+#define MBEDTLS_CIPHER_C
+#define MBEDTLS_AES_C
+#define MBEDTLS_CCM_C
+#define MBEDTLS_ECDSA_C
+#define MBEDTLS_ECP_C
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+#endif /* CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING */
+
+#ifdef CRYPTO_HW_ACCELERATOR
+#include "mbedtls_accelerator_config.h"
+#endif
+
+#include "mbedtls/check_config.h"
+
+#endif /* MCUBOOT_MBEDTLS_CONFIG_RSA */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map/flash_map.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map/flash_map.h
new file mode 100644
index 0000000000..f47b585622
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map/flash_map.h
@@ -0,0 +1,153 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2018-2020 Arm Limited.
+ */
+
+#ifndef H_UTIL_FLASH_MAP_
+#define H_UTIL_FLASH_MAP_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ * Provides abstraction of flash regions for type of use.
+ * I.e. dude where's my image?
+ *
+ * System will contain a map which contains flash areas. Every
+ * region will contain flash identifier, offset within flash and length.
+ *
+ * 1. This system map could be in a file within filesystem (Initializer
+ * must know/figure out where the filesystem is at).
+ * 2. Map could be at fixed location for project (compiled to code)
+ * 3. Map could be at specific place in flash (put in place at mfg time).
+ *
+ * Note that the map you use must be valid for BSP it's for,
+ * match the linker scripts when platform executes from flash,
+ * and match the target offset specified in download script.
+ */
+#include 
+
+/*
+ * For now, we only support one flash device.
+ *
+ * Pick a random device ID for it that's unlikely to collide with
+ * anything "real".
+ */
+#define FLASH_DEVICE_ID                 100
+#define FLASH_DEVICE_BASE               FLASH_BASE_ADDRESS
+
+/**
+ * @brief Structure describing an area on a flash device.
+ *
+ * Multiple flash devices may be available in the system, each of
+ * which may have its own areas. For this reason, flash areas track
+ * which flash device they are part of.
+ */
+struct flash_area {
+    /**
+     * This flash area's ID; unique in the system.
+     */
+    uint8_t fa_id;
+
+    /**
+     * ID of the flash device this area is a part of.
+     */
+    uint8_t fa_device_id;
+
+    uint16_t pad16;
+
+    /**
+     * This area's offset, relative to the beginning of its flash
+     * device's storage.
+     */
+    uint32_t fa_off;
+
+    /**
+     * This area's size, in bytes.
+     */
+    uint32_t fa_size;
+};
+
+/**
+ * @brief Structure describing a sector within a flash area.
+ *
+ * Each sector has an offset relative to the start of its flash area
+ * (NOT relative to the start of its flash device), and a size. A
+ * flash area may contain sectors with different sizes.
+ */
+struct flash_sector {
+    /**
+     * Offset of this sector, from the start of its flash area (not device).
+     */
+    uint32_t fs_off;
+
+    /**
+     * Size of this sector, in bytes.
+     */
+    uint32_t fs_size;
+};
+
+/*
+ * Start using flash area.
+ */
+int flash_area_open(uint8_t id, const struct flash_area **area);
+
+void flash_area_close(const struct flash_area *area);
+
+/*
+ * Read/write/erase. Offset is relative from beginning of flash area.
+ */
+int flash_area_read(const struct flash_area *area, uint32_t off, void *dst,
+                    uint32_t len);
+
+int flash_area_write(const struct flash_area *area, uint32_t off,
+                     const void *src, uint32_t len);
+
+int flash_area_erase(const struct flash_area *area, uint32_t off, uint32_t len);
+
+/*
+ * Alignment restriction for flash writes.
+ */
+uint32_t flash_area_align(const struct flash_area *area);
+
+/*
+ * Given flash area ID, return info about sectors within the area.
+ */
+int flash_area_get_sectors(int fa_id, uint32_t *count,
+  struct flash_sector *sectors);
+
+/*
+ * Similar to flash_area_get_sectors(), but return the values in an
+ * array of struct flash_area instead.
+ */
+__attribute__((deprecated))
+int flash_area_to_sectors(int idx, int *cnt, struct flash_area *ret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_UTIL_FLASH_MAP_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map_backend/flash_map_backend.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map_backend/flash_map_backend.h
new file mode 100644
index 0000000000..09d69eaeb5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/flash_map_backend/flash_map_backend.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+#ifndef __FLASH_MAP_BACKEND_H__
+#define __FLASH_MAP_BACKEND_H__
+
+#include "flash_map/flash_map.h"
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Provides abstraction of flash regions for type of use.
+ *
+ * System will contain a map which contains flash areas. Every
+ * region will contain flash identifier, offset within flash and length.
+ */
+
+/*
+ * Retrieve a memory-mapped flash device's base address.
+ *
+ * On success, the address will be stored in the value pointed to by
+ * ret.
+ *
+ * Returns 0 on success, or an error code on failure.
+ */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret);
+
+int flash_area_id_from_image_slot(int slot);
+int flash_area_id_from_multi_image_slot(int image_index, int slot);
+
+/**
+ * Converts the specified flash area ID to an image slot index.
+ *
+ * Returns image slot index (0 or 1), or -1 if ID doesn't correspond to an image
+ * slot.
+ */
+int flash_area_id_to_image_slot(int area_id);
+
+/**
+ * Converts the specified flash area ID and image index (in multi-image setup)
+ * to an image slot index.
+ *
+ * Returns image slot index (0 or 1), or -1 if ID doesn't correspond to an image
+ * slot.
+ */
+int flash_area_id_to_multi_image_slot(int image_index, int area_id);
+
+/*
+ * Returns the value expected to be read when accessing any erased
+ * flash byte.
+ */
+uint8_t flash_area_erased_val(const struct flash_area *fap);
+
+/*
+ * Reads len bytes from off, and checks if the read data is erased.
+ *
+ * Returns 1 if erased, 0 if non-erased, and -1 on failure.
+ */
+int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
+        void *dst, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FLASH_MAP_BACKEND_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_config.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_config.h
new file mode 100644
index 0000000000..a0dfe0981d
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_config.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018 Open Source Foundries Limited
+ * Copyright (c) 2019 Arm Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+#ifndef __MCUBOOT_CONFIG_H__
+#define __MCUBOOT_CONFIG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file is also included by the simulator, but we don't want to
+ * define anything here in simulator builds.
+ *
+ * Instead of using mcuboot_config.h, the simulator adds MCUBOOT_xxx
+ * configuration flags to the compiler command lines based on the
+ * values of environment variables. However, the file still must
+ * exist, or bootutil won't build.
+ */
+#ifndef __BOOTSIM__
+
+/*
+ * In TF-M most of the configuration flags (e.g. signature type,
+ * upgrade mode ...) are handled by the CMake-based buildsystem and
+ * added to the compiler command lines.
+ */
+
+/*
+ * Cryptographic settings
+ */
+#define MCUBOOT_USE_MBED_TLS
+
+/*
+ * Logging
+ */
+#define MCUBOOT_HAVE_LOGGING    1
+
+#endif /* !__BOOTSIM__ */
+
+/*
+ * Watchdog feeding
+ */
+#define MCUBOOT_WATCHDOG_FEED()     \
+    do {                            \
+        /* Do nothing. */           \
+    } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCUBOOT_CONFIG_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_logging.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_logging.h
new file mode 100644
index 0000000000..f4bb1ec911
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/mcuboot_config/mcuboot_logging.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ * Copyright (c) 2019 Arm Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MCUBOOT_LOGGING_H__
+#define __MCUBOOT_LOGGING_H__
+
+#include "bootutil/ignore.h"
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MCUBOOT_LOG_LEVEL_OFF       0
+#define MCUBOOT_LOG_LEVEL_ERROR     1
+#define MCUBOOT_LOG_LEVEL_WARNING   2
+#define MCUBOOT_LOG_LEVEL_INFO      3
+#define MCUBOOT_LOG_LEVEL_DEBUG     4
+
+/*
+ * The compiled log level determines the maximum level that can be
+ * printed. Messages at or below this level can be printed.
+ */
+#ifndef MCUBOOT_LOG_LEVEL
+#define MCUBOOT_LOG_LEVEL           MCUBOOT_LOG_LEVEL_INFO
+#endif
+
+#define MCUBOOT_LOG_MODULE_DECLARE(domain)      /* Ignore */
+#define MCUBOOT_LOG_MODULE_REGISTER(domain)     /* Ignore */
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_ERROR
+#define MCUBOOT_LOG_ERR(_fmt, ...)                  \
+    printf("[ERR] " _fmt "\r\n", ##__VA_ARGS__)
+#else
+#define MCUBOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_WARNING
+#define MCUBOOT_LOG_WRN(_fmt, ...)                  \
+    printf("[WRN] " _fmt "\r\n", ##__VA_ARGS__)
+#else
+#define MCUBOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_INFO
+#define MCUBOOT_LOG_INF(_fmt, ...)                  \
+    printf("[INF] " _fmt "\r\n", ##__VA_ARGS__)
+#else
+#define MCUBOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
+#endif
+
+#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
+#define MCUBOOT_LOG_DBG(_fmt, ...)                  \
+    printf("[DBG] " _fmt "\r\n", ##__VA_ARGS__)
+#else
+#define MCUBOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCUBOOT_LOGGING_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/os/os_malloc.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/os/os_malloc.h
new file mode 100644
index 0000000000..2338ce170b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/os/os_malloc.h
@@ -0,0 +1,38 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2020 Arm Limited.
+ */
+
+#ifndef H_OS_MALLOC_
+#define H_OS_MALLOC_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_OS_MALLOC_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/security_cnt.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/security_cnt.h
new file mode 100644
index 0000000000..7c17a9443b
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/security_cnt.h
@@ -0,0 +1,64 @@
+/*
+ *  Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SECURITY_CNT_H__
+#define __SECURITY_CNT_H__
+
+/**
+ * @file security_cnt.h
+ *
+ * @note The interface must be implemented in a fail-safe way that is
+ *       resistant to asynchronous power failures or it can use hardware
+ *       counters that have this capability, if supported by the platform.
+ *       When a counter incrementation was interrupted it must be able to
+ *       continue the incrementation process or recover the previous consistent
+ *       status of the counters. If the counters have reached a stable status
+ *       (every counter incrementation operation has finished), from that point
+ *       their value cannot decrease due to any kind of power failure.
+ */
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialises the security counters.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+int32_t boot_nv_security_counter_init(void);
+
+/**
+ * Reads the stored value of a given image's security counter.
+ *
+ * @param image_id          Index of the image (from 0).
+ * @param security_cnt      Pointer to store the security counter value.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+int32_t boot_nv_security_counter_get(uint32_t image_id, uint32_t *security_cnt);
+
+/**
+ * Updates the stored value of a given image's security counter with a new
+ * security counter value if the new one is greater.
+ *
+ * @param image_id          Index of the image (from 0).
+ * @param img_security_cnt  New security counter value. The new value must be
+ *                          between 0 and UINT32_MAX and it must be greater than
+ *                          or equal to the current security counter value.
+ *
+ * @return                  0 on success; nonzero on failure.
+ */
+int32_t boot_nv_security_counter_update(uint32_t image_id,
+                                        uint32_t img_security_cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SECURITY_CNT_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/sysflash/sysflash.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/sysflash/sysflash.h
new file mode 100644
index 0000000000..9ade3a3808
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/sysflash/sysflash.h
@@ -0,0 +1,50 @@
+/* Manual version of auto-generated version. */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2020 Arm Limited.
+ */
+
+#ifndef __SYSFLASH_H__
+#define __SYSFLASH_H__
+
+#include "flash_layout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (MCUBOOT_IMAGE_NUMBER == 1)
+/*
+ * NOTE: the definition below returns the same values for true/false on
+ * purpose, to avoid having to mark x as non-used by all callers when
+ * running in single image mode.
+ */
+#define FLASH_AREA_IMAGE_PRIMARY(x)     (((x) == 0) ? FLASH_AREA_0_ID : \
+                                                      FLASH_AREA_0_ID)
+#define FLASH_AREA_IMAGE_SECONDARY(x)   (((x) == 0) ? FLASH_AREA_2_ID : \
+                                                      FLASH_AREA_2_ID)
+#elif (MCUBOOT_IMAGE_NUMBER == 2)
+/* MCUBoot currently supports only up to 2 updatable firmware images.
+ * If the number of the current image is greater than MCUBOOT_IMAGE_NUMBER - 1
+ * then a dummy value will be assigned to the flash area macros.
+ */
+#define FLASH_AREA_IMAGE_PRIMARY(x)     (((x) == 0) ? FLASH_AREA_0_ID : \
+                                         ((x) == 1) ? FLASH_AREA_1_ID : \
+                                                      255 )
+#define FLASH_AREA_IMAGE_SECONDARY(x)   (((x) == 0) ? FLASH_AREA_2_ID : \
+                                         ((x) == 1) ? FLASH_AREA_3_ID : \
+                                                      255 )
+#else
+#error "Image slot and flash area mapping is not defined"
+#endif
+
+#define FLASH_AREA_IMAGE_SCRATCH        FLASH_AREA_SCRATCH_ID
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSFLASH_H__ */
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/target.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/target.h
new file mode 100644
index 0000000000..a812df6476
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/include/target.h
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2017, Linaro Ltd
+ *  Copyright (c) 2018-2020, Arm Limited.
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ */
+
+#ifndef H_TARGETS_TARGET_
+#define H_TARGETS_TARGET_
+
+/* Target specific defines: flash partitions; flash driver name, etc.
+ * Comes from: platform/ext/target///partition
+ */
+#include "flash_layout.h"
+
+#ifndef FLASH_BASE_ADDRESS
+#error "FLASH_BASE_ADDRESS must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_IMAGE_SECTOR_SIZE
+#error "FLASH_AREA_IMAGE_SECTOR_SIZE must be defined by the target"
+#endif
+
+#ifdef MCUBOOT_RAM_LOADING
+#ifndef IMAGE_EXECUTABLE_RAM_START
+#error "If MCUBOOT_RAM_LOADING is set then IMAGE_EXECUTABLE_RAM_START must be \
+defined by the target"
+#endif
+
+#ifndef IMAGE_EXECUTABLE_RAM_SIZE
+#error "If MCUBOOT_RAM_LOADING is set then IMAGE_EXECUTABLE_RAM_SIZE must be \
+defined by the target"
+#endif
+#endif /* MCUBOOT_RAM_LOADING */
+
+#ifndef FLASH_AREA_0_OFFSET
+#error "FLASH_AREA_0_OFFSET must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_0_SIZE
+#error "FLASH_AREA_0_SIZE must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_2_OFFSET
+#error "FLASH_AREA_2_OFFSET must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_2_SIZE
+#error "FLASH_AREA_2_SIZE must be defined by the target"
+#endif
+
+#if (MCUBOOT_IMAGE_NUMBER == 2)
+#ifndef FLASH_AREA_1_OFFSET
+#error "FLASH_AREA_1_OFFSET must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_1_SIZE
+#error "FLASH_AREA_1_SIZE must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_3_OFFSET
+#error "FLASH_AREA_3_OFFSET must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_3_SIZE
+#error "FLASH_AREA_3_SIZE must be defined by the target"
+#endif
+#endif /* (MCUBOOT_IMAGE_NUMBER == 2) */
+
+#ifndef FLASH_AREA_SCRATCH_OFFSET
+#error "FLASH_AREA_SCRATCH_OFFSET must be defined by the target"
+#endif
+
+#ifndef FLASH_AREA_SCRATCH_SIZE
+#error "FLASH_AREA_SCRATCH_SIZE must be defined by the target"
+#endif
+
+#ifndef FLASH_DEV_NAME
+#error "BL2 supports CMSIS flash interface and device name must be specified"
+#endif
+
+#ifndef MCUBOOT_STATUS_MAX_ENTRIES
+#error "MCUBOOT_STATUS_MAX_ENTRIES must be defined by the target"
+#endif
+
+#ifndef MCUBOOT_MAX_IMG_SECTORS
+#error "MCUBOOT_MAX_IMG_SECTORS must be defined by the target"
+#endif
+
+#endif /* H_TARGETS_TARGET_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/keys.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/keys.c
new file mode 100644
index 0000000000..c8f960bf98
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/keys.c
@@ -0,0 +1,248 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Original code taken from mcuboot project at:
+ * https://github.com/JuulLabs-OSS/mcuboot
+ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a
+ * Modifications are Copyright (c) 2019 Arm Limited.
+ */
+
+#include 
+
+#if !defined(MCUBOOT_HW_KEY)
+#if defined(MCUBOOT_SIGN_RSA)
+#if MCUBOOT_SIGN_RSA_LEN == 2048
+#define HAVE_KEYS
+const unsigned char rsa_pub_key[] = {
+    0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01,
+    0x00, 0xd1, 0x06, 0x08, 0x1a, 0x18, 0x44, 0x2c,
+    0x18, 0xe8, 0xfb, 0xfd, 0xf7, 0x0d, 0xa3, 0x4f,
+    0x1f, 0xbb, 0xee, 0x5e, 0xf9, 0xaa, 0xd2, 0x4b,
+    0x18, 0xd3, 0x5a, 0xe9, 0x6d, 0x18, 0x80, 0x19,
+    0xf9, 0xf0, 0x9c, 0x34, 0x1b, 0xcb, 0xf3, 0xbc,
+    0x74, 0xdb, 0x42, 0xe7, 0x8c, 0x7f, 0x10, 0x53,
+    0x7e, 0x43, 0x5e, 0x0d, 0x57, 0x2c, 0x44, 0xd1,
+    0x67, 0x08, 0x0f, 0x0d, 0xbb, 0x5c, 0xee, 0xec,
+    0xb3, 0x99, 0xdf, 0xe0, 0x4d, 0x84, 0x0b, 0xaa,
+    0x77, 0x41, 0x60, 0xed, 0x15, 0x28, 0x49, 0xa7,
+    0x01, 0xb4, 0x3c, 0x10, 0xe6, 0x69, 0x8c, 0x2f,
+    0x5f, 0xac, 0x41, 0x4d, 0x9e, 0x5c, 0x14, 0xdf,
+    0xf2, 0xf8, 0xcf, 0x3d, 0x1e, 0x6f, 0xe7, 0x5b,
+    0xba, 0xb4, 0xa9, 0xc8, 0x88, 0x7e, 0x47, 0x3c,
+    0x94, 0xc3, 0x77, 0x67, 0x54, 0x4b, 0xaa, 0x8d,
+    0x38, 0x35, 0xca, 0x62, 0x61, 0x7e, 0xb7, 0xe1,
+    0x15, 0xdb, 0x77, 0x73, 0xd4, 0xbe, 0x7b, 0x72,
+    0x21, 0x89, 0x69, 0x24, 0xfb, 0xf8, 0x65, 0x6e,
+    0x64, 0x3e, 0xc8, 0x0e, 0xd7, 0x85, 0xd5, 0x5c,
+    0x4a, 0xe4, 0x53, 0x0d, 0x2f, 0xff, 0xb7, 0xfd,
+    0xf3, 0x13, 0x39, 0x83, 0x3f, 0xa3, 0xae, 0xd2,
+    0x0f, 0xa7, 0x6a, 0x9d, 0xf9, 0xfe, 0xb8, 0xce,
+    0xfa, 0x2a, 0xbe, 0xaf, 0xb8, 0xe0, 0xfa, 0x82,
+    0x37, 0x54, 0xf4, 0x3e, 0xe1, 0x2b, 0xd0, 0xd3,
+    0x08, 0x58, 0x18, 0xf6, 0x5e, 0x4c, 0xc8, 0x88,
+    0x81, 0x31, 0xad, 0x5f, 0xb0, 0x82, 0x17, 0xf2,
+    0x8a, 0x69, 0x27, 0x23, 0xf3, 0xab, 0x87, 0x3e,
+    0x93, 0x1a, 0x1d, 0xfe, 0xe8, 0xf8, 0x1a, 0x24,
+    0x66, 0x59, 0xf8, 0x1c, 0xab, 0xdc, 0xce, 0x68,
+    0x1b, 0x66, 0x64, 0x35, 0xec, 0xfa, 0x0d, 0x11,
+    0x9d, 0xaf, 0x5c, 0x3a, 0xa7, 0xd1, 0x67, 0xc6,
+    0x47, 0xef, 0xb1, 0x4b, 0x2c, 0x62, 0xe1, 0xd1,
+    0xc9, 0x02, 0x03, 0x01, 0x00, 0x01,
+};
+const unsigned int rsa_pub_key_len = 270;
+#if (MCUBOOT_IMAGE_NUMBER ==2)
+const unsigned char rsa_pub_key_1[] = {
+    0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01,
+    0x00, 0xac, 0xd2, 0x74, 0x93, 0x3e, 0x5f, 0xe7,
+    0xaf, 0xf2, 0xc8, 0x6c, 0xe8, 0x58, 0x51, 0x63,
+    0x77, 0x0e, 0x52, 0xfe, 0x58, 0xd5, 0xbb, 0xa5,
+    0xe3, 0x9c, 0x8a, 0xcd, 0x14, 0x0a, 0x89, 0xc6,
+    0x15, 0xae, 0x49, 0x04, 0x9f, 0x5f, 0x3d, 0x2b,
+    0x89, 0x12, 0x1f, 0x3e, 0x7f, 0x05, 0xfc, 0x0b,
+    0x99, 0x26, 0x63, 0x5e, 0x96, 0xef, 0x33, 0xbc,
+    0x8c, 0x27, 0x68, 0x4d, 0x46, 0x8d, 0x66, 0x33,
+    0x99, 0x3b, 0x38, 0x11, 0x1b, 0xe3, 0xac, 0x18,
+    0x07, 0x95, 0x48, 0x87, 0xb2, 0xab, 0x4f, 0x2d,
+    0x0e, 0x12, 0x51, 0x1b, 0x7f, 0x33, 0xba, 0x78,
+    0xb1, 0xd5, 0xfa, 0x7f, 0xbf, 0x71, 0x4b, 0xe4,
+    0x5f, 0x67, 0x57, 0x67, 0xd5, 0xab, 0xbb, 0x64,
+    0x06, 0x17, 0x3d, 0x81, 0xeb, 0xd8, 0xc1, 0xf9,
+    0x7a, 0x57, 0xd3, 0x29, 0x5c, 0x10, 0xff, 0xa7,
+    0xd3, 0x3a, 0x58, 0x3f, 0x25, 0x8a, 0xc5, 0x84,
+    0x7b, 0x97, 0x27, 0xa5, 0xe4, 0x90, 0xe7, 0xdf,
+    0x1c, 0x33, 0xe6, 0x7c, 0xaf, 0x68, 0x77, 0x5e,
+    0x1f, 0x09, 0x6e, 0xdd, 0x92, 0x60, 0x4e, 0xac,
+    0x73, 0x84, 0xb0, 0xf7, 0xb6, 0x02, 0xc2, 0xce,
+    0x9f, 0xaf, 0xad, 0xb2, 0xb1, 0x57, 0xcc, 0xf9,
+    0x06, 0x1d, 0x6a, 0x25, 0x2f, 0x72, 0x2a, 0x7d,
+    0xfe, 0x0d, 0xed, 0xb8, 0xc2, 0x95, 0x88, 0x41,
+    0xf2, 0x45, 0xa8, 0x6e, 0x6a, 0x85, 0xee, 0xae,
+    0xfa, 0x8a, 0x79, 0xfa, 0xfe, 0x7e, 0x40, 0x49,
+    0x43, 0xec, 0x2c, 0x8e, 0x8e, 0x82, 0x7e, 0xe2,
+    0xf8, 0x0f, 0xf2, 0xe9, 0x7d, 0xa3, 0x7f, 0xac,
+    0x23, 0xbd, 0x0a, 0x42, 0xea, 0x18, 0xfb, 0x72,
+    0xa0, 0x9a, 0x24, 0x01, 0xc8, 0x27, 0x8c, 0x56,
+    0x24, 0x93, 0x82, 0xdf, 0x23, 0x19, 0x96, 0x73,
+    0xf2, 0x11, 0xc3, 0x05, 0xe6, 0xa5, 0xb8, 0x0b,
+    0xe0, 0x73, 0xce, 0x07, 0x9b, 0x57, 0xe6, 0x8e,
+    0xfb, 0x02, 0x03, 0x01, 0x00, 0x01,
+};
+const unsigned int rsa_pub_key_len_1 = 270;
+#endif
+#elif MCUBOOT_SIGN_RSA_LEN == 3072
+#define HAVE_KEYS
+const unsigned char rsa_pub_key[] = {
+    0x30, 0x82, 0x01, 0x8a, 0x02, 0x82, 0x01, 0x81,
+    0x00, 0x9c, 0xba, 0xc2, 0x5a, 0xbf, 0xcc, 0xc5,
+    0x4f, 0x20, 0x0c, 0x4f, 0x6f, 0x6c, 0x51, 0x4f,
+    0x5c, 0x0a, 0xab, 0x80, 0xb8, 0x6b, 0x10, 0xc4,
+    0x9b, 0x2b, 0xc4, 0x52, 0x32, 0x09, 0x4b, 0x3b,
+    0x27, 0x94, 0x6a, 0x1d, 0xd5, 0x4c, 0xa8, 0x5c,
+    0xa0, 0xc0, 0x76, 0x95, 0x7b, 0x26, 0x04, 0xb1,
+    0x13, 0x7e, 0x78, 0x27, 0xd6, 0x0c, 0xb4, 0xe8,
+    0xb0, 0x2d, 0x92, 0x52, 0x8a, 0xfb, 0x69, 0xff,
+    0x42, 0x10, 0xaa, 0x56, 0x0c, 0x83, 0xc8, 0x65,
+    0x6e, 0xba, 0x0d, 0x5f, 0x8e, 0xf7, 0x2b, 0x29,
+    0x92, 0xfc, 0x42, 0x2d, 0x2d, 0xf9, 0x80, 0xf5,
+    0x85, 0x21, 0x87, 0xea, 0xac, 0x40, 0xa8, 0xcb,
+    0xd0, 0xa8, 0x3b, 0xe2, 0xd2, 0xec, 0xf0, 0x14,
+    0x48, 0x0e, 0xcf, 0x2b, 0x8a, 0x4b, 0xa4, 0xcd,
+    0xa1, 0x05, 0x5b, 0x17, 0x66, 0x1d, 0xde, 0x6e,
+    0x44, 0xfe, 0x46, 0xa3, 0x0d, 0xd0, 0x69, 0xbf,
+    0x8c, 0xad, 0xa9, 0x16, 0x68, 0x51, 0xeb, 0x79,
+    0x91, 0x20, 0xe6, 0x81, 0x03, 0x07, 0x89, 0x40,
+    0x55, 0x4b, 0xeb, 0xcf, 0x67, 0xf8, 0x31, 0xc7,
+    0x1c, 0x54, 0x4e, 0x52, 0x0b, 0x60, 0xe8, 0xa2,
+    0x50, 0x07, 0xd1, 0xcf, 0xce, 0x12, 0x26, 0xcd,
+    0x8e, 0x82, 0x8d, 0x4e, 0x64, 0xa9, 0xf7, 0xc7,
+    0x21, 0x99, 0x25, 0x07, 0xdd, 0xc5, 0xd5, 0x5f,
+    0xf4, 0x63, 0xfa, 0xcc, 0x2b, 0xda, 0x06, 0x5c,
+    0x59, 0x67, 0xb0, 0x06, 0x35, 0xe9, 0xaa, 0x92,
+    0x45, 0x35, 0xe5, 0xa0, 0x03, 0xff, 0x1c, 0x02,
+    0xb5, 0xc7, 0x4e, 0x94, 0x4b, 0x6e, 0xad, 0x73,
+    0x9d, 0xce, 0x6f, 0x09, 0xb3, 0xb1, 0x8f, 0x60,
+    0x6c, 0xa2, 0xfa, 0xcd, 0x77, 0x0f, 0xcc, 0x27,
+    0xe6, 0x36, 0x58, 0xb3, 0x52, 0xf7, 0x8f, 0xbe,
+    0x49, 0x98, 0xb7, 0xe9, 0x60, 0xfd, 0x97, 0x57,
+    0xcd, 0xea, 0xd3, 0x0b, 0xdf, 0xa2, 0x42, 0xf7,
+    0x44, 0xd3, 0x87, 0xde, 0xe0, 0x10, 0x03, 0x94,
+    0xda, 0xfc, 0xbc, 0xdd, 0xbe, 0x93, 0xb3, 0x4a,
+    0x2b, 0x58, 0xdc, 0x96, 0x12, 0xf2, 0x6f, 0x23,
+    0xba, 0x3b, 0x37, 0xfe, 0xfc, 0x18, 0x1f, 0x75,
+    0x7d, 0x54, 0x01, 0x0e, 0xbe, 0x3d, 0x18, 0x13,
+    0xb3, 0x28, 0xb9, 0x34, 0x2c, 0xd5, 0xfb, 0xc5,
+    0x33, 0xbd, 0x87, 0xbd, 0x3b, 0xe4, 0x1d, 0xd7,
+    0x02, 0x3d, 0x1c, 0x72, 0x65, 0x72, 0x43, 0x43,
+    0x36, 0xa8, 0xfa, 0xe6, 0x73, 0x2d, 0xa4, 0x61,
+    0xe8, 0x02, 0x9c, 0x3a, 0x56, 0x4d, 0x1c, 0xd1,
+    0x76, 0x9c, 0x8c, 0xaa, 0x5f, 0x1b, 0xeb, 0x1c,
+    0x4a, 0xf5, 0xb9, 0xb8, 0x6f, 0x41, 0x4b, 0x27,
+    0x87, 0xde, 0xf6, 0x94, 0x1f, 0xdd, 0xe6, 0xf1,
+    0xa9, 0xc2, 0x02, 0xc2, 0x4f, 0xa3, 0xfc, 0xa4,
+    0x03, 0x5a, 0xd9, 0x6f, 0x78, 0xfd, 0x84, 0xf0,
+    0xe5, 0xfd, 0x3d, 0xa5, 0x4d, 0x1b, 0xad, 0x5b,
+    0x4b, 0x02, 0x03, 0x01, 0x00, 0x01,
+};
+const unsigned int rsa_pub_key_len = 398;
+#if (MCUBOOT_IMAGE_NUMBER == 2)
+const unsigned char rsa_pub_key_1[] = {
+    0x30, 0x82, 0x01, 0x8a, 0x02, 0x82, 0x01, 0x81,
+    0x00, 0xbf, 0xb7, 0xb0, 0x9f, 0xe8, 0xc8, 0xd1,
+    0xfe, 0x16, 0x1d, 0x53, 0x87, 0x97, 0x79, 0x1c,
+    0x15, 0xc7, 0x99, 0x16, 0x6c, 0xca, 0xb8, 0x2d,
+    0xca, 0xc2, 0x0d, 0x62, 0xf9, 0xeb, 0x8f, 0xe9,
+    0x3a, 0x18, 0x43, 0x47, 0xd7, 0xbb, 0xd5, 0x62,
+    0xbc, 0xe3, 0x33, 0x63, 0xa7, 0xa3, 0xa8, 0x5c,
+    0xf3, 0x23, 0x78, 0xfd, 0x2d, 0x07, 0x21, 0x1f,
+    0xb9, 0x54, 0x70, 0x28, 0xa9, 0x08, 0xda, 0x50,
+    0x7e, 0x9e, 0x8e, 0xcc, 0x68, 0x4e, 0x7f, 0x48,
+    0x0d, 0xea, 0x27, 0xe8, 0xc6, 0xef, 0xad, 0x5f,
+    0x9d, 0x46, 0x4a, 0xbc, 0x69, 0x9a, 0x30, 0x5f,
+    0x3b, 0xc1, 0x52, 0x92, 0xf8, 0xbc, 0x75, 0xd4,
+    0x3c, 0x27, 0x70, 0x40, 0x00, 0xa6, 0x2e, 0x28,
+    0x7f, 0x59, 0xe5, 0x60, 0x43, 0x11, 0xdc, 0x31,
+    0x09, 0x7d, 0xcf, 0x2f, 0x41, 0x3f, 0xb6, 0x52,
+    0x1a, 0xa3, 0x49, 0x16, 0xf2, 0xb5, 0xb3, 0x9c,
+    0x3c, 0xfb, 0x5e, 0x2c, 0x1f, 0x22, 0x86, 0xbd,
+    0xae, 0xbe, 0x36, 0x52, 0xbd, 0xc4, 0xf0, 0x58,
+    0x69, 0x36, 0xa7, 0x80, 0x3e, 0x81, 0xb3, 0x54,
+    0x98, 0xe4, 0x5d, 0x95, 0xed, 0x21, 0xf0, 0xba,
+    0xae, 0x21, 0xfb, 0xc4, 0x19, 0x87, 0x55, 0xd1,
+    0x2b, 0x4f, 0x00, 0xd8, 0x41, 0x58, 0xcb, 0xdb,
+    0xa9, 0x9a, 0x53, 0xe9, 0x6c, 0x67, 0xcb, 0x7c,
+    0x5d, 0xf6, 0x91, 0x06, 0x75, 0x52, 0xf2, 0xc0,
+    0x7e, 0xb1, 0x6b, 0x5d, 0x30, 0x40, 0x40, 0x2f,
+    0xd8, 0x1e, 0x95, 0x3c, 0x05, 0x97, 0x7f, 0xf0,
+    0x04, 0xf0, 0x4e, 0x2c, 0xd5, 0x39, 0x0e, 0x94,
+    0x3d, 0x7c, 0x03, 0x08, 0x1d, 0x09, 0x08, 0xf2,
+    0x8d, 0x44, 0x0d, 0xcf, 0xb3, 0x96, 0x3d, 0x5a,
+    0x76, 0xe8, 0xf6, 0xee, 0x93, 0x64, 0xe8, 0x57,
+    0xd1, 0xe2, 0xf5, 0x0b, 0x18, 0x69, 0x6f, 0xe9,
+    0xe1, 0x3d, 0xf8, 0x89, 0x49, 0x28, 0xe6, 0xaf,
+    0xb8, 0xa8, 0xc6, 0x42, 0x55, 0x2d, 0xc1, 0xdb,
+    0x8c, 0x5d, 0xb2, 0x6d, 0x7f, 0xfe, 0x26, 0xea,
+    0x75, 0xd9, 0xfd, 0x1f, 0xdc, 0x22, 0x3b, 0xa4,
+    0x1b, 0xa7, 0xad, 0xeb, 0x71, 0xdf, 0xbd, 0xb4,
+    0x37, 0xd1, 0xeb, 0xbe, 0x08, 0x10, 0x1c, 0x78,
+    0x84, 0x1c, 0x9a, 0x75, 0xc4, 0xad, 0xe5, 0xef,
+    0x73, 0x17, 0xac, 0x69, 0x78, 0xbc, 0xd6, 0x37,
+    0x8c, 0x0c, 0x14, 0x21, 0x06, 0x47, 0xbd, 0xf8,
+    0x0a, 0xac, 0x19, 0x09, 0x9d, 0x0d, 0x1d, 0x72,
+    0xe1, 0x3e, 0x1a, 0x74, 0xea, 0x86, 0xd9, 0x5c,
+    0x4a, 0xcd, 0xcc, 0xc6, 0x94, 0xa7, 0xfe, 0xda,
+    0x0b, 0x87, 0x11, 0xbb, 0x6b, 0xf0, 0x3a, 0xe3,
+    0x4f, 0x82, 0x4f, 0xb1, 0xe4, 0xa4, 0xcd, 0xbc,
+    0x70, 0x3c, 0x9d, 0x9c, 0x49, 0xf9, 0xcf, 0x28,
+    0x6d, 0xb8, 0xda, 0x6f, 0x7d, 0x38, 0x57, 0x55,
+    0x43, 0x2a, 0x73, 0x8d, 0xb6, 0x18, 0xfd, 0x70,
+    0xa7, 0x02, 0x03, 0x01, 0x00, 0x01,
+};
+const unsigned int rsa_pub_key_len_1 = 398;
+#endif
+#endif
+#else
+#error "No public key available for given signing algorithm."
+#endif
+
+#if defined(HAVE_KEYS)
+const struct bootutil_key bootutil_keys[] = {
+    {
+        .key = rsa_pub_key,
+        .len = &rsa_pub_key_len,
+    },
+#if (MCUBOOT_IMAGE_NUMBER == 2)
+    {
+        .key = rsa_pub_key_1,
+        .len = &rsa_pub_key_len_1,
+    },
+#endif
+};
+const int bootutil_key_cnt = MCUBOOT_IMAGE_NUMBER;
+#endif /* HAVE_KEYS */
+#else  /* MCUBOOT_HW_KEY */
+unsigned int pub_key_len;
+struct bootutil_key bootutil_keys[1] = {
+    {
+        .key = 0,
+        .len = &pub_key_len,
+    },
+};
+const int bootutil_key_cnt = 1;
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048.pem b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048.pem
new file mode 100644
index 0000000000..78c0c34194
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048.pem
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEowIBAAKCAQEA0QYIGhhELBjo+/33DaNPH7vuXvmq0ksY01rpbRiAGfnwnDQb
+y/O8dNtC54x/EFN+Q14NVyxE0WcIDw27XO7ss5nf4E2EC6p3QWDtFShJpwG0PBDm
+aYwvX6xBTZ5cFN/y+M89Hm/nW7q0qciIfkc8lMN3Z1RLqo04NcpiYX634RXbd3PU
+vntyIYlpJPv4ZW5kPsgO14XVXErkUw0v/7f98xM5gz+jrtIPp2qd+f64zvoqvq+4
+4PqCN1T0PuEr0NMIWBj2XkzIiIExrV+wghfyimknI/Orhz6TGh3+6PgaJGZZ+Byr
+3M5oG2ZkNez6DRGdr1w6p9FnxkfvsUssYuHRyQIDAQABAoIBAEahFCHFK1v/OtLT
+eSSZl0Xw2dYr5QXULFpWsOOVUMv2QdB2ZyIehQKziEL3nYPlwpd+82EOa16awwVb
+LYF0lnUFvLltV/4dJtjnqJTqnSCamc1mJIVrwiJA8XwJ07GWDuL2G//p7jJ3v05T
+nZOV/KmD9xfqSvshZun+LgolqHqcrAa1f4cmuP9C9oqenZryljyfj7piaIZGI0JR
+PrJJ5kImYJqRcMgKTyHP4L8nwQ4moMJr6zbfbWxxb5TC7KVZSQ9UKZZ+ZLuy/pkU
+Qe4G8XSE0r+R9u4JCg87I1vgHhn8WJSxVX027OVUq5HfOzg2skQBTcExph5V9B2b
+onNxd8UCgYEA/32PW+ZwRcdKXMj+QVkxXUd6xkXy7mTXPEaQuOLWZQgrSqAFH1l4
+5/6d099KAJrjM6kR8pKXtz72IIyMHTPm332ghymjKvaEl2XP9sF+f6FmYURar4y6
+8Zh3eivP86+Q/YzOGKwtRSziBMzrAfoIXgtwH8pwIPYLP3zBV4449ZsCgYEA0XC/
+gu2ub5M6EXBnjq9K2d4LlTyAPsIbAcMSwkhOUH4YJFS22qXLYQUA9zM+DUyLCrl/
+PKN2G0HQVgMb4DIbeHv8kXB5oGm5zfbWorWqOomXB3AsI7X8YDMtf/PsZV2amBei
+qVskmPJQV21qFyeOcHlT+dHuRb0O0un3dK8RHmsCgYEApDCH4dJ80osZoflVVJ/C
+VqTqJOOtFEFgBQ+AUCEPEQyn7aRaxmPUjJsXyKJVx3/ChV+g9hf5Qj1HJXHNVbMW
+KwhsEpDSmHimizlV5clBxzntNpMcCHdTaJHILo5bbMqmThugE0ELMsp+UgFzAeky
+WWXWX8fUOYqFff5prh/rQQMCgYBQQ8FhT+113Rp37HgDerJY5HvT6afMZV8sQbJC
+uqsotepSohShnsBeoihIlF7HgfoXVhepCYwNzh8ll3NrbEiS2BFnO4+hJmOKx3pi
+SPTAElLLCvYfiXL6+yII01ZZUpIYj5ZLCR7xbovTtZ7e2M4B1L2WFBoYp+eydO/c
+y+rnmQKBgCh0gfyBT/OKPkfKv+Bbt8HcoxgEj+TyH+vYdeTbP9ZSJ6y5utMbPg7z
+iLLbJ+9IcSwPCwJSmI+I0Om4xEp4ZblCrzAG7hWvG2NNzxQjmoOOrAANyTvJR/ap
+N+UkQA4WrMSKEYyBlRS/hR9Unz31vMc2k9Re0ukWhWh/QksQGDfJ
+-----END RSA PRIVATE KEY-----
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048_1.pem b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048_1.pem
new file mode 100644
index 0000000000..4ebd239866
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-2048_1.pem
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEogIBAAKCAQEArNJ0kz5f56/yyGzoWFFjdw5S/ljVu6XjnIrNFAqJxhWuSQSf
+Xz0riRIfPn8F/AuZJmNelu8zvIwnaE1GjWYzmTs4ERvjrBgHlUiHsqtPLQ4SURt/
+M7p4sdX6f79xS+RfZ1dn1au7ZAYXPYHr2MH5elfTKVwQ/6fTOlg/JYrFhHuXJ6Xk
+kOffHDPmfK9od14fCW7dkmBOrHOEsPe2AsLOn6+tsrFXzPkGHWolL3Iqff4N7bjC
+lYhB8kWobmqF7q76inn6/n5ASUPsLI6Ogn7i+A/y6X2jf6wjvQpC6hj7cqCaJAHI
+J4xWJJOC3yMZlnPyEcMF5qW4C+BzzgebV+aO+wIDAQABAoH/d45TSlZcNZ7Pote0
+sWRpUUBKw3bkZTjdvSEVV+GMB8mRe4udgfiCcmpjzIt5sf0g3CDiNVUSKKpmMkGp
+psHAVsDtu7UPfuS6Wj7sbfqufpZXFZHWhz9fP6d7I+T/yJpNzBZepSWoltZso9OK
+CBz1ky1hzbr81EYr8+QYl/m1RD0WiYh0ALuCipRyjtz6ObZ6pRZ/5pSVGmDNn1oM
+EuOZQsF/6qumXWLMBWApVnGl9TW0De5u7oqJATezbIi9ntXNeh6xMgiRAtUAcxtl
+SyN67OfL6odfsNbpIef9itcqPGbfxxrwASjqtm5dPVOsXloUwBBlRIkimWLfu50v
+5yAJAoGBALq1VlAjFYerxlHwZzy/Ie46vXhYPIGozPBaeuUahA6u2mtyvKfGw0XX
+liwxGYTE7OWqmBag0oLAVEO80J0wYIkfHZhnb5Ee/R2nqsY+AnHvApFhFiK6L5ME
+fHOgVMIWzbktb9EX5KGBVSZG1mIsuw1rOHGqv6+K0bYyHXbJaeG5AoGBAOz10mmX
+Ch6rIWsByVkgCXJZp4BrUOzW5Zg9Zplc2HKIrWt8kNnkn1Qjdug01Y9QngGTA6J3
+/84EekZsKoLmhsja6/gIozF8YkC9r4iqDlTmYXpdSpt8LhJsfuNPgP9IgHhWb/k3
+HxLswDO6tztlD2hVYgnaSAjjLUegs8M/1WBTAoGAHgwe5uiuh1YCpZ8tzh3oZQF5
+CowQuMEksi2th39b70z+g7pEWC/pryzB0zzXoYFbqp5ouYOKPVaceQZDAHkPoCGs
+zqEe2FkHXSVlm1/RXuqbHDBmspIKI/vd13HfEhk/ZGTGkPzqY39/55gQ2l3egItX
+2xsinCqYE10/VqWVb6kCgYEAn79hqNmwcth/4PoFWdZlR/f1Gng+yExf4HCUeJPF
+QAGwmCQUKzEb0MdP5F+qEcIRo5IPAzrO837FSDCnwDPVbhdYuZBpJHVsb6Txb7rl
+ior98FZwc74V+Um3iVsR5ghkw7vSJTrp8gI12SnpWVtaNcZKH8ZOhd9RqVZHmjuw
+iA0CgYEAg6HOdDKMj7hksdGxnoNehRR1iJcJRZk0KicjCbF0JNuyFmmg/omfFfVI
++5cD49xx5dCfXx02oo5+yaEXhO4+ByCDoRk+YvnBJKUH1Ne7oD3J4nqCtoFd5Ev+
+d9bo/UsQ22DZVeKbyjnuWnHzjm0+2u1OSCSx911BbOyGgvG89WQ=
+-----END RSA PRIVATE KEY-----
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072.pem b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072.pem
new file mode 100644
index 0000000000..8f58c69c8a
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4gIBAAKCAYEAnLrCWr/MxU8gDE9vbFFPXAqrgLhrEMSbK8RSMglLOyeUah3V
+TKhcoMB2lXsmBLETfngn1gy06LAtklKK+2n/QhCqVgyDyGVuug1fjvcrKZL8Qi0t
++YD1hSGH6qxAqMvQqDvi0uzwFEgOzyuKS6TNoQVbF2Yd3m5E/kajDdBpv4ytqRZo
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+xdVf9GP6zCvaBlxZZ7AGNemqkkU15aAD/xwCtcdOlEturXOdzm8Js7GPYGyi+s13
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+8m8jujs3/vwYH3V9VAEOvj0YE7MouTQs1fvFM72HvTvkHdcCPRxyZXJDQzao+uZz
+LaRh6AKcOlZNHNF2nIyqXxvrHEr1ubhvQUsnh972lB/d5vGpwgLCT6P8pANa2W94
+/YTw5f09pU0brVtLAgMBAAECggGAG786mltbctEL0PIdPVV10cs3yq2bktfjys9S
+Z/ZaQcpDjbfjY9NotrLsK5GmTO1WkKzQDKaqPom2P7HqVhFRdg5CQcKscAV5IWot
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+xBmlIwPWVjzCRTnYUxQuxCAYf+qvgNylKQKBwQDXi3UGI7t30rYNMdIjMn1GPkhW
+o62BOJNCusoXiGnbVOkj8qBayf7kPu10ONBzHcYL7+SQYeVVXQY+DH033ji8oa0J
+p1xMGIlx4JZEduQYlk0ke4hUNrcBQczTRA47DmMm2kIdWlaTHtB7aCJNx72IrwWn
+lVTY9TWm6+yOPcpV5JfyCMM6GqoRycikgNS5IQug5hl2pFVLw+UTfxo6msYaAOnp
+ICUjoeDUKS0Z8+FtzGhAkWTk8GXIiPbfu7RoN1MCgcAcah6Poq2QKTR/AJ76REdf
+jwM7SgKCY1aWx9Ua+nDCCOVA4qLZjOeM7yTX0wyltX2Db+MgYdQFdM6k3o8ckFvS
+G2AoA6i+Ih0/EM0QhTK9oLkCxo/Q1YpJxY/wqWASkhb26pNF0B2Aoi7zxPAcQ1I0
+VrTO3h/JPHhEqKDDwuMWHO/f8fdDwtEba6YDokdSpVKygvlgXdaiz7RU7ckIDZne
+n3hHuwVFqsyMbZzOtSUs2SrgDZmA9zKRA6xjEq9E/yECgcAnm7XecfSCGVNg61XN
+J/sDTHCokx1QEKBm88ItPuEM7/aDp5M1+8Z+FN43rDUJ4l/BU8zxhzvISvbZshvU
+h15vs1oD2yBHz356UaXrYNmbdwsn+BdeOku4zGmiLPBcg9FOk27wy+f60v/GnaUo
+G9tFYbwtRnC4CZ9ZVCM9JDepPv9494lAhSPZbvYS3KW6e0sSvxXQynPuH0paIdIl
+EMn0f1R8hW6ttJKHCiYCjeFP9u71ZoJe25oolpqfFHQbbocCgcAuBR4w3Qmnbscm
+3b7fyy8n3AXa1gIfYjjPpR35qyp1K9thiLyj66YZIl0ACC/dt08lmI9/lguRoNIQ
+AfjzZ8DByZa0caiSiFIMlgNZXdh7N3BUNNbIQk98Wd91gBlWDAiFEhrJKFPpRkmv
+FySATPYcq0lcrjJb3IW2GDK4uo/jb4Nb7Cfog95W6T76XcSKHS5O8k1aI4kFPRsr
+1wGZw64OkA8VXVaCaEBQ4brZ1YKB3mx4/tDqwn0I6bqkGRX3RJg=
+-----END RSA PRIVATE KEY-----
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072_1.pem b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072_1.pem
new file mode 100644
index 0000000000..40250b3a92
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/root-rsa-3072_1.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG5AIBAAKCAYEAv7ewn+jI0f4WHVOHl3kcFceZFmzKuC3Kwg1i+euP6ToYQ0fX
+u9VivOMzY6ejqFzzI3j9LQchH7lUcCipCNpQfp6OzGhOf0gN6ifoxu+tX51GSrxp
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+Z8t8XfaRBnVS8sB+sWtdMEBAL9gelTwFl3/wBPBOLNU5DpQ9fAMIHQkI8o1EDc+z
+lj1aduj27pNk6FfR4vULGGlv6eE9+IlJKOavuKjGQlUtwduMXbJtf/4m6nXZ/R/c
+IjukG6et63HfvbQ30eu+CBAceIQcmnXEreXvcxesaXi81jeMDBQhBke9+AqsGQmd
+DR1y4T4adOqG2VxKzczGlKf+2guHEbtr8DrjT4JPseSkzbxwPJ2cSfnPKG242m99
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+ZwkoxdIiscs1U/nVwvsh9uqMdi5Kap45SFvVx0dVpUPPHYEQtvxems3Owh9AjHuA
+PRq09uLLTB+XbmFD7wIExZAsEiXfrbs1Ovkhx+/xfIONbOUXbIHaSk6q0/bYX8nt
+28pJpTFuWORWVCoUVMuWAyNANBOEnYSTqSXw4cHs4aJ6fOgup0EYHsro8dMd6HWe
+BAZyrqTFxK7L8w/Vl9tWXKTDVfvlj8DHRwWBQhvS1P4XWaEcVopv7Sy4XK7UUeXm
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+/86W55qTRgtHQmb+oPBn8NYDxnYhEYFzGbpoAPD83U4CyGbnoqp5tsmssw8SfvWH
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+jmhj/aOSzcmcJNfx1bdqCyxuK6iw583awBtctjsCgcEArcdwvG74I4GPsM48b1fL
+48nLtipSAot5rBIi5F7Du91+k1eJwfmhs1I0iWe2txg+ZadtRXcPetRpW2CRQnZl
+I12n2m/t62igoabiHFhAxiZeIZEO+UljVP8LgyILX2zBKZs8MHKzZFcvs2KW4yoB
+wSQ04M2q0SGkp6iQzRUX3fbpK9BkOFoMJcaVg7t6IbMHx9b8TXxlBklLJF4/r1pg
+H1ZLwS82uHdGfkPwt/dnK+Tiwtj9J+3+1D+ArIhffACZAoHBANghRLOIv41QP73h
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+lpC0hMDYaErm+VjnImo9v+DwziRvzbJnqe+oAuncQuw5mUiRYfNRf3mM7ZpiJAjU
+YM6mAqkXzwmmDsASXpGkAn+QWo3dh41JZvXfRsF0ya0/2siLrwKBwBBX7YegsNPJ
+skp5AAwYDvujDISc3aLxqEc1UHyM5SmKVt1U0/Dsyod0ZBMe27N8t9INFqy+G7hI
+Y1sthsk6DyM1hSiZsLBTossJgyu3Tf3e300NTmc6CpFSRqL1L4lcSzKAGNTWvS9H
+5q+MpRkZLzug83pmFw0qTWTw8p79cpELM4sklLg8L5cnLDLZyU+Gr5ZshkgpkXJI
+egyV0maL40d5fDsX2ZqCZQPrQ7+FhDHKg/jf3Z3lXHwTAKBNrQGN6g==
+-----END RSA PRIVATE KEY-----
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/assemble.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/assemble.py
new file mode 100644
index 0000000000..5a75424699
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/assemble.py
@@ -0,0 +1,93 @@
+#! /usr/bin/env python3
+#
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2017-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Assemble multiple images into a single image that can be flashed on the device.
+"""
+
+import argparse
+import errno
+import io
+import re
+import os
+import shutil
+import macro_parser
+
+offset_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_OFFSET\s*=\s*(.*)")
+size_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_MAX_SIZE\s*=\s*(.*)")
+
+class Assembly():
+    def __init__(self, layout_path, output):
+        self.output = output
+        self.layout_path = layout_path
+        self.find_slots()
+        try:
+            os.unlink(output)
+        except OSError as e:
+            if e.errno != errno.ENOENT:
+                raise
+
+    def find_slots(self):
+        offsets = {}
+        sizes = {}
+
+        offsets = macro_parser.evaluate_macro(self.layout_path, offset_re, 1, 2)
+        sizes = macro_parser.evaluate_macro(self.layout_path, size_re, 1, 2)
+
+        if 'SECURE' not in offsets:
+            raise Exception("Image config does not have secure partition")
+
+        if 'NON_SECURE' not in offsets:
+            raise Exception("Image config does not have non-secure partition")
+
+        self.offsets = offsets
+        self.sizes = sizes
+
+    def add_image(self, source, partition):
+        with open(self.output, 'ab') as ofd:
+            ofd.seek(0, os.SEEK_END)
+            pos = ofd.tell()
+            if pos > self.offsets[partition]:
+                raise Exception("Partitions not in order, unsupported")
+            if pos < self.offsets[partition]:
+                ofd.write(b'\xFF' * (self.offsets[partition] - pos))
+            statinfo = os.stat(source)
+            if statinfo.st_size > self.sizes[partition]:
+                raise Exception("Image {} is too large for partition".format(source))
+            with open(source, 'rb') as rfd:
+                shutil.copyfileobj(rfd, ofd, 0x10000)
+
+def main():
+    parser = argparse.ArgumentParser()
+
+    parser.add_argument('-l', '--layout', required=True,
+            help='Location of the file that contains preprocessed macros')
+    parser.add_argument('-s', '--secure', required=True,
+            help='Unsigned secure image')
+    parser.add_argument('-n', '--non_secure',
+            help='Unsigned non-secure image')
+    parser.add_argument('-o', '--output', required=True,
+            help='Filename to write full image to')
+
+    args = parser.parse_args()
+    output = Assembly(args.layout, args.output)
+
+    output.add_image(args.secure, "SECURE")
+    output.add_image(args.non_secure, "NON_SECURE")
+
+if __name__ == '__main__':
+    main()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool.py
new file mode 100644
index 0000000000..2d1d97bbb9
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool.py
@@ -0,0 +1,216 @@
+#! /usr/bin/env python3
+#
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function
+import os
+import re
+import argparse
+from imgtool_lib import keys
+from imgtool_lib import image
+from imgtool_lib import version
+import sys
+import macro_parser
+
+sign_bin_size_re = re.compile(r"^\s*RE_SIGN_BIN_SIZE\s*=\s*(.*)")
+image_load_address_re = re.compile(r"^\s*RE_IMAGE_LOAD_ADDRESS\s*=\s*(.*)")
+
+# Returns the last version number if present, or None if not
+def get_last_version(path):
+    if (os.path.isfile(path) == False): # Version file not present
+        return None
+    else: # Version file is present, check it has a valid number inside it
+        with open(path, "r") as oldFile:
+            fileContents = oldFile.read()
+            if version.version_re.match(fileContents): # number is valid
+                return version.decode_version(fileContents)
+            else:
+                return None
+
+def next_version_number(args, defaultVersion, path):
+    newVersion = None
+    versionProvided = False
+    if (version.compare(args.version, defaultVersion) == 0): # Default version
+        lastVersion = get_last_version(path)
+        if (lastVersion is not None):
+            newVersion = version.increment_build_num(lastVersion)
+        else:
+            newVersion = version.increment_build_num(defaultVersion)
+    else: # Version number has been explicitly provided (not using the default)
+        versionProvided = True
+        newVersion = args.version
+    versionString = "{a}.{b}.{c}+{d}".format(
+                    a=str(newVersion.major),
+                    b=str(newVersion.minor),
+                    c=str(newVersion.revision),
+                    d=str(newVersion.build)
+    )
+    if not versionProvided:
+        with open(path, "w") as newFile:
+            newFile.write(versionString)
+    print("**[INFO]** Image version number set to " + versionString)
+    return newVersion
+
+def gen_rsa2048(args):
+    keys.RSAutil.generate().export_private(args.key)
+
+def gen_rsa3072(args):
+    keys.RSAutil.generate(key_size=3072).export_private(args.key)
+
+keygens = {
+        'rsa-2048': gen_rsa2048,
+        'rsa-3072': gen_rsa3072, }
+
+def do_keygen(args):
+    if args.type not in keygens:
+        msg = "Unexpected key type: {}".format(args.type)
+        raise argparse.ArgumentTypeError(msg)
+    keygens[args.type](args)
+
+def do_getpub(args):
+    key = keys.load(args.key)
+    if args.lang == 'c':
+        key.emit_c()
+    else:
+        msg = "Unsupported language, valid are: c"
+        raise argparse.ArgumentTypeError(msg)
+
+def do_sign(args):
+    if args.rsa_pkcs1_15:
+        keys.sign_rsa_pss = False
+
+    version_num = next_version_number(args,
+                                      version.decode_version("0"),
+                                      "lastVerNum.txt")
+
+    if args.security_counter is None:
+        # Security counter has not been explicitly provided,
+        # generate it from the version number
+        args.security_counter = ((version_num.major << 24)
+                                 + (version_num.minor << 16)
+                                 + version_num.revision)
+
+    if "_s.c" in args.layout:
+        sw_type = "SPE"
+    elif "_ns.c" in args.layout:
+        sw_type = "NSPE"
+    else:
+        sw_type = "NSPE_SPE"
+
+    pad_size = macro_parser.evaluate_macro(args.layout, sign_bin_size_re, 0, 1)
+    img = image.Image.load(args.infile,
+                           version=version_num,
+                           header_size=args.header_size,
+                           security_cnt=args.security_counter,
+                           included_header=args.included_header,
+                           pad=pad_size)
+    key = keys.load(args.key, args.public_key_format) if args.key else None
+    ram_load_address = macro_parser.evaluate_macro(args.layout, image_load_address_re, 0, 1)
+    img.sign(sw_type, key, ram_load_address, args.dependencies)
+
+    if pad_size:
+        img.pad_to(pad_size, args.align)
+
+    img.save(args.outfile)
+
+subcmds = {
+        'keygen': do_keygen,
+        'getpub': do_getpub,
+        'sign': do_sign, }
+
+
+def get_dependencies(text):
+    if text is not None:
+        versions = []
+        images = re.findall(r"\((\d+)", text)
+        if len(images) == 0:
+            msg = "Image dependency format is invalid: {}".format(text)
+            raise argparse.ArgumentTypeError(msg)
+        raw_versions = re.findall(r",\s*([0-9.+]+)\)", text)
+        if len(images) != len(raw_versions):
+            msg = '''There's a mismatch between the number of dependency images
+            and versions in: {}'''.format(text)
+            raise argparse.ArgumentTypeError(msg)
+        for raw_version in raw_versions:
+            try:
+                versions.append(version.decode_version(raw_version))
+            except ValueError as e:
+                print(e)
+        dependencies = dict()
+        dependencies[image.DEP_IMAGES_KEY] = images
+        dependencies[image.DEP_VERSIONS_KEY] = versions
+        return dependencies
+
+
+def alignment_value(text):
+    value = int(text)
+    if value not in [1, 2, 4, 8]:
+        msg = "{} must be one of 1, 2, 4 or 8".format(value)
+        raise argparse.ArgumentTypeError(msg)
+    return value
+
+def intparse(text):
+    """Parse a command line argument as an integer.
+
+    Accepts 0x and other prefixes to allow other bases to be used."""
+    return int(text, 0)
+
+def args():
+    parser = argparse.ArgumentParser()
+    subs = parser.add_subparsers(help='subcommand help', dest='subcmd')
+
+    keygenp = subs.add_parser('keygen', help='Generate pub/private keypair')
+    keygenp.add_argument('-k', '--key', metavar='filename', required=True)
+    keygenp.add_argument('-t', '--type', metavar='type',
+                         choices=keygens.keys(), required=True)
+
+    getpub = subs.add_parser('getpub', help='Get public key from keypair')
+    getpub.add_argument('-k', '--key', metavar='filename', required=True)
+    getpub.add_argument('-l', '--lang', metavar='lang', default='c')
+
+    sign = subs.add_parser('sign', help='Sign an image with a private key')
+    sign.add_argument('-l', '--layout', required=True,
+                      help='Location of the file that contains preprocessed macros')
+    sign.add_argument('-k', '--key', metavar='filename')
+    sign.add_argument("-K", "--public-key-format",
+                      help='In what format to add the public key to the image manifest: full or hash',
+                      metavar='pub_key_format', choices=['full', 'hash'], default='hash')
+    sign.add_argument("--align", type=alignment_value, required=True)
+    sign.add_argument("-v", "--version", type=version.decode_version,
+                      default="0.0.0+0")
+    sign.add_argument("-d", "--dependencies", type=get_dependencies,
+                      required=False, help='''Add dependence on another image,
+                      format: "(,), ... "''')
+    sign.add_argument("-s", "--security-counter", type=intparse,
+                      help='Specify explicitly the security counter value')
+    sign.add_argument("-H", "--header-size", type=intparse, required=True)
+    sign.add_argument("--included-header", default=False, action='store_true',
+                      help='Image has gap for header')
+    sign.add_argument("--rsa-pkcs1-15",
+                      help='Use old PKCS#1 v1.5 signature algorithm',
+                      default=False, action='store_true')
+    sign.add_argument("infile")
+    sign.add_argument("outfile")
+
+    args = parser.parse_args()
+    if args.subcmd is None:
+        print('Must specify a subcommand', file=sys.stderr)
+        sys.exit(1)
+
+    subcmds[args.subcmd](args)
+
+if __name__ == '__main__':
+    args()
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/__init__.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/__init__.py
new file mode 100644
index 0000000000..fd240440dc
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/__init__.py
@@ -0,0 +1,18 @@
+# Copyright 2017 Linaro Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# This file is intentionally empty.
+#
+# The __init__.py files are required to make Python treat the directories as
+# containing packages.
\ No newline at end of file
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/boot_record.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/boot_record.py
new file mode 100644
index 0000000000..41887bb5f0
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/boot_record.py
@@ -0,0 +1,77 @@
+
+# Copyright (c) 2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import cbor
+
+
+# SW component IDs
+SW_COMPONENT_RANGE = 0
+SW_COMPONENT_TYPE = SW_COMPONENT_RANGE + 1
+MEASUREMENT_VALUE = SW_COMPONENT_RANGE + 2
+SW_COMPONENT_VERSION = SW_COMPONENT_RANGE + 4
+SIGNER_ID = SW_COMPONENT_RANGE + 5
+MEASUREMENT_DESCRIPTION = SW_COMPONENT_RANGE + 6
+
+
+def create_sw_component_data(sw_type, sw_version, sw_measurement_type,
+                             sw_measurement_value, sw_signer_id):
+
+    # List of SW component claims (key ID + value)
+    key_value_list = [
+        SW_COMPONENT_TYPE, sw_type,
+        SW_COMPONENT_VERSION, sw_version,
+        SIGNER_ID, sw_signer_id,
+        MEASUREMENT_DESCRIPTION, sw_measurement_type,
+        MEASUREMENT_VALUE, sw_measurement_value
+    ]
+    # The measurement value should be the last item (key + value) in the list
+    # to make it easier to modify its value later in the bootloader.
+    # A dictionary would be the best suited data structure to store these
+    # key-value pairs (claims), however dictionaries are not sorted, but for
+    # example the lists do keep to order of items which we care about now.
+    # An ordered dictionary could be used instead, but it would be converted
+    # to a dict before the encoding and this conversion may not keep the order
+    # of the items.
+
+    if (len(key_value_list) % 2) != 0:
+        print('Error: The length of the sw component claim list must '
+              'be even (key + value).', file=sys.stderr)
+        sys.exit(1)
+    else:
+        claim_number = (int)(len(key_value_list) / 2)
+
+    # The output of this function must be a CBOR encoded map (dictionary) of
+    # the SW component claims. The CBOR representation of an array and a map
+    # (dictionary) is quite similar. To convert the encoded list to a map, it
+    # is enough to modify the first byte (CBOR data item header) of the
+    # data. This applies up to 23 items (11 claims in this case) - until the 5
+    # lower bits of the item header are used as an item count specifier.
+
+    if claim_number > 11:
+        print('Error: There are more than 11 claims in the '
+              'list of sw component claims.', file=sys.stderr)
+        sys.exit(1)
+
+    record_array = bytearray(cbor.dumps(key_value_list))
+    # Modify the CBOR data item header (from array to map)
+    # 7..5 bits : Major type
+    #             Array - 0x80
+    #             Map   - 0xA0
+    # 4..0 bits : Number of items
+    record_array[0] = 0xA0 + claim_number
+
+    return bytes(record_array)
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/image.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/image.py
new file mode 100644
index 0000000000..d790a75f7e
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/image.py
@@ -0,0 +1,267 @@
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Image signing and management.
+"""
+
+from . import version as versmod
+from . import boot_record as br
+import hashlib
+import struct
+
+IMAGE_MAGIC = 0x96f3b83d
+IMAGE_HEADER_SIZE = 32
+TLV_HEADER_SIZE = 4
+PAYLOAD_DIGEST_SIZE = 32  # SHA256 hash
+KEYHASH_SIZE = 32
+DEP_IMAGES_KEY = "images"
+DEP_VERSIONS_KEY = "versions"
+
+# Image header flags.
+IMAGE_F = {
+        'PIC':                   0x0000001,
+        'NON_BOOTABLE':          0x0000010,
+        'RAM_LOAD':              0x0000020, }
+TLV_VALUES = {
+        'KEYHASH': 0x01,
+        'KEY'    : 0x02,
+        'SHA256' : 0x10,
+        'RSA2048': 0x20,
+        'RSA3072': 0x23,
+        'DEPENDENCY': 0x40,
+        'SEC_CNT': 0x50,
+        'BOOT_RECORD': 0x60, }
+
+TLV_INFO_SIZE = 4
+TLV_INFO_MAGIC = 0x6907
+TLV_PROT_INFO_MAGIC = 0x6908
+
+# Sizes of the image trailer, depending on flash write size.
+trailer_sizes = {
+    write_size: 128 * 3 * write_size + 8 * 2 + 16
+    for write_size in [1, 2, 4, 8]
+}
+
+boot_magic = bytearray([
+    0x77, 0xc2, 0x95, 0xf3,
+    0x60, 0xd2, 0xef, 0x7f,
+    0x35, 0x52, 0x50, 0x0f,
+    0x2c, 0xb6, 0x79, 0x80, ])
+
+class TLV():
+    def __init__(self, magic=TLV_INFO_MAGIC):
+        self.magic = magic
+        self.buf = bytearray()
+
+    def __len__(self):
+        return TLV_INFO_SIZE + len(self.buf)
+
+    def add(self, kind, payload):
+        """
+        Add a TLV record.  Kind should be a string found in TLV_VALUES above.
+        """
+        buf = struct.pack(' 0:
+            obj.payload = (b'\000' * obj.header_size) + obj.payload
+
+        obj.check()
+        return obj
+
+    def __init__(self, version, header_size=IMAGE_HEADER_SIZE, security_cnt=0,
+                 pad=0):
+        self.version = version
+        self.header_size = header_size or IMAGE_HEADER_SIZE
+        self.security_cnt = security_cnt
+        self.pad = pad
+
+    def __repr__(self):
+        return "".format(
+                self.version,
+                self.header_size,
+                self.security_cnt,
+                self.pad,
+                len(self.payload))
+
+    def save(self, path):
+        with open(path, 'wb') as f:
+            f.write(self.payload)
+
+    def check(self):
+        """Perform some sanity checking of the image."""
+        # If there is a header requested, make sure that the image
+        # starts with all zeros.
+        if self.header_size > 0:
+            if any(v != 0 and v != b'\000' for v in self.payload[0:self.header_size]):
+                raise Exception("Padding requested, but image does not start with zeros")
+
+    def sign(self, sw_type, key, ramLoadAddress, dependencies=None):
+        image_version = (str(self.version.major) + '.'
+                      + str(self.version.minor) + '.'
+                      + str(self.version.revision))
+
+        # Calculate the hash of the public key
+        if key is not None:
+            pub = key.get_public_bytes()
+            sha = hashlib.sha256()
+            sha.update(pub)
+            pubbytes = sha.digest()
+        else:
+            pubbytes = bytes(KEYHASH_SIZE)
+
+        # The image hash is computed over the image header, the image itself
+        # and the protected TLV area. However, the boot record TLV (which is
+        # part of the protected area) should contain this hash before it is
+        # even calculated. For this reason the script fills this field with
+        # zeros and the bootloader will insert the right value later.
+        image_hash = bytes(PAYLOAD_DIGEST_SIZE)
+
+        # Create CBOR encoded boot record
+        boot_record = br.create_sw_component_data(sw_type, image_version,
+                                                  "SHA256", image_hash,
+                                                  pubbytes)
+
+        # Mandatory protected TLV area: TLV info header
+        #                               + security counter TLV
+        #                               + boot record TLV
+        # Size of the security counter TLV: header ('BBH') + payload ('I')
+        #                                   = 8 Bytes
+        protected_tlv_size = TLV_INFO_SIZE + 8 + TLV_HEADER_SIZE \
+                           + len(boot_record)
+
+        if dependencies is None:
+            dependencies_num = 0
+        else:
+            # Size of a dependency TLV:
+            # header ('BBH') + payload('IBBHI') = 16 Bytes
+            dependencies_num = len(dependencies[DEP_IMAGES_KEY])
+            protected_tlv_size += (dependencies_num * 16)
+
+        # At this point the image is already on the payload, this adds
+        # the header to the payload as well
+        self.add_header(key, protected_tlv_size, ramLoadAddress)
+
+        prot_tlv = TLV(TLV_PROT_INFO_MAGIC)
+
+        # Protected TLVs must be added first, because they are also included
+        # in the hash calculation
+        payload = struct.pack('I', self.security_cnt)
+        prot_tlv.add('SEC_CNT', payload)
+        prot_tlv.add('BOOT_RECORD', boot_record)
+
+        if dependencies_num != 0:
+            for i in range(dependencies_num):
+                payload = struct.pack(
+                                '<'+'B3x'+'BBHI',
+                                int(dependencies[DEP_IMAGES_KEY][i]),
+                                dependencies[DEP_VERSIONS_KEY][i].major,
+                                dependencies[DEP_VERSIONS_KEY][i].minor,
+                                dependencies[DEP_VERSIONS_KEY][i].revision,
+                                dependencies[DEP_VERSIONS_KEY][i].build
+                                )
+                prot_tlv.add('DEPENDENCY', payload)
+
+        self.payload += prot_tlv.get()
+
+        sha = hashlib.sha256()
+        sha.update(self.payload)
+        image_hash = sha.digest()
+
+        tlv = TLV()
+
+        tlv.add('SHA256', image_hash)
+
+        if key is not None:
+            if key.get_public_key_format() == 'hash':
+                tlv.add('KEYHASH', pubbytes)
+            else:
+                tlv.add('KEY', pub)
+
+            sig = key.sign(self.payload)
+            tlv.add(key.sig_tlv(), sig)
+
+        self.payload += tlv.get()
+
+    def add_header(self, key, protected_tlv_size, ramLoadAddress):
+        """Install the image header.
+
+        The key is needed to know the type of signature, and
+        approximate the size of the signature."""
+
+        flags = 0
+        if ramLoadAddress is not None:
+            # add the load address flag to the header to indicate that an SRAM
+            # load address macro has been defined
+            flags |= IMAGE_F["RAM_LOAD"]
+
+        fmt = ('<' +
+            # type ImageHdr struct {
+            'I' +    # Magic    uint32
+            'I' +    # LoadAddr uint32
+            'H' +    # HdrSz    uint16
+            'H' +    # PTLVSz   uint16
+            'I' +    # ImgSz    uint32
+            'I' +    # Flags    uint32
+            'BBHI' + # Vers     ImageVersion
+            'I'      # Pad1     uint32
+            ) # }
+        assert struct.calcsize(fmt) == IMAGE_HEADER_SIZE
+        header = struct.pack(fmt,
+                IMAGE_MAGIC,
+                0 if (ramLoadAddress is None) else ramLoadAddress, # LoadAddr
+                self.header_size,
+                protected_tlv_size,  # TLV info header + Protected TLVs
+                len(self.payload) - self.header_size,  # ImageSz
+                flags,
+                self.version.major,
+                self.version.minor or 0,
+                self.version.revision or 0,
+                self.version.build or 0,
+                0)  # Pad1
+        self.payload = bytearray(self.payload)
+        self.payload[:len(header)] = header
+
+    def pad_to(self, size, align):
+        """Pad the image to the given size, with the given flash alignment."""
+        tsize = trailer_sizes[align]
+        padding = size - (len(self.payload) + tsize)
+        if padding < 0:
+            msg = "Image size (0x{:x}) + trailer (0x{:x}) exceeds requested size 0x{:x}".format(
+                    len(self.payload), tsize, size)
+            raise Exception(msg)
+        pbytes  = b'\xff' * padding
+        pbytes += b'\xff' * (tsize - len(boot_magic))
+        pbytes += boot_magic
+        self.payload += pbytes
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/keys.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/keys.py
new file mode 100644
index 0000000000..7ee9671bd5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/keys.py
@@ -0,0 +1,136 @@
+# Copyright (c) 2017,2019 Linaro Limited.
+# Copyright (c) 2017-2019, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Cryptographic key management for imgtool.
+"""
+
+from __future__ import print_function
+from cryptography.hazmat.backends import default_backend
+from cryptography.hazmat.primitives import serialization
+from cryptography.hazmat.primitives.hashes import SHA256
+from cryptography.hazmat.primitives.asymmetric import rsa
+from cryptography.hazmat.primitives.asymmetric.padding import PSS, PKCS1v15
+from cryptography.hazmat.primitives.asymmetric.padding import MGF1
+import hashlib
+from pyasn1.type import namedtype, univ
+from pyasn1.codec.der.encoder import encode
+
+# Sizes that bootutil will recognize
+RSA_KEY_SIZES = [2048, 3072]
+
+# Public exponent
+PUBLIC_EXPONENT = 65537
+
+# By default, we use RSA-PSS (PKCS 2.1).  That can be overridden on
+# the command line to support the older (less secure) PKCS1.5
+sign_rsa_pss = True
+
+AUTOGEN_MESSAGE = "/* Autogenerated by imgtool.py, do not edit. */"
+
+class RSAUsageError(Exception):
+    pass
+
+class RSAutil():
+    def __init__(self, key, public_key_format='hash'):
+        """Construct an RSA key with the given key data"""
+        self.key = key
+        self.public_key_format = public_key_format
+
+    def key_size(self):
+        return self.key.key_size
+
+    def get_public_key_format(self):
+        return self.public_key_format
+
+    @staticmethod
+    def generate(key_size=2048):
+        if key_size not in RSA_KEY_SIZES:
+            raise RSAUsageError("Key size {} is not supported by MCUboot"
+                                .format(key_size))
+        return RSAutil(rsa.generate_private_key(
+                public_exponent=PUBLIC_EXPONENT,
+                key_size=key_size,
+                backend=default_backend()))
+
+    def export_private(self, path):
+        with open(path, 'wb') as f:
+            f.write(self.key.private_bytes(
+                    encoding=serialization.Encoding.PEM,
+                    format=serialization.PrivateFormat.TraditionalOpenSSL,
+                    encryption_algorithm=serialization.NoEncryption()))
+
+    def get_public_bytes(self):
+        return self.key.public_key().public_bytes(
+                encoding=serialization.Encoding.DER,
+                format=serialization.PublicFormat.PKCS1)
+
+    def emit_c(self):
+        print(AUTOGEN_MESSAGE)
+        print("const unsigned char rsa_pub_key[] = {", end='')
+        encoded = self.get_public_bytes()
+        for count, b in enumerate(encoded):
+            if count % 8 == 0:
+                print("\n\t", end='')
+            else:
+                print(" ", end='')
+            print("0x{:02x},".format(b), end='')
+        print("\n};")
+        print("const unsigned int rsa_pub_key_len = {};".format(len(encoded)))
+
+    def sig_type(self):
+        """Return the type of this signature (as a string)"""
+        if sign_rsa_pss:
+            return "PKCS1_PSS_RSA{}_SHA256".format(self.key_size())
+        else:
+            return "PKCS15_RSA{}_SHA256".format(self.key_size())
+
+    def sig_len(self):
+        return 256 if self.key_size() == 2048 else 384
+
+    def sig_tlv(self):
+        return "RSA2048" if self.key_size() == 2048 else "RSA3072"
+
+    def sign(self, payload):
+        if sign_rsa_pss:
+            signature = self.key.sign(
+                data=payload,
+                padding=PSS(
+                    mgf=MGF1(SHA256()),
+                    salt_length=32
+                ),
+                algorithm=SHA256()
+            )
+        else:
+            signature = self.key.sign(
+                data=payload,
+                padding=PKCS1v15(),
+                algorithm=SHA256()
+            )
+        assert len(signature) == self.sig_len()
+        return signature
+
+def load(path, public_key_format='hash'):
+    with open(path, 'rb') as f:
+        pem = f.read()
+    try:
+        key = serialization.load_pem_private_key(
+            pem,
+            password=None,
+            backend=default_backend()
+        )
+        return RSAutil(key, public_key_format)
+    except ValueError:
+        raise Exception("Unsupported RSA key file")
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/version.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/version.py
new file mode 100644
index 0000000000..d1d45f0385
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/imgtool_lib/version.py
@@ -0,0 +1,66 @@
+# Copyright 2017 Linaro Limited
+# Copyright (c) 2018, Arm Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Semi Semantic Versioning
+
+Implements a subset of semantic versioning that is supportable by the image header.
+"""
+
+import argparse
+from collections import namedtuple
+import re
+
+SemiSemVersion = namedtuple('SemiSemVersion', ['major', 'minor', 'revision', 'build'])
+
+def increment_build_num(lastVer):
+    newVer = SemiSemVersion(lastVer.major, lastVer.minor, lastVer.revision, lastVer.build + 1)
+    return newVer
+
+# -1 if a is older than b; 0 if they're the same version; 1 if a is newer than b
+def compare(a, b):
+    if (a.major > b.major): return 1
+    elif (a.major < b.major): return -1
+    else:
+        if (a.minor > b.minor): return 1
+        elif (a.minor < b.minor): return -1
+        else:
+            if (a.revision > b.revision): return 1
+            elif (a.revision < b.revision): return -1
+            else:
+                if (a.build > b.build): return 1
+                elif (a.build < b.build): return -1
+                else: return 0
+
+version_re = re.compile(r"""^([1-9]\d*|0)(\.([1-9]\d*|0)(\.([1-9]\d*|0)(\+([1-9]\d*|0))?)?)?$""")
+def decode_version(text):
+    """Decode the version string, which should be of the form maj.min.rev+build"""
+    m = version_re.match(text)
+    if m:
+        result = SemiSemVersion(
+                int(m.group(1)) if m.group(1) else 0,
+                int(m.group(3)) if m.group(3) else 0,
+                int(m.group(5)) if m.group(5) else 0,
+                int(m.group(7)) if m.group(7) else 0)
+        return result
+    else:
+        msg = "Invalid version number, should be maj.min.rev+build with later parts optional"
+        raise argparse.ArgumentTypeError(msg)
+
+if __name__ == '__main__':
+    print(decode_version("1.2"))
+    print(decode_version("1.0"))
+    print(decode_version("0.0.2+75"))
+    print(decode_version("0.0.0+00"))
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/macro_parser.py b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/macro_parser.py
new file mode 100644
index 0000000000..5e489a9c57
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/ext/mcuboot/scripts/macro_parser.py
@@ -0,0 +1,70 @@
+#! /usr/bin/env python3
+#
+# -----------------------------------------------------------------------------
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# -----------------------------------------------------------------------------
+
+
+import re
+import os
+
+expression_re = re.compile(r"[(]?(([(]?(((0x)[0-9a-fA-F]+)|([0-9]+))[)]?)\s*([\+\-]\s*([(]?(((0x)[0-9a-fA-F]+)|([0-9]+))[)]?)\s*)*)[)]?")
+
+# Simple parser that takes a string and evaluates an expression from it.
+# The expression might contain additions and subtractions amongst numbers that
+# are written in decimal or hexadecimal form.
+# The parses can process expressions in which the parentheses does not change
+# the sign of the following number or numbers in an expression.
+# Thus the parser can process the following expression: (x + y)
+# However it will not calculate the correct sum for the expression below:
+# (x - (y + z))
+def parse_and_sum(text):
+    m = expression_re.match(text)
+    if m is None:
+        msg = "The script was probably invoked manually"
+        msg += " with having certain macros nested in flash_layouts.h.\n"
+        msg += "Please revisit the flash_layout.h file and hardcode values"
+        msg += " for the (NON-)SECURE_IMAGE_OFFSET and"
+        msg += " (NON-)SECURE_IMAGE_MAX_SIZE macros"
+        raise Exception(msg)
+
+    nums = re.findall(r'(0x[A-Fa-f0-9]+)|[\d]+', m.group(0))
+    for i in range(len(nums)):
+        nums[i] = int(nums[i], 0)
+    ops = re.findall(r'\+|\-', m.group(0))
+    sum = nums[0]
+    for i in range(len(ops)):
+        if ops[i] == '+':
+            sum += nums[i+1]
+        else:
+            sum -= nums[i+1]
+    return sum
+
+
+# Opens a file that contains the macro of interest, then finds the macro with
+# a regular expression, parses the expression that is defined for the given
+# macro. Lastly it evaluates the expression with the parse_and_sum function
+def evaluate_macro(file, regexp, matchGroupKey, matchGroupData):
+    regexp_compiled = re.compile(regexp)
+
+    if os.path.isabs(file):
+        configFile = file
+    else:
+        scriptsDir = os.path.dirname(os.path.abspath(__file__))
+        configFile = os.path.join(scriptsDir, file)
+
+    macroValue = {}
+    with open(configFile, 'r') as macros_preprocessed_file:
+        for line in macros_preprocessed_file:
+            m = regexp_compiled.match(line)
+            if m is not None:
+                macroValue[m.group(matchGroupKey)] = \
+                parse_and_sum(m.group(matchGroupData))
+
+    if (matchGroupKey == 0 and not macroValue):
+        macroValue["None"] = None
+
+    return list(macroValue.values())[0] if (matchGroupKey == 0) else macroValue
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_hal.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_hal.h
new file mode 100644
index 0000000000..03ff53bfa1
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_hal.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __BOOT_HAL_H__
+#define __BOOT_HAL_H__
+
+/* Include header section */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief It clears that part of the RAM which was used by MCUBoot, expect the
+ *        TFM_SHARED_DATA area, which is used to pass data to the TF-M runtime.
+ *
+ * \note  This function must be implemented per target platform by system
+ *        integrator. If the bootloader has not loaded any secret to the shared
+ *        RAM then this function can immediately return to shorten the boot-up
+ *        time. Clearing RAM area can be done several way, it is platform
+ *        dependent:
+ *        - Overwritten with a pre-defined constant value (i.e.: 0).
+ *        - Overwritten with a random value.
+ *        - Change the secret if its location is known.
+ *        - Set a register which can hide some part of the flash/RAM against
+ *          next stage software components.
+ *        - Etc.
+ */
+void boot_clear_bl2_ram_area(void);
+
+/**
+ * \brief Platform peripherals and devices initialization.
+ *        Can be overridden for platform specific initialization.
+ *
+ * \return Returns 0 on success, non-zero otherwise
+ */
+int32_t boot_platform_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOT_HAL_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_record.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_record.h
new file mode 100644
index 0000000000..c39d7525b9
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/boot_record.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __BOOT_RECORD_H__
+#define __BOOT_RECORD_H__
+
+#include 
+#include 
+#include 
+#include "bootutil/image.h"
+#include "flash_map/flash_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * \enum shared_data_err_t
+ *
+ * \brief Return values for adding data entry to shared memory area
+ */
+enum shared_memory_err_t {
+    SHARED_MEMORY_OK = 0,
+    SHARED_MEMORY_OVERFLOW = 1,
+    SHARED_MEMORY_OVERWRITE = 2,
+    SHARED_MEMORY_GEN_ERROR = 3,
+
+    /* This is used to force the maximum size */
+    TLV_TYPE_MAX = INT_MAX
+};
+
+/*!
+ * \enum boot_status_err_t
+ *
+ * \brief Return values for saving boot status information to shared memory area
+ */
+enum boot_status_err_t {
+    BOOT_STATUS_OK,
+    BOOT_STATUS_ERROR,
+};
+
+/*!
+ * \brief Add a data item to the shared data area between bootloader and
+ *        runtime SW
+ *
+ * \param[in] major_type  TLV major type, identify consumer
+ * \param[in] minor_type  TLV minor type, identify TLV type
+ * \param[in] size        length of added data
+ * \param[in] data        pointer to data
+ *
+ * \return Returns error code as specified in \ref shared_memory_err_t
+ */
+enum shared_memory_err_t
+boot_add_data_to_shared_area(uint8_t        major_type,
+                             uint16_t       minor_type,
+                             size_t         size,
+                             const uint8_t *data);
+
+/*!
+ * \brief Add an image's all boot status information to the shared data area
+ *        between bootloader and runtime SW
+ *
+ * \param[in]  sw_module  Identifier of the SW component
+ * \param[in]  hdr        Pointer to the image header stored in RAM
+ * \param[in]  fap        Pointer to the flash area where image is stored
+ *
+ * \return Returns error code as specified in \ref boot_status_err_t
+ */
+enum boot_status_err_t
+boot_save_boot_status(uint8_t sw_module,
+                      const struct image_header *hdr,
+                      const struct flash_area *fap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOT_RECORD_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/tfm_boot_status.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/tfm_boot_status.h
new file mode 100644
index 0000000000..c321d97825
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/include/tfm_boot_status.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_BOOT_STATUS_H__
+#define __TFM_BOOT_STATUS_H__
+
+#include 
+#include 
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Major numbers (4 bit) to identify
+ * the consumer of shared data in runtime SW
+ */
+#define TLV_MAJOR_CORE     0x0
+#define TLV_MAJOR_IAS      0x1
+
+/**
+ * The shared data between boot loader and runtime SW is TLV encoded. The
+ * shared data is stored in a well known location in secure memory and this is
+ * a contract between boot loader and runtime SW.
+ *
+ * The structure of shared data must be the following:
+ *  - At the beginning there must be a header: struct shared_data_tlv_header
+ *    This contains a magic number and a size field which covers the entire
+ *    size of the shared data area including this header.
+ *  - After the header there come the entries which are composed from an entry
+ *    header structure: struct shared_data_tlv_entry and the data. In the entry
+ *    header is a type field (tly_type) which identify the consumer of the
+ *    entry in the runtime SW and specify the subtype of that data item. There
+ *    is a size field (tlv_len) which covers the size of the entry header and
+ *    the data. After this structure comes the actual data.
+ *  - Arbitrary number and size of data entry can be in the shared memory area.
+ *
+ * This table gives of overview about the tlv_type field in the entry header.
+ * The tlv_type always composed from a major and minor number. Major number
+ * identifies the addressee in runtime SW, who should process the data entry.
+ * Minor number used to encode more info about the data entry. The actual
+ * definition of minor number could change per major number. In case of boot
+ * status data, which is going to be processed by initial attestation service
+ * the minor number is split further to two part: sw_module and claim. The
+ * sw_module identifies the SW component in the system which the data item
+ * belongs to and the claim part identifies the exact type of the data.
+ *
+ * |---------------------------------------|
+ * |            tlv_type (16)              |
+ * |---------------------------------------|
+ * | tlv_major(4)|      tlv_minor(12)      |
+ * |---------------------------------------|
+ * | MAJOR_IAS   | sw_module(6) | claim(6) |
+ * |---------------------------------------|
+ * | MAJOR_CORE  |          TBD            |
+ * |---------------------------------------|
+ */
+
+/* Initial attestation: SW components / SW modules
+ * This list is intended to be adjusted per device. It contains more SW
+ * components than currently available in TF-M project. It serves as an example,
+ * what kind of SW components might be available.
+ */
+#define SW_GENERAL     0x00
+#define SW_BL2         0x01
+#define SW_PROT        0x02
+#define SW_AROT        0x03
+#define SW_SPE         0x04
+#define SW_NSPE        0x05
+#define SW_S_NS        0x06
+#define SW_MAX         0x07
+
+/* Initial attestation: Claim per SW components / SW modules */
+/* Bits: 0-2 */
+#define SW_VERSION       0x00
+#define SW_SIGNER_ID     0x01
+/* Reserved              0x02 */
+#define SW_TYPE          0x03
+/* Bits: 3-5 */
+#define SW_MEASURE_VALUE 0x08
+#define SW_MEASURE_TYPE  0x09
+#define SW_BOOT_RECORD   0x3F
+
+/* Initial attestation: General claim does not belong any particular SW
+ * component. But they might be part of the boot status.
+ */
+#define BOOT_SEED          0x00
+#define HW_VERSION         0x01
+#define SECURITY_LIFECYCLE 0x02
+
+/* Minor numbers (12 bit) to identify attestation service related data */
+#define TLV_MINOR_IAS_BOOT_SEED       ((SW_GENERAL << 6) | BOOT_SEED)
+#define TLV_MINOR_IAS_HW_VERSION      ((SW_GENERAL << 6) | HW_VERSION)
+#define TLV_MINOR_IAS_SLC             ((SW_GENERAL << 6) | SECURITY_LIFECYCLE)
+
+/* Bootloader - It can be more stage */
+#define TLV_MINOR_IAS_BL2_MEASURE_VALUE  ((SW_BL2  << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_BL2_MEASURE_TYPE   ((SW_BL2  << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_BL2_VERSION        ((SW_BL2  << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_BL2_SIGNER_ID      ((SW_BL2  << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_BL2_TYPE           ((SW_BL2  << 6) | SW_TYPE)
+
+/* PROT: PSA Root of Trust */
+#define TLV_MINOR_IAS_PROT_MEASURE_VALUE ((SW_PROT << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_PROT_MEASURE_TYPE  ((SW_PROT << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_PROT_VERSION       ((SW_PROT << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_PROT_SIGNER_ID     ((SW_PROT << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_PROT_TYPE          ((SW_PROT << 6) | SW_TYPE)
+
+/* AROT: Application Root of Trust */
+#define TLV_MINOR_IAS_AROT_MEASURE_VALUE ((SW_AROT << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_AROT_MEASURE_TYPE  ((SW_AROT << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_AROT_VERSION       ((SW_AROT << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_AROT_SIGNER_ID     ((SW_AROT << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_AROT_TYPE          ((SW_AROT << 6) | SW_TYPE)
+
+/* Non-secure processing environment - single non-secure image */
+#define TLV_MINOR_IAS_NSPE_MEASURE_VALUE ((SW_NSPE << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_NSPE_MEASURE_TYPE  ((SW_NSPE << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_NSPE_VERSION       ((SW_NSPE << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_NSPE_SIGNER_ID     ((SW_NSPE << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_NSPE_TYPE          ((SW_NSPE << 6) | SW_TYPE)
+
+/* Secure processing environment (ARoT + PRoT) - single secure image */
+#define TLV_MINOR_IAS_SPE_MEASURE_VALUE  ((SW_SPE  << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_SPE_MEASURE_TYPE   ((SW_SPE  << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_SPE_VERSION        ((SW_SPE  << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_SPE_SIGNER_ID      ((SW_SPE  << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_SPE_TYPE           ((SW_SPE  << 6) | SW_TYPE)
+
+/* SPE + NSPE - combined secure and non-secure image */
+#define TLV_MINOR_IAS_S_NS_MEASURE_VALUE ((SW_S_NS << 6) | SW_MEASURE_VALUE)
+#define TLV_MINOR_IAS_S_NS_MEASURE_TYPE  ((SW_S_NS << 6) | SW_MEASURE_TYPE)
+#define TLV_MINOR_IAS_S_NS_VERSION       ((SW_S_NS << 6) | SW_VERSION)
+#define TLV_MINOR_IAS_S_NS_SIGNER_ID     ((SW_S_NS << 6) | SW_SIGNER_ID)
+#define TLV_MINOR_IAS_S_NS_TYPE          ((SW_S_NS << 6) | SW_TYPE)
+
+/* General macros to handle TLV type */
+#define MAJOR_MASK 0xF     /* 4  bit */
+#define MAJOR_POS  12      /* 12 bit */
+#define MINOR_MASK 0xFFF   /* 12 bit */
+
+#define SET_TLV_TYPE(major, minor) \
+        ((((major) & MAJOR_MASK) << MAJOR_POS) | ((minor) & MINOR_MASK))
+#define GET_MAJOR(tlv_type) ((tlv_type) >> MAJOR_POS)
+#define GET_MINOR(tlv_type) ((tlv_type) &  MINOR_MASK)
+
+/* Initial attestation specific macros */
+#define MODULE_POS 6               /* 6 bit */
+#define CLAIM_MASK 0x3F            /* 6 bit */
+#define MEASUREMENT_CLAIM_POS 3    /* 3 bit */
+
+#define GET_IAS_MODULE(tlv_type) (GET_MINOR(tlv_type) >> MODULE_POS)
+#define GET_IAS_CLAIM(tlv_type)  (GET_MINOR(tlv_type)  & CLAIM_MASK)
+#define SET_IAS_MINOR(sw_module, claim) (((sw_module) << 6) | (claim))
+
+#define GET_IAS_MEASUREMENT_CLAIM(ias_claim) ((ias_claim) >> \
+                                              MEASUREMENT_CLAIM_POS)
+
+/* Magic value which marks the beginning of shared data area in memory */
+#define SHARED_DATA_TLV_INFO_MAGIC    0x2016
+
+/**
+ * Shared data TLV header.  All fields in little endian.
+ *
+ *    -----------------------------------
+ *    | tlv_magic(16) | tlv_tot_len(16) |
+ *    -----------------------------------
+ */
+struct shared_data_tlv_header {
+    uint16_t tlv_magic;
+    uint16_t tlv_tot_len; /* size of whole TLV area (including this header) */
+};
+
+#define SHARED_DATA_HEADER_SIZE sizeof(struct shared_data_tlv_header)
+
+/**
+ * Shared data TLV entry header format. All fields in little endian.
+ *
+ *    -------------------------------
+ *    | tlv_type(16) |  tlv_len(16) |
+ *    -------------------------------
+ *    |         Raw data            |
+ *    -------------------------------
+ */
+struct shared_data_tlv_entry {
+    uint16_t tlv_type;
+    uint16_t tlv_len; /* size of single TLV entry (including this header). */
+};
+
+/**
+ * \struct tfm_boot_data
+ *
+ * \brief Store the data for the runtime SW
+ */
+struct tfm_boot_data {
+    struct shared_data_tlv_header header;
+    uint8_t data[];
+};
+
+#define SHARED_DATA_ENTRY_HEADER_SIZE sizeof(struct shared_data_tlv_entry)
+#define SHARED_DATA_ENTRY_SIZE(size) (size + SHARED_DATA_ENTRY_HEADER_SIZE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TFM_BOOT_STATUS_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/boot_record.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/boot_record.c
new file mode 100644
index 0000000000..c9483f6ffe
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/boot_record.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "boot_record.h"
+#include "region_defs.h"
+#include "tfm_boot_status.h"
+#include "target.h"
+#include "../ext/mcuboot/bootutil/src/bootutil_priv.h"
+#include "bootutil/image.h"
+#include "bootutil/sha256.h"
+#include "flash_map/flash_map.h"
+#include 
+#include 
+#include 
+
+#define SHA256_HASH_SIZE    (32u)
+#if defined(MCUBOOT_SIGN_RSA) && defined(MCUBOOT_HW_KEY)
+#   define SIG_BUF_SIZE     (MCUBOOT_SIGN_RSA_LEN / 8)
+#endif
+
+/*!
+ * \def MAX_BOOT_RECORD_SZ
+ *
+ * \brief Maximum size of the measured boot record.
+ *
+ * Its size can be calculated based on the following aspects:
+ *   - There are 5 allowed software component claims,
+ *   - SHA256 is used as the measurement method for the other claims.
+ * Considering these aspects, the only claim which size can vary is the
+ * type of the software component. In case of single image boot it is
+ * "NSPE_SPE" which results the maximum boot record size of 96.
+ */
+#define MAX_BOOT_RECORD_SZ  (96u)
+
+/*!
+ * \var shared_memory_init_done
+ *
+ * \brief Indicates whether shared memory area was already initialized.
+ *
+ */
+static uint32_t shared_memory_init_done;
+
+/*!
+ * \def SHARED_MEMORY_UNINITIALZED
+ *
+ * \brief Indicates that shared memory is uninitialized.
+ */
+#define SHARED_MEMORY_UNINITIALZED (0u)
+
+/*!
+ * \def SHARED_MEMORY_INITIALZED
+ *
+ * \brief Indicates that shared memory was already initialized.
+ */
+#define SHARED_MEMORY_INITIALZED   (1u)
+
+/* Compile time check to verify that shared data region is not overlapping with
+ * non-secure data area.
+ */
+#if ((BOOT_TFM_SHARED_DATA_BASE  >= NS_DATA_START && \
+      BOOT_TFM_SHARED_DATA_BASE  <= NS_DATA_LIMIT) || \
+     (BOOT_TFM_SHARED_DATA_LIMIT >= NS_DATA_START && \
+      BOOT_TFM_SHARED_DATA_LIMIT <= NS_DATA_LIMIT))
+#error "Shared data area and non-secure data area is overlapping"
+#endif
+
+#ifdef MCUBOOT_INDIVIDUAL_CLAIMS
+/*!
+ * \brief Add the measurement data of SW component to the shared memory area
+ *
+ * Measurements data are:
+ *  - measurement value:  Hash of the image, read out from the image's manifest
+ *                        section.
+ *  - measurement type:   Short test description: SHA256, etc.
+ *  - signer ID:          Hash of the image public key, read out from the
+ *                        image's manifest section.
+ *
+ * \param[in]  sw_module  Identifier of the SW component
+ * \param[in]  hdr        Pointer to the image header stored in RAM
+ * \param[in]  fap        Pointer to the flash area where image is stored
+ *
+ * \return Returns error code as specified in \ref boot_status_err_t
+ */
+static enum boot_status_err_t
+boot_save_sw_measurements(uint8_t sw_module,
+                          const struct image_header *hdr,
+                          const struct flash_area *fap)
+{
+    struct image_tlv_iter it;
+    uint32_t offset;
+    uint16_t len;
+    uint8_t type;
+    uint8_t buf[32];
+    int32_t res;
+    uint16_t ias_minor;
+    enum shared_memory_err_t res2;
+    char measure_type[] = "SHA256";
+#if defined(MCUBOOT_SIGN_RSA) && defined(MCUBOOT_HW_KEY)
+    /* Few extra bytes for encoding and for public exponent */
+    uint8_t key_buf[SIG_BUF_SIZE + 24];
+    bootutil_sha256_context sha256_ctx;
+#endif
+
+    /* Manifest data is concatenated to the end of the image. It is encoded in
+     * TLV format.
+     */
+
+    res = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Iterates over the manifest data and copy the relevant attributes to the
+     * shared data area:
+     *  - image hash:      SW component measurement value
+     *  - public key hash: Signer ID
+     */
+    while (true) {
+        res = bootutil_tlv_iter_next(&it, &offset, &len, &type);
+        if (res < 0) {
+            return BOOT_STATUS_ERROR;
+        } else if (res > 0) {
+            break;
+        }
+
+        if (type == IMAGE_TLV_SHA256) {
+            /* Get the image's hash value from the manifest section */
+            if (len != sizeof(buf)) { /* SHA256 - 32 bytes */
+                return BOOT_STATUS_ERROR;
+            }
+
+            res = LOAD_IMAGE_DATA(hdr, fap, offset, buf, len);
+            if (res) {
+                return BOOT_STATUS_ERROR;
+            }
+
+            /* Add the image's hash value to the shared data area */
+            ias_minor = SET_IAS_MINOR(sw_module, SW_MEASURE_VALUE);
+            res2 = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                                ias_minor,
+                                                len,
+                                                buf);
+            if (res2) {
+                return BOOT_STATUS_ERROR;
+            }
+
+            /* Add the measurement type to the shared data area */
+            ias_minor = SET_IAS_MINOR(sw_module, SW_MEASURE_TYPE);
+            res2 = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                                ias_minor,
+                                                sizeof(measure_type) - 1,
+                                                (const uint8_t *)measure_type);
+            if (res2) {
+                return BOOT_STATUS_ERROR;
+            }
+
+#ifdef MCUBOOT_SIGN_RSA
+#ifndef MCUBOOT_HW_KEY
+        } else if (type == IMAGE_TLV_KEYHASH) {
+            /* Get the hash of the public key from the manifest section */
+            if (len != sizeof(buf)) { /* SHA256 - 32 bytes */
+                return BOOT_STATUS_ERROR;
+            }
+
+            res = LOAD_IMAGE_DATA(hdr, fap, offset, buf, len);
+            if (res) {
+                return BOOT_STATUS_ERROR;
+            }
+#else /* MCUBOOT_HW_KEY */
+        } else if (type == IMAGE_TLV_KEY) {
+            /* Get the public key from the manifest section. */
+            if (len > sizeof(key_buf)) {
+                return BOOT_STATUS_ERROR;
+            }
+            res = LOAD_IMAGE_DATA(hdr, fap, offset, key_buf, len);
+            if (res) {
+                return BOOT_STATUS_ERROR;
+            }
+
+            /* Calculate the hash of the public key. */
+            bootutil_sha256_init(&sha256_ctx);
+            bootutil_sha256_update(&sha256_ctx, key_buf, len);
+            bootutil_sha256_finish(&sha256_ctx, buf);
+#endif /* MCUBOOT_HW_KEY */
+
+            /* Add the hash of the public key to the shared data area */
+            ias_minor = SET_IAS_MINOR(sw_module, SW_SIGNER_ID);
+            res2 = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                                ias_minor,
+                                                SHA256_HASH_SIZE,
+                                                buf);
+            if (res2) {
+                return BOOT_STATUS_ERROR;
+            }
+#endif
+        }
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+ * \brief Add a type identifier(short test name) of SW component to the shared
+ *        memory area
+ *
+ * \param[in]  sw_module  Identifier of the SW component
+ *
+ * \return Returns error code as specified in \ref boot_status_err_t
+ */
+static enum boot_status_err_t
+boot_save_sw_type(uint8_t sw_module)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+    const char *sw_type;
+    static const char sw_comp_s[] = "SPE";
+    static const char sw_comp_ns[] = "NSPE";
+    static const char sw_comp_ns_s[] = "NSPE_SPE";
+
+    switch (sw_module) {
+    case SW_SPE:
+        sw_type = sw_comp_s;
+        break;
+    case SW_NSPE:
+        sw_type = sw_comp_ns;
+        break;
+    case SW_S_NS:
+        sw_type = sw_comp_ns_s;
+        break;
+    default:
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Add the type identifier of the SW component to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_TYPE);
+    res = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                       ias_minor,
+                                       strlen(sw_type),
+                                       (const uint8_t *)sw_type);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+ * \brief Add the version of SW component to the shared memory area
+ *
+ * \param[in]  sw_module  Identifier of the SW component
+ * \param[in]  hdr        Pointer to the image header stored in RAM
+ *
+ * \return Returns error code as specified in \ref boot_status_err_t
+ */
+static enum boot_status_err_t
+boot_save_sw_version(uint8_t sw_module,
+                     const struct image_header *hdr)
+{
+    int32_t cnt;
+    enum shared_memory_err_t res;
+    char sw_version[14]; /* 8bit.8bit.16bit: 3 + 1 + 3 + 1 + 5 + 1 */
+    uint16_t ias_minor;
+
+    /* FixMe: snprintf can be replaced with a custom implementation */
+    cnt = snprintf(sw_version, sizeof(sw_version), "%u.%u.%u",
+                   hdr->ih_ver.iv_major,
+                   hdr->ih_ver.iv_minor,
+                   hdr->ih_ver.iv_revision);
+    if (cnt < 0 || cnt >= sizeof(sw_version)) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Add the version of the SW component to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_VERSION);
+    res = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                       ias_minor,
+                                       cnt,
+                                       (const uint8_t *)sw_version);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+#endif /* MCUBOOT_INDIVIDUAL_CLAIMS */
+
+/* See in boot_record.h */
+enum shared_memory_err_t
+boot_add_data_to_shared_area(uint8_t        major_type,
+                             uint16_t       minor_type,
+                             size_t         size,
+                             const uint8_t *data)
+{
+#if 0  //HACK
+    struct shared_data_tlv_entry tlv_entry = {0};
+    struct tfm_boot_data *boot_data;
+    uint8_t *next_tlv;
+    uint16_t boot_data_size;
+    uintptr_t tlv_end, offset;
+
+    boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE;
+
+    /* Check whether first time to call this function. If does then initialise
+     * shared data area.
+     */
+    if (shared_memory_init_done == SHARED_MEMORY_UNINITIALZED) {
+        memset((void *)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE);
+        boot_data->header.tlv_magic   = SHARED_DATA_TLV_INFO_MAGIC;
+        boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE;
+        shared_memory_init_done = SHARED_MEMORY_INITIALZED;
+    }
+
+    /* Check whether TLV entry is already added.
+     * Get the boundaries of TLV section
+     */
+    tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len;
+    offset  = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE;
+
+    /* Iterates over the TLV section looks for the same entry if found then
+     * returns with error: SHARED_MEMORY_OVERWRITE
+     */
+    for (; offset < tlv_end; offset += tlv_entry.tlv_len) {
+        /* Create local copy to avoid unaligned access */
+        memcpy(&tlv_entry, (const void *)offset, SHARED_DATA_ENTRY_HEADER_SIZE);
+        if (GET_MAJOR(tlv_entry.tlv_type) == major_type &&
+            GET_MINOR(tlv_entry.tlv_type) == minor_type) {
+            return SHARED_MEMORY_OVERWRITE;
+        }
+    }
+
+    /* Add TLV entry */
+    tlv_entry.tlv_type = SET_TLV_TYPE(major_type, minor_type);
+    tlv_entry.tlv_len  = SHARED_DATA_ENTRY_SIZE(size);
+
+    if (!boot_u16_safe_add(&boot_data_size, boot_data->header.tlv_tot_len,
+                           tlv_entry.tlv_len)) {
+        return SHARED_MEMORY_GEN_ERROR;
+    }
+
+    /* Verify overflow of shared area */
+    if (boot_data_size > BOOT_TFM_SHARED_DATA_SIZE) {
+        return SHARED_MEMORY_OVERFLOW;
+    }
+
+    next_tlv = (uint8_t *)boot_data + boot_data->header.tlv_tot_len;
+    memcpy(next_tlv, &tlv_entry, SHARED_DATA_ENTRY_HEADER_SIZE);
+
+    next_tlv += SHARED_DATA_ENTRY_HEADER_SIZE;
+    memcpy(next_tlv, data, size);
+
+    boot_data->header.tlv_tot_len += tlv_entry.tlv_len;
+
+    return SHARED_MEMORY_OK;
+#endif
+}
+
+/* See in boot_record.h */
+enum boot_status_err_t
+boot_save_boot_status(uint8_t sw_module,
+                      const struct image_header *hdr,
+                      const struct flash_area *fap)
+{
+#ifdef MCUBOOT_INDIVIDUAL_CLAIMS
+    /* This implementation is deprecated and will probably
+     * be removed in the future.
+     */
+
+    enum boot_status_err_t res;
+
+    res = boot_save_sw_type(sw_module);
+    if (res) {
+        return res;
+    }
+
+    res = boot_save_sw_version(sw_module, hdr);
+    if (res) {
+        return res;
+    }
+
+    res = boot_save_sw_measurements(sw_module, hdr, fap);
+    if (res) {
+        return res;
+    }
+
+    return BOOT_STATUS_OK;
+
+#else /* MCUBOOT_INDIVIDUAL_CLAIMS */
+
+    struct image_tlv_iter it;
+    uint32_t offset;
+    uint16_t len;
+    uint8_t type;
+    size_t record_len = 0;
+    uint8_t image_hash[32]; /* SHA256 - 32 Bytes */
+    uint8_t buf[MAX_BOOT_RECORD_SZ];
+    uint32_t boot_record_found = 0;
+    uint32_t hash_found = 0;
+    uint16_t ias_minor;
+    int32_t res;
+    enum shared_memory_err_t res2;
+
+    /* Manifest data is concatenated to the end of the image.
+     * It is encoded in TLV format.
+     */
+
+    res = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Traverse through the TLV area to find the boot record
+     * and image hash TLVs.
+     */
+    while (true) {
+        res = bootutil_tlv_iter_next(&it, &offset, &len, &type);
+        if (res < 0) {
+            return BOOT_STATUS_ERROR;
+        } else if (res > 0) {
+            break;
+        }
+
+        if (type == IMAGE_TLV_BOOT_RECORD) {
+            if (len > sizeof(buf)) {
+                return BOOT_STATUS_ERROR;
+            }
+            res = LOAD_IMAGE_DATA(hdr, fap, offset, buf, len);
+            if (res) {
+                return BOOT_STATUS_ERROR;
+            }
+
+            record_len = len;
+            boot_record_found = 1;
+
+        } else if (type == IMAGE_TLV_SHA256) {
+            /* Get the image's hash value from the manifest section. */
+            if (len > sizeof(image_hash)) {
+                return BOOT_STATUS_ERROR;
+            }
+            res = LOAD_IMAGE_DATA(hdr, fap, offset, image_hash, len);
+            if (res) {
+                return BOOT_STATUS_ERROR;
+            }
+
+            hash_found = 1;
+
+            /* The boot record TLV is part of the protected TLV area which is
+             * located before the other parts of the TLV area (including the
+             * image hash) so at this point it is okay to break the loop
+             * as the boot record TLV should have already been found.
+             */
+            break;
+        }
+    }
+
+
+    if (!boot_record_found || !hash_found) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Update the measurement value (hash of the image) data item in the
+     * boot record. It is always the last item in the structure to make
+     * it easy to calculate its position.
+     * The image hash is computed over the image header, the image itself and
+     * the protected TLV area (which should already include the image hash as
+     * part of the boot record TLV). For this reason this field has been
+     * filled with zeros during the image signing process.
+     */
+    offset = record_len - sizeof(image_hash);
+    /* Avoid buffer overflow. */
+    if ((offset + sizeof(image_hash)) > sizeof(buf)) {
+        return BOOT_STATUS_ERROR;
+    }
+    memcpy(buf + offset, image_hash, sizeof(image_hash));
+
+    /* Add the CBOR encoded boot record to the shared data area. */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_BOOT_RECORD);
+    res2 = boot_add_data_to_shared_area(TLV_MAJOR_IAS,
+                                        ias_minor,
+                                        record_len,
+                                        buf);
+    if (res2) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+
+#endif /* MCUBOOT_INDIVIDUAL_CLAIMS */
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/flash_map.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/flash_map.c
new file mode 100644
index 0000000000..72e7ca137a
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/flash_map.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include 
+#include "target.h"
+#include "bl2_util.h"
+#include "flash_map/flash_map.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "bootutil/bootutil_log.h"
+#include "Driver_Flash.h"
+
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+static const struct flash_area flash_map[] = {
+    {
+        .fa_id = FLASH_AREA_0_ID,
+        .fa_device_id = FLASH_DEVICE_ID,
+        .fa_off = FLASH_AREA_0_OFFSET,
+        .fa_size = FLASH_AREA_0_SIZE,
+    },
+    {
+        .fa_id = FLASH_AREA_2_ID,
+        .fa_device_id = FLASH_DEVICE_ID,
+        .fa_off = FLASH_AREA_2_OFFSET,
+        .fa_size = FLASH_AREA_2_SIZE,
+    },
+#if (MCUBOOT_IMAGE_NUMBER == 2)
+    {
+        .fa_id = FLASH_AREA_1_ID,
+        .fa_device_id = FLASH_DEVICE_ID,
+        .fa_off = FLASH_AREA_1_OFFSET,
+        .fa_size = FLASH_AREA_1_SIZE,
+    },
+    {
+        .fa_id = FLASH_AREA_3_ID,
+        .fa_device_id = FLASH_DEVICE_ID,
+        .fa_off = FLASH_AREA_3_OFFSET,
+        .fa_size = FLASH_AREA_3_SIZE,
+    },
+#endif
+    {
+        .fa_id = FLASH_AREA_SCRATCH_ID,
+        .fa_device_id = FLASH_DEVICE_ID,
+        .fa_off = FLASH_AREA_SCRATCH_OFFSET,
+        .fa_size = FLASH_AREA_SCRATCH_SIZE,
+    },
+};
+
+static const int flash_map_entry_num = ARRAY_SIZE(flash_map);
+
+/*
+ * `open` a flash area.  The `area` in this case is not the individual
+ * sectors, but describes the particular flash area in question.
+ */
+int flash_area_open(uint8_t id, const struct flash_area **area)
+{
+    int i;
+
+    BOOT_LOG_DBG("area %d", id);
+
+    for (i = 0; i < flash_map_entry_num; i++) {
+        if (id == flash_map[i].fa_id) {
+            break;
+        }
+    }
+    if (i == flash_map_entry_num) {
+        return -1;
+    }
+
+    *area = &flash_map[i];
+    return 0;
+}
+
+void flash_area_close(const struct flash_area *area)
+{
+    /* Nothing to do. */
+}
+
+int flash_area_read(const struct flash_area *area, uint32_t off, void *dst,
+                    uint32_t len)
+{
+    BOOT_LOG_DBG("read area=%d, off=%#x, len=%#x", area->fa_id, off, len);
+    return FLASH_DEV_NAME.ReadData(area->fa_off + off, dst, len);
+}
+
+int flash_area_write(const struct flash_area *area, uint32_t off,
+                     const void *src, uint32_t len)
+{
+    BOOT_LOG_DBG("write area=%d, off=%#x, len=%#x", area->fa_id, off, len);
+    return FLASH_DEV_NAME.ProgramData(area->fa_off + off, src, len);
+}
+
+int flash_area_erase(const struct flash_area *area, uint32_t off, uint32_t len)
+{
+    ARM_FLASH_INFO *flash_info;
+    uint32_t deleted_len = 0;
+    int32_t rc = 0;
+
+    BOOT_LOG_DBG("erase area=%d, off=%#x, len=%#x", area->fa_id, off, len);
+    flash_info = FLASH_DEV_NAME.GetInfo();
+
+    if (flash_info->sector_info == NULL) {
+        /* Uniform sector layout */
+        while (deleted_len < len) {
+            rc = FLASH_DEV_NAME.EraseSector(area->fa_off + off);
+            if (rc != 0) {
+                break;
+            }
+            deleted_len += flash_info->sector_size;
+            off         += flash_info->sector_size;
+        }
+    } else {
+        /* Inhomogeneous sector layout, explicitly defined
+         * Currently not supported.
+         */
+    }
+
+    return rc;
+}
+
+uint32_t flash_area_align(const struct flash_area *area)
+{
+    ARM_FLASH_INFO *flash_info;
+
+    flash_info = FLASH_DEV_NAME.GetInfo();
+    return flash_info->program_unit;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/security_cnt.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/security_cnt.c
new file mode 100644
index 0000000000..825a2d67d0
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/bl2/src/security_cnt.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "../ext/mcuboot/include/security_cnt.h"
+#include "../../platform/include/tfm_plat_nv_counters.h"
+#include "../../platform/include/tfm_plat_defs.h"
+#include 
+
+#define TFM_BOOT_NV_COUNTER_0    PLAT_NV_COUNTER_3   /* NV counter of Image 0 */
+#define TFM_BOOT_NV_COUNTER_1    PLAT_NV_COUNTER 4   /* NV counter of Image 1 */
+#define TFM_BOOT_NV_COUNTER_MAX  PLAT_NV_COUNTER_MAX
+
+static enum tfm_nv_counter_t get_nv_counter_from_image_id(uint32_t image_id)
+{
+    uint32_t nv_counter;
+
+    /* Avoid integer overflow */
+    if ((UINT32_MAX - TFM_BOOT_NV_COUNTER_0) < image_id) {
+        return TFM_BOOT_NV_COUNTER_MAX;
+    }
+
+    nv_counter = TFM_BOOT_NV_COUNTER_0 + image_id;
+
+    /* Check the existence of the enumerated counter value */
+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
+        return TFM_BOOT_NV_COUNTER_MAX;
+    }
+
+    return (enum tfm_nv_counter_t)nv_counter;
+}
+
+int32_t boot_nv_security_counter_init(void)
+{
+    enum tfm_plat_err_t err;
+
+    err = tfm_plat_init_nv_counter();
+    if (err != TFM_PLAT_ERR_SUCCESS) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int32_t boot_nv_security_counter_get(uint32_t image_id, uint32_t *security_cnt)
+{
+    enum tfm_nv_counter_t nv_counter;
+    enum tfm_plat_err_t err;
+
+    /* Check if it's a null-pointer. */
+    if (!security_cnt) {
+        return -1;
+    }
+
+    nv_counter = get_nv_counter_from_image_id(image_id);
+    if (nv_counter == TFM_BOOT_NV_COUNTER_MAX) {
+        return -1;
+    }
+
+    err = tfm_plat_read_nv_counter(nv_counter,
+                                   sizeof(*security_cnt),
+                                   (uint8_t *)security_cnt);
+    if (err != TFM_PLAT_ERR_SUCCESS) {
+        return -1;
+    }
+
+    return 0;
+}
+
+int32_t boot_nv_security_counter_update(uint32_t image_id,
+                                        uint32_t img_security_cnt)
+{
+    enum tfm_nv_counter_t nv_counter;
+    enum tfm_plat_err_t err;
+
+    nv_counter = get_nv_counter_from_image_id(image_id);
+    if (nv_counter == TFM_BOOT_NV_COUNTER_MAX) {
+        return -1;
+    }
+
+    err = tfm_plat_set_nv_counter(nv_counter, img_security_cnt);
+    if (err != TFM_PLAT_ERR_SUCCESS) {
+        return -1;
+    }
+
+    return 0;
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/hal_entry.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/hal_entry.c
new file mode 100644
index 0000000000..876d72e7bd
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/hal_entry.c
@@ -0,0 +1,42 @@
+#include "hal_data.h"
+
+FSP_CPP_HEADER
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+FSP_CPP_FOOTER
+
+int bl2_main(void);
+
+/*******************************************************************************************************************//**
+ * The RA Configuration tool generates main() and uses it to generate threads if an RTOS is used.  This function is
+ * called by main() when no RTOS is used.
+ **********************************************************************************************************************/
+void hal_entry(void) {
+	/* TODO: add your own code here */
+    bl2_main();
+}
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart(bsp_warm_start_event_t event) {
+	if (BSP_WARM_START_RESET == event) {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+		/* Enable reading from data flash. */
+		R_FACI_LP->DFLCTL = 1U;
+
+		/* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+		 * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+	}
+
+	if (BSP_WARM_START_POST_C == event) {
+		/* C runtime environment and system clocks are setup. */
+
+		/* Configure pins. */
+		R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+	}
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_armclang.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_armclang.h
new file mode 100644
index 0000000000..c024ff0ee8
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_armclang.h
@@ -0,0 +1,1796 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//lint -esym(9058, IRQn)   disable MISRA 2012 Rule 2.4 for IRQn
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include     /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32)  disable MISRA 2012 Rule 2.4 for T_UINT32
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT16_READ)  disable MISRA 2012 Rule 2.4 for T_UINT16_READ
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_WRITE)  disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+//lint -esym(9058, T_UINT32_READ)  disable MISRA 2012 Rule 2.4 for T_UINT32_READ
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_compiler.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_compiler.h
new file mode 100644
index 0000000000..5a828c3d54
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_compiler.h
@@ -0,0 +1,325 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include 
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+
+  #include 
+
+  /* CMSIS compiler control architecture macros */
+  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+    #ifndef __ARM_ARCH_6M__
+      #define __ARM_ARCH_6M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7M__)
+    #ifndef __ARM_ARCH_7M__
+      #define __ARM_ARCH_7M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7EM__)
+    #ifndef __ARM_ARCH_7EM__
+      #define __ARM_ARCH_7EM__                     1
+    #endif
+  #endif
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        __packed struct
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    __packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+
+  // Workaround for missing __CLZ intrinsic in
+  // various versions of the IAR compilers.
+  // __IAR_FEATURE_CLZ__ should be defined by
+  // the compiler that supports __CLZ internally.
+  #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+    __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+    {
+      if (data == 0u) { return 32u; }
+      
+      uint32_t count = 0;
+      uint32_t mask = 0x80000000;
+      
+      while ((data & mask) == 0)
+      {
+        count += 1u;
+        mask = mask >> 1u;
+      }
+      
+      return (count);
+    }
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include 
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include 
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_gcc.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_gcc.h
new file mode 100644
index 0000000000..ec28b86da8
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_gcc.h
@@ -0,0 +1,2026 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_version.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_version.h
new file mode 100644
index 0000000000..d458a6c859
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm23.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm23.h
new file mode 100644
index 0000000000..db8938ef9a
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm23.h
@@ -0,0 +1,1888 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.3
+ * @date     09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm33.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm33.h
new file mode 100644
index 0000000000..bcaff9588d
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/cmsis/core_cm33.h
@@ -0,0 +1,2898 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )     /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/boot_hal.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/boot_hal.c
new file mode 100644
index 0000000000..3f71fdd888
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/boot_hal.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+//#include "cmsis.h"
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+#include "bootutil/bootutil_log.h"
+
+#if defined(__ARMCC_VERSION)
+__attribute__((naked)) void boot_clear_bl2_ram_area(void)
+{
+    __asm volatile(
+        ".syntax unified                             \n"
+        "mov     r0, #0                              \n"
+        "ldr     r1, =Image$$ER_DATA$$Base           \n"
+        "ldr     r2, =Image$$ARM_LIB_HEAP$$ZI$$Limit \n"
+        "subs    r2, r2, r1                          \n"
+        "Loop:                                       \n"
+        "subs    r2, #4                              \n"
+        "itt     ge                                  \n"
+        "strge   r0, [r1, r2]                        \n"
+        "bge     Loop                                \n"
+        "bx      lr                                  \n"
+         : : : "r0" , "r1" , "r2" , "memory"
+    );
+}
+#endif
+
+#define FAW_START_ADDR       (0xFFFC)
+#define FAW_END_ADDR         (0x200000)
+
+/* Flash device name must be specified by target */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+static void flash_FAW_Set(uint32_t start_addr, uint32_t end_addr)
+{
+    int ret_val = 0;
+
+    volatile uint32_t faws =  (uint32_t) ((R_FACI_HP->FAWMON_b.FAWS) << 13);
+    volatile uint32_t fawe =  (uint32_t) ((R_FACI_HP->FAWMON_b.FAWE) << 13);
+
+    if(faws == fawe)
+    {
+        BOOT_LOG_INF("Configuring FAW settings");
+        FSP_CRITICAL_SECTION_DEFINE;
+        FSP_CRITICAL_SECTION_ENTER;
+        ret_val = R_FLASH_HP_AccessWindowSet(&g_flash_ctrl, start_addr, end_addr);
+        FSP_CRITICAL_SECTION_EXIT;
+        if(ret_val)
+        {
+            BOOT_LOG_ERR("Failed to set Flash Access Window: 0x%x",ret_val);
+        }
+    }
+}
+
+
+/* bootloader platform-specific HW intialization */
+int32_t boot_platform_init(void)
+{
+    int32_t result;
+
+    result = FLASH_DEV_NAME.Initialize(NULL);
+    if(ARM_DRIVER_OK != result)
+    {
+        BOOT_LOG_ERR("");
+        while(1);
+    }
+
+    /* Set the FAW to lock the Secure code and data region */
+    flash_FAW_Set(FAW_START_ADDR, FAW_END_ADDR);
+
+    result = mbedtls_platform_setup(NULL);
+    if(result != 0) {
+        BOOT_LOG_ERR("mbedtls_platform_setup failed!!!");
+        while(1)
+            ;
+    }
+
+    result = psa_crypto_init();
+    if(result != 0) {
+        BOOT_LOG_ERR("psa_crypto_init failed!!!");
+        while(1)
+            ;
+    }
+
+    return result;
+}
diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/RTT_User_Interface.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.c
similarity index 51%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/RTT_User_Interface.h
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.c
index 6af96baf49..6ee9aa323e 100644
--- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/RTT_User_Interface.h
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.c
@@ -1,7 +1,3 @@
-/***********************************************************************************************************************
- * File Name    : RTT_User_Interface.h
- * Description  : Contains RTT Viewer input and output related macros and function definition
- ***********************************************************************************************************************/
 /***********************************************************************************************************************
  * DISCLAIMER
  * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
@@ -18,32 +14,75 @@
  * following link:
  * http://www.renesas.com/disclaimer
  *
- * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
  ***********************************************************************************************************************/
 
+#include "uart_stdout.h"
+
+#include 
+#include 
+#include 
+#include 
+#include "hal_data.h"
+//#include "target_cfg.h"
+
+
+#define ASSERT_HIGH(X)  assert(X == ARM_DRIVER_OK)
+
+
+/* Imports USART driver */
+extern ARM_DRIVER_USART   Driver_USART;
+
+int _write(int fd, char *str, int len);
+
+static void uart_putc(unsigned char c)
+{
+    int32_t ret = ARM_DRIVER_OK;
+
+    ret = Driver_USART.Send(&c, 1);
+    ASSERT_HIGH(ret);
+}
+
+/* Redirects printf to TFM_DRIVER_STDIO in case of ARMCLANG*/
+#if defined(__ARMCC_VERSION)
+/* __ARMCC_VERSION is only defined starting from Arm compiler version 6 */
+int fputc(int ch, FILE *f)
+{
+    /* Send byte to USART */
+    uart_putc(ch);
+
+    /* Return character written */
+    return ch;
+}
+#elif defined(__GNUC__)
+/* Redirects printf to TFM_DRIVER_STDIO in case of GNUARM */
+int _write(int fd, char *str, int len)
+{
+    int i;
+    (void)fd;   /* Not used, avoid warning */
+
+    for (i = 0; i < len; i++) {
+        /* Send byte to USART */
+        uart_putc((unsigned char)str[i]);
+    }
 
-#ifndef RTT_USER_INTERFACE_H_
-#define RTT_USER_INTERFACE_H_
+    /* Return the number of characters written */
+    return len;
+}
+#endif
 
-#define MAX_NO_TEST_MSG                     (10)
+void stdio_init(void)
+{
+    int32_t ret = ARM_DRIVER_OK;
 
-/* Switch Commands */
-#define VIEW_SECURITY_SETTING                       '1'
-#define SECURE_FLASH_OPERATION                      '2'
-#define SECURE_SRAM_OPERATION                       '3'
-#define NON_SECURE_FLASH_OPERATION                  '4'
-#define SECURE_FLASH_READ			                'a'
-#define SECURE_FLASH_WRITE			                'b'
-#define SET_UP_FAW			                  		'c'
-#define RESET_FAW									'd'
-#define SECURE_SRAM_READ							'g'
-#define SECURE_SRAM_WRITE							'h'
-#define NON_SECURE_FLASH_READ						'm'
-#define NON_SECURE_FLASH_WRITE						'n'
-#define EXIT                                        '~'
-#define BUFF_SIZE                       0x0d
-#define BUFF_INDEX                      0x00
+    ret = Driver_USART.Initialize(NULL);
+    ASSERT_HIGH(ret);
+}
 
-extern void start_RTT_user_interface();
+void stdio_uninit(void)
+{
+    int32_t ret = ARM_DRIVER_OK;
 
-#endif /* RTT_USER_INTERFACE_H_ */
+    ret = Driver_USART.Uninitialize();
+    ASSERT_HIGH(ret);
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.h
new file mode 100644
index 0000000000..59f8765e48
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/common/uart_stdout.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __UART_STDOUT_H__
+#define __UART_STDOUT_H__
+
+#include 
+
+
+
+/**
+ * \brief UART channels that
+ *        can be used from TFM
+ */
+enum uart_channel {
+    UART0_CHANNEL = 0,
+    UART1_CHANNEL,
+    UART_INVALID
+};
+
+/**
+ * \brief Initializes the STDIO.
+ *
+ */
+void stdio_init(void);
+
+/**
+ * \brief Uninitializes the STDIO.
+ */
+void stdio_uninit(void);
+
+#endif /* __UART_STDOUT_H__ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Common.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Common.h
new file mode 100644
index 0000000000..cdf44b3325
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Common.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Jan 2014
+ * $Revision:    V2.00
+ *
+ * Project:      Common Driver definitions
+ */
+
+/* History:
+ *  Version 2.00
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include 
+#include 
+#include 
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Flash.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Flash.h
new file mode 100644
index 0000000000..24c1c6e61f
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_Flash.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_FLASH_STATUS made volatile
+ *  Version 2.0
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_FLASH_H_
+#define DRIVER_FLASH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+#include "hal_data.h"
+#include 
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef volatile struct _ARM_FLASH_STATUS {
+  uint32_t busy     : 1;                ///< Flash busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Configure(void)
+  \brief       Configure Flash parameters.
+  \return      \ref execution_status
+*/
+/**
+
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+  uint32_t reserved     : 28;           ///< Reserved (must be zero)
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_FLASH_H_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_USART.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_USART.h
new file mode 100644
index 0000000000..d0b95f3cc5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_USART.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ *  Version 2.2
+ *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
+ *  Version 2.1
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include 
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   18
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   19
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+#define TFM_DRIVER_STDIO    Driver_USART
+
+/**
+\brief USART Status
+*/
+typedef volatile struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+  uint32_t reserved         : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef volatile struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive
+  uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+  uint32_t reserved           : 11;     ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_crypto.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_crypto.h
new file mode 100644
index 0000000000..ab1de83767
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/driver/Driver_crypto.h
@@ -0,0 +1,232 @@
+/***********************************************************************************************************************
+ * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
+ *
+ * This file is part of Renesas Flexible Software Package (FSP)
+ *
+ * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
+ * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
+ *
+ * This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
+ * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
+ * or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
+ * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
+ * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
+ * CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
+ * CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
+ * included in this file may be subject to different terms.
+ **********************************************************************************************************************/
+
+/**********************************************************************************************************************
+ * File Name    : r_crypto_api.h
+ * Description  : Crypto_Interface
+ ***********************************************************************************************************************
+ * History : DD.MM.YYYY Version Description
+ *           Crypto_Interface  1.00    Initial Release.
+ **********************************************************************************************************************/
+
+/*******************************************************************************************************************//**
+ * @ingroup Interface_Library
+ * @defgroup Crypto_API Crypto Interface
+ *
+ * @brief Cryptographic algorithm APIs for encryption/decryption, signing/verification, and hashing.
+ *
+ * @{
+ **********************************************************************************************************************/
+
+#ifndef DRV_CRYPTO_API_H
+#define DRV_CRYPTO_API_H
+
+/***********************************************************************************************************************
+ * Includes
+ **********************************************************************************************************************/
+/** Register definitions, common services and error codes. */
+
+/**********************************************************************************************************************
+ * Macro definitions
+ **********************************************************************************************************************/
+#define CRYPTO_API_VERSION_MAJOR (01)
+#define CRYPTO_API_VERSION_MINOR (00)
+
+/**********************************************************************************************************************
+ * Typedef definitions
+ **********************************************************************************************************************/
+/** Crypto_Interface Add API definitions required by user here. */
+typedef struct st_crypto_ctrl
+{
+    uint32_t  state; //!< indicates state of the SCE/SCE-Lite driver e.g whether it is initialized
+    uint32_t  cb_data;
+    void (*p_sce_long_plg_start_callback)(void);
+    void (*p_sce_long_plg_end_callback)(void);
+} crypto_ctrl_t;
+
+/**********************************************************************************************************************
+ * Enumerations
+ **********************************************************************************************************************/
+
+/** Enumerator for Crypto API uint32_t[] array word endian selection */
+typedef enum e_crypto_word_endian
+{
+    CRYPTO_WORD_ENDIAN_BIG = 0,
+    CRYPTO_WORD_ENDIAN_LITTLE = 1
+} crypto_word_endian_t;
+
+/** MIN and MAX values under enums are for internal use only */
+
+/** Enumerated Crypto Algorithm Type */
+typedef enum e_crypto_algorithm_type
+{
+    CRYPTO_ALGORITHM_TYPE_MIN,
+    CRYPTO_ALGORITHM_TYPE_RSA,
+    CRYPTO_ALGORITHM_TYPE_HASH,
+    CRYPTO_ALGORITHM_TYPE_AES,
+    CRYPTO_ALGORITHM_TYPE_TRNG,
+    CRYPTO_ALGORITHM_TYPE_ECC,
+    /* Add any new entries here */
+    CRYPTO_ALGORITHM_TYPE_MAX
+}crypto_algorithm_type_t;
+
+/** Enumerated HASH Types */
+typedef enum e_crypto_type_hash
+{
+    CRYPTO_TYPE_HASH_MIN,
+    CRYPTO_TYPE_HASH_1,
+    CRYPTO_TYPE_HASH_224,
+    CRYPTO_TYPE_HASH_256,
+    /* Add any new entries here */
+    CRYPTO_TYPE_HASH_MD5,
+    CRYPTO_TYPE_HASH_MAX
+}crypto_hash_type_t;
+
+/** Enumerated Key Types */
+typedef enum e_crypto_key_type
+{
+    CRYPTO_KEY_TYPE_MIN,
+    CRYPTO_KEY_TYPE_AES_PLAIN_TEXT,
+    CRYPTO_KEY_TYPE_AES_WRAPPED,
+    CRYPTO_KEY_TYPE_RSA_PLAIN_TEXT,
+    CRYPTO_KEY_TYPE_RSA_CRT_PLAIN_TEXT,
+    CRYPTO_KEY_TYPE_RSA_WRAPPED,
+    CRYPTO_KEY_TYPE_ECC_PLAIN_TEXT,
+    CRYPTO_KEY_TYPE_ECC_WRAPPED,
+    /* Add any new entries here */
+    CRYPTO_KEY_TYPE_MAX
+}crypto_key_type_t;
+
+/** Enumerated Key Sizes */
+typedef enum e_crypto_key_size
+{
+    CRYPTO_KEY_SIZE_MIN,
+    CRYPTO_KEY_SIZE_AES_128,
+    CRYPTO_KEY_SIZE_AES_256,
+    CRYPTO_KEY_SIZE_AES_192,
+    CRYPTO_KEY_SIZE_RSA_1024,
+    CRYPTO_KEY_SIZE_RSA_2048,
+    CRYPTO_KEY_SIZE_ECC_256,
+    CRYPTO_KEY_SIZE_ECC_192,
+    /* Add any new entries here */
+    CRYPTO_KEY_SIZE_MAX
+}crypto_key_size_t;
+
+/** Enumerated chaining modes */
+typedef enum e_crypto_chaining_mode
+{
+    CRYPTO_CHAINING_MODE_MIN,
+    CRYPTO_ECB_MODE,
+    CRYPTO_CBC_MODE,
+    CRYPTO_CTR_MODE,
+    CRYPTO_GCM_MODE,
+    CRYPTO_XTS_MODE,
+    /* Add any new entries here */
+    CRYPTO_CHAINING_MODE_MAX,
+}crypto_chaining_mode_t;
+
+/**********************************************************************************************************************
+ * Structures
+ **********************************************************************************************************************/
+
+/** A structure to handle data among Crypto HAL modules */
+typedef  struct r_crypto_data_handle
+{
+    uint32_t   * p_data;             ///< Pointer to data
+    uint32_t    data_length;         ///< The length of data pointed by p_data
+} r_crypto_data_handle_t;
+
+/** Crypto engine configuration parameters */
+typedef struct st_crypto_cfg
+{
+    void (*p_sce_long_plg_start_callback)(void);
+
+    /** Callback provided when a ISR occurs.  Set to NULL for no CPU interrupt. */
+    void (*p_sce_long_plg_end_callback)(void);
+
+    /** Endian flag, indicates word endianness for the uint32_t[] array inputs used in Crypto APIs */
+    crypto_word_endian_t endian_flag;
+} crypto_cfg_t;
+
+
+/** Parameters for requesting HAL API interface object */
+typedef struct r_crypto_interface_get_param
+{
+    crypto_algorithm_type_t      algorithm_type;
+    crypto_key_type_t            key_type;
+    crypto_key_size_t            key_size;
+    crypto_chaining_mode_t       chaining_mode;
+    crypto_hash_type_t           hash_type;
+}crypto_interface_get_param_t;
+
+/** Crypto_Interface SCE functions implemented at the HAL layer will follow this API. */
+typedef struct st_crypto_api
+{
+    /** Open crypto module using the given configuration
+     * @param[in,out] p_ctrl pointer to control structure. Must be declared by user. Elements set here.
+     * @param[in]     p_cfg  pointer to configuration structure. All elements of this structure must be set by user
+     */
+    uint32_t (* open)(crypto_ctrl_t * const p_ctrl, crypto_cfg_t const * const p_cfg);
+
+    /** Close the crypto interface module for the given control structure p_ctrl
+     * @param[in] p_ctrl pointer to control structure
+     */
+    uint32_t (* close)(crypto_ctrl_t * const p_ctrl);
+
+    /** Get API interface structure object based on the interface_info provided.
+     * @param[in] interface_info    pointer to structure containing requested interface information.
+     * @param[out] p_interface      pointer whose value points to interface structure object.
+     *
+     * @note p_interface must be of pointer type and its address must be passed in this API.
+     *       Passing the pointer and not its address may result in undefined behavior at run-time.
+     * @note Value of p_interface is allowed to be passed as NULL at the time of API call.
+     */
+    uint32_t (*interfaceGet)(crypto_interface_get_param_t * const interface_info, void * const  p_interface);
+
+    /** Get status of SCE initialization
+     * @param[out] p_status initialization status of SCE module will be written to the memory pointed to by p_status
+     */
+    uint32_t (* statusGet)(uint32_t * p_status);
+
+    /** Gets version and stores it in provided pointer p_version.
+     * @param[out]    p_version  Code and API version used.
+     */
+    uint32_t (* versionGet)(fsp_version_t * const p_version);
+} crypto_api_t;
+
+/** This structure encompasses everything that is needed to use an instance of this interface. */
+typedef struct st_crypto_instance {
+    crypto_ctrl_t   * p_ctrl ;         ///< Pointer to the control structure for this instance
+    crypto_cfg_t    const * p_cfg  ;   ///< Pointer to the configuration structure for this instance
+    crypto_api_t    const * p_api  ;   ///< Pointer to the API structure for this instance
+} crypto_instance_t;
+
+/**********************************************************************************************************************
+ * Exported global variables
+ **********************************************************************************************************************/
+/** @cond INC_HEADER_DEFS_SEC */
+/** Filled in Interface API structure. */
+//extern const crypto_api_t g_sce_crypto_api;
+/** @endcond */
+
+#endif /* DRV_CRYPTO_API_H */
+
+/*******************************************************************************************************************//**
+ * @} (end defgroup Crypto_API)
+ **********************************************************************************************************************/
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_flash.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_flash.c
new file mode 100644
index 0000000000..8d41d13b3a
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_flash.c
@@ -0,0 +1,367 @@
+/***********************************************************************************************************************
+* File Name    : driver_flash.c
+* Description  : This file contains flash driver specific API implementation.
+* ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+#include 
+#include 
+#include 
+#include "hal_data.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg)  ((void)arg)
+#endif
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+
+#define NUM_OF_CF_BLOCKS(x)     ((x) / FLASH0_SECTOR_SIZE)
+
+/* Code Flash */
+#define FLASH0_BASE_S         0x0
+#define FLASH0_SIZE           0x00200000 /* 2 MB */
+#define FLASH0_SECTOR_SIZE    0x00008000 /* 32 kB */
+#define FLASH0_PAGE_SIZE      0x00000080 /* 128 bytes */
+#define FLASH0_PROGRAM_UNIT   0x80       /* Minimum write size */
+
+/* Data Flash */
+#define FLASH1_BASE_S         0x40100000
+#define FLASH1_SIZE           0x10000   /* 64 KB */
+#define FLASH1_SECTOR_SIZE    0x40      /* 64 bytes */
+#define FLASH1_PAGE_SIZE      0x4       /* 4 bytes */
+#define FLASH1_PROGRAM_UNIT   0x4       /* 4 bytes */
+
+
+
+/*
+ * ARM FLASH device structure
+ */
+struct arm_flash_dev_t {
+    const uint32_t memory_base;   /*!< FLASH memory base address */
+    ARM_FLASH_INFO *data;         /*!< FLASH data */
+};
+
+/* Driver Version */
+static ARM_DRIVER_VERSION DriverVersion = {
+    ARM_FLASH_API_VERSION,
+    ARM_FLASH_DRV_VERSION
+};
+
+struct ARM_Flash_FAW_Configure {
+    const uint32_t start_addr;
+    const uint32_t end_addr;
+};
+
+static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev,
+                              uint32_t offset)
+{
+    uint32_t flash_limit = 0;
+    int32_t rc = 0;
+
+    flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size)
+                   - 1;
+
+    if (offset > flash_limit) {
+        rc = -1;
+    }
+    return rc;
+}
+
+static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev,
+                                uint32_t param)
+{
+    int32_t rc = 0;
+
+    if ((param % flash_dev->data->program_unit) != 0) {
+        rc = -1;
+    }
+    return rc;
+}
+
+static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev,
+                                 uint32_t offset)
+{
+    int32_t rc = 0;
+
+    if ((offset % flash_dev->data->sector_size) != 0) {
+        rc = -1;
+    }
+    return rc;
+}
+
+
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+    .sector_info  = NULL,                  /* Uniform sector layout */
+    .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+    .sector_size  = FLASH0_SECTOR_SIZE,
+    .page_size    = FLASH0_PAGE_SIZE,
+    .program_unit = FLASH0_PROGRAM_UNIT,
+    .erased_value = 0xFF};
+
+static ARM_FLASH_INFO ARM_FLASH1_DEV_DATA = {
+     .sector_info  = NULL,                  /* Uniform sector layout */
+     .sector_count = FLASH1_SIZE / FLASH1_SECTOR_SIZE,
+     .sector_size  = FLASH1_SECTOR_SIZE,
+     .page_size    = FLASH1_PAGE_SIZE,
+     .program_unit = FLASH1_PROGRAM_UNIT,
+     .erased_value = 0xFF
+};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+#if (__DOMAIN_NS == 1)
+    .memory_base = FLASH0_BASE_NS,
+#else
+    .memory_base = FLASH0_BASE_S,
+#endif /* __DOMAIN_NS == 1 */
+    .data        = &(ARM_FLASH0_DEV_DATA)};
+
+static struct arm_flash_dev_t ARM_FLASH1_DEV = {
+    .memory_base = FLASH1_BASE_S,
+
+    .data = &(ARM_FLASH1_DEV_DATA)
+};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+struct arm_flash_dev_t *FLASH1_DEV = &ARM_FLASH1_DEV;
+
+
+/*
+ * Functions
+ */
+
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+    fsp_version_t ver;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_FLASH_HP_VersionGet(&ver);
+    if(FSP_SUCCESS != fsp_err)
+    {
+        DriverVersion.api = (uint16_t)((uint16_t)(ver.api_version_major << 8) | (ver.api_version_minor));
+        DriverVersion.drv = (uint16_t)((uint16_t)(ver.code_version_major << 8) | (ver.code_version_minor));
+    }
+    else
+    {
+        memset(&DriverVersion, 0, sizeof(DriverVersion));
+    }
+
+    return DriverVersion;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+    ARG_UNUSED(cb_event);
+    fsp_err_t  fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_FLASH_HP_Open(&g_flash_ctrl, &g_flash_cfg);
+    if(FSP_SUCCESS != fsp_err)
+        return ARM_DRIVER_ERROR;
+    else
+        return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+    fsp_err_t  fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_FLASH_HP_Close(&g_flash_ctrl);
+    if(FSP_SUCCESS != fsp_err)
+        return ARM_DRIVER_ERROR;
+    else
+        return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+    int32_t ret = ARM_DRIVER_OK;
+
+    switch (state) {
+    case ARM_POWER_FULL:
+        /* Nothing to be done */
+        ret = ARM_DRIVER_OK;
+        break;
+
+    case ARM_POWER_OFF:
+    case ARM_POWER_LOW:
+    default:
+        ret = ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    return ret;
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+    int32_t rc = 0;
+
+    if(data == NULL || cnt == 0)
+        return ARM_DRIVER_ERROR_PARAMETER;
+
+    if(addr >= FLASH1_BASE_S)
+    {
+        /* Check flash memory boundaries */
+        rc = is_range_valid(FLASH1_DEV, (addr - FLASH1_DEV->memory_base)  + cnt);
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+    else
+    {
+        /* Check flash memory boundaries */
+        rc = is_range_valid(FLASH0_DEV, addr + cnt);
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+
+    memcpy(data, (void *)addr, cnt);
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data,
+                                     uint32_t cnt)
+{
+    int32_t rc = 0;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+    unsigned int copy_size = 0;
+
+    if(data == NULL || cnt == 0)
+        return ARM_DRIVER_ERROR_PARAMETER;
+
+    uint8_t *buf = (uint8_t*)data;
+
+    if(addr >= FLASH1_BASE_S)
+    {
+         /* Check flash memory boundaries and alignment with minimal write size */
+        rc = is_range_valid(FLASH1_DEV, (addr - FLASH1_DEV->memory_base) + cnt);
+        rc |= is_write_aligned(FLASH1_DEV, addr);
+        rc |= is_write_aligned(FLASH1_DEV, cnt);
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+    else
+    {
+         /* Check flash memory boundaries and alignment with minimal write size */
+        rc = is_range_valid(FLASH0_DEV, addr + cnt);
+        rc |= is_write_aligned(FLASH0_DEV, addr);
+        rc |= is_write_aligned(FLASH0_DEV, cnt);
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+
+    while(cnt > 0)
+    {
+        if(cnt > FLASH0_DEV->data->page_size)
+        {
+            copy_size = FLASH0_DEV->data->page_size;
+        }
+        else
+        {
+            copy_size = cnt;
+        }
+
+        FSP_CRITICAL_SECTION_DEFINE;
+
+        FSP_CRITICAL_SECTION_ENTER;
+
+        fsp_err = R_FLASH_HP_Write(&g_flash_ctrl, (uint32_t)buf, addr, copy_size);
+
+        FSP_CRITICAL_SECTION_EXIT;
+
+        if(FSP_SUCCESS == fsp_err)
+        {
+            if(cnt >= copy_size)
+                cnt -= copy_size;
+            else
+                cnt = 0;
+
+            buf += (copy_size);
+            addr += (copy_size);
+        }
+        else
+        {
+            return ARM_DRIVER_ERROR;
+        }
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+    int32_t rc = 0;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    if(addr >= FLASH1_BASE_S)
+    {
+        rc  = is_range_valid(FLASH1_DEV, (addr - FLASH1_DEV->memory_base));
+        rc |= is_sector_aligned(FLASH1_DEV, (addr - FLASH1_DEV->memory_base));
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+    else
+    {
+        rc  = is_range_valid(FLASH0_DEV, addr);
+        rc |= is_sector_aligned(FLASH0_DEV, addr);
+        if (rc != 0) {
+            return ARM_DRIVER_ERROR_PARAMETER;
+        }
+    }
+
+    FSP_CRITICAL_SECTION_DEFINE;
+
+    FSP_CRITICAL_SECTION_ENTER;
+
+    fsp_err = R_FLASH_HP_Erase(&g_flash_ctrl, addr, 1);
+
+    FSP_CRITICAL_SECTION_EXIT;
+
+    if(FSP_SUCCESS == fsp_err)
+        return ARM_DRIVER_OK;
+    else
+        return ARM_DRIVER_ERROR;
+}
+
+static ARM_FLASH_INFO *ARM_Flash_GetInfo(void)
+{
+    return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+    ARM_Flash_GetVersion,
+    NULL,
+    ARM_Flash_Initialize,
+    ARM_Flash_Uninitialize,
+    ARM_Flash_PowerControl,
+    ARM_Flash_ReadData,
+    ARM_Flash_ProgramData,
+    ARM_Flash_EraseSector,
+    NULL,
+    NULL,
+    ARM_Flash_GetInfo
+};
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_usart.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_usart.c
new file mode 100644
index 0000000000..8f4d0cf59f
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/driver_usart.c
@@ -0,0 +1,195 @@
+/***********************************************************************************************************************
+* File Name    : driver_usart.c
+* Description  : This file contains uart driver specific API implementation.
+* ***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+#include 
+#include 
+#include 
+#include "hal_data.h"
+
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg)  ((void)arg)
+#endif
+
+
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION   ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+volatile uart_event_t g_uart_evt = 0;
+
+/* Driver Version */
+static ARM_DRIVER_VERSION DriverVersion = {
+       ARM_USART_API_VERSION,
+       ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static ARM_USART_CAPABILITIES DriverCapabilities = {
+        1, /* supports UART (Asynchronous) mode */
+        0, /* supports Synchronous Master mode */
+        0, /* supports Synchronous Slave mode */
+        0, /* supports UART Single-wire mode */
+        0, /* supports UART IrDA mode */
+        0, /* supports UART Smart Card mode */
+        0, /* Smart Card Clock generator available */
+        0, /* RTS Flow Control available */
+        0, /* CTS Flow Control available */
+        0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+        0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+        0, /* RTS Line: 0=not available, 1=available */
+        0, /* CTS Line: 0=not available, 1=available */
+        0, /* DTR Line: 0=not available, 1=available */
+        0, /* DSR Line: 0=not available, 1=available */
+        0, /* DCD Line: 0=not available, 1=available */
+        0, /* RI Line: 0=not available, 1=available */
+        0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+        0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+        0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+        0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+        0  /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+    fsp_version_t ver;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_SCI_UART_VersionGet(&ver);
+    if(FSP_SUCCESS != fsp_err)
+    {
+        DriverVersion.api = (uint16_t)((uint16_t)(ver.api_version_major << 8) | (ver.api_version_minor));
+        DriverVersion.drv = (uint16_t)((uint16_t)(ver.code_version_major << 8) | (ver.code_version_minor));
+    }
+    else
+    {
+        memset(&DriverVersion, 0, sizeof(DriverVersion));
+    }
+
+    return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+    return DriverCapabilities;
+}
+
+static int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+    ARG_UNUSED(cb_event);
+    fsp_err_t  fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_SCI_UART_Open(&g_uart_ctrl, &g_uart_cfg);
+    if(FSP_SUCCESS != fsp_err)
+        return ARM_DRIVER_ERROR;
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART_Uninitialize(void)
+{
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    fsp_err = R_SCI_UART_Close(&g_uart_ctrl);
+    if(FSP_SUCCESS != fsp_err)
+        return ARM_DRIVER_ERROR;
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)
+{
+    (void)state; /* Not used, avoid warning */
+    /* Nothing to be done */
+    return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static int32_t ARM_USART_Send(const void *data, uint32_t num)
+{
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    if(num == 0 || data == NULL)
+        return ARM_DRIVER_ERROR;
+
+    g_uart_evt = 0;
+
+    fsp_err = R_SCI_UART_Write(&g_uart_ctrl, data, num);
+    if(FSP_SUCCESS != fsp_err)
+    {
+        return ARM_DRIVER_ERROR;
+    }
+
+    /* Wait for UART Tx to complete */
+    while(!g_uart_evt);
+
+    if((g_uart_evt != UART_EVENT_TX_DATA_EMPTY))
+        return ARM_DRIVER_ERROR;
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART_Receive(void *data, uint32_t num)
+{
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    if(data == NULL)
+        return ARM_DRIVER_ERROR;
+
+    g_uart_evt = 0;
+
+    fsp_err = R_SCI_UART_Read(&g_uart_ctrl, data, num);
+    if(FSP_SUCCESS != fsp_err)
+        return ARM_DRIVER_ERROR;
+
+    /* Wait for UART Rx to complete */
+    while(!g_uart_evt);
+
+    if(g_uart_evt != UART_EVENT_RX_COMPLETE)
+        return ARM_DRIVER_ERROR;
+
+    return ARM_DRIVER_OK;
+}
+
+void user_uart_callback(uart_callback_args_t  *p_args)
+{
+    g_uart_evt = p_args->event;
+}
+
+extern ARM_DRIVER_USART Driver_USART;
+ARM_DRIVER_USART Driver_USART = {
+    ARM_USART_GetVersion,
+    ARM_USART_GetCapabilities,
+    ARM_USART_Initialize,
+    ARM_USART_Uninitialize,
+    ARM_USART_PowerControl,
+    ARM_USART_Send,
+    ARM_USART_Receive,
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/dummy_nv_counters.c b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/dummy_nv_counters.c
new file mode 100644
index 0000000000..1b71d6b4ad
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/dummy_nv_counters.c
@@ -0,0 +1,167 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+
+#include 
+#include 
+#include 
+#include "tfm_plat_nv_counters.h"
+
+#define SECTOR_OFFSET               0
+#define NV_COUNTER_SIZE             sizeof(uint32_t)
+#define INIT_VALUE_SIZE             NV_COUNTER_SIZE
+#define NV_COUNTERS_AREA_OFFSET     (TFM_NV_COUNTERS_AREA_ADDR - \
+                                     TFM_NV_COUNTERS_SECTOR_ADDR)
+
+#define NV_COUNTERS_INITIALIZED     0xC0DE0042
+
+
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+enum tfm_plat_err_t tfm_plat_init_nv_counter(void)
+{
+    int32_t err;
+    uint32_t i;
+    uint32_t nbr_counters = ((TFM_NV_COUNTERS_AREA_SIZE - INIT_VALUE_SIZE)
+                             / NV_COUNTER_SIZE);
+    uint32_t *p_nv_counter;
+    uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE] = {0};
+
+    /* Read the whole sector to be able to erase and write later in the flash */
+    err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+                                  TFM_NV_COUNTERS_SECTOR_SIZE);
+    if (err != ARM_DRIVER_OK) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    /* Set the pointer to nv counters position */
+    p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET);
+
+    if (p_nv_counter[nbr_counters] == NV_COUNTERS_INITIALIZED) {
+        return TFM_PLAT_ERR_SUCCESS;
+    }
+
+    /* Add watermark, at the end of the NV counters area, to indicate that NV
+     * counters have been initialized.
+     */
+    p_nv_counter[nbr_counters] = NV_COUNTERS_INITIALIZED;
+
+    /* Initialize all counters to 0 */
+    for (i = 0; i < nbr_counters; i++) {
+        p_nv_counter[i] = 0;
+    }
+
+    /* Erase sector before write in it */
+    err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+    if (err != ARM_DRIVER_OK) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    /* Write in flash the in-memory block content after modification */
+    err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+                                     TFM_NV_COUNTERS_SECTOR_SIZE);
+    if (err != ARM_DRIVER_OK) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id,
+                                             uint32_t size, uint8_t *val)
+{
+    int32_t  err;
+    uint32_t flash_addr;
+
+    if (size != NV_COUNTER_SIZE) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    flash_addr = TFM_NV_COUNTERS_AREA_ADDR + (counter_id * NV_COUNTER_SIZE);
+
+    err = FLASH_DEV_NAME.ReadData(flash_addr, val, NV_COUNTER_SIZE);
+    if (err != ARM_DRIVER_OK) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id,
+                                            uint32_t value)
+{
+    int32_t  err;
+    uint32_t *p_nv_counter;
+    uint8_t  sector_data[TFM_NV_COUNTERS_SECTOR_SIZE];
+
+    /* Read the whole sector to be able to erase and write later in the flash */
+    err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+                                  TFM_NV_COUNTERS_SECTOR_SIZE);
+    if (err != ARM_DRIVER_OK) {
+        return TFM_PLAT_ERR_SYSTEM_ERR;
+    }
+
+    /* Set the pointer to nv counter position */
+    p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET +
+                                (counter_id * NV_COUNTER_SIZE));
+
+    if (value != *p_nv_counter) {
+
+        if (value > *p_nv_counter) {
+            *p_nv_counter = value;
+        } else {
+            return TFM_PLAT_ERR_INVALID_INPUT;
+        }
+
+        /* Erase sector before write in it */
+        err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+        if (err != ARM_DRIVER_OK) {
+            return TFM_PLAT_ERR_SYSTEM_ERR;
+        }
+
+        /* Write in flash the in-memory block content after modification */
+        err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR,
+                                         sector_data,
+                                         TFM_NV_COUNTERS_SECTOR_SIZE);
+        if (err != ARM_DRIVER_OK) {
+            return TFM_PLAT_ERR_SYSTEM_ERR;
+        }
+    }
+
+    return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_increment_nv_counter(
+                                           enum tfm_nv_counter_t counter_id)
+{
+    uint32_t security_cnt;
+    enum tfm_plat_err_t err;
+
+    err = tfm_plat_read_nv_counter(counter_id,
+                                   sizeof(security_cnt),
+                                   (uint8_t *)&security_cnt);
+    if (err != TFM_PLAT_ERR_SUCCESS) {
+        return err;
+    }
+
+    if (security_cnt == UINT32_MAX) {
+        return TFM_PLAT_ERR_MAX_VALUE;
+    }
+
+    return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u);
+}
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/flash_layout.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/flash_layout.h
new file mode 100644
index 0000000000..a89a5c1ed5
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/flash_layout.h
@@ -0,0 +1,136 @@
+/***********************************************************************************************************************
+* File Name    : flash_layout.h
+* Description  : Memory partition related macro definition file
+***********************************************************************************************************************/
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+* this software. By using this software, you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/*
+ *   Flash layout on Renesas RA6M3 devices in case of MCUBOOT_OVERWRITE_ONLY use case:
+ *
+ *   Section                            Offset              Size
+ *
+ *   BL2                                0x0000_0000          64KB
+ *   Primary Image Area                 0x0001_0000         960KB
+ *   Secondary Image Area               0x0010_0000         960KB
+ *   Scratch Area                       0x001F_0000          32KB
+ */
+
+#define MAX(X,Y)                       ((X) > (Y) ? (X) : (Y))
+
+/* Size of a Secure and of a Non-secure image */
+#define FLASH_S_PARTITION_SIZE              (0)
+#define FLASH_NS_PARTITION_SIZE             (0xF0000) /* 30 * 32KB block = 960KB */
+#define FLASH_MAX_PARTITION_SIZE            ((FLASH_S_PARTITION_SIZE >   \
+                                             FLASH_NS_PARTITION_SIZE) ? \
+                                             FLASH_S_PARTITION_SIZE :    \
+                                             FLASH_NS_PARTITION_SIZE)
+
+#define FLASH_TOTAL_SIZE                    (0x00200000)    /*  2MB  */
+
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE        (0x8000)    /* 32 KB */
+
+/* Sector size of the flash hardware */
+#define FLASH_BOOT_SECTOR_SIZE              (0x2000)    /* 8 KB */
+
+/* Flash layout info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS                  (0)
+
+/* Offset and size definitions of the flash partitions that are handled by the
+ * bootloader. The image swapping is done between IMAGE_PRIMARY and
+ * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image
+ * swapping.
+ */
+#define FLASH_AREA_BL2_OFFSET               (0x0)
+#define FLASH_AREA_BL2_SIZE                 (8 * FLASH_BOOT_SECTOR_SIZE)
+
+#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
+#define FLASH_AREA_0_ID                     (1)
+#define FLASH_AREA_0_OFFSET                 (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_0_SIZE                   (FLASH_NS_PARTITION_SIZE)
+
+#define FLASH_AREA_2_ID                     (FLASH_AREA_0_ID + 1)
+#define FLASH_AREA_2_OFFSET                 (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
+#define FLASH_AREA_2_SIZE                   (FLASH_NS_PARTITION_SIZE)
+
+/* Scratch area */
+#define FLASH_AREA_SCRATCH_ID               (FLASH_AREA_2_ID + 1)
+#define FLASH_AREA_SCRATCH_OFFSET           (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
+
+#ifndef MCUBOOT_OVERWRITE_ONLY
+#define FLASH_AREA_SCRATCH_SIZE             (FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+/* The maximum number of status entries supported by the bootloader. */
+/* The maximum number of status entries must be at least 2. For more
+ * information see the MCUBoot issue:
+ * https://github.com/JuulLabs-OSS/mcuboot/issues/427.
+ */
+#define BOOT_STATUS_MAX_ENTRIES             ((FLASH_S_PARTITION_SIZE + \
+                                             FLASH_NS_PARTITION_SIZE) / \
+                                             FLASH_AREA_SCRATCH_SIZE)
+
+#else
+#define FLASH_AREA_SCRATCH_SIZE             (0)
+
+/* The maximum number of status entries supported by the bootloader. */
+/* The maximum number of status entries must be at least 2. For more
+ * information see the MCUBoot issue:
+ * https://github.com/JuulLabs-OSS/mcuboot/issues/427.
+ */
+#define MCUBOOT_STATUS_MAX_ENTRIES             (0)
+
+#endif
+
+
+/* Maximum number of image sectors supported by the bootloader. */
+#define MCUBOOT_MAX_IMG_SECTORS       (( FLASH_S_PARTITION_SIZE +  \
+                                      FLASH_NS_PARTITION_SIZE) / \
+                                      FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+
+#elif (MCUBOOT_IMAGE_NUMBER == 2)
+
+#else
+#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
+#endif
+
+/*  NV Counters definitions */
+#define FLASH_NV_COUNTERS_AREA_OFFSET       (0x40100000)
+#define FLASH_NV_COUNTERS_AREA_SIZE         (0x40)   /* 64 bytes */
+
+/* Flash device name used by BL2
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME               Driver_FLASH0
+
+/* NV Counters definitions */
+#define TFM_NV_COUNTERS_AREA_ADDR    FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_AREA_SIZE    (0x40) /* 64 bytes */
+#define TFM_NV_COUNTERS_SECTOR_ADDR  FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_SECTOR_SIZE  FLASH_NV_COUNTERS_AREA_SIZE
+
+#define TOTAL_ROM_SIZE               FLASH_TOTAL_SIZE
+#define TOTAL_RAM_SIZE               (0xA0000)      /* 640 KB */
+
+
+#endif /* __FLASH_LAYOUT_H__ */
+
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/region_defs.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/region_defs.h
new file mode 100644
index 0000000000..3dd85016ce
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/ext/target/ek-ra6m3/region_defs.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
+                                           + FLASH_S_PARTITION_SIZE)
+#else
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \
+                                           + FLASH_S_PARTITION_SIZE)
+#endif /* !LINK_TO_SECONDARY_PARTITION */
+
+
+
+
+#define BL2_HEAP_SIZE           (0x0001000)
+#define BL2_MSP_STACK_SIZE      (0x0001800)
+
+
+/* This size of buffer is big enough to store an attestation
+ * token produced by initial attestation service
+ */
+#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE   (0x250)
+
+#ifdef __ARM_ARCH_8M_MAIN__
+/* MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+#ifdef BL2
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_0_OFFSET)
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_2_OFFSET)
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
+#endif /* !LINK_TO_SECONDARY_PARTITION */
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
+#endif /* BL2 */
+
+#endif
+
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
+                                           + FLASH_S_PARTITION_SIZE)
+#else
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \
+                                           + FLASH_S_PARTITION_SIZE)
+#endif /* !LINK_TO_SECONDARY_PARTITION */
+
+/* Boot partition structure if MCUBoot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0400 Image area
+ * 0x7_0000 Trailer
+ */
+/* IMAGE_CODE_SIZE is the space available for the software binary image.
+ * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE
+ * because we reserve space for the image header and trailer introduced
+ * by the bootloader.
+ */
+#ifdef BL2
+#define BL2_HEADER_SIZE      (0x400)       /* 1 KB */
+#define BL2_TRAILER_SIZE     (0x10000)     /* 64 KB */
+#else
+/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */
+#define BL2_HEADER_SIZE      (0x0)
+#define BL2_TRAILER_SIZE     (0x10400)
+#endif /* BL2 */
+
+#ifdef __ARM_ARCH_8M_MAIN__
+#define IMAGE_S_CODE_SIZE \
+            (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+#endif
+
+#define IMAGE_NS_CODE_SIZE \
+            (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+#define CMSE_VENEER_REGION_SIZE     (0x300)
+
+/* Alias definitions for secure and non-secure areas*/
+#ifdef __ARM_ARCH_8M_MAIN__
+#define S_ROM_ALIAS(x)  (S_ROM_ALIAS_BASE + (x))
+#endif
+
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
+
+#ifdef __ARM_ARCH_8M_MAIN__
+#define S_RAM_ALIAS(x)  (S_RAM_ALIAS_BASE + (x))
+#endif
+
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
+
+#ifdef __ARM_ARCH_8M_MAIN__
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+             (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define S_CODE_START    (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE     (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START    (S_RAM_ALIAS(0x0))
+#define S_DATA_SIZE     (TOTAL_RAM_SIZE / 2)
+#define S_DATA_LIMIT    (S_DATA_START + S_DATA_SIZE - 1)
+
+/* CMSE Veneers region */
+#define CMSE_VENEER_REGION_START  (S_CODE_LIMIT + 1)
+#endif
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+                        (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define NS_CODE_START   (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE    (IMAGE_NS_CODE_SIZE)
+#define NS_CODE_LIMIT   (NS_CODE_START + NS_CODE_SIZE - 1)
+
+#define NS_DATA_START   (NS_RAM_ALIAS(TOTAL_RAM_SIZE / 2))
+#define NS_DATA_SIZE    (TOTAL_RAM_SIZE / 2)
+#define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE - 1)
+
+/* NS partition information is used for MPC and SAU configuration */
+#define NS_PARTITION_START \
+            (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
+
+/* Secondary partition for new images in case of firmware upgrade */
+#define SECONDARY_PARTITION_START \
+            (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
+#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
+                                  FLASH_NS_PARTITION_SIZE)
+
+#ifdef BL2
+/* Bootloader regions */
+#define BL2_CODE_START    (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
+#define BL2_CODE_SIZE     (FLASH_AREA_BL2_SIZE)
+#define BL2_CODE_LIMIT    (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START    (S_RAM_ALIAS(0x0))
+#define BL2_DATA_SIZE     (TOTAL_RAM_SIZE)
+#define BL2_DATA_LIMIT    (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
+#ifdef __ARM_ARCH_8M_MAIN__
+/* Shared data area between bootloader and runtime firmware.
+ * Shared data area is allocated at the beginning of the RAM, it is overlapping
+ * with TF-M Secure code's MSP stack
+ */
+#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
+#define BOOT_TFM_SHARED_DATA_SIZE (0x400)
+#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
+                                    BOOT_TFM_SHARED_DATA_SIZE - 1)
+#endif
+
+#endif /* __REGION_DEFS_H__ */
diff --git a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/menu_callbacks.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_defs.h
similarity index 62%
rename from application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/menu_callbacks.h
rename to application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_defs.h
index 2b8a5b38eb..b611173968 100644
--- a/application_projects/secure_data_at_rest/embedded/secure_data_at_rest_ek_ra6m3/e2studio/src/menu_callbacks.h
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_defs.h
@@ -1,7 +1,3 @@
-/***********************************************************************************************************************
- * File Name    : menu_callbacks.h
- * Description  : Contains macros, function definitions used for user command processing
- ***********************************************************************************************************************/
 /***********************************************************************************************************************
  * DISCLAIMER
  * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
@@ -18,26 +14,25 @@
  * following link:
  * http://www.renesas.com/disclaimer
  *
- * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
  ***********************************************************************************************************************/
 
-#ifndef MENU_CALLBACKS_H_
-#define MENU_CALLBACKS_H_
+#ifndef __TFM_PLAT_DEFS_H__
+#define __TFM_PLAT_DEFS_H__
 
-void read_secure_settings(void);
-void test_secure_code(void);
-void test_non_secure_code(void);
+#include 
+#include 
 
+enum tfm_plat_err_t {
+    TFM_PLAT_ERR_SUCCESS = 0,
+    TFM_PLAT_ERR_SYSTEM_ERR,
+    TFM_PLAT_ERR_MAX_VALUE,
+    TFM_PLAT_ERR_INVALID_INPUT,
+    TFM_PLAT_ERR_UNSUPPORTED,
+    /* Following entry is only to ensure the error code of int size */
+    TFM_PLAT_ERR_FORCE_INT_SIZE = INT_MAX
+};
 
-void secure_sram_code_read(void);
-void secure_code_read(void);
-void non_secure_code_read(void);
 
-void secure_sram_code_write(void);
-void secure_code_write(void);
-void non_secure_code_write(void);
+#endif /* __TFM_PLAT_DEFS_H__ */
 
-void non_secure_code_leak_test(void);
-void setup_faw(void);
-void reset_faw(void);
-#endif /* MENU_CALLBACKS_H_ */
diff --git a/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_nv_counters.h b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_nv_counters.h
new file mode 100644
index 0000000000..de772ee203
--- /dev/null
+++ b/application_projects/secure_boot_solution/SecureBoot_Package/src/SecureBoot/Secureboot_EK_RA6M3/src/platform/include/tfm_plat_nv_counters.h
@@ -0,0 +1,102 @@
+/***********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
+ * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+ ***********************************************************************************************************************/
+
+#ifndef __TFM_PLAT_NV_COUNTERS_H__
+#define __TFM_PLAT_NV_COUNTERS_H__
+
+#include 
+#include "tfm_plat_defs.h"
+
+enum tfm_nv_counter_t {
+    PLAT_NV_COUNTER_0 = 0,  /* Used by SST service */
+    PLAT_NV_COUNTER_1,      /* Used by SST service */
+    PLAT_NV_COUNTER_2,      /* Used by SST service */
+    PLAT_NV_COUNTER_3,      /* Used by bootloader */
+    PLAT_NV_COUNTER_MAX
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Initialises all non-volatile (NV) counters.
+ *
+ * \return  TFM_PLAT_ERR_SUCCESS if the initialization succeeds, otherwise
+ *          TFM_PLAT_ERR_SYSTEM_ERR
+ */
+enum tfm_plat_err_t tfm_plat_init_nv_counter(void);
+
+/**
+ * \brief Reads the given non-volatile (NV) counter.
+ *
+ * \param[in]  counter_id  NV counter ID.
+ * \param[in]  size        Size of the buffer to store NV counter value
+ *                         in bytes.
+ * \param[out] val         Pointer to store the current NV counter value.
+ *
+ * \return  TFM_PLAT_ERR_SUCCESS if the value is read correctly. Otherwise,
+ *          it returns TFM_PLAT_ERR_SYSTEM_ERR.
+ */
+enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id,
+                                             uint32_t size, uint8_t *val);
+
+/**
+ * \brief Increments the given non-volatile (NV) counter.
+ *
+ * \param[in] counter_id  NV counter ID.
+ *
+ * \return  When the NV counter reaches its maximum value, the
+ *          TFM_PLAT_ERR_MAX_VALUE error is returned to indicate the value
+ *          cannot be incremented. Otherwise, it returns TFM_PLAT_ERR_SUCCESS.
+ */
+enum tfm_plat_err_t tfm_plat_increment_nv_counter(
+                                              enum tfm_nv_counter_t counter_id);
+
+/**
+ * \brief Sets the given non-volatile (NV) counter to the specified value.
+ *
+ * \param[in] counter_id  NV counter ID.
+ * \param[in] value       New value of the NV counter. The maximum value that
+ *                        can be set depends on the constraints of the
+ *                        underlying implementation, but it always must be
+ *                        greater than or equal to the current NV counter value.
+ *
+ * \retval TFM_PLAT_ERR_SUCCESS         The NV counter is set successfully
+ * \retval TFM_PLAT_ERR_INVALID_INPUT   The new value is less than the current
+ *                                      counter value
+ * \retval TFM_PLAT_ERR_MAX_VALUE       The new value is greater than the
+ *                                      maximum value of the NV counter
+ * \retval TFM_PLAT_ERR_UNSUPPORTED     The function is not implemented for
+ *                                      the given platform or the new value is
+ *                                      not representable on the underlying
+ *                                      counter implementation
+ * \retval TFM_PLAT_ERR_SYSTEM_ERR      An unspecified error occurred
+ *                                      (none of the other standard error codes
+ *                                      are applicable)
+ */
+enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id,
+                                            uint32_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TFM_PLAT_NV_COUNTERS_H__ */
+
diff --git a/application_projects/secure_boot_solution/r01an5347eu0110-ra-arm-secure-boot-solution-ra6m3.pdf b/application_projects/secure_boot_solution/r01an5347eu0110-ra-arm-secure-boot-solution-ra6m3.pdf
new file mode 100644
index 0000000000..099bcc5154
Binary files /dev/null and b/application_projects/secure_boot_solution/r01an5347eu0110-ra-arm-secure-boot-solution-ra6m3.pdf differ
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.cproject b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.cproject
new file mode 100644
index 0000000000..d9824ebb59
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.cproject
@@ -0,0 +1,300 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+						
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+	
+
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.project b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.project
new file mode 100644
index 0000000000..3b5710eb4c
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.project
@@ -0,0 +1,38 @@
+
+
+	reset_ek_ra6m3
+	
+	
+	
+	
+		
+			org.eclipse.xtext.ui.shared.xtextBuilder
+			
+			
+		
+		
+			com.renesas.cdt.ra.contentgen.raBuilder
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+		com.renesas.cdt.ra.contentgen.raNature
+		org.eclipse.xtext.ui.shared.xtextNature
+	
+
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/CoverageSetting.xml b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/CoverageSetting.xml
new file mode 100644
index 0000000000..9554acb752
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/CoverageSetting.xml
@@ -0,0 +1,7 @@
+
+
+    1.0
+    
+        
+    
+
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/DebugVirtualConsoleSetting.xml b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/DebugVirtualConsoleSetting.xml
new file mode 100644
index 0000000000..098c55d872
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/DebugVirtualConsoleSetting.xml
@@ -0,0 +1,12 @@
+
+
+
+        true
+        
+        false
+        
+        0
+        true
+        false
+    
+
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
new file mode 100644
index 0000000000..450a47cf61
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=9.2.1.20191025
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.content.prefs b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.content.prefs
new file mode 100644
index 0000000000..f77288b8f3
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.content.prefs
@@ -0,0 +1,2 @@
+com.renesas.cdt.ra.content.defaultlinkerscript=script/ra6m3.ld
+eclipse.preferences.version=1
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
new file mode 100644
index 0000000000..71da5399d9
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.packs.componentfiles.prefs
@@ -0,0 +1,16 @@
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/all=3831616655,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2506583203,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|4214990036,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|12129667,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2083176475,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1395162982,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|4111916304,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|4163895945,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|490858859,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3679261956,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|2262931981,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|373608954,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|984407218,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|498646134,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2220305532,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2182658037,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2924246150,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1383382254,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3528041316,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3047267965,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|979987894,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h
+Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.6.0/libraries=
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.1.0/all=3753099063,ra/board/ra6m3_ek/board_leds.c|3219229514,ra/board/ra6m3_ek/board_ethernet_phy.h|2171210938,ra/board/ra6m3_ek/board_init.h|270190773,ra/board/ra6m3_ek/board_init.c|667942982,ra/board/ra6m3_ek/board.h|547978938,ra/board/ra6m3_ek/board_leds.h
+Renesas\#\#BSP\#\#Board\#\#ra6m3_ek\#\#\#\#1.1.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.1.0/all=3326152699,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#1.1.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFC\#\#1.1.0/libraries=
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.1.0/all=1047097663,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2017027947,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h|412750923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h
+Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#1.1.0/libraries=
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.1.0/all=1455555581,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1417282846,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2687014826,ra/fsp/src/bsp/mcu/all/bsp_common.c|3081550272,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|4110700937,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|4239686018,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1747067909,ra/fsp/inc/fsp_common_api.h|2298882886,ra/fsp/inc/instances/r_ioport.h|2503058501,ra/fsp/src/bsp/mcu/all/bsp_delay.c|1219976787,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1954369379,ra/fsp/inc/fsp_features.h|3326152699,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3744453931,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|839014393,ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd|3706642864,ra/fsp/src/bsp/mcu/all/bsp_common.h|724348230,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|15519568,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1248105138,ra/fsp/inc/api/bsp_api.h|3312859967,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2856633492,ra/fsp/inc/api/r_ioport_api.h|3332349192,ra/fsp/src/bsp/mcu/all/bsp_io.c|1465263727,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3331707473,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1686790147,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1610165669,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1705712330,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2826325088,ra/fsp/src/bsp/mcu/all/bsp_io.h|1067477278,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2857175933,ra/fsp/inc/fsp_version.h|3017820483,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
+Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#1.1.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#1.1.0/all=1089305404,ra/fsp/inc/instances/r_flash_hp.h|3393114147,ra/fsp/src/r_flash_hp/r_flash_hp.c|4021293974,ra/fsp/inc/api/r_flash_api.h|3984233619,ra/fsp/inc/api/r_cgc_api.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#1.1.0/libraries=
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.1.0/all=2856633492,ra/fsp/inc/api/r_ioport_api.h|1161308720,ra/fsp/src/r_ioport/r_ioport.c|2298882886,ra/fsp/inc/instances/r_ioport.h
+Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#1.1.0/libraries=
+eclipse.preferences.version=1
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.settingseditor.prefs b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.settingseditor.prefs
similarity index 100%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/.settings/com.renesas.cdt.ra.settingseditor.prefs
rename to application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/com.renesas.cdt.ra.settingseditor.prefs
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/language.settings.xml b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/language.settings.xml
new file mode 100644
index 0000000000..cbf9e267ed
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
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+			
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+	
+		
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+			
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diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/org.eclipse.cdt.core.prefs b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000..253f23cad3
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,172 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.core.formatter.align_composite_type_declarators=false
+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
+org.eclipse.cdt.core.formatter.alignment_for_assignment=16
+org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=82
+org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16
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+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=82
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+org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
+org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
+org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
+org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=82
+org.eclipse.cdt.core.formatter.alignment_for_member_access=0
+org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16
+org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16
+org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16
+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
+org.eclipse.cdt.core.formatter.comment.line_up_line_comment_in_blocks_on_first_column=false
+org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1
+org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true
+org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=true
+org.eclipse.cdt.core.formatter.compact_else_if=true
+org.eclipse.cdt.core.formatter.continuation_indentation=2
+org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2
+org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false
+org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=false
+org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false
+org.eclipse.cdt.core.formatter.indent_empty_lines=false
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+org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true
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+org.eclipse.cdt.core.formatter.insert_space_before_comma_in_expression_list=do not insert
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diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/R7FA6M3AH3CFC.pincfg b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/R7FA6M3AH3CFC.pincfg
new file mode 100644
index 0000000000..5d97f4831e
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/R7FA6M3AH3CFC.pincfg
@@ -0,0 +1,36 @@
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\ No newline at end of file
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/RA6M3-EK.pincfg b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/RA6M3-EK.pincfg
new file mode 100644
index 0000000000..ffdfccea71
--- /dev/null
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/RA6M3-EK.pincfg
@@ -0,0 +1,855 @@
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\ No newline at end of file
diff --git a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/configuration.xml b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/configuration.xml
similarity index 93%
rename from application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/configuration.xml
rename to application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/configuration.xml
index 9b9d0121da..6a96d11461 100644
--- a/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/e2studio/configuration.xml
+++ b/application_projects/secure_data_at_rest/embedded/reset_ek_ra6m3/configuration.xml
@@ -8,8 +8,7 @@